target/riscv/pmp.c

   1 /*
   2  * QEMU RISC-V PMP (Physical Memory Protection)
   3  *
   4  * Author: Daire McNamara, daire.mcnamara@emdalo.com
   5  *         Ivan Griffin, ivan.griffin@emdalo.com
   6  *
   7  * This provides a RISC-V Physical Memory Protection implementation
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2 or later, as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 /*
  23  * PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu/log.h"
  28 #include "qapi/error.h"
  29 #include "cpu.h"
  30 #include "trace.h"
  31
  32 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
  33     uint8_t val);
  34 static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
  35 static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
  36
  37 /*
  38  * Accessor method to extract address matching type 'a field' from cfg reg
  39  */
  40 static inline uint8_t pmp_get_a_field(uint8_t cfg)
  41 {
  42     uint8_t a = cfg >> 3;
  43     return a & 0x3;
  44 }
  45
  46 /*
  47  * Check whether a PMP is locked or not.
  48  */
  49 static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
  50 {
  51
  52     if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
  53         return 1;
  54     }
  55
  56     /* Top PMP has no 'next' to check */
  57     if ((pmp_index + 1u) >= MAX_RISCV_PMPS) {
  58         return 0;
  59     }
  60
  61     /* In TOR mode, need to check the lock bit of the next pmp
  62      * (if there is a next)
  63      */
  64     const uint8_t a_field =
  65         pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
  66     if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
  67          (PMP_AMATCH_TOR == a_field)) {
  68         return 1;
  69     }
  70
  71     return 0;
  72 }
  73
  74 /*
  75  * Count the number of active rules.
  76  */
  77 static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
  78 {
  79      return env->pmp_state.num_rules;
  80 }
  81
  82 /*
  83  * Accessor to get the cfg reg for a specific PMP/HART
  84  */
  85 static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
  86 {
  87     if (pmp_index < MAX_RISCV_PMPS) {
  88         return env->pmp_state.pmp[pmp_index].cfg_reg;
  89     }
  90
  91     return 0;
  92 }
  93
  94
  95 /*
  96  * Accessor to set the cfg reg for a specific PMP/HART
  97  * Bounds checks and relevant lock bit.
  98  */
  99 static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
 100 {
 101     if (pmp_index < MAX_RISCV_PMPS) {
 102         if (!pmp_is_locked(env, pmp_index)) {
 103             env->pmp_state.pmp[pmp_index].cfg_reg = val;
 104             pmp_update_rule(env, pmp_index);
 105         } else {
 106             qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
 107         }
 108     } else {
 109         qemu_log_mask(LOG_GUEST_ERROR,
 110                       "ignoring pmpcfg write - out of bounds\n");
 111     }
 112 }
 113
 114 static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
 115 {
 116     /*
 117        aaaa...aaa0   8-byte NAPOT range
 118        aaaa...aa01   16-byte NAPOT range
 119        aaaa...a011   32-byte NAPOT range
 120        ...
 121        aa01...1111   2^XLEN-byte NAPOT range
 122        a011...1111   2^(XLEN+1)-byte NAPOT range
 123        0111...1111   2^(XLEN+2)-byte NAPOT range
 124        1111...1111   Reserved
 125     */
 126     if (a == -1) {
 127         *sa = 0u;
 128         *ea = -1;
 129         return;
 130     } else {
 131         target_ulong t1 = ctz64(~a);
 132         target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2;
 133         target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1;
 134         *sa = base;
 135         *ea = base + range;
 136     }
 137 }
 138
 139 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
 140 {
 141     uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
 142     target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
 143     target_ulong prev_addr = 0u;
 144     target_ulong sa = 0u;
 145     target_ulong ea = 0u;
 146
 147     if (pmp_index >= 1u) {
 148         prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg;
 149     }
 150
 151     switch (pmp_get_a_field(this_cfg)) {
 152     case PMP_AMATCH_OFF:
 153         sa = 0u;
 154         ea = -1;
 155         break;
 156
 157     case PMP_AMATCH_TOR:
 158         sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
 159         ea = (this_addr << 2) - 1u;
 160         break;
 161
 162     case PMP_AMATCH_NA4:
 163         sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
 164         ea = (sa + 4u) - 1u;
 165         break;
 166
 167     case PMP_AMATCH_NAPOT:
 168         pmp_decode_napot(this_addr, &sa, &ea);
 169         break;
 170
 171     default:
 172         sa = 0u;
 173         ea = 0u;
 174         break;
 175     }
 176
 177     env->pmp_state.addr[pmp_index].sa = sa;
 178     env->pmp_state.addr[pmp_index].ea = ea;
 179 }
 180
 181 void pmp_update_rule_nums(CPURISCVState *env)
 182 {
 183     int i;
 184
 185     env->pmp_state.num_rules = 0;
 186     for (i = 0; i < MAX_RISCV_PMPS; i++) {
 187         const uint8_t a_field =
 188             pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
 189         if (PMP_AMATCH_OFF != a_field) {
 190             env->pmp_state.num_rules++;
 191         }
 192     }
 193 }
 194
 195 /* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
 196  *   end address values.
 197  *   This function is called relatively infrequently whereas the check that
 198  *   an address is within a pmp rule is called often, so optimise that one
 199  */
 200 static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
 201 {
 202     pmp_update_rule_addr(env, pmp_index);
 203     pmp_update_rule_nums(env);
 204 }
 205
 206 static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
 207 {
 208     int result = 0;
 209
 210     if ((addr >= env->pmp_state.addr[pmp_index].sa)
 211         && (addr <= env->pmp_state.addr[pmp_index].ea)) {
 212         result = 1;
 213     } else {
 214         result = 0;
 215     }
 216
 217     return result;
 218 }
 219
 220
 221 /*
 222  * Public Interface
 223  */
 224
 225 /*
 226  * Check if the address has required RWX privs to complete desired operation
 227  */
 228 bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
 229     target_ulong size, pmp_priv_t privs, target_ulong mode)
 230 {
 231     int i = 0;
 232     int ret = -1;
 233     int pmp_size = 0;
 234     target_ulong s = 0;
 235     target_ulong e = 0;
 236     pmp_priv_t allowed_privs = 0;
 237
 238     /* Short cut if no rules */
 239     if (0 == pmp_get_num_rules(env)) {
 240         return true;
 241     }
 242
 243     if (size == 0) {
 244         if (riscv_feature(env, RISCV_FEATURE_MMU)) {
 245             /*
 246              * If size is unknown (0), assume that all bytes
 247              * from addr to the end of the page will be accessed.
 248              */
 249             pmp_size = -(addr | TARGET_PAGE_MASK);
 250         } else {
 251             pmp_size = sizeof(target_ulong);
 252         }
 253     } else {
 254         pmp_size = size;
 255     }
 256
 257     /* 1.10 draft priv spec states there is an implicit order
 258          from low to high */
 259     for (i = 0; i < MAX_RISCV_PMPS; i++) {
 260         s = pmp_is_in_range(env, i, addr);
 261         e = pmp_is_in_range(env, i, addr + pmp_size - 1);
 262
 263         /* partially inside */
 264         if ((s + e) == 1) {
 265             qemu_log_mask(LOG_GUEST_ERROR,
 266                           "pmp violation - access is partially inside\n");
 267             ret = 0;
 268             break;
 269         }
 270
 271         /* fully inside */
 272         const uint8_t a_field =
 273             pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
 274
 275         /*
 276          * If the PMP entry is not off and the address is in range, do the priv
 277          * check
 278          */
 279         if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
 280             allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
 281             if ((mode != PRV_M) || pmp_is_locked(env, i)) {
 282                 allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
 283             }
 284
 285             if ((privs & allowed_privs) == privs) {
 286                 ret = 1;
 287                 break;
 288             } else {
 289                 ret = 0;
 290                 break;
 291             }
 292         }
 293     }
 294
 295     /* No rule matched */
 296     if (ret == -1) {
 297         if (mode == PRV_M) {
 298             ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
 299                       * M-Mode access, the access succeeds */
 300         } else {
 301             ret = 0; /* Other modes are not allowed to succeed if they don't
 302                       * match a rule, but there are rules.  We've checked for
 303                       * no rule earlier in this function. */
 304         }
 305     }
 306
 307     return ret == 1 ? true : false;
 308 }
 309
 310
 311 /*
 312  * Handle a write to a pmpcfg CSP
 313  */
 314 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
 315     target_ulong val)
 316 {
 317     int i;
 318     uint8_t cfg_val;
 319
 320     trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
 321
 322     if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
 323         qemu_log_mask(LOG_GUEST_ERROR,
 324                       "ignoring pmpcfg write - incorrect address\n");
 325         return;
 326     }
 327
 328     for (i = 0; i < sizeof(target_ulong); i++) {
 329         cfg_val = (val >> 8 * i)  & 0xff;
 330         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
 331     }
 332 }
 333
 334
 335 /*
 336  * Handle a read from a pmpcfg CSP
 337  */
 338 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
 339 {
 340     int i;
 341     target_ulong cfg_val = 0;
 342     target_ulong val = 0;
 343
 344     for (i = 0; i < sizeof(target_ulong); i++) {
 345         val = pmp_read_cfg(env, (reg_index * 4) + i);
 346         cfg_val |= (val << (i * 8));
 347     }
 348     trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
 349
 350     return cfg_val;
 351 }
 352
 353
 354 /*
 355  * Handle a write to a pmpaddr CSP
 356  */
 357 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
 358     target_ulong val)
 359 {
 360     trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
 361     if (addr_index < MAX_RISCV_PMPS) {
 362         if (!pmp_is_locked(env, addr_index)) {
 363             env->pmp_state.pmp[addr_index].addr_reg = val;
 364             pmp_update_rule(env, addr_index);
 365         } else {
 366             qemu_log_mask(LOG_GUEST_ERROR,
 367                           "ignoring pmpaddr write - locked\n");
 368         }
 369     } else {
 370         qemu_log_mask(LOG_GUEST_ERROR,
 371                       "ignoring pmpaddr write - out of bounds\n");
 372     }
 373 }
 374
 375
 376 /*
 377  * Handle a read from a pmpaddr CSP
 378  */
 379 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
 380 {
 381     target_ulong val = 0;
 382
 383     if (addr_index < MAX_RISCV_PMPS) {
 384         val = env->pmp_state.pmp[addr_index].addr_reg;
 385         trace_pmpaddr_csr_read(env->mhartid, addr_index, val);
 386     } else {
 387         qemu_log_mask(LOG_GUEST_ERROR,
 388                       "ignoring pmpaddr read - out of bounds\n");
 389     }
 390
 391     return val;
 392 }
 393
 394 /*
 395  * Calculate the TLB size if the start address or the end address of
 396  * PMP entry is presented in thie TLB page.
 397  */
 398 static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
 399                                      target_ulong tlb_sa, target_ulong tlb_ea)
 400 {
 401     target_ulong pmp_sa = env->pmp_state.addr[pmp_index].sa;
 402     target_ulong pmp_ea = env->pmp_state.addr[pmp_index].ea;
 403
 404     if (pmp_sa >= tlb_sa && pmp_ea <= tlb_ea) {
 405         return pmp_ea - pmp_sa + 1;
 406     }
 407
 408     if (pmp_sa >= tlb_sa && pmp_sa <= tlb_ea && pmp_ea >= tlb_ea) {
 409         return tlb_ea - pmp_sa + 1;
 410     }
 411
 412     if (pmp_ea <= tlb_ea && pmp_ea >= tlb_sa && pmp_sa <= tlb_sa) {
 413         return pmp_ea - tlb_sa + 1;
 414     }
 415
 416     return 0;
 417 }
 418
 419 /*
 420  * Check is there a PMP entry which range covers this page. If so,
 421  * try to find the minimum granularity for the TLB size.
 422  */
 423 bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
 424                          target_ulong *tlb_size)
 425 {
 426     int i;
 427     target_ulong val;
 428     target_ulong tlb_ea = (tlb_sa + TARGET_PAGE_SIZE - 1);
 429
 430     for (i = 0; i < MAX_RISCV_PMPS; i++) {
 431         val = pmp_get_tlb_size(env, i, tlb_sa, tlb_ea);
 432         if (val) {
 433             if (*tlb_size == 0 || *tlb_size > val) {
 434                 *tlb_size = val;
 435             }
 436         }
 437     }
 438
 439     if (*tlb_size != 0) {
 440         return true;
 441     }
 442
 443     return false;
 444 }