2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
34 /* global register indices */
35 static TCGv cpu_gpr
[32], cpu_pc
;
36 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
40 #include "exec/gen-icount.h"
42 typedef struct DisasContext
{
43 DisasContextBase base
;
44 /* pc_succ_insn points to the instruction following base.pc_next */
45 target_ulong pc_succ_insn
;
46 target_ulong priv_ver
;
51 /* Remember the rounding mode encoded in the previous fp instruction,
52 which we have already installed into env->fp_status. Or -1 for
53 no previous fp instruction. Note that we exit the TB when writing
54 to any system register, which includes CSR_FRM, so we do not have
55 to reset this known value. */
60 /* convert riscv funct3 to qemu memop for load/store */
61 static const int tcg_memop_lookup
[8] = {
76 #define CASE_OP_32_64(X) case X: case glue(X, W)
78 #define CASE_OP_32_64(X) case X
81 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
83 return ctx
->misa
& ext
;
86 static void generate_exception(DisasContext
*ctx
, int excp
)
88 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
89 TCGv_i32 helper_tmp
= tcg_const_i32(excp
);
90 gen_helper_raise_exception(cpu_env
, helper_tmp
);
91 tcg_temp_free_i32(helper_tmp
);
92 ctx
->base
.is_jmp
= DISAS_NORETURN
;
95 static void generate_exception_mbadaddr(DisasContext
*ctx
, int excp
)
97 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
98 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
99 TCGv_i32 helper_tmp
= tcg_const_i32(excp
);
100 gen_helper_raise_exception(cpu_env
, helper_tmp
);
101 tcg_temp_free_i32(helper_tmp
);
102 ctx
->base
.is_jmp
= DISAS_NORETURN
;
105 static void gen_exception_debug(void)
107 TCGv_i32 helper_tmp
= tcg_const_i32(EXCP_DEBUG
);
108 gen_helper_raise_exception(cpu_env
, helper_tmp
);
109 tcg_temp_free_i32(helper_tmp
);
112 /* Wrapper around tcg_gen_exit_tb that handles single stepping */
113 static void exit_tb(DisasContext
*ctx
)
115 if (ctx
->base
.singlestep_enabled
) {
116 gen_exception_debug();
118 tcg_gen_exit_tb(NULL
, 0);
122 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
123 static void lookup_and_goto_ptr(DisasContext
*ctx
)
125 if (ctx
->base
.singlestep_enabled
) {
126 gen_exception_debug();
128 tcg_gen_lookup_and_goto_ptr();
132 static void gen_exception_illegal(DisasContext
*ctx
)
134 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
137 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
139 generate_exception_mbadaddr(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
142 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
144 if (unlikely(ctx
->base
.singlestep_enabled
)) {
148 #ifndef CONFIG_USER_ONLY
149 return (ctx
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
155 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
157 if (use_goto_tb(ctx
, dest
)) {
158 /* chaining is only allowed when the jump is to the same page */
160 tcg_gen_movi_tl(cpu_pc
, dest
);
162 /* No need to check for single stepping here as use_goto_tb() will
163 * return false in case of single stepping.
165 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
167 tcg_gen_movi_tl(cpu_pc
, dest
);
168 lookup_and_goto_ptr(ctx
);
172 /* Wrapper for getting reg values - need to check of reg is zero since
173 * cpu_gpr[0] is not actually allocated
175 static inline void gen_get_gpr(TCGv t
, int reg_num
)
178 tcg_gen_movi_tl(t
, 0);
180 tcg_gen_mov_tl(t
, cpu_gpr
[reg_num
]);
184 /* Wrapper for setting reg values - need to check of reg is zero since
185 * cpu_gpr[0] is not actually allocated. this is more for safety purposes,
186 * since we usually avoid calling the OP_TYPE_gen function if we see a write to
189 static inline void gen_set_gpr(int reg_num_dst
, TCGv t
)
191 if (reg_num_dst
!= 0) {
192 tcg_gen_mov_tl(cpu_gpr
[reg_num_dst
], t
);
196 static void gen_mulhsu(TCGv ret
, TCGv arg1
, TCGv arg2
)
198 TCGv rl
= tcg_temp_new();
199 TCGv rh
= tcg_temp_new();
201 tcg_gen_mulu2_tl(rl
, rh
, arg1
, arg2
);
202 /* fix up for one negative */
203 tcg_gen_sari_tl(rl
, arg1
, TARGET_LONG_BITS
- 1);
204 tcg_gen_and_tl(rl
, rl
, arg2
);
205 tcg_gen_sub_tl(ret
, rh
, rl
);
211 static void gen_div(TCGv ret
, TCGv source1
, TCGv source2
)
213 TCGv cond1
, cond2
, zeroreg
, resultopt1
;
215 * Handle by altering args to tcg_gen_div to produce req'd results:
216 * For overflow: want source1 in source1 and 1 in source2
217 * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
219 cond1
= tcg_temp_new();
220 cond2
= tcg_temp_new();
221 zeroreg
= tcg_const_tl(0);
222 resultopt1
= tcg_temp_new();
224 tcg_gen_movi_tl(resultopt1
, (target_ulong
)-1);
225 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond2
, source2
, (target_ulong
)(~0L));
226 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source1
,
227 ((target_ulong
)1) << (TARGET_LONG_BITS
- 1));
228 tcg_gen_and_tl(cond1
, cond1
, cond2
); /* cond1 = overflow */
229 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond2
, source2
, 0); /* cond2 = div 0 */
230 /* if div by zero, set source1 to -1, otherwise don't change */
231 tcg_gen_movcond_tl(TCG_COND_EQ
, source1
, cond2
, zeroreg
, source1
,
233 /* if overflow or div by zero, set source2 to 1, else don't change */
234 tcg_gen_or_tl(cond1
, cond1
, cond2
);
235 tcg_gen_movi_tl(resultopt1
, (target_ulong
)1);
236 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond1
, zeroreg
, source2
,
238 tcg_gen_div_tl(ret
, source1
, source2
);
240 tcg_temp_free(cond1
);
241 tcg_temp_free(cond2
);
242 tcg_temp_free(zeroreg
);
243 tcg_temp_free(resultopt1
);
246 static void gen_divu(TCGv ret
, TCGv source1
, TCGv source2
)
248 TCGv cond1
, zeroreg
, resultopt1
;
249 cond1
= tcg_temp_new();
251 zeroreg
= tcg_const_tl(0);
252 resultopt1
= tcg_temp_new();
254 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source2
, 0);
255 tcg_gen_movi_tl(resultopt1
, (target_ulong
)-1);
256 tcg_gen_movcond_tl(TCG_COND_EQ
, source1
, cond1
, zeroreg
, source1
,
258 tcg_gen_movi_tl(resultopt1
, (target_ulong
)1);
259 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond1
, zeroreg
, source2
,
261 tcg_gen_divu_tl(ret
, source1
, source2
);
263 tcg_temp_free(cond1
);
264 tcg_temp_free(zeroreg
);
265 tcg_temp_free(resultopt1
);
268 static void gen_rem(TCGv ret
, TCGv source1
, TCGv source2
)
270 TCGv cond1
, cond2
, zeroreg
, resultopt1
;
272 cond1
= tcg_temp_new();
273 cond2
= tcg_temp_new();
274 zeroreg
= tcg_const_tl(0);
275 resultopt1
= tcg_temp_new();
277 tcg_gen_movi_tl(resultopt1
, 1L);
278 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond2
, source2
, (target_ulong
)-1);
279 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source1
,
280 (target_ulong
)1 << (TARGET_LONG_BITS
- 1));
281 tcg_gen_and_tl(cond2
, cond1
, cond2
); /* cond1 = overflow */
282 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source2
, 0); /* cond2 = div 0 */
283 /* if overflow or div by zero, set source2 to 1, else don't change */
284 tcg_gen_or_tl(cond2
, cond1
, cond2
);
285 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond2
, zeroreg
, source2
,
287 tcg_gen_rem_tl(resultopt1
, source1
, source2
);
288 /* if div by zero, just return the original dividend */
289 tcg_gen_movcond_tl(TCG_COND_EQ
, ret
, cond1
, zeroreg
, resultopt1
,
292 tcg_temp_free(cond1
);
293 tcg_temp_free(cond2
);
294 tcg_temp_free(zeroreg
);
295 tcg_temp_free(resultopt1
);
298 static void gen_remu(TCGv ret
, TCGv source1
, TCGv source2
)
300 TCGv cond1
, zeroreg
, resultopt1
;
301 cond1
= tcg_temp_new();
302 zeroreg
= tcg_const_tl(0);
303 resultopt1
= tcg_temp_new();
305 tcg_gen_movi_tl(resultopt1
, (target_ulong
)1);
306 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source2
, 0);
307 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond1
, zeroreg
, source2
,
309 tcg_gen_remu_tl(resultopt1
, source1
, source2
);
310 /* if div by zero, just return the original dividend */
311 tcg_gen_movcond_tl(TCG_COND_EQ
, ret
, cond1
, zeroreg
, resultopt1
,
314 tcg_temp_free(cond1
);
315 tcg_temp_free(zeroreg
);
316 tcg_temp_free(resultopt1
);
319 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
321 target_ulong next_pc
;
323 /* check misaligned: */
324 next_pc
= ctx
->base
.pc_next
+ imm
;
325 if (!has_ext(ctx
, RVC
)) {
326 if ((next_pc
& 0x3) != 0) {
327 gen_exception_inst_addr_mis(ctx
);
332 tcg_gen_movi_tl(cpu_gpr
[rd
], ctx
->pc_succ_insn
);
335 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
336 ctx
->base
.is_jmp
= DISAS_NORETURN
;
339 #ifdef TARGET_RISCV64
340 static void gen_load_c(DisasContext
*ctx
, uint32_t opc
, int rd
, int rs1
,
343 TCGv t0
= tcg_temp_new();
344 TCGv t1
= tcg_temp_new();
345 gen_get_gpr(t0
, rs1
);
346 tcg_gen_addi_tl(t0
, t0
, imm
);
347 int memop
= tcg_memop_lookup
[(opc
>> 12) & 0x7];
350 gen_exception_illegal(ctx
);
354 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, memop
);
360 static void gen_store_c(DisasContext
*ctx
, uint32_t opc
, int rs1
, int rs2
,
363 TCGv t0
= tcg_temp_new();
364 TCGv dat
= tcg_temp_new();
365 gen_get_gpr(t0
, rs1
);
366 tcg_gen_addi_tl(t0
, t0
, imm
);
367 gen_get_gpr(dat
, rs2
);
368 int memop
= tcg_memop_lookup
[(opc
>> 12) & 0x7];
371 gen_exception_illegal(ctx
);
375 tcg_gen_qemu_st_tl(dat
, t0
, ctx
->mem_idx
, memop
);
381 #ifndef CONFIG_USER_ONLY
382 /* The states of mstatus_fs are:
383 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
384 * We will have already diagnosed disabled state,
385 * and need to turn initial/clean into dirty.
387 static void mark_fs_dirty(DisasContext
*ctx
)
390 if (ctx
->mstatus_fs
== MSTATUS_FS
) {
393 /* Remember the state change for the rest of the TB. */
394 ctx
->mstatus_fs
= MSTATUS_FS
;
396 tmp
= tcg_temp_new();
397 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
398 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
399 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
403 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
406 #if !defined(TARGET_RISCV64)
407 static void gen_fp_load(DisasContext
*ctx
, uint32_t opc
, int rd
,
408 int rs1
, target_long imm
)
412 if (ctx
->mstatus_fs
== 0) {
413 gen_exception_illegal(ctx
);
418 gen_get_gpr(t0
, rs1
);
419 tcg_gen_addi_tl(t0
, t0
, imm
);
423 if (!has_ext(ctx
, RVF
)) {
426 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
], t0
, ctx
->mem_idx
, MO_TEUL
);
427 /* RISC-V requires NaN-boxing of narrower width floating point values */
428 tcg_gen_ori_i64(cpu_fpr
[rd
], cpu_fpr
[rd
], 0xffffffff00000000ULL
);
431 if (!has_ext(ctx
, RVD
)) {
434 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
], t0
, ctx
->mem_idx
, MO_TEQ
);
438 gen_exception_illegal(ctx
);
446 static void gen_fp_store(DisasContext
*ctx
, uint32_t opc
, int rs1
,
447 int rs2
, target_long imm
)
451 if (ctx
->mstatus_fs
== 0) {
452 gen_exception_illegal(ctx
);
457 gen_get_gpr(t0
, rs1
);
458 tcg_gen_addi_tl(t0
, t0
, imm
);
462 if (!has_ext(ctx
, RVF
)) {
465 tcg_gen_qemu_st_i64(cpu_fpr
[rs2
], t0
, ctx
->mem_idx
, MO_TEUL
);
468 if (!has_ext(ctx
, RVD
)) {
471 tcg_gen_qemu_st_i64(cpu_fpr
[rs2
], t0
, ctx
->mem_idx
, MO_TEQ
);
475 gen_exception_illegal(ctx
);
483 static void gen_set_rm(DisasContext
*ctx
, int rm
)
487 if (ctx
->frm
== rm
) {
491 t0
= tcg_const_i32(rm
);
492 gen_helper_set_rounding_mode(cpu_env
, t0
);
493 tcg_temp_free_i32(t0
);
496 static void decode_RV32_64C0(DisasContext
*ctx
)
498 uint8_t funct3
= extract32(ctx
->opcode
, 13, 3);
499 uint8_t rd_rs2
= GET_C_RS2S(ctx
->opcode
);
500 uint8_t rs1s
= GET_C_RS1S(ctx
->opcode
);
504 #if defined(TARGET_RISCV64)
505 /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
506 gen_load_c(ctx
, OPC_RISC_LD
, rd_rs2
, rs1s
,
507 GET_C_LD_IMM(ctx
->opcode
));
509 /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
510 gen_fp_load(ctx
, OPC_RISC_FLW
, rd_rs2
, rs1s
,
511 GET_C_LW_IMM(ctx
->opcode
));
515 #if defined(TARGET_RISCV64)
516 /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
517 gen_store_c(ctx
, OPC_RISC_SD
, rs1s
, rd_rs2
,
518 GET_C_LD_IMM(ctx
->opcode
));
520 /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
521 gen_fp_store(ctx
, OPC_RISC_FSW
, rs1s
, rd_rs2
,
522 GET_C_LW_IMM(ctx
->opcode
));
528 static void decode_RV32_64C(DisasContext
*ctx
)
530 uint8_t op
= extract32(ctx
->opcode
, 0, 2);
534 decode_RV32_64C0(ctx
);
539 #define EX_SH(amount) \
540 static int ex_shift_##amount(DisasContext *ctx, int imm) \
542 return imm << amount; \
550 #define REQUIRE_EXT(ctx, ext) do { \
551 if (!has_ext(ctx, ext)) { \
556 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
561 static int ex_rvc_shifti(DisasContext
*ctx
, int imm
)
563 /* For RV128 a shamt of 0 means a shift by 64. */
564 return imm
? imm
: 64;
567 /* Include the auto-generated decoder for 32 bit insn */
568 #include "decode_insn32.inc.c"
570 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
,
571 void (*func
)(TCGv
, TCGv
, target_long
))
574 source1
= tcg_temp_new();
576 gen_get_gpr(source1
, a
->rs1
);
578 (*func
)(source1
, source1
, a
->imm
);
580 gen_set_gpr(a
->rd
, source1
);
581 tcg_temp_free(source1
);
585 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
,
586 void (*func
)(TCGv
, TCGv
, TCGv
))
588 TCGv source1
, source2
;
589 source1
= tcg_temp_new();
590 source2
= tcg_temp_new();
592 gen_get_gpr(source1
, a
->rs1
);
593 tcg_gen_movi_tl(source2
, a
->imm
);
595 (*func
)(source1
, source1
, source2
);
597 gen_set_gpr(a
->rd
, source1
);
598 tcg_temp_free(source1
);
599 tcg_temp_free(source2
);
603 #ifdef TARGET_RISCV64
604 static void gen_addw(TCGv ret
, TCGv arg1
, TCGv arg2
)
606 tcg_gen_add_tl(ret
, arg1
, arg2
);
607 tcg_gen_ext32s_tl(ret
, ret
);
610 static void gen_subw(TCGv ret
, TCGv arg1
, TCGv arg2
)
612 tcg_gen_sub_tl(ret
, arg1
, arg2
);
613 tcg_gen_ext32s_tl(ret
, ret
);
616 static void gen_mulw(TCGv ret
, TCGv arg1
, TCGv arg2
)
618 tcg_gen_mul_tl(ret
, arg1
, arg2
);
619 tcg_gen_ext32s_tl(ret
, ret
);
622 static bool gen_arith_div_w(DisasContext
*ctx
, arg_r
*a
,
623 void(*func
)(TCGv
, TCGv
, TCGv
))
625 TCGv source1
, source2
;
626 source1
= tcg_temp_new();
627 source2
= tcg_temp_new();
629 gen_get_gpr(source1
, a
->rs1
);
630 gen_get_gpr(source2
, a
->rs2
);
631 tcg_gen_ext32s_tl(source1
, source1
);
632 tcg_gen_ext32s_tl(source2
, source2
);
634 (*func
)(source1
, source1
, source2
);
636 tcg_gen_ext32s_tl(source1
, source1
);
637 gen_set_gpr(a
->rd
, source1
);
638 tcg_temp_free(source1
);
639 tcg_temp_free(source2
);
643 static bool gen_arith_div_uw(DisasContext
*ctx
, arg_r
*a
,
644 void(*func
)(TCGv
, TCGv
, TCGv
))
646 TCGv source1
, source2
;
647 source1
= tcg_temp_new();
648 source2
= tcg_temp_new();
650 gen_get_gpr(source1
, a
->rs1
);
651 gen_get_gpr(source2
, a
->rs2
);
652 tcg_gen_ext32u_tl(source1
, source1
);
653 tcg_gen_ext32u_tl(source2
, source2
);
655 (*func
)(source1
, source1
, source2
);
657 tcg_gen_ext32s_tl(source1
, source1
);
658 gen_set_gpr(a
->rd
, source1
);
659 tcg_temp_free(source1
);
660 tcg_temp_free(source2
);
666 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
,
667 void(*func
)(TCGv
, TCGv
, TCGv
))
669 TCGv source1
, source2
;
670 source1
= tcg_temp_new();
671 source2
= tcg_temp_new();
673 gen_get_gpr(source1
, a
->rs1
);
674 gen_get_gpr(source2
, a
->rs2
);
676 (*func
)(source1
, source1
, source2
);
678 gen_set_gpr(a
->rd
, source1
);
679 tcg_temp_free(source1
);
680 tcg_temp_free(source2
);
684 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
,
685 void(*func
)(TCGv
, TCGv
, TCGv
))
687 TCGv source1
= tcg_temp_new();
688 TCGv source2
= tcg_temp_new();
690 gen_get_gpr(source1
, a
->rs1
);
691 gen_get_gpr(source2
, a
->rs2
);
693 tcg_gen_andi_tl(source2
, source2
, TARGET_LONG_BITS
- 1);
694 (*func
)(source1
, source1
, source2
);
696 gen_set_gpr(a
->rd
, source1
);
697 tcg_temp_free(source1
);
698 tcg_temp_free(source2
);
702 /* Include insn module translation function */
703 #include "insn_trans/trans_rvi.inc.c"
704 #include "insn_trans/trans_rvm.inc.c"
705 #include "insn_trans/trans_rva.inc.c"
706 #include "insn_trans/trans_rvf.inc.c"
707 #include "insn_trans/trans_rvd.inc.c"
708 #include "insn_trans/trans_privileged.inc.c"
711 * Auto-generated decoder.
712 * Note that the 16-bit decoder reuses some of the trans_* functions
713 * initially declared by the 32-bit decoder, which results in duplicate
714 * declaration warnings. Suppress them.
716 #ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
717 # pragma GCC diagnostic push
718 # pragma GCC diagnostic ignored "-Wredundant-decls"
720 # pragma GCC diagnostic ignored "-Wtypedef-redefinition"
724 #include "decode_insn16.inc.c"
726 #ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
727 # pragma GCC diagnostic pop
730 static void decode_opc(DisasContext
*ctx
)
732 /* check for compressed insn */
733 if (extract32(ctx
->opcode
, 0, 2) != 3) {
734 if (!has_ext(ctx
, RVC
)) {
735 gen_exception_illegal(ctx
);
737 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
738 if (!decode_insn16(ctx
, ctx
->opcode
)) {
739 /* fall back to old decoder */
740 decode_RV32_64C(ctx
);
744 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
745 if (!decode_insn32(ctx
, ctx
->opcode
)) {
746 gen_exception_illegal(ctx
);
751 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
753 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
754 CPURISCVState
*env
= cs
->env_ptr
;
756 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
757 ctx
->mem_idx
= ctx
->base
.tb
->flags
& TB_FLAGS_MMU_MASK
;
758 ctx
->mstatus_fs
= ctx
->base
.tb
->flags
& TB_FLAGS_MSTATUS_FS
;
759 ctx
->priv_ver
= env
->priv_ver
;
760 ctx
->misa
= env
->misa
;
761 ctx
->frm
= -1; /* unknown rounding mode */
764 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
768 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
770 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
772 tcg_gen_insn_start(ctx
->base
.pc_next
);
775 static bool riscv_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
776 const CPUBreakpoint
*bp
)
778 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
780 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
781 ctx
->base
.is_jmp
= DISAS_NORETURN
;
782 gen_exception_debug();
783 /* The address covered by the breakpoint must be included in
784 [tb->pc, tb->pc + tb->size) in order to for it to be
785 properly cleared -- thus we increment the PC here so that
786 the logic setting tb->size below does the right thing. */
787 ctx
->base
.pc_next
+= 4;
791 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
793 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
794 CPURISCVState
*env
= cpu
->env_ptr
;
796 ctx
->opcode
= cpu_ldl_code(env
, ctx
->base
.pc_next
);
798 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
800 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
801 target_ulong page_start
;
803 page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
804 if (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
) {
805 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
810 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
812 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
814 switch (ctx
->base
.is_jmp
) {
816 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
821 g_assert_not_reached();
825 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
827 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
828 log_target_disas(cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
831 static const TranslatorOps riscv_tr_ops
= {
832 .init_disas_context
= riscv_tr_init_disas_context
,
833 .tb_start
= riscv_tr_tb_start
,
834 .insn_start
= riscv_tr_insn_start
,
835 .breakpoint_check
= riscv_tr_breakpoint_check
,
836 .translate_insn
= riscv_tr_translate_insn
,
837 .tb_stop
= riscv_tr_tb_stop
,
838 .disas_log
= riscv_tr_disas_log
,
841 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
845 translator_loop(&riscv_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
848 void riscv_translate_init(void)
852 /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
853 /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
854 /* registers, unless you specifically block reads/writes to reg 0 */
857 for (i
= 1; i
< 32; i
++) {
858 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
859 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
862 for (i
= 0; i
< 32; i
++) {
863 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
864 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
867 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
868 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
870 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),