2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
34 /* global register indices */
35 static TCGv cpu_gpr
[32], cpu_pc
;
36 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
40 #include "exec/gen-icount.h"
42 typedef struct DisasContext
{
43 DisasContextBase base
;
44 /* pc_succ_insn points to the instruction following base.pc_next */
45 target_ulong pc_succ_insn
;
46 target_ulong priv_ver
;
51 /* Remember the rounding mode encoded in the previous fp instruction,
52 which we have already installed into env->fp_status. Or -1 for
53 no previous fp instruction. Note that we exit the TB when writing
54 to any system register, which includes CSR_FRM, so we do not have
55 to reset this known value. */
60 /* convert riscv funct3 to qemu memop for load/store */
61 static const int tcg_memop_lookup
[8] = {
76 #define CASE_OP_32_64(X) case X: case glue(X, W)
78 #define CASE_OP_32_64(X) case X
81 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
83 return ctx
->misa
& ext
;
86 static void generate_exception(DisasContext
*ctx
, int excp
)
88 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
89 TCGv_i32 helper_tmp
= tcg_const_i32(excp
);
90 gen_helper_raise_exception(cpu_env
, helper_tmp
);
91 tcg_temp_free_i32(helper_tmp
);
92 ctx
->base
.is_jmp
= DISAS_NORETURN
;
95 static void generate_exception_mbadaddr(DisasContext
*ctx
, int excp
)
97 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
98 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
99 TCGv_i32 helper_tmp
= tcg_const_i32(excp
);
100 gen_helper_raise_exception(cpu_env
, helper_tmp
);
101 tcg_temp_free_i32(helper_tmp
);
102 ctx
->base
.is_jmp
= DISAS_NORETURN
;
105 static void gen_exception_debug(void)
107 TCGv_i32 helper_tmp
= tcg_const_i32(EXCP_DEBUG
);
108 gen_helper_raise_exception(cpu_env
, helper_tmp
);
109 tcg_temp_free_i32(helper_tmp
);
112 static void gen_exception_illegal(DisasContext
*ctx
)
114 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
117 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
119 generate_exception_mbadaddr(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
122 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
124 if (unlikely(ctx
->base
.singlestep_enabled
)) {
128 #ifndef CONFIG_USER_ONLY
129 return (ctx
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
135 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
137 if (use_goto_tb(ctx
, dest
)) {
138 /* chaining is only allowed when the jump is to the same page */
140 tcg_gen_movi_tl(cpu_pc
, dest
);
141 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
143 tcg_gen_movi_tl(cpu_pc
, dest
);
144 if (ctx
->base
.singlestep_enabled
) {
145 gen_exception_debug();
147 tcg_gen_lookup_and_goto_ptr();
152 /* Wrapper for getting reg values - need to check of reg is zero since
153 * cpu_gpr[0] is not actually allocated
155 static inline void gen_get_gpr(TCGv t
, int reg_num
)
158 tcg_gen_movi_tl(t
, 0);
160 tcg_gen_mov_tl(t
, cpu_gpr
[reg_num
]);
164 /* Wrapper for setting reg values - need to check of reg is zero since
165 * cpu_gpr[0] is not actually allocated. this is more for safety purposes,
166 * since we usually avoid calling the OP_TYPE_gen function if we see a write to
169 static inline void gen_set_gpr(int reg_num_dst
, TCGv t
)
171 if (reg_num_dst
!= 0) {
172 tcg_gen_mov_tl(cpu_gpr
[reg_num_dst
], t
);
176 static void gen_mulhsu(TCGv ret
, TCGv arg1
, TCGv arg2
)
178 TCGv rl
= tcg_temp_new();
179 TCGv rh
= tcg_temp_new();
181 tcg_gen_mulu2_tl(rl
, rh
, arg1
, arg2
);
182 /* fix up for one negative */
183 tcg_gen_sari_tl(rl
, arg1
, TARGET_LONG_BITS
- 1);
184 tcg_gen_and_tl(rl
, rl
, arg2
);
185 tcg_gen_sub_tl(ret
, rh
, rl
);
191 static void gen_div(TCGv ret
, TCGv source1
, TCGv source2
)
193 TCGv cond1
, cond2
, zeroreg
, resultopt1
;
195 * Handle by altering args to tcg_gen_div to produce req'd results:
196 * For overflow: want source1 in source1 and 1 in source2
197 * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
199 cond1
= tcg_temp_new();
200 cond2
= tcg_temp_new();
201 zeroreg
= tcg_const_tl(0);
202 resultopt1
= tcg_temp_new();
204 tcg_gen_movi_tl(resultopt1
, (target_ulong
)-1);
205 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond2
, source2
, (target_ulong
)(~0L));
206 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source1
,
207 ((target_ulong
)1) << (TARGET_LONG_BITS
- 1));
208 tcg_gen_and_tl(cond1
, cond1
, cond2
); /* cond1 = overflow */
209 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond2
, source2
, 0); /* cond2 = div 0 */
210 /* if div by zero, set source1 to -1, otherwise don't change */
211 tcg_gen_movcond_tl(TCG_COND_EQ
, source1
, cond2
, zeroreg
, source1
,
213 /* if overflow or div by zero, set source2 to 1, else don't change */
214 tcg_gen_or_tl(cond1
, cond1
, cond2
);
215 tcg_gen_movi_tl(resultopt1
, (target_ulong
)1);
216 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond1
, zeroreg
, source2
,
218 tcg_gen_div_tl(ret
, source1
, source2
);
220 tcg_temp_free(cond1
);
221 tcg_temp_free(cond2
);
222 tcg_temp_free(zeroreg
);
223 tcg_temp_free(resultopt1
);
226 static void gen_divu(TCGv ret
, TCGv source1
, TCGv source2
)
228 TCGv cond1
, zeroreg
, resultopt1
;
229 cond1
= tcg_temp_new();
231 zeroreg
= tcg_const_tl(0);
232 resultopt1
= tcg_temp_new();
234 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source2
, 0);
235 tcg_gen_movi_tl(resultopt1
, (target_ulong
)-1);
236 tcg_gen_movcond_tl(TCG_COND_EQ
, source1
, cond1
, zeroreg
, source1
,
238 tcg_gen_movi_tl(resultopt1
, (target_ulong
)1);
239 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond1
, zeroreg
, source2
,
241 tcg_gen_divu_tl(ret
, source1
, source2
);
243 tcg_temp_free(cond1
);
244 tcg_temp_free(zeroreg
);
245 tcg_temp_free(resultopt1
);
248 static void gen_rem(TCGv ret
, TCGv source1
, TCGv source2
)
250 TCGv cond1
, cond2
, zeroreg
, resultopt1
;
252 cond1
= tcg_temp_new();
253 cond2
= tcg_temp_new();
254 zeroreg
= tcg_const_tl(0);
255 resultopt1
= tcg_temp_new();
257 tcg_gen_movi_tl(resultopt1
, 1L);
258 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond2
, source2
, (target_ulong
)-1);
259 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source1
,
260 (target_ulong
)1 << (TARGET_LONG_BITS
- 1));
261 tcg_gen_and_tl(cond2
, cond1
, cond2
); /* cond1 = overflow */
262 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source2
, 0); /* cond2 = div 0 */
263 /* if overflow or div by zero, set source2 to 1, else don't change */
264 tcg_gen_or_tl(cond2
, cond1
, cond2
);
265 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond2
, zeroreg
, source2
,
267 tcg_gen_rem_tl(resultopt1
, source1
, source2
);
268 /* if div by zero, just return the original dividend */
269 tcg_gen_movcond_tl(TCG_COND_EQ
, ret
, cond1
, zeroreg
, resultopt1
,
272 tcg_temp_free(cond1
);
273 tcg_temp_free(cond2
);
274 tcg_temp_free(zeroreg
);
275 tcg_temp_free(resultopt1
);
278 static void gen_remu(TCGv ret
, TCGv source1
, TCGv source2
)
280 TCGv cond1
, zeroreg
, resultopt1
;
281 cond1
= tcg_temp_new();
282 zeroreg
= tcg_const_tl(0);
283 resultopt1
= tcg_temp_new();
285 tcg_gen_movi_tl(resultopt1
, (target_ulong
)1);
286 tcg_gen_setcondi_tl(TCG_COND_EQ
, cond1
, source2
, 0);
287 tcg_gen_movcond_tl(TCG_COND_EQ
, source2
, cond1
, zeroreg
, source2
,
289 tcg_gen_remu_tl(resultopt1
, source1
, source2
);
290 /* if div by zero, just return the original dividend */
291 tcg_gen_movcond_tl(TCG_COND_EQ
, ret
, cond1
, zeroreg
, resultopt1
,
294 tcg_temp_free(cond1
);
295 tcg_temp_free(zeroreg
);
296 tcg_temp_free(resultopt1
);
299 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
301 target_ulong next_pc
;
303 /* check misaligned: */
304 next_pc
= ctx
->base
.pc_next
+ imm
;
305 if (!has_ext(ctx
, RVC
)) {
306 if ((next_pc
& 0x3) != 0) {
307 gen_exception_inst_addr_mis(ctx
);
312 tcg_gen_movi_tl(cpu_gpr
[rd
], ctx
->pc_succ_insn
);
315 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
316 ctx
->base
.is_jmp
= DISAS_NORETURN
;
319 #ifdef TARGET_RISCV64
320 static void gen_load_c(DisasContext
*ctx
, uint32_t opc
, int rd
, int rs1
,
323 TCGv t0
= tcg_temp_new();
324 TCGv t1
= tcg_temp_new();
325 gen_get_gpr(t0
, rs1
);
326 tcg_gen_addi_tl(t0
, t0
, imm
);
327 int memop
= tcg_memop_lookup
[(opc
>> 12) & 0x7];
330 gen_exception_illegal(ctx
);
334 tcg_gen_qemu_ld_tl(t1
, t0
, ctx
->mem_idx
, memop
);
340 static void gen_store_c(DisasContext
*ctx
, uint32_t opc
, int rs1
, int rs2
,
343 TCGv t0
= tcg_temp_new();
344 TCGv dat
= tcg_temp_new();
345 gen_get_gpr(t0
, rs1
);
346 tcg_gen_addi_tl(t0
, t0
, imm
);
347 gen_get_gpr(dat
, rs2
);
348 int memop
= tcg_memop_lookup
[(opc
>> 12) & 0x7];
351 gen_exception_illegal(ctx
);
355 tcg_gen_qemu_st_tl(dat
, t0
, ctx
->mem_idx
, memop
);
361 #ifndef CONFIG_USER_ONLY
362 /* The states of mstatus_fs are:
363 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
364 * We will have already diagnosed disabled state,
365 * and need to turn initial/clean into dirty.
367 static void mark_fs_dirty(DisasContext
*ctx
)
370 if (ctx
->mstatus_fs
== MSTATUS_FS
) {
373 /* Remember the state change for the rest of the TB. */
374 ctx
->mstatus_fs
= MSTATUS_FS
;
376 tmp
= tcg_temp_new();
377 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
378 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
379 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
383 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
386 #if !defined(TARGET_RISCV64)
387 static void gen_fp_load(DisasContext
*ctx
, uint32_t opc
, int rd
,
388 int rs1
, target_long imm
)
392 if (ctx
->mstatus_fs
== 0) {
393 gen_exception_illegal(ctx
);
398 gen_get_gpr(t0
, rs1
);
399 tcg_gen_addi_tl(t0
, t0
, imm
);
403 if (!has_ext(ctx
, RVF
)) {
406 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
], t0
, ctx
->mem_idx
, MO_TEUL
);
407 /* RISC-V requires NaN-boxing of narrower width floating point values */
408 tcg_gen_ori_i64(cpu_fpr
[rd
], cpu_fpr
[rd
], 0xffffffff00000000ULL
);
411 if (!has_ext(ctx
, RVD
)) {
414 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
], t0
, ctx
->mem_idx
, MO_TEQ
);
418 gen_exception_illegal(ctx
);
426 static void gen_fp_store(DisasContext
*ctx
, uint32_t opc
, int rs1
,
427 int rs2
, target_long imm
)
431 if (ctx
->mstatus_fs
== 0) {
432 gen_exception_illegal(ctx
);
437 gen_get_gpr(t0
, rs1
);
438 tcg_gen_addi_tl(t0
, t0
, imm
);
442 if (!has_ext(ctx
, RVF
)) {
445 tcg_gen_qemu_st_i64(cpu_fpr
[rs2
], t0
, ctx
->mem_idx
, MO_TEUL
);
448 if (!has_ext(ctx
, RVD
)) {
451 tcg_gen_qemu_st_i64(cpu_fpr
[rs2
], t0
, ctx
->mem_idx
, MO_TEQ
);
455 gen_exception_illegal(ctx
);
463 static void gen_set_rm(DisasContext
*ctx
, int rm
)
467 if (ctx
->frm
== rm
) {
471 t0
= tcg_const_i32(rm
);
472 gen_helper_set_rounding_mode(cpu_env
, t0
);
473 tcg_temp_free_i32(t0
);
476 static void decode_RV32_64C0(DisasContext
*ctx
)
478 uint8_t funct3
= extract32(ctx
->opcode
, 13, 3);
479 uint8_t rd_rs2
= GET_C_RS2S(ctx
->opcode
);
480 uint8_t rs1s
= GET_C_RS1S(ctx
->opcode
);
484 #if defined(TARGET_RISCV64)
485 /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/
486 gen_load_c(ctx
, OPC_RISC_LD
, rd_rs2
, rs1s
,
487 GET_C_LD_IMM(ctx
->opcode
));
489 /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/
490 gen_fp_load(ctx
, OPC_RISC_FLW
, rd_rs2
, rs1s
,
491 GET_C_LW_IMM(ctx
->opcode
));
495 #if defined(TARGET_RISCV64)
496 /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/
497 gen_store_c(ctx
, OPC_RISC_SD
, rs1s
, rd_rs2
,
498 GET_C_LD_IMM(ctx
->opcode
));
500 /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/
501 gen_fp_store(ctx
, OPC_RISC_FSW
, rs1s
, rd_rs2
,
502 GET_C_LW_IMM(ctx
->opcode
));
508 static void decode_RV32_64C(DisasContext
*ctx
)
510 uint8_t op
= extract32(ctx
->opcode
, 0, 2);
514 decode_RV32_64C0(ctx
);
519 #define EX_SH(amount) \
520 static int ex_shift_##amount(int imm) \
522 return imm << amount; \
530 #define REQUIRE_EXT(ctx, ext) do { \
531 if (!has_ext(ctx, ext)) { \
536 static int ex_rvc_register(int reg
)
541 bool decode_insn32(DisasContext
*ctx
, uint32_t insn
);
542 /* Include the auto-generated decoder for 32 bit insn */
543 #include "decode_insn32.inc.c"
545 static bool gen_arith_imm(DisasContext
*ctx
, arg_i
*a
,
546 void(*func
)(TCGv
, TCGv
, TCGv
))
548 TCGv source1
, source2
;
549 source1
= tcg_temp_new();
550 source2
= tcg_temp_new();
552 gen_get_gpr(source1
, a
->rs1
);
553 tcg_gen_movi_tl(source2
, a
->imm
);
555 (*func
)(source1
, source1
, source2
);
557 gen_set_gpr(a
->rd
, source1
);
558 tcg_temp_free(source1
);
559 tcg_temp_free(source2
);
563 #ifdef TARGET_RISCV64
564 static void gen_addw(TCGv ret
, TCGv arg1
, TCGv arg2
)
566 tcg_gen_add_tl(ret
, arg1
, arg2
);
567 tcg_gen_ext32s_tl(ret
, ret
);
570 static void gen_subw(TCGv ret
, TCGv arg1
, TCGv arg2
)
572 tcg_gen_sub_tl(ret
, arg1
, arg2
);
573 tcg_gen_ext32s_tl(ret
, ret
);
576 static void gen_mulw(TCGv ret
, TCGv arg1
, TCGv arg2
)
578 tcg_gen_mul_tl(ret
, arg1
, arg2
);
579 tcg_gen_ext32s_tl(ret
, ret
);
582 static bool gen_arith_div_w(DisasContext
*ctx
, arg_r
*a
,
583 void(*func
)(TCGv
, TCGv
, TCGv
))
585 TCGv source1
, source2
;
586 source1
= tcg_temp_new();
587 source2
= tcg_temp_new();
589 gen_get_gpr(source1
, a
->rs1
);
590 gen_get_gpr(source2
, a
->rs2
);
591 tcg_gen_ext32s_tl(source1
, source1
);
592 tcg_gen_ext32s_tl(source2
, source2
);
594 (*func
)(source1
, source1
, source2
);
596 tcg_gen_ext32s_tl(source1
, source1
);
597 gen_set_gpr(a
->rd
, source1
);
598 tcg_temp_free(source1
);
599 tcg_temp_free(source2
);
603 static bool gen_arith_div_uw(DisasContext
*ctx
, arg_r
*a
,
604 void(*func
)(TCGv
, TCGv
, TCGv
))
606 TCGv source1
, source2
;
607 source1
= tcg_temp_new();
608 source2
= tcg_temp_new();
610 gen_get_gpr(source1
, a
->rs1
);
611 gen_get_gpr(source2
, a
->rs2
);
612 tcg_gen_ext32u_tl(source1
, source1
);
613 tcg_gen_ext32u_tl(source2
, source2
);
615 (*func
)(source1
, source1
, source2
);
617 tcg_gen_ext32s_tl(source1
, source1
);
618 gen_set_gpr(a
->rd
, source1
);
619 tcg_temp_free(source1
);
620 tcg_temp_free(source2
);
626 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
,
627 void(*func
)(TCGv
, TCGv
, TCGv
))
629 TCGv source1
, source2
;
630 source1
= tcg_temp_new();
631 source2
= tcg_temp_new();
633 gen_get_gpr(source1
, a
->rs1
);
634 gen_get_gpr(source2
, a
->rs2
);
636 (*func
)(source1
, source1
, source2
);
638 gen_set_gpr(a
->rd
, source1
);
639 tcg_temp_free(source1
);
640 tcg_temp_free(source2
);
644 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
,
645 void(*func
)(TCGv
, TCGv
, TCGv
))
647 TCGv source1
= tcg_temp_new();
648 TCGv source2
= tcg_temp_new();
650 gen_get_gpr(source1
, a
->rs1
);
651 gen_get_gpr(source2
, a
->rs2
);
653 tcg_gen_andi_tl(source2
, source2
, TARGET_LONG_BITS
- 1);
654 (*func
)(source1
, source1
, source2
);
656 gen_set_gpr(a
->rd
, source1
);
657 tcg_temp_free(source1
);
658 tcg_temp_free(source2
);
662 /* Include insn module translation function */
663 #include "insn_trans/trans_rvi.inc.c"
664 #include "insn_trans/trans_rvm.inc.c"
665 #include "insn_trans/trans_rva.inc.c"
666 #include "insn_trans/trans_rvf.inc.c"
667 #include "insn_trans/trans_rvd.inc.c"
668 #include "insn_trans/trans_privileged.inc.c"
670 bool decode_insn16(DisasContext
*ctx
, uint16_t insn
);
671 /* auto-generated decoder*/
672 #include "decode_insn16.inc.c"
673 #include "insn_trans/trans_rvc.inc.c"
675 static void decode_opc(DisasContext
*ctx
)
677 /* check for compressed insn */
678 if (extract32(ctx
->opcode
, 0, 2) != 3) {
679 if (!has_ext(ctx
, RVC
)) {
680 gen_exception_illegal(ctx
);
682 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
683 if (!decode_insn16(ctx
, ctx
->opcode
)) {
684 /* fall back to old decoder */
685 decode_RV32_64C(ctx
);
689 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
690 if (!decode_insn32(ctx
, ctx
->opcode
)) {
691 gen_exception_illegal(ctx
);
696 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
698 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
699 CPURISCVState
*env
= cs
->env_ptr
;
701 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
702 ctx
->mem_idx
= ctx
->base
.tb
->flags
& TB_FLAGS_MMU_MASK
;
703 ctx
->mstatus_fs
= ctx
->base
.tb
->flags
& TB_FLAGS_MSTATUS_FS
;
704 ctx
->priv_ver
= env
->priv_ver
;
705 ctx
->misa
= env
->misa
;
706 ctx
->frm
= -1; /* unknown rounding mode */
709 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
713 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
715 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
717 tcg_gen_insn_start(ctx
->base
.pc_next
);
720 static bool riscv_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
721 const CPUBreakpoint
*bp
)
723 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
725 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
726 ctx
->base
.is_jmp
= DISAS_NORETURN
;
727 gen_exception_debug();
728 /* The address covered by the breakpoint must be included in
729 [tb->pc, tb->pc + tb->size) in order to for it to be
730 properly cleared -- thus we increment the PC here so that
731 the logic setting tb->size below does the right thing. */
732 ctx
->base
.pc_next
+= 4;
736 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
738 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
739 CPURISCVState
*env
= cpu
->env_ptr
;
741 ctx
->opcode
= cpu_ldl_code(env
, ctx
->base
.pc_next
);
743 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
745 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
746 target_ulong page_start
;
748 page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
749 if (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
) {
750 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
755 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
757 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
759 switch (ctx
->base
.is_jmp
) {
761 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
766 g_assert_not_reached();
770 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
772 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
773 log_target_disas(cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
776 static const TranslatorOps riscv_tr_ops
= {
777 .init_disas_context
= riscv_tr_init_disas_context
,
778 .tb_start
= riscv_tr_tb_start
,
779 .insn_start
= riscv_tr_insn_start
,
780 .breakpoint_check
= riscv_tr_breakpoint_check
,
781 .translate_insn
= riscv_tr_translate_insn
,
782 .tb_stop
= riscv_tr_tb_stop
,
783 .disas_log
= riscv_tr_disas_log
,
786 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
790 translator_loop(&riscv_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
793 void riscv_translate_init(void)
797 /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
798 /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
799 /* registers, unless you specifically block reads/writes to reg 0 */
802 for (i
= 1; i
< 32; i
++) {
803 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
804 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
807 for (i
= 0; i
< 32; i
++) {
808 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
809 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
812 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
813 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
815 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),