target/riscv/translate.c

   1 /*
   2  * RISC-V emulation for qemu: main translation routines.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/log.h"
  21 #include "cpu.h"
  22 #include "tcg/tcg-op.h"
  23 #include "disas/disas.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "exec/exec-all.h"
  26 #include "exec/helper-proto.h"
  27 #include "exec/helper-gen.h"
  28
  29 #include "exec/translator.h"
  30 #include "exec/log.h"
  31
  32 #include "instmap.h"
  33
  34 /* global register indices */
  35 static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
  36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
  37 static TCGv load_res;
  38 static TCGv load_val;
  39
  40 #include "exec/gen-icount.h"
  41
  42 /*
  43  * If an operation is being performed on less than TARGET_LONG_BITS,
  44  * it may require the inputs to be sign- or zero-extended; which will
  45  * depend on the exact operation being performed.
  46  */
  47 typedef enum {
  48     EXT_NONE,
  49     EXT_SIGN,
  50     EXT_ZERO,
  51 } DisasExtend;
  52
  53 typedef struct DisasContext {
  54     DisasContextBase base;
  55     /* pc_succ_insn points to the instruction following base.pc_next */
  56     target_ulong pc_succ_insn;
  57     target_ulong priv_ver;
  58     target_ulong misa;
  59     uint32_t opcode;
  60     uint32_t mstatus_fs;
  61     uint32_t mem_idx;
  62     /* Remember the rounding mode encoded in the previous fp instruction,
  63        which we have already installed into env->fp_status.  Or -1 for
  64        no previous fp instruction.  Note that we exit the TB when writing
  65        to any system register, which includes CSR_FRM, so we do not have
  66        to reset this known value.  */
  67     int frm;
  68     bool w;
  69     bool virt_enabled;
  70     bool ext_ifencei;
  71     bool hlsx;
  72     /* vector extension */
  73     bool vill;
  74     uint8_t lmul;
  75     uint8_t sew;
  76     uint16_t vlen;
  77     uint16_t mlen;
  78     bool vl_eq_vlmax;
  79     uint8_t ntemp;
  80     CPUState *cs;
  81     TCGv zero;
  82     /* Space for 3 operands plus 1 extra for address computation. */
  83     TCGv temp[4];
  84 } DisasContext;
  85
  86 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
  87 {
  88     return ctx->misa & ext;
  89 }
  90
  91 #ifdef TARGET_RISCV32
  92 # define is_32bit(ctx)  true
  93 #elif defined(CONFIG_USER_ONLY)
  94 # define is_32bit(ctx)  false
  95 #else
  96 static inline bool is_32bit(DisasContext *ctx)
  97 {
  98     return (ctx->misa & RV32) == RV32;
  99 }
 100 #endif
 101
 102 /* The word size for this operation. */
 103 static inline int oper_len(DisasContext *ctx)
 104 {
 105     return ctx->w ? 32 : TARGET_LONG_BITS;
 106 }
 107
 108
 109 /*
 110  * RISC-V requires NaN-boxing of narrower width floating point values.
 111  * This applies when a 32-bit value is assigned to a 64-bit FP register.
 112  * For consistency and simplicity, we nanbox results even when the RVD
 113  * extension is not present.
 114  */
 115 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
 116 {
 117     tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
 118 }
 119
 120 /*
 121  * A narrow n-bit operation, where n < FLEN, checks that input operands
 122  * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
 123  * If so, the least-significant bits of the input are used, otherwise the
 124  * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
 125  *
 126  * Here, the result is always nan-boxed, even the canonical nan.
 127  */
 128 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
 129 {
 130     TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
 131     TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull);
 132
 133     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
 134 }
 135
 136 static void generate_exception(DisasContext *ctx, int excp)
 137 {
 138     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 139     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
 140     ctx->base.is_jmp = DISAS_NORETURN;
 141 }
 142
 143 static void generate_exception_mtval(DisasContext *ctx, int excp)
 144 {
 145     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 146     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
 147     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
 148     ctx->base.is_jmp = DISAS_NORETURN;
 149 }
 150
 151 static void gen_exception_debug(void)
 152 {
 153     gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
 154 }
 155
 156 /* Wrapper around tcg_gen_exit_tb that handles single stepping */
 157 static void exit_tb(DisasContext *ctx)
 158 {
 159     if (ctx->base.singlestep_enabled) {
 160         gen_exception_debug();
 161     } else {
 162         tcg_gen_exit_tb(NULL, 0);
 163     }
 164 }
 165
 166 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
 167 static void lookup_and_goto_ptr(DisasContext *ctx)
 168 {
 169     if (ctx->base.singlestep_enabled) {
 170         gen_exception_debug();
 171     } else {
 172         tcg_gen_lookup_and_goto_ptr();
 173     }
 174 }
 175
 176 static void gen_exception_illegal(DisasContext *ctx)
 177 {
 178     generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
 179 }
 180
 181 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 182 {
 183     generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
 184 }
 185
 186 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 187 {
 188     if (translator_use_goto_tb(&ctx->base, dest)) {
 189         tcg_gen_goto_tb(n);
 190         tcg_gen_movi_tl(cpu_pc, dest);
 191         tcg_gen_exit_tb(ctx->base.tb, n);
 192     } else {
 193         tcg_gen_movi_tl(cpu_pc, dest);
 194         lookup_and_goto_ptr(ctx);
 195     }
 196 }
 197
 198 /*
 199  * Wrappers for getting reg values.
 200  *
 201  * The $zero register does not have cpu_gpr[0] allocated -- we supply the
 202  * constant zero as a source, and an uninitialized sink as destination.
 203  *
 204  * Further, we may provide an extension for word operations.
 205  */
 206 static TCGv temp_new(DisasContext *ctx)
 207 {
 208     assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
 209     return ctx->temp[ctx->ntemp++] = tcg_temp_new();
 210 }
 211
 212 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
 213 {
 214     TCGv t;
 215
 216     if (reg_num == 0) {
 217         return ctx->zero;
 218     }
 219
 220     switch (ctx->w ? ext : EXT_NONE) {
 221     case EXT_NONE:
 222         return cpu_gpr[reg_num];
 223     case EXT_SIGN:
 224         t = temp_new(ctx);
 225         tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
 226         return t;
 227     case EXT_ZERO:
 228         t = temp_new(ctx);
 229         tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
 230         return t;
 231     }
 232     g_assert_not_reached();
 233 }
 234
 235 static TCGv dest_gpr(DisasContext *ctx, int reg_num)
 236 {
 237     if (reg_num == 0 || ctx->w) {
 238         return temp_new(ctx);
 239     }
 240     return cpu_gpr[reg_num];
 241 }
 242
 243 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
 244 {
 245     if (reg_num != 0) {
 246         if (ctx->w) {
 247             tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
 248         } else {
 249             tcg_gen_mov_tl(cpu_gpr[reg_num], t);
 250         }
 251     }
 252 }
 253
 254 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 255 {
 256     target_ulong next_pc;
 257
 258     /* check misaligned: */
 259     next_pc = ctx->base.pc_next + imm;
 260     if (!has_ext(ctx, RVC)) {
 261         if ((next_pc & 0x3) != 0) {
 262             gen_exception_inst_addr_mis(ctx);
 263             return;
 264         }
 265     }
 266     if (rd != 0) {
 267         tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
 268     }
 269
 270     gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
 271     ctx->base.is_jmp = DISAS_NORETURN;
 272 }
 273
 274 #ifndef CONFIG_USER_ONLY
 275 /* The states of mstatus_fs are:
 276  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
 277  * We will have already diagnosed disabled state,
 278  * and need to turn initial/clean into dirty.
 279  */
 280 static void mark_fs_dirty(DisasContext *ctx)
 281 {
 282     TCGv tmp;
 283     target_ulong sd;
 284
 285     if (ctx->mstatus_fs == MSTATUS_FS) {
 286         return;
 287     }
 288     /* Remember the state change for the rest of the TB.  */
 289     ctx->mstatus_fs = MSTATUS_FS;
 290
 291     tmp = tcg_temp_new();
 292     sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
 293
 294     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 295     tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 296     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 297
 298     if (ctx->virt_enabled) {
 299         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 300         tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 301         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 302     }
 303     tcg_temp_free(tmp);
 304 }
 305 #else
 306 static inline void mark_fs_dirty(DisasContext *ctx) { }
 307 #endif
 308
 309 static void gen_set_rm(DisasContext *ctx, int rm)
 310 {
 311     if (ctx->frm == rm) {
 312         return;
 313     }
 314     ctx->frm = rm;
 315     gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
 316 }
 317
 318 static int ex_plus_1(DisasContext *ctx, int nf)
 319 {
 320     return nf + 1;
 321 }
 322
 323 #define EX_SH(amount) \
 324     static int ex_shift_##amount(DisasContext *ctx, int imm) \
 325     {                                         \
 326         return imm << amount;                 \
 327     }
 328 EX_SH(1)
 329 EX_SH(2)
 330 EX_SH(3)
 331 EX_SH(4)
 332 EX_SH(12)
 333
 334 #define REQUIRE_EXT(ctx, ext) do { \
 335     if (!has_ext(ctx, ext)) {      \
 336         return false;              \
 337     }                              \
 338 } while (0)
 339
 340 #define REQUIRE_32BIT(ctx) do { \
 341     if (!is_32bit(ctx)) {       \
 342         return false;           \
 343     }                           \
 344 } while (0)
 345
 346 #define REQUIRE_64BIT(ctx) do { \
 347     if (is_32bit(ctx)) {        \
 348         return false;           \
 349     }                           \
 350 } while (0)
 351
 352 static int ex_rvc_register(DisasContext *ctx, int reg)
 353 {
 354     return 8 + reg;
 355 }
 356
 357 static int ex_rvc_shifti(DisasContext *ctx, int imm)
 358 {
 359     /* For RV128 a shamt of 0 means a shift by 64. */
 360     return imm ? imm : 64;
 361 }
 362
 363 /* Include the auto-generated decoder for 32 bit insn */
 364 #include "decode-insn32.c.inc"
 365
 366 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
 367                              void (*func)(TCGv, TCGv, target_long))
 368 {
 369     TCGv dest = dest_gpr(ctx, a->rd);
 370     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 371
 372     func(dest, src1, a->imm);
 373
 374     gen_set_gpr(ctx, a->rd, dest);
 375     return true;
 376 }
 377
 378 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
 379                              void (*func)(TCGv, TCGv, TCGv))
 380 {
 381     TCGv dest = dest_gpr(ctx, a->rd);
 382     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 383     TCGv src2 = tcg_constant_tl(a->imm);
 384
 385     func(dest, src1, src2);
 386
 387     gen_set_gpr(ctx, a->rd, dest);
 388     return true;
 389 }
 390
 391 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
 392                       void (*func)(TCGv, TCGv, TCGv))
 393 {
 394     TCGv dest = dest_gpr(ctx, a->rd);
 395     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 396     TCGv src2 = get_gpr(ctx, a->rs2, ext);
 397
 398     func(dest, src1, src2);
 399
 400     gen_set_gpr(ctx, a->rd, dest);
 401     return true;
 402 }
 403
 404 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
 405                              void (*func)(TCGv, TCGv, target_long))
 406 {
 407     TCGv dest, src1;
 408     int max_len = oper_len(ctx);
 409
 410     if (a->shamt >= max_len) {
 411         return false;
 412     }
 413
 414     dest = dest_gpr(ctx, a->rd);
 415     src1 = get_gpr(ctx, a->rs1, ext);
 416
 417     func(dest, src1, a->shamt);
 418
 419     gen_set_gpr(ctx, a->rd, dest);
 420     return true;
 421 }
 422
 423 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
 424                              void (*func)(TCGv, TCGv, TCGv))
 425 {
 426     TCGv dest, src1, src2;
 427     int max_len = oper_len(ctx);
 428
 429     if (a->shamt >= max_len) {
 430         return false;
 431     }
 432
 433     dest = dest_gpr(ctx, a->rd);
 434     src1 = get_gpr(ctx, a->rs1, ext);
 435     src2 = tcg_constant_tl(a->shamt);
 436
 437     func(dest, src1, src2);
 438
 439     gen_set_gpr(ctx, a->rd, dest);
 440     return true;
 441 }
 442
 443 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
 444                       void (*func)(TCGv, TCGv, TCGv))
 445 {
 446     TCGv dest = dest_gpr(ctx, a->rd);
 447     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 448     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 449     TCGv ext2 = tcg_temp_new();
 450
 451     tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
 452     func(dest, src1, ext2);
 453
 454     gen_set_gpr(ctx, a->rd, dest);
 455     tcg_temp_free(ext2);
 456     return true;
 457 }
 458
 459 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
 460                       void (*func)(TCGv, TCGv))
 461 {
 462     TCGv dest = dest_gpr(ctx, a->rd);
 463     TCGv src1 = get_gpr(ctx, a->rs1, ext);
 464
 465     func(dest, src1);
 466
 467     gen_set_gpr(ctx, a->rd, dest);
 468     return true;
 469 }
 470
 471 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 472 {
 473     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 474     CPUState *cpu = ctx->cs;
 475     CPURISCVState *env = cpu->env_ptr;
 476
 477     return cpu_ldl_code(env, pc);
 478 }
 479
 480 /* Include insn module translation function */
 481 #include "insn_trans/trans_rvi.c.inc"
 482 #include "insn_trans/trans_rvm.c.inc"
 483 #include "insn_trans/trans_rva.c.inc"
 484 #include "insn_trans/trans_rvf.c.inc"
 485 #include "insn_trans/trans_rvd.c.inc"
 486 #include "insn_trans/trans_rvh.c.inc"
 487 #include "insn_trans/trans_rvv.c.inc"
 488 #include "insn_trans/trans_rvb.c.inc"
 489 #include "insn_trans/trans_privileged.c.inc"
 490
 491 /* Include the auto-generated decoder for 16 bit insn */
 492 #include "decode-insn16.c.inc"
 493
 494 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 495 {
 496     /* check for compressed insn */
 497     if (extract16(opcode, 0, 2) != 3) {
 498         if (!has_ext(ctx, RVC)) {
 499             gen_exception_illegal(ctx);
 500         } else {
 501             ctx->pc_succ_insn = ctx->base.pc_next + 2;
 502             if (!decode_insn16(ctx, opcode)) {
 503                 gen_exception_illegal(ctx);
 504             }
 505         }
 506     } else {
 507         uint32_t opcode32 = opcode;
 508         opcode32 = deposit32(opcode32, 16, 16,
 509                              translator_lduw(env, &ctx->base,
 510                                              ctx->base.pc_next + 2));
 511         ctx->pc_succ_insn = ctx->base.pc_next + 4;
 512         if (!decode_insn32(ctx, opcode32)) {
 513             gen_exception_illegal(ctx);
 514         }
 515     }
 516 }
 517
 518 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 519 {
 520     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 521     CPURISCVState *env = cs->env_ptr;
 522     RISCVCPU *cpu = RISCV_CPU(cs);
 523     uint32_t tb_flags = ctx->base.tb->flags;
 524
 525     ctx->pc_succ_insn = ctx->base.pc_first;
 526     ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
 527     ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
 528     ctx->priv_ver = env->priv_ver;
 529 #if !defined(CONFIG_USER_ONLY)
 530     if (riscv_has_ext(env, RVH)) {
 531         ctx->virt_enabled = riscv_cpu_virt_enabled(env);
 532     } else {
 533         ctx->virt_enabled = false;
 534     }
 535 #else
 536     ctx->virt_enabled = false;
 537 #endif
 538     ctx->misa = env->misa;
 539     ctx->frm = -1;  /* unknown rounding mode */
 540     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
 541     ctx->vlen = cpu->cfg.vlen;
 542     ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
 543     ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
 544     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
 545     ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
 546     ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
 547     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
 548     ctx->cs = cs;
 549     ctx->w = false;
 550     ctx->ntemp = 0;
 551     memset(ctx->temp, 0, sizeof(ctx->temp));
 552
 553     ctx->zero = tcg_constant_tl(0);
 554 }
 555
 556 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 557 {
 558 }
 559
 560 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 561 {
 562     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 563
 564     tcg_gen_insn_start(ctx->base.pc_next);
 565 }
 566
 567 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 568 {
 569     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 570     CPURISCVState *env = cpu->env_ptr;
 571     uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
 572
 573     decode_opc(env, ctx, opcode16);
 574     ctx->base.pc_next = ctx->pc_succ_insn;
 575     ctx->w = false;
 576
 577     for (int i = ctx->ntemp - 1; i >= 0; --i) {
 578         tcg_temp_free(ctx->temp[i]);
 579         ctx->temp[i] = NULL;
 580     }
 581     ctx->ntemp = 0;
 582
 583     if (ctx->base.is_jmp == DISAS_NEXT) {
 584         target_ulong page_start;
 585
 586         page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
 587         if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
 588             ctx->base.is_jmp = DISAS_TOO_MANY;
 589         }
 590     }
 591 }
 592
 593 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 594 {
 595     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 596
 597     switch (ctx->base.is_jmp) {
 598     case DISAS_TOO_MANY:
 599         gen_goto_tb(ctx, 0, ctx->base.pc_next);
 600         break;
 601     case DISAS_NORETURN:
 602         break;
 603     default:
 604         g_assert_not_reached();
 605     }
 606 }
 607
 608 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
 609 {
 610 #ifndef CONFIG_USER_ONLY
 611     RISCVCPU *rvcpu = RISCV_CPU(cpu);
 612     CPURISCVState *env = &rvcpu->env;
 613 #endif
 614
 615     qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
 616 #ifndef CONFIG_USER_ONLY
 617     qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt);
 618 #endif
 619     log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
 620 }
 621
 622 static const TranslatorOps riscv_tr_ops = {
 623     .init_disas_context = riscv_tr_init_disas_context,
 624     .tb_start           = riscv_tr_tb_start,
 625     .insn_start         = riscv_tr_insn_start,
 626     .translate_insn     = riscv_tr_translate_insn,
 627     .tb_stop            = riscv_tr_tb_stop,
 628     .disas_log          = riscv_tr_disas_log,
 629 };
 630
 631 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
 632 {
 633     DisasContext ctx;
 634
 635     translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
 636 }
 637
 638 void riscv_translate_init(void)
 639 {
 640     int i;
 641
 642     /*
 643      * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
 644      * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
 645      * unless you specifically block reads/writes to reg 0.
 646      */
 647     cpu_gpr[0] = NULL;
 648
 649     for (i = 1; i < 32; i++) {
 650         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
 651             offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
 652     }
 653
 654     for (i = 0; i < 32; i++) {
 655         cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
 656             offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
 657     }
 658
 659     cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
 660     cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
 661     load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
 662                              "load_res");
 663     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
 664                              "load_val");
 665 }