2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
31 #include "semihosting/semihost.h"
34 #include "internals.h"
36 /* global register indices */
37 static TCGv cpu_gpr
[32], cpu_gprh
[32], cpu_pc
, cpu_vl
, cpu_vstart
;
38 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
41 /* globals for PM CSRs */
45 #include "exec/gen-icount.h"
48 * If an operation is being performed on less than TARGET_LONG_BITS,
49 * it may require the inputs to be sign- or zero-extended; which will
50 * depend on the exact operation being performed.
58 typedef struct DisasContext
{
59 DisasContextBase base
;
60 /* pc_succ_insn points to the instruction following base.pc_next */
61 target_ulong pc_succ_insn
;
62 target_ulong priv_ver
;
63 RISCVMXL misa_mxl_max
;
69 uint32_t mstatus_hs_fs
;
70 uint32_t mstatus_hs_vs
;
72 /* Remember the rounding mode encoded in the previous fp instruction,
73 which we have already installed into env->fp_status. Or -1 for
74 no previous fp instruction. Note that we exit the TB when writing
75 to any system register, which includes CSR_FRM, so we do not have
76 to reset this known value. */
81 const RISCVCPUConfig
*cfg_ptr
;
83 /* vector extension */
86 * Encode LMUL to lmul as follows:
107 /* Space for 3 operands plus 1 extra for address computation. */
109 /* Space for 4 operands(1 dest and <=3 src) for float point computation */
112 /* PointerMasking extension */
113 bool pm_mask_enabled
;
114 bool pm_base_enabled
;
115 /* Use icount trigger for native debug */
117 /* TCG of the current insn_start */
121 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
123 return ctx
->misa_ext
& ext
;
126 static bool always_true_p(DisasContext
*ctx
__attribute__((__unused__
)))
131 #define MATERIALISE_EXT_PREDICATE(ext) \
132 static bool has_ ## ext ## _p(DisasContext *ctx) \
134 return ctx->cfg_ptr->ext_ ## ext ; \
137 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
);
139 #ifdef TARGET_RISCV32
140 #define get_xl(ctx) MXL_RV32
141 #elif defined(CONFIG_USER_ONLY)
142 #define get_xl(ctx) MXL_RV64
144 #define get_xl(ctx) ((ctx)->xl)
147 /* The word size for this machine mode. */
148 static inline int __attribute__((unused
)) get_xlen(DisasContext
*ctx
)
150 return 16 << get_xl(ctx
);
153 /* The operation length, as opposed to the xlen. */
154 #ifdef TARGET_RISCV32
155 #define get_ol(ctx) MXL_RV32
157 #define get_ol(ctx) ((ctx)->ol)
160 static inline int get_olen(DisasContext
*ctx
)
162 return 16 << get_ol(ctx
);
165 /* The maximum register length */
166 #ifdef TARGET_RISCV32
167 #define get_xl_max(ctx) MXL_RV32
169 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
173 * RISC-V requires NaN-boxing of narrower width floating point values.
174 * This applies when a 32-bit value is assigned to a 64-bit FP register.
175 * For consistency and simplicity, we nanbox results even when the RVD
176 * extension is not present.
178 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
180 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
183 static void gen_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
185 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(16, 48));
189 * A narrow n-bit operation, where n < FLEN, checks that input operands
190 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
191 * If so, the least-significant bits of the input are used, otherwise the
192 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
194 * Here, the result is always nan-boxed, even the canonical nan.
196 static void gen_check_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
198 TCGv_i64 t_max
= tcg_const_i64(0xffffffffffff0000ull
);
199 TCGv_i64 t_nan
= tcg_const_i64(0xffffffffffff7e00ull
);
201 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
202 tcg_temp_free_i64(t_max
);
203 tcg_temp_free_i64(t_nan
);
206 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
208 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
209 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
211 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
214 static void decode_save_opc(DisasContext
*ctx
)
216 assert(ctx
->insn_start
!= NULL
);
217 tcg_set_insn_start_param(ctx
->insn_start
, 1, ctx
->opcode
);
218 ctx
->insn_start
= NULL
;
221 static void gen_set_pc_imm(DisasContext
*ctx
, target_ulong dest
)
223 if (get_xl(ctx
) == MXL_RV32
) {
224 dest
= (int32_t)dest
;
226 tcg_gen_movi_tl(cpu_pc
, dest
);
229 static void gen_set_pc(DisasContext
*ctx
, TCGv dest
)
231 if (get_xl(ctx
) == MXL_RV32
) {
232 tcg_gen_ext32s_tl(cpu_pc
, dest
);
234 tcg_gen_mov_tl(cpu_pc
, dest
);
238 static void generate_exception(DisasContext
*ctx
, int excp
)
240 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
241 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
242 ctx
->base
.is_jmp
= DISAS_NORETURN
;
245 static void gen_exception_illegal(DisasContext
*ctx
)
247 tcg_gen_st_i32(tcg_constant_i32(ctx
->opcode
), cpu_env
,
248 offsetof(CPURISCVState
, bins
));
249 if (ctx
->virt_inst_excp
) {
250 generate_exception(ctx
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
);
252 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
256 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
258 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
259 generate_exception(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
262 static void lookup_and_goto_ptr(DisasContext
*ctx
)
264 #ifndef CONFIG_USER_ONLY
266 gen_helper_itrigger_match(cpu_env
);
269 tcg_gen_lookup_and_goto_ptr();
272 static void exit_tb(DisasContext
*ctx
)
274 #ifndef CONFIG_USER_ONLY
276 gen_helper_itrigger_match(cpu_env
);
279 tcg_gen_exit_tb(NULL
, 0);
282 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
285 * Under itrigger, instruction executes one by one like singlestep,
286 * direct block chain benefits will be small.
288 if (translator_use_goto_tb(&ctx
->base
, dest
) && !ctx
->itrigger
) {
290 gen_set_pc_imm(ctx
, dest
);
291 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
293 gen_set_pc_imm(ctx
, dest
);
294 lookup_and_goto_ptr(ctx
);
299 * Wrappers for getting reg values.
301 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
302 * constant zero as a source, and an uninitialized sink as destination.
304 * Further, we may provide an extension for word operations.
306 static TCGv
temp_new(DisasContext
*ctx
)
308 assert(ctx
->ntemp
< ARRAY_SIZE(ctx
->temp
));
309 return ctx
->temp
[ctx
->ntemp
++] = tcg_temp_new();
312 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
320 switch (get_ol(ctx
)) {
327 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
331 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
334 g_assert_not_reached();
341 g_assert_not_reached();
343 return cpu_gpr
[reg_num
];
346 static TCGv
get_gprh(DisasContext
*ctx
, int reg_num
)
348 assert(get_xl(ctx
) == MXL_RV128
);
352 return cpu_gprh
[reg_num
];
355 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
357 if (reg_num
== 0 || get_olen(ctx
) < TARGET_LONG_BITS
) {
358 return temp_new(ctx
);
360 return cpu_gpr
[reg_num
];
363 static TCGv
dest_gprh(DisasContext
*ctx
, int reg_num
)
366 return temp_new(ctx
);
368 return cpu_gprh
[reg_num
];
371 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
374 switch (get_ol(ctx
)) {
376 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
380 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
383 g_assert_not_reached();
386 if (get_xl_max(ctx
) == MXL_RV128
) {
387 tcg_gen_sari_tl(cpu_gprh
[reg_num
], cpu_gpr
[reg_num
], 63);
392 static void gen_set_gpri(DisasContext
*ctx
, int reg_num
, target_long imm
)
395 switch (get_ol(ctx
)) {
397 tcg_gen_movi_tl(cpu_gpr
[reg_num
], (int32_t)imm
);
401 tcg_gen_movi_tl(cpu_gpr
[reg_num
], imm
);
404 g_assert_not_reached();
407 if (get_xl_max(ctx
) == MXL_RV128
) {
408 tcg_gen_movi_tl(cpu_gprh
[reg_num
], -(imm
< 0));
413 static void gen_set_gpr128(DisasContext
*ctx
, int reg_num
, TCGv rl
, TCGv rh
)
415 assert(get_ol(ctx
) == MXL_RV128
);
417 tcg_gen_mov_tl(cpu_gpr
[reg_num
], rl
);
418 tcg_gen_mov_tl(cpu_gprh
[reg_num
], rh
);
422 static TCGv_i64
ftemp_new(DisasContext
*ctx
)
424 assert(ctx
->nftemp
< ARRAY_SIZE(ctx
->ftemp
));
425 return ctx
->ftemp
[ctx
->nftemp
++] = tcg_temp_new_i64();
428 static TCGv_i64
get_fpr_hs(DisasContext
*ctx
, int reg_num
)
430 if (!ctx
->cfg_ptr
->ext_zfinx
) {
431 return cpu_fpr
[reg_num
];
435 return tcg_constant_i64(0);
437 switch (get_xl(ctx
)) {
439 #ifdef TARGET_RISCV32
441 TCGv_i64 t
= ftemp_new(ctx
);
442 tcg_gen_ext_i32_i64(t
, cpu_gpr
[reg_num
]);
448 return cpu_gpr
[reg_num
];
451 g_assert_not_reached();
455 static TCGv_i64
get_fpr_d(DisasContext
*ctx
, int reg_num
)
457 if (!ctx
->cfg_ptr
->ext_zfinx
) {
458 return cpu_fpr
[reg_num
];
462 return tcg_constant_i64(0);
464 switch (get_xl(ctx
)) {
467 TCGv_i64 t
= ftemp_new(ctx
);
468 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1]);
471 #ifdef TARGET_RISCV64
473 return cpu_gpr
[reg_num
];
476 g_assert_not_reached();
480 static TCGv_i64
dest_fpr(DisasContext
*ctx
, int reg_num
)
482 if (!ctx
->cfg_ptr
->ext_zfinx
) {
483 return cpu_fpr
[reg_num
];
487 return ftemp_new(ctx
);
490 switch (get_xl(ctx
)) {
492 return ftemp_new(ctx
);
493 #ifdef TARGET_RISCV64
495 return cpu_gpr
[reg_num
];
498 g_assert_not_reached();
502 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
503 static void gen_set_fpr_hs(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
505 if (!ctx
->cfg_ptr
->ext_zfinx
) {
506 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
510 switch (get_xl(ctx
)) {
512 #ifdef TARGET_RISCV32
513 tcg_gen_extrl_i64_i32(cpu_gpr
[reg_num
], t
);
518 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
522 g_assert_not_reached();
527 static void gen_set_fpr_d(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
529 if (!ctx
->cfg_ptr
->ext_zfinx
) {
530 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
535 switch (get_xl(ctx
)) {
537 #ifdef TARGET_RISCV32
538 tcg_gen_extr_i64_i32(cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1], t
);
541 tcg_gen_ext32s_i64(cpu_gpr
[reg_num
], t
);
542 tcg_gen_sari_i64(cpu_gpr
[reg_num
+ 1], t
, 32);
545 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
549 g_assert_not_reached();
554 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
556 target_ulong next_pc
;
558 /* check misaligned: */
559 next_pc
= ctx
->base
.pc_next
+ imm
;
560 if (!has_ext(ctx
, RVC
)) {
561 if ((next_pc
& 0x3) != 0) {
562 gen_exception_inst_addr_mis(ctx
);
567 gen_set_gpri(ctx
, rd
, ctx
->pc_succ_insn
);
568 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
569 ctx
->base
.is_jmp
= DISAS_NORETURN
;
572 /* Compute a canonical address from a register plus offset. */
573 static TCGv
get_address(DisasContext
*ctx
, int rs1
, int imm
)
575 TCGv addr
= temp_new(ctx
);
576 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
578 tcg_gen_addi_tl(addr
, src1
, imm
);
579 if (ctx
->pm_mask_enabled
) {
580 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
581 } else if (get_xl(ctx
) == MXL_RV32
) {
582 tcg_gen_ext32u_tl(addr
, addr
);
584 if (ctx
->pm_base_enabled
) {
585 tcg_gen_or_tl(addr
, addr
, pm_base
);
590 #ifndef CONFIG_USER_ONLY
591 /* The states of mstatus_fs are:
592 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
593 * We will have already diagnosed disabled state,
594 * and need to turn initial/clean into dirty.
596 static void mark_fs_dirty(DisasContext
*ctx
)
600 if (!has_ext(ctx
, RVF
)) {
604 if (ctx
->mstatus_fs
!= MSTATUS_FS
) {
605 /* Remember the state change for the rest of the TB. */
606 ctx
->mstatus_fs
= MSTATUS_FS
;
608 tmp
= tcg_temp_new();
609 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
610 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
611 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
615 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_fs
!= MSTATUS_FS
) {
616 /* Remember the stage change for the rest of the TB. */
617 ctx
->mstatus_hs_fs
= MSTATUS_FS
;
619 tmp
= tcg_temp_new();
620 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
621 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
622 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
627 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
630 #ifndef CONFIG_USER_ONLY
631 /* The states of mstatus_vs are:
632 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
633 * We will have already diagnosed disabled state,
634 * and need to turn initial/clean into dirty.
636 static void mark_vs_dirty(DisasContext
*ctx
)
640 if (ctx
->mstatus_vs
!= MSTATUS_VS
) {
641 /* Remember the state change for the rest of the TB. */
642 ctx
->mstatus_vs
= MSTATUS_VS
;
644 tmp
= tcg_temp_new();
645 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
646 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
647 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
651 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_vs
!= MSTATUS_VS
) {
652 /* Remember the stage change for the rest of the TB. */
653 ctx
->mstatus_hs_vs
= MSTATUS_VS
;
655 tmp
= tcg_temp_new();
656 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
657 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
658 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
663 static inline void mark_vs_dirty(DisasContext
*ctx
) { }
666 static void gen_set_rm(DisasContext
*ctx
, int rm
)
668 if (ctx
->frm
== rm
) {
673 if (rm
== RISCV_FRM_ROD
) {
674 gen_helper_set_rod_rounding_mode(cpu_env
);
678 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
679 decode_save_opc(ctx
);
680 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
683 static int ex_plus_1(DisasContext
*ctx
, int nf
)
688 #define EX_SH(amount) \
689 static int ex_shift_##amount(DisasContext *ctx, int imm) \
691 return imm << amount; \
699 #define REQUIRE_EXT(ctx, ext) do { \
700 if (!has_ext(ctx, ext)) { \
705 #define REQUIRE_32BIT(ctx) do { \
706 if (get_xl(ctx) != MXL_RV32) { \
711 #define REQUIRE_64BIT(ctx) do { \
712 if (get_xl(ctx) != MXL_RV64) { \
717 #define REQUIRE_128BIT(ctx) do { \
718 if (get_xl(ctx) != MXL_RV128) { \
723 #define REQUIRE_64_OR_128BIT(ctx) do { \
724 if (get_xl(ctx) == MXL_RV32) { \
729 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \
730 if (!ctx->cfg_ptr->ext_##A && \
731 !ctx->cfg_ptr->ext_##B) { \
736 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
741 static int ex_rvc_shiftli(DisasContext
*ctx
, int imm
)
743 /* For RV128 a shamt of 0 means a shift by 64. */
744 if (get_ol(ctx
) == MXL_RV128
) {
745 imm
= imm
? imm
: 64;
750 static int ex_rvc_shiftri(DisasContext
*ctx
, int imm
)
753 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right
754 * shifts, the shamt is sign-extended.
756 if (get_ol(ctx
) == MXL_RV128
) {
757 imm
= imm
| (imm
& 32) << 1;
758 imm
= imm
? imm
: 64;
763 /* Include the auto-generated decoder for 32 bit insn */
764 #include "decode-insn32.c.inc"
766 static bool gen_logic_imm_fn(DisasContext
*ctx
, arg_i
*a
,
767 void (*func
)(TCGv
, TCGv
, target_long
))
769 TCGv dest
= dest_gpr(ctx
, a
->rd
);
770 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
772 func(dest
, src1
, a
->imm
);
774 if (get_xl(ctx
) == MXL_RV128
) {
775 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
776 TCGv desth
= dest_gprh(ctx
, a
->rd
);
778 func(desth
, src1h
, -(a
->imm
< 0));
779 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
781 gen_set_gpr(ctx
, a
->rd
, dest
);
787 static bool gen_logic(DisasContext
*ctx
, arg_r
*a
,
788 void (*func
)(TCGv
, TCGv
, TCGv
))
790 TCGv dest
= dest_gpr(ctx
, a
->rd
);
791 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
792 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
794 func(dest
, src1
, src2
);
796 if (get_xl(ctx
) == MXL_RV128
) {
797 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
798 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
799 TCGv desth
= dest_gprh(ctx
, a
->rd
);
801 func(desth
, src1h
, src2h
);
802 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
804 gen_set_gpr(ctx
, a
->rd
, dest
);
810 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
811 void (*func
)(TCGv
, TCGv
, target_long
),
812 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
814 TCGv dest
= dest_gpr(ctx
, a
->rd
);
815 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
817 if (get_ol(ctx
) < MXL_RV128
) {
818 func(dest
, src1
, a
->imm
);
819 gen_set_gpr(ctx
, a
->rd
, dest
);
825 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
826 TCGv desth
= dest_gprh(ctx
, a
->rd
);
828 f128(dest
, desth
, src1
, src1h
, a
->imm
);
829 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
834 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
835 void (*func
)(TCGv
, TCGv
, TCGv
),
836 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
838 TCGv dest
= dest_gpr(ctx
, a
->rd
);
839 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
840 TCGv src2
= tcg_constant_tl(a
->imm
);
842 if (get_ol(ctx
) < MXL_RV128
) {
843 func(dest
, src1
, src2
);
844 gen_set_gpr(ctx
, a
->rd
, dest
);
850 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
851 TCGv src2h
= tcg_constant_tl(-(a
->imm
< 0));
852 TCGv desth
= dest_gprh(ctx
, a
->rd
);
854 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
855 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
860 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
861 void (*func
)(TCGv
, TCGv
, TCGv
),
862 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
864 TCGv dest
= dest_gpr(ctx
, a
->rd
);
865 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
866 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
868 if (get_ol(ctx
) < MXL_RV128
) {
869 func(dest
, src1
, src2
);
870 gen_set_gpr(ctx
, a
->rd
, dest
);
876 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
877 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
878 TCGv desth
= dest_gprh(ctx
, a
->rd
);
880 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
881 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
886 static bool gen_arith_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
887 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
888 void (*f_32
)(TCGv
, TCGv
, TCGv
),
889 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
891 int olen
= get_olen(ctx
);
893 if (olen
!= TARGET_LONG_BITS
) {
896 } else if (olen
!= 128) {
897 g_assert_not_reached();
900 return gen_arith(ctx
, a
, ext
, f_tl
, f_128
);
903 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
904 void (*func
)(TCGv
, TCGv
, target_long
),
905 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
908 int max_len
= get_olen(ctx
);
910 if (a
->shamt
>= max_len
) {
914 dest
= dest_gpr(ctx
, a
->rd
);
915 src1
= get_gpr(ctx
, a
->rs1
, ext
);
918 func(dest
, src1
, a
->shamt
);
919 gen_set_gpr(ctx
, a
->rd
, dest
);
921 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
922 TCGv desth
= dest_gprh(ctx
, a
->rd
);
927 f128(dest
, desth
, src1
, src1h
, a
->shamt
);
928 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
933 static bool gen_shift_imm_fn_per_ol(DisasContext
*ctx
, arg_shift
*a
,
935 void (*f_tl
)(TCGv
, TCGv
, target_long
),
936 void (*f_32
)(TCGv
, TCGv
, target_long
),
937 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
,
940 int olen
= get_olen(ctx
);
941 if (olen
!= TARGET_LONG_BITS
) {
944 } else if (olen
!= 128) {
945 g_assert_not_reached();
948 return gen_shift_imm_fn(ctx
, a
, ext
, f_tl
, f_128
);
951 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
952 void (*func
)(TCGv
, TCGv
, TCGv
))
954 TCGv dest
, src1
, src2
;
955 int max_len
= get_olen(ctx
);
957 if (a
->shamt
>= max_len
) {
961 dest
= dest_gpr(ctx
, a
->rd
);
962 src1
= get_gpr(ctx
, a
->rs1
, ext
);
963 src2
= tcg_constant_tl(a
->shamt
);
965 func(dest
, src1
, src2
);
967 gen_set_gpr(ctx
, a
->rd
, dest
);
971 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
972 void (*func
)(TCGv
, TCGv
, TCGv
),
973 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
975 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
976 TCGv ext2
= tcg_temp_new();
977 int max_len
= get_olen(ctx
);
979 tcg_gen_andi_tl(ext2
, src2
, max_len
- 1);
981 TCGv dest
= dest_gpr(ctx
, a
->rd
);
982 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
985 func(dest
, src1
, ext2
);
986 gen_set_gpr(ctx
, a
->rd
, dest
);
988 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
989 TCGv desth
= dest_gprh(ctx
, a
->rd
);
994 f128(dest
, desth
, src1
, src1h
, ext2
);
995 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
1001 static bool gen_shift_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
1002 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
1003 void (*f_32
)(TCGv
, TCGv
, TCGv
),
1004 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
1006 int olen
= get_olen(ctx
);
1007 if (olen
!= TARGET_LONG_BITS
) {
1010 } else if (olen
!= 128) {
1011 g_assert_not_reached();
1014 return gen_shift(ctx
, a
, ext
, f_tl
, f_128
);
1017 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1018 void (*func
)(TCGv
, TCGv
))
1020 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1021 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1025 gen_set_gpr(ctx
, a
->rd
, dest
);
1029 static bool gen_unary_per_ol(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1030 void (*f_tl
)(TCGv
, TCGv
),
1031 void (*f_32
)(TCGv
, TCGv
))
1033 int olen
= get_olen(ctx
);
1035 if (olen
!= TARGET_LONG_BITS
) {
1039 g_assert_not_reached();
1042 return gen_unary(ctx
, a
, ext
, f_tl
);
1045 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
1047 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1048 CPUState
*cpu
= ctx
->cs
;
1049 CPURISCVState
*env
= cpu
->env_ptr
;
1051 return cpu_ldl_code(env
, pc
);
1054 /* Include insn module translation function */
1055 #include "insn_trans/trans_rvi.c.inc"
1056 #include "insn_trans/trans_rvm.c.inc"
1057 #include "insn_trans/trans_rva.c.inc"
1058 #include "insn_trans/trans_rvf.c.inc"
1059 #include "insn_trans/trans_rvd.c.inc"
1060 #include "insn_trans/trans_rvh.c.inc"
1061 #include "insn_trans/trans_rvv.c.inc"
1062 #include "insn_trans/trans_rvb.c.inc"
1063 #include "insn_trans/trans_rvzawrs.c.inc"
1064 #include "insn_trans/trans_rvzfh.c.inc"
1065 #include "insn_trans/trans_rvk.c.inc"
1066 #include "insn_trans/trans_privileged.c.inc"
1067 #include "insn_trans/trans_svinval.c.inc"
1068 #include "insn_trans/trans_xventanacondops.c.inc"
1070 /* Include the auto-generated decoder for 16 bit insn */
1071 #include "decode-insn16.c.inc"
1072 /* Include decoders for factored-out extensions */
1073 #include "decode-XVentanaCondOps.c.inc"
1075 /* The specification allows for longer insns, but not supported by qemu. */
1076 #define MAX_INSN_LEN 4
1078 static inline int insn_len(uint16_t first_word
)
1080 return (first_word
& 3) == 3 ? 4 : 2;
1083 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
1086 * A table with predicate (i.e., guard) functions and decoder functions
1087 * that are tested in-order until a decoder matches onto the opcode.
1089 static const struct {
1090 bool (*guard_func
)(DisasContext
*);
1091 bool (*decode_func
)(DisasContext
*, uint32_t);
1093 { always_true_p
, decode_insn32
},
1094 { has_XVentanaCondOps_p
, decode_XVentanaCodeOps
},
1097 ctx
->virt_inst_excp
= false;
1098 /* Check for compressed insn */
1099 if (insn_len(opcode
) == 2) {
1100 ctx
->opcode
= opcode
;
1101 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
1102 if (has_ext(ctx
, RVC
) && decode_insn16(ctx
, opcode
)) {
1106 uint32_t opcode32
= opcode
;
1107 opcode32
= deposit32(opcode32
, 16, 16,
1108 translator_lduw(env
, &ctx
->base
,
1109 ctx
->base
.pc_next
+ 2));
1110 ctx
->opcode
= opcode32
;
1111 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
1113 for (size_t i
= 0; i
< ARRAY_SIZE(decoders
); ++i
) {
1114 if (decoders
[i
].guard_func(ctx
) &&
1115 decoders
[i
].decode_func(ctx
, opcode32
)) {
1121 gen_exception_illegal(ctx
);
1124 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
1126 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1127 CPURISCVState
*env
= cs
->env_ptr
;
1128 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1129 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
1131 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
1132 ctx
->mem_idx
= FIELD_EX32(tb_flags
, TB_FLAGS
, MEM_IDX
);
1133 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
1134 ctx
->mstatus_vs
= tb_flags
& TB_FLAGS_MSTATUS_VS
;
1135 ctx
->priv_ver
= env
->priv_ver
;
1136 #if !defined(CONFIG_USER_ONLY)
1137 if (riscv_has_ext(env
, RVH
)) {
1138 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
1140 ctx
->virt_enabled
= false;
1143 ctx
->virt_enabled
= false;
1145 ctx
->misa_ext
= env
->misa_ext
;
1146 ctx
->frm
= -1; /* unknown rounding mode */
1147 ctx
->cfg_ptr
= &(cpu
->cfg
);
1148 ctx
->mstatus_hs_fs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_FS
);
1149 ctx
->mstatus_hs_vs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_VS
);
1150 ctx
->hlsx
= FIELD_EX32(tb_flags
, TB_FLAGS
, HLSX
);
1151 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
1152 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
1153 ctx
->lmul
= sextract32(FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
), 0, 3);
1154 ctx
->vta
= FIELD_EX32(tb_flags
, TB_FLAGS
, VTA
) && cpu
->cfg
.rvv_ta_all_1s
;
1155 ctx
->vma
= FIELD_EX32(tb_flags
, TB_FLAGS
, VMA
) && cpu
->cfg
.rvv_ma_all_1s
;
1156 ctx
->cfg_vta_all_1s
= cpu
->cfg
.rvv_ta_all_1s
;
1157 ctx
->vstart
= env
->vstart
;
1158 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
1159 ctx
->misa_mxl_max
= env
->misa_mxl_max
;
1160 ctx
->xl
= FIELD_EX32(tb_flags
, TB_FLAGS
, XL
);
1163 memset(ctx
->temp
, 0, sizeof(ctx
->temp
));
1165 memset(ctx
->ftemp
, 0, sizeof(ctx
->ftemp
));
1166 ctx
->pm_mask_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_MASK_ENABLED
);
1167 ctx
->pm_base_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_BASE_ENABLED
);
1168 ctx
->itrigger
= FIELD_EX32(tb_flags
, TB_FLAGS
, ITRIGGER
);
1169 ctx
->zero
= tcg_constant_tl(0);
1172 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
1176 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1178 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1180 tcg_gen_insn_start(ctx
->base
.pc_next
, 0);
1181 ctx
->insn_start
= tcg_last_op();
1184 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1186 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1187 CPURISCVState
*env
= cpu
->env_ptr
;
1188 uint16_t opcode16
= translator_lduw(env
, &ctx
->base
, ctx
->base
.pc_next
);
1192 decode_opc(env
, ctx
, opcode16
);
1193 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
1195 for (i
= ctx
->ntemp
- 1; i
>= 0; --i
) {
1196 tcg_temp_free(ctx
->temp
[i
]);
1197 ctx
->temp
[i
] = NULL
;
1200 for (i
= ctx
->nftemp
- 1; i
>= 0; --i
) {
1201 tcg_temp_free_i64(ctx
->ftemp
[i
]);
1202 ctx
->ftemp
[i
] = NULL
;
1206 /* Only the first insn within a TB is allowed to cross a page boundary. */
1207 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
1208 if (ctx
->itrigger
|| !is_same_page(&ctx
->base
, ctx
->base
.pc_next
)) {
1209 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1211 unsigned page_ofs
= ctx
->base
.pc_next
& ~TARGET_PAGE_MASK
;
1213 if (page_ofs
> TARGET_PAGE_SIZE
- MAX_INSN_LEN
) {
1214 uint16_t next_insn
= cpu_lduw_code(env
, ctx
->base
.pc_next
);
1215 int len
= insn_len(next_insn
);
1217 if (!is_same_page(&ctx
->base
, ctx
->base
.pc_next
+ len
)) {
1218 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1225 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1227 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1229 switch (ctx
->base
.is_jmp
) {
1230 case DISAS_TOO_MANY
:
1231 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1233 case DISAS_NORETURN
:
1236 g_assert_not_reached();
1240 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
,
1241 CPUState
*cpu
, FILE *logfile
)
1243 #ifndef CONFIG_USER_ONLY
1244 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
1245 CPURISCVState
*env
= &rvcpu
->env
;
1248 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1249 #ifndef CONFIG_USER_ONLY
1250 fprintf(logfile
, "Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n",
1251 env
->priv
, env
->virt
);
1253 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1256 static const TranslatorOps riscv_tr_ops
= {
1257 .init_disas_context
= riscv_tr_init_disas_context
,
1258 .tb_start
= riscv_tr_tb_start
,
1259 .insn_start
= riscv_tr_insn_start
,
1260 .translate_insn
= riscv_tr_translate_insn
,
1261 .tb_stop
= riscv_tr_tb_stop
,
1262 .disas_log
= riscv_tr_disas_log
,
1265 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
,
1266 target_ulong pc
, void *host_pc
)
1270 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &riscv_tr_ops
, &ctx
.base
);
1273 void riscv_translate_init(void)
1278 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1279 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1280 * unless you specifically block reads/writes to reg 0.
1285 for (i
= 1; i
< 32; i
++) {
1286 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
1287 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
1288 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
1289 offsetof(CPURISCVState
, gprh
[i
]), riscv_int_regnamesh
[i
]);
1292 for (i
= 0; i
< 32; i
++) {
1293 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
1294 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
1297 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
1298 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
1299 cpu_vstart
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vstart
),
1301 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
1303 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),
1305 /* Assign PM CSRs to tcg globals */
1306 pm_mask
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmmask
),
1308 pm_base
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmbase
),