2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
33 #include "internals.h"
35 /* global register indices */
36 static TCGv cpu_gpr
[32], cpu_gprh
[32], cpu_pc
, cpu_vl
, cpu_vstart
;
37 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
40 /* globals for PM CSRs */
44 #include "exec/gen-icount.h"
47 * If an operation is being performed on less than TARGET_LONG_BITS,
48 * it may require the inputs to be sign- or zero-extended; which will
49 * depend on the exact operation being performed.
57 typedef struct DisasContext
{
58 DisasContextBase base
;
59 /* pc_succ_insn points to the instruction following base.pc_next */
60 target_ulong pc_succ_insn
;
61 target_ulong priv_ver
;
62 RISCVMXL misa_mxl_max
;
68 uint32_t mstatus_hs_fs
;
69 uint32_t mstatus_hs_vs
;
71 /* Remember the rounding mode encoded in the previous fp instruction,
72 which we have already installed into env->fp_status. Or -1 for
73 no previous fp instruction. Note that we exit the TB when writing
74 to any system register, which includes CSR_FRM, so we do not have
75 to reset this known value. */
79 const RISCVCPUConfig
*cfg_ptr
;
81 /* vector extension */
84 * Encode LMUL to lmul as follows:
102 /* Space for 3 operands plus 1 extra for address computation. */
104 /* Space for 4 operands(1 dest and <=3 src) for float point computation */
107 /* PointerMasking extension */
108 bool pm_mask_enabled
;
109 bool pm_base_enabled
;
112 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
114 return ctx
->misa_ext
& ext
;
117 static bool always_true_p(DisasContext
*ctx
__attribute__((__unused__
)))
122 #define MATERIALISE_EXT_PREDICATE(ext) \
123 static bool has_ ## ext ## _p(DisasContext *ctx) \
125 return ctx->cfg_ptr->ext_ ## ext ; \
128 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
);
130 #ifdef TARGET_RISCV32
131 #define get_xl(ctx) MXL_RV32
132 #elif defined(CONFIG_USER_ONLY)
133 #define get_xl(ctx) MXL_RV64
135 #define get_xl(ctx) ((ctx)->xl)
138 /* The word size for this machine mode. */
139 static inline int __attribute__((unused
)) get_xlen(DisasContext
*ctx
)
141 return 16 << get_xl(ctx
);
144 /* The operation length, as opposed to the xlen. */
145 #ifdef TARGET_RISCV32
146 #define get_ol(ctx) MXL_RV32
148 #define get_ol(ctx) ((ctx)->ol)
151 static inline int get_olen(DisasContext
*ctx
)
153 return 16 << get_ol(ctx
);
156 /* The maximum register length */
157 #ifdef TARGET_RISCV32
158 #define get_xl_max(ctx) MXL_RV32
160 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
164 * RISC-V requires NaN-boxing of narrower width floating point values.
165 * This applies when a 32-bit value is assigned to a 64-bit FP register.
166 * For consistency and simplicity, we nanbox results even when the RVD
167 * extension is not present.
169 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
171 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
174 static void gen_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
176 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(16, 48));
180 * A narrow n-bit operation, where n < FLEN, checks that input operands
181 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
182 * If so, the least-significant bits of the input are used, otherwise the
183 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
185 * Here, the result is always nan-boxed, even the canonical nan.
187 static void gen_check_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
189 TCGv_i64 t_max
= tcg_const_i64(0xffffffffffff0000ull
);
190 TCGv_i64 t_nan
= tcg_const_i64(0xffffffffffff7e00ull
);
192 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
193 tcg_temp_free_i64(t_max
);
194 tcg_temp_free_i64(t_nan
);
197 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
199 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
200 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
202 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
205 static void gen_set_pc_imm(DisasContext
*ctx
, target_ulong dest
)
207 if (get_xl(ctx
) == MXL_RV32
) {
208 dest
= (int32_t)dest
;
210 tcg_gen_movi_tl(cpu_pc
, dest
);
213 static void gen_set_pc(DisasContext
*ctx
, TCGv dest
)
215 if (get_xl(ctx
) == MXL_RV32
) {
216 tcg_gen_ext32s_tl(cpu_pc
, dest
);
218 tcg_gen_mov_tl(cpu_pc
, dest
);
222 static void generate_exception(DisasContext
*ctx
, int excp
)
224 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
225 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
226 ctx
->base
.is_jmp
= DISAS_NORETURN
;
229 static void generate_exception_mtval(DisasContext
*ctx
, int excp
)
231 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
232 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
233 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
234 ctx
->base
.is_jmp
= DISAS_NORETURN
;
237 static void gen_exception_illegal(DisasContext
*ctx
)
239 tcg_gen_st_i32(tcg_constant_i32(ctx
->opcode
), cpu_env
,
240 offsetof(CPURISCVState
, bins
));
242 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
245 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
247 generate_exception_mtval(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
250 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
252 if (translator_use_goto_tb(&ctx
->base
, dest
)) {
254 gen_set_pc_imm(ctx
, dest
);
255 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
257 gen_set_pc_imm(ctx
, dest
);
258 tcg_gen_lookup_and_goto_ptr();
263 * Wrappers for getting reg values.
265 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
266 * constant zero as a source, and an uninitialized sink as destination.
268 * Further, we may provide an extension for word operations.
270 static TCGv
temp_new(DisasContext
*ctx
)
272 assert(ctx
->ntemp
< ARRAY_SIZE(ctx
->temp
));
273 return ctx
->temp
[ctx
->ntemp
++] = tcg_temp_new();
276 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
284 switch (get_ol(ctx
)) {
291 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
295 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
298 g_assert_not_reached();
305 g_assert_not_reached();
307 return cpu_gpr
[reg_num
];
310 static TCGv
get_gprh(DisasContext
*ctx
, int reg_num
)
312 assert(get_xl(ctx
) == MXL_RV128
);
316 return cpu_gprh
[reg_num
];
319 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
321 if (reg_num
== 0 || get_olen(ctx
) < TARGET_LONG_BITS
) {
322 return temp_new(ctx
);
324 return cpu_gpr
[reg_num
];
327 static TCGv
dest_gprh(DisasContext
*ctx
, int reg_num
)
330 return temp_new(ctx
);
332 return cpu_gprh
[reg_num
];
335 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
338 switch (get_ol(ctx
)) {
340 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
344 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
347 g_assert_not_reached();
350 if (get_xl_max(ctx
) == MXL_RV128
) {
351 tcg_gen_sari_tl(cpu_gprh
[reg_num
], cpu_gpr
[reg_num
], 63);
356 static void gen_set_gpri(DisasContext
*ctx
, int reg_num
, target_long imm
)
359 switch (get_ol(ctx
)) {
361 tcg_gen_movi_tl(cpu_gpr
[reg_num
], (int32_t)imm
);
365 tcg_gen_movi_tl(cpu_gpr
[reg_num
], imm
);
368 g_assert_not_reached();
371 if (get_xl_max(ctx
) == MXL_RV128
) {
372 tcg_gen_movi_tl(cpu_gprh
[reg_num
], -(imm
< 0));
377 static void gen_set_gpr128(DisasContext
*ctx
, int reg_num
, TCGv rl
, TCGv rh
)
379 assert(get_ol(ctx
) == MXL_RV128
);
381 tcg_gen_mov_tl(cpu_gpr
[reg_num
], rl
);
382 tcg_gen_mov_tl(cpu_gprh
[reg_num
], rh
);
386 static TCGv_i64
ftemp_new(DisasContext
*ctx
)
388 assert(ctx
->nftemp
< ARRAY_SIZE(ctx
->ftemp
));
389 return ctx
->ftemp
[ctx
->nftemp
++] = tcg_temp_new_i64();
392 static TCGv_i64
get_fpr_hs(DisasContext
*ctx
, int reg_num
)
394 if (!ctx
->cfg_ptr
->ext_zfinx
) {
395 return cpu_fpr
[reg_num
];
399 return tcg_constant_i64(0);
401 switch (get_xl(ctx
)) {
403 #ifdef TARGET_RISCV32
405 TCGv_i64 t
= ftemp_new(ctx
);
406 tcg_gen_ext_i32_i64(t
, cpu_gpr
[reg_num
]);
412 return cpu_gpr
[reg_num
];
415 g_assert_not_reached();
419 static TCGv_i64
get_fpr_d(DisasContext
*ctx
, int reg_num
)
421 if (!ctx
->cfg_ptr
->ext_zfinx
) {
422 return cpu_fpr
[reg_num
];
426 return tcg_constant_i64(0);
428 switch (get_xl(ctx
)) {
431 TCGv_i64 t
= ftemp_new(ctx
);
432 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1]);
435 #ifdef TARGET_RISCV64
437 return cpu_gpr
[reg_num
];
440 g_assert_not_reached();
444 static TCGv_i64
dest_fpr(DisasContext
*ctx
, int reg_num
)
446 if (!ctx
->cfg_ptr
->ext_zfinx
) {
447 return cpu_fpr
[reg_num
];
451 return ftemp_new(ctx
);
454 switch (get_xl(ctx
)) {
456 return ftemp_new(ctx
);
457 #ifdef TARGET_RISCV64
459 return cpu_gpr
[reg_num
];
462 g_assert_not_reached();
466 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
467 static void gen_set_fpr_hs(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
469 if (!ctx
->cfg_ptr
->ext_zfinx
) {
470 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
474 switch (get_xl(ctx
)) {
476 #ifdef TARGET_RISCV32
477 tcg_gen_extrl_i64_i32(cpu_gpr
[reg_num
], t
);
482 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
486 g_assert_not_reached();
491 static void gen_set_fpr_d(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
493 if (!ctx
->cfg_ptr
->ext_zfinx
) {
494 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
499 switch (get_xl(ctx
)) {
501 #ifdef TARGET_RISCV32
502 tcg_gen_extr_i64_i32(cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1], t
);
505 tcg_gen_ext32s_i64(cpu_gpr
[reg_num
], t
);
506 tcg_gen_sari_i64(cpu_gpr
[reg_num
+ 1], t
, 32);
509 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
513 g_assert_not_reached();
518 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
520 target_ulong next_pc
;
522 /* check misaligned: */
523 next_pc
= ctx
->base
.pc_next
+ imm
;
524 if (!has_ext(ctx
, RVC
)) {
525 if ((next_pc
& 0x3) != 0) {
526 gen_exception_inst_addr_mis(ctx
);
531 gen_set_gpri(ctx
, rd
, ctx
->pc_succ_insn
);
532 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
533 ctx
->base
.is_jmp
= DISAS_NORETURN
;
536 /* Compute a canonical address from a register plus offset. */
537 static TCGv
get_address(DisasContext
*ctx
, int rs1
, int imm
)
539 TCGv addr
= temp_new(ctx
);
540 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
542 tcg_gen_addi_tl(addr
, src1
, imm
);
543 if (ctx
->pm_mask_enabled
) {
544 tcg_gen_and_tl(addr
, addr
, pm_mask
);
545 } else if (get_xl(ctx
) == MXL_RV32
) {
546 tcg_gen_ext32u_tl(addr
, addr
);
548 if (ctx
->pm_base_enabled
) {
549 tcg_gen_or_tl(addr
, addr
, pm_base
);
554 #ifndef CONFIG_USER_ONLY
555 /* The states of mstatus_fs are:
556 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
557 * We will have already diagnosed disabled state,
558 * and need to turn initial/clean into dirty.
560 static void mark_fs_dirty(DisasContext
*ctx
)
564 if (!has_ext(ctx
, RVF
)) {
568 if (ctx
->mstatus_fs
!= MSTATUS_FS
) {
569 /* Remember the state change for the rest of the TB. */
570 ctx
->mstatus_fs
= MSTATUS_FS
;
572 tmp
= tcg_temp_new();
573 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
574 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
575 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
579 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_fs
!= MSTATUS_FS
) {
580 /* Remember the stage change for the rest of the TB. */
581 ctx
->mstatus_hs_fs
= MSTATUS_FS
;
583 tmp
= tcg_temp_new();
584 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
585 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
586 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
591 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
594 #ifndef CONFIG_USER_ONLY
595 /* The states of mstatus_vs are:
596 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
597 * We will have already diagnosed disabled state,
598 * and need to turn initial/clean into dirty.
600 static void mark_vs_dirty(DisasContext
*ctx
)
604 if (ctx
->mstatus_vs
!= MSTATUS_VS
) {
605 /* Remember the state change for the rest of the TB. */
606 ctx
->mstatus_vs
= MSTATUS_VS
;
608 tmp
= tcg_temp_new();
609 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
610 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
611 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
615 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_vs
!= MSTATUS_VS
) {
616 /* Remember the stage change for the rest of the TB. */
617 ctx
->mstatus_hs_vs
= MSTATUS_VS
;
619 tmp
= tcg_temp_new();
620 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
621 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
622 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
627 static inline void mark_vs_dirty(DisasContext
*ctx
) { }
630 static void gen_set_rm(DisasContext
*ctx
, int rm
)
632 if (ctx
->frm
== rm
) {
637 if (rm
== RISCV_FRM_ROD
) {
638 gen_helper_set_rod_rounding_mode(cpu_env
);
642 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
645 static int ex_plus_1(DisasContext
*ctx
, int nf
)
650 #define EX_SH(amount) \
651 static int ex_shift_##amount(DisasContext *ctx, int imm) \
653 return imm << amount; \
661 #define REQUIRE_EXT(ctx, ext) do { \
662 if (!has_ext(ctx, ext)) { \
667 #define REQUIRE_32BIT(ctx) do { \
668 if (get_xl(ctx) != MXL_RV32) { \
673 #define REQUIRE_64BIT(ctx) do { \
674 if (get_xl(ctx) != MXL_RV64) { \
679 #define REQUIRE_128BIT(ctx) do { \
680 if (get_xl(ctx) != MXL_RV128) { \
685 #define REQUIRE_64_OR_128BIT(ctx) do { \
686 if (get_xl(ctx) == MXL_RV32) { \
691 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
696 static int ex_rvc_shifti(DisasContext
*ctx
, int imm
)
698 /* For RV128 a shamt of 0 means a shift by 64. */
699 return imm
? imm
: 64;
702 /* Include the auto-generated decoder for 32 bit insn */
703 #include "decode-insn32.c.inc"
705 static bool gen_logic_imm_fn(DisasContext
*ctx
, arg_i
*a
,
706 void (*func
)(TCGv
, TCGv
, target_long
))
708 TCGv dest
= dest_gpr(ctx
, a
->rd
);
709 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
711 func(dest
, src1
, a
->imm
);
713 if (get_xl(ctx
) == MXL_RV128
) {
714 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
715 TCGv desth
= dest_gprh(ctx
, a
->rd
);
717 func(desth
, src1h
, -(a
->imm
< 0));
718 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
720 gen_set_gpr(ctx
, a
->rd
, dest
);
726 static bool gen_logic(DisasContext
*ctx
, arg_r
*a
,
727 void (*func
)(TCGv
, TCGv
, TCGv
))
729 TCGv dest
= dest_gpr(ctx
, a
->rd
);
730 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
731 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
733 func(dest
, src1
, src2
);
735 if (get_xl(ctx
) == MXL_RV128
) {
736 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
737 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
738 TCGv desth
= dest_gprh(ctx
, a
->rd
);
740 func(desth
, src1h
, src2h
);
741 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
743 gen_set_gpr(ctx
, a
->rd
, dest
);
749 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
750 void (*func
)(TCGv
, TCGv
, target_long
),
751 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
753 TCGv dest
= dest_gpr(ctx
, a
->rd
);
754 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
756 if (get_ol(ctx
) < MXL_RV128
) {
757 func(dest
, src1
, a
->imm
);
758 gen_set_gpr(ctx
, a
->rd
, dest
);
764 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
765 TCGv desth
= dest_gprh(ctx
, a
->rd
);
767 f128(dest
, desth
, src1
, src1h
, a
->imm
);
768 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
773 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
774 void (*func
)(TCGv
, TCGv
, TCGv
),
775 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
777 TCGv dest
= dest_gpr(ctx
, a
->rd
);
778 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
779 TCGv src2
= tcg_constant_tl(a
->imm
);
781 if (get_ol(ctx
) < MXL_RV128
) {
782 func(dest
, src1
, src2
);
783 gen_set_gpr(ctx
, a
->rd
, dest
);
789 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
790 TCGv src2h
= tcg_constant_tl(-(a
->imm
< 0));
791 TCGv desth
= dest_gprh(ctx
, a
->rd
);
793 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
794 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
799 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
800 void (*func
)(TCGv
, TCGv
, TCGv
),
801 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
803 TCGv dest
= dest_gpr(ctx
, a
->rd
);
804 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
805 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
807 if (get_ol(ctx
) < MXL_RV128
) {
808 func(dest
, src1
, src2
);
809 gen_set_gpr(ctx
, a
->rd
, dest
);
815 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
816 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
817 TCGv desth
= dest_gprh(ctx
, a
->rd
);
819 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
820 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
825 static bool gen_arith_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
826 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
827 void (*f_32
)(TCGv
, TCGv
, TCGv
),
828 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
830 int olen
= get_olen(ctx
);
832 if (olen
!= TARGET_LONG_BITS
) {
835 } else if (olen
!= 128) {
836 g_assert_not_reached();
839 return gen_arith(ctx
, a
, ext
, f_tl
, f_128
);
842 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
843 void (*func
)(TCGv
, TCGv
, target_long
),
844 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
847 int max_len
= get_olen(ctx
);
849 if (a
->shamt
>= max_len
) {
853 dest
= dest_gpr(ctx
, a
->rd
);
854 src1
= get_gpr(ctx
, a
->rs1
, ext
);
857 func(dest
, src1
, a
->shamt
);
858 gen_set_gpr(ctx
, a
->rd
, dest
);
860 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
861 TCGv desth
= dest_gprh(ctx
, a
->rd
);
866 f128(dest
, desth
, src1
, src1h
, a
->shamt
);
867 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
872 static bool gen_shift_imm_fn_per_ol(DisasContext
*ctx
, arg_shift
*a
,
874 void (*f_tl
)(TCGv
, TCGv
, target_long
),
875 void (*f_32
)(TCGv
, TCGv
, target_long
),
876 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
,
879 int olen
= get_olen(ctx
);
880 if (olen
!= TARGET_LONG_BITS
) {
883 } else if (olen
!= 128) {
884 g_assert_not_reached();
887 return gen_shift_imm_fn(ctx
, a
, ext
, f_tl
, f_128
);
890 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
891 void (*func
)(TCGv
, TCGv
, TCGv
))
893 TCGv dest
, src1
, src2
;
894 int max_len
= get_olen(ctx
);
896 if (a
->shamt
>= max_len
) {
900 dest
= dest_gpr(ctx
, a
->rd
);
901 src1
= get_gpr(ctx
, a
->rs1
, ext
);
902 src2
= tcg_constant_tl(a
->shamt
);
904 func(dest
, src1
, src2
);
906 gen_set_gpr(ctx
, a
->rd
, dest
);
910 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
911 void (*func
)(TCGv
, TCGv
, TCGv
),
912 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
914 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
915 TCGv ext2
= tcg_temp_new();
916 int max_len
= get_olen(ctx
);
918 tcg_gen_andi_tl(ext2
, src2
, max_len
- 1);
920 TCGv dest
= dest_gpr(ctx
, a
->rd
);
921 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
924 func(dest
, src1
, ext2
);
925 gen_set_gpr(ctx
, a
->rd
, dest
);
927 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
928 TCGv desth
= dest_gprh(ctx
, a
->rd
);
933 f128(dest
, desth
, src1
, src1h
, ext2
);
934 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
940 static bool gen_shift_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
941 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
942 void (*f_32
)(TCGv
, TCGv
, TCGv
),
943 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
945 int olen
= get_olen(ctx
);
946 if (olen
!= TARGET_LONG_BITS
) {
949 } else if (olen
!= 128) {
950 g_assert_not_reached();
953 return gen_shift(ctx
, a
, ext
, f_tl
, f_128
);
956 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
957 void (*func
)(TCGv
, TCGv
))
959 TCGv dest
= dest_gpr(ctx
, a
->rd
);
960 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
964 gen_set_gpr(ctx
, a
->rd
, dest
);
968 static bool gen_unary_per_ol(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
969 void (*f_tl
)(TCGv
, TCGv
),
970 void (*f_32
)(TCGv
, TCGv
))
972 int olen
= get_olen(ctx
);
974 if (olen
!= TARGET_LONG_BITS
) {
978 g_assert_not_reached();
981 return gen_unary(ctx
, a
, ext
, f_tl
);
984 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
986 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
987 CPUState
*cpu
= ctx
->cs
;
988 CPURISCVState
*env
= cpu
->env_ptr
;
990 return cpu_ldl_code(env
, pc
);
993 /* Include insn module translation function */
994 #include "insn_trans/trans_rvi.c.inc"
995 #include "insn_trans/trans_rvm.c.inc"
996 #include "insn_trans/trans_rva.c.inc"
997 #include "insn_trans/trans_rvf.c.inc"
998 #include "insn_trans/trans_rvd.c.inc"
999 #include "insn_trans/trans_rvh.c.inc"
1000 #include "insn_trans/trans_rvv.c.inc"
1001 #include "insn_trans/trans_rvb.c.inc"
1002 #include "insn_trans/trans_rvzfh.c.inc"
1003 #include "insn_trans/trans_privileged.c.inc"
1004 #include "insn_trans/trans_svinval.c.inc"
1005 #include "insn_trans/trans_xventanacondops.c.inc"
1007 /* Include the auto-generated decoder for 16 bit insn */
1008 #include "decode-insn16.c.inc"
1009 /* Include decoders for factored-out extensions */
1010 #include "decode-XVentanaCondOps.c.inc"
1012 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
1015 * A table with predicate (i.e., guard) functions and decoder functions
1016 * that are tested in-order until a decoder matches onto the opcode.
1018 static const struct {
1019 bool (*guard_func
)(DisasContext
*);
1020 bool (*decode_func
)(DisasContext
*, uint32_t);
1022 { always_true_p
, decode_insn32
},
1023 { has_XVentanaCondOps_p
, decode_XVentanaCodeOps
},
1026 /* Check for compressed insn */
1027 if (extract16(opcode
, 0, 2) != 3) {
1028 if (!has_ext(ctx
, RVC
)) {
1029 gen_exception_illegal(ctx
);
1031 ctx
->opcode
= opcode
;
1032 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
1033 if (decode_insn16(ctx
, opcode
)) {
1038 uint32_t opcode32
= opcode
;
1039 opcode32
= deposit32(opcode32
, 16, 16,
1040 translator_lduw(env
, &ctx
->base
,
1041 ctx
->base
.pc_next
+ 2));
1042 ctx
->opcode
= opcode32
;
1043 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
1045 for (size_t i
= 0; i
< ARRAY_SIZE(decoders
); ++i
) {
1046 if (decoders
[i
].guard_func(ctx
) &&
1047 decoders
[i
].decode_func(ctx
, opcode32
)) {
1053 gen_exception_illegal(ctx
);
1056 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
1058 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1059 CPURISCVState
*env
= cs
->env_ptr
;
1060 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1061 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
1063 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
1064 ctx
->mem_idx
= FIELD_EX32(tb_flags
, TB_FLAGS
, MEM_IDX
);
1065 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
1066 ctx
->mstatus_vs
= tb_flags
& TB_FLAGS_MSTATUS_VS
;
1067 ctx
->priv_ver
= env
->priv_ver
;
1068 #if !defined(CONFIG_USER_ONLY)
1069 if (riscv_has_ext(env
, RVH
)) {
1070 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
1072 ctx
->virt_enabled
= false;
1075 ctx
->virt_enabled
= false;
1077 ctx
->misa_ext
= env
->misa_ext
;
1078 ctx
->frm
= -1; /* unknown rounding mode */
1079 ctx
->cfg_ptr
= &(cpu
->cfg
);
1080 ctx
->mstatus_hs_fs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_FS
);
1081 ctx
->mstatus_hs_vs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_VS
);
1082 ctx
->hlsx
= FIELD_EX32(tb_flags
, TB_FLAGS
, HLSX
);
1083 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
1084 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
1085 ctx
->lmul
= sextract32(FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
), 0, 3);
1086 ctx
->vstart
= env
->vstart
;
1087 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
1088 ctx
->misa_mxl_max
= env
->misa_mxl_max
;
1089 ctx
->xl
= FIELD_EX32(tb_flags
, TB_FLAGS
, XL
);
1092 memset(ctx
->temp
, 0, sizeof(ctx
->temp
));
1094 memset(ctx
->ftemp
, 0, sizeof(ctx
->ftemp
));
1095 ctx
->pm_mask_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_MASK_ENABLED
);
1096 ctx
->pm_base_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_BASE_ENABLED
);
1097 ctx
->zero
= tcg_constant_tl(0);
1100 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
1104 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1106 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1108 tcg_gen_insn_start(ctx
->base
.pc_next
);
1111 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1113 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1114 CPURISCVState
*env
= cpu
->env_ptr
;
1115 uint16_t opcode16
= translator_lduw(env
, &ctx
->base
, ctx
->base
.pc_next
);
1119 decode_opc(env
, ctx
, opcode16
);
1120 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
1122 for (i
= ctx
->ntemp
- 1; i
>= 0; --i
) {
1123 tcg_temp_free(ctx
->temp
[i
]);
1124 ctx
->temp
[i
] = NULL
;
1127 for (i
= ctx
->nftemp
- 1; i
>= 0; --i
) {
1128 tcg_temp_free_i64(ctx
->ftemp
[i
]);
1129 ctx
->ftemp
[i
] = NULL
;
1133 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
1134 target_ulong page_start
;
1136 page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
1137 if (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
) {
1138 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1143 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1145 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1147 switch (ctx
->base
.is_jmp
) {
1148 case DISAS_TOO_MANY
:
1149 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1151 case DISAS_NORETURN
:
1154 g_assert_not_reached();
1158 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
1160 #ifndef CONFIG_USER_ONLY
1161 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
1162 CPURISCVState
*env
= &rvcpu
->env
;
1165 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1166 #ifndef CONFIG_USER_ONLY
1167 qemu_log("Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n", env
->priv
, env
->virt
);
1169 log_target_disas(cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1172 static const TranslatorOps riscv_tr_ops
= {
1173 .init_disas_context
= riscv_tr_init_disas_context
,
1174 .tb_start
= riscv_tr_tb_start
,
1175 .insn_start
= riscv_tr_insn_start
,
1176 .translate_insn
= riscv_tr_translate_insn
,
1177 .tb_stop
= riscv_tr_tb_stop
,
1178 .disas_log
= riscv_tr_disas_log
,
1181 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
1185 translator_loop(&riscv_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
1188 void riscv_translate_init(void)
1193 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1194 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1195 * unless you specifically block reads/writes to reg 0.
1200 for (i
= 1; i
< 32; i
++) {
1201 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
1202 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
1203 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
1204 offsetof(CPURISCVState
, gprh
[i
]), riscv_int_regnamesh
[i
]);
1207 for (i
= 0; i
< 32; i
++) {
1208 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
1209 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
1212 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
1213 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
1214 cpu_vstart
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vstart
),
1216 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
1218 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),
1220 /* Assign PM CSRs to tcg globals */
1221 pm_mask
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmmask
),
1223 pm_base
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmbase
),