2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
31 #include "semihosting/semihost.h"
34 #include "internals.h"
36 /* global register indices */
37 static TCGv cpu_gpr
[32], cpu_gprh
[32], cpu_pc
, cpu_vl
, cpu_vstart
;
38 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
41 /* globals for PM CSRs */
45 #include "exec/gen-icount.h"
48 * If an operation is being performed on less than TARGET_LONG_BITS,
49 * it may require the inputs to be sign- or zero-extended; which will
50 * depend on the exact operation being performed.
58 typedef struct DisasContext
{
59 DisasContextBase base
;
60 /* pc_succ_insn points to the instruction following base.pc_next */
61 target_ulong pc_succ_insn
;
62 target_ulong priv_ver
;
63 RISCVMXL misa_mxl_max
;
69 uint32_t mstatus_hs_fs
;
70 uint32_t mstatus_hs_vs
;
72 /* Remember the rounding mode encoded in the previous fp instruction,
73 which we have already installed into env->fp_status. Or -1 for
74 no previous fp instruction. Note that we exit the TB when writing
75 to any system register, which includes CSR_FRM, so we do not have
76 to reset this known value. */
81 const RISCVCPUConfig
*cfg_ptr
;
83 /* vector extension */
86 * Encode LMUL to lmul as follows:
107 /* Space for 3 operands plus 1 extra for address computation. */
109 /* Space for 4 operands(1 dest and <=3 src) for float point computation */
112 /* PointerMasking extension */
113 bool pm_mask_enabled
;
114 bool pm_base_enabled
;
115 /* Use icount trigger for native debug */
117 /* FRM is known to contain a valid value. */
119 /* TCG of the current insn_start */
123 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
125 return ctx
->misa_ext
& ext
;
128 static bool always_true_p(DisasContext
*ctx
__attribute__((__unused__
)))
133 static bool has_xthead_p(DisasContext
*ctx
__attribute__((__unused__
)))
135 return ctx
->cfg_ptr
->ext_xtheadba
|| ctx
->cfg_ptr
->ext_xtheadbb
||
136 ctx
->cfg_ptr
->ext_xtheadbs
|| ctx
->cfg_ptr
->ext_xtheadcmo
||
137 ctx
->cfg_ptr
->ext_xtheadcondmov
||
138 ctx
->cfg_ptr
->ext_xtheadfmemidx
|| ctx
->cfg_ptr
->ext_xtheadfmv
||
139 ctx
->cfg_ptr
->ext_xtheadmac
|| ctx
->cfg_ptr
->ext_xtheadmemidx
||
140 ctx
->cfg_ptr
->ext_xtheadmempair
|| ctx
->cfg_ptr
->ext_xtheadsync
;
143 #define MATERIALISE_EXT_PREDICATE(ext) \
144 static bool has_ ## ext ## _p(DisasContext *ctx) \
146 return ctx->cfg_ptr->ext_ ## ext ; \
149 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
);
151 #ifdef TARGET_RISCV32
152 #define get_xl(ctx) MXL_RV32
153 #elif defined(CONFIG_USER_ONLY)
154 #define get_xl(ctx) MXL_RV64
156 #define get_xl(ctx) ((ctx)->xl)
159 /* The word size for this machine mode. */
160 static inline int __attribute__((unused
)) get_xlen(DisasContext
*ctx
)
162 return 16 << get_xl(ctx
);
165 /* The operation length, as opposed to the xlen. */
166 #ifdef TARGET_RISCV32
167 #define get_ol(ctx) MXL_RV32
169 #define get_ol(ctx) ((ctx)->ol)
172 static inline int get_olen(DisasContext
*ctx
)
174 return 16 << get_ol(ctx
);
177 /* The maximum register length */
178 #ifdef TARGET_RISCV32
179 #define get_xl_max(ctx) MXL_RV32
181 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
185 * RISC-V requires NaN-boxing of narrower width floating point values.
186 * This applies when a 32-bit value is assigned to a 64-bit FP register.
187 * For consistency and simplicity, we nanbox results even when the RVD
188 * extension is not present.
190 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
192 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
195 static void gen_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
197 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(16, 48));
201 * A narrow n-bit operation, where n < FLEN, checks that input operands
202 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
203 * If so, the least-significant bits of the input are used, otherwise the
204 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
206 * Here, the result is always nan-boxed, even the canonical nan.
208 static void gen_check_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
210 TCGv_i64 t_max
= tcg_const_i64(0xffffffffffff0000ull
);
211 TCGv_i64 t_nan
= tcg_const_i64(0xffffffffffff7e00ull
);
213 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
214 tcg_temp_free_i64(t_max
);
215 tcg_temp_free_i64(t_nan
);
218 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
220 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
221 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
223 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
226 static void decode_save_opc(DisasContext
*ctx
)
228 assert(ctx
->insn_start
!= NULL
);
229 tcg_set_insn_start_param(ctx
->insn_start
, 1, ctx
->opcode
);
230 ctx
->insn_start
= NULL
;
233 static void gen_set_pc_imm(DisasContext
*ctx
, target_ulong dest
)
235 if (get_xl(ctx
) == MXL_RV32
) {
236 dest
= (int32_t)dest
;
238 tcg_gen_movi_tl(cpu_pc
, dest
);
241 static void gen_set_pc(DisasContext
*ctx
, TCGv dest
)
243 if (get_xl(ctx
) == MXL_RV32
) {
244 tcg_gen_ext32s_tl(cpu_pc
, dest
);
246 tcg_gen_mov_tl(cpu_pc
, dest
);
250 static void generate_exception(DisasContext
*ctx
, int excp
)
252 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
253 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
254 ctx
->base
.is_jmp
= DISAS_NORETURN
;
257 static void gen_exception_illegal(DisasContext
*ctx
)
259 tcg_gen_st_i32(tcg_constant_i32(ctx
->opcode
), cpu_env
,
260 offsetof(CPURISCVState
, bins
));
261 if (ctx
->virt_inst_excp
) {
262 generate_exception(ctx
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
);
264 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
268 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
270 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
271 generate_exception(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
274 static void lookup_and_goto_ptr(DisasContext
*ctx
)
276 #ifndef CONFIG_USER_ONLY
278 gen_helper_itrigger_match(cpu_env
);
281 tcg_gen_lookup_and_goto_ptr();
284 static void exit_tb(DisasContext
*ctx
)
286 #ifndef CONFIG_USER_ONLY
288 gen_helper_itrigger_match(cpu_env
);
291 tcg_gen_exit_tb(NULL
, 0);
294 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
297 * Under itrigger, instruction executes one by one like singlestep,
298 * direct block chain benefits will be small.
300 if (translator_use_goto_tb(&ctx
->base
, dest
) && !ctx
->itrigger
) {
302 gen_set_pc_imm(ctx
, dest
);
303 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
305 gen_set_pc_imm(ctx
, dest
);
306 lookup_and_goto_ptr(ctx
);
311 * Wrappers for getting reg values.
313 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
314 * constant zero as a source, and an uninitialized sink as destination.
316 * Further, we may provide an extension for word operations.
318 static TCGv
temp_new(DisasContext
*ctx
)
320 assert(ctx
->ntemp
< ARRAY_SIZE(ctx
->temp
));
321 return ctx
->temp
[ctx
->ntemp
++] = tcg_temp_new();
324 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
332 switch (get_ol(ctx
)) {
339 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
343 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
346 g_assert_not_reached();
353 g_assert_not_reached();
355 return cpu_gpr
[reg_num
];
358 static TCGv
get_gprh(DisasContext
*ctx
, int reg_num
)
360 assert(get_xl(ctx
) == MXL_RV128
);
364 return cpu_gprh
[reg_num
];
367 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
369 if (reg_num
== 0 || get_olen(ctx
) < TARGET_LONG_BITS
) {
370 return temp_new(ctx
);
372 return cpu_gpr
[reg_num
];
375 static TCGv
dest_gprh(DisasContext
*ctx
, int reg_num
)
378 return temp_new(ctx
);
380 return cpu_gprh
[reg_num
];
383 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
386 switch (get_ol(ctx
)) {
388 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
392 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
395 g_assert_not_reached();
398 if (get_xl_max(ctx
) == MXL_RV128
) {
399 tcg_gen_sari_tl(cpu_gprh
[reg_num
], cpu_gpr
[reg_num
], 63);
404 static void gen_set_gpri(DisasContext
*ctx
, int reg_num
, target_long imm
)
407 switch (get_ol(ctx
)) {
409 tcg_gen_movi_tl(cpu_gpr
[reg_num
], (int32_t)imm
);
413 tcg_gen_movi_tl(cpu_gpr
[reg_num
], imm
);
416 g_assert_not_reached();
419 if (get_xl_max(ctx
) == MXL_RV128
) {
420 tcg_gen_movi_tl(cpu_gprh
[reg_num
], -(imm
< 0));
425 static void gen_set_gpr128(DisasContext
*ctx
, int reg_num
, TCGv rl
, TCGv rh
)
427 assert(get_ol(ctx
) == MXL_RV128
);
429 tcg_gen_mov_tl(cpu_gpr
[reg_num
], rl
);
430 tcg_gen_mov_tl(cpu_gprh
[reg_num
], rh
);
434 static TCGv_i64
ftemp_new(DisasContext
*ctx
)
436 assert(ctx
->nftemp
< ARRAY_SIZE(ctx
->ftemp
));
437 return ctx
->ftemp
[ctx
->nftemp
++] = tcg_temp_new_i64();
440 static TCGv_i64
get_fpr_hs(DisasContext
*ctx
, int reg_num
)
442 if (!ctx
->cfg_ptr
->ext_zfinx
) {
443 return cpu_fpr
[reg_num
];
447 return tcg_constant_i64(0);
449 switch (get_xl(ctx
)) {
451 #ifdef TARGET_RISCV32
453 TCGv_i64 t
= ftemp_new(ctx
);
454 tcg_gen_ext_i32_i64(t
, cpu_gpr
[reg_num
]);
460 return cpu_gpr
[reg_num
];
463 g_assert_not_reached();
467 static TCGv_i64
get_fpr_d(DisasContext
*ctx
, int reg_num
)
469 if (!ctx
->cfg_ptr
->ext_zfinx
) {
470 return cpu_fpr
[reg_num
];
474 return tcg_constant_i64(0);
476 switch (get_xl(ctx
)) {
479 TCGv_i64 t
= ftemp_new(ctx
);
480 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1]);
483 #ifdef TARGET_RISCV64
485 return cpu_gpr
[reg_num
];
488 g_assert_not_reached();
492 static TCGv_i64
dest_fpr(DisasContext
*ctx
, int reg_num
)
494 if (!ctx
->cfg_ptr
->ext_zfinx
) {
495 return cpu_fpr
[reg_num
];
499 return ftemp_new(ctx
);
502 switch (get_xl(ctx
)) {
504 return ftemp_new(ctx
);
505 #ifdef TARGET_RISCV64
507 return cpu_gpr
[reg_num
];
510 g_assert_not_reached();
514 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
515 static void gen_set_fpr_hs(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
517 if (!ctx
->cfg_ptr
->ext_zfinx
) {
518 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
522 switch (get_xl(ctx
)) {
524 #ifdef TARGET_RISCV32
525 tcg_gen_extrl_i64_i32(cpu_gpr
[reg_num
], t
);
530 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
534 g_assert_not_reached();
539 static void gen_set_fpr_d(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
541 if (!ctx
->cfg_ptr
->ext_zfinx
) {
542 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
547 switch (get_xl(ctx
)) {
549 #ifdef TARGET_RISCV32
550 tcg_gen_extr_i64_i32(cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1], t
);
553 tcg_gen_ext32s_i64(cpu_gpr
[reg_num
], t
);
554 tcg_gen_sari_i64(cpu_gpr
[reg_num
+ 1], t
, 32);
557 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
561 g_assert_not_reached();
566 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
568 target_ulong next_pc
;
570 /* check misaligned: */
571 next_pc
= ctx
->base
.pc_next
+ imm
;
572 if (!has_ext(ctx
, RVC
)) {
573 if ((next_pc
& 0x3) != 0) {
574 gen_exception_inst_addr_mis(ctx
);
579 gen_set_gpri(ctx
, rd
, ctx
->pc_succ_insn
);
580 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
581 ctx
->base
.is_jmp
= DISAS_NORETURN
;
584 /* Compute a canonical address from a register plus offset. */
585 static TCGv
get_address(DisasContext
*ctx
, int rs1
, int imm
)
587 TCGv addr
= temp_new(ctx
);
588 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
590 tcg_gen_addi_tl(addr
, src1
, imm
);
591 if (ctx
->pm_mask_enabled
) {
592 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
593 } else if (get_xl(ctx
) == MXL_RV32
) {
594 tcg_gen_ext32u_tl(addr
, addr
);
596 if (ctx
->pm_base_enabled
) {
597 tcg_gen_or_tl(addr
, addr
, pm_base
);
602 /* Compute a canonical address from a register plus reg offset. */
603 static TCGv
get_address_indexed(DisasContext
*ctx
, int rs1
, TCGv offs
)
605 TCGv addr
= temp_new(ctx
);
606 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
608 tcg_gen_add_tl(addr
, src1
, offs
);
609 if (ctx
->pm_mask_enabled
) {
610 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
611 } else if (get_xl(ctx
) == MXL_RV32
) {
612 tcg_gen_ext32u_tl(addr
, addr
);
614 if (ctx
->pm_base_enabled
) {
615 tcg_gen_or_tl(addr
, addr
, pm_base
);
620 #ifndef CONFIG_USER_ONLY
621 /* The states of mstatus_fs are:
622 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
623 * We will have already diagnosed disabled state,
624 * and need to turn initial/clean into dirty.
626 static void mark_fs_dirty(DisasContext
*ctx
)
630 if (!has_ext(ctx
, RVF
)) {
634 if (ctx
->mstatus_fs
!= MSTATUS_FS
) {
635 /* Remember the state change for the rest of the TB. */
636 ctx
->mstatus_fs
= MSTATUS_FS
;
638 tmp
= tcg_temp_new();
639 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
640 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
641 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
645 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_fs
!= MSTATUS_FS
) {
646 /* Remember the stage change for the rest of the TB. */
647 ctx
->mstatus_hs_fs
= MSTATUS_FS
;
649 tmp
= tcg_temp_new();
650 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
651 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
652 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
657 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
660 #ifndef CONFIG_USER_ONLY
661 /* The states of mstatus_vs are:
662 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
663 * We will have already diagnosed disabled state,
664 * and need to turn initial/clean into dirty.
666 static void mark_vs_dirty(DisasContext
*ctx
)
670 if (ctx
->mstatus_vs
!= MSTATUS_VS
) {
671 /* Remember the state change for the rest of the TB. */
672 ctx
->mstatus_vs
= MSTATUS_VS
;
674 tmp
= tcg_temp_new();
675 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
676 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
677 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
681 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_vs
!= MSTATUS_VS
) {
682 /* Remember the stage change for the rest of the TB. */
683 ctx
->mstatus_hs_vs
= MSTATUS_VS
;
685 tmp
= tcg_temp_new();
686 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
687 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
688 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
693 static inline void mark_vs_dirty(DisasContext
*ctx
) { }
696 static void gen_set_rm(DisasContext
*ctx
, int rm
)
698 if (ctx
->frm
== rm
) {
703 if (rm
== RISCV_FRM_DYN
) {
704 /* The helper will return only if frm valid. */
705 ctx
->frm_valid
= true;
708 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
709 decode_save_opc(ctx
);
710 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
713 static void gen_set_rm_chkfrm(DisasContext
*ctx
, int rm
)
715 if (ctx
->frm
== rm
&& ctx
->frm_valid
) {
719 ctx
->frm_valid
= true;
721 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
722 decode_save_opc(ctx
);
723 gen_helper_set_rounding_mode_chkfrm(cpu_env
, tcg_constant_i32(rm
));
726 static int ex_plus_1(DisasContext
*ctx
, int nf
)
731 #define EX_SH(amount) \
732 static int ex_shift_##amount(DisasContext *ctx, int imm) \
734 return imm << amount; \
742 #define REQUIRE_EXT(ctx, ext) do { \
743 if (!has_ext(ctx, ext)) { \
748 #define REQUIRE_32BIT(ctx) do { \
749 if (get_xl(ctx) != MXL_RV32) { \
754 #define REQUIRE_64BIT(ctx) do { \
755 if (get_xl(ctx) != MXL_RV64) { \
760 #define REQUIRE_128BIT(ctx) do { \
761 if (get_xl(ctx) != MXL_RV128) { \
766 #define REQUIRE_64_OR_128BIT(ctx) do { \
767 if (get_xl(ctx) == MXL_RV32) { \
772 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \
773 if (!ctx->cfg_ptr->ext_##A && \
774 !ctx->cfg_ptr->ext_##B) { \
779 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
784 static int ex_rvc_shiftli(DisasContext
*ctx
, int imm
)
786 /* For RV128 a shamt of 0 means a shift by 64. */
787 if (get_ol(ctx
) == MXL_RV128
) {
788 imm
= imm
? imm
: 64;
793 static int ex_rvc_shiftri(DisasContext
*ctx
, int imm
)
796 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right
797 * shifts, the shamt is sign-extended.
799 if (get_ol(ctx
) == MXL_RV128
) {
800 imm
= imm
| (imm
& 32) << 1;
801 imm
= imm
? imm
: 64;
806 /* Include the auto-generated decoder for 32 bit insn */
807 #include "decode-insn32.c.inc"
809 static bool gen_logic_imm_fn(DisasContext
*ctx
, arg_i
*a
,
810 void (*func
)(TCGv
, TCGv
, target_long
))
812 TCGv dest
= dest_gpr(ctx
, a
->rd
);
813 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
815 func(dest
, src1
, a
->imm
);
817 if (get_xl(ctx
) == MXL_RV128
) {
818 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
819 TCGv desth
= dest_gprh(ctx
, a
->rd
);
821 func(desth
, src1h
, -(a
->imm
< 0));
822 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
824 gen_set_gpr(ctx
, a
->rd
, dest
);
830 static bool gen_logic(DisasContext
*ctx
, arg_r
*a
,
831 void (*func
)(TCGv
, TCGv
, TCGv
))
833 TCGv dest
= dest_gpr(ctx
, a
->rd
);
834 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
835 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
837 func(dest
, src1
, src2
);
839 if (get_xl(ctx
) == MXL_RV128
) {
840 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
841 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
842 TCGv desth
= dest_gprh(ctx
, a
->rd
);
844 func(desth
, src1h
, src2h
);
845 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
847 gen_set_gpr(ctx
, a
->rd
, dest
);
853 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
854 void (*func
)(TCGv
, TCGv
, target_long
),
855 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
857 TCGv dest
= dest_gpr(ctx
, a
->rd
);
858 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
860 if (get_ol(ctx
) < MXL_RV128
) {
861 func(dest
, src1
, a
->imm
);
862 gen_set_gpr(ctx
, a
->rd
, dest
);
868 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
869 TCGv desth
= dest_gprh(ctx
, a
->rd
);
871 f128(dest
, desth
, src1
, src1h
, a
->imm
);
872 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
877 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
878 void (*func
)(TCGv
, TCGv
, TCGv
),
879 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
881 TCGv dest
= dest_gpr(ctx
, a
->rd
);
882 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
883 TCGv src2
= tcg_constant_tl(a
->imm
);
885 if (get_ol(ctx
) < MXL_RV128
) {
886 func(dest
, src1
, src2
);
887 gen_set_gpr(ctx
, a
->rd
, dest
);
893 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
894 TCGv src2h
= tcg_constant_tl(-(a
->imm
< 0));
895 TCGv desth
= dest_gprh(ctx
, a
->rd
);
897 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
898 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
903 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
904 void (*func
)(TCGv
, TCGv
, TCGv
),
905 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
907 TCGv dest
= dest_gpr(ctx
, a
->rd
);
908 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
909 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
911 if (get_ol(ctx
) < MXL_RV128
) {
912 func(dest
, src1
, src2
);
913 gen_set_gpr(ctx
, a
->rd
, dest
);
919 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
920 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
921 TCGv desth
= dest_gprh(ctx
, a
->rd
);
923 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
924 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
929 static bool gen_arith_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
930 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
931 void (*f_32
)(TCGv
, TCGv
, TCGv
),
932 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
934 int olen
= get_olen(ctx
);
936 if (olen
!= TARGET_LONG_BITS
) {
939 } else if (olen
!= 128) {
940 g_assert_not_reached();
943 return gen_arith(ctx
, a
, ext
, f_tl
, f_128
);
946 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
947 void (*func
)(TCGv
, TCGv
, target_long
),
948 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
951 int max_len
= get_olen(ctx
);
953 if (a
->shamt
>= max_len
) {
957 dest
= dest_gpr(ctx
, a
->rd
);
958 src1
= get_gpr(ctx
, a
->rs1
, ext
);
961 func(dest
, src1
, a
->shamt
);
962 gen_set_gpr(ctx
, a
->rd
, dest
);
964 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
965 TCGv desth
= dest_gprh(ctx
, a
->rd
);
970 f128(dest
, desth
, src1
, src1h
, a
->shamt
);
971 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
976 static bool gen_shift_imm_fn_per_ol(DisasContext
*ctx
, arg_shift
*a
,
978 void (*f_tl
)(TCGv
, TCGv
, target_long
),
979 void (*f_32
)(TCGv
, TCGv
, target_long
),
980 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
,
983 int olen
= get_olen(ctx
);
984 if (olen
!= TARGET_LONG_BITS
) {
987 } else if (olen
!= 128) {
988 g_assert_not_reached();
991 return gen_shift_imm_fn(ctx
, a
, ext
, f_tl
, f_128
);
994 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
995 void (*func
)(TCGv
, TCGv
, TCGv
))
997 TCGv dest
, src1
, src2
;
998 int max_len
= get_olen(ctx
);
1000 if (a
->shamt
>= max_len
) {
1004 dest
= dest_gpr(ctx
, a
->rd
);
1005 src1
= get_gpr(ctx
, a
->rs1
, ext
);
1006 src2
= tcg_constant_tl(a
->shamt
);
1008 func(dest
, src1
, src2
);
1010 gen_set_gpr(ctx
, a
->rd
, dest
);
1014 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
1015 void (*func
)(TCGv
, TCGv
, TCGv
),
1016 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
1018 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
1019 TCGv ext2
= tcg_temp_new();
1020 int max_len
= get_olen(ctx
);
1022 tcg_gen_andi_tl(ext2
, src2
, max_len
- 1);
1024 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1025 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1027 if (max_len
< 128) {
1028 func(dest
, src1
, ext2
);
1029 gen_set_gpr(ctx
, a
->rd
, dest
);
1031 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
1032 TCGv desth
= dest_gprh(ctx
, a
->rd
);
1037 f128(dest
, desth
, src1
, src1h
, ext2
);
1038 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
1040 tcg_temp_free(ext2
);
1044 static bool gen_shift_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
1045 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
1046 void (*f_32
)(TCGv
, TCGv
, TCGv
),
1047 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
1049 int olen
= get_olen(ctx
);
1050 if (olen
!= TARGET_LONG_BITS
) {
1053 } else if (olen
!= 128) {
1054 g_assert_not_reached();
1057 return gen_shift(ctx
, a
, ext
, f_tl
, f_128
);
1060 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1061 void (*func
)(TCGv
, TCGv
))
1063 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1064 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1068 gen_set_gpr(ctx
, a
->rd
, dest
);
1072 static bool gen_unary_per_ol(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1073 void (*f_tl
)(TCGv
, TCGv
),
1074 void (*f_32
)(TCGv
, TCGv
))
1076 int olen
= get_olen(ctx
);
1078 if (olen
!= TARGET_LONG_BITS
) {
1082 g_assert_not_reached();
1085 return gen_unary(ctx
, a
, ext
, f_tl
);
1088 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
1090 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1091 CPUState
*cpu
= ctx
->cs
;
1092 CPURISCVState
*env
= cpu
->env_ptr
;
1094 return cpu_ldl_code(env
, pc
);
1097 /* Include insn module translation function */
1098 #include "insn_trans/trans_rvi.c.inc"
1099 #include "insn_trans/trans_rvm.c.inc"
1100 #include "insn_trans/trans_rva.c.inc"
1101 #include "insn_trans/trans_rvf.c.inc"
1102 #include "insn_trans/trans_rvd.c.inc"
1103 #include "insn_trans/trans_rvh.c.inc"
1104 #include "insn_trans/trans_rvv.c.inc"
1105 #include "insn_trans/trans_rvb.c.inc"
1106 #include "insn_trans/trans_rvzicond.c.inc"
1107 #include "insn_trans/trans_rvzawrs.c.inc"
1108 #include "insn_trans/trans_rvzfh.c.inc"
1109 #include "insn_trans/trans_rvk.c.inc"
1110 #include "insn_trans/trans_privileged.c.inc"
1111 #include "insn_trans/trans_svinval.c.inc"
1112 #include "decode-xthead.c.inc"
1113 #include "insn_trans/trans_xthead.c.inc"
1114 #include "insn_trans/trans_xventanacondops.c.inc"
1116 /* Include the auto-generated decoder for 16 bit insn */
1117 #include "decode-insn16.c.inc"
1118 /* Include decoders for factored-out extensions */
1119 #include "decode-XVentanaCondOps.c.inc"
1121 /* The specification allows for longer insns, but not supported by qemu. */
1122 #define MAX_INSN_LEN 4
1124 static inline int insn_len(uint16_t first_word
)
1126 return (first_word
& 3) == 3 ? 4 : 2;
1129 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
1132 * A table with predicate (i.e., guard) functions and decoder functions
1133 * that are tested in-order until a decoder matches onto the opcode.
1135 static const struct {
1136 bool (*guard_func
)(DisasContext
*);
1137 bool (*decode_func
)(DisasContext
*, uint32_t);
1139 { always_true_p
, decode_insn32
},
1140 { has_xthead_p
, decode_xthead
},
1141 { has_XVentanaCondOps_p
, decode_XVentanaCodeOps
},
1144 ctx
->virt_inst_excp
= false;
1145 /* Check for compressed insn */
1146 if (insn_len(opcode
) == 2) {
1147 ctx
->opcode
= opcode
;
1148 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
1149 if (has_ext(ctx
, RVC
) && decode_insn16(ctx
, opcode
)) {
1153 uint32_t opcode32
= opcode
;
1154 opcode32
= deposit32(opcode32
, 16, 16,
1155 translator_lduw(env
, &ctx
->base
,
1156 ctx
->base
.pc_next
+ 2));
1157 ctx
->opcode
= opcode32
;
1158 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
1160 for (size_t i
= 0; i
< ARRAY_SIZE(decoders
); ++i
) {
1161 if (decoders
[i
].guard_func(ctx
) &&
1162 decoders
[i
].decode_func(ctx
, opcode32
)) {
1168 gen_exception_illegal(ctx
);
1171 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
1173 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1174 CPURISCVState
*env
= cs
->env_ptr
;
1175 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1176 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
1178 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
1179 ctx
->mem_idx
= FIELD_EX32(tb_flags
, TB_FLAGS
, MEM_IDX
);
1180 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
1181 ctx
->mstatus_vs
= tb_flags
& TB_FLAGS_MSTATUS_VS
;
1182 ctx
->priv_ver
= env
->priv_ver
;
1183 #if !defined(CONFIG_USER_ONLY)
1184 if (riscv_has_ext(env
, RVH
)) {
1185 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
1187 ctx
->virt_enabled
= false;
1190 ctx
->virt_enabled
= false;
1192 ctx
->misa_ext
= env
->misa_ext
;
1193 ctx
->frm
= -1; /* unknown rounding mode */
1194 ctx
->cfg_ptr
= &(cpu
->cfg
);
1195 ctx
->mstatus_hs_fs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_FS
);
1196 ctx
->mstatus_hs_vs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_VS
);
1197 ctx
->hlsx
= FIELD_EX32(tb_flags
, TB_FLAGS
, HLSX
);
1198 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
1199 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
1200 ctx
->lmul
= sextract32(FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
), 0, 3);
1201 ctx
->vta
= FIELD_EX32(tb_flags
, TB_FLAGS
, VTA
) && cpu
->cfg
.rvv_ta_all_1s
;
1202 ctx
->vma
= FIELD_EX32(tb_flags
, TB_FLAGS
, VMA
) && cpu
->cfg
.rvv_ma_all_1s
;
1203 ctx
->cfg_vta_all_1s
= cpu
->cfg
.rvv_ta_all_1s
;
1204 ctx
->vstart
= env
->vstart
;
1205 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
1206 ctx
->misa_mxl_max
= env
->misa_mxl_max
;
1207 ctx
->xl
= FIELD_EX32(tb_flags
, TB_FLAGS
, XL
);
1210 memset(ctx
->temp
, 0, sizeof(ctx
->temp
));
1212 memset(ctx
->ftemp
, 0, sizeof(ctx
->ftemp
));
1213 ctx
->pm_mask_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_MASK_ENABLED
);
1214 ctx
->pm_base_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_BASE_ENABLED
);
1215 ctx
->itrigger
= FIELD_EX32(tb_flags
, TB_FLAGS
, ITRIGGER
);
1216 ctx
->zero
= tcg_constant_tl(0);
1217 ctx
->virt_inst_excp
= false;
1220 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
1224 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1226 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1228 tcg_gen_insn_start(ctx
->base
.pc_next
, 0);
1229 ctx
->insn_start
= tcg_last_op();
1232 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1234 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1235 CPURISCVState
*env
= cpu
->env_ptr
;
1236 uint16_t opcode16
= translator_lduw(env
, &ctx
->base
, ctx
->base
.pc_next
);
1240 decode_opc(env
, ctx
, opcode16
);
1241 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
1243 for (i
= ctx
->ntemp
- 1; i
>= 0; --i
) {
1244 tcg_temp_free(ctx
->temp
[i
]);
1245 ctx
->temp
[i
] = NULL
;
1248 for (i
= ctx
->nftemp
- 1; i
>= 0; --i
) {
1249 tcg_temp_free_i64(ctx
->ftemp
[i
]);
1250 ctx
->ftemp
[i
] = NULL
;
1254 /* Only the first insn within a TB is allowed to cross a page boundary. */
1255 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
1256 if (ctx
->itrigger
|| !is_same_page(&ctx
->base
, ctx
->base
.pc_next
)) {
1257 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1259 unsigned page_ofs
= ctx
->base
.pc_next
& ~TARGET_PAGE_MASK
;
1261 if (page_ofs
> TARGET_PAGE_SIZE
- MAX_INSN_LEN
) {
1262 uint16_t next_insn
= cpu_lduw_code(env
, ctx
->base
.pc_next
);
1263 int len
= insn_len(next_insn
);
1265 if (!is_same_page(&ctx
->base
, ctx
->base
.pc_next
+ len
- 1)) {
1266 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1273 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1275 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1277 switch (ctx
->base
.is_jmp
) {
1278 case DISAS_TOO_MANY
:
1279 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1281 case DISAS_NORETURN
:
1284 g_assert_not_reached();
1288 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
,
1289 CPUState
*cpu
, FILE *logfile
)
1291 #ifndef CONFIG_USER_ONLY
1292 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
1293 CPURISCVState
*env
= &rvcpu
->env
;
1296 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1297 #ifndef CONFIG_USER_ONLY
1298 fprintf(logfile
, "Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n",
1299 env
->priv
, env
->virt
);
1301 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1304 static const TranslatorOps riscv_tr_ops
= {
1305 .init_disas_context
= riscv_tr_init_disas_context
,
1306 .tb_start
= riscv_tr_tb_start
,
1307 .insn_start
= riscv_tr_insn_start
,
1308 .translate_insn
= riscv_tr_translate_insn
,
1309 .tb_stop
= riscv_tr_tb_stop
,
1310 .disas_log
= riscv_tr_disas_log
,
1313 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
1314 target_ulong pc
, void *host_pc
)
1318 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &riscv_tr_ops
, &ctx
.base
);
1321 void riscv_translate_init(void)
1326 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1327 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1328 * unless you specifically block reads/writes to reg 0.
1333 for (i
= 1; i
< 32; i
++) {
1334 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
1335 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
1336 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
1337 offsetof(CPURISCVState
, gprh
[i
]), riscv_int_regnamesh
[i
]);
1340 for (i
= 0; i
< 32; i
++) {
1341 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
1342 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
1345 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
1346 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
1347 cpu_vstart
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vstart
),
1349 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
1351 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),
1353 /* Assign PM CSRs to tcg globals */
1354 pm_mask
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmmask
),
1356 pm_base
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmbase
),