2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
31 #include "semihosting/semihost.h"
34 #include "internals.h"
36 /* global register indices */
37 static TCGv cpu_gpr
[32], cpu_gprh
[32], cpu_pc
, cpu_vl
, cpu_vstart
;
38 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
41 /* globals for PM CSRs */
45 #include "exec/gen-icount.h"
48 * If an operation is being performed on less than TARGET_LONG_BITS,
49 * it may require the inputs to be sign- or zero-extended; which will
50 * depend on the exact operation being performed.
58 typedef struct DisasContext
{
59 DisasContextBase base
;
60 /* pc_succ_insn points to the instruction following base.pc_next */
61 target_ulong pc_succ_insn
;
62 target_ulong priv_ver
;
63 RISCVMXL misa_mxl_max
;
69 uint32_t mstatus_hs_fs
;
70 uint32_t mstatus_hs_vs
;
72 /* Remember the rounding mode encoded in the previous fp instruction,
73 which we have already installed into env->fp_status. Or -1 for
74 no previous fp instruction. Note that we exit the TB when writing
75 to any system register, which includes CSR_FRM, so we do not have
76 to reset this known value. */
81 const RISCVCPUConfig
*cfg_ptr
;
83 /* vector extension */
86 * Encode LMUL to lmul as follows:
106 /* PointerMasking extension */
107 bool pm_mask_enabled
;
108 bool pm_base_enabled
;
109 /* Use icount trigger for native debug */
111 /* FRM is known to contain a valid value. */
113 /* TCG of the current insn_start */
117 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
119 return ctx
->misa_ext
& ext
;
122 static bool always_true_p(DisasContext
*ctx
__attribute__((__unused__
)))
127 static bool has_xthead_p(DisasContext
*ctx
__attribute__((__unused__
)))
129 return ctx
->cfg_ptr
->ext_xtheadba
|| ctx
->cfg_ptr
->ext_xtheadbb
||
130 ctx
->cfg_ptr
->ext_xtheadbs
|| ctx
->cfg_ptr
->ext_xtheadcmo
||
131 ctx
->cfg_ptr
->ext_xtheadcondmov
||
132 ctx
->cfg_ptr
->ext_xtheadfmemidx
|| ctx
->cfg_ptr
->ext_xtheadfmv
||
133 ctx
->cfg_ptr
->ext_xtheadmac
|| ctx
->cfg_ptr
->ext_xtheadmemidx
||
134 ctx
->cfg_ptr
->ext_xtheadmempair
|| ctx
->cfg_ptr
->ext_xtheadsync
;
137 #define MATERIALISE_EXT_PREDICATE(ext) \
138 static bool has_ ## ext ## _p(DisasContext *ctx) \
140 return ctx->cfg_ptr->ext_ ## ext ; \
143 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
);
145 #ifdef TARGET_RISCV32
146 #define get_xl(ctx) MXL_RV32
147 #elif defined(CONFIG_USER_ONLY)
148 #define get_xl(ctx) MXL_RV64
150 #define get_xl(ctx) ((ctx)->xl)
153 /* The word size for this machine mode. */
154 static inline int __attribute__((unused
)) get_xlen(DisasContext
*ctx
)
156 return 16 << get_xl(ctx
);
159 /* The operation length, as opposed to the xlen. */
160 #ifdef TARGET_RISCV32
161 #define get_ol(ctx) MXL_RV32
163 #define get_ol(ctx) ((ctx)->ol)
166 static inline int get_olen(DisasContext
*ctx
)
168 return 16 << get_ol(ctx
);
171 /* The maximum register length */
172 #ifdef TARGET_RISCV32
173 #define get_xl_max(ctx) MXL_RV32
175 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
179 * RISC-V requires NaN-boxing of narrower width floating point values.
180 * This applies when a 32-bit value is assigned to a 64-bit FP register.
181 * For consistency and simplicity, we nanbox results even when the RVD
182 * extension is not present.
184 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
186 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
189 static void gen_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
191 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(16, 48));
195 * A narrow n-bit operation, where n < FLEN, checks that input operands
196 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
197 * If so, the least-significant bits of the input are used, otherwise the
198 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
200 * Here, the result is always nan-boxed, even the canonical nan.
202 static void gen_check_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
204 TCGv_i64 t_max
= tcg_const_i64(0xffffffffffff0000ull
);
205 TCGv_i64 t_nan
= tcg_const_i64(0xffffffffffff7e00ull
);
207 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
208 tcg_temp_free_i64(t_max
);
209 tcg_temp_free_i64(t_nan
);
212 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
214 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
215 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
217 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
220 static void decode_save_opc(DisasContext
*ctx
)
222 assert(ctx
->insn_start
!= NULL
);
223 tcg_set_insn_start_param(ctx
->insn_start
, 1, ctx
->opcode
);
224 ctx
->insn_start
= NULL
;
227 static void gen_set_pc_imm(DisasContext
*ctx
, target_ulong dest
)
229 if (get_xl(ctx
) == MXL_RV32
) {
230 dest
= (int32_t)dest
;
232 tcg_gen_movi_tl(cpu_pc
, dest
);
235 static void gen_set_pc(DisasContext
*ctx
, TCGv dest
)
237 if (get_xl(ctx
) == MXL_RV32
) {
238 tcg_gen_ext32s_tl(cpu_pc
, dest
);
240 tcg_gen_mov_tl(cpu_pc
, dest
);
244 static void generate_exception(DisasContext
*ctx
, int excp
)
246 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
247 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
248 ctx
->base
.is_jmp
= DISAS_NORETURN
;
251 static void gen_exception_illegal(DisasContext
*ctx
)
253 tcg_gen_st_i32(tcg_constant_i32(ctx
->opcode
), cpu_env
,
254 offsetof(CPURISCVState
, bins
));
255 if (ctx
->virt_inst_excp
) {
256 generate_exception(ctx
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
);
258 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
262 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
264 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
265 generate_exception(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
268 static void lookup_and_goto_ptr(DisasContext
*ctx
)
270 #ifndef CONFIG_USER_ONLY
272 gen_helper_itrigger_match(cpu_env
);
275 tcg_gen_lookup_and_goto_ptr();
278 static void exit_tb(DisasContext
*ctx
)
280 #ifndef CONFIG_USER_ONLY
282 gen_helper_itrigger_match(cpu_env
);
285 tcg_gen_exit_tb(NULL
, 0);
288 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
291 * Under itrigger, instruction executes one by one like singlestep,
292 * direct block chain benefits will be small.
294 if (translator_use_goto_tb(&ctx
->base
, dest
) && !ctx
->itrigger
) {
296 gen_set_pc_imm(ctx
, dest
);
297 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
299 gen_set_pc_imm(ctx
, dest
);
300 lookup_and_goto_ptr(ctx
);
305 * Wrappers for getting reg values.
307 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
308 * constant zero as a source, and an uninitialized sink as destination.
310 * Further, we may provide an extension for word operations.
312 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
320 switch (get_ol(ctx
)) {
327 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
331 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
334 g_assert_not_reached();
341 g_assert_not_reached();
343 return cpu_gpr
[reg_num
];
346 static TCGv
get_gprh(DisasContext
*ctx
, int reg_num
)
348 assert(get_xl(ctx
) == MXL_RV128
);
352 return cpu_gprh
[reg_num
];
355 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
357 if (reg_num
== 0 || get_olen(ctx
) < TARGET_LONG_BITS
) {
358 return tcg_temp_new();
360 return cpu_gpr
[reg_num
];
363 static TCGv
dest_gprh(DisasContext
*ctx
, int reg_num
)
366 return tcg_temp_new();
368 return cpu_gprh
[reg_num
];
371 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
374 switch (get_ol(ctx
)) {
376 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
380 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
383 g_assert_not_reached();
386 if (get_xl_max(ctx
) == MXL_RV128
) {
387 tcg_gen_sari_tl(cpu_gprh
[reg_num
], cpu_gpr
[reg_num
], 63);
392 static void gen_set_gpri(DisasContext
*ctx
, int reg_num
, target_long imm
)
395 switch (get_ol(ctx
)) {
397 tcg_gen_movi_tl(cpu_gpr
[reg_num
], (int32_t)imm
);
401 tcg_gen_movi_tl(cpu_gpr
[reg_num
], imm
);
404 g_assert_not_reached();
407 if (get_xl_max(ctx
) == MXL_RV128
) {
408 tcg_gen_movi_tl(cpu_gprh
[reg_num
], -(imm
< 0));
413 static void gen_set_gpr128(DisasContext
*ctx
, int reg_num
, TCGv rl
, TCGv rh
)
415 assert(get_ol(ctx
) == MXL_RV128
);
417 tcg_gen_mov_tl(cpu_gpr
[reg_num
], rl
);
418 tcg_gen_mov_tl(cpu_gprh
[reg_num
], rh
);
422 static TCGv_i64
get_fpr_hs(DisasContext
*ctx
, int reg_num
)
424 if (!ctx
->cfg_ptr
->ext_zfinx
) {
425 return cpu_fpr
[reg_num
];
429 return tcg_constant_i64(0);
431 switch (get_xl(ctx
)) {
433 #ifdef TARGET_RISCV32
435 TCGv_i64 t
= tcg_temp_new_i64();
436 tcg_gen_ext_i32_i64(t
, cpu_gpr
[reg_num
]);
442 return cpu_gpr
[reg_num
];
445 g_assert_not_reached();
449 static TCGv_i64
get_fpr_d(DisasContext
*ctx
, int reg_num
)
451 if (!ctx
->cfg_ptr
->ext_zfinx
) {
452 return cpu_fpr
[reg_num
];
456 return tcg_constant_i64(0);
458 switch (get_xl(ctx
)) {
461 TCGv_i64 t
= tcg_temp_new_i64();
462 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1]);
465 #ifdef TARGET_RISCV64
467 return cpu_gpr
[reg_num
];
470 g_assert_not_reached();
474 static TCGv_i64
dest_fpr(DisasContext
*ctx
, int reg_num
)
476 if (!ctx
->cfg_ptr
->ext_zfinx
) {
477 return cpu_fpr
[reg_num
];
481 return tcg_temp_new_i64();
484 switch (get_xl(ctx
)) {
486 return tcg_temp_new_i64();
487 #ifdef TARGET_RISCV64
489 return cpu_gpr
[reg_num
];
492 g_assert_not_reached();
496 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
497 static void gen_set_fpr_hs(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
499 if (!ctx
->cfg_ptr
->ext_zfinx
) {
500 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
504 switch (get_xl(ctx
)) {
506 #ifdef TARGET_RISCV32
507 tcg_gen_extrl_i64_i32(cpu_gpr
[reg_num
], t
);
512 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
516 g_assert_not_reached();
521 static void gen_set_fpr_d(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
523 if (!ctx
->cfg_ptr
->ext_zfinx
) {
524 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
529 switch (get_xl(ctx
)) {
531 #ifdef TARGET_RISCV32
532 tcg_gen_extr_i64_i32(cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1], t
);
535 tcg_gen_ext32s_i64(cpu_gpr
[reg_num
], t
);
536 tcg_gen_sari_i64(cpu_gpr
[reg_num
+ 1], t
, 32);
539 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
543 g_assert_not_reached();
548 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
550 target_ulong next_pc
;
552 /* check misaligned: */
553 next_pc
= ctx
->base
.pc_next
+ imm
;
554 if (!has_ext(ctx
, RVC
)) {
555 if ((next_pc
& 0x3) != 0) {
556 gen_exception_inst_addr_mis(ctx
);
561 gen_set_gpri(ctx
, rd
, ctx
->pc_succ_insn
);
562 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
563 ctx
->base
.is_jmp
= DISAS_NORETURN
;
566 /* Compute a canonical address from a register plus offset. */
567 static TCGv
get_address(DisasContext
*ctx
, int rs1
, int imm
)
569 TCGv addr
= tcg_temp_new();
570 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
572 tcg_gen_addi_tl(addr
, src1
, imm
);
573 if (ctx
->pm_mask_enabled
) {
574 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
575 } else if (get_xl(ctx
) == MXL_RV32
) {
576 tcg_gen_ext32u_tl(addr
, addr
);
578 if (ctx
->pm_base_enabled
) {
579 tcg_gen_or_tl(addr
, addr
, pm_base
);
584 /* Compute a canonical address from a register plus reg offset. */
585 static TCGv
get_address_indexed(DisasContext
*ctx
, int rs1
, TCGv offs
)
587 TCGv addr
= tcg_temp_new();
588 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
590 tcg_gen_add_tl(addr
, src1
, offs
);
591 if (ctx
->pm_mask_enabled
) {
592 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
593 } else if (get_xl(ctx
) == MXL_RV32
) {
594 tcg_gen_ext32u_tl(addr
, addr
);
596 if (ctx
->pm_base_enabled
) {
597 tcg_gen_or_tl(addr
, addr
, pm_base
);
602 #ifndef CONFIG_USER_ONLY
603 /* The states of mstatus_fs are:
604 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
605 * We will have already diagnosed disabled state,
606 * and need to turn initial/clean into dirty.
608 static void mark_fs_dirty(DisasContext
*ctx
)
612 if (!has_ext(ctx
, RVF
)) {
616 if (ctx
->mstatus_fs
!= MSTATUS_FS
) {
617 /* Remember the state change for the rest of the TB. */
618 ctx
->mstatus_fs
= MSTATUS_FS
;
620 tmp
= tcg_temp_new();
621 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
622 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
623 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
627 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_fs
!= MSTATUS_FS
) {
628 /* Remember the stage change for the rest of the TB. */
629 ctx
->mstatus_hs_fs
= MSTATUS_FS
;
631 tmp
= tcg_temp_new();
632 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
633 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
634 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
639 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
642 #ifndef CONFIG_USER_ONLY
643 /* The states of mstatus_vs are:
644 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
645 * We will have already diagnosed disabled state,
646 * and need to turn initial/clean into dirty.
648 static void mark_vs_dirty(DisasContext
*ctx
)
652 if (ctx
->mstatus_vs
!= MSTATUS_VS
) {
653 /* Remember the state change for the rest of the TB. */
654 ctx
->mstatus_vs
= MSTATUS_VS
;
656 tmp
= tcg_temp_new();
657 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
658 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
659 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
663 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_vs
!= MSTATUS_VS
) {
664 /* Remember the stage change for the rest of the TB. */
665 ctx
->mstatus_hs_vs
= MSTATUS_VS
;
667 tmp
= tcg_temp_new();
668 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
669 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
670 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
675 static inline void mark_vs_dirty(DisasContext
*ctx
) { }
678 static void gen_set_rm(DisasContext
*ctx
, int rm
)
680 if (ctx
->frm
== rm
) {
685 if (rm
== RISCV_FRM_DYN
) {
686 /* The helper will return only if frm valid. */
687 ctx
->frm_valid
= true;
690 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
691 decode_save_opc(ctx
);
692 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
695 static void gen_set_rm_chkfrm(DisasContext
*ctx
, int rm
)
697 if (ctx
->frm
== rm
&& ctx
->frm_valid
) {
701 ctx
->frm_valid
= true;
703 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
704 decode_save_opc(ctx
);
705 gen_helper_set_rounding_mode_chkfrm(cpu_env
, tcg_constant_i32(rm
));
708 static int ex_plus_1(DisasContext
*ctx
, int nf
)
713 #define EX_SH(amount) \
714 static int ex_shift_##amount(DisasContext *ctx, int imm) \
716 return imm << amount; \
724 #define REQUIRE_EXT(ctx, ext) do { \
725 if (!has_ext(ctx, ext)) { \
730 #define REQUIRE_32BIT(ctx) do { \
731 if (get_xl(ctx) != MXL_RV32) { \
736 #define REQUIRE_64BIT(ctx) do { \
737 if (get_xl(ctx) != MXL_RV64) { \
742 #define REQUIRE_128BIT(ctx) do { \
743 if (get_xl(ctx) != MXL_RV128) { \
748 #define REQUIRE_64_OR_128BIT(ctx) do { \
749 if (get_xl(ctx) == MXL_RV32) { \
754 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \
755 if (!ctx->cfg_ptr->ext_##A && \
756 !ctx->cfg_ptr->ext_##B) { \
761 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
766 static int ex_rvc_shiftli(DisasContext
*ctx
, int imm
)
768 /* For RV128 a shamt of 0 means a shift by 64. */
769 if (get_ol(ctx
) == MXL_RV128
) {
770 imm
= imm
? imm
: 64;
775 static int ex_rvc_shiftri(DisasContext
*ctx
, int imm
)
778 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right
779 * shifts, the shamt is sign-extended.
781 if (get_ol(ctx
) == MXL_RV128
) {
782 imm
= imm
| (imm
& 32) << 1;
783 imm
= imm
? imm
: 64;
788 /* Include the auto-generated decoder for 32 bit insn */
789 #include "decode-insn32.c.inc"
791 static bool gen_logic_imm_fn(DisasContext
*ctx
, arg_i
*a
,
792 void (*func
)(TCGv
, TCGv
, target_long
))
794 TCGv dest
= dest_gpr(ctx
, a
->rd
);
795 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
797 func(dest
, src1
, a
->imm
);
799 if (get_xl(ctx
) == MXL_RV128
) {
800 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
801 TCGv desth
= dest_gprh(ctx
, a
->rd
);
803 func(desth
, src1h
, -(a
->imm
< 0));
804 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
806 gen_set_gpr(ctx
, a
->rd
, dest
);
812 static bool gen_logic(DisasContext
*ctx
, arg_r
*a
,
813 void (*func
)(TCGv
, TCGv
, TCGv
))
815 TCGv dest
= dest_gpr(ctx
, a
->rd
);
816 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
817 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
819 func(dest
, src1
, src2
);
821 if (get_xl(ctx
) == MXL_RV128
) {
822 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
823 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
824 TCGv desth
= dest_gprh(ctx
, a
->rd
);
826 func(desth
, src1h
, src2h
);
827 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
829 gen_set_gpr(ctx
, a
->rd
, dest
);
835 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
836 void (*func
)(TCGv
, TCGv
, target_long
),
837 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
839 TCGv dest
= dest_gpr(ctx
, a
->rd
);
840 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
842 if (get_ol(ctx
) < MXL_RV128
) {
843 func(dest
, src1
, a
->imm
);
844 gen_set_gpr(ctx
, a
->rd
, dest
);
850 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
851 TCGv desth
= dest_gprh(ctx
, a
->rd
);
853 f128(dest
, desth
, src1
, src1h
, a
->imm
);
854 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
859 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
860 void (*func
)(TCGv
, TCGv
, TCGv
),
861 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
863 TCGv dest
= dest_gpr(ctx
, a
->rd
);
864 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
865 TCGv src2
= tcg_constant_tl(a
->imm
);
867 if (get_ol(ctx
) < MXL_RV128
) {
868 func(dest
, src1
, src2
);
869 gen_set_gpr(ctx
, a
->rd
, dest
);
875 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
876 TCGv src2h
= tcg_constant_tl(-(a
->imm
< 0));
877 TCGv desth
= dest_gprh(ctx
, a
->rd
);
879 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
880 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
885 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
886 void (*func
)(TCGv
, TCGv
, TCGv
),
887 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
889 TCGv dest
= dest_gpr(ctx
, a
->rd
);
890 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
891 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
893 if (get_ol(ctx
) < MXL_RV128
) {
894 func(dest
, src1
, src2
);
895 gen_set_gpr(ctx
, a
->rd
, dest
);
901 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
902 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
903 TCGv desth
= dest_gprh(ctx
, a
->rd
);
905 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
906 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
911 static bool gen_arith_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
912 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
913 void (*f_32
)(TCGv
, TCGv
, TCGv
),
914 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
916 int olen
= get_olen(ctx
);
918 if (olen
!= TARGET_LONG_BITS
) {
921 } else if (olen
!= 128) {
922 g_assert_not_reached();
925 return gen_arith(ctx
, a
, ext
, f_tl
, f_128
);
928 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
929 void (*func
)(TCGv
, TCGv
, target_long
),
930 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
933 int max_len
= get_olen(ctx
);
935 if (a
->shamt
>= max_len
) {
939 dest
= dest_gpr(ctx
, a
->rd
);
940 src1
= get_gpr(ctx
, a
->rs1
, ext
);
943 func(dest
, src1
, a
->shamt
);
944 gen_set_gpr(ctx
, a
->rd
, dest
);
946 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
947 TCGv desth
= dest_gprh(ctx
, a
->rd
);
952 f128(dest
, desth
, src1
, src1h
, a
->shamt
);
953 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
958 static bool gen_shift_imm_fn_per_ol(DisasContext
*ctx
, arg_shift
*a
,
960 void (*f_tl
)(TCGv
, TCGv
, target_long
),
961 void (*f_32
)(TCGv
, TCGv
, target_long
),
962 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
,
965 int olen
= get_olen(ctx
);
966 if (olen
!= TARGET_LONG_BITS
) {
969 } else if (olen
!= 128) {
970 g_assert_not_reached();
973 return gen_shift_imm_fn(ctx
, a
, ext
, f_tl
, f_128
);
976 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
977 void (*func
)(TCGv
, TCGv
, TCGv
))
979 TCGv dest
, src1
, src2
;
980 int max_len
= get_olen(ctx
);
982 if (a
->shamt
>= max_len
) {
986 dest
= dest_gpr(ctx
, a
->rd
);
987 src1
= get_gpr(ctx
, a
->rs1
, ext
);
988 src2
= tcg_constant_tl(a
->shamt
);
990 func(dest
, src1
, src2
);
992 gen_set_gpr(ctx
, a
->rd
, dest
);
996 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
997 void (*func
)(TCGv
, TCGv
, TCGv
),
998 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
1000 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
1001 TCGv ext2
= tcg_temp_new();
1002 int max_len
= get_olen(ctx
);
1004 tcg_gen_andi_tl(ext2
, src2
, max_len
- 1);
1006 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1007 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1009 if (max_len
< 128) {
1010 func(dest
, src1
, ext2
);
1011 gen_set_gpr(ctx
, a
->rd
, dest
);
1013 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
1014 TCGv desth
= dest_gprh(ctx
, a
->rd
);
1019 f128(dest
, desth
, src1
, src1h
, ext2
);
1020 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
1022 tcg_temp_free(ext2
);
1026 static bool gen_shift_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
1027 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
1028 void (*f_32
)(TCGv
, TCGv
, TCGv
),
1029 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
1031 int olen
= get_olen(ctx
);
1032 if (olen
!= TARGET_LONG_BITS
) {
1035 } else if (olen
!= 128) {
1036 g_assert_not_reached();
1039 return gen_shift(ctx
, a
, ext
, f_tl
, f_128
);
1042 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1043 void (*func
)(TCGv
, TCGv
))
1045 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1046 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1050 gen_set_gpr(ctx
, a
->rd
, dest
);
1054 static bool gen_unary_per_ol(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1055 void (*f_tl
)(TCGv
, TCGv
),
1056 void (*f_32
)(TCGv
, TCGv
))
1058 int olen
= get_olen(ctx
);
1060 if (olen
!= TARGET_LONG_BITS
) {
1064 g_assert_not_reached();
1067 return gen_unary(ctx
, a
, ext
, f_tl
);
1070 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
1072 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1073 CPUState
*cpu
= ctx
->cs
;
1074 CPURISCVState
*env
= cpu
->env_ptr
;
1076 return cpu_ldl_code(env
, pc
);
1079 /* Include insn module translation function */
1080 #include "insn_trans/trans_rvi.c.inc"
1081 #include "insn_trans/trans_rvm.c.inc"
1082 #include "insn_trans/trans_rva.c.inc"
1083 #include "insn_trans/trans_rvf.c.inc"
1084 #include "insn_trans/trans_rvd.c.inc"
1085 #include "insn_trans/trans_rvh.c.inc"
1086 #include "insn_trans/trans_rvv.c.inc"
1087 #include "insn_trans/trans_rvb.c.inc"
1088 #include "insn_trans/trans_rvzicond.c.inc"
1089 #include "insn_trans/trans_rvzawrs.c.inc"
1090 #include "insn_trans/trans_rvzfh.c.inc"
1091 #include "insn_trans/trans_rvk.c.inc"
1092 #include "insn_trans/trans_privileged.c.inc"
1093 #include "insn_trans/trans_svinval.c.inc"
1094 #include "decode-xthead.c.inc"
1095 #include "insn_trans/trans_xthead.c.inc"
1096 #include "insn_trans/trans_xventanacondops.c.inc"
1098 /* Include the auto-generated decoder for 16 bit insn */
1099 #include "decode-insn16.c.inc"
1100 /* Include decoders for factored-out extensions */
1101 #include "decode-XVentanaCondOps.c.inc"
1103 /* The specification allows for longer insns, but not supported by qemu. */
1104 #define MAX_INSN_LEN 4
1106 static inline int insn_len(uint16_t first_word
)
1108 return (first_word
& 3) == 3 ? 4 : 2;
1111 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
1114 * A table with predicate (i.e., guard) functions and decoder functions
1115 * that are tested in-order until a decoder matches onto the opcode.
1117 static const struct {
1118 bool (*guard_func
)(DisasContext
*);
1119 bool (*decode_func
)(DisasContext
*, uint32_t);
1121 { always_true_p
, decode_insn32
},
1122 { has_xthead_p
, decode_xthead
},
1123 { has_XVentanaCondOps_p
, decode_XVentanaCodeOps
},
1126 ctx
->virt_inst_excp
= false;
1127 /* Check for compressed insn */
1128 if (insn_len(opcode
) == 2) {
1129 ctx
->opcode
= opcode
;
1130 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
1131 if (has_ext(ctx
, RVC
) && decode_insn16(ctx
, opcode
)) {
1135 uint32_t opcode32
= opcode
;
1136 opcode32
= deposit32(opcode32
, 16, 16,
1137 translator_lduw(env
, &ctx
->base
,
1138 ctx
->base
.pc_next
+ 2));
1139 ctx
->opcode
= opcode32
;
1140 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
1142 for (size_t i
= 0; i
< ARRAY_SIZE(decoders
); ++i
) {
1143 if (decoders
[i
].guard_func(ctx
) &&
1144 decoders
[i
].decode_func(ctx
, opcode32
)) {
1150 gen_exception_illegal(ctx
);
1153 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
1155 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1156 CPURISCVState
*env
= cs
->env_ptr
;
1157 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1158 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
1160 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
1161 ctx
->mem_idx
= FIELD_EX32(tb_flags
, TB_FLAGS
, MEM_IDX
);
1162 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
1163 ctx
->mstatus_vs
= tb_flags
& TB_FLAGS_MSTATUS_VS
;
1164 ctx
->priv_ver
= env
->priv_ver
;
1165 #if !defined(CONFIG_USER_ONLY)
1166 if (riscv_has_ext(env
, RVH
)) {
1167 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
1169 ctx
->virt_enabled
= false;
1172 ctx
->virt_enabled
= false;
1174 ctx
->misa_ext
= env
->misa_ext
;
1175 ctx
->frm
= -1; /* unknown rounding mode */
1176 ctx
->cfg_ptr
= &(cpu
->cfg
);
1177 ctx
->mstatus_hs_fs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_FS
);
1178 ctx
->mstatus_hs_vs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_VS
);
1179 ctx
->hlsx
= FIELD_EX32(tb_flags
, TB_FLAGS
, HLSX
);
1180 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
1181 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
1182 ctx
->lmul
= sextract32(FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
), 0, 3);
1183 ctx
->vta
= FIELD_EX32(tb_flags
, TB_FLAGS
, VTA
) && cpu
->cfg
.rvv_ta_all_1s
;
1184 ctx
->vma
= FIELD_EX32(tb_flags
, TB_FLAGS
, VMA
) && cpu
->cfg
.rvv_ma_all_1s
;
1185 ctx
->cfg_vta_all_1s
= cpu
->cfg
.rvv_ta_all_1s
;
1186 ctx
->vstart
= env
->vstart
;
1187 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
1188 ctx
->misa_mxl_max
= env
->misa_mxl_max
;
1189 ctx
->xl
= FIELD_EX32(tb_flags
, TB_FLAGS
, XL
);
1191 ctx
->pm_mask_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_MASK_ENABLED
);
1192 ctx
->pm_base_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_BASE_ENABLED
);
1193 ctx
->itrigger
= FIELD_EX32(tb_flags
, TB_FLAGS
, ITRIGGER
);
1194 ctx
->zero
= tcg_constant_tl(0);
1195 ctx
->virt_inst_excp
= false;
1198 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
1202 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1204 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1206 tcg_gen_insn_start(ctx
->base
.pc_next
, 0);
1207 ctx
->insn_start
= tcg_last_op();
1210 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1212 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1213 CPURISCVState
*env
= cpu
->env_ptr
;
1214 uint16_t opcode16
= translator_lduw(env
, &ctx
->base
, ctx
->base
.pc_next
);
1217 decode_opc(env
, ctx
, opcode16
);
1218 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
1220 /* Only the first insn within a TB is allowed to cross a page boundary. */
1221 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
1222 if (ctx
->itrigger
|| !is_same_page(&ctx
->base
, ctx
->base
.pc_next
)) {
1223 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1225 unsigned page_ofs
= ctx
->base
.pc_next
& ~TARGET_PAGE_MASK
;
1227 if (page_ofs
> TARGET_PAGE_SIZE
- MAX_INSN_LEN
) {
1228 uint16_t next_insn
= cpu_lduw_code(env
, ctx
->base
.pc_next
);
1229 int len
= insn_len(next_insn
);
1231 if (!is_same_page(&ctx
->base
, ctx
->base
.pc_next
+ len
- 1)) {
1232 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1239 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1241 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1243 switch (ctx
->base
.is_jmp
) {
1244 case DISAS_TOO_MANY
:
1245 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1247 case DISAS_NORETURN
:
1250 g_assert_not_reached();
1254 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
,
1255 CPUState
*cpu
, FILE *logfile
)
1257 #ifndef CONFIG_USER_ONLY
1258 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
1259 CPURISCVState
*env
= &rvcpu
->env
;
1262 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1263 #ifndef CONFIG_USER_ONLY
1264 fprintf(logfile
, "Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n",
1265 env
->priv
, env
->virt
);
1267 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1270 static const TranslatorOps riscv_tr_ops
= {
1271 .init_disas_context
= riscv_tr_init_disas_context
,
1272 .tb_start
= riscv_tr_tb_start
,
1273 .insn_start
= riscv_tr_insn_start
,
1274 .translate_insn
= riscv_tr_translate_insn
,
1275 .tb_stop
= riscv_tr_tb_stop
,
1276 .disas_log
= riscv_tr_disas_log
,
1279 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
1280 target_ulong pc
, void *host_pc
)
1284 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &riscv_tr_ops
, &ctx
.base
);
1287 void riscv_translate_init(void)
1292 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1293 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1294 * unless you specifically block reads/writes to reg 0.
1299 for (i
= 1; i
< 32; i
++) {
1300 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
1301 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
1302 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
1303 offsetof(CPURISCVState
, gprh
[i
]), riscv_int_regnamesh
[i
]);
1306 for (i
= 0; i
< 32; i
++) {
1307 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
1308 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
1311 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
1312 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
1313 cpu_vstart
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vstart
),
1315 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
1317 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),
1319 /* Assign PM CSRs to tcg globals */
1320 pm_mask
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmmask
),
1322 pm_base
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmbase
),