2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
33 #include "internals.h"
35 /* global register indices */
36 static TCGv cpu_gpr
[32], cpu_gprh
[32], cpu_pc
, cpu_vl
, cpu_vstart
;
37 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
40 /* globals for PM CSRs */
44 #include "exec/gen-icount.h"
47 * If an operation is being performed on less than TARGET_LONG_BITS,
48 * it may require the inputs to be sign- or zero-extended; which will
49 * depend on the exact operation being performed.
57 typedef struct DisasContext
{
58 DisasContextBase base
;
59 /* pc_succ_insn points to the instruction following base.pc_next */
60 target_ulong pc_succ_insn
;
61 target_ulong priv_ver
;
62 RISCVMXL misa_mxl_max
;
68 uint32_t mstatus_hs_fs
;
69 uint32_t mstatus_hs_vs
;
71 /* Remember the rounding mode encoded in the previous fp instruction,
72 which we have already installed into env->fp_status. Or -1 for
73 no previous fp instruction. Note that we exit the TB when writing
74 to any system register, which includes CSR_FRM, so we do not have
75 to reset this known value. */
79 const RISCVCPUConfig
*cfg_ptr
;
81 /* vector extension */
84 * Encode LMUL to lmul as follows:
102 /* Space for 3 operands plus 1 extra for address computation. */
104 /* Space for 4 operands(1 dest and <=3 src) for float point computation */
107 /* PointerMasking extension */
108 bool pm_mask_enabled
;
109 bool pm_base_enabled
;
110 /* TCG of the current insn_start */
114 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
116 return ctx
->misa_ext
& ext
;
119 static bool always_true_p(DisasContext
*ctx
__attribute__((__unused__
)))
124 #define MATERIALISE_EXT_PREDICATE(ext) \
125 static bool has_ ## ext ## _p(DisasContext *ctx) \
127 return ctx->cfg_ptr->ext_ ## ext ; \
130 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
);
132 #ifdef TARGET_RISCV32
133 #define get_xl(ctx) MXL_RV32
134 #elif defined(CONFIG_USER_ONLY)
135 #define get_xl(ctx) MXL_RV64
137 #define get_xl(ctx) ((ctx)->xl)
140 /* The word size for this machine mode. */
141 static inline int __attribute__((unused
)) get_xlen(DisasContext
*ctx
)
143 return 16 << get_xl(ctx
);
146 /* The operation length, as opposed to the xlen. */
147 #ifdef TARGET_RISCV32
148 #define get_ol(ctx) MXL_RV32
150 #define get_ol(ctx) ((ctx)->ol)
153 static inline int get_olen(DisasContext
*ctx
)
155 return 16 << get_ol(ctx
);
158 /* The maximum register length */
159 #ifdef TARGET_RISCV32
160 #define get_xl_max(ctx) MXL_RV32
162 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
166 * RISC-V requires NaN-boxing of narrower width floating point values.
167 * This applies when a 32-bit value is assigned to a 64-bit FP register.
168 * For consistency and simplicity, we nanbox results even when the RVD
169 * extension is not present.
171 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
173 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
176 static void gen_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
178 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(16, 48));
182 * A narrow n-bit operation, where n < FLEN, checks that input operands
183 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
184 * If so, the least-significant bits of the input are used, otherwise the
185 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
187 * Here, the result is always nan-boxed, even the canonical nan.
189 static void gen_check_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
191 TCGv_i64 t_max
= tcg_const_i64(0xffffffffffff0000ull
);
192 TCGv_i64 t_nan
= tcg_const_i64(0xffffffffffff7e00ull
);
194 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
195 tcg_temp_free_i64(t_max
);
196 tcg_temp_free_i64(t_nan
);
199 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
201 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
202 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
204 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
207 static void gen_set_pc_imm(DisasContext
*ctx
, target_ulong dest
)
209 if (get_xl(ctx
) == MXL_RV32
) {
210 dest
= (int32_t)dest
;
212 tcg_gen_movi_tl(cpu_pc
, dest
);
215 static void gen_set_pc(DisasContext
*ctx
, TCGv dest
)
217 if (get_xl(ctx
) == MXL_RV32
) {
218 tcg_gen_ext32s_tl(cpu_pc
, dest
);
220 tcg_gen_mov_tl(cpu_pc
, dest
);
224 static void generate_exception(DisasContext
*ctx
, int excp
)
226 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
227 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
228 ctx
->base
.is_jmp
= DISAS_NORETURN
;
231 static void generate_exception_mtval(DisasContext
*ctx
, int excp
)
233 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
234 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
235 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
236 ctx
->base
.is_jmp
= DISAS_NORETURN
;
239 static void gen_exception_illegal(DisasContext
*ctx
)
241 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
244 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
246 generate_exception_mtval(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
249 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
251 if (translator_use_goto_tb(&ctx
->base
, dest
)) {
253 gen_set_pc_imm(ctx
, dest
);
254 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
256 gen_set_pc_imm(ctx
, dest
);
257 tcg_gen_lookup_and_goto_ptr();
262 * Wrappers for getting reg values.
264 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
265 * constant zero as a source, and an uninitialized sink as destination.
267 * Further, we may provide an extension for word operations.
269 static TCGv
temp_new(DisasContext
*ctx
)
271 assert(ctx
->ntemp
< ARRAY_SIZE(ctx
->temp
));
272 return ctx
->temp
[ctx
->ntemp
++] = tcg_temp_new();
275 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
283 switch (get_ol(ctx
)) {
290 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
294 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
297 g_assert_not_reached();
304 g_assert_not_reached();
306 return cpu_gpr
[reg_num
];
309 static TCGv
get_gprh(DisasContext
*ctx
, int reg_num
)
311 assert(get_xl(ctx
) == MXL_RV128
);
315 return cpu_gprh
[reg_num
];
318 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
320 if (reg_num
== 0 || get_olen(ctx
) < TARGET_LONG_BITS
) {
321 return temp_new(ctx
);
323 return cpu_gpr
[reg_num
];
326 static TCGv
dest_gprh(DisasContext
*ctx
, int reg_num
)
329 return temp_new(ctx
);
331 return cpu_gprh
[reg_num
];
334 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
337 switch (get_ol(ctx
)) {
339 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
343 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
346 g_assert_not_reached();
349 if (get_xl_max(ctx
) == MXL_RV128
) {
350 tcg_gen_sari_tl(cpu_gprh
[reg_num
], cpu_gpr
[reg_num
], 63);
355 static void gen_set_gpri(DisasContext
*ctx
, int reg_num
, target_long imm
)
358 switch (get_ol(ctx
)) {
360 tcg_gen_movi_tl(cpu_gpr
[reg_num
], (int32_t)imm
);
364 tcg_gen_movi_tl(cpu_gpr
[reg_num
], imm
);
367 g_assert_not_reached();
370 if (get_xl_max(ctx
) == MXL_RV128
) {
371 tcg_gen_movi_tl(cpu_gprh
[reg_num
], -(imm
< 0));
376 static void gen_set_gpr128(DisasContext
*ctx
, int reg_num
, TCGv rl
, TCGv rh
)
378 assert(get_ol(ctx
) == MXL_RV128
);
380 tcg_gen_mov_tl(cpu_gpr
[reg_num
], rl
);
381 tcg_gen_mov_tl(cpu_gprh
[reg_num
], rh
);
385 static TCGv_i64
ftemp_new(DisasContext
*ctx
)
387 assert(ctx
->nftemp
< ARRAY_SIZE(ctx
->ftemp
));
388 return ctx
->ftemp
[ctx
->nftemp
++] = tcg_temp_new_i64();
391 static TCGv_i64
get_fpr_hs(DisasContext
*ctx
, int reg_num
)
393 if (!ctx
->cfg_ptr
->ext_zfinx
) {
394 return cpu_fpr
[reg_num
];
398 return tcg_constant_i64(0);
400 switch (get_xl(ctx
)) {
402 #ifdef TARGET_RISCV32
404 TCGv_i64 t
= ftemp_new(ctx
);
405 tcg_gen_ext_i32_i64(t
, cpu_gpr
[reg_num
]);
411 return cpu_gpr
[reg_num
];
414 g_assert_not_reached();
418 static TCGv_i64
get_fpr_d(DisasContext
*ctx
, int reg_num
)
420 if (!ctx
->cfg_ptr
->ext_zfinx
) {
421 return cpu_fpr
[reg_num
];
425 return tcg_constant_i64(0);
427 switch (get_xl(ctx
)) {
430 TCGv_i64 t
= ftemp_new(ctx
);
431 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1]);
434 #ifdef TARGET_RISCV64
436 return cpu_gpr
[reg_num
];
439 g_assert_not_reached();
443 static TCGv_i64
dest_fpr(DisasContext
*ctx
, int reg_num
)
445 if (!ctx
->cfg_ptr
->ext_zfinx
) {
446 return cpu_fpr
[reg_num
];
450 return ftemp_new(ctx
);
453 switch (get_xl(ctx
)) {
455 return ftemp_new(ctx
);
456 #ifdef TARGET_RISCV64
458 return cpu_gpr
[reg_num
];
461 g_assert_not_reached();
465 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
466 static void gen_set_fpr_hs(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
468 if (!ctx
->cfg_ptr
->ext_zfinx
) {
469 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
473 switch (get_xl(ctx
)) {
475 #ifdef TARGET_RISCV32
476 tcg_gen_extrl_i64_i32(cpu_gpr
[reg_num
], t
);
481 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
485 g_assert_not_reached();
490 static void gen_set_fpr_d(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
492 if (!ctx
->cfg_ptr
->ext_zfinx
) {
493 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
498 switch (get_xl(ctx
)) {
500 #ifdef TARGET_RISCV32
501 tcg_gen_extr_i64_i32(cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1], t
);
504 tcg_gen_ext32s_i64(cpu_gpr
[reg_num
], t
);
505 tcg_gen_sari_i64(cpu_gpr
[reg_num
+ 1], t
, 32);
508 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
512 g_assert_not_reached();
517 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
519 target_ulong next_pc
;
521 /* check misaligned: */
522 next_pc
= ctx
->base
.pc_next
+ imm
;
523 if (!has_ext(ctx
, RVC
)) {
524 if ((next_pc
& 0x3) != 0) {
525 gen_exception_inst_addr_mis(ctx
);
530 gen_set_gpri(ctx
, rd
, ctx
->pc_succ_insn
);
531 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
532 ctx
->base
.is_jmp
= DISAS_NORETURN
;
535 /* Compute a canonical address from a register plus offset. */
536 static TCGv
get_address(DisasContext
*ctx
, int rs1
, int imm
)
538 TCGv addr
= temp_new(ctx
);
539 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
541 tcg_gen_addi_tl(addr
, src1
, imm
);
542 if (ctx
->pm_mask_enabled
) {
543 tcg_gen_and_tl(addr
, addr
, pm_mask
);
544 } else if (get_xl(ctx
) == MXL_RV32
) {
545 tcg_gen_ext32u_tl(addr
, addr
);
547 if (ctx
->pm_base_enabled
) {
548 tcg_gen_or_tl(addr
, addr
, pm_base
);
553 #ifndef CONFIG_USER_ONLY
554 /* The states of mstatus_fs are:
555 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
556 * We will have already diagnosed disabled state,
557 * and need to turn initial/clean into dirty.
559 static void mark_fs_dirty(DisasContext
*ctx
)
563 if (!has_ext(ctx
, RVF
)) {
567 if (ctx
->mstatus_fs
!= MSTATUS_FS
) {
568 /* Remember the state change for the rest of the TB. */
569 ctx
->mstatus_fs
= MSTATUS_FS
;
571 tmp
= tcg_temp_new();
572 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
573 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
574 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
578 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_fs
!= MSTATUS_FS
) {
579 /* Remember the stage change for the rest of the TB. */
580 ctx
->mstatus_hs_fs
= MSTATUS_FS
;
582 tmp
= tcg_temp_new();
583 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
584 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
585 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
590 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
593 #ifndef CONFIG_USER_ONLY
594 /* The states of mstatus_vs are:
595 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
596 * We will have already diagnosed disabled state,
597 * and need to turn initial/clean into dirty.
599 static void mark_vs_dirty(DisasContext
*ctx
)
603 if (ctx
->mstatus_vs
!= MSTATUS_VS
) {
604 /* Remember the state change for the rest of the TB. */
605 ctx
->mstatus_vs
= MSTATUS_VS
;
607 tmp
= tcg_temp_new();
608 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
609 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
610 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
614 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_vs
!= MSTATUS_VS
) {
615 /* Remember the stage change for the rest of the TB. */
616 ctx
->mstatus_hs_vs
= MSTATUS_VS
;
618 tmp
= tcg_temp_new();
619 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
620 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
621 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
626 static inline void mark_vs_dirty(DisasContext
*ctx
) { }
629 static void gen_set_rm(DisasContext
*ctx
, int rm
)
631 if (ctx
->frm
== rm
) {
636 if (rm
== RISCV_FRM_ROD
) {
637 gen_helper_set_rod_rounding_mode(cpu_env
);
641 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
644 static int ex_plus_1(DisasContext
*ctx
, int nf
)
649 #define EX_SH(amount) \
650 static int ex_shift_##amount(DisasContext *ctx, int imm) \
652 return imm << amount; \
660 #define REQUIRE_EXT(ctx, ext) do { \
661 if (!has_ext(ctx, ext)) { \
666 #define REQUIRE_32BIT(ctx) do { \
667 if (get_xl(ctx) != MXL_RV32) { \
672 #define REQUIRE_64BIT(ctx) do { \
673 if (get_xl(ctx) != MXL_RV64) { \
678 #define REQUIRE_128BIT(ctx) do { \
679 if (get_xl(ctx) != MXL_RV128) { \
684 #define REQUIRE_64_OR_128BIT(ctx) do { \
685 if (get_xl(ctx) == MXL_RV32) { \
690 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \
691 if (!ctx->cfg_ptr->ext_##A && \
692 !ctx->cfg_ptr->ext_##B) { \
697 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
702 static int ex_rvc_shifti(DisasContext
*ctx
, int imm
)
704 /* For RV128 a shamt of 0 means a shift by 64. */
705 return imm
? imm
: 64;
708 /* Include the auto-generated decoder for 32 bit insn */
709 #include "decode-insn32.c.inc"
711 static bool gen_logic_imm_fn(DisasContext
*ctx
, arg_i
*a
,
712 void (*func
)(TCGv
, TCGv
, target_long
))
714 TCGv dest
= dest_gpr(ctx
, a
->rd
);
715 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
717 func(dest
, src1
, a
->imm
);
719 if (get_xl(ctx
) == MXL_RV128
) {
720 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
721 TCGv desth
= dest_gprh(ctx
, a
->rd
);
723 func(desth
, src1h
, -(a
->imm
< 0));
724 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
726 gen_set_gpr(ctx
, a
->rd
, dest
);
732 static bool gen_logic(DisasContext
*ctx
, arg_r
*a
,
733 void (*func
)(TCGv
, TCGv
, TCGv
))
735 TCGv dest
= dest_gpr(ctx
, a
->rd
);
736 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
737 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
739 func(dest
, src1
, src2
);
741 if (get_xl(ctx
) == MXL_RV128
) {
742 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
743 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
744 TCGv desth
= dest_gprh(ctx
, a
->rd
);
746 func(desth
, src1h
, src2h
);
747 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
749 gen_set_gpr(ctx
, a
->rd
, dest
);
755 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
756 void (*func
)(TCGv
, TCGv
, target_long
),
757 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
759 TCGv dest
= dest_gpr(ctx
, a
->rd
);
760 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
762 if (get_ol(ctx
) < MXL_RV128
) {
763 func(dest
, src1
, a
->imm
);
764 gen_set_gpr(ctx
, a
->rd
, dest
);
770 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
771 TCGv desth
= dest_gprh(ctx
, a
->rd
);
773 f128(dest
, desth
, src1
, src1h
, a
->imm
);
774 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
779 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
780 void (*func
)(TCGv
, TCGv
, TCGv
),
781 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
783 TCGv dest
= dest_gpr(ctx
, a
->rd
);
784 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
785 TCGv src2
= tcg_constant_tl(a
->imm
);
787 if (get_ol(ctx
) < MXL_RV128
) {
788 func(dest
, src1
, src2
);
789 gen_set_gpr(ctx
, a
->rd
, dest
);
795 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
796 TCGv src2h
= tcg_constant_tl(-(a
->imm
< 0));
797 TCGv desth
= dest_gprh(ctx
, a
->rd
);
799 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
800 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
805 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
806 void (*func
)(TCGv
, TCGv
, TCGv
),
807 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
809 TCGv dest
= dest_gpr(ctx
, a
->rd
);
810 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
811 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
813 if (get_ol(ctx
) < MXL_RV128
) {
814 func(dest
, src1
, src2
);
815 gen_set_gpr(ctx
, a
->rd
, dest
);
821 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
822 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
823 TCGv desth
= dest_gprh(ctx
, a
->rd
);
825 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
826 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
831 static bool gen_arith_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
832 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
833 void (*f_32
)(TCGv
, TCGv
, TCGv
),
834 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
836 int olen
= get_olen(ctx
);
838 if (olen
!= TARGET_LONG_BITS
) {
841 } else if (olen
!= 128) {
842 g_assert_not_reached();
845 return gen_arith(ctx
, a
, ext
, f_tl
, f_128
);
848 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
849 void (*func
)(TCGv
, TCGv
, target_long
),
850 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
853 int max_len
= get_olen(ctx
);
855 if (a
->shamt
>= max_len
) {
859 dest
= dest_gpr(ctx
, a
->rd
);
860 src1
= get_gpr(ctx
, a
->rs1
, ext
);
863 func(dest
, src1
, a
->shamt
);
864 gen_set_gpr(ctx
, a
->rd
, dest
);
866 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
867 TCGv desth
= dest_gprh(ctx
, a
->rd
);
872 f128(dest
, desth
, src1
, src1h
, a
->shamt
);
873 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
878 static bool gen_shift_imm_fn_per_ol(DisasContext
*ctx
, arg_shift
*a
,
880 void (*f_tl
)(TCGv
, TCGv
, target_long
),
881 void (*f_32
)(TCGv
, TCGv
, target_long
),
882 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
,
885 int olen
= get_olen(ctx
);
886 if (olen
!= TARGET_LONG_BITS
) {
889 } else if (olen
!= 128) {
890 g_assert_not_reached();
893 return gen_shift_imm_fn(ctx
, a
, ext
, f_tl
, f_128
);
896 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
897 void (*func
)(TCGv
, TCGv
, TCGv
))
899 TCGv dest
, src1
, src2
;
900 int max_len
= get_olen(ctx
);
902 if (a
->shamt
>= max_len
) {
906 dest
= dest_gpr(ctx
, a
->rd
);
907 src1
= get_gpr(ctx
, a
->rs1
, ext
);
908 src2
= tcg_constant_tl(a
->shamt
);
910 func(dest
, src1
, src2
);
912 gen_set_gpr(ctx
, a
->rd
, dest
);
916 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
917 void (*func
)(TCGv
, TCGv
, TCGv
),
918 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
920 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
921 TCGv ext2
= tcg_temp_new();
922 int max_len
= get_olen(ctx
);
924 tcg_gen_andi_tl(ext2
, src2
, max_len
- 1);
926 TCGv dest
= dest_gpr(ctx
, a
->rd
);
927 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
930 func(dest
, src1
, ext2
);
931 gen_set_gpr(ctx
, a
->rd
, dest
);
933 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
934 TCGv desth
= dest_gprh(ctx
, a
->rd
);
939 f128(dest
, desth
, src1
, src1h
, ext2
);
940 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
946 static bool gen_shift_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
947 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
948 void (*f_32
)(TCGv
, TCGv
, TCGv
),
949 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
951 int olen
= get_olen(ctx
);
952 if (olen
!= TARGET_LONG_BITS
) {
955 } else if (olen
!= 128) {
956 g_assert_not_reached();
959 return gen_shift(ctx
, a
, ext
, f_tl
, f_128
);
962 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
963 void (*func
)(TCGv
, TCGv
))
965 TCGv dest
= dest_gpr(ctx
, a
->rd
);
966 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
970 gen_set_gpr(ctx
, a
->rd
, dest
);
974 static bool gen_unary_per_ol(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
975 void (*f_tl
)(TCGv
, TCGv
),
976 void (*f_32
)(TCGv
, TCGv
))
978 int olen
= get_olen(ctx
);
980 if (olen
!= TARGET_LONG_BITS
) {
984 g_assert_not_reached();
987 return gen_unary(ctx
, a
, ext
, f_tl
);
990 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
992 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
993 CPUState
*cpu
= ctx
->cs
;
994 CPURISCVState
*env
= cpu
->env_ptr
;
996 return cpu_ldl_code(env
, pc
);
999 /* Include insn module translation function */
1000 #include "insn_trans/trans_rvi.c.inc"
1001 #include "insn_trans/trans_rvm.c.inc"
1002 #include "insn_trans/trans_rva.c.inc"
1003 #include "insn_trans/trans_rvf.c.inc"
1004 #include "insn_trans/trans_rvd.c.inc"
1005 #include "insn_trans/trans_rvh.c.inc"
1006 #include "insn_trans/trans_rvv.c.inc"
1007 #include "insn_trans/trans_rvb.c.inc"
1008 #include "insn_trans/trans_rvzfh.c.inc"
1009 #include "insn_trans/trans_rvk.c.inc"
1010 #include "insn_trans/trans_privileged.c.inc"
1011 #include "insn_trans/trans_svinval.c.inc"
1012 #include "insn_trans/trans_xventanacondops.c.inc"
1014 /* Include the auto-generated decoder for 16 bit insn */
1015 #include "decode-insn16.c.inc"
1016 /* Include decoders for factored-out extensions */
1017 #include "decode-XVentanaCondOps.c.inc"
1019 static inline void decode_save_opc(DisasContext
*ctx
, target_ulong opc
)
1021 assert(ctx
->insn_start
!= NULL
);
1022 tcg_set_insn_start_param(ctx
->insn_start
, 1, opc
);
1023 ctx
->insn_start
= NULL
;
1026 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
1029 * A table with predicate (i.e., guard) functions and decoder functions
1030 * that are tested in-order until a decoder matches onto the opcode.
1032 static const struct {
1033 bool (*guard_func
)(DisasContext
*);
1034 bool (*decode_func
)(DisasContext
*, uint32_t);
1036 { always_true_p
, decode_insn32
},
1037 { has_XVentanaCondOps_p
, decode_XVentanaCodeOps
},
1040 /* Check for compressed insn */
1041 if (extract16(opcode
, 0, 2) != 3) {
1042 decode_save_opc(ctx
, opcode
);
1043 if (!has_ext(ctx
, RVC
)) {
1044 gen_exception_illegal(ctx
);
1046 ctx
->opcode
= opcode
;
1047 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
1048 if (decode_insn16(ctx
, opcode
)) {
1053 uint32_t opcode32
= opcode
;
1054 opcode32
= deposit32(opcode32
, 16, 16,
1055 translator_lduw(env
, &ctx
->base
,
1056 ctx
->base
.pc_next
+ 2));
1057 decode_save_opc(ctx
, opcode32
);
1058 ctx
->opcode
= opcode32
;
1059 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
1061 for (size_t i
= 0; i
< ARRAY_SIZE(decoders
); ++i
) {
1062 if (decoders
[i
].guard_func(ctx
) &&
1063 decoders
[i
].decode_func(ctx
, opcode32
)) {
1069 gen_exception_illegal(ctx
);
1072 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
1074 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1075 CPURISCVState
*env
= cs
->env_ptr
;
1076 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1077 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
1079 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
1080 ctx
->mem_idx
= FIELD_EX32(tb_flags
, TB_FLAGS
, MEM_IDX
);
1081 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
1082 ctx
->mstatus_vs
= tb_flags
& TB_FLAGS_MSTATUS_VS
;
1083 ctx
->priv_ver
= env
->priv_ver
;
1084 #if !defined(CONFIG_USER_ONLY)
1085 if (riscv_has_ext(env
, RVH
)) {
1086 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
1088 ctx
->virt_enabled
= false;
1091 ctx
->virt_enabled
= false;
1093 ctx
->misa_ext
= env
->misa_ext
;
1094 ctx
->frm
= -1; /* unknown rounding mode */
1095 ctx
->cfg_ptr
= &(cpu
->cfg
);
1096 ctx
->mstatus_hs_fs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_FS
);
1097 ctx
->mstatus_hs_vs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_VS
);
1098 ctx
->hlsx
= FIELD_EX32(tb_flags
, TB_FLAGS
, HLSX
);
1099 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
1100 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
1101 ctx
->lmul
= sextract32(FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
), 0, 3);
1102 ctx
->vstart
= env
->vstart
;
1103 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
1104 ctx
->misa_mxl_max
= env
->misa_mxl_max
;
1105 ctx
->xl
= FIELD_EX32(tb_flags
, TB_FLAGS
, XL
);
1108 memset(ctx
->temp
, 0, sizeof(ctx
->temp
));
1110 memset(ctx
->ftemp
, 0, sizeof(ctx
->ftemp
));
1111 ctx
->pm_mask_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_MASK_ENABLED
);
1112 ctx
->pm_base_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_BASE_ENABLED
);
1113 ctx
->zero
= tcg_constant_tl(0);
1116 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
1120 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1122 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1124 tcg_gen_insn_start(ctx
->base
.pc_next
, 0);
1125 ctx
->insn_start
= tcg_last_op();
1128 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1130 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1131 CPURISCVState
*env
= cpu
->env_ptr
;
1132 uint16_t opcode16
= translator_lduw(env
, &ctx
->base
, ctx
->base
.pc_next
);
1136 decode_opc(env
, ctx
, opcode16
);
1137 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
1139 for (i
= ctx
->ntemp
- 1; i
>= 0; --i
) {
1140 tcg_temp_free(ctx
->temp
[i
]);
1141 ctx
->temp
[i
] = NULL
;
1144 for (i
= ctx
->nftemp
- 1; i
>= 0; --i
) {
1145 tcg_temp_free_i64(ctx
->ftemp
[i
]);
1146 ctx
->ftemp
[i
] = NULL
;
1150 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
1151 target_ulong page_start
;
1153 page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
1154 if (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
) {
1155 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1160 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1162 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1164 switch (ctx
->base
.is_jmp
) {
1165 case DISAS_TOO_MANY
:
1166 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1168 case DISAS_NORETURN
:
1171 g_assert_not_reached();
1175 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
,
1176 CPUState
*cpu
, FILE *logfile
)
1178 #ifndef CONFIG_USER_ONLY
1179 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
1180 CPURISCVState
*env
= &rvcpu
->env
;
1183 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1184 #ifndef CONFIG_USER_ONLY
1185 fprintf(logfile
, "Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n",
1186 env
->priv
, env
->virt
);
1188 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1191 static const TranslatorOps riscv_tr_ops
= {
1192 .init_disas_context
= riscv_tr_init_disas_context
,
1193 .tb_start
= riscv_tr_tb_start
,
1194 .insn_start
= riscv_tr_insn_start
,
1195 .translate_insn
= riscv_tr_translate_insn
,
1196 .tb_stop
= riscv_tr_tb_stop
,
1197 .disas_log
= riscv_tr_disas_log
,
1200 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
1204 translator_loop(&riscv_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
1207 void riscv_translate_init(void)
1212 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1213 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1214 * unless you specifically block reads/writes to reg 0.
1219 for (i
= 1; i
< 32; i
++) {
1220 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
1221 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
1222 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
1223 offsetof(CPURISCVState
, gprh
[i
]), riscv_int_regnamesh
[i
]);
1226 for (i
= 0; i
< 32; i
++) {
1227 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
1228 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
1231 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
1232 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
1233 cpu_vstart
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vstart
),
1235 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
1237 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),
1239 /* Assign PM CSRs to tcg globals */
1240 pm_mask
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmmask
),
1242 pm_base
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmbase
),