2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
31 #include "semihosting/semihost.h"
34 #include "internals.h"
36 /* global register indices */
37 static TCGv cpu_gpr
[32], cpu_gprh
[32], cpu_pc
, cpu_vl
, cpu_vstart
;
38 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
41 /* globals for PM CSRs */
45 #include "exec/gen-icount.h"
48 * If an operation is being performed on less than TARGET_LONG_BITS,
49 * it may require the inputs to be sign- or zero-extended; which will
50 * depend on the exact operation being performed.
58 typedef struct DisasContext
{
59 DisasContextBase base
;
60 /* pc_succ_insn points to the instruction following base.pc_next */
61 target_ulong pc_succ_insn
;
62 target_ulong priv_ver
;
63 RISCVMXL misa_mxl_max
;
69 uint32_t mstatus_hs_fs
;
70 uint32_t mstatus_hs_vs
;
72 /* Remember the rounding mode encoded in the previous fp instruction,
73 which we have already installed into env->fp_status. Or -1 for
74 no previous fp instruction. Note that we exit the TB when writing
75 to any system register, which includes CSR_FRM, so we do not have
76 to reset this known value. */
81 const RISCVCPUConfig
*cfg_ptr
;
83 /* vector extension */
86 * Encode LMUL to lmul as follows:
106 /* PointerMasking extension */
107 bool pm_mask_enabled
;
108 bool pm_base_enabled
;
109 /* Use icount trigger for native debug */
111 /* FRM is known to contain a valid value. */
113 /* TCG of the current insn_start */
117 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
119 return ctx
->misa_ext
& ext
;
122 static bool always_true_p(DisasContext
*ctx
__attribute__((__unused__
)))
127 static bool has_xthead_p(DisasContext
*ctx
__attribute__((__unused__
)))
129 return ctx
->cfg_ptr
->ext_xtheadba
|| ctx
->cfg_ptr
->ext_xtheadbb
||
130 ctx
->cfg_ptr
->ext_xtheadbs
|| ctx
->cfg_ptr
->ext_xtheadcmo
||
131 ctx
->cfg_ptr
->ext_xtheadcondmov
||
132 ctx
->cfg_ptr
->ext_xtheadfmemidx
|| ctx
->cfg_ptr
->ext_xtheadfmv
||
133 ctx
->cfg_ptr
->ext_xtheadmac
|| ctx
->cfg_ptr
->ext_xtheadmemidx
||
134 ctx
->cfg_ptr
->ext_xtheadmempair
|| ctx
->cfg_ptr
->ext_xtheadsync
;
137 #define MATERIALISE_EXT_PREDICATE(ext) \
138 static bool has_ ## ext ## _p(DisasContext *ctx) \
140 return ctx->cfg_ptr->ext_ ## ext ; \
143 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
);
145 #ifdef TARGET_RISCV32
146 #define get_xl(ctx) MXL_RV32
147 #elif defined(CONFIG_USER_ONLY)
148 #define get_xl(ctx) MXL_RV64
150 #define get_xl(ctx) ((ctx)->xl)
153 /* The word size for this machine mode. */
154 static inline int __attribute__((unused
)) get_xlen(DisasContext
*ctx
)
156 return 16 << get_xl(ctx
);
159 /* The operation length, as opposed to the xlen. */
160 #ifdef TARGET_RISCV32
161 #define get_ol(ctx) MXL_RV32
163 #define get_ol(ctx) ((ctx)->ol)
166 static inline int get_olen(DisasContext
*ctx
)
168 return 16 << get_ol(ctx
);
171 /* The maximum register length */
172 #ifdef TARGET_RISCV32
173 #define get_xl_max(ctx) MXL_RV32
175 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
179 * RISC-V requires NaN-boxing of narrower width floating point values.
180 * This applies when a 32-bit value is assigned to a 64-bit FP register.
181 * For consistency and simplicity, we nanbox results even when the RVD
182 * extension is not present.
184 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
186 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
189 static void gen_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
191 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(16, 48));
195 * A narrow n-bit operation, where n < FLEN, checks that input operands
196 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
197 * If so, the least-significant bits of the input are used, otherwise the
198 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
200 * Here, the result is always nan-boxed, even the canonical nan.
202 static void gen_check_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
204 TCGv_i64 t_max
= tcg_constant_i64(0xffffffffffff0000ull
);
205 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffffffff7e00ull
);
207 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
210 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
212 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
213 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
215 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
218 static void decode_save_opc(DisasContext
*ctx
)
220 assert(ctx
->insn_start
!= NULL
);
221 tcg_set_insn_start_param(ctx
->insn_start
, 1, ctx
->opcode
);
222 ctx
->insn_start
= NULL
;
225 static void gen_set_pc_imm(DisasContext
*ctx
, target_ulong dest
)
227 if (get_xl(ctx
) == MXL_RV32
) {
228 dest
= (int32_t)dest
;
230 tcg_gen_movi_tl(cpu_pc
, dest
);
233 static void gen_set_pc(DisasContext
*ctx
, TCGv dest
)
235 if (get_xl(ctx
) == MXL_RV32
) {
236 tcg_gen_ext32s_tl(cpu_pc
, dest
);
238 tcg_gen_mov_tl(cpu_pc
, dest
);
242 static void generate_exception(DisasContext
*ctx
, int excp
)
244 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
245 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
246 ctx
->base
.is_jmp
= DISAS_NORETURN
;
249 static void gen_exception_illegal(DisasContext
*ctx
)
251 tcg_gen_st_i32(tcg_constant_i32(ctx
->opcode
), cpu_env
,
252 offsetof(CPURISCVState
, bins
));
253 if (ctx
->virt_inst_excp
) {
254 generate_exception(ctx
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
);
256 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
260 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
262 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
263 generate_exception(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
266 static void lookup_and_goto_ptr(DisasContext
*ctx
)
268 #ifndef CONFIG_USER_ONLY
270 gen_helper_itrigger_match(cpu_env
);
273 tcg_gen_lookup_and_goto_ptr();
276 static void exit_tb(DisasContext
*ctx
)
278 #ifndef CONFIG_USER_ONLY
280 gen_helper_itrigger_match(cpu_env
);
283 tcg_gen_exit_tb(NULL
, 0);
286 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
289 * Under itrigger, instruction executes one by one like singlestep,
290 * direct block chain benefits will be small.
292 if (translator_use_goto_tb(&ctx
->base
, dest
) && !ctx
->itrigger
) {
294 gen_set_pc_imm(ctx
, dest
);
295 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
297 gen_set_pc_imm(ctx
, dest
);
298 lookup_and_goto_ptr(ctx
);
303 * Wrappers for getting reg values.
305 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
306 * constant zero as a source, and an uninitialized sink as destination.
308 * Further, we may provide an extension for word operations.
310 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
318 switch (get_ol(ctx
)) {
325 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
329 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
332 g_assert_not_reached();
339 g_assert_not_reached();
341 return cpu_gpr
[reg_num
];
344 static TCGv
get_gprh(DisasContext
*ctx
, int reg_num
)
346 assert(get_xl(ctx
) == MXL_RV128
);
350 return cpu_gprh
[reg_num
];
353 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
355 if (reg_num
== 0 || get_olen(ctx
) < TARGET_LONG_BITS
) {
356 return tcg_temp_new();
358 return cpu_gpr
[reg_num
];
361 static TCGv
dest_gprh(DisasContext
*ctx
, int reg_num
)
364 return tcg_temp_new();
366 return cpu_gprh
[reg_num
];
369 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
372 switch (get_ol(ctx
)) {
374 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
378 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
381 g_assert_not_reached();
384 if (get_xl_max(ctx
) == MXL_RV128
) {
385 tcg_gen_sari_tl(cpu_gprh
[reg_num
], cpu_gpr
[reg_num
], 63);
390 static void gen_set_gpri(DisasContext
*ctx
, int reg_num
, target_long imm
)
393 switch (get_ol(ctx
)) {
395 tcg_gen_movi_tl(cpu_gpr
[reg_num
], (int32_t)imm
);
399 tcg_gen_movi_tl(cpu_gpr
[reg_num
], imm
);
402 g_assert_not_reached();
405 if (get_xl_max(ctx
) == MXL_RV128
) {
406 tcg_gen_movi_tl(cpu_gprh
[reg_num
], -(imm
< 0));
411 static void gen_set_gpr128(DisasContext
*ctx
, int reg_num
, TCGv rl
, TCGv rh
)
413 assert(get_ol(ctx
) == MXL_RV128
);
415 tcg_gen_mov_tl(cpu_gpr
[reg_num
], rl
);
416 tcg_gen_mov_tl(cpu_gprh
[reg_num
], rh
);
420 static TCGv_i64
get_fpr_hs(DisasContext
*ctx
, int reg_num
)
422 if (!ctx
->cfg_ptr
->ext_zfinx
) {
423 return cpu_fpr
[reg_num
];
427 return tcg_constant_i64(0);
429 switch (get_xl(ctx
)) {
431 #ifdef TARGET_RISCV32
433 TCGv_i64 t
= tcg_temp_new_i64();
434 tcg_gen_ext_i32_i64(t
, cpu_gpr
[reg_num
]);
440 return cpu_gpr
[reg_num
];
443 g_assert_not_reached();
447 static TCGv_i64
get_fpr_d(DisasContext
*ctx
, int reg_num
)
449 if (!ctx
->cfg_ptr
->ext_zfinx
) {
450 return cpu_fpr
[reg_num
];
454 return tcg_constant_i64(0);
456 switch (get_xl(ctx
)) {
459 TCGv_i64 t
= tcg_temp_new_i64();
460 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1]);
463 #ifdef TARGET_RISCV64
465 return cpu_gpr
[reg_num
];
468 g_assert_not_reached();
472 static TCGv_i64
dest_fpr(DisasContext
*ctx
, int reg_num
)
474 if (!ctx
->cfg_ptr
->ext_zfinx
) {
475 return cpu_fpr
[reg_num
];
479 return tcg_temp_new_i64();
482 switch (get_xl(ctx
)) {
484 return tcg_temp_new_i64();
485 #ifdef TARGET_RISCV64
487 return cpu_gpr
[reg_num
];
490 g_assert_not_reached();
494 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
495 static void gen_set_fpr_hs(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
497 if (!ctx
->cfg_ptr
->ext_zfinx
) {
498 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
502 switch (get_xl(ctx
)) {
504 #ifdef TARGET_RISCV32
505 tcg_gen_extrl_i64_i32(cpu_gpr
[reg_num
], t
);
510 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
514 g_assert_not_reached();
519 static void gen_set_fpr_d(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
521 if (!ctx
->cfg_ptr
->ext_zfinx
) {
522 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
527 switch (get_xl(ctx
)) {
529 #ifdef TARGET_RISCV32
530 tcg_gen_extr_i64_i32(cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1], t
);
533 tcg_gen_ext32s_i64(cpu_gpr
[reg_num
], t
);
534 tcg_gen_sari_i64(cpu_gpr
[reg_num
+ 1], t
, 32);
537 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
541 g_assert_not_reached();
546 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
548 target_ulong next_pc
;
550 /* check misaligned: */
551 next_pc
= ctx
->base
.pc_next
+ imm
;
552 if (!has_ext(ctx
, RVC
)) {
553 if ((next_pc
& 0x3) != 0) {
554 gen_exception_inst_addr_mis(ctx
);
559 gen_set_gpri(ctx
, rd
, ctx
->pc_succ_insn
);
560 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
561 ctx
->base
.is_jmp
= DISAS_NORETURN
;
564 /* Compute a canonical address from a register plus offset. */
565 static TCGv
get_address(DisasContext
*ctx
, int rs1
, int imm
)
567 TCGv addr
= tcg_temp_new();
568 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
570 tcg_gen_addi_tl(addr
, src1
, imm
);
571 if (ctx
->pm_mask_enabled
) {
572 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
573 } else if (get_xl(ctx
) == MXL_RV32
) {
574 tcg_gen_ext32u_tl(addr
, addr
);
576 if (ctx
->pm_base_enabled
) {
577 tcg_gen_or_tl(addr
, addr
, pm_base
);
582 /* Compute a canonical address from a register plus reg offset. */
583 static TCGv
get_address_indexed(DisasContext
*ctx
, int rs1
, TCGv offs
)
585 TCGv addr
= tcg_temp_new();
586 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
588 tcg_gen_add_tl(addr
, src1
, offs
);
589 if (ctx
->pm_mask_enabled
) {
590 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
591 } else if (get_xl(ctx
) == MXL_RV32
) {
592 tcg_gen_ext32u_tl(addr
, addr
);
594 if (ctx
->pm_base_enabled
) {
595 tcg_gen_or_tl(addr
, addr
, pm_base
);
600 #ifndef CONFIG_USER_ONLY
601 /* The states of mstatus_fs are:
602 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
603 * We will have already diagnosed disabled state,
604 * and need to turn initial/clean into dirty.
606 static void mark_fs_dirty(DisasContext
*ctx
)
610 if (!has_ext(ctx
, RVF
)) {
614 if (ctx
->mstatus_fs
!= MSTATUS_FS
) {
615 /* Remember the state change for the rest of the TB. */
616 ctx
->mstatus_fs
= MSTATUS_FS
;
618 tmp
= tcg_temp_new();
619 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
620 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
621 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
624 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_fs
!= MSTATUS_FS
) {
625 /* Remember the stage change for the rest of the TB. */
626 ctx
->mstatus_hs_fs
= MSTATUS_FS
;
628 tmp
= tcg_temp_new();
629 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
630 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
631 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
635 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
638 #ifndef CONFIG_USER_ONLY
639 /* The states of mstatus_vs are:
640 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
641 * We will have already diagnosed disabled state,
642 * and need to turn initial/clean into dirty.
644 static void mark_vs_dirty(DisasContext
*ctx
)
648 if (ctx
->mstatus_vs
!= MSTATUS_VS
) {
649 /* Remember the state change for the rest of the TB. */
650 ctx
->mstatus_vs
= MSTATUS_VS
;
652 tmp
= tcg_temp_new();
653 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
654 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
655 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
658 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_vs
!= MSTATUS_VS
) {
659 /* Remember the stage change for the rest of the TB. */
660 ctx
->mstatus_hs_vs
= MSTATUS_VS
;
662 tmp
= tcg_temp_new();
663 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
664 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
665 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
669 static inline void mark_vs_dirty(DisasContext
*ctx
) { }
672 static void gen_set_rm(DisasContext
*ctx
, int rm
)
674 if (ctx
->frm
== rm
) {
679 if (rm
== RISCV_FRM_DYN
) {
680 /* The helper will return only if frm valid. */
681 ctx
->frm_valid
= true;
684 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
685 decode_save_opc(ctx
);
686 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
689 static void gen_set_rm_chkfrm(DisasContext
*ctx
, int rm
)
691 if (ctx
->frm
== rm
&& ctx
->frm_valid
) {
695 ctx
->frm_valid
= true;
697 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
698 decode_save_opc(ctx
);
699 gen_helper_set_rounding_mode_chkfrm(cpu_env
, tcg_constant_i32(rm
));
702 static int ex_plus_1(DisasContext
*ctx
, int nf
)
707 #define EX_SH(amount) \
708 static int ex_shift_##amount(DisasContext *ctx, int imm) \
710 return imm << amount; \
718 #define REQUIRE_EXT(ctx, ext) do { \
719 if (!has_ext(ctx, ext)) { \
724 #define REQUIRE_32BIT(ctx) do { \
725 if (get_xl(ctx) != MXL_RV32) { \
730 #define REQUIRE_64BIT(ctx) do { \
731 if (get_xl(ctx) != MXL_RV64) { \
736 #define REQUIRE_128BIT(ctx) do { \
737 if (get_xl(ctx) != MXL_RV128) { \
742 #define REQUIRE_64_OR_128BIT(ctx) do { \
743 if (get_xl(ctx) == MXL_RV32) { \
748 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \
749 if (!ctx->cfg_ptr->ext_##A && \
750 !ctx->cfg_ptr->ext_##B) { \
755 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
760 static int ex_rvc_shiftli(DisasContext
*ctx
, int imm
)
762 /* For RV128 a shamt of 0 means a shift by 64. */
763 if (get_ol(ctx
) == MXL_RV128
) {
764 imm
= imm
? imm
: 64;
769 static int ex_rvc_shiftri(DisasContext
*ctx
, int imm
)
772 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right
773 * shifts, the shamt is sign-extended.
775 if (get_ol(ctx
) == MXL_RV128
) {
776 imm
= imm
| (imm
& 32) << 1;
777 imm
= imm
? imm
: 64;
782 /* Include the auto-generated decoder for 32 bit insn */
783 #include "decode-insn32.c.inc"
785 static bool gen_logic_imm_fn(DisasContext
*ctx
, arg_i
*a
,
786 void (*func
)(TCGv
, TCGv
, target_long
))
788 TCGv dest
= dest_gpr(ctx
, a
->rd
);
789 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
791 func(dest
, src1
, a
->imm
);
793 if (get_xl(ctx
) == MXL_RV128
) {
794 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
795 TCGv desth
= dest_gprh(ctx
, a
->rd
);
797 func(desth
, src1h
, -(a
->imm
< 0));
798 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
800 gen_set_gpr(ctx
, a
->rd
, dest
);
806 static bool gen_logic(DisasContext
*ctx
, arg_r
*a
,
807 void (*func
)(TCGv
, TCGv
, TCGv
))
809 TCGv dest
= dest_gpr(ctx
, a
->rd
);
810 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
811 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
813 func(dest
, src1
, src2
);
815 if (get_xl(ctx
) == MXL_RV128
) {
816 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
817 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
818 TCGv desth
= dest_gprh(ctx
, a
->rd
);
820 func(desth
, src1h
, src2h
);
821 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
823 gen_set_gpr(ctx
, a
->rd
, dest
);
829 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
830 void (*func
)(TCGv
, TCGv
, target_long
),
831 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
833 TCGv dest
= dest_gpr(ctx
, a
->rd
);
834 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
836 if (get_ol(ctx
) < MXL_RV128
) {
837 func(dest
, src1
, a
->imm
);
838 gen_set_gpr(ctx
, a
->rd
, dest
);
844 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
845 TCGv desth
= dest_gprh(ctx
, a
->rd
);
847 f128(dest
, desth
, src1
, src1h
, a
->imm
);
848 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
853 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
854 void (*func
)(TCGv
, TCGv
, TCGv
),
855 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
857 TCGv dest
= dest_gpr(ctx
, a
->rd
);
858 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
859 TCGv src2
= tcg_constant_tl(a
->imm
);
861 if (get_ol(ctx
) < MXL_RV128
) {
862 func(dest
, src1
, src2
);
863 gen_set_gpr(ctx
, a
->rd
, dest
);
869 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
870 TCGv src2h
= tcg_constant_tl(-(a
->imm
< 0));
871 TCGv desth
= dest_gprh(ctx
, a
->rd
);
873 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
874 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
879 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
880 void (*func
)(TCGv
, TCGv
, TCGv
),
881 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
883 TCGv dest
= dest_gpr(ctx
, a
->rd
);
884 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
885 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
887 if (get_ol(ctx
) < MXL_RV128
) {
888 func(dest
, src1
, src2
);
889 gen_set_gpr(ctx
, a
->rd
, dest
);
895 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
896 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
897 TCGv desth
= dest_gprh(ctx
, a
->rd
);
899 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
900 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
905 static bool gen_arith_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
906 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
907 void (*f_32
)(TCGv
, TCGv
, TCGv
),
908 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
910 int olen
= get_olen(ctx
);
912 if (olen
!= TARGET_LONG_BITS
) {
915 } else if (olen
!= 128) {
916 g_assert_not_reached();
919 return gen_arith(ctx
, a
, ext
, f_tl
, f_128
);
922 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
923 void (*func
)(TCGv
, TCGv
, target_long
),
924 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
927 int max_len
= get_olen(ctx
);
929 if (a
->shamt
>= max_len
) {
933 dest
= dest_gpr(ctx
, a
->rd
);
934 src1
= get_gpr(ctx
, a
->rs1
, ext
);
937 func(dest
, src1
, a
->shamt
);
938 gen_set_gpr(ctx
, a
->rd
, dest
);
940 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
941 TCGv desth
= dest_gprh(ctx
, a
->rd
);
946 f128(dest
, desth
, src1
, src1h
, a
->shamt
);
947 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
952 static bool gen_shift_imm_fn_per_ol(DisasContext
*ctx
, arg_shift
*a
,
954 void (*f_tl
)(TCGv
, TCGv
, target_long
),
955 void (*f_32
)(TCGv
, TCGv
, target_long
),
956 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
,
959 int olen
= get_olen(ctx
);
960 if (olen
!= TARGET_LONG_BITS
) {
963 } else if (olen
!= 128) {
964 g_assert_not_reached();
967 return gen_shift_imm_fn(ctx
, a
, ext
, f_tl
, f_128
);
970 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
971 void (*func
)(TCGv
, TCGv
, TCGv
))
973 TCGv dest
, src1
, src2
;
974 int max_len
= get_olen(ctx
);
976 if (a
->shamt
>= max_len
) {
980 dest
= dest_gpr(ctx
, a
->rd
);
981 src1
= get_gpr(ctx
, a
->rs1
, ext
);
982 src2
= tcg_constant_tl(a
->shamt
);
984 func(dest
, src1
, src2
);
986 gen_set_gpr(ctx
, a
->rd
, dest
);
990 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
991 void (*func
)(TCGv
, TCGv
, TCGv
),
992 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
994 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
995 TCGv ext2
= tcg_temp_new();
996 int max_len
= get_olen(ctx
);
998 tcg_gen_andi_tl(ext2
, src2
, max_len
- 1);
1000 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1001 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1003 if (max_len
< 128) {
1004 func(dest
, src1
, ext2
);
1005 gen_set_gpr(ctx
, a
->rd
, dest
);
1007 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
1008 TCGv desth
= dest_gprh(ctx
, a
->rd
);
1013 f128(dest
, desth
, src1
, src1h
, ext2
);
1014 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
1019 static bool gen_shift_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
1020 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
1021 void (*f_32
)(TCGv
, TCGv
, TCGv
),
1022 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
1024 int olen
= get_olen(ctx
);
1025 if (olen
!= TARGET_LONG_BITS
) {
1028 } else if (olen
!= 128) {
1029 g_assert_not_reached();
1032 return gen_shift(ctx
, a
, ext
, f_tl
, f_128
);
1035 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1036 void (*func
)(TCGv
, TCGv
))
1038 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1039 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1043 gen_set_gpr(ctx
, a
->rd
, dest
);
1047 static bool gen_unary_per_ol(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1048 void (*f_tl
)(TCGv
, TCGv
),
1049 void (*f_32
)(TCGv
, TCGv
))
1051 int olen
= get_olen(ctx
);
1053 if (olen
!= TARGET_LONG_BITS
) {
1057 g_assert_not_reached();
1060 return gen_unary(ctx
, a
, ext
, f_tl
);
1063 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
1065 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1066 CPUState
*cpu
= ctx
->cs
;
1067 CPURISCVState
*env
= cpu
->env_ptr
;
1069 return cpu_ldl_code(env
, pc
);
1072 /* Include insn module translation function */
1073 #include "insn_trans/trans_rvi.c.inc"
1074 #include "insn_trans/trans_rvm.c.inc"
1075 #include "insn_trans/trans_rva.c.inc"
1076 #include "insn_trans/trans_rvf.c.inc"
1077 #include "insn_trans/trans_rvd.c.inc"
1078 #include "insn_trans/trans_rvh.c.inc"
1079 #include "insn_trans/trans_rvv.c.inc"
1080 #include "insn_trans/trans_rvb.c.inc"
1081 #include "insn_trans/trans_rvzicond.c.inc"
1082 #include "insn_trans/trans_rvzawrs.c.inc"
1083 #include "insn_trans/trans_rvzicbo.c.inc"
1084 #include "insn_trans/trans_rvzfh.c.inc"
1085 #include "insn_trans/trans_rvk.c.inc"
1086 #include "insn_trans/trans_privileged.c.inc"
1087 #include "insn_trans/trans_svinval.c.inc"
1088 #include "decode-xthead.c.inc"
1089 #include "insn_trans/trans_xthead.c.inc"
1090 #include "insn_trans/trans_xventanacondops.c.inc"
1092 /* Include the auto-generated decoder for 16 bit insn */
1093 #include "decode-insn16.c.inc"
1094 /* Include decoders for factored-out extensions */
1095 #include "decode-XVentanaCondOps.c.inc"
1097 /* The specification allows for longer insns, but not supported by qemu. */
1098 #define MAX_INSN_LEN 4
1100 static inline int insn_len(uint16_t first_word
)
1102 return (first_word
& 3) == 3 ? 4 : 2;
1105 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
1108 * A table with predicate (i.e., guard) functions and decoder functions
1109 * that are tested in-order until a decoder matches onto the opcode.
1111 static const struct {
1112 bool (*guard_func
)(DisasContext
*);
1113 bool (*decode_func
)(DisasContext
*, uint32_t);
1115 { always_true_p
, decode_insn32
},
1116 { has_xthead_p
, decode_xthead
},
1117 { has_XVentanaCondOps_p
, decode_XVentanaCodeOps
},
1120 ctx
->virt_inst_excp
= false;
1121 /* Check for compressed insn */
1122 if (insn_len(opcode
) == 2) {
1123 ctx
->opcode
= opcode
;
1124 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
1125 if (has_ext(ctx
, RVC
) && decode_insn16(ctx
, opcode
)) {
1129 uint32_t opcode32
= opcode
;
1130 opcode32
= deposit32(opcode32
, 16, 16,
1131 translator_lduw(env
, &ctx
->base
,
1132 ctx
->base
.pc_next
+ 2));
1133 ctx
->opcode
= opcode32
;
1134 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
1136 for (size_t i
= 0; i
< ARRAY_SIZE(decoders
); ++i
) {
1137 if (decoders
[i
].guard_func(ctx
) &&
1138 decoders
[i
].decode_func(ctx
, opcode32
)) {
1144 gen_exception_illegal(ctx
);
1147 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
1149 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1150 CPURISCVState
*env
= cs
->env_ptr
;
1151 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1152 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
1154 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
1155 ctx
->mem_idx
= FIELD_EX32(tb_flags
, TB_FLAGS
, MEM_IDX
);
1156 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
1157 ctx
->mstatus_vs
= tb_flags
& TB_FLAGS_MSTATUS_VS
;
1158 ctx
->priv_ver
= env
->priv_ver
;
1159 #if !defined(CONFIG_USER_ONLY)
1160 if (riscv_has_ext(env
, RVH
)) {
1161 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
1163 ctx
->virt_enabled
= false;
1166 ctx
->virt_enabled
= false;
1168 ctx
->misa_ext
= env
->misa_ext
;
1169 ctx
->frm
= -1; /* unknown rounding mode */
1170 ctx
->cfg_ptr
= &(cpu
->cfg
);
1171 ctx
->mstatus_hs_fs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_FS
);
1172 ctx
->mstatus_hs_vs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_VS
);
1173 ctx
->hlsx
= FIELD_EX32(tb_flags
, TB_FLAGS
, HLSX
);
1174 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
1175 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
1176 ctx
->lmul
= sextract32(FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
), 0, 3);
1177 ctx
->vta
= FIELD_EX32(tb_flags
, TB_FLAGS
, VTA
) && cpu
->cfg
.rvv_ta_all_1s
;
1178 ctx
->vma
= FIELD_EX32(tb_flags
, TB_FLAGS
, VMA
) && cpu
->cfg
.rvv_ma_all_1s
;
1179 ctx
->cfg_vta_all_1s
= cpu
->cfg
.rvv_ta_all_1s
;
1180 ctx
->vstart
= env
->vstart
;
1181 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
1182 ctx
->misa_mxl_max
= env
->misa_mxl_max
;
1183 ctx
->xl
= FIELD_EX32(tb_flags
, TB_FLAGS
, XL
);
1185 ctx
->pm_mask_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_MASK_ENABLED
);
1186 ctx
->pm_base_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_BASE_ENABLED
);
1187 ctx
->itrigger
= FIELD_EX32(tb_flags
, TB_FLAGS
, ITRIGGER
);
1188 ctx
->zero
= tcg_constant_tl(0);
1189 ctx
->virt_inst_excp
= false;
1192 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
1196 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1198 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1200 tcg_gen_insn_start(ctx
->base
.pc_next
, 0);
1201 ctx
->insn_start
= tcg_last_op();
1204 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1206 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1207 CPURISCVState
*env
= cpu
->env_ptr
;
1208 uint16_t opcode16
= translator_lduw(env
, &ctx
->base
, ctx
->base
.pc_next
);
1211 decode_opc(env
, ctx
, opcode16
);
1212 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
1214 /* Only the first insn within a TB is allowed to cross a page boundary. */
1215 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
1216 if (ctx
->itrigger
|| !is_same_page(&ctx
->base
, ctx
->base
.pc_next
)) {
1217 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1219 unsigned page_ofs
= ctx
->base
.pc_next
& ~TARGET_PAGE_MASK
;
1221 if (page_ofs
> TARGET_PAGE_SIZE
- MAX_INSN_LEN
) {
1222 uint16_t next_insn
= cpu_lduw_code(env
, ctx
->base
.pc_next
);
1223 int len
= insn_len(next_insn
);
1225 if (!is_same_page(&ctx
->base
, ctx
->base
.pc_next
+ len
- 1)) {
1226 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1233 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1235 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1237 switch (ctx
->base
.is_jmp
) {
1238 case DISAS_TOO_MANY
:
1239 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1241 case DISAS_NORETURN
:
1244 g_assert_not_reached();
1248 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
,
1249 CPUState
*cpu
, FILE *logfile
)
1251 #ifndef CONFIG_USER_ONLY
1252 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
1253 CPURISCVState
*env
= &rvcpu
->env
;
1256 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1257 #ifndef CONFIG_USER_ONLY
1258 fprintf(logfile
, "Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n",
1259 env
->priv
, env
->virt
);
1261 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1264 static const TranslatorOps riscv_tr_ops
= {
1265 .init_disas_context
= riscv_tr_init_disas_context
,
1266 .tb_start
= riscv_tr_tb_start
,
1267 .insn_start
= riscv_tr_insn_start
,
1268 .translate_insn
= riscv_tr_translate_insn
,
1269 .tb_stop
= riscv_tr_tb_stop
,
1270 .disas_log
= riscv_tr_disas_log
,
1273 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
1274 target_ulong pc
, void *host_pc
)
1278 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &riscv_tr_ops
, &ctx
.base
);
1281 void riscv_translate_init(void)
1286 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1287 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1288 * unless you specifically block reads/writes to reg 0.
1293 for (i
= 1; i
< 32; i
++) {
1294 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
1295 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
1296 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
1297 offsetof(CPURISCVState
, gprh
[i
]), riscv_int_regnamesh
[i
]);
1300 for (i
= 0; i
< 32; i
++) {
1301 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
1302 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
1305 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
1306 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
1307 cpu_vstart
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vstart
),
1309 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
1311 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),
1313 /* Assign PM CSRs to tcg globals */
1314 pm_mask
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmmask
),
1316 pm_base
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmbase
),