2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
31 #include "semihosting/semihost.h"
34 #include "internals.h"
36 #define HELPER_H "helper.h"
37 #include "exec/helper-info.c.inc"
40 /* global register indices */
41 static TCGv cpu_gpr
[32], cpu_gprh
[32], cpu_pc
, cpu_vl
, cpu_vstart
;
42 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
45 /* globals for PM CSRs */
50 * If an operation is being performed on less than TARGET_LONG_BITS,
51 * it may require the inputs to be sign- or zero-extended; which will
52 * depend on the exact operation being performed.
60 typedef struct DisasContext
{
61 DisasContextBase base
;
62 /* pc_succ_insn points to the instruction following base.pc_next */
63 target_ulong pc_succ_insn
;
64 target_ulong priv_ver
;
65 RISCVMXL misa_mxl_max
;
69 RISCVExtStatus mstatus_fs
;
70 RISCVExtStatus mstatus_vs
;
74 * Remember the rounding mode encoded in the previous fp instruction,
75 * which we have already installed into env->fp_status. Or -1 for
76 * no previous fp instruction. Note that we exit the TB when writing
77 * to any system register, which includes CSR_FRM, so we do not have
78 * to reset this known value.
84 const RISCVCPUConfig
*cfg_ptr
;
85 /* vector extension */
88 * Encode LMUL to lmul as follows:
108 /* PointerMasking extension */
109 bool pm_mask_enabled
;
110 bool pm_base_enabled
;
111 /* Use icount trigger for native debug */
113 /* FRM is known to contain a valid value. */
115 /* TCG of the current insn_start */
119 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
121 return ctx
->misa_ext
& ext
;
124 static bool always_true_p(DisasContext
*ctx
__attribute__((__unused__
)))
129 static bool has_xthead_p(DisasContext
*ctx
__attribute__((__unused__
)))
131 return ctx
->cfg_ptr
->ext_xtheadba
|| ctx
->cfg_ptr
->ext_xtheadbb
||
132 ctx
->cfg_ptr
->ext_xtheadbs
|| ctx
->cfg_ptr
->ext_xtheadcmo
||
133 ctx
->cfg_ptr
->ext_xtheadcondmov
||
134 ctx
->cfg_ptr
->ext_xtheadfmemidx
|| ctx
->cfg_ptr
->ext_xtheadfmv
||
135 ctx
->cfg_ptr
->ext_xtheadmac
|| ctx
->cfg_ptr
->ext_xtheadmemidx
||
136 ctx
->cfg_ptr
->ext_xtheadmempair
|| ctx
->cfg_ptr
->ext_xtheadsync
;
139 #define MATERIALISE_EXT_PREDICATE(ext) \
140 static bool has_ ## ext ## _p(DisasContext *ctx) \
142 return ctx->cfg_ptr->ext_ ## ext ; \
145 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
);
147 #ifdef TARGET_RISCV32
148 #define get_xl(ctx) MXL_RV32
149 #elif defined(CONFIG_USER_ONLY)
150 #define get_xl(ctx) MXL_RV64
152 #define get_xl(ctx) ((ctx)->xl)
155 /* The word size for this machine mode. */
156 static inline int __attribute__((unused
)) get_xlen(DisasContext
*ctx
)
158 return 16 << get_xl(ctx
);
161 /* The operation length, as opposed to the xlen. */
162 #ifdef TARGET_RISCV32
163 #define get_ol(ctx) MXL_RV32
165 #define get_ol(ctx) ((ctx)->ol)
168 static inline int get_olen(DisasContext
*ctx
)
170 return 16 << get_ol(ctx
);
173 /* The maximum register length */
174 #ifdef TARGET_RISCV32
175 #define get_xl_max(ctx) MXL_RV32
177 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
181 * RISC-V requires NaN-boxing of narrower width floating point values.
182 * This applies when a 32-bit value is assigned to a 64-bit FP register.
183 * For consistency and simplicity, we nanbox results even when the RVD
184 * extension is not present.
186 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
188 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
191 static void gen_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
193 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(16, 48));
197 * A narrow n-bit operation, where n < FLEN, checks that input operands
198 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
199 * If so, the least-significant bits of the input are used, otherwise the
200 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
202 * Here, the result is always nan-boxed, even the canonical nan.
204 static void gen_check_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
206 TCGv_i64 t_max
= tcg_constant_i64(0xffffffffffff0000ull
);
207 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffffffff7e00ull
);
209 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
212 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
214 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
215 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
217 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
220 static void decode_save_opc(DisasContext
*ctx
)
222 assert(ctx
->insn_start
!= NULL
);
223 tcg_set_insn_start_param(ctx
->insn_start
, 1, ctx
->opcode
);
224 ctx
->insn_start
= NULL
;
227 static void gen_pc_plus_diff(TCGv target
, DisasContext
*ctx
,
230 if (get_xl(ctx
) == MXL_RV32
) {
231 dest
= (int32_t)dest
;
233 tcg_gen_movi_tl(target
, dest
);
236 static void gen_set_pc_imm(DisasContext
*ctx
, target_ulong dest
)
238 gen_pc_plus_diff(cpu_pc
, ctx
, dest
);
241 static void generate_exception(DisasContext
*ctx
, int excp
)
243 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
244 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
245 ctx
->base
.is_jmp
= DISAS_NORETURN
;
248 static void gen_exception_illegal(DisasContext
*ctx
)
250 tcg_gen_st_i32(tcg_constant_i32(ctx
->opcode
), cpu_env
,
251 offsetof(CPURISCVState
, bins
));
252 if (ctx
->virt_inst_excp
) {
253 generate_exception(ctx
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
);
255 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
259 static void gen_exception_inst_addr_mis(DisasContext
*ctx
, TCGv target
)
261 tcg_gen_st_tl(target
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
262 generate_exception(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
265 static void lookup_and_goto_ptr(DisasContext
*ctx
)
267 #ifndef CONFIG_USER_ONLY
269 gen_helper_itrigger_match(cpu_env
);
272 tcg_gen_lookup_and_goto_ptr();
275 static void exit_tb(DisasContext
*ctx
)
277 #ifndef CONFIG_USER_ONLY
279 gen_helper_itrigger_match(cpu_env
);
282 tcg_gen_exit_tb(NULL
, 0);
285 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
288 * Under itrigger, instruction executes one by one like singlestep,
289 * direct block chain benefits will be small.
291 if (translator_use_goto_tb(&ctx
->base
, dest
) && !ctx
->itrigger
) {
293 gen_set_pc_imm(ctx
, dest
);
294 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
296 gen_set_pc_imm(ctx
, dest
);
297 lookup_and_goto_ptr(ctx
);
302 * Wrappers for getting reg values.
304 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
305 * constant zero as a source, and an uninitialized sink as destination.
307 * Further, we may provide an extension for word operations.
309 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
317 switch (get_ol(ctx
)) {
324 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
328 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
331 g_assert_not_reached();
338 g_assert_not_reached();
340 return cpu_gpr
[reg_num
];
343 static TCGv
get_gprh(DisasContext
*ctx
, int reg_num
)
345 assert(get_xl(ctx
) == MXL_RV128
);
349 return cpu_gprh
[reg_num
];
352 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
354 if (reg_num
== 0 || get_olen(ctx
) < TARGET_LONG_BITS
) {
355 return tcg_temp_new();
357 return cpu_gpr
[reg_num
];
360 static TCGv
dest_gprh(DisasContext
*ctx
, int reg_num
)
363 return tcg_temp_new();
365 return cpu_gprh
[reg_num
];
368 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
371 switch (get_ol(ctx
)) {
373 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
377 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
380 g_assert_not_reached();
383 if (get_xl_max(ctx
) == MXL_RV128
) {
384 tcg_gen_sari_tl(cpu_gprh
[reg_num
], cpu_gpr
[reg_num
], 63);
389 static void gen_set_gpri(DisasContext
*ctx
, int reg_num
, target_long imm
)
392 switch (get_ol(ctx
)) {
394 tcg_gen_movi_tl(cpu_gpr
[reg_num
], (int32_t)imm
);
398 tcg_gen_movi_tl(cpu_gpr
[reg_num
], imm
);
401 g_assert_not_reached();
404 if (get_xl_max(ctx
) == MXL_RV128
) {
405 tcg_gen_movi_tl(cpu_gprh
[reg_num
], -(imm
< 0));
410 static void gen_set_gpr128(DisasContext
*ctx
, int reg_num
, TCGv rl
, TCGv rh
)
412 assert(get_ol(ctx
) == MXL_RV128
);
414 tcg_gen_mov_tl(cpu_gpr
[reg_num
], rl
);
415 tcg_gen_mov_tl(cpu_gprh
[reg_num
], rh
);
419 static TCGv_i64
get_fpr_hs(DisasContext
*ctx
, int reg_num
)
421 if (!ctx
->cfg_ptr
->ext_zfinx
) {
422 return cpu_fpr
[reg_num
];
426 return tcg_constant_i64(0);
428 switch (get_xl(ctx
)) {
430 #ifdef TARGET_RISCV32
432 TCGv_i64 t
= tcg_temp_new_i64();
433 tcg_gen_ext_i32_i64(t
, cpu_gpr
[reg_num
]);
439 return cpu_gpr
[reg_num
];
442 g_assert_not_reached();
446 static TCGv_i64
get_fpr_d(DisasContext
*ctx
, int reg_num
)
448 if (!ctx
->cfg_ptr
->ext_zfinx
) {
449 return cpu_fpr
[reg_num
];
453 return tcg_constant_i64(0);
455 switch (get_xl(ctx
)) {
458 TCGv_i64 t
= tcg_temp_new_i64();
459 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1]);
462 #ifdef TARGET_RISCV64
464 return cpu_gpr
[reg_num
];
467 g_assert_not_reached();
471 static TCGv_i64
dest_fpr(DisasContext
*ctx
, int reg_num
)
473 if (!ctx
->cfg_ptr
->ext_zfinx
) {
474 return cpu_fpr
[reg_num
];
478 return tcg_temp_new_i64();
481 switch (get_xl(ctx
)) {
483 return tcg_temp_new_i64();
484 #ifdef TARGET_RISCV64
486 return cpu_gpr
[reg_num
];
489 g_assert_not_reached();
493 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */
494 static void gen_set_fpr_hs(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
496 if (!ctx
->cfg_ptr
->ext_zfinx
) {
497 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
501 switch (get_xl(ctx
)) {
503 #ifdef TARGET_RISCV32
504 tcg_gen_extrl_i64_i32(cpu_gpr
[reg_num
], t
);
509 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
513 g_assert_not_reached();
518 static void gen_set_fpr_d(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
520 if (!ctx
->cfg_ptr
->ext_zfinx
) {
521 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
526 switch (get_xl(ctx
)) {
528 #ifdef TARGET_RISCV32
529 tcg_gen_extr_i64_i32(cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1], t
);
532 tcg_gen_ext32s_i64(cpu_gpr
[reg_num
], t
);
533 tcg_gen_sari_i64(cpu_gpr
[reg_num
+ 1], t
, 32);
536 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
540 g_assert_not_reached();
545 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
547 target_ulong next_pc
;
549 /* check misaligned: */
550 next_pc
= ctx
->base
.pc_next
+ imm
;
551 if (!has_ext(ctx
, RVC
) && !ctx
->cfg_ptr
->ext_zca
) {
552 if ((next_pc
& 0x3) != 0) {
553 TCGv target_pc
= tcg_temp_new();
554 gen_pc_plus_diff(target_pc
, ctx
, next_pc
);
555 gen_exception_inst_addr_mis(ctx
, target_pc
);
560 gen_set_gpri(ctx
, rd
, ctx
->pc_succ_insn
);
561 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
562 ctx
->base
.is_jmp
= DISAS_NORETURN
;
565 /* Compute a canonical address from a register plus offset. */
566 static TCGv
get_address(DisasContext
*ctx
, int rs1
, int imm
)
568 TCGv addr
= tcg_temp_new();
569 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
571 tcg_gen_addi_tl(addr
, src1
, imm
);
572 if (ctx
->pm_mask_enabled
) {
573 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
574 } else if (get_xl(ctx
) == MXL_RV32
) {
575 tcg_gen_ext32u_tl(addr
, addr
);
577 if (ctx
->pm_base_enabled
) {
578 tcg_gen_or_tl(addr
, addr
, pm_base
);
583 /* Compute a canonical address from a register plus reg offset. */
584 static TCGv
get_address_indexed(DisasContext
*ctx
, int rs1
, TCGv offs
)
586 TCGv addr
= tcg_temp_new();
587 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
589 tcg_gen_add_tl(addr
, src1
, offs
);
590 if (ctx
->pm_mask_enabled
) {
591 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
592 } else if (get_xl(ctx
) == MXL_RV32
) {
593 tcg_gen_ext32u_tl(addr
, addr
);
595 if (ctx
->pm_base_enabled
) {
596 tcg_gen_or_tl(addr
, addr
, pm_base
);
601 #ifndef CONFIG_USER_ONLY
603 * We will have already diagnosed disabled state,
604 * and need to turn initial/clean into dirty.
606 static void mark_fs_dirty(DisasContext
*ctx
)
610 if (!has_ext(ctx
, RVF
)) {
614 if (ctx
->mstatus_fs
!= EXT_STATUS_DIRTY
) {
615 /* Remember the state change for the rest of the TB. */
616 ctx
->mstatus_fs
= EXT_STATUS_DIRTY
;
618 tmp
= tcg_temp_new();
619 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
620 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
621 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
623 if (ctx
->virt_enabled
) {
624 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
625 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
626 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
631 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
634 #ifndef CONFIG_USER_ONLY
636 * We will have already diagnosed disabled state,
637 * and need to turn initial/clean into dirty.
639 static void mark_vs_dirty(DisasContext
*ctx
)
643 if (ctx
->mstatus_vs
!= EXT_STATUS_DIRTY
) {
644 /* Remember the state change for the rest of the TB. */
645 ctx
->mstatus_vs
= EXT_STATUS_DIRTY
;
647 tmp
= tcg_temp_new();
648 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
649 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
650 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
652 if (ctx
->virt_enabled
) {
653 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
654 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
655 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
660 static inline void mark_vs_dirty(DisasContext
*ctx
) { }
663 static void gen_set_rm(DisasContext
*ctx
, int rm
)
665 if (ctx
->frm
== rm
) {
670 if (rm
== RISCV_FRM_DYN
) {
671 /* The helper will return only if frm valid. */
672 ctx
->frm_valid
= true;
675 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
676 decode_save_opc(ctx
);
677 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
680 static void gen_set_rm_chkfrm(DisasContext
*ctx
, int rm
)
682 if (ctx
->frm
== rm
&& ctx
->frm_valid
) {
686 ctx
->frm_valid
= true;
688 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
689 decode_save_opc(ctx
);
690 gen_helper_set_rounding_mode_chkfrm(cpu_env
, tcg_constant_i32(rm
));
693 static int ex_plus_1(DisasContext
*ctx
, int nf
)
698 #define EX_SH(amount) \
699 static int ex_shift_##amount(DisasContext *ctx, int imm) \
701 return imm << amount; \
709 #define REQUIRE_EXT(ctx, ext) do { \
710 if (!has_ext(ctx, ext)) { \
715 #define REQUIRE_32BIT(ctx) do { \
716 if (get_xl(ctx) != MXL_RV32) { \
721 #define REQUIRE_64BIT(ctx) do { \
722 if (get_xl(ctx) != MXL_RV64) { \
727 #define REQUIRE_128BIT(ctx) do { \
728 if (get_xl(ctx) != MXL_RV128) { \
733 #define REQUIRE_64_OR_128BIT(ctx) do { \
734 if (get_xl(ctx) == MXL_RV32) { \
739 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \
740 if (!ctx->cfg_ptr->ext_##A && \
741 !ctx->cfg_ptr->ext_##B) { \
746 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
751 static int ex_sreg_register(DisasContext
*ctx
, int reg
)
753 return reg
< 2 ? reg
+ 8 : reg
+ 16;
756 static int ex_rvc_shiftli(DisasContext
*ctx
, int imm
)
758 /* For RV128 a shamt of 0 means a shift by 64. */
759 if (get_ol(ctx
) == MXL_RV128
) {
760 imm
= imm
? imm
: 64;
765 static int ex_rvc_shiftri(DisasContext
*ctx
, int imm
)
768 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right
769 * shifts, the shamt is sign-extended.
771 if (get_ol(ctx
) == MXL_RV128
) {
772 imm
= imm
| (imm
& 32) << 1;
773 imm
= imm
? imm
: 64;
778 /* Include the auto-generated decoder for 32 bit insn */
779 #include "decode-insn32.c.inc"
781 static bool gen_logic_imm_fn(DisasContext
*ctx
, arg_i
*a
,
782 void (*func
)(TCGv
, TCGv
, target_long
))
784 TCGv dest
= dest_gpr(ctx
, a
->rd
);
785 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
787 func(dest
, src1
, a
->imm
);
789 if (get_xl(ctx
) == MXL_RV128
) {
790 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
791 TCGv desth
= dest_gprh(ctx
, a
->rd
);
793 func(desth
, src1h
, -(a
->imm
< 0));
794 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
796 gen_set_gpr(ctx
, a
->rd
, dest
);
802 static bool gen_logic(DisasContext
*ctx
, arg_r
*a
,
803 void (*func
)(TCGv
, TCGv
, TCGv
))
805 TCGv dest
= dest_gpr(ctx
, a
->rd
);
806 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
807 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
809 func(dest
, src1
, src2
);
811 if (get_xl(ctx
) == MXL_RV128
) {
812 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
813 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
814 TCGv desth
= dest_gprh(ctx
, a
->rd
);
816 func(desth
, src1h
, src2h
);
817 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
819 gen_set_gpr(ctx
, a
->rd
, dest
);
825 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
826 void (*func
)(TCGv
, TCGv
, target_long
),
827 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
829 TCGv dest
= dest_gpr(ctx
, a
->rd
);
830 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
832 if (get_ol(ctx
) < MXL_RV128
) {
833 func(dest
, src1
, a
->imm
);
834 gen_set_gpr(ctx
, a
->rd
, dest
);
840 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
841 TCGv desth
= dest_gprh(ctx
, a
->rd
);
843 f128(dest
, desth
, src1
, src1h
, a
->imm
);
844 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
849 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
850 void (*func
)(TCGv
, TCGv
, TCGv
),
851 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
853 TCGv dest
= dest_gpr(ctx
, a
->rd
);
854 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
855 TCGv src2
= tcg_constant_tl(a
->imm
);
857 if (get_ol(ctx
) < MXL_RV128
) {
858 func(dest
, src1
, src2
);
859 gen_set_gpr(ctx
, a
->rd
, dest
);
865 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
866 TCGv src2h
= tcg_constant_tl(-(a
->imm
< 0));
867 TCGv desth
= dest_gprh(ctx
, a
->rd
);
869 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
870 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
875 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
876 void (*func
)(TCGv
, TCGv
, TCGv
),
877 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
879 TCGv dest
= dest_gpr(ctx
, a
->rd
);
880 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
881 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
883 if (get_ol(ctx
) < MXL_RV128
) {
884 func(dest
, src1
, src2
);
885 gen_set_gpr(ctx
, a
->rd
, dest
);
891 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
892 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
893 TCGv desth
= dest_gprh(ctx
, a
->rd
);
895 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
896 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
901 static bool gen_arith_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
902 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
903 void (*f_32
)(TCGv
, TCGv
, TCGv
),
904 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
906 int olen
= get_olen(ctx
);
908 if (olen
!= TARGET_LONG_BITS
) {
911 } else if (olen
!= 128) {
912 g_assert_not_reached();
915 return gen_arith(ctx
, a
, ext
, f_tl
, f_128
);
918 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
919 void (*func
)(TCGv
, TCGv
, target_long
),
920 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
923 int max_len
= get_olen(ctx
);
925 if (a
->shamt
>= max_len
) {
929 dest
= dest_gpr(ctx
, a
->rd
);
930 src1
= get_gpr(ctx
, a
->rs1
, ext
);
933 func(dest
, src1
, a
->shamt
);
934 gen_set_gpr(ctx
, a
->rd
, dest
);
936 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
937 TCGv desth
= dest_gprh(ctx
, a
->rd
);
942 f128(dest
, desth
, src1
, src1h
, a
->shamt
);
943 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
948 static bool gen_shift_imm_fn_per_ol(DisasContext
*ctx
, arg_shift
*a
,
950 void (*f_tl
)(TCGv
, TCGv
, target_long
),
951 void (*f_32
)(TCGv
, TCGv
, target_long
),
952 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
,
955 int olen
= get_olen(ctx
);
956 if (olen
!= TARGET_LONG_BITS
) {
959 } else if (olen
!= 128) {
960 g_assert_not_reached();
963 return gen_shift_imm_fn(ctx
, a
, ext
, f_tl
, f_128
);
966 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
967 void (*func
)(TCGv
, TCGv
, TCGv
))
969 TCGv dest
, src1
, src2
;
970 int max_len
= get_olen(ctx
);
972 if (a
->shamt
>= max_len
) {
976 dest
= dest_gpr(ctx
, a
->rd
);
977 src1
= get_gpr(ctx
, a
->rs1
, ext
);
978 src2
= tcg_constant_tl(a
->shamt
);
980 func(dest
, src1
, src2
);
982 gen_set_gpr(ctx
, a
->rd
, dest
);
986 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
987 void (*func
)(TCGv
, TCGv
, TCGv
),
988 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
990 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
991 TCGv ext2
= tcg_temp_new();
992 int max_len
= get_olen(ctx
);
994 tcg_gen_andi_tl(ext2
, src2
, max_len
- 1);
996 TCGv dest
= dest_gpr(ctx
, a
->rd
);
997 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1000 func(dest
, src1
, ext2
);
1001 gen_set_gpr(ctx
, a
->rd
, dest
);
1003 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
1004 TCGv desth
= dest_gprh(ctx
, a
->rd
);
1009 f128(dest
, desth
, src1
, src1h
, ext2
);
1010 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
1015 static bool gen_shift_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
1016 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
1017 void (*f_32
)(TCGv
, TCGv
, TCGv
),
1018 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
1020 int olen
= get_olen(ctx
);
1021 if (olen
!= TARGET_LONG_BITS
) {
1024 } else if (olen
!= 128) {
1025 g_assert_not_reached();
1028 return gen_shift(ctx
, a
, ext
, f_tl
, f_128
);
1031 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1032 void (*func
)(TCGv
, TCGv
))
1034 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1035 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1039 gen_set_gpr(ctx
, a
->rd
, dest
);
1043 static bool gen_unary_per_ol(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1044 void (*f_tl
)(TCGv
, TCGv
),
1045 void (*f_32
)(TCGv
, TCGv
))
1047 int olen
= get_olen(ctx
);
1049 if (olen
!= TARGET_LONG_BITS
) {
1053 g_assert_not_reached();
1056 return gen_unary(ctx
, a
, ext
, f_tl
);
1059 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
1061 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1062 CPUState
*cpu
= ctx
->cs
;
1063 CPURISCVState
*env
= cpu
->env_ptr
;
1065 return cpu_ldl_code(env
, pc
);
1068 /* Include insn module translation function */
1069 #include "insn_trans/trans_rvi.c.inc"
1070 #include "insn_trans/trans_rvm.c.inc"
1071 #include "insn_trans/trans_rva.c.inc"
1072 #include "insn_trans/trans_rvf.c.inc"
1073 #include "insn_trans/trans_rvd.c.inc"
1074 #include "insn_trans/trans_rvh.c.inc"
1075 #include "insn_trans/trans_rvv.c.inc"
1076 #include "insn_trans/trans_rvb.c.inc"
1077 #include "insn_trans/trans_rvzicond.c.inc"
1078 #include "insn_trans/trans_rvzawrs.c.inc"
1079 #include "insn_trans/trans_rvzicbo.c.inc"
1080 #include "insn_trans/trans_rvzfh.c.inc"
1081 #include "insn_trans/trans_rvk.c.inc"
1082 #include "insn_trans/trans_privileged.c.inc"
1083 #include "insn_trans/trans_svinval.c.inc"
1084 #include "decode-xthead.c.inc"
1085 #include "insn_trans/trans_xthead.c.inc"
1086 #include "insn_trans/trans_xventanacondops.c.inc"
1088 /* Include the auto-generated decoder for 16 bit insn */
1089 #include "decode-insn16.c.inc"
1090 #include "insn_trans/trans_rvzce.c.inc"
1092 /* Include decoders for factored-out extensions */
1093 #include "decode-XVentanaCondOps.c.inc"
1095 /* The specification allows for longer insns, but not supported by qemu. */
1096 #define MAX_INSN_LEN 4
1098 static inline int insn_len(uint16_t first_word
)
1100 return (first_word
& 3) == 3 ? 4 : 2;
1103 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
1106 * A table with predicate (i.e., guard) functions and decoder functions
1107 * that are tested in-order until a decoder matches onto the opcode.
1109 static const struct {
1110 bool (*guard_func
)(DisasContext
*);
1111 bool (*decode_func
)(DisasContext
*, uint32_t);
1113 { always_true_p
, decode_insn32
},
1114 { has_xthead_p
, decode_xthead
},
1115 { has_XVentanaCondOps_p
, decode_XVentanaCodeOps
},
1118 ctx
->virt_inst_excp
= false;
1119 /* Check for compressed insn */
1120 if (insn_len(opcode
) == 2) {
1121 ctx
->opcode
= opcode
;
1122 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
1124 * The Zca extension is added as way to refer to instructions in the C
1125 * extension that do not include the floating-point loads and stores
1127 if ((has_ext(ctx
, RVC
) || ctx
->cfg_ptr
->ext_zca
) &&
1128 decode_insn16(ctx
, opcode
)) {
1132 uint32_t opcode32
= opcode
;
1133 opcode32
= deposit32(opcode32
, 16, 16,
1134 translator_lduw(env
, &ctx
->base
,
1135 ctx
->base
.pc_next
+ 2));
1136 ctx
->opcode
= opcode32
;
1137 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
1139 for (size_t i
= 0; i
< ARRAY_SIZE(decoders
); ++i
) {
1140 if (decoders
[i
].guard_func(ctx
) &&
1141 decoders
[i
].decode_func(ctx
, opcode32
)) {
1147 gen_exception_illegal(ctx
);
1150 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
1152 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1153 CPURISCVState
*env
= cs
->env_ptr
;
1154 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1155 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
1157 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
1158 ctx
->priv
= FIELD_EX32(tb_flags
, TB_FLAGS
, PRIV
);
1159 ctx
->mem_idx
= FIELD_EX32(tb_flags
, TB_FLAGS
, MEM_IDX
);
1160 ctx
->mstatus_fs
= FIELD_EX32(tb_flags
, TB_FLAGS
, FS
);
1161 ctx
->mstatus_vs
= FIELD_EX32(tb_flags
, TB_FLAGS
, VS
);
1162 ctx
->priv_ver
= env
->priv_ver
;
1163 ctx
->virt_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, VIRT_ENABLED
);
1164 ctx
->misa_ext
= env
->misa_ext
;
1165 ctx
->frm
= -1; /* unknown rounding mode */
1166 ctx
->cfg_ptr
= &(cpu
->cfg
);
1167 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
1168 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
1169 ctx
->lmul
= sextract32(FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
), 0, 3);
1170 ctx
->vta
= FIELD_EX32(tb_flags
, TB_FLAGS
, VTA
) && cpu
->cfg
.rvv_ta_all_1s
;
1171 ctx
->vma
= FIELD_EX32(tb_flags
, TB_FLAGS
, VMA
) && cpu
->cfg
.rvv_ma_all_1s
;
1172 ctx
->cfg_vta_all_1s
= cpu
->cfg
.rvv_ta_all_1s
;
1173 ctx
->vstart_eq_zero
= FIELD_EX32(tb_flags
, TB_FLAGS
, VSTART_EQ_ZERO
);
1174 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
1175 ctx
->misa_mxl_max
= env
->misa_mxl_max
;
1176 ctx
->xl
= FIELD_EX32(tb_flags
, TB_FLAGS
, XL
);
1178 ctx
->pm_mask_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_MASK_ENABLED
);
1179 ctx
->pm_base_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_BASE_ENABLED
);
1180 ctx
->itrigger
= FIELD_EX32(tb_flags
, TB_FLAGS
, ITRIGGER
);
1181 ctx
->zero
= tcg_constant_tl(0);
1182 ctx
->virt_inst_excp
= false;
1185 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
1189 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1191 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1193 tcg_gen_insn_start(ctx
->base
.pc_next
, 0);
1194 ctx
->insn_start
= tcg_last_op();
1197 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1199 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1200 CPURISCVState
*env
= cpu
->env_ptr
;
1201 uint16_t opcode16
= translator_lduw(env
, &ctx
->base
, ctx
->base
.pc_next
);
1204 decode_opc(env
, ctx
, opcode16
);
1205 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
1207 /* Only the first insn within a TB is allowed to cross a page boundary. */
1208 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
1209 if (ctx
->itrigger
|| !is_same_page(&ctx
->base
, ctx
->base
.pc_next
)) {
1210 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1212 unsigned page_ofs
= ctx
->base
.pc_next
& ~TARGET_PAGE_MASK
;
1214 if (page_ofs
> TARGET_PAGE_SIZE
- MAX_INSN_LEN
) {
1215 uint16_t next_insn
= cpu_lduw_code(env
, ctx
->base
.pc_next
);
1216 int len
= insn_len(next_insn
);
1218 if (!is_same_page(&ctx
->base
, ctx
->base
.pc_next
+ len
- 1)) {
1219 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1226 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1228 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1230 switch (ctx
->base
.is_jmp
) {
1231 case DISAS_TOO_MANY
:
1232 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1234 case DISAS_NORETURN
:
1237 g_assert_not_reached();
1241 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
,
1242 CPUState
*cpu
, FILE *logfile
)
1244 #ifndef CONFIG_USER_ONLY
1245 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
1246 CPURISCVState
*env
= &rvcpu
->env
;
1249 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1250 #ifndef CONFIG_USER_ONLY
1251 fprintf(logfile
, "Priv: "TARGET_FMT_ld
"; Virt: %d\n",
1252 env
->priv
, env
->virt_enabled
);
1254 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1257 static const TranslatorOps riscv_tr_ops
= {
1258 .init_disas_context
= riscv_tr_init_disas_context
,
1259 .tb_start
= riscv_tr_tb_start
,
1260 .insn_start
= riscv_tr_insn_start
,
1261 .translate_insn
= riscv_tr_translate_insn
,
1262 .tb_stop
= riscv_tr_tb_stop
,
1263 .disas_log
= riscv_tr_disas_log
,
1266 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
1267 target_ulong pc
, void *host_pc
)
1271 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &riscv_tr_ops
, &ctx
.base
);
1274 void riscv_translate_init(void)
1279 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1280 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1281 * unless you specifically block reads/writes to reg 0.
1286 for (i
= 1; i
< 32; i
++) {
1287 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
1288 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
1289 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
1290 offsetof(CPURISCVState
, gprh
[i
]), riscv_int_regnamesh
[i
]);
1293 for (i
= 0; i
< 32; i
++) {
1294 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
1295 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
1298 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
1299 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
1300 cpu_vstart
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vstart
),
1302 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
1304 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),
1306 /* Assign PM CSRs to tcg globals */
1307 pm_mask
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmmask
),
1309 pm_base
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmbase
),