2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
31 #include "semihosting/semihost.h"
34 #include "internals.h"
36 /* global register indices */
37 static TCGv cpu_gpr
[32], cpu_gprh
[32], cpu_pc
, cpu_vl
, cpu_vstart
;
38 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
41 /* globals for PM CSRs */
45 #include "exec/gen-icount.h"
48 * If an operation is being performed on less than TARGET_LONG_BITS,
49 * it may require the inputs to be sign- or zero-extended; which will
50 * depend on the exact operation being performed.
58 typedef struct DisasContext
{
59 DisasContextBase base
;
60 /* pc_succ_insn points to the instruction following base.pc_next */
61 target_ulong pc_succ_insn
;
62 target_ulong priv_ver
;
63 RISCVMXL misa_mxl_max
;
69 uint32_t mstatus_hs_fs
;
70 uint32_t mstatus_hs_vs
;
72 /* Remember the rounding mode encoded in the previous fp instruction,
73 which we have already installed into env->fp_status. Or -1 for
74 no previous fp instruction. Note that we exit the TB when writing
75 to any system register, which includes CSR_FRM, so we do not have
76 to reset this known value. */
81 const RISCVCPUConfig
*cfg_ptr
;
83 /* vector extension */
86 * Encode LMUL to lmul as follows:
107 /* Space for 3 operands plus 1 extra for address computation. */
109 /* Space for 4 operands(1 dest and <=3 src) for float point computation */
112 /* PointerMasking extension */
113 bool pm_mask_enabled
;
114 bool pm_base_enabled
;
115 /* Use icount trigger for native debug */
117 /* FRM is known to contain a valid value. */
119 /* TCG of the current insn_start */
123 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
125 return ctx
->misa_ext
& ext
;
128 static bool always_true_p(DisasContext
*ctx
__attribute__((__unused__
)))
133 static bool has_xthead_p(DisasContext
*ctx
__attribute__((__unused__
)))
135 return ctx
->cfg_ptr
->ext_xtheadba
|| ctx
->cfg_ptr
->ext_xtheadcmo
||
136 ctx
->cfg_ptr
->ext_xtheadsync
;
139 #define MATERIALISE_EXT_PREDICATE(ext) \
140 static bool has_ ## ext ## _p(DisasContext *ctx) \
142 return ctx->cfg_ptr->ext_ ## ext ; \
145 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
);
147 #ifdef TARGET_RISCV32
148 #define get_xl(ctx) MXL_RV32
149 #elif defined(CONFIG_USER_ONLY)
150 #define get_xl(ctx) MXL_RV64
152 #define get_xl(ctx) ((ctx)->xl)
155 /* The word size for this machine mode. */
156 static inline int __attribute__((unused
)) get_xlen(DisasContext
*ctx
)
158 return 16 << get_xl(ctx
);
161 /* The operation length, as opposed to the xlen. */
162 #ifdef TARGET_RISCV32
163 #define get_ol(ctx) MXL_RV32
165 #define get_ol(ctx) ((ctx)->ol)
168 static inline int get_olen(DisasContext
*ctx
)
170 return 16 << get_ol(ctx
);
173 /* The maximum register length */
174 #ifdef TARGET_RISCV32
175 #define get_xl_max(ctx) MXL_RV32
177 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
181 * RISC-V requires NaN-boxing of narrower width floating point values.
182 * This applies when a 32-bit value is assigned to a 64-bit FP register.
183 * For consistency and simplicity, we nanbox results even when the RVD
184 * extension is not present.
186 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
188 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
191 static void gen_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
193 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(16, 48));
197 * A narrow n-bit operation, where n < FLEN, checks that input operands
198 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
199 * If so, the least-significant bits of the input are used, otherwise the
200 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
202 * Here, the result is always nan-boxed, even the canonical nan.
204 static void gen_check_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
206 TCGv_i64 t_max
= tcg_const_i64(0xffffffffffff0000ull
);
207 TCGv_i64 t_nan
= tcg_const_i64(0xffffffffffff7e00ull
);
209 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
210 tcg_temp_free_i64(t_max
);
211 tcg_temp_free_i64(t_nan
);
214 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
216 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
217 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
219 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
222 static void decode_save_opc(DisasContext
*ctx
)
224 assert(ctx
->insn_start
!= NULL
);
225 tcg_set_insn_start_param(ctx
->insn_start
, 1, ctx
->opcode
);
226 ctx
->insn_start
= NULL
;
229 static void gen_set_pc_imm(DisasContext
*ctx
, target_ulong dest
)
231 if (get_xl(ctx
) == MXL_RV32
) {
232 dest
= (int32_t)dest
;
234 tcg_gen_movi_tl(cpu_pc
, dest
);
237 static void gen_set_pc(DisasContext
*ctx
, TCGv dest
)
239 if (get_xl(ctx
) == MXL_RV32
) {
240 tcg_gen_ext32s_tl(cpu_pc
, dest
);
242 tcg_gen_mov_tl(cpu_pc
, dest
);
246 static void generate_exception(DisasContext
*ctx
, int excp
)
248 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
249 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
250 ctx
->base
.is_jmp
= DISAS_NORETURN
;
253 static void gen_exception_illegal(DisasContext
*ctx
)
255 tcg_gen_st_i32(tcg_constant_i32(ctx
->opcode
), cpu_env
,
256 offsetof(CPURISCVState
, bins
));
257 if (ctx
->virt_inst_excp
) {
258 generate_exception(ctx
, RISCV_EXCP_VIRT_INSTRUCTION_FAULT
);
260 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
264 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
266 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
267 generate_exception(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
270 static void lookup_and_goto_ptr(DisasContext
*ctx
)
272 #ifndef CONFIG_USER_ONLY
274 gen_helper_itrigger_match(cpu_env
);
277 tcg_gen_lookup_and_goto_ptr();
280 static void exit_tb(DisasContext
*ctx
)
282 #ifndef CONFIG_USER_ONLY
284 gen_helper_itrigger_match(cpu_env
);
287 tcg_gen_exit_tb(NULL
, 0);
290 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
293 * Under itrigger, instruction executes one by one like singlestep,
294 * direct block chain benefits will be small.
296 if (translator_use_goto_tb(&ctx
->base
, dest
) && !ctx
->itrigger
) {
298 gen_set_pc_imm(ctx
, dest
);
299 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
301 gen_set_pc_imm(ctx
, dest
);
302 lookup_and_goto_ptr(ctx
);
307 * Wrappers for getting reg values.
309 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
310 * constant zero as a source, and an uninitialized sink as destination.
312 * Further, we may provide an extension for word operations.
314 static TCGv
temp_new(DisasContext
*ctx
)
316 assert(ctx
->ntemp
< ARRAY_SIZE(ctx
->temp
));
317 return ctx
->temp
[ctx
->ntemp
++] = tcg_temp_new();
320 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
328 switch (get_ol(ctx
)) {
335 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
339 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
342 g_assert_not_reached();
349 g_assert_not_reached();
351 return cpu_gpr
[reg_num
];
354 static TCGv
get_gprh(DisasContext
*ctx
, int reg_num
)
356 assert(get_xl(ctx
) == MXL_RV128
);
360 return cpu_gprh
[reg_num
];
363 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
365 if (reg_num
== 0 || get_olen(ctx
) < TARGET_LONG_BITS
) {
366 return temp_new(ctx
);
368 return cpu_gpr
[reg_num
];
371 static TCGv
dest_gprh(DisasContext
*ctx
, int reg_num
)
374 return temp_new(ctx
);
376 return cpu_gprh
[reg_num
];
379 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
382 switch (get_ol(ctx
)) {
384 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
388 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
391 g_assert_not_reached();
394 if (get_xl_max(ctx
) == MXL_RV128
) {
395 tcg_gen_sari_tl(cpu_gprh
[reg_num
], cpu_gpr
[reg_num
], 63);
400 static void gen_set_gpri(DisasContext
*ctx
, int reg_num
, target_long imm
)
403 switch (get_ol(ctx
)) {
405 tcg_gen_movi_tl(cpu_gpr
[reg_num
], (int32_t)imm
);
409 tcg_gen_movi_tl(cpu_gpr
[reg_num
], imm
);
412 g_assert_not_reached();
415 if (get_xl_max(ctx
) == MXL_RV128
) {
416 tcg_gen_movi_tl(cpu_gprh
[reg_num
], -(imm
< 0));
421 static void gen_set_gpr128(DisasContext
*ctx
, int reg_num
, TCGv rl
, TCGv rh
)
423 assert(get_ol(ctx
) == MXL_RV128
);
425 tcg_gen_mov_tl(cpu_gpr
[reg_num
], rl
);
426 tcg_gen_mov_tl(cpu_gprh
[reg_num
], rh
);
430 static TCGv_i64
ftemp_new(DisasContext
*ctx
)
432 assert(ctx
->nftemp
< ARRAY_SIZE(ctx
->ftemp
));
433 return ctx
->ftemp
[ctx
->nftemp
++] = tcg_temp_new_i64();
436 static TCGv_i64
get_fpr_hs(DisasContext
*ctx
, int reg_num
)
438 if (!ctx
->cfg_ptr
->ext_zfinx
) {
439 return cpu_fpr
[reg_num
];
443 return tcg_constant_i64(0);
445 switch (get_xl(ctx
)) {
447 #ifdef TARGET_RISCV32
449 TCGv_i64 t
= ftemp_new(ctx
);
450 tcg_gen_ext_i32_i64(t
, cpu_gpr
[reg_num
]);
456 return cpu_gpr
[reg_num
];
459 g_assert_not_reached();
463 static TCGv_i64
get_fpr_d(DisasContext
*ctx
, int reg_num
)
465 if (!ctx
->cfg_ptr
->ext_zfinx
) {
466 return cpu_fpr
[reg_num
];
470 return tcg_constant_i64(0);
472 switch (get_xl(ctx
)) {
475 TCGv_i64 t
= ftemp_new(ctx
);
476 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1]);
479 #ifdef TARGET_RISCV64
481 return cpu_gpr
[reg_num
];
484 g_assert_not_reached();
488 static TCGv_i64
dest_fpr(DisasContext
*ctx
, int reg_num
)
490 if (!ctx
->cfg_ptr
->ext_zfinx
) {
491 return cpu_fpr
[reg_num
];
495 return ftemp_new(ctx
);
498 switch (get_xl(ctx
)) {
500 return ftemp_new(ctx
);
501 #ifdef TARGET_RISCV64
503 return cpu_gpr
[reg_num
];
506 g_assert_not_reached();
510 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
511 static void gen_set_fpr_hs(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
513 if (!ctx
->cfg_ptr
->ext_zfinx
) {
514 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
518 switch (get_xl(ctx
)) {
520 #ifdef TARGET_RISCV32
521 tcg_gen_extrl_i64_i32(cpu_gpr
[reg_num
], t
);
526 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
530 g_assert_not_reached();
535 static void gen_set_fpr_d(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
537 if (!ctx
->cfg_ptr
->ext_zfinx
) {
538 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
543 switch (get_xl(ctx
)) {
545 #ifdef TARGET_RISCV32
546 tcg_gen_extr_i64_i32(cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1], t
);
549 tcg_gen_ext32s_i64(cpu_gpr
[reg_num
], t
);
550 tcg_gen_sari_i64(cpu_gpr
[reg_num
+ 1], t
, 32);
553 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
557 g_assert_not_reached();
562 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
564 target_ulong next_pc
;
566 /* check misaligned: */
567 next_pc
= ctx
->base
.pc_next
+ imm
;
568 if (!has_ext(ctx
, RVC
)) {
569 if ((next_pc
& 0x3) != 0) {
570 gen_exception_inst_addr_mis(ctx
);
575 gen_set_gpri(ctx
, rd
, ctx
->pc_succ_insn
);
576 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
577 ctx
->base
.is_jmp
= DISAS_NORETURN
;
580 /* Compute a canonical address from a register plus offset. */
581 static TCGv
get_address(DisasContext
*ctx
, int rs1
, int imm
)
583 TCGv addr
= temp_new(ctx
);
584 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
586 tcg_gen_addi_tl(addr
, src1
, imm
);
587 if (ctx
->pm_mask_enabled
) {
588 tcg_gen_andc_tl(addr
, addr
, pm_mask
);
589 } else if (get_xl(ctx
) == MXL_RV32
) {
590 tcg_gen_ext32u_tl(addr
, addr
);
592 if (ctx
->pm_base_enabled
) {
593 tcg_gen_or_tl(addr
, addr
, pm_base
);
598 #ifndef CONFIG_USER_ONLY
599 /* The states of mstatus_fs are:
600 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
601 * We will have already diagnosed disabled state,
602 * and need to turn initial/clean into dirty.
604 static void mark_fs_dirty(DisasContext
*ctx
)
608 if (!has_ext(ctx
, RVF
)) {
612 if (ctx
->mstatus_fs
!= MSTATUS_FS
) {
613 /* Remember the state change for the rest of the TB. */
614 ctx
->mstatus_fs
= MSTATUS_FS
;
616 tmp
= tcg_temp_new();
617 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
618 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
619 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
623 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_fs
!= MSTATUS_FS
) {
624 /* Remember the stage change for the rest of the TB. */
625 ctx
->mstatus_hs_fs
= MSTATUS_FS
;
627 tmp
= tcg_temp_new();
628 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
629 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
630 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
635 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
638 #ifndef CONFIG_USER_ONLY
639 /* The states of mstatus_vs are:
640 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
641 * We will have already diagnosed disabled state,
642 * and need to turn initial/clean into dirty.
644 static void mark_vs_dirty(DisasContext
*ctx
)
648 if (ctx
->mstatus_vs
!= MSTATUS_VS
) {
649 /* Remember the state change for the rest of the TB. */
650 ctx
->mstatus_vs
= MSTATUS_VS
;
652 tmp
= tcg_temp_new();
653 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
654 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
655 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
659 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_vs
!= MSTATUS_VS
) {
660 /* Remember the stage change for the rest of the TB. */
661 ctx
->mstatus_hs_vs
= MSTATUS_VS
;
663 tmp
= tcg_temp_new();
664 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
665 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
666 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
671 static inline void mark_vs_dirty(DisasContext
*ctx
) { }
674 static void gen_set_rm(DisasContext
*ctx
, int rm
)
676 if (ctx
->frm
== rm
) {
681 if (rm
== RISCV_FRM_DYN
) {
682 /* The helper will return only if frm valid. */
683 ctx
->frm_valid
= true;
686 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
687 decode_save_opc(ctx
);
688 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
691 static void gen_set_rm_chkfrm(DisasContext
*ctx
, int rm
)
693 if (ctx
->frm
== rm
&& ctx
->frm_valid
) {
697 ctx
->frm_valid
= true;
699 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
700 decode_save_opc(ctx
);
701 gen_helper_set_rounding_mode_chkfrm(cpu_env
, tcg_constant_i32(rm
));
704 static int ex_plus_1(DisasContext
*ctx
, int nf
)
709 #define EX_SH(amount) \
710 static int ex_shift_##amount(DisasContext *ctx, int imm) \
712 return imm << amount; \
720 #define REQUIRE_EXT(ctx, ext) do { \
721 if (!has_ext(ctx, ext)) { \
726 #define REQUIRE_32BIT(ctx) do { \
727 if (get_xl(ctx) != MXL_RV32) { \
732 #define REQUIRE_64BIT(ctx) do { \
733 if (get_xl(ctx) != MXL_RV64) { \
738 #define REQUIRE_128BIT(ctx) do { \
739 if (get_xl(ctx) != MXL_RV128) { \
744 #define REQUIRE_64_OR_128BIT(ctx) do { \
745 if (get_xl(ctx) == MXL_RV32) { \
750 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \
751 if (!ctx->cfg_ptr->ext_##A && \
752 !ctx->cfg_ptr->ext_##B) { \
757 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
762 static int ex_rvc_shiftli(DisasContext
*ctx
, int imm
)
764 /* For RV128 a shamt of 0 means a shift by 64. */
765 if (get_ol(ctx
) == MXL_RV128
) {
766 imm
= imm
? imm
: 64;
771 static int ex_rvc_shiftri(DisasContext
*ctx
, int imm
)
774 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right
775 * shifts, the shamt is sign-extended.
777 if (get_ol(ctx
) == MXL_RV128
) {
778 imm
= imm
| (imm
& 32) << 1;
779 imm
= imm
? imm
: 64;
784 /* Include the auto-generated decoder for 32 bit insn */
785 #include "decode-insn32.c.inc"
787 static bool gen_logic_imm_fn(DisasContext
*ctx
, arg_i
*a
,
788 void (*func
)(TCGv
, TCGv
, target_long
))
790 TCGv dest
= dest_gpr(ctx
, a
->rd
);
791 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
793 func(dest
, src1
, a
->imm
);
795 if (get_xl(ctx
) == MXL_RV128
) {
796 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
797 TCGv desth
= dest_gprh(ctx
, a
->rd
);
799 func(desth
, src1h
, -(a
->imm
< 0));
800 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
802 gen_set_gpr(ctx
, a
->rd
, dest
);
808 static bool gen_logic(DisasContext
*ctx
, arg_r
*a
,
809 void (*func
)(TCGv
, TCGv
, TCGv
))
811 TCGv dest
= dest_gpr(ctx
, a
->rd
);
812 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
813 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
815 func(dest
, src1
, src2
);
817 if (get_xl(ctx
) == MXL_RV128
) {
818 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
819 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
820 TCGv desth
= dest_gprh(ctx
, a
->rd
);
822 func(desth
, src1h
, src2h
);
823 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
825 gen_set_gpr(ctx
, a
->rd
, dest
);
831 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
832 void (*func
)(TCGv
, TCGv
, target_long
),
833 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
835 TCGv dest
= dest_gpr(ctx
, a
->rd
);
836 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
838 if (get_ol(ctx
) < MXL_RV128
) {
839 func(dest
, src1
, a
->imm
);
840 gen_set_gpr(ctx
, a
->rd
, dest
);
846 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
847 TCGv desth
= dest_gprh(ctx
, a
->rd
);
849 f128(dest
, desth
, src1
, src1h
, a
->imm
);
850 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
855 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
856 void (*func
)(TCGv
, TCGv
, TCGv
),
857 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
859 TCGv dest
= dest_gpr(ctx
, a
->rd
);
860 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
861 TCGv src2
= tcg_constant_tl(a
->imm
);
863 if (get_ol(ctx
) < MXL_RV128
) {
864 func(dest
, src1
, src2
);
865 gen_set_gpr(ctx
, a
->rd
, dest
);
871 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
872 TCGv src2h
= tcg_constant_tl(-(a
->imm
< 0));
873 TCGv desth
= dest_gprh(ctx
, a
->rd
);
875 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
876 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
881 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
882 void (*func
)(TCGv
, TCGv
, TCGv
),
883 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
885 TCGv dest
= dest_gpr(ctx
, a
->rd
);
886 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
887 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
889 if (get_ol(ctx
) < MXL_RV128
) {
890 func(dest
, src1
, src2
);
891 gen_set_gpr(ctx
, a
->rd
, dest
);
897 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
898 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
899 TCGv desth
= dest_gprh(ctx
, a
->rd
);
901 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
902 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
907 static bool gen_arith_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
908 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
909 void (*f_32
)(TCGv
, TCGv
, TCGv
),
910 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
912 int olen
= get_olen(ctx
);
914 if (olen
!= TARGET_LONG_BITS
) {
917 } else if (olen
!= 128) {
918 g_assert_not_reached();
921 return gen_arith(ctx
, a
, ext
, f_tl
, f_128
);
924 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
925 void (*func
)(TCGv
, TCGv
, target_long
),
926 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
929 int max_len
= get_olen(ctx
);
931 if (a
->shamt
>= max_len
) {
935 dest
= dest_gpr(ctx
, a
->rd
);
936 src1
= get_gpr(ctx
, a
->rs1
, ext
);
939 func(dest
, src1
, a
->shamt
);
940 gen_set_gpr(ctx
, a
->rd
, dest
);
942 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
943 TCGv desth
= dest_gprh(ctx
, a
->rd
);
948 f128(dest
, desth
, src1
, src1h
, a
->shamt
);
949 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
954 static bool gen_shift_imm_fn_per_ol(DisasContext
*ctx
, arg_shift
*a
,
956 void (*f_tl
)(TCGv
, TCGv
, target_long
),
957 void (*f_32
)(TCGv
, TCGv
, target_long
),
958 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
,
961 int olen
= get_olen(ctx
);
962 if (olen
!= TARGET_LONG_BITS
) {
965 } else if (olen
!= 128) {
966 g_assert_not_reached();
969 return gen_shift_imm_fn(ctx
, a
, ext
, f_tl
, f_128
);
972 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
973 void (*func
)(TCGv
, TCGv
, TCGv
))
975 TCGv dest
, src1
, src2
;
976 int max_len
= get_olen(ctx
);
978 if (a
->shamt
>= max_len
) {
982 dest
= dest_gpr(ctx
, a
->rd
);
983 src1
= get_gpr(ctx
, a
->rs1
, ext
);
984 src2
= tcg_constant_tl(a
->shamt
);
986 func(dest
, src1
, src2
);
988 gen_set_gpr(ctx
, a
->rd
, dest
);
992 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
993 void (*func
)(TCGv
, TCGv
, TCGv
),
994 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
996 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
997 TCGv ext2
= tcg_temp_new();
998 int max_len
= get_olen(ctx
);
1000 tcg_gen_andi_tl(ext2
, src2
, max_len
- 1);
1002 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1003 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1005 if (max_len
< 128) {
1006 func(dest
, src1
, ext2
);
1007 gen_set_gpr(ctx
, a
->rd
, dest
);
1009 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
1010 TCGv desth
= dest_gprh(ctx
, a
->rd
);
1015 f128(dest
, desth
, src1
, src1h
, ext2
);
1016 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
1018 tcg_temp_free(ext2
);
1022 static bool gen_shift_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
1023 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
1024 void (*f_32
)(TCGv
, TCGv
, TCGv
),
1025 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
1027 int olen
= get_olen(ctx
);
1028 if (olen
!= TARGET_LONG_BITS
) {
1031 } else if (olen
!= 128) {
1032 g_assert_not_reached();
1035 return gen_shift(ctx
, a
, ext
, f_tl
, f_128
);
1038 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1039 void (*func
)(TCGv
, TCGv
))
1041 TCGv dest
= dest_gpr(ctx
, a
->rd
);
1042 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
1046 gen_set_gpr(ctx
, a
->rd
, dest
);
1050 static bool gen_unary_per_ol(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
1051 void (*f_tl
)(TCGv
, TCGv
),
1052 void (*f_32
)(TCGv
, TCGv
))
1054 int olen
= get_olen(ctx
);
1056 if (olen
!= TARGET_LONG_BITS
) {
1060 g_assert_not_reached();
1063 return gen_unary(ctx
, a
, ext
, f_tl
);
1066 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
1068 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1069 CPUState
*cpu
= ctx
->cs
;
1070 CPURISCVState
*env
= cpu
->env_ptr
;
1072 return cpu_ldl_code(env
, pc
);
1075 /* Include insn module translation function */
1076 #include "insn_trans/trans_rvi.c.inc"
1077 #include "insn_trans/trans_rvm.c.inc"
1078 #include "insn_trans/trans_rva.c.inc"
1079 #include "insn_trans/trans_rvf.c.inc"
1080 #include "insn_trans/trans_rvd.c.inc"
1081 #include "insn_trans/trans_rvh.c.inc"
1082 #include "insn_trans/trans_rvv.c.inc"
1083 #include "insn_trans/trans_rvb.c.inc"
1084 #include "insn_trans/trans_rvzawrs.c.inc"
1085 #include "insn_trans/trans_rvzfh.c.inc"
1086 #include "insn_trans/trans_rvk.c.inc"
1087 #include "insn_trans/trans_privileged.c.inc"
1088 #include "insn_trans/trans_svinval.c.inc"
1089 #include "decode-xthead.c.inc"
1090 #include "insn_trans/trans_xthead.c.inc"
1091 #include "insn_trans/trans_xventanacondops.c.inc"
1093 /* Include the auto-generated decoder for 16 bit insn */
1094 #include "decode-insn16.c.inc"
1095 /* Include decoders for factored-out extensions */
1096 #include "decode-XVentanaCondOps.c.inc"
1098 /* The specification allows for longer insns, but not supported by qemu. */
1099 #define MAX_INSN_LEN 4
1101 static inline int insn_len(uint16_t first_word
)
1103 return (first_word
& 3) == 3 ? 4 : 2;
1106 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
1109 * A table with predicate (i.e., guard) functions and decoder functions
1110 * that are tested in-order until a decoder matches onto the opcode.
1112 static const struct {
1113 bool (*guard_func
)(DisasContext
*);
1114 bool (*decode_func
)(DisasContext
*, uint32_t);
1116 { always_true_p
, decode_insn32
},
1117 { has_xthead_p
, decode_xthead
},
1118 { has_XVentanaCondOps_p
, decode_XVentanaCodeOps
},
1121 ctx
->virt_inst_excp
= false;
1122 /* Check for compressed insn */
1123 if (insn_len(opcode
) == 2) {
1124 ctx
->opcode
= opcode
;
1125 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
1126 if (has_ext(ctx
, RVC
) && decode_insn16(ctx
, opcode
)) {
1130 uint32_t opcode32
= opcode
;
1131 opcode32
= deposit32(opcode32
, 16, 16,
1132 translator_lduw(env
, &ctx
->base
,
1133 ctx
->base
.pc_next
+ 2));
1134 ctx
->opcode
= opcode32
;
1135 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
1137 for (size_t i
= 0; i
< ARRAY_SIZE(decoders
); ++i
) {
1138 if (decoders
[i
].guard_func(ctx
) &&
1139 decoders
[i
].decode_func(ctx
, opcode32
)) {
1145 gen_exception_illegal(ctx
);
1148 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
1150 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1151 CPURISCVState
*env
= cs
->env_ptr
;
1152 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1153 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
1155 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
1156 ctx
->mem_idx
= FIELD_EX32(tb_flags
, TB_FLAGS
, MEM_IDX
);
1157 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
1158 ctx
->mstatus_vs
= tb_flags
& TB_FLAGS_MSTATUS_VS
;
1159 ctx
->priv_ver
= env
->priv_ver
;
1160 #if !defined(CONFIG_USER_ONLY)
1161 if (riscv_has_ext(env
, RVH
)) {
1162 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
1164 ctx
->virt_enabled
= false;
1167 ctx
->virt_enabled
= false;
1169 ctx
->misa_ext
= env
->misa_ext
;
1170 ctx
->frm
= -1; /* unknown rounding mode */
1171 ctx
->cfg_ptr
= &(cpu
->cfg
);
1172 ctx
->mstatus_hs_fs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_FS
);
1173 ctx
->mstatus_hs_vs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_VS
);
1174 ctx
->hlsx
= FIELD_EX32(tb_flags
, TB_FLAGS
, HLSX
);
1175 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
1176 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
1177 ctx
->lmul
= sextract32(FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
), 0, 3);
1178 ctx
->vta
= FIELD_EX32(tb_flags
, TB_FLAGS
, VTA
) && cpu
->cfg
.rvv_ta_all_1s
;
1179 ctx
->vma
= FIELD_EX32(tb_flags
, TB_FLAGS
, VMA
) && cpu
->cfg
.rvv_ma_all_1s
;
1180 ctx
->cfg_vta_all_1s
= cpu
->cfg
.rvv_ta_all_1s
;
1181 ctx
->vstart
= env
->vstart
;
1182 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
1183 ctx
->misa_mxl_max
= env
->misa_mxl_max
;
1184 ctx
->xl
= FIELD_EX32(tb_flags
, TB_FLAGS
, XL
);
1187 memset(ctx
->temp
, 0, sizeof(ctx
->temp
));
1189 memset(ctx
->ftemp
, 0, sizeof(ctx
->ftemp
));
1190 ctx
->pm_mask_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_MASK_ENABLED
);
1191 ctx
->pm_base_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_BASE_ENABLED
);
1192 ctx
->itrigger
= FIELD_EX32(tb_flags
, TB_FLAGS
, ITRIGGER
);
1193 ctx
->zero
= tcg_constant_tl(0);
1196 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
1200 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1202 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1204 tcg_gen_insn_start(ctx
->base
.pc_next
, 0);
1205 ctx
->insn_start
= tcg_last_op();
1208 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1210 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1211 CPURISCVState
*env
= cpu
->env_ptr
;
1212 uint16_t opcode16
= translator_lduw(env
, &ctx
->base
, ctx
->base
.pc_next
);
1216 decode_opc(env
, ctx
, opcode16
);
1217 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
1219 for (i
= ctx
->ntemp
- 1; i
>= 0; --i
) {
1220 tcg_temp_free(ctx
->temp
[i
]);
1221 ctx
->temp
[i
] = NULL
;
1224 for (i
= ctx
->nftemp
- 1; i
>= 0; --i
) {
1225 tcg_temp_free_i64(ctx
->ftemp
[i
]);
1226 ctx
->ftemp
[i
] = NULL
;
1230 /* Only the first insn within a TB is allowed to cross a page boundary. */
1231 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
1232 if (ctx
->itrigger
|| !is_same_page(&ctx
->base
, ctx
->base
.pc_next
)) {
1233 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1235 unsigned page_ofs
= ctx
->base
.pc_next
& ~TARGET_PAGE_MASK
;
1237 if (page_ofs
> TARGET_PAGE_SIZE
- MAX_INSN_LEN
) {
1238 uint16_t next_insn
= cpu_lduw_code(env
, ctx
->base
.pc_next
);
1239 int len
= insn_len(next_insn
);
1241 if (!is_same_page(&ctx
->base
, ctx
->base
.pc_next
+ len
)) {
1242 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1249 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1251 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1253 switch (ctx
->base
.is_jmp
) {
1254 case DISAS_TOO_MANY
:
1255 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1257 case DISAS_NORETURN
:
1260 g_assert_not_reached();
1264 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
,
1265 CPUState
*cpu
, FILE *logfile
)
1267 #ifndef CONFIG_USER_ONLY
1268 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
1269 CPURISCVState
*env
= &rvcpu
->env
;
1272 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1273 #ifndef CONFIG_USER_ONLY
1274 fprintf(logfile
, "Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n",
1275 env
->priv
, env
->virt
);
1277 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1280 static const TranslatorOps riscv_tr_ops
= {
1281 .init_disas_context
= riscv_tr_init_disas_context
,
1282 .tb_start
= riscv_tr_tb_start
,
1283 .insn_start
= riscv_tr_insn_start
,
1284 .translate_insn
= riscv_tr_translate_insn
,
1285 .tb_stop
= riscv_tr_tb_stop
,
1286 .disas_log
= riscv_tr_disas_log
,
1289 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
,
1290 target_ulong pc
, void *host_pc
)
1294 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &riscv_tr_ops
, &ctx
.base
);
1297 void riscv_translate_init(void)
1302 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1303 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1304 * unless you specifically block reads/writes to reg 0.
1309 for (i
= 1; i
< 32; i
++) {
1310 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
1311 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
1312 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
1313 offsetof(CPURISCVState
, gprh
[i
]), riscv_int_regnamesh
[i
]);
1316 for (i
= 0; i
< 32; i
++) {
1317 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
1318 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
1321 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
1322 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
1323 cpu_vstart
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vstart
),
1325 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
1327 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),
1329 /* Assign PM CSRs to tcg globals */
1330 pm_mask
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmmask
),
1332 pm_base
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmbase
),