2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
33 #include "internals.h"
35 /* global register indices */
36 static TCGv cpu_gpr
[32], cpu_gprh
[32], cpu_pc
, cpu_vl
, cpu_vstart
;
37 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
40 /* globals for PM CSRs */
44 #include "exec/gen-icount.h"
47 * If an operation is being performed on less than TARGET_LONG_BITS,
48 * it may require the inputs to be sign- or zero-extended; which will
49 * depend on the exact operation being performed.
57 typedef struct DisasContext
{
58 DisasContextBase base
;
59 /* pc_succ_insn points to the instruction following base.pc_next */
60 target_ulong pc_succ_insn
;
61 target_ulong priv_ver
;
62 RISCVMXL misa_mxl_max
;
68 uint32_t mstatus_hs_fs
;
69 uint32_t mstatus_hs_vs
;
71 /* Remember the rounding mode encoded in the previous fp instruction,
72 which we have already installed into env->fp_status. Or -1 for
73 no previous fp instruction. Note that we exit the TB when writing
74 to any system register, which includes CSR_FRM, so we do not have
75 to reset this known value. */
79 const RISCVCPUConfig
*cfg_ptr
;
81 /* vector extension */
84 * Encode LMUL to lmul as follows:
104 /* Space for 3 operands plus 1 extra for address computation. */
106 /* Space for 4 operands(1 dest and <=3 src) for float point computation */
109 /* PointerMasking extension */
110 bool pm_mask_enabled
;
111 bool pm_base_enabled
;
112 /* TCG of the current insn_start */
116 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
118 return ctx
->misa_ext
& ext
;
121 static bool always_true_p(DisasContext
*ctx
__attribute__((__unused__
)))
126 #define MATERIALISE_EXT_PREDICATE(ext) \
127 static bool has_ ## ext ## _p(DisasContext *ctx) \
129 return ctx->cfg_ptr->ext_ ## ext ; \
132 MATERIALISE_EXT_PREDICATE(XVentanaCondOps
);
134 #ifdef TARGET_RISCV32
135 #define get_xl(ctx) MXL_RV32
136 #elif defined(CONFIG_USER_ONLY)
137 #define get_xl(ctx) MXL_RV64
139 #define get_xl(ctx) ((ctx)->xl)
142 /* The word size for this machine mode. */
143 static inline int __attribute__((unused
)) get_xlen(DisasContext
*ctx
)
145 return 16 << get_xl(ctx
);
148 /* The operation length, as opposed to the xlen. */
149 #ifdef TARGET_RISCV32
150 #define get_ol(ctx) MXL_RV32
152 #define get_ol(ctx) ((ctx)->ol)
155 static inline int get_olen(DisasContext
*ctx
)
157 return 16 << get_ol(ctx
);
160 /* The maximum register length */
161 #ifdef TARGET_RISCV32
162 #define get_xl_max(ctx) MXL_RV32
164 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
168 * RISC-V requires NaN-boxing of narrower width floating point values.
169 * This applies when a 32-bit value is assigned to a 64-bit FP register.
170 * For consistency and simplicity, we nanbox results even when the RVD
171 * extension is not present.
173 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
175 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
178 static void gen_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
180 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(16, 48));
184 * A narrow n-bit operation, where n < FLEN, checks that input operands
185 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
186 * If so, the least-significant bits of the input are used, otherwise the
187 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
189 * Here, the result is always nan-boxed, even the canonical nan.
191 static void gen_check_nanbox_h(TCGv_i64 out
, TCGv_i64 in
)
193 TCGv_i64 t_max
= tcg_const_i64(0xffffffffffff0000ull
);
194 TCGv_i64 t_nan
= tcg_const_i64(0xffffffffffff7e00ull
);
196 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
197 tcg_temp_free_i64(t_max
);
198 tcg_temp_free_i64(t_nan
);
201 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
203 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
204 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
206 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
209 static void decode_save_opc(DisasContext
*ctx
)
211 assert(ctx
->insn_start
!= NULL
);
212 tcg_set_insn_start_param(ctx
->insn_start
, 1, ctx
->opcode
);
213 ctx
->insn_start
= NULL
;
216 static void gen_set_pc_imm(DisasContext
*ctx
, target_ulong dest
)
218 if (get_xl(ctx
) == MXL_RV32
) {
219 dest
= (int32_t)dest
;
221 tcg_gen_movi_tl(cpu_pc
, dest
);
224 static void gen_set_pc(DisasContext
*ctx
, TCGv dest
)
226 if (get_xl(ctx
) == MXL_RV32
) {
227 tcg_gen_ext32s_tl(cpu_pc
, dest
);
229 tcg_gen_mov_tl(cpu_pc
, dest
);
233 static void generate_exception(DisasContext
*ctx
, int excp
)
235 gen_set_pc_imm(ctx
, ctx
->base
.pc_next
);
236 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
237 ctx
->base
.is_jmp
= DISAS_NORETURN
;
240 static void gen_exception_illegal(DisasContext
*ctx
)
242 tcg_gen_st_i32(tcg_constant_i32(ctx
->opcode
), cpu_env
,
243 offsetof(CPURISCVState
, bins
));
244 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
247 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
249 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
250 generate_exception(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
253 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
255 if (translator_use_goto_tb(&ctx
->base
, dest
)) {
257 gen_set_pc_imm(ctx
, dest
);
258 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
260 gen_set_pc_imm(ctx
, dest
);
261 tcg_gen_lookup_and_goto_ptr();
266 * Wrappers for getting reg values.
268 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
269 * constant zero as a source, and an uninitialized sink as destination.
271 * Further, we may provide an extension for word operations.
273 static TCGv
temp_new(DisasContext
*ctx
)
275 assert(ctx
->ntemp
< ARRAY_SIZE(ctx
->temp
));
276 return ctx
->temp
[ctx
->ntemp
++] = tcg_temp_new();
279 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
287 switch (get_ol(ctx
)) {
294 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
298 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
301 g_assert_not_reached();
308 g_assert_not_reached();
310 return cpu_gpr
[reg_num
];
313 static TCGv
get_gprh(DisasContext
*ctx
, int reg_num
)
315 assert(get_xl(ctx
) == MXL_RV128
);
319 return cpu_gprh
[reg_num
];
322 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
324 if (reg_num
== 0 || get_olen(ctx
) < TARGET_LONG_BITS
) {
325 return temp_new(ctx
);
327 return cpu_gpr
[reg_num
];
330 static TCGv
dest_gprh(DisasContext
*ctx
, int reg_num
)
333 return temp_new(ctx
);
335 return cpu_gprh
[reg_num
];
338 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
341 switch (get_ol(ctx
)) {
343 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
347 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
350 g_assert_not_reached();
353 if (get_xl_max(ctx
) == MXL_RV128
) {
354 tcg_gen_sari_tl(cpu_gprh
[reg_num
], cpu_gpr
[reg_num
], 63);
359 static void gen_set_gpri(DisasContext
*ctx
, int reg_num
, target_long imm
)
362 switch (get_ol(ctx
)) {
364 tcg_gen_movi_tl(cpu_gpr
[reg_num
], (int32_t)imm
);
368 tcg_gen_movi_tl(cpu_gpr
[reg_num
], imm
);
371 g_assert_not_reached();
374 if (get_xl_max(ctx
) == MXL_RV128
) {
375 tcg_gen_movi_tl(cpu_gprh
[reg_num
], -(imm
< 0));
380 static void gen_set_gpr128(DisasContext
*ctx
, int reg_num
, TCGv rl
, TCGv rh
)
382 assert(get_ol(ctx
) == MXL_RV128
);
384 tcg_gen_mov_tl(cpu_gpr
[reg_num
], rl
);
385 tcg_gen_mov_tl(cpu_gprh
[reg_num
], rh
);
389 static TCGv_i64
ftemp_new(DisasContext
*ctx
)
391 assert(ctx
->nftemp
< ARRAY_SIZE(ctx
->ftemp
));
392 return ctx
->ftemp
[ctx
->nftemp
++] = tcg_temp_new_i64();
395 static TCGv_i64
get_fpr_hs(DisasContext
*ctx
, int reg_num
)
397 if (!ctx
->cfg_ptr
->ext_zfinx
) {
398 return cpu_fpr
[reg_num
];
402 return tcg_constant_i64(0);
404 switch (get_xl(ctx
)) {
406 #ifdef TARGET_RISCV32
408 TCGv_i64 t
= ftemp_new(ctx
);
409 tcg_gen_ext_i32_i64(t
, cpu_gpr
[reg_num
]);
415 return cpu_gpr
[reg_num
];
418 g_assert_not_reached();
422 static TCGv_i64
get_fpr_d(DisasContext
*ctx
, int reg_num
)
424 if (!ctx
->cfg_ptr
->ext_zfinx
) {
425 return cpu_fpr
[reg_num
];
429 return tcg_constant_i64(0);
431 switch (get_xl(ctx
)) {
434 TCGv_i64 t
= ftemp_new(ctx
);
435 tcg_gen_concat_tl_i64(t
, cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1]);
438 #ifdef TARGET_RISCV64
440 return cpu_gpr
[reg_num
];
443 g_assert_not_reached();
447 static TCGv_i64
dest_fpr(DisasContext
*ctx
, int reg_num
)
449 if (!ctx
->cfg_ptr
->ext_zfinx
) {
450 return cpu_fpr
[reg_num
];
454 return ftemp_new(ctx
);
457 switch (get_xl(ctx
)) {
459 return ftemp_new(ctx
);
460 #ifdef TARGET_RISCV64
462 return cpu_gpr
[reg_num
];
465 g_assert_not_reached();
469 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */
470 static void gen_set_fpr_hs(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
472 if (!ctx
->cfg_ptr
->ext_zfinx
) {
473 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
477 switch (get_xl(ctx
)) {
479 #ifdef TARGET_RISCV32
480 tcg_gen_extrl_i64_i32(cpu_gpr
[reg_num
], t
);
485 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
489 g_assert_not_reached();
494 static void gen_set_fpr_d(DisasContext
*ctx
, int reg_num
, TCGv_i64 t
)
496 if (!ctx
->cfg_ptr
->ext_zfinx
) {
497 tcg_gen_mov_i64(cpu_fpr
[reg_num
], t
);
502 switch (get_xl(ctx
)) {
504 #ifdef TARGET_RISCV32
505 tcg_gen_extr_i64_i32(cpu_gpr
[reg_num
], cpu_gpr
[reg_num
+ 1], t
);
508 tcg_gen_ext32s_i64(cpu_gpr
[reg_num
], t
);
509 tcg_gen_sari_i64(cpu_gpr
[reg_num
+ 1], t
, 32);
512 tcg_gen_mov_i64(cpu_gpr
[reg_num
], t
);
516 g_assert_not_reached();
521 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
523 target_ulong next_pc
;
525 /* check misaligned: */
526 next_pc
= ctx
->base
.pc_next
+ imm
;
527 if (!has_ext(ctx
, RVC
)) {
528 if ((next_pc
& 0x3) != 0) {
529 gen_exception_inst_addr_mis(ctx
);
534 gen_set_gpri(ctx
, rd
, ctx
->pc_succ_insn
);
535 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
536 ctx
->base
.is_jmp
= DISAS_NORETURN
;
539 /* Compute a canonical address from a register plus offset. */
540 static TCGv
get_address(DisasContext
*ctx
, int rs1
, int imm
)
542 TCGv addr
= temp_new(ctx
);
543 TCGv src1
= get_gpr(ctx
, rs1
, EXT_NONE
);
545 tcg_gen_addi_tl(addr
, src1
, imm
);
546 if (ctx
->pm_mask_enabled
) {
547 tcg_gen_and_tl(addr
, addr
, pm_mask
);
548 } else if (get_xl(ctx
) == MXL_RV32
) {
549 tcg_gen_ext32u_tl(addr
, addr
);
551 if (ctx
->pm_base_enabled
) {
552 tcg_gen_or_tl(addr
, addr
, pm_base
);
557 #ifndef CONFIG_USER_ONLY
558 /* The states of mstatus_fs are:
559 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
560 * We will have already diagnosed disabled state,
561 * and need to turn initial/clean into dirty.
563 static void mark_fs_dirty(DisasContext
*ctx
)
567 if (!has_ext(ctx
, RVF
)) {
571 if (ctx
->mstatus_fs
!= MSTATUS_FS
) {
572 /* Remember the state change for the rest of the TB. */
573 ctx
->mstatus_fs
= MSTATUS_FS
;
575 tmp
= tcg_temp_new();
576 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
577 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
578 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
582 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_fs
!= MSTATUS_FS
) {
583 /* Remember the stage change for the rest of the TB. */
584 ctx
->mstatus_hs_fs
= MSTATUS_FS
;
586 tmp
= tcg_temp_new();
587 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
588 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
);
589 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
594 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
597 #ifndef CONFIG_USER_ONLY
598 /* The states of mstatus_vs are:
599 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
600 * We will have already diagnosed disabled state,
601 * and need to turn initial/clean into dirty.
603 static void mark_vs_dirty(DisasContext
*ctx
)
607 if (ctx
->mstatus_vs
!= MSTATUS_VS
) {
608 /* Remember the state change for the rest of the TB. */
609 ctx
->mstatus_vs
= MSTATUS_VS
;
611 tmp
= tcg_temp_new();
612 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
613 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
614 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
618 if (ctx
->virt_enabled
&& ctx
->mstatus_hs_vs
!= MSTATUS_VS
) {
619 /* Remember the stage change for the rest of the TB. */
620 ctx
->mstatus_hs_vs
= MSTATUS_VS
;
622 tmp
= tcg_temp_new();
623 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
624 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_VS
);
625 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
630 static inline void mark_vs_dirty(DisasContext
*ctx
) { }
633 static void gen_set_rm(DisasContext
*ctx
, int rm
)
635 if (ctx
->frm
== rm
) {
640 if (rm
== RISCV_FRM_ROD
) {
641 gen_helper_set_rod_rounding_mode(cpu_env
);
645 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
646 decode_save_opc(ctx
);
647 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
650 static int ex_plus_1(DisasContext
*ctx
, int nf
)
655 #define EX_SH(amount) \
656 static int ex_shift_##amount(DisasContext *ctx, int imm) \
658 return imm << amount; \
666 #define REQUIRE_EXT(ctx, ext) do { \
667 if (!has_ext(ctx, ext)) { \
672 #define REQUIRE_32BIT(ctx) do { \
673 if (get_xl(ctx) != MXL_RV32) { \
678 #define REQUIRE_64BIT(ctx) do { \
679 if (get_xl(ctx) != MXL_RV64) { \
684 #define REQUIRE_128BIT(ctx) do { \
685 if (get_xl(ctx) != MXL_RV128) { \
690 #define REQUIRE_64_OR_128BIT(ctx) do { \
691 if (get_xl(ctx) == MXL_RV32) { \
696 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \
697 if (!ctx->cfg_ptr->ext_##A && \
698 !ctx->cfg_ptr->ext_##B) { \
703 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
708 static int ex_rvc_shifti(DisasContext
*ctx
, int imm
)
710 /* For RV128 a shamt of 0 means a shift by 64. */
711 return imm
? imm
: 64;
714 /* Include the auto-generated decoder for 32 bit insn */
715 #include "decode-insn32.c.inc"
717 static bool gen_logic_imm_fn(DisasContext
*ctx
, arg_i
*a
,
718 void (*func
)(TCGv
, TCGv
, target_long
))
720 TCGv dest
= dest_gpr(ctx
, a
->rd
);
721 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
723 func(dest
, src1
, a
->imm
);
725 if (get_xl(ctx
) == MXL_RV128
) {
726 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
727 TCGv desth
= dest_gprh(ctx
, a
->rd
);
729 func(desth
, src1h
, -(a
->imm
< 0));
730 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
732 gen_set_gpr(ctx
, a
->rd
, dest
);
738 static bool gen_logic(DisasContext
*ctx
, arg_r
*a
,
739 void (*func
)(TCGv
, TCGv
, TCGv
))
741 TCGv dest
= dest_gpr(ctx
, a
->rd
);
742 TCGv src1
= get_gpr(ctx
, a
->rs1
, EXT_NONE
);
743 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
745 func(dest
, src1
, src2
);
747 if (get_xl(ctx
) == MXL_RV128
) {
748 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
749 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
750 TCGv desth
= dest_gprh(ctx
, a
->rd
);
752 func(desth
, src1h
, src2h
);
753 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
755 gen_set_gpr(ctx
, a
->rd
, dest
);
761 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
762 void (*func
)(TCGv
, TCGv
, target_long
),
763 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
765 TCGv dest
= dest_gpr(ctx
, a
->rd
);
766 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
768 if (get_ol(ctx
) < MXL_RV128
) {
769 func(dest
, src1
, a
->imm
);
770 gen_set_gpr(ctx
, a
->rd
, dest
);
776 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
777 TCGv desth
= dest_gprh(ctx
, a
->rd
);
779 f128(dest
, desth
, src1
, src1h
, a
->imm
);
780 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
785 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
786 void (*func
)(TCGv
, TCGv
, TCGv
),
787 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
789 TCGv dest
= dest_gpr(ctx
, a
->rd
);
790 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
791 TCGv src2
= tcg_constant_tl(a
->imm
);
793 if (get_ol(ctx
) < MXL_RV128
) {
794 func(dest
, src1
, src2
);
795 gen_set_gpr(ctx
, a
->rd
, dest
);
801 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
802 TCGv src2h
= tcg_constant_tl(-(a
->imm
< 0));
803 TCGv desth
= dest_gprh(ctx
, a
->rd
);
805 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
806 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
811 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
812 void (*func
)(TCGv
, TCGv
, TCGv
),
813 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
815 TCGv dest
= dest_gpr(ctx
, a
->rd
);
816 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
817 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
819 if (get_ol(ctx
) < MXL_RV128
) {
820 func(dest
, src1
, src2
);
821 gen_set_gpr(ctx
, a
->rd
, dest
);
827 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
828 TCGv src2h
= get_gprh(ctx
, a
->rs2
);
829 TCGv desth
= dest_gprh(ctx
, a
->rd
);
831 f128(dest
, desth
, src1
, src1h
, src2
, src2h
);
832 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
837 static bool gen_arith_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
838 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
839 void (*f_32
)(TCGv
, TCGv
, TCGv
),
840 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
842 int olen
= get_olen(ctx
);
844 if (olen
!= TARGET_LONG_BITS
) {
847 } else if (olen
!= 128) {
848 g_assert_not_reached();
851 return gen_arith(ctx
, a
, ext
, f_tl
, f_128
);
854 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
855 void (*func
)(TCGv
, TCGv
, target_long
),
856 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, target_long
))
859 int max_len
= get_olen(ctx
);
861 if (a
->shamt
>= max_len
) {
865 dest
= dest_gpr(ctx
, a
->rd
);
866 src1
= get_gpr(ctx
, a
->rs1
, ext
);
869 func(dest
, src1
, a
->shamt
);
870 gen_set_gpr(ctx
, a
->rd
, dest
);
872 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
873 TCGv desth
= dest_gprh(ctx
, a
->rd
);
878 f128(dest
, desth
, src1
, src1h
, a
->shamt
);
879 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
884 static bool gen_shift_imm_fn_per_ol(DisasContext
*ctx
, arg_shift
*a
,
886 void (*f_tl
)(TCGv
, TCGv
, target_long
),
887 void (*f_32
)(TCGv
, TCGv
, target_long
),
888 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
,
891 int olen
= get_olen(ctx
);
892 if (olen
!= TARGET_LONG_BITS
) {
895 } else if (olen
!= 128) {
896 g_assert_not_reached();
899 return gen_shift_imm_fn(ctx
, a
, ext
, f_tl
, f_128
);
902 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
903 void (*func
)(TCGv
, TCGv
, TCGv
))
905 TCGv dest
, src1
, src2
;
906 int max_len
= get_olen(ctx
);
908 if (a
->shamt
>= max_len
) {
912 dest
= dest_gpr(ctx
, a
->rd
);
913 src1
= get_gpr(ctx
, a
->rs1
, ext
);
914 src2
= tcg_constant_tl(a
->shamt
);
916 func(dest
, src1
, src2
);
918 gen_set_gpr(ctx
, a
->rd
, dest
);
922 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
923 void (*func
)(TCGv
, TCGv
, TCGv
),
924 void (*f128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
926 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
927 TCGv ext2
= tcg_temp_new();
928 int max_len
= get_olen(ctx
);
930 tcg_gen_andi_tl(ext2
, src2
, max_len
- 1);
932 TCGv dest
= dest_gpr(ctx
, a
->rd
);
933 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
936 func(dest
, src1
, ext2
);
937 gen_set_gpr(ctx
, a
->rd
, dest
);
939 TCGv src1h
= get_gprh(ctx
, a
->rs1
);
940 TCGv desth
= dest_gprh(ctx
, a
->rd
);
945 f128(dest
, desth
, src1
, src1h
, ext2
);
946 gen_set_gpr128(ctx
, a
->rd
, dest
, desth
);
952 static bool gen_shift_per_ol(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
953 void (*f_tl
)(TCGv
, TCGv
, TCGv
),
954 void (*f_32
)(TCGv
, TCGv
, TCGv
),
955 void (*f_128
)(TCGv
, TCGv
, TCGv
, TCGv
, TCGv
))
957 int olen
= get_olen(ctx
);
958 if (olen
!= TARGET_LONG_BITS
) {
961 } else if (olen
!= 128) {
962 g_assert_not_reached();
965 return gen_shift(ctx
, a
, ext
, f_tl
, f_128
);
968 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
969 void (*func
)(TCGv
, TCGv
))
971 TCGv dest
= dest_gpr(ctx
, a
->rd
);
972 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
976 gen_set_gpr(ctx
, a
->rd
, dest
);
980 static bool gen_unary_per_ol(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
981 void (*f_tl
)(TCGv
, TCGv
),
982 void (*f_32
)(TCGv
, TCGv
))
984 int olen
= get_olen(ctx
);
986 if (olen
!= TARGET_LONG_BITS
) {
990 g_assert_not_reached();
993 return gen_unary(ctx
, a
, ext
, f_tl
);
996 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
998 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
999 CPUState
*cpu
= ctx
->cs
;
1000 CPURISCVState
*env
= cpu
->env_ptr
;
1002 return cpu_ldl_code(env
, pc
);
1005 /* Include insn module translation function */
1006 #include "insn_trans/trans_rvi.c.inc"
1007 #include "insn_trans/trans_rvm.c.inc"
1008 #include "insn_trans/trans_rva.c.inc"
1009 #include "insn_trans/trans_rvf.c.inc"
1010 #include "insn_trans/trans_rvd.c.inc"
1011 #include "insn_trans/trans_rvh.c.inc"
1012 #include "insn_trans/trans_rvv.c.inc"
1013 #include "insn_trans/trans_rvb.c.inc"
1014 #include "insn_trans/trans_rvzfh.c.inc"
1015 #include "insn_trans/trans_rvk.c.inc"
1016 #include "insn_trans/trans_privileged.c.inc"
1017 #include "insn_trans/trans_svinval.c.inc"
1018 #include "insn_trans/trans_xventanacondops.c.inc"
1020 /* Include the auto-generated decoder for 16 bit insn */
1021 #include "decode-insn16.c.inc"
1022 /* Include decoders for factored-out extensions */
1023 #include "decode-XVentanaCondOps.c.inc"
1025 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
1028 * A table with predicate (i.e., guard) functions and decoder functions
1029 * that are tested in-order until a decoder matches onto the opcode.
1031 static const struct {
1032 bool (*guard_func
)(DisasContext
*);
1033 bool (*decode_func
)(DisasContext
*, uint32_t);
1035 { always_true_p
, decode_insn32
},
1036 { has_XVentanaCondOps_p
, decode_XVentanaCodeOps
},
1039 /* Check for compressed insn */
1040 if (extract16(opcode
, 0, 2) != 3) {
1041 if (!has_ext(ctx
, RVC
)) {
1042 gen_exception_illegal(ctx
);
1044 ctx
->opcode
= opcode
;
1045 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
1046 if (decode_insn16(ctx
, opcode
)) {
1051 uint32_t opcode32
= opcode
;
1052 opcode32
= deposit32(opcode32
, 16, 16,
1053 translator_lduw(env
, &ctx
->base
,
1054 ctx
->base
.pc_next
+ 2));
1055 ctx
->opcode
= opcode32
;
1056 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
1058 for (size_t i
= 0; i
< ARRAY_SIZE(decoders
); ++i
) {
1059 if (decoders
[i
].guard_func(ctx
) &&
1060 decoders
[i
].decode_func(ctx
, opcode32
)) {
1066 gen_exception_illegal(ctx
);
1069 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
1071 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1072 CPURISCVState
*env
= cs
->env_ptr
;
1073 RISCVCPU
*cpu
= RISCV_CPU(cs
);
1074 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
1076 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
1077 ctx
->mem_idx
= FIELD_EX32(tb_flags
, TB_FLAGS
, MEM_IDX
);
1078 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
1079 ctx
->mstatus_vs
= tb_flags
& TB_FLAGS_MSTATUS_VS
;
1080 ctx
->priv_ver
= env
->priv_ver
;
1081 #if !defined(CONFIG_USER_ONLY)
1082 if (riscv_has_ext(env
, RVH
)) {
1083 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
1085 ctx
->virt_enabled
= false;
1088 ctx
->virt_enabled
= false;
1090 ctx
->misa_ext
= env
->misa_ext
;
1091 ctx
->frm
= -1; /* unknown rounding mode */
1092 ctx
->cfg_ptr
= &(cpu
->cfg
);
1093 ctx
->mstatus_hs_fs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_FS
);
1094 ctx
->mstatus_hs_vs
= FIELD_EX32(tb_flags
, TB_FLAGS
, MSTATUS_HS_VS
);
1095 ctx
->hlsx
= FIELD_EX32(tb_flags
, TB_FLAGS
, HLSX
);
1096 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
1097 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
1098 ctx
->lmul
= sextract32(FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
), 0, 3);
1099 ctx
->vta
= FIELD_EX32(tb_flags
, TB_FLAGS
, VTA
) && cpu
->cfg
.rvv_ta_all_1s
;
1100 ctx
->cfg_vta_all_1s
= cpu
->cfg
.rvv_ta_all_1s
;
1101 ctx
->vstart
= env
->vstart
;
1102 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
1103 ctx
->misa_mxl_max
= env
->misa_mxl_max
;
1104 ctx
->xl
= FIELD_EX32(tb_flags
, TB_FLAGS
, XL
);
1107 memset(ctx
->temp
, 0, sizeof(ctx
->temp
));
1109 memset(ctx
->ftemp
, 0, sizeof(ctx
->ftemp
));
1110 ctx
->pm_mask_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_MASK_ENABLED
);
1111 ctx
->pm_base_enabled
= FIELD_EX32(tb_flags
, TB_FLAGS
, PM_BASE_ENABLED
);
1112 ctx
->zero
= tcg_constant_tl(0);
1115 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
1119 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1121 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1123 tcg_gen_insn_start(ctx
->base
.pc_next
, 0);
1124 ctx
->insn_start
= tcg_last_op();
1127 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1129 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1130 CPURISCVState
*env
= cpu
->env_ptr
;
1131 uint16_t opcode16
= translator_lduw(env
, &ctx
->base
, ctx
->base
.pc_next
);
1135 decode_opc(env
, ctx
, opcode16
);
1136 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
1138 for (i
= ctx
->ntemp
- 1; i
>= 0; --i
) {
1139 tcg_temp_free(ctx
->temp
[i
]);
1140 ctx
->temp
[i
] = NULL
;
1143 for (i
= ctx
->nftemp
- 1; i
>= 0; --i
) {
1144 tcg_temp_free_i64(ctx
->ftemp
[i
]);
1145 ctx
->ftemp
[i
] = NULL
;
1149 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
1150 target_ulong page_start
;
1152 page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
1153 if (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
) {
1154 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
1159 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1161 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
1163 switch (ctx
->base
.is_jmp
) {
1164 case DISAS_TOO_MANY
:
1165 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1167 case DISAS_NORETURN
:
1170 g_assert_not_reached();
1174 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
,
1175 CPUState
*cpu
, FILE *logfile
)
1177 #ifndef CONFIG_USER_ONLY
1178 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
1179 CPURISCVState
*env
= &rvcpu
->env
;
1182 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1183 #ifndef CONFIG_USER_ONLY
1184 fprintf(logfile
, "Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n",
1185 env
->priv
, env
->virt
);
1187 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1190 static const TranslatorOps riscv_tr_ops
= {
1191 .init_disas_context
= riscv_tr_init_disas_context
,
1192 .tb_start
= riscv_tr_tb_start
,
1193 .insn_start
= riscv_tr_insn_start
,
1194 .translate_insn
= riscv_tr_translate_insn
,
1195 .tb_stop
= riscv_tr_tb_stop
,
1196 .disas_log
= riscv_tr_disas_log
,
1199 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
1203 translator_loop(&riscv_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
1206 void riscv_translate_init(void)
1211 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1212 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1213 * unless you specifically block reads/writes to reg 0.
1218 for (i
= 1; i
< 32; i
++) {
1219 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
1220 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
1221 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
1222 offsetof(CPURISCVState
, gprh
[i
]), riscv_int_regnamesh
[i
]);
1225 for (i
= 0; i
< 32; i
++) {
1226 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
1227 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
1230 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
1231 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
1232 cpu_vstart
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vstart
),
1234 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
1236 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),
1238 /* Assign PM CSRs to tcg globals */
1239 pm_mask
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmmask
),
1241 pm_base
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, cur_pmbase
),