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target/riscv: vector integer comparison instructions
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1 /*
2 * RISC-V Vector Extension Helpers for QEMU.
3 *
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/memop.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "tcg/tcg-gvec-desc.h"
25 #include "internals.h"
26 #include <math.h>
27
28 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
29 target_ulong s2)
30 {
31 int vlmax, vl;
32 RISCVCPU *cpu = env_archcpu(env);
33 uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
34 uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
35 bool vill = FIELD_EX64(s2, VTYPE, VILL);
36 target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
37
38 if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
39 /* only set vill bit. */
40 env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
41 env->vl = 0;
42 env->vstart = 0;
43 return 0;
44 }
45
46 vlmax = vext_get_vlmax(cpu, s2);
47 if (s1 <= vlmax) {
48 vl = s1;
49 } else {
50 vl = vlmax;
51 }
52 env->vl = vl;
53 env->vtype = s2;
54 env->vstart = 0;
55 return vl;
56 }
57
58 /*
59 * Note that vector data is stored in host-endian 64-bit chunks,
60 * so addressing units smaller than that needs a host-endian fixup.
61 */
62 #ifdef HOST_WORDS_BIGENDIAN
63 #define H1(x) ((x) ^ 7)
64 #define H1_2(x) ((x) ^ 6)
65 #define H1_4(x) ((x) ^ 4)
66 #define H2(x) ((x) ^ 3)
67 #define H4(x) ((x) ^ 1)
68 #define H8(x) ((x))
69 #else
70 #define H1(x) (x)
71 #define H1_2(x) (x)
72 #define H1_4(x) (x)
73 #define H2(x) (x)
74 #define H4(x) (x)
75 #define H8(x) (x)
76 #endif
77
78 static inline uint32_t vext_nf(uint32_t desc)
79 {
80 return FIELD_EX32(simd_data(desc), VDATA, NF);
81 }
82
83 static inline uint32_t vext_mlen(uint32_t desc)
84 {
85 return FIELD_EX32(simd_data(desc), VDATA, MLEN);
86 }
87
88 static inline uint32_t vext_vm(uint32_t desc)
89 {
90 return FIELD_EX32(simd_data(desc), VDATA, VM);
91 }
92
93 static inline uint32_t vext_lmul(uint32_t desc)
94 {
95 return FIELD_EX32(simd_data(desc), VDATA, LMUL);
96 }
97
98 static uint32_t vext_wd(uint32_t desc)
99 {
100 return (simd_data(desc) >> 11) & 0x1;
101 }
102
103 /*
104 * Get vector group length in bytes. Its range is [64, 2048].
105 *
106 * As simd_desc support at most 256, the max vlen is 512 bits.
107 * So vlen in bytes is encoded as maxsz.
108 */
109 static inline uint32_t vext_maxsz(uint32_t desc)
110 {
111 return simd_maxsz(desc) << vext_lmul(desc);
112 }
113
114 /*
115 * This function checks watchpoint before real load operation.
116 *
117 * In softmmu mode, the TLB API probe_access is enough for watchpoint check.
118 * In user mode, there is no watchpoint support now.
119 *
120 * It will trigger an exception if there is no mapping in TLB
121 * and page table walk can't fill the TLB entry. Then the guest
122 * software can return here after process the exception or never return.
123 */
124 static void probe_pages(CPURISCVState *env, target_ulong addr,
125 target_ulong len, uintptr_t ra,
126 MMUAccessType access_type)
127 {
128 target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
129 target_ulong curlen = MIN(pagelen, len);
130
131 probe_access(env, addr, curlen, access_type,
132 cpu_mmu_index(env, false), ra);
133 if (len > curlen) {
134 addr += curlen;
135 curlen = len - curlen;
136 probe_access(env, addr, curlen, access_type,
137 cpu_mmu_index(env, false), ra);
138 }
139 }
140
141 #ifdef HOST_WORDS_BIGENDIAN
142 static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
143 {
144 /*
145 * Split the remaining range to two parts.
146 * The first part is in the last uint64_t unit.
147 * The second part start from the next uint64_t unit.
148 */
149 int part1 = 0, part2 = tot - cnt;
150 if (cnt % 8) {
151 part1 = 8 - (cnt % 8);
152 part2 = tot - cnt - part1;
153 memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1);
154 memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2);
155 } else {
156 memset(tail, 0, part2);
157 }
158 }
159 #else
160 static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
161 {
162 memset(tail, 0, tot - cnt);
163 }
164 #endif
165
166 static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
167 {
168 int8_t *cur = ((int8_t *)vd + H1(idx));
169 vext_clear(cur, cnt, tot);
170 }
171
172 static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
173 {
174 int16_t *cur = ((int16_t *)vd + H2(idx));
175 vext_clear(cur, cnt, tot);
176 }
177
178 static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
179 {
180 int32_t *cur = ((int32_t *)vd + H4(idx));
181 vext_clear(cur, cnt, tot);
182 }
183
184 static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
185 {
186 int64_t *cur = (int64_t *)vd + idx;
187 vext_clear(cur, cnt, tot);
188 }
189
190 static inline void vext_set_elem_mask(void *v0, int mlen, int index,
191 uint8_t value)
192 {
193 int idx = (index * mlen) / 64;
194 int pos = (index * mlen) % 64;
195 uint64_t old = ((uint64_t *)v0)[idx];
196 ((uint64_t *)v0)[idx] = deposit64(old, pos, mlen, value);
197 }
198
199 static inline int vext_elem_mask(void *v0, int mlen, int index)
200 {
201 int idx = (index * mlen) / 64;
202 int pos = (index * mlen) % 64;
203 return (((uint64_t *)v0)[idx] >> pos) & 1;
204 }
205
206 /* elements operations for load and store */
207 typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
208 uint32_t idx, void *vd, uintptr_t retaddr);
209 typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot);
210
211 #define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
212 static void NAME(CPURISCVState *env, abi_ptr addr, \
213 uint32_t idx, void *vd, uintptr_t retaddr)\
214 { \
215 MTYPE data; \
216 ETYPE *cur = ((ETYPE *)vd + H(idx)); \
217 data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
218 *cur = data; \
219 } \
220
221 GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb)
222 GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb)
223 GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb)
224 GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb)
225 GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw)
226 GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw)
227 GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw)
228 GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl)
229 GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl)
230 GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb)
231 GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw)
232 GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl)
233 GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq)
234 GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub)
235 GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub)
236 GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub)
237 GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub)
238 GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw)
239 GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw)
240 GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw)
241 GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl)
242 GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl)
243
244 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
245 static void NAME(CPURISCVState *env, abi_ptr addr, \
246 uint32_t idx, void *vd, uintptr_t retaddr)\
247 { \
248 ETYPE data = *((ETYPE *)vd + H(idx)); \
249 cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
250 }
251
252 GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb)
253 GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb)
254 GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb)
255 GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb)
256 GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw)
257 GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw)
258 GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw)
259 GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl)
260 GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl)
261 GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
262 GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
263 GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
264 GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq)
265
266 /*
267 *** stride: access vector element from strided memory
268 */
269 static void
270 vext_ldst_stride(void *vd, void *v0, target_ulong base,
271 target_ulong stride, CPURISCVState *env,
272 uint32_t desc, uint32_t vm,
273 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
274 uint32_t esz, uint32_t msz, uintptr_t ra,
275 MMUAccessType access_type)
276 {
277 uint32_t i, k;
278 uint32_t nf = vext_nf(desc);
279 uint32_t mlen = vext_mlen(desc);
280 uint32_t vlmax = vext_maxsz(desc) / esz;
281
282 /* probe every access*/
283 for (i = 0; i < env->vl; i++) {
284 if (!vm && !vext_elem_mask(v0, mlen, i)) {
285 continue;
286 }
287 probe_pages(env, base + stride * i, nf * msz, ra, access_type);
288 }
289 /* do real access */
290 for (i = 0; i < env->vl; i++) {
291 k = 0;
292 if (!vm && !vext_elem_mask(v0, mlen, i)) {
293 continue;
294 }
295 while (k < nf) {
296 target_ulong addr = base + stride * i + k * msz;
297 ldst_elem(env, addr, i + k * vlmax, vd, ra);
298 k++;
299 }
300 }
301 /* clear tail elements */
302 if (clear_elem) {
303 for (k = 0; k < nf; k++) {
304 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
305 }
306 }
307 }
308
309 #define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
310 void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
311 target_ulong stride, CPURISCVState *env, \
312 uint32_t desc) \
313 { \
314 uint32_t vm = vext_vm(desc); \
315 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
316 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
317 GETPC(), MMU_DATA_LOAD); \
318 }
319
320 GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb)
321 GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh)
322 GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl)
323 GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq)
324 GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh)
325 GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl)
326 GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq)
327 GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl)
328 GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq)
329 GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb)
330 GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh)
331 GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl)
332 GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq)
333 GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
334 GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
335 GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
336 GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
337 GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
338 GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
339 GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
340 GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
341 GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
342
343 #define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \
344 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
345 target_ulong stride, CPURISCVState *env, \
346 uint32_t desc) \
347 { \
348 uint32_t vm = vext_vm(desc); \
349 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
350 NULL, sizeof(ETYPE), sizeof(MTYPE), \
351 GETPC(), MMU_DATA_STORE); \
352 }
353
354 GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b)
355 GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h)
356 GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w)
357 GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d)
358 GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h)
359 GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w)
360 GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d)
361 GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w)
362 GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d)
363 GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b)
364 GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h)
365 GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w)
366 GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
367
368 /*
369 *** unit-stride: access elements stored contiguously in memory
370 */
371
372 /* unmasked unit-stride load and store operation*/
373 static void
374 vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
375 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
376 uint32_t esz, uint32_t msz, uintptr_t ra,
377 MMUAccessType access_type)
378 {
379 uint32_t i, k;
380 uint32_t nf = vext_nf(desc);
381 uint32_t vlmax = vext_maxsz(desc) / esz;
382
383 /* probe every access */
384 probe_pages(env, base, env->vl * nf * msz, ra, access_type);
385 /* load bytes from guest memory */
386 for (i = 0; i < env->vl; i++) {
387 k = 0;
388 while (k < nf) {
389 target_ulong addr = base + (i * nf + k) * msz;
390 ldst_elem(env, addr, i + k * vlmax, vd, ra);
391 k++;
392 }
393 }
394 /* clear tail elements */
395 if (clear_elem) {
396 for (k = 0; k < nf; k++) {
397 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
398 }
399 }
400 }
401
402 /*
403 * masked unit-stride load and store operation will be a special case of stride,
404 * stride = NF * sizeof (MTYPE)
405 */
406
407 #define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
408 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
409 CPURISCVState *env, uint32_t desc) \
410 { \
411 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
412 vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
413 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
414 GETPC(), MMU_DATA_LOAD); \
415 } \
416 \
417 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
418 CPURISCVState *env, uint32_t desc) \
419 { \
420 vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \
421 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \
422 }
423
424 GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb)
425 GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh)
426 GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl)
427 GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq)
428 GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh)
429 GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl)
430 GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq)
431 GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl)
432 GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq)
433 GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb)
434 GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh)
435 GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl)
436 GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq)
437 GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
438 GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
439 GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
440 GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
441 GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
442 GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
443 GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
444 GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
445 GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
446
447 #define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \
448 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
449 CPURISCVState *env, uint32_t desc) \
450 { \
451 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
452 vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
453 NULL, sizeof(ETYPE), sizeof(MTYPE), \
454 GETPC(), MMU_DATA_STORE); \
455 } \
456 \
457 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
458 CPURISCVState *env, uint32_t desc) \
459 { \
460 vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \
461 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\
462 }
463
464 GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b)
465 GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h)
466 GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w)
467 GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d)
468 GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h)
469 GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w)
470 GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d)
471 GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w)
472 GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d)
473 GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b)
474 GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h)
475 GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w)
476 GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d)
477
478 /*
479 *** index: access vector element from indexed memory
480 */
481 typedef target_ulong vext_get_index_addr(target_ulong base,
482 uint32_t idx, void *vs2);
483
484 #define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \
485 static target_ulong NAME(target_ulong base, \
486 uint32_t idx, void *vs2) \
487 { \
488 return (base + *((ETYPE *)vs2 + H(idx))); \
489 }
490
491 GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
492 GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
493 GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
494 GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
495
496 static inline void
497 vext_ldst_index(void *vd, void *v0, target_ulong base,
498 void *vs2, CPURISCVState *env, uint32_t desc,
499 vext_get_index_addr get_index_addr,
500 vext_ldst_elem_fn *ldst_elem,
501 clear_fn *clear_elem,
502 uint32_t esz, uint32_t msz, uintptr_t ra,
503 MMUAccessType access_type)
504 {
505 uint32_t i, k;
506 uint32_t nf = vext_nf(desc);
507 uint32_t vm = vext_vm(desc);
508 uint32_t mlen = vext_mlen(desc);
509 uint32_t vlmax = vext_maxsz(desc) / esz;
510
511 /* probe every access*/
512 for (i = 0; i < env->vl; i++) {
513 if (!vm && !vext_elem_mask(v0, mlen, i)) {
514 continue;
515 }
516 probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
517 access_type);
518 }
519 /* load bytes from guest memory */
520 for (i = 0; i < env->vl; i++) {
521 k = 0;
522 if (!vm && !vext_elem_mask(v0, mlen, i)) {
523 continue;
524 }
525 while (k < nf) {
526 abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
527 ldst_elem(env, addr, i + k * vlmax, vd, ra);
528 k++;
529 }
530 }
531 /* clear tail elements */
532 if (clear_elem) {
533 for (k = 0; k < nf; k++) {
534 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
535 }
536 }
537 }
538
539 #define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \
540 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
541 void *vs2, CPURISCVState *env, uint32_t desc) \
542 { \
543 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
544 LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
545 GETPC(), MMU_DATA_LOAD); \
546 }
547
548 GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb)
549 GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh)
550 GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl)
551 GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq)
552 GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh)
553 GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl)
554 GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq)
555 GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl)
556 GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq)
557 GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb)
558 GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh)
559 GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl)
560 GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq)
561 GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb)
562 GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh)
563 GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl)
564 GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq)
565 GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh)
566 GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl)
567 GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq)
568 GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl)
569 GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq)
570
571 #define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
572 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
573 void *vs2, CPURISCVState *env, uint32_t desc) \
574 { \
575 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
576 STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\
577 GETPC(), MMU_DATA_STORE); \
578 }
579
580 GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b)
581 GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h)
582 GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w)
583 GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d)
584 GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h)
585 GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w)
586 GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d)
587 GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w)
588 GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d)
589 GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
590 GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
591 GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
592 GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
593
594 /*
595 *** unit-stride fault-only-fisrt load instructions
596 */
597 static inline void
598 vext_ldff(void *vd, void *v0, target_ulong base,
599 CPURISCVState *env, uint32_t desc,
600 vext_ldst_elem_fn *ldst_elem,
601 clear_fn *clear_elem,
602 uint32_t esz, uint32_t msz, uintptr_t ra)
603 {
604 void *host;
605 uint32_t i, k, vl = 0;
606 uint32_t mlen = vext_mlen(desc);
607 uint32_t nf = vext_nf(desc);
608 uint32_t vm = vext_vm(desc);
609 uint32_t vlmax = vext_maxsz(desc) / esz;
610 target_ulong addr, offset, remain;
611
612 /* probe every access*/
613 for (i = 0; i < env->vl; i++) {
614 if (!vm && !vext_elem_mask(v0, mlen, i)) {
615 continue;
616 }
617 addr = base + nf * i * msz;
618 if (i == 0) {
619 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
620 } else {
621 /* if it triggers an exception, no need to check watchpoint */
622 remain = nf * msz;
623 while (remain > 0) {
624 offset = -(addr | TARGET_PAGE_MASK);
625 host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
626 cpu_mmu_index(env, false));
627 if (host) {
628 #ifdef CONFIG_USER_ONLY
629 if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
630 vl = i;
631 goto ProbeSuccess;
632 }
633 #else
634 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
635 #endif
636 } else {
637 vl = i;
638 goto ProbeSuccess;
639 }
640 if (remain <= offset) {
641 break;
642 }
643 remain -= offset;
644 addr += offset;
645 }
646 }
647 }
648 ProbeSuccess:
649 /* load bytes from guest memory */
650 if (vl != 0) {
651 env->vl = vl;
652 }
653 for (i = 0; i < env->vl; i++) {
654 k = 0;
655 if (!vm && !vext_elem_mask(v0, mlen, i)) {
656 continue;
657 }
658 while (k < nf) {
659 target_ulong addr = base + (i * nf + k) * msz;
660 ldst_elem(env, addr, i + k * vlmax, vd, ra);
661 k++;
662 }
663 }
664 /* clear tail elements */
665 if (vl != 0) {
666 return;
667 }
668 for (k = 0; k < nf; k++) {
669 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
670 }
671 }
672
673 #define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
674 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
675 CPURISCVState *env, uint32_t desc) \
676 { \
677 vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
678 sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
679 }
680
681 GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb)
682 GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh)
683 GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl)
684 GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq)
685 GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh)
686 GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl)
687 GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq)
688 GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl)
689 GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq)
690 GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb)
691 GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh)
692 GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl)
693 GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq)
694 GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb)
695 GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh)
696 GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl)
697 GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq)
698 GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh)
699 GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl)
700 GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq)
701 GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl)
702 GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq)
703
704 /*
705 *** Vector AMO Operations (Zvamo)
706 */
707 typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
708 uint32_t wd, uint32_t idx, CPURISCVState *env,
709 uintptr_t retaddr);
710
711 /* no atomic opreation for vector atomic insructions */
712 #define DO_SWAP(N, M) (M)
713 #define DO_AND(N, M) (N & M)
714 #define DO_XOR(N, M) (N ^ M)
715 #define DO_OR(N, M) (N | M)
716 #define DO_ADD(N, M) (N + M)
717
718 #define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \
719 static void \
720 vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
721 uint32_t wd, uint32_t idx, \
722 CPURISCVState *env, uintptr_t retaddr)\
723 { \
724 typedef int##ESZ##_t ETYPE; \
725 typedef int##MSZ##_t MTYPE; \
726 typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \
727 ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \
728 MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \
729 \
730 cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \
731 if (wd) { \
732 *pe3 = a; \
733 } \
734 }
735
736 /* Signed min/max */
737 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
738 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
739
740 /* Unsigned min/max */
741 #define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
742 #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
743
744 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l)
745 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l)
746 GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l)
747 GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l)
748 GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l)
749 GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
750 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
751 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
752 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
753 #ifdef TARGET_RISCV64
754 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
755 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
756 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
757 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q)
758 GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l)
759 GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q)
760 GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l)
761 GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q)
762 GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l)
763 GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q)
764 GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l)
765 GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q)
766 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l)
767 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q)
768 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
769 GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
770 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
771 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
772 #endif
773
774 static inline void
775 vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
776 void *vs2, CPURISCVState *env, uint32_t desc,
777 vext_get_index_addr get_index_addr,
778 vext_amo_noatomic_fn *noatomic_op,
779 clear_fn *clear_elem,
780 uint32_t esz, uint32_t msz, uintptr_t ra)
781 {
782 uint32_t i;
783 target_long addr;
784 uint32_t wd = vext_wd(desc);
785 uint32_t vm = vext_vm(desc);
786 uint32_t mlen = vext_mlen(desc);
787 uint32_t vlmax = vext_maxsz(desc) / esz;
788
789 for (i = 0; i < env->vl; i++) {
790 if (!vm && !vext_elem_mask(v0, mlen, i)) {
791 continue;
792 }
793 probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
794 probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
795 }
796 for (i = 0; i < env->vl; i++) {
797 if (!vm && !vext_elem_mask(v0, mlen, i)) {
798 continue;
799 }
800 addr = get_index_addr(base, i, vs2);
801 noatomic_op(vs3, addr, wd, i, env, ra);
802 }
803 clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
804 }
805
806 #define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \
807 void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
808 void *vs2, CPURISCVState *env, uint32_t desc) \
809 { \
810 vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
811 INDEX_FN, vext_##NAME##_noatomic_op, \
812 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
813 GETPC()); \
814 }
815
816 #ifdef TARGET_RISCV64
817 GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq)
818 GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq)
819 GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq)
820 GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq)
821 GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq)
822 GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq)
823 GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq)
824 GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq)
825 GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq)
826 GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq)
827 GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq)
828 GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq)
829 GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq)
830 GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq)
831 GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
832 GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
833 GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
834 GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
835 #endif
836 GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl)
837 GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl)
838 GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl)
839 GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl)
840 GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl)
841 GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl)
842 GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl)
843 GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl)
844 GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
845
846 /*
847 *** Vector Integer Arithmetic Instructions
848 */
849
850 /* expand macro args before macro */
851 #define RVVCALL(macro, ...) macro(__VA_ARGS__)
852
853 /* (TD, T1, T2, TX1, TX2) */
854 #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t
855 #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t
856 #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t
857 #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t
858
859 /* operation of two vector elements */
860 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
861
862 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
863 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
864 { \
865 TX1 s1 = *((T1 *)vs1 + HS1(i)); \
866 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
867 *((TD *)vd + HD(i)) = OP(s2, s1); \
868 }
869 #define DO_SUB(N, M) (N - M)
870 #define DO_RSUB(N, M) (M - N)
871
872 RVVCALL(OPIVV2, vadd_vv_b, OP_SSS_B, H1, H1, H1, DO_ADD)
873 RVVCALL(OPIVV2, vadd_vv_h, OP_SSS_H, H2, H2, H2, DO_ADD)
874 RVVCALL(OPIVV2, vadd_vv_w, OP_SSS_W, H4, H4, H4, DO_ADD)
875 RVVCALL(OPIVV2, vadd_vv_d, OP_SSS_D, H8, H8, H8, DO_ADD)
876 RVVCALL(OPIVV2, vsub_vv_b, OP_SSS_B, H1, H1, H1, DO_SUB)
877 RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB)
878 RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB)
879 RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
880
881 static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
882 CPURISCVState *env, uint32_t desc,
883 uint32_t esz, uint32_t dsz,
884 opivv2_fn *fn, clear_fn *clearfn)
885 {
886 uint32_t vlmax = vext_maxsz(desc) / esz;
887 uint32_t mlen = vext_mlen(desc);
888 uint32_t vm = vext_vm(desc);
889 uint32_t vl = env->vl;
890 uint32_t i;
891
892 for (i = 0; i < vl; i++) {
893 if (!vm && !vext_elem_mask(v0, mlen, i)) {
894 continue;
895 }
896 fn(vd, vs1, vs2, i);
897 }
898 clearfn(vd, vl, vl * dsz, vlmax * dsz);
899 }
900
901 /* generate the helpers for OPIVV */
902 #define GEN_VEXT_VV(NAME, ESZ, DSZ, CLEAR_FN) \
903 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
904 void *vs2, CPURISCVState *env, \
905 uint32_t desc) \
906 { \
907 do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \
908 do_##NAME, CLEAR_FN); \
909 }
910
911 GEN_VEXT_VV(vadd_vv_b, 1, 1, clearb)
912 GEN_VEXT_VV(vadd_vv_h, 2, 2, clearh)
913 GEN_VEXT_VV(vadd_vv_w, 4, 4, clearl)
914 GEN_VEXT_VV(vadd_vv_d, 8, 8, clearq)
915 GEN_VEXT_VV(vsub_vv_b, 1, 1, clearb)
916 GEN_VEXT_VV(vsub_vv_h, 2, 2, clearh)
917 GEN_VEXT_VV(vsub_vv_w, 4, 4, clearl)
918 GEN_VEXT_VV(vsub_vv_d, 8, 8, clearq)
919
920 typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
921
922 /*
923 * (T1)s1 gives the real operator type.
924 * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
925 */
926 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
927 static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
928 { \
929 TX2 s2 = *((T2 *)vs2 + HS2(i)); \
930 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \
931 }
932
933 RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD)
934 RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD)
935 RVVCALL(OPIVX2, vadd_vx_w, OP_SSS_W, H4, H4, DO_ADD)
936 RVVCALL(OPIVX2, vadd_vx_d, OP_SSS_D, H8, H8, DO_ADD)
937 RVVCALL(OPIVX2, vsub_vx_b, OP_SSS_B, H1, H1, DO_SUB)
938 RVVCALL(OPIVX2, vsub_vx_h, OP_SSS_H, H2, H2, DO_SUB)
939 RVVCALL(OPIVX2, vsub_vx_w, OP_SSS_W, H4, H4, DO_SUB)
940 RVVCALL(OPIVX2, vsub_vx_d, OP_SSS_D, H8, H8, DO_SUB)
941 RVVCALL(OPIVX2, vrsub_vx_b, OP_SSS_B, H1, H1, DO_RSUB)
942 RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB)
943 RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB)
944 RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
945
946 static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
947 CPURISCVState *env, uint32_t desc,
948 uint32_t esz, uint32_t dsz,
949 opivx2_fn fn, clear_fn *clearfn)
950 {
951 uint32_t vlmax = vext_maxsz(desc) / esz;
952 uint32_t mlen = vext_mlen(desc);
953 uint32_t vm = vext_vm(desc);
954 uint32_t vl = env->vl;
955 uint32_t i;
956
957 for (i = 0; i < vl; i++) {
958 if (!vm && !vext_elem_mask(v0, mlen, i)) {
959 continue;
960 }
961 fn(vd, s1, vs2, i);
962 }
963 clearfn(vd, vl, vl * dsz, vlmax * dsz);
964 }
965
966 /* generate the helpers for OPIVX */
967 #define GEN_VEXT_VX(NAME, ESZ, DSZ, CLEAR_FN) \
968 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
969 void *vs2, CPURISCVState *env, \
970 uint32_t desc) \
971 { \
972 do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \
973 do_##NAME, CLEAR_FN); \
974 }
975
976 GEN_VEXT_VX(vadd_vx_b, 1, 1, clearb)
977 GEN_VEXT_VX(vadd_vx_h, 2, 2, clearh)
978 GEN_VEXT_VX(vadd_vx_w, 4, 4, clearl)
979 GEN_VEXT_VX(vadd_vx_d, 8, 8, clearq)
980 GEN_VEXT_VX(vsub_vx_b, 1, 1, clearb)
981 GEN_VEXT_VX(vsub_vx_h, 2, 2, clearh)
982 GEN_VEXT_VX(vsub_vx_w, 4, 4, clearl)
983 GEN_VEXT_VX(vsub_vx_d, 8, 8, clearq)
984 GEN_VEXT_VX(vrsub_vx_b, 1, 1, clearb)
985 GEN_VEXT_VX(vrsub_vx_h, 2, 2, clearh)
986 GEN_VEXT_VX(vrsub_vx_w, 4, 4, clearl)
987 GEN_VEXT_VX(vrsub_vx_d, 8, 8, clearq)
988
989 void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc)
990 {
991 intptr_t oprsz = simd_oprsz(desc);
992 intptr_t i;
993
994 for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
995 *(uint8_t *)(d + i) = (uint8_t)b - *(uint8_t *)(a + i);
996 }
997 }
998
999 void HELPER(vec_rsubs16)(void *d, void *a, uint64_t b, uint32_t desc)
1000 {
1001 intptr_t oprsz = simd_oprsz(desc);
1002 intptr_t i;
1003
1004 for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
1005 *(uint16_t *)(d + i) = (uint16_t)b - *(uint16_t *)(a + i);
1006 }
1007 }
1008
1009 void HELPER(vec_rsubs32)(void *d, void *a, uint64_t b, uint32_t desc)
1010 {
1011 intptr_t oprsz = simd_oprsz(desc);
1012 intptr_t i;
1013
1014 for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
1015 *(uint32_t *)(d + i) = (uint32_t)b - *(uint32_t *)(a + i);
1016 }
1017 }
1018
1019 void HELPER(vec_rsubs64)(void *d, void *a, uint64_t b, uint32_t desc)
1020 {
1021 intptr_t oprsz = simd_oprsz(desc);
1022 intptr_t i;
1023
1024 for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
1025 *(uint64_t *)(d + i) = b - *(uint64_t *)(a + i);
1026 }
1027 }
1028
1029 /* Vector Widening Integer Add/Subtract */
1030 #define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t
1031 #define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t
1032 #define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t
1033 #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t
1034 #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t
1035 #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t
1036 #define WOP_WUUU_B uint16_t, uint8_t, uint16_t, uint16_t, uint16_t
1037 #define WOP_WUUU_H uint32_t, uint16_t, uint32_t, uint32_t, uint32_t
1038 #define WOP_WUUU_W uint64_t, uint32_t, uint64_t, uint64_t, uint64_t
1039 #define WOP_WSSS_B int16_t, int8_t, int16_t, int16_t, int16_t
1040 #define WOP_WSSS_H int32_t, int16_t, int32_t, int32_t, int32_t
1041 #define WOP_WSSS_W int64_t, int32_t, int64_t, int64_t, int64_t
1042 RVVCALL(OPIVV2, vwaddu_vv_b, WOP_UUU_B, H2, H1, H1, DO_ADD)
1043 RVVCALL(OPIVV2, vwaddu_vv_h, WOP_UUU_H, H4, H2, H2, DO_ADD)
1044 RVVCALL(OPIVV2, vwaddu_vv_w, WOP_UUU_W, H8, H4, H4, DO_ADD)
1045 RVVCALL(OPIVV2, vwsubu_vv_b, WOP_UUU_B, H2, H1, H1, DO_SUB)
1046 RVVCALL(OPIVV2, vwsubu_vv_h, WOP_UUU_H, H4, H2, H2, DO_SUB)
1047 RVVCALL(OPIVV2, vwsubu_vv_w, WOP_UUU_W, H8, H4, H4, DO_SUB)
1048 RVVCALL(OPIVV2, vwadd_vv_b, WOP_SSS_B, H2, H1, H1, DO_ADD)
1049 RVVCALL(OPIVV2, vwadd_vv_h, WOP_SSS_H, H4, H2, H2, DO_ADD)
1050 RVVCALL(OPIVV2, vwadd_vv_w, WOP_SSS_W, H8, H4, H4, DO_ADD)
1051 RVVCALL(OPIVV2, vwsub_vv_b, WOP_SSS_B, H2, H1, H1, DO_SUB)
1052 RVVCALL(OPIVV2, vwsub_vv_h, WOP_SSS_H, H4, H2, H2, DO_SUB)
1053 RVVCALL(OPIVV2, vwsub_vv_w, WOP_SSS_W, H8, H4, H4, DO_SUB)
1054 RVVCALL(OPIVV2, vwaddu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_ADD)
1055 RVVCALL(OPIVV2, vwaddu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_ADD)
1056 RVVCALL(OPIVV2, vwaddu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_ADD)
1057 RVVCALL(OPIVV2, vwsubu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_SUB)
1058 RVVCALL(OPIVV2, vwsubu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_SUB)
1059 RVVCALL(OPIVV2, vwsubu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_SUB)
1060 RVVCALL(OPIVV2, vwadd_wv_b, WOP_WSSS_B, H2, H1, H1, DO_ADD)
1061 RVVCALL(OPIVV2, vwadd_wv_h, WOP_WSSS_H, H4, H2, H2, DO_ADD)
1062 RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD)
1063 RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB)
1064 RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB)
1065 RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB)
1066 GEN_VEXT_VV(vwaddu_vv_b, 1, 2, clearh)
1067 GEN_VEXT_VV(vwaddu_vv_h, 2, 4, clearl)
1068 GEN_VEXT_VV(vwaddu_vv_w, 4, 8, clearq)
1069 GEN_VEXT_VV(vwsubu_vv_b, 1, 2, clearh)
1070 GEN_VEXT_VV(vwsubu_vv_h, 2, 4, clearl)
1071 GEN_VEXT_VV(vwsubu_vv_w, 4, 8, clearq)
1072 GEN_VEXT_VV(vwadd_vv_b, 1, 2, clearh)
1073 GEN_VEXT_VV(vwadd_vv_h, 2, 4, clearl)
1074 GEN_VEXT_VV(vwadd_vv_w, 4, 8, clearq)
1075 GEN_VEXT_VV(vwsub_vv_b, 1, 2, clearh)
1076 GEN_VEXT_VV(vwsub_vv_h, 2, 4, clearl)
1077 GEN_VEXT_VV(vwsub_vv_w, 4, 8, clearq)
1078 GEN_VEXT_VV(vwaddu_wv_b, 1, 2, clearh)
1079 GEN_VEXT_VV(vwaddu_wv_h, 2, 4, clearl)
1080 GEN_VEXT_VV(vwaddu_wv_w, 4, 8, clearq)
1081 GEN_VEXT_VV(vwsubu_wv_b, 1, 2, clearh)
1082 GEN_VEXT_VV(vwsubu_wv_h, 2, 4, clearl)
1083 GEN_VEXT_VV(vwsubu_wv_w, 4, 8, clearq)
1084 GEN_VEXT_VV(vwadd_wv_b, 1, 2, clearh)
1085 GEN_VEXT_VV(vwadd_wv_h, 2, 4, clearl)
1086 GEN_VEXT_VV(vwadd_wv_w, 4, 8, clearq)
1087 GEN_VEXT_VV(vwsub_wv_b, 1, 2, clearh)
1088 GEN_VEXT_VV(vwsub_wv_h, 2, 4, clearl)
1089 GEN_VEXT_VV(vwsub_wv_w, 4, 8, clearq)
1090
1091 RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD)
1092 RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD)
1093 RVVCALL(OPIVX2, vwaddu_vx_w, WOP_UUU_W, H8, H4, DO_ADD)
1094 RVVCALL(OPIVX2, vwsubu_vx_b, WOP_UUU_B, H2, H1, DO_SUB)
1095 RVVCALL(OPIVX2, vwsubu_vx_h, WOP_UUU_H, H4, H2, DO_SUB)
1096 RVVCALL(OPIVX2, vwsubu_vx_w, WOP_UUU_W, H8, H4, DO_SUB)
1097 RVVCALL(OPIVX2, vwadd_vx_b, WOP_SSS_B, H2, H1, DO_ADD)
1098 RVVCALL(OPIVX2, vwadd_vx_h, WOP_SSS_H, H4, H2, DO_ADD)
1099 RVVCALL(OPIVX2, vwadd_vx_w, WOP_SSS_W, H8, H4, DO_ADD)
1100 RVVCALL(OPIVX2, vwsub_vx_b, WOP_SSS_B, H2, H1, DO_SUB)
1101 RVVCALL(OPIVX2, vwsub_vx_h, WOP_SSS_H, H4, H2, DO_SUB)
1102 RVVCALL(OPIVX2, vwsub_vx_w, WOP_SSS_W, H8, H4, DO_SUB)
1103 RVVCALL(OPIVX2, vwaddu_wx_b, WOP_WUUU_B, H2, H1, DO_ADD)
1104 RVVCALL(OPIVX2, vwaddu_wx_h, WOP_WUUU_H, H4, H2, DO_ADD)
1105 RVVCALL(OPIVX2, vwaddu_wx_w, WOP_WUUU_W, H8, H4, DO_ADD)
1106 RVVCALL(OPIVX2, vwsubu_wx_b, WOP_WUUU_B, H2, H1, DO_SUB)
1107 RVVCALL(OPIVX2, vwsubu_wx_h, WOP_WUUU_H, H4, H2, DO_SUB)
1108 RVVCALL(OPIVX2, vwsubu_wx_w, WOP_WUUU_W, H8, H4, DO_SUB)
1109 RVVCALL(OPIVX2, vwadd_wx_b, WOP_WSSS_B, H2, H1, DO_ADD)
1110 RVVCALL(OPIVX2, vwadd_wx_h, WOP_WSSS_H, H4, H2, DO_ADD)
1111 RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD)
1112 RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB)
1113 RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB)
1114 RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB)
1115 GEN_VEXT_VX(vwaddu_vx_b, 1, 2, clearh)
1116 GEN_VEXT_VX(vwaddu_vx_h, 2, 4, clearl)
1117 GEN_VEXT_VX(vwaddu_vx_w, 4, 8, clearq)
1118 GEN_VEXT_VX(vwsubu_vx_b, 1, 2, clearh)
1119 GEN_VEXT_VX(vwsubu_vx_h, 2, 4, clearl)
1120 GEN_VEXT_VX(vwsubu_vx_w, 4, 8, clearq)
1121 GEN_VEXT_VX(vwadd_vx_b, 1, 2, clearh)
1122 GEN_VEXT_VX(vwadd_vx_h, 2, 4, clearl)
1123 GEN_VEXT_VX(vwadd_vx_w, 4, 8, clearq)
1124 GEN_VEXT_VX(vwsub_vx_b, 1, 2, clearh)
1125 GEN_VEXT_VX(vwsub_vx_h, 2, 4, clearl)
1126 GEN_VEXT_VX(vwsub_vx_w, 4, 8, clearq)
1127 GEN_VEXT_VX(vwaddu_wx_b, 1, 2, clearh)
1128 GEN_VEXT_VX(vwaddu_wx_h, 2, 4, clearl)
1129 GEN_VEXT_VX(vwaddu_wx_w, 4, 8, clearq)
1130 GEN_VEXT_VX(vwsubu_wx_b, 1, 2, clearh)
1131 GEN_VEXT_VX(vwsubu_wx_h, 2, 4, clearl)
1132 GEN_VEXT_VX(vwsubu_wx_w, 4, 8, clearq)
1133 GEN_VEXT_VX(vwadd_wx_b, 1, 2, clearh)
1134 GEN_VEXT_VX(vwadd_wx_h, 2, 4, clearl)
1135 GEN_VEXT_VX(vwadd_wx_w, 4, 8, clearq)
1136 GEN_VEXT_VX(vwsub_wx_b, 1, 2, clearh)
1137 GEN_VEXT_VX(vwsub_wx_h, 2, 4, clearl)
1138 GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq)
1139
1140 /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
1141 #define DO_VADC(N, M, C) (N + M + C)
1142 #define DO_VSBC(N, M, C) (N - M - C)
1143
1144 #define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
1145 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1146 CPURISCVState *env, uint32_t desc) \
1147 { \
1148 uint32_t mlen = vext_mlen(desc); \
1149 uint32_t vl = env->vl; \
1150 uint32_t esz = sizeof(ETYPE); \
1151 uint32_t vlmax = vext_maxsz(desc) / esz; \
1152 uint32_t i; \
1153 \
1154 for (i = 0; i < vl; i++) { \
1155 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1156 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1157 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1158 \
1159 *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
1160 } \
1161 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1162 }
1163
1164 GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb)
1165 GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC, clearh)
1166 GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC, clearl)
1167 GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC, clearq)
1168
1169 GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC, clearb)
1170 GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC, clearh)
1171 GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC, clearl)
1172 GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq)
1173
1174 #define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
1175 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
1176 CPURISCVState *env, uint32_t desc) \
1177 { \
1178 uint32_t mlen = vext_mlen(desc); \
1179 uint32_t vl = env->vl; \
1180 uint32_t esz = sizeof(ETYPE); \
1181 uint32_t vlmax = vext_maxsz(desc) / esz; \
1182 uint32_t i; \
1183 \
1184 for (i = 0; i < vl; i++) { \
1185 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1186 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1187 \
1188 *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
1189 } \
1190 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1191 }
1192
1193 GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb)
1194 GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC, clearh)
1195 GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC, clearl)
1196 GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC, clearq)
1197
1198 GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC, clearb)
1199 GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC, clearh)
1200 GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC, clearl)
1201 GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
1202
1203 #define DO_MADC(N, M, C) (C ? (__typeof(N))(N + M + 1) <= N : \
1204 (__typeof(N))(N + M) < N)
1205 #define DO_MSBC(N, M, C) (C ? N <= M : N < M)
1206
1207 #define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \
1208 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1209 CPURISCVState *env, uint32_t desc) \
1210 { \
1211 uint32_t mlen = vext_mlen(desc); \
1212 uint32_t vl = env->vl; \
1213 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1214 uint32_t i; \
1215 \
1216 for (i = 0; i < vl; i++) { \
1217 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1218 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1219 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1220 \
1221 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\
1222 } \
1223 for (; i < vlmax; i++) { \
1224 vext_set_elem_mask(vd, mlen, i, 0); \
1225 } \
1226 }
1227
1228 GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
1229 GEN_VEXT_VMADC_VVM(vmadc_vvm_h, uint16_t, H2, DO_MADC)
1230 GEN_VEXT_VMADC_VVM(vmadc_vvm_w, uint32_t, H4, DO_MADC)
1231 GEN_VEXT_VMADC_VVM(vmadc_vvm_d, uint64_t, H8, DO_MADC)
1232
1233 GEN_VEXT_VMADC_VVM(vmsbc_vvm_b, uint8_t, H1, DO_MSBC)
1234 GEN_VEXT_VMADC_VVM(vmsbc_vvm_h, uint16_t, H2, DO_MSBC)
1235 GEN_VEXT_VMADC_VVM(vmsbc_vvm_w, uint32_t, H4, DO_MSBC)
1236 GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC)
1237
1238 #define GEN_VEXT_VMADC_VXM(NAME, ETYPE, H, DO_OP) \
1239 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
1240 void *vs2, CPURISCVState *env, uint32_t desc) \
1241 { \
1242 uint32_t mlen = vext_mlen(desc); \
1243 uint32_t vl = env->vl; \
1244 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1245 uint32_t i; \
1246 \
1247 for (i = 0; i < vl; i++) { \
1248 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1249 uint8_t carry = vext_elem_mask(v0, mlen, i); \
1250 \
1251 vext_set_elem_mask(vd, mlen, i, \
1252 DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
1253 } \
1254 for (; i < vlmax; i++) { \
1255 vext_set_elem_mask(vd, mlen, i, 0); \
1256 } \
1257 }
1258
1259 GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC)
1260 GEN_VEXT_VMADC_VXM(vmadc_vxm_h, uint16_t, H2, DO_MADC)
1261 GEN_VEXT_VMADC_VXM(vmadc_vxm_w, uint32_t, H4, DO_MADC)
1262 GEN_VEXT_VMADC_VXM(vmadc_vxm_d, uint64_t, H8, DO_MADC)
1263
1264 GEN_VEXT_VMADC_VXM(vmsbc_vxm_b, uint8_t, H1, DO_MSBC)
1265 GEN_VEXT_VMADC_VXM(vmsbc_vxm_h, uint16_t, H2, DO_MSBC)
1266 GEN_VEXT_VMADC_VXM(vmsbc_vxm_w, uint32_t, H4, DO_MSBC)
1267 GEN_VEXT_VMADC_VXM(vmsbc_vxm_d, uint64_t, H8, DO_MSBC)
1268
1269 /* Vector Bitwise Logical Instructions */
1270 RVVCALL(OPIVV2, vand_vv_b, OP_SSS_B, H1, H1, H1, DO_AND)
1271 RVVCALL(OPIVV2, vand_vv_h, OP_SSS_H, H2, H2, H2, DO_AND)
1272 RVVCALL(OPIVV2, vand_vv_w, OP_SSS_W, H4, H4, H4, DO_AND)
1273 RVVCALL(OPIVV2, vand_vv_d, OP_SSS_D, H8, H8, H8, DO_AND)
1274 RVVCALL(OPIVV2, vor_vv_b, OP_SSS_B, H1, H1, H1, DO_OR)
1275 RVVCALL(OPIVV2, vor_vv_h, OP_SSS_H, H2, H2, H2, DO_OR)
1276 RVVCALL(OPIVV2, vor_vv_w, OP_SSS_W, H4, H4, H4, DO_OR)
1277 RVVCALL(OPIVV2, vor_vv_d, OP_SSS_D, H8, H8, H8, DO_OR)
1278 RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR)
1279 RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR)
1280 RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR)
1281 RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR)
1282 GEN_VEXT_VV(vand_vv_b, 1, 1, clearb)
1283 GEN_VEXT_VV(vand_vv_h, 2, 2, clearh)
1284 GEN_VEXT_VV(vand_vv_w, 4, 4, clearl)
1285 GEN_VEXT_VV(vand_vv_d, 8, 8, clearq)
1286 GEN_VEXT_VV(vor_vv_b, 1, 1, clearb)
1287 GEN_VEXT_VV(vor_vv_h, 2, 2, clearh)
1288 GEN_VEXT_VV(vor_vv_w, 4, 4, clearl)
1289 GEN_VEXT_VV(vor_vv_d, 8, 8, clearq)
1290 GEN_VEXT_VV(vxor_vv_b, 1, 1, clearb)
1291 GEN_VEXT_VV(vxor_vv_h, 2, 2, clearh)
1292 GEN_VEXT_VV(vxor_vv_w, 4, 4, clearl)
1293 GEN_VEXT_VV(vxor_vv_d, 8, 8, clearq)
1294
1295 RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND)
1296 RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND)
1297 RVVCALL(OPIVX2, vand_vx_w, OP_SSS_W, H4, H4, DO_AND)
1298 RVVCALL(OPIVX2, vand_vx_d, OP_SSS_D, H8, H8, DO_AND)
1299 RVVCALL(OPIVX2, vor_vx_b, OP_SSS_B, H1, H1, DO_OR)
1300 RVVCALL(OPIVX2, vor_vx_h, OP_SSS_H, H2, H2, DO_OR)
1301 RVVCALL(OPIVX2, vor_vx_w, OP_SSS_W, H4, H4, DO_OR)
1302 RVVCALL(OPIVX2, vor_vx_d, OP_SSS_D, H8, H8, DO_OR)
1303 RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR)
1304 RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR)
1305 RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR)
1306 RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR)
1307 GEN_VEXT_VX(vand_vx_b, 1, 1, clearb)
1308 GEN_VEXT_VX(vand_vx_h, 2, 2, clearh)
1309 GEN_VEXT_VX(vand_vx_w, 4, 4, clearl)
1310 GEN_VEXT_VX(vand_vx_d, 8, 8, clearq)
1311 GEN_VEXT_VX(vor_vx_b, 1, 1, clearb)
1312 GEN_VEXT_VX(vor_vx_h, 2, 2, clearh)
1313 GEN_VEXT_VX(vor_vx_w, 4, 4, clearl)
1314 GEN_VEXT_VX(vor_vx_d, 8, 8, clearq)
1315 GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb)
1316 GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh)
1317 GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl)
1318 GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq)
1319
1320 /* Vector Single-Width Bit Shift Instructions */
1321 #define DO_SLL(N, M) (N << (M))
1322 #define DO_SRL(N, M) (N >> (M))
1323
1324 /* generate the helpers for shift instructions with two vector operators */
1325 #define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK, CLEAR_FN) \
1326 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
1327 void *vs2, CPURISCVState *env, uint32_t desc) \
1328 { \
1329 uint32_t mlen = vext_mlen(desc); \
1330 uint32_t vm = vext_vm(desc); \
1331 uint32_t vl = env->vl; \
1332 uint32_t esz = sizeof(TS1); \
1333 uint32_t vlmax = vext_maxsz(desc) / esz; \
1334 uint32_t i; \
1335 \
1336 for (i = 0; i < vl; i++) { \
1337 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1338 continue; \
1339 } \
1340 TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
1341 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
1342 *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
1343 } \
1344 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1345 }
1346
1347 GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb)
1348 GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf, clearh)
1349 GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f, clearl)
1350 GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f, clearq)
1351
1352 GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
1353 GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
1354 GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
1355 GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
1356
1357 GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
1358 GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
1359 GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
1360 GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
1361
1362 /* generate the helpers for shift instructions with one vector and one scalar */
1363 #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK, CLEAR_FN) \
1364 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
1365 void *vs2, CPURISCVState *env, uint32_t desc) \
1366 { \
1367 uint32_t mlen = vext_mlen(desc); \
1368 uint32_t vm = vext_vm(desc); \
1369 uint32_t vl = env->vl; \
1370 uint32_t esz = sizeof(TD); \
1371 uint32_t vlmax = vext_maxsz(desc) / esz; \
1372 uint32_t i; \
1373 \
1374 for (i = 0; i < vl; i++) { \
1375 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1376 continue; \
1377 } \
1378 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
1379 *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
1380 } \
1381 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
1382 }
1383
1384 GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb)
1385 GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf, clearh)
1386 GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f, clearl)
1387 GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f, clearq)
1388
1389 GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
1390 GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
1391 GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
1392 GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
1393
1394 GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
1395 GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
1396 GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
1397 GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
1398
1399 /* Vector Narrowing Integer Right Shift Instructions */
1400 GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
1401 GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
1402 GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
1403 GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
1404 GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
1405 GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
1406 GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
1407 GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
1408 GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
1409 GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
1410 GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
1411 GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
1412
1413 /* Vector Integer Comparison Instructions */
1414 #define DO_MSEQ(N, M) (N == M)
1415 #define DO_MSNE(N, M) (N != M)
1416 #define DO_MSLT(N, M) (N < M)
1417 #define DO_MSLE(N, M) (N <= M)
1418 #define DO_MSGT(N, M) (N > M)
1419
1420 #define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \
1421 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
1422 CPURISCVState *env, uint32_t desc) \
1423 { \
1424 uint32_t mlen = vext_mlen(desc); \
1425 uint32_t vm = vext_vm(desc); \
1426 uint32_t vl = env->vl; \
1427 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1428 uint32_t i; \
1429 \
1430 for (i = 0; i < vl; i++) { \
1431 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
1432 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1433 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1434 continue; \
1435 } \
1436 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \
1437 } \
1438 for (; i < vlmax; i++) { \
1439 vext_set_elem_mask(vd, mlen, i, 0); \
1440 } \
1441 }
1442
1443 GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
1444 GEN_VEXT_CMP_VV(vmseq_vv_h, uint16_t, H2, DO_MSEQ)
1445 GEN_VEXT_CMP_VV(vmseq_vv_w, uint32_t, H4, DO_MSEQ)
1446 GEN_VEXT_CMP_VV(vmseq_vv_d, uint64_t, H8, DO_MSEQ)
1447
1448 GEN_VEXT_CMP_VV(vmsne_vv_b, uint8_t, H1, DO_MSNE)
1449 GEN_VEXT_CMP_VV(vmsne_vv_h, uint16_t, H2, DO_MSNE)
1450 GEN_VEXT_CMP_VV(vmsne_vv_w, uint32_t, H4, DO_MSNE)
1451 GEN_VEXT_CMP_VV(vmsne_vv_d, uint64_t, H8, DO_MSNE)
1452
1453 GEN_VEXT_CMP_VV(vmsltu_vv_b, uint8_t, H1, DO_MSLT)
1454 GEN_VEXT_CMP_VV(vmsltu_vv_h, uint16_t, H2, DO_MSLT)
1455 GEN_VEXT_CMP_VV(vmsltu_vv_w, uint32_t, H4, DO_MSLT)
1456 GEN_VEXT_CMP_VV(vmsltu_vv_d, uint64_t, H8, DO_MSLT)
1457
1458 GEN_VEXT_CMP_VV(vmslt_vv_b, int8_t, H1, DO_MSLT)
1459 GEN_VEXT_CMP_VV(vmslt_vv_h, int16_t, H2, DO_MSLT)
1460 GEN_VEXT_CMP_VV(vmslt_vv_w, int32_t, H4, DO_MSLT)
1461 GEN_VEXT_CMP_VV(vmslt_vv_d, int64_t, H8, DO_MSLT)
1462
1463 GEN_VEXT_CMP_VV(vmsleu_vv_b, uint8_t, H1, DO_MSLE)
1464 GEN_VEXT_CMP_VV(vmsleu_vv_h, uint16_t, H2, DO_MSLE)
1465 GEN_VEXT_CMP_VV(vmsleu_vv_w, uint32_t, H4, DO_MSLE)
1466 GEN_VEXT_CMP_VV(vmsleu_vv_d, uint64_t, H8, DO_MSLE)
1467
1468 GEN_VEXT_CMP_VV(vmsle_vv_b, int8_t, H1, DO_MSLE)
1469 GEN_VEXT_CMP_VV(vmsle_vv_h, int16_t, H2, DO_MSLE)
1470 GEN_VEXT_CMP_VV(vmsle_vv_w, int32_t, H4, DO_MSLE)
1471 GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE)
1472
1473 #define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \
1474 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
1475 CPURISCVState *env, uint32_t desc) \
1476 { \
1477 uint32_t mlen = vext_mlen(desc); \
1478 uint32_t vm = vext_vm(desc); \
1479 uint32_t vl = env->vl; \
1480 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
1481 uint32_t i; \
1482 \
1483 for (i = 0; i < vl; i++) { \
1484 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
1485 if (!vm && !vext_elem_mask(v0, mlen, i)) { \
1486 continue; \
1487 } \
1488 vext_set_elem_mask(vd, mlen, i, \
1489 DO_OP(s2, (ETYPE)(target_long)s1)); \
1490 } \
1491 for (; i < vlmax; i++) { \
1492 vext_set_elem_mask(vd, mlen, i, 0); \
1493 } \
1494 }
1495
1496 GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
1497 GEN_VEXT_CMP_VX(vmseq_vx_h, uint16_t, H2, DO_MSEQ)
1498 GEN_VEXT_CMP_VX(vmseq_vx_w, uint32_t, H4, DO_MSEQ)
1499 GEN_VEXT_CMP_VX(vmseq_vx_d, uint64_t, H8, DO_MSEQ)
1500
1501 GEN_VEXT_CMP_VX(vmsne_vx_b, uint8_t, H1, DO_MSNE)
1502 GEN_VEXT_CMP_VX(vmsne_vx_h, uint16_t, H2, DO_MSNE)
1503 GEN_VEXT_CMP_VX(vmsne_vx_w, uint32_t, H4, DO_MSNE)
1504 GEN_VEXT_CMP_VX(vmsne_vx_d, uint64_t, H8, DO_MSNE)
1505
1506 GEN_VEXT_CMP_VX(vmsltu_vx_b, uint8_t, H1, DO_MSLT)
1507 GEN_VEXT_CMP_VX(vmsltu_vx_h, uint16_t, H2, DO_MSLT)
1508 GEN_VEXT_CMP_VX(vmsltu_vx_w, uint32_t, H4, DO_MSLT)
1509 GEN_VEXT_CMP_VX(vmsltu_vx_d, uint64_t, H8, DO_MSLT)
1510
1511 GEN_VEXT_CMP_VX(vmslt_vx_b, int8_t, H1, DO_MSLT)
1512 GEN_VEXT_CMP_VX(vmslt_vx_h, int16_t, H2, DO_MSLT)
1513 GEN_VEXT_CMP_VX(vmslt_vx_w, int32_t, H4, DO_MSLT)
1514 GEN_VEXT_CMP_VX(vmslt_vx_d, int64_t, H8, DO_MSLT)
1515
1516 GEN_VEXT_CMP_VX(vmsleu_vx_b, uint8_t, H1, DO_MSLE)
1517 GEN_VEXT_CMP_VX(vmsleu_vx_h, uint16_t, H2, DO_MSLE)
1518 GEN_VEXT_CMP_VX(vmsleu_vx_w, uint32_t, H4, DO_MSLE)
1519 GEN_VEXT_CMP_VX(vmsleu_vx_d, uint64_t, H8, DO_MSLE)
1520
1521 GEN_VEXT_CMP_VX(vmsle_vx_b, int8_t, H1, DO_MSLE)
1522 GEN_VEXT_CMP_VX(vmsle_vx_h, int16_t, H2, DO_MSLE)
1523 GEN_VEXT_CMP_VX(vmsle_vx_w, int32_t, H4, DO_MSLE)
1524 GEN_VEXT_CMP_VX(vmsle_vx_d, int64_t, H8, DO_MSLE)
1525
1526 GEN_VEXT_CMP_VX(vmsgtu_vx_b, uint8_t, H1, DO_MSGT)
1527 GEN_VEXT_CMP_VX(vmsgtu_vx_h, uint16_t, H2, DO_MSGT)
1528 GEN_VEXT_CMP_VX(vmsgtu_vx_w, uint32_t, H4, DO_MSGT)
1529 GEN_VEXT_CMP_VX(vmsgtu_vx_d, uint64_t, H8, DO_MSGT)
1530
1531 GEN_VEXT_CMP_VX(vmsgt_vx_b, int8_t, H1, DO_MSGT)
1532 GEN_VEXT_CMP_VX(vmsgt_vx_h, int16_t, H2, DO_MSGT)
1533 GEN_VEXT_CMP_VX(vmsgt_vx_w, int32_t, H4, DO_MSGT)
1534 GEN_VEXT_CMP_VX(vmsgt_vx_d, int64_t, H8, DO_MSGT)
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