target/riscv/xthead.decode

   1 #
   2 # Translation routines for the instructions of the XThead* ISA extensions
   3 #
   4 # Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
   5 #                    Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
   6 #
   7 # SPDX-License-Identifier: LGPL-2.1-or-later
   8 #
   9 # The documentation of the ISA extensions can be found here:
  10 #   https://github.com/T-head-Semi/thead-extension-spec/releases/latest
  11
  12 # Fields:
  13 %rd        7:5
  14 %rd1       7:5
  15 %rs        15:5
  16 %rs1       15:5
  17 %rd2       20:5
  18 %rs2       20:5
  19 %sh5       20:5
  20 %imm5      20:s5
  21 %sh6       20:6
  22 %sh2       25:2
  23 %imm2      25:2
  24
  25 # Argument sets
  26 &r         rd rs1 rs2                               !extern
  27 &r2        rd rs1                                   !extern
  28 &shift     shamt rs1 rd                             !extern
  29 &th_bfext  msb lsb rs1 rd
  30 &th_pair   rd1 rs rd2 sh2
  31 &th_memidx rd rs1 rs2 imm2
  32 &th_meminc rd rs1 imm5 imm2
  33
  34 # Formats
  35 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
  36 @rs2_s      ....... ..... ..... ... ..... .......   %rs2 %rs1
  37 @r          ....... ..... .....  ... ..... .......  &r %rs2 %rs1 %rd
  38 @r2         ....... ..... .....  ... ..... .......  &r2 %rs1 %rd
  39 @th_bfext   msb:6  lsb:6  .....  ... ..... .......  &th_bfext %rs1 %rd
  40 @sh5        ....... ..... .....  ... ..... .......  &shift  shamt=%sh5      %rs1 %rd
  41 @sh6        ...... ...... .....  ... ..... .......  &shift shamt=%sh6 %rs1 %rd
  42 @th_pair    ..... .. ..... ..... ... ..... .......  &th_pair %rd1 %rs %rd2 %sh2
  43 @th_memidx  ..... .. ..... ..... ... ..... .......  &th_memidx %rd %rs1 %rs2 %imm2
  44 @th_meminc  ..... .. ..... ..... ... ..... .......  &th_meminc %rd %rs1 %imm5 %imm2
  45
  46 # XTheadBa
  47 # Instead of defining a new encoding, we simply use the decoder to
  48 # extract the imm[0:1] field and dispatch to separate translation
  49 # functions (mirroring the `sh[123]add` instructions from Zba and
  50 # the regular RVI `add` instruction.
  51 #
  52 # The only difference between sh[123]add and addsl is that the shift
  53 # is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
  54 #
  55 # Note that shift-by-0 is a valid operation according to the manual.
  56 # This will be equivalent to a regular add.
  57 add              0000000 ..... ..... 001 ..... 0001011 @r
  58 th_addsl1        0000001 ..... ..... 001 ..... 0001011 @r
  59 th_addsl2        0000010 ..... ..... 001 ..... 0001011 @r
  60 th_addsl3        0000011 ..... ..... 001 ..... 0001011 @r
  61
  62 # XTheadBb
  63 th_ext           ...... ...... ..... 010 ..... 0001011 @th_bfext
  64 th_extu          ...... ...... ..... 011 ..... 0001011 @th_bfext
  65 th_ff0           1000010 00000 ..... 001 ..... 0001011 @r2
  66 th_ff1           1000011 00000 ..... 001 ..... 0001011 @r2
  67 th_srri          000100 ...... ..... 001 ..... 0001011 @sh6
  68 th_srriw         0001010 ..... ..... 001 ..... 0001011 @sh5
  69 th_rev           1000001 00000 ..... 001 ..... 0001011 @r2
  70 th_revw          1001000 00000 ..... 001 ..... 0001011 @r2
  71 th_tstnbz        1000000 00000 ..... 001 ..... 0001011 @r2
  72
  73 # XTheadBs
  74 th_tst           100010 ...... ..... 001 ..... 0001011 @sh6
  75
  76 # XTheadCmo
  77 th_dcache_call   0000000 00001 00000 000 00000 0001011
  78 th_dcache_ciall  0000000 00011 00000 000 00000 0001011
  79 th_dcache_iall   0000000 00010 00000 000 00000 0001011
  80 th_dcache_cpa    0000001 01001 ..... 000 00000 0001011 @sfence_vm
  81 th_dcache_cipa   0000001 01011 ..... 000 00000 0001011 @sfence_vm
  82 th_dcache_ipa    0000001 01010 ..... 000 00000 0001011 @sfence_vm
  83 th_dcache_cva    0000001 00101 ..... 000 00000 0001011 @sfence_vm
  84 th_dcache_civa   0000001 00111 ..... 000 00000 0001011 @sfence_vm
  85 th_dcache_iva    0000001 00110 ..... 000 00000 0001011 @sfence_vm
  86 th_dcache_csw    0000001 00001 ..... 000 00000 0001011 @sfence_vm
  87 th_dcache_cisw   0000001 00011 ..... 000 00000 0001011 @sfence_vm
  88 th_dcache_isw    0000001 00010 ..... 000 00000 0001011 @sfence_vm
  89 th_dcache_cpal1  0000001 01000 ..... 000 00000 0001011 @sfence_vm
  90 th_dcache_cval1  0000001 00100 ..... 000 00000 0001011 @sfence_vm
  91 th_icache_iall   0000000 10000 00000 000 00000 0001011
  92 th_icache_ialls  0000000 10001 00000 000 00000 0001011
  93 th_icache_ipa    0000001 11000 ..... 000 00000 0001011 @sfence_vm
  94 th_icache_iva    0000001 10000 ..... 000 00000 0001011 @sfence_vm
  95 th_l2cache_call  0000000 10101 00000 000 00000 0001011
  96 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
  97 th_l2cache_iall  0000000 10110 00000 000 00000 0001011
  98
  99 # XTheadCondMov
 100 th_mveqz         0100000 ..... .....  001 ..... 0001011 @r
 101 th_mvnez         0100001 ..... .....  001 ..... 0001011 @r
 102
 103 # XTheadFMemIdx
 104 th_flrd          01100 .. ..... ..... 110 ..... 0001011 @th_memidx
 105 th_flrw          01000 .. ..... ..... 110 ..... 0001011 @th_memidx
 106 th_flurd         01110 .. ..... ..... 110 ..... 0001011 @th_memidx
 107 th_flurw         01010 .. ..... ..... 110 ..... 0001011 @th_memidx
 108 th_fsrd          01100 .. ..... ..... 111 ..... 0001011 @th_memidx
 109 th_fsrw          01000 .. ..... ..... 111 ..... 0001011 @th_memidx
 110 th_fsurd         01110 .. ..... ..... 111 ..... 0001011 @th_memidx
 111 th_fsurw         01010 .. ..... ..... 111 ..... 0001011 @th_memidx
 112
 113 # XTheadFmv
 114 th_fmv_hw_x      1010000  00000 ..... 001 ..... 0001011 @r2
 115 th_fmv_x_hw      1100000  00000 ..... 001 ..... 0001011 @r2
 116
 117 # XTheadMac
 118 th_mula          00100 00 ..... ..... 001 ..... 0001011 @r
 119 th_mulah         00101 00 ..... ..... 001 ..... 0001011 @r
 120 th_mulaw         00100 10 ..... ..... 001 ..... 0001011 @r
 121 th_muls          00100 01 ..... ..... 001 ..... 0001011 @r
 122 th_mulsh         00101 01 ..... ..... 001 ..... 0001011 @r
 123 th_mulsw         00100 11 ..... ..... 001 ..... 0001011 @r
 124
 125 # XTheadMemIdx
 126 th_ldia          01111 .. ..... ..... 100 ..... 0001011 @th_meminc
 127 th_ldib          01101 .. ..... ..... 100 ..... 0001011 @th_meminc
 128 th_lwia          01011 .. ..... ..... 100 ..... 0001011 @th_meminc
 129 th_lwib          01001 .. ..... ..... 100 ..... 0001011 @th_meminc
 130 th_lwuia         11011 .. ..... ..... 100 ..... 0001011 @th_meminc
 131 th_lwuib         11001 .. ..... ..... 100 ..... 0001011 @th_meminc
 132 th_lhia          00111 .. ..... ..... 100 ..... 0001011 @th_meminc
 133 th_lhib          00101 .. ..... ..... 100 ..... 0001011 @th_meminc
 134 th_lhuia         10111 .. ..... ..... 100 ..... 0001011 @th_meminc
 135 th_lhuib         10101 .. ..... ..... 100 ..... 0001011 @th_meminc
 136 th_lbia          00011 .. ..... ..... 100 ..... 0001011 @th_meminc
 137 th_lbib          00001 .. ..... ..... 100 ..... 0001011 @th_meminc
 138 th_lbuia         10011 .. ..... ..... 100 ..... 0001011 @th_meminc
 139 th_lbuib         10001 .. ..... ..... 100 ..... 0001011 @th_meminc
 140 th_sdia          01111 .. ..... ..... 101 ..... 0001011 @th_meminc
 141 th_sdib          01101 .. ..... ..... 101 ..... 0001011 @th_meminc
 142 th_swia          01011 .. ..... ..... 101 ..... 0001011 @th_meminc
 143 th_swib          01001 .. ..... ..... 101 ..... 0001011 @th_meminc
 144 th_shia          00111 .. ..... ..... 101 ..... 0001011 @th_meminc
 145 th_shib          00101 .. ..... ..... 101 ..... 0001011 @th_meminc
 146 th_sbia          00011 .. ..... ..... 101 ..... 0001011 @th_meminc
 147 th_sbib          00001 .. ..... ..... 101 ..... 0001011 @th_meminc
 148
 149 th_lrd           01100 .. ..... ..... 100 ..... 0001011 @th_memidx
 150 th_lrw           01000 .. ..... ..... 100 ..... 0001011 @th_memidx
 151 th_lrwu          11000 .. ..... ..... 100 ..... 0001011 @th_memidx
 152 th_lrh           00100 .. ..... ..... 100 ..... 0001011 @th_memidx
 153 th_lrhu          10100 .. ..... ..... 100 ..... 0001011 @th_memidx
 154 th_lrb           00000 .. ..... ..... 100 ..... 0001011 @th_memidx
 155 th_lrbu          10000 .. ..... ..... 100 ..... 0001011 @th_memidx
 156 th_srd           01100 .. ..... ..... 101 ..... 0001011 @th_memidx
 157 th_srw           01000 .. ..... ..... 101 ..... 0001011 @th_memidx
 158 th_srh           00100 .. ..... ..... 101 ..... 0001011 @th_memidx
 159 th_srb           00000 .. ..... ..... 101 ..... 0001011 @th_memidx
 160
 161 th_lurd          01110 .. ..... ..... 100 ..... 0001011 @th_memidx
 162 th_lurw          01010 .. ..... ..... 100 ..... 0001011 @th_memidx
 163 th_lurwu         11010 .. ..... ..... 100 ..... 0001011 @th_memidx
 164 th_lurh          00110 .. ..... ..... 100 ..... 0001011 @th_memidx
 165 th_lurhu         10110 .. ..... ..... 100 ..... 0001011 @th_memidx
 166 th_lurb          00010 .. ..... ..... 100 ..... 0001011 @th_memidx
 167 th_lurbu         10010 .. ..... ..... 100 ..... 0001011 @th_memidx
 168 th_surd          01110 .. ..... ..... 101 ..... 0001011 @th_memidx
 169 th_surw          01010 .. ..... ..... 101 ..... 0001011 @th_memidx
 170 th_surh          00110 .. ..... ..... 101 ..... 0001011 @th_memidx
 171 th_surb          00010 .. ..... ..... 101 ..... 0001011 @th_memidx
 172
 173 # XTheadMemPair
 174 th_ldd           11111 .. ..... ..... 100 ..... 0001011 @th_pair
 175 th_lwd           11100 .. ..... ..... 100 ..... 0001011 @th_pair
 176 th_lwud          11110 .. ..... ..... 100 ..... 0001011 @th_pair
 177 th_sdd           11111 .. ..... ..... 101 ..... 0001011 @th_pair
 178 th_swd           11100 .. ..... ..... 101 ..... 0001011 @th_pair
 179
 180 # XTheadSync
 181 th_sfence_vmas   0000010 ..... ..... 000 00000 0001011 @rs2_s
 182 th_sync          0000000 11000 00000 000 00000 0001011
 183 th_sync_i        0000000 11010 00000 000 00000 0001011
 184 th_sync_is       0000000 11011 00000 000 00000 0001011
 185 th_sync_s        0000000 11001 00000 000 00000 0001011