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target/rx: Put tb_flags into DisasContext
[mirror_qemu.git] / target / rx / translate.c
1 /*
2 * RX translation
3 *
4 * Copyright (c) 2019 Yoshinori Sato
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "qemu/bswap.h"
21 #include "qemu/qemu-print.h"
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "tcg/tcg-op.h"
25 #include "exec/cpu_ldst.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28 #include "exec/translator.h"
29 #include "exec/log.h"
30
31 typedef struct DisasContext {
32 DisasContextBase base;
33 CPURXState *env;
34 uint32_t pc;
35 uint32_t tb_flags;
36 } DisasContext;
37
38 typedef struct DisasCompare {
39 TCGv value;
40 TCGv temp;
41 TCGCond cond;
42 } DisasCompare;
43
44 const char *rx_crname(uint8_t cr)
45 {
46 static const char *cr_names[] = {
47 "psw", "pc", "usp", "fpsw", "", "", "", "",
48 "bpsw", "bpc", "isp", "fintv", "intb", "", "", ""
49 };
50 if (cr >= ARRAY_SIZE(cr_names)) {
51 return "illegal";
52 }
53 return cr_names[cr];
54 }
55
56 /* Target-specific values for dc->base.is_jmp. */
57 #define DISAS_JUMP DISAS_TARGET_0
58 #define DISAS_UPDATE DISAS_TARGET_1
59 #define DISAS_EXIT DISAS_TARGET_2
60
61 /* global register indexes */
62 static TCGv cpu_regs[16];
63 static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c;
64 static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl;
65 static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp;
66 static TCGv cpu_fintv, cpu_intb, cpu_pc;
67 static TCGv_i64 cpu_acc;
68
69 #define cpu_sp cpu_regs[0]
70
71 #include "exec/gen-icount.h"
72
73 /* decoder helper */
74 static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn,
75 int i, int n)
76 {
77 while (++i <= n) {
78 uint8_t b = cpu_ldub_code(ctx->env, ctx->base.pc_next++);
79 insn |= b << (32 - i * 8);
80 }
81 return insn;
82 }
83
84 static uint32_t li(DisasContext *ctx, int sz)
85 {
86 int32_t tmp, addr;
87 CPURXState *env = ctx->env;
88 addr = ctx->base.pc_next;
89
90 tcg_debug_assert(sz < 4);
91 switch (sz) {
92 case 1:
93 ctx->base.pc_next += 1;
94 return cpu_ldsb_code(env, addr);
95 case 2:
96 ctx->base.pc_next += 2;
97 return cpu_ldsw_code(env, addr);
98 case 3:
99 ctx->base.pc_next += 3;
100 tmp = cpu_ldsb_code(env, addr + 2) << 16;
101 tmp |= cpu_lduw_code(env, addr) & 0xffff;
102 return tmp;
103 case 0:
104 ctx->base.pc_next += 4;
105 return cpu_ldl_code(env, addr);
106 }
107 return 0;
108 }
109
110 static int bdsp_s(DisasContext *ctx, int d)
111 {
112 /*
113 * 0 -> 8
114 * 1 -> 9
115 * 2 -> 10
116 * 3 -> 3
117 * :
118 * 7 -> 7
119 */
120 if (d < 3) {
121 d += 8;
122 }
123 return d;
124 }
125
126 /* Include the auto-generated decoder. */
127 #include "decode-insns.c.inc"
128
129 void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
130 {
131 RXCPU *cpu = RX_CPU(cs);
132 CPURXState *env = &cpu->env;
133 int i;
134 uint32_t psw;
135
136 psw = rx_cpu_pack_psw(env);
137 qemu_fprintf(f, "pc=0x%08x psw=0x%08x\n",
138 env->pc, psw);
139 for (i = 0; i < 16; i += 4) {
140 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
141 i, env->regs[i], i + 1, env->regs[i + 1],
142 i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]);
143 }
144 }
145
146 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
147 {
148 if (translator_use_goto_tb(&dc->base, dest)) {
149 tcg_gen_goto_tb(n);
150 tcg_gen_movi_i32(cpu_pc, dest);
151 tcg_gen_exit_tb(dc->base.tb, n);
152 } else {
153 tcg_gen_movi_i32(cpu_pc, dest);
154 tcg_gen_lookup_and_goto_ptr();
155 }
156 dc->base.is_jmp = DISAS_NORETURN;
157 }
158
159 /* generic load wrapper */
160 static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem)
161 {
162 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE);
163 }
164
165 /* unsigned load wrapper */
166 static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem)
167 {
168 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE);
169 }
170
171 /* generic store wrapper */
172 static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem)
173 {
174 tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE);
175 }
176
177 /* [ri, rb] */
178 static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem,
179 int size, int ri, int rb)
180 {
181 tcg_gen_shli_i32(mem, cpu_regs[ri], size);
182 tcg_gen_add_i32(mem, mem, cpu_regs[rb]);
183 }
184
185 /* dsp[reg] */
186 static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem,
187 int ld, int size, int reg)
188 {
189 uint32_t dsp;
190
191 tcg_debug_assert(ld < 3);
192 switch (ld) {
193 case 0:
194 return cpu_regs[reg];
195 case 1:
196 dsp = cpu_ldub_code(ctx->env, ctx->base.pc_next) << size;
197 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp);
198 ctx->base.pc_next += 1;
199 return mem;
200 case 2:
201 dsp = cpu_lduw_code(ctx->env, ctx->base.pc_next) << size;
202 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp);
203 ctx->base.pc_next += 2;
204 return mem;
205 }
206 return NULL;
207 }
208
209 static inline MemOp mi_to_mop(unsigned mi)
210 {
211 static const MemOp mop[5] = { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB };
212 tcg_debug_assert(mi < 5);
213 return mop[mi];
214 }
215
216 /* load source operand */
217 static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem,
218 int ld, int mi, int rs)
219 {
220 TCGv addr;
221 MemOp mop;
222 if (ld < 3) {
223 mop = mi_to_mop(mi);
224 addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs);
225 tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE);
226 return mem;
227 } else {
228 return cpu_regs[rs];
229 }
230 }
231
232 /* Processor mode check */
233 static int is_privileged(DisasContext *ctx, int is_exception)
234 {
235 if (FIELD_EX32(ctx->tb_flags, PSW, PM)) {
236 if (is_exception) {
237 gen_helper_raise_privilege_violation(cpu_env);
238 }
239 return 0;
240 } else {
241 return 1;
242 }
243 }
244
245 /* generate QEMU condition */
246 static void psw_cond(DisasCompare *dc, uint32_t cond)
247 {
248 tcg_debug_assert(cond < 16);
249 switch (cond) {
250 case 0: /* z */
251 dc->cond = TCG_COND_EQ;
252 dc->value = cpu_psw_z;
253 break;
254 case 1: /* nz */
255 dc->cond = TCG_COND_NE;
256 dc->value = cpu_psw_z;
257 break;
258 case 2: /* c */
259 dc->cond = TCG_COND_NE;
260 dc->value = cpu_psw_c;
261 break;
262 case 3: /* nc */
263 dc->cond = TCG_COND_EQ;
264 dc->value = cpu_psw_c;
265 break;
266 case 4: /* gtu (C& ~Z) == 1 */
267 case 5: /* leu (C& ~Z) == 0 */
268 tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0);
269 tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c);
270 dc->cond = (cond == 4) ? TCG_COND_NE : TCG_COND_EQ;
271 dc->value = dc->temp;
272 break;
273 case 6: /* pz (S == 0) */
274 dc->cond = TCG_COND_GE;
275 dc->value = cpu_psw_s;
276 break;
277 case 7: /* n (S == 1) */
278 dc->cond = TCG_COND_LT;
279 dc->value = cpu_psw_s;
280 break;
281 case 8: /* ge (S^O)==0 */
282 case 9: /* lt (S^O)==1 */
283 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s);
284 dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT;
285 dc->value = dc->temp;
286 break;
287 case 10: /* gt ((S^O)|Z)==0 */
288 case 11: /* le ((S^O)|Z)==1 */
289 tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s);
290 tcg_gen_sari_i32(dc->temp, dc->temp, 31);
291 tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp);
292 dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ;
293 dc->value = dc->temp;
294 break;
295 case 12: /* o */
296 dc->cond = TCG_COND_LT;
297 dc->value = cpu_psw_o;
298 break;
299 case 13: /* no */
300 dc->cond = TCG_COND_GE;
301 dc->value = cpu_psw_o;
302 break;
303 case 14: /* always true */
304 dc->cond = TCG_COND_ALWAYS;
305 dc->value = dc->temp;
306 break;
307 case 15: /* always false */
308 dc->cond = TCG_COND_NEVER;
309 dc->value = dc->temp;
310 break;
311 }
312 }
313
314 static void move_from_cr(TCGv ret, int cr, uint32_t pc)
315 {
316 TCGv z = tcg_const_i32(0);
317 switch (cr) {
318 case 0: /* PSW */
319 gen_helper_pack_psw(ret, cpu_env);
320 break;
321 case 1: /* PC */
322 tcg_gen_movi_i32(ret, pc);
323 break;
324 case 2: /* USP */
325 tcg_gen_movcond_i32(TCG_COND_NE, ret,
326 cpu_psw_u, z, cpu_sp, cpu_usp);
327 break;
328 case 3: /* FPSW */
329 tcg_gen_mov_i32(ret, cpu_fpsw);
330 break;
331 case 8: /* BPSW */
332 tcg_gen_mov_i32(ret, cpu_bpsw);
333 break;
334 case 9: /* BPC */
335 tcg_gen_mov_i32(ret, cpu_bpc);
336 break;
337 case 10: /* ISP */
338 tcg_gen_movcond_i32(TCG_COND_EQ, ret,
339 cpu_psw_u, z, cpu_sp, cpu_isp);
340 break;
341 case 11: /* FINTV */
342 tcg_gen_mov_i32(ret, cpu_fintv);
343 break;
344 case 12: /* INTB */
345 tcg_gen_mov_i32(ret, cpu_intb);
346 break;
347 default:
348 qemu_log_mask(LOG_GUEST_ERROR, "Unimplement control register %d", cr);
349 /* Unimplement registers return 0 */
350 tcg_gen_movi_i32(ret, 0);
351 break;
352 }
353 tcg_temp_free(z);
354 }
355
356 static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
357 {
358 TCGv z;
359 if (cr >= 8 && !is_privileged(ctx, 0)) {
360 /* Some control registers can only be written in privileged mode. */
361 qemu_log_mask(LOG_GUEST_ERROR,
362 "disallow control register write %s", rx_crname(cr));
363 return;
364 }
365 z = tcg_const_i32(0);
366 switch (cr) {
367 case 0: /* PSW */
368 gen_helper_set_psw(cpu_env, val);
369 break;
370 /* case 1: to PC not supported */
371 case 2: /* USP */
372 tcg_gen_mov_i32(cpu_usp, val);
373 tcg_gen_movcond_i32(TCG_COND_NE, cpu_sp,
374 cpu_psw_u, z, cpu_usp, cpu_sp);
375 break;
376 case 3: /* FPSW */
377 gen_helper_set_fpsw(cpu_env, val);
378 break;
379 case 8: /* BPSW */
380 tcg_gen_mov_i32(cpu_bpsw, val);
381 break;
382 case 9: /* BPC */
383 tcg_gen_mov_i32(cpu_bpc, val);
384 break;
385 case 10: /* ISP */
386 tcg_gen_mov_i32(cpu_isp, val);
387 /* if PSW.U is 0, copy isp to r0 */
388 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_sp,
389 cpu_psw_u, z, cpu_isp, cpu_sp);
390 break;
391 case 11: /* FINTV */
392 tcg_gen_mov_i32(cpu_fintv, val);
393 break;
394 case 12: /* INTB */
395 tcg_gen_mov_i32(cpu_intb, val);
396 break;
397 default:
398 qemu_log_mask(LOG_GUEST_ERROR,
399 "Unimplement control register %d", cr);
400 break;
401 }
402 tcg_temp_free(z);
403 }
404
405 static void push(TCGv val)
406 {
407 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
408 rx_gen_st(MO_32, val, cpu_sp);
409 }
410
411 static void pop(TCGv ret)
412 {
413 rx_gen_ld(MO_32, ret, cpu_sp);
414 tcg_gen_addi_i32(cpu_sp, cpu_sp, 4);
415 }
416
417 /* mov.<bwl> rs,dsp5[rd] */
418 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a)
419 {
420 TCGv mem;
421 mem = tcg_temp_new();
422 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
423 rx_gen_st(a->sz, cpu_regs[a->rs], mem);
424 tcg_temp_free(mem);
425 return true;
426 }
427
428 /* mov.<bwl> dsp5[rs],rd */
429 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a)
430 {
431 TCGv mem;
432 mem = tcg_temp_new();
433 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz);
434 rx_gen_ld(a->sz, cpu_regs[a->rd], mem);
435 tcg_temp_free(mem);
436 return true;
437 }
438
439 /* mov.l #uimm4,rd */
440 /* mov.l #uimm8,rd */
441 /* mov.l #imm,rd */
442 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a)
443 {
444 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm);
445 return true;
446 }
447
448 /* mov.<bwl> #uimm8,dsp[rd] */
449 /* mov.<bwl> #imm, dsp[rd] */
450 static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a)
451 {
452 TCGv imm, mem;
453 imm = tcg_const_i32(a->imm);
454 mem = tcg_temp_new();
455 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
456 rx_gen_st(a->sz, imm, mem);
457 tcg_temp_free(imm);
458 tcg_temp_free(mem);
459 return true;
460 }
461
462 /* mov.<bwl> [ri,rb],rd */
463 static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a)
464 {
465 TCGv mem;
466 mem = tcg_temp_new();
467 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb);
468 rx_gen_ld(a->sz, cpu_regs[a->rd], mem);
469 tcg_temp_free(mem);
470 return true;
471 }
472
473 /* mov.<bwl> rd,[ri,rb] */
474 static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a)
475 {
476 TCGv mem;
477 mem = tcg_temp_new();
478 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb);
479 rx_gen_st(a->sz, cpu_regs[a->rs], mem);
480 tcg_temp_free(mem);
481 return true;
482 }
483
484 /* mov.<bwl> dsp[rs],dsp[rd] */
485 /* mov.<bwl> rs,dsp[rd] */
486 /* mov.<bwl> dsp[rs],rd */
487 /* mov.<bwl> rs,rd */
488 static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
489 {
490 static void (* const mov[])(TCGv ret, TCGv arg) = {
491 tcg_gen_ext8s_i32, tcg_gen_ext16s_i32, tcg_gen_mov_i32,
492 };
493 TCGv tmp, mem, addr;
494 if (a->lds == 3 && a->ldd == 3) {
495 /* mov.<bwl> rs,rd */
496 mov[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]);
497 return true;
498 }
499
500 mem = tcg_temp_new();
501 if (a->lds == 3) {
502 /* mov.<bwl> rs,dsp[rd] */
503 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs);
504 rx_gen_st(a->sz, cpu_regs[a->rd], addr);
505 } else if (a->ldd == 3) {
506 /* mov.<bwl> dsp[rs],rd */
507 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs);
508 rx_gen_ld(a->sz, cpu_regs[a->rd], addr);
509 } else {
510 /* mov.<bwl> dsp[rs],dsp[rd] */
511 tmp = tcg_temp_new();
512 addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs);
513 rx_gen_ld(a->sz, tmp, addr);
514 addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd);
515 rx_gen_st(a->sz, tmp, addr);
516 tcg_temp_free(tmp);
517 }
518 tcg_temp_free(mem);
519 return true;
520 }
521
522 /* mov.<bwl> rs,[rd+] */
523 /* mov.<bwl> rs,[-rd] */
524 static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a)
525 {
526 TCGv val;
527 val = tcg_temp_new();
528 tcg_gen_mov_i32(val, cpu_regs[a->rs]);
529 if (a->ad == 1) {
530 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
531 }
532 rx_gen_st(a->sz, val, cpu_regs[a->rd]);
533 if (a->ad == 0) {
534 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
535 }
536 tcg_temp_free(val);
537 return true;
538 }
539
540 /* mov.<bwl> [rd+],rs */
541 /* mov.<bwl> [-rd],rs */
542 static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a)
543 {
544 TCGv val;
545 val = tcg_temp_new();
546 if (a->ad == 1) {
547 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
548 }
549 rx_gen_ld(a->sz, val, cpu_regs[a->rd]);
550 if (a->ad == 0) {
551 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
552 }
553 tcg_gen_mov_i32(cpu_regs[a->rs], val);
554 tcg_temp_free(val);
555 return true;
556 }
557
558 /* movu.<bw> dsp5[rs],rd */
559 /* movu.<bw> dsp[rs],rd */
560 static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a)
561 {
562 TCGv mem;
563 mem = tcg_temp_new();
564 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz);
565 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem);
566 tcg_temp_free(mem);
567 return true;
568 }
569
570 /* movu.<bw> rs,rd */
571 static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a)
572 {
573 static void (* const ext[])(TCGv ret, TCGv arg) = {
574 tcg_gen_ext8u_i32, tcg_gen_ext16u_i32,
575 };
576 ext[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]);
577 return true;
578 }
579
580 /* movu.<bw> [ri,rb],rd */
581 static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a)
582 {
583 TCGv mem;
584 mem = tcg_temp_new();
585 rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb);
586 rx_gen_ldu(a->sz, cpu_regs[a->rd], mem);
587 tcg_temp_free(mem);
588 return true;
589 }
590
591 /* movu.<bw> [rd+],rs */
592 /* mov.<bw> [-rd],rs */
593 static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a)
594 {
595 TCGv val;
596 val = tcg_temp_new();
597 if (a->ad == 1) {
598 tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
599 }
600 rx_gen_ldu(a->sz, val, cpu_regs[a->rd]);
601 if (a->ad == 0) {
602 tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
603 }
604 tcg_gen_mov_i32(cpu_regs[a->rs], val);
605 tcg_temp_free(val);
606 return true;
607 }
608
609
610 /* pop rd */
611 static bool trans_POP(DisasContext *ctx, arg_POP *a)
612 {
613 /* mov.l [r0+], rd */
614 arg_MOV_rp mov_a;
615 mov_a.rd = 0;
616 mov_a.rs = a->rd;
617 mov_a.ad = 0;
618 mov_a.sz = MO_32;
619 trans_MOV_pr(ctx, &mov_a);
620 return true;
621 }
622
623 /* popc cr */
624 static bool trans_POPC(DisasContext *ctx, arg_POPC *a)
625 {
626 TCGv val;
627 val = tcg_temp_new();
628 pop(val);
629 move_to_cr(ctx, val, a->cr);
630 if (a->cr == 0 && is_privileged(ctx, 0)) {
631 /* PSW.I may be updated here. exit TB. */
632 ctx->base.is_jmp = DISAS_UPDATE;
633 }
634 tcg_temp_free(val);
635 return true;
636 }
637
638 /* popm rd-rd2 */
639 static bool trans_POPM(DisasContext *ctx, arg_POPM *a)
640 {
641 int r;
642 if (a->rd == 0 || a->rd >= a->rd2) {
643 qemu_log_mask(LOG_GUEST_ERROR,
644 "Invalid register ranges r%d-r%d", a->rd, a->rd2);
645 }
646 r = a->rd;
647 while (r <= a->rd2 && r < 16) {
648 pop(cpu_regs[r++]);
649 }
650 return true;
651 }
652
653
654 /* push.<bwl> rs */
655 static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a)
656 {
657 TCGv val;
658 val = tcg_temp_new();
659 tcg_gen_mov_i32(val, cpu_regs[a->rs]);
660 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
661 rx_gen_st(a->sz, val, cpu_sp);
662 tcg_temp_free(val);
663 return true;
664 }
665
666 /* push.<bwl> dsp[rs] */
667 static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a)
668 {
669 TCGv mem, val, addr;
670 mem = tcg_temp_new();
671 val = tcg_temp_new();
672 addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs);
673 rx_gen_ld(a->sz, val, addr);
674 tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
675 rx_gen_st(a->sz, val, cpu_sp);
676 tcg_temp_free(mem);
677 tcg_temp_free(val);
678 return true;
679 }
680
681 /* pushc rx */
682 static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a)
683 {
684 TCGv val;
685 val = tcg_temp_new();
686 move_from_cr(val, a->cr, ctx->pc);
687 push(val);
688 tcg_temp_free(val);
689 return true;
690 }
691
692 /* pushm rs-rs2 */
693 static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a)
694 {
695 int r;
696
697 if (a->rs == 0 || a->rs >= a->rs2) {
698 qemu_log_mask(LOG_GUEST_ERROR,
699 "Invalid register ranges r%d-r%d", a->rs, a->rs2);
700 }
701 r = a->rs2;
702 while (r >= a->rs && r >= 0) {
703 push(cpu_regs[r--]);
704 }
705 return true;
706 }
707
708 /* xchg rs,rd */
709 static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a)
710 {
711 TCGv tmp;
712 tmp = tcg_temp_new();
713 tcg_gen_mov_i32(tmp, cpu_regs[a->rs]);
714 tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]);
715 tcg_gen_mov_i32(cpu_regs[a->rd], tmp);
716 tcg_temp_free(tmp);
717 return true;
718 }
719
720 /* xchg dsp[rs].<mi>,rd */
721 static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a)
722 {
723 TCGv mem, addr;
724 mem = tcg_temp_new();
725 switch (a->mi) {
726 case 0: /* dsp[rs].b */
727 case 1: /* dsp[rs].w */
728 case 2: /* dsp[rs].l */
729 addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs);
730 break;
731 case 3: /* dsp[rs].uw */
732 case 4: /* dsp[rs].ub */
733 addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs);
734 break;
735 default:
736 g_assert_not_reached();
737 }
738 tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd],
739 0, mi_to_mop(a->mi));
740 tcg_temp_free(mem);
741 return true;
742 }
743
744 static inline void stcond(TCGCond cond, int rd, int imm)
745 {
746 TCGv z;
747 TCGv _imm;
748 z = tcg_const_i32(0);
749 _imm = tcg_const_i32(imm);
750 tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z,
751 _imm, cpu_regs[rd]);
752 tcg_temp_free(z);
753 tcg_temp_free(_imm);
754 }
755
756 /* stz #imm,rd */
757 static bool trans_STZ(DisasContext *ctx, arg_STZ *a)
758 {
759 stcond(TCG_COND_EQ, a->rd, a->imm);
760 return true;
761 }
762
763 /* stnz #imm,rd */
764 static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a)
765 {
766 stcond(TCG_COND_NE, a->rd, a->imm);
767 return true;
768 }
769
770 /* sccnd.<bwl> rd */
771 /* sccnd.<bwl> dsp:[rd] */
772 static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a)
773 {
774 DisasCompare dc;
775 TCGv val, mem, addr;
776 dc.temp = tcg_temp_new();
777 psw_cond(&dc, a->cd);
778 if (a->ld < 3) {
779 val = tcg_temp_new();
780 mem = tcg_temp_new();
781 tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0);
782 addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd);
783 rx_gen_st(a->sz, val, addr);
784 tcg_temp_free(val);
785 tcg_temp_free(mem);
786 } else {
787 tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0);
788 }
789 tcg_temp_free(dc.temp);
790 return true;
791 }
792
793 /* rtsd #imm */
794 static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a)
795 {
796 tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2);
797 pop(cpu_pc);
798 ctx->base.is_jmp = DISAS_JUMP;
799 return true;
800 }
801
802 /* rtsd #imm, rd-rd2 */
803 static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a)
804 {
805 int dst;
806 int adj;
807
808 if (a->rd2 >= a->rd) {
809 adj = a->imm - (a->rd2 - a->rd + 1);
810 } else {
811 adj = a->imm - (15 - a->rd + 1);
812 }
813
814 tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2);
815 dst = a->rd;
816 while (dst <= a->rd2 && dst < 16) {
817 pop(cpu_regs[dst++]);
818 }
819 pop(cpu_pc);
820 ctx->base.is_jmp = DISAS_JUMP;
821 return true;
822 }
823
824 typedef void (*op2fn)(TCGv ret, TCGv arg1);
825 typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2);
826
827 static inline void rx_gen_op_rr(op2fn opr, int dst, int src)
828 {
829 opr(cpu_regs[dst], cpu_regs[src]);
830 }
831
832 static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)
833 {
834 opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]);
835 }
836
837 static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
838 {
839 TCGv imm = tcg_const_i32(src2);
840 opr(cpu_regs[dst], cpu_regs[src], imm);
841 tcg_temp_free(imm);
842 }
843
844 static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx,
845 int dst, int src, int ld, int mi)
846 {
847 TCGv val, mem;
848 mem = tcg_temp_new();
849 val = rx_load_source(ctx, mem, ld, mi, src);
850 opr(cpu_regs[dst], cpu_regs[dst], val);
851 tcg_temp_free(mem);
852 }
853
854 static void rx_and(TCGv ret, TCGv arg1, TCGv arg2)
855 {
856 tcg_gen_and_i32(cpu_psw_s, arg1, arg2);
857 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
858 tcg_gen_mov_i32(ret, cpu_psw_s);
859 }
860
861 /* and #uimm:4, rd */
862 /* and #imm, rd */
863 static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a)
864 {
865 rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm);
866 return true;
867 }
868
869 /* and dsp[rs], rd */
870 /* and rs,rd */
871 static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a)
872 {
873 rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi);
874 return true;
875 }
876
877 /* and rs,rs2,rd */
878 static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a)
879 {
880 rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2);
881 return true;
882 }
883
884 static void rx_or(TCGv ret, TCGv arg1, TCGv arg2)
885 {
886 tcg_gen_or_i32(cpu_psw_s, arg1, arg2);
887 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
888 tcg_gen_mov_i32(ret, cpu_psw_s);
889 }
890
891 /* or #uimm:4, rd */
892 /* or #imm, rd */
893 static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a)
894 {
895 rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm);
896 return true;
897 }
898
899 /* or dsp[rs], rd */
900 /* or rs,rd */
901 static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a)
902 {
903 rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi);
904 return true;
905 }
906
907 /* or rs,rs2,rd */
908 static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a)
909 {
910 rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2);
911 return true;
912 }
913
914 static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2)
915 {
916 tcg_gen_xor_i32(cpu_psw_s, arg1, arg2);
917 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
918 tcg_gen_mov_i32(ret, cpu_psw_s);
919 }
920
921 /* xor #imm, rd */
922 static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a)
923 {
924 rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm);
925 return true;
926 }
927
928 /* xor dsp[rs], rd */
929 /* xor rs,rd */
930 static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a)
931 {
932 rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi);
933 return true;
934 }
935
936 static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2)
937 {
938 tcg_gen_and_i32(cpu_psw_s, arg1, arg2);
939 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
940 }
941
942 /* tst #imm, rd */
943 static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a)
944 {
945 rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm);
946 return true;
947 }
948
949 /* tst dsp[rs], rd */
950 /* tst rs, rd */
951 static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a)
952 {
953 rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi);
954 return true;
955 }
956
957 static void rx_not(TCGv ret, TCGv arg1)
958 {
959 tcg_gen_not_i32(ret, arg1);
960 tcg_gen_mov_i32(cpu_psw_z, ret);
961 tcg_gen_mov_i32(cpu_psw_s, ret);
962 }
963
964 /* not rd */
965 /* not rs, rd */
966 static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a)
967 {
968 rx_gen_op_rr(rx_not, a->rd, a->rs);
969 return true;
970 }
971
972 static void rx_neg(TCGv ret, TCGv arg1)
973 {
974 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000);
975 tcg_gen_neg_i32(ret, arg1);
976 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0);
977 tcg_gen_mov_i32(cpu_psw_z, ret);
978 tcg_gen_mov_i32(cpu_psw_s, ret);
979 }
980
981
982 /* neg rd */
983 /* neg rs, rd */
984 static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a)
985 {
986 rx_gen_op_rr(rx_neg, a->rd, a->rs);
987 return true;
988 }
989
990 /* ret = arg1 + arg2 + psw_c */
991 static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2)
992 {
993 TCGv z;
994 z = tcg_const_i32(0);
995 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z);
996 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z);
997 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
998 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
999 tcg_gen_xor_i32(z, arg1, arg2);
1000 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
1001 tcg_gen_mov_i32(ret, cpu_psw_s);
1002 tcg_temp_free(z);
1003 }
1004
1005 /* adc #imm, rd */
1006 static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a)
1007 {
1008 rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm);
1009 return true;
1010 }
1011
1012 /* adc rs, rd */
1013 static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a)
1014 {
1015 rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs);
1016 return true;
1017 }
1018
1019 /* adc dsp[rs], rd */
1020 static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a)
1021 {
1022 /* mi only 2 */
1023 if (a->mi != 2) {
1024 return false;
1025 }
1026 rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi);
1027 return true;
1028 }
1029
1030 /* ret = arg1 + arg2 */
1031 static void rx_add(TCGv ret, TCGv arg1, TCGv arg2)
1032 {
1033 TCGv z;
1034 z = tcg_const_i32(0);
1035 tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z);
1036 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
1037 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
1038 tcg_gen_xor_i32(z, arg1, arg2);
1039 tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
1040 tcg_gen_mov_i32(ret, cpu_psw_s);
1041 tcg_temp_free(z);
1042 }
1043
1044 /* add #uimm4, rd */
1045 /* add #imm, rs, rd */
1046 static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a)
1047 {
1048 rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm);
1049 return true;
1050 }
1051
1052 /* add rs, rd */
1053 /* add dsp[rs], rd */
1054 static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a)
1055 {
1056 rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi);
1057 return true;
1058 }
1059
1060 /* add rs, rs2, rd */
1061 static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a)
1062 {
1063 rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2);
1064 return true;
1065 }
1066
1067 /* ret = arg1 - arg2 */
1068 static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
1069 {
1070 TCGv temp;
1071 tcg_gen_sub_i32(cpu_psw_s, arg1, arg2);
1072 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
1073 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2);
1074 tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
1075 temp = tcg_temp_new_i32();
1076 tcg_gen_xor_i32(temp, arg1, arg2);
1077 tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
1078 tcg_temp_free_i32(temp);
1079 /* CMP not required return */
1080 if (ret) {
1081 tcg_gen_mov_i32(ret, cpu_psw_s);
1082 }
1083 }
1084 static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2)
1085 {
1086 rx_sub(NULL, arg1, arg2);
1087 }
1088 /* ret = arg1 - arg2 - !psw_c */
1089 /* -> ret = arg1 + ~arg2 + psw_c */
1090 static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2)
1091 {
1092 TCGv temp;
1093 temp = tcg_temp_new();
1094 tcg_gen_not_i32(temp, arg2);
1095 rx_adc(ret, arg1, temp);
1096 tcg_temp_free(temp);
1097 }
1098
1099 /* cmp #imm4, rs2 */
1100 /* cmp #imm8, rs2 */
1101 /* cmp #imm, rs2 */
1102 static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a)
1103 {
1104 rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm);
1105 return true;
1106 }
1107
1108 /* cmp rs, rs2 */
1109 /* cmp dsp[rs], rs2 */
1110 static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a)
1111 {
1112 rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi);
1113 return true;
1114 }
1115
1116 /* sub #imm4, rd */
1117 static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a)
1118 {
1119 rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm);
1120 return true;
1121 }
1122
1123 /* sub rs, rd */
1124 /* sub dsp[rs], rd */
1125 static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a)
1126 {
1127 rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi);
1128 return true;
1129 }
1130
1131 /* sub rs2, rs, rd */
1132 static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a)
1133 {
1134 rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs);
1135 return true;
1136 }
1137
1138 /* sbb rs, rd */
1139 static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a)
1140 {
1141 rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs);
1142 return true;
1143 }
1144
1145 /* sbb dsp[rs], rd */
1146 static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
1147 {
1148 /* mi only 2 */
1149 if (a->mi != 2) {
1150 return false;
1151 }
1152 rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi);
1153 return true;
1154 }
1155
1156 static void rx_abs(TCGv ret, TCGv arg1)
1157 {
1158 TCGv neg;
1159 TCGv zero;
1160 neg = tcg_temp_new();
1161 zero = tcg_const_i32(0);
1162 tcg_gen_neg_i32(neg, arg1);
1163 tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1);
1164 tcg_temp_free(neg);
1165 tcg_temp_free(zero);
1166 }
1167
1168 /* abs rd */
1169 /* abs rs, rd */
1170 static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a)
1171 {
1172 rx_gen_op_rr(rx_abs, a->rd, a->rs);
1173 return true;
1174 }
1175
1176 /* max #imm, rd */
1177 static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a)
1178 {
1179 rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm);
1180 return true;
1181 }
1182
1183 /* max rs, rd */
1184 /* max dsp[rs], rd */
1185 static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a)
1186 {
1187 rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi);
1188 return true;
1189 }
1190
1191 /* min #imm, rd */
1192 static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a)
1193 {
1194 rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm);
1195 return true;
1196 }
1197
1198 /* min rs, rd */
1199 /* min dsp[rs], rd */
1200 static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a)
1201 {
1202 rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi);
1203 return true;
1204 }
1205
1206 /* mul #uimm4, rd */
1207 /* mul #imm, rd */
1208 static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a)
1209 {
1210 rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm);
1211 return true;
1212 }
1213
1214 /* mul rs, rd */
1215 /* mul dsp[rs], rd */
1216 static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a)
1217 {
1218 rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi);
1219 return true;
1220 }
1221
1222 /* mul rs, rs2, rd */
1223 static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a)
1224 {
1225 rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2);
1226 return true;
1227 }
1228
1229 /* emul #imm, rd */
1230 static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
1231 {
1232 TCGv imm = tcg_const_i32(a->imm);
1233 if (a->rd > 14) {
1234 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
1235 }
1236 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
1237 cpu_regs[a->rd], imm);
1238 tcg_temp_free(imm);
1239 return true;
1240 }
1241
1242 /* emul rs, rd */
1243 /* emul dsp[rs], rd */
1244 static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
1245 {
1246 TCGv val, mem;
1247 if (a->rd > 14) {
1248 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
1249 }
1250 mem = tcg_temp_new();
1251 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
1252 tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
1253 cpu_regs[a->rd], val);
1254 tcg_temp_free(mem);
1255 return true;
1256 }
1257
1258 /* emulu #imm, rd */
1259 static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
1260 {
1261 TCGv imm = tcg_const_i32(a->imm);
1262 if (a->rd > 14) {
1263 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
1264 }
1265 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
1266 cpu_regs[a->rd], imm);
1267 tcg_temp_free(imm);
1268 return true;
1269 }
1270
1271 /* emulu rs, rd */
1272 /* emulu dsp[rs], rd */
1273 static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a)
1274 {
1275 TCGv val, mem;
1276 if (a->rd > 14) {
1277 qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
1278 }
1279 mem = tcg_temp_new();
1280 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
1281 tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
1282 cpu_regs[a->rd], val);
1283 tcg_temp_free(mem);
1284 return true;
1285 }
1286
1287 static void rx_div(TCGv ret, TCGv arg1, TCGv arg2)
1288 {
1289 gen_helper_div(ret, cpu_env, arg1, arg2);
1290 }
1291
1292 static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2)
1293 {
1294 gen_helper_divu(ret, cpu_env, arg1, arg2);
1295 }
1296
1297 /* div #imm, rd */
1298 static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a)
1299 {
1300 rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm);
1301 return true;
1302 }
1303
1304 /* div rs, rd */
1305 /* div dsp[rs], rd */
1306 static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a)
1307 {
1308 rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi);
1309 return true;
1310 }
1311
1312 /* divu #imm, rd */
1313 static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a)
1314 {
1315 rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm);
1316 return true;
1317 }
1318
1319 /* divu rs, rd */
1320 /* divu dsp[rs], rd */
1321 static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a)
1322 {
1323 rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi);
1324 return true;
1325 }
1326
1327
1328 /* shll #imm:5, rd */
1329 /* shll #imm:5, rs2, rd */
1330 static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a)
1331 {
1332 TCGv tmp;
1333 tmp = tcg_temp_new();
1334 if (a->imm) {
1335 tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm);
1336 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm);
1337 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0);
1338 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff);
1339 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp);
1340 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0);
1341 } else {
1342 tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]);
1343 tcg_gen_movi_i32(cpu_psw_c, 0);
1344 tcg_gen_movi_i32(cpu_psw_o, 0);
1345 }
1346 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]);
1347 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]);
1348 return true;
1349 }
1350
1351 /* shll rs, rd */
1352 static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
1353 {
1354 TCGLabel *noshift, *done;
1355 TCGv count, tmp;
1356
1357 noshift = gen_new_label();
1358 done = gen_new_label();
1359 /* if (cpu_regs[a->rs]) { */
1360 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift);
1361 count = tcg_const_i32(32);
1362 tmp = tcg_temp_new();
1363 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31);
1364 tcg_gen_sub_i32(count, count, tmp);
1365 tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count);
1366 tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp);
1367 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0);
1368 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff);
1369 tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp);
1370 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0);
1371 tcg_gen_br(done);
1372 /* } else { */
1373 gen_set_label(noshift);
1374 tcg_gen_movi_i32(cpu_psw_c, 0);
1375 tcg_gen_movi_i32(cpu_psw_o, 0);
1376 /* } */
1377 gen_set_label(done);
1378 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]);
1379 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]);
1380 tcg_temp_free(count);
1381 tcg_temp_free(tmp);
1382 return true;
1383 }
1384
1385 static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm,
1386 unsigned int alith)
1387 {
1388 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = {
1389 tcg_gen_shri_i32, tcg_gen_sari_i32,
1390 };
1391 tcg_debug_assert(alith < 2);
1392 if (imm) {
1393 gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1);
1394 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001);
1395 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1);
1396 } else {
1397 tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]);
1398 tcg_gen_movi_i32(cpu_psw_c, 0);
1399 }
1400 tcg_gen_movi_i32(cpu_psw_o, 0);
1401 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]);
1402 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]);
1403 }
1404
1405 static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith)
1406 {
1407 TCGLabel *noshift, *done;
1408 TCGv count;
1409 static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = {
1410 tcg_gen_shri_i32, tcg_gen_sari_i32,
1411 };
1412 static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) = {
1413 tcg_gen_shr_i32, tcg_gen_sar_i32,
1414 };
1415 tcg_debug_assert(alith < 2);
1416 noshift = gen_new_label();
1417 done = gen_new_label();
1418 count = tcg_temp_new();
1419 /* if (cpu_regs[rs]) { */
1420 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift);
1421 tcg_gen_andi_i32(count, cpu_regs[rs], 31);
1422 tcg_gen_subi_i32(count, count, 1);
1423 gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count);
1424 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001);
1425 gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1);
1426 tcg_gen_br(done);
1427 /* } else { */
1428 gen_set_label(noshift);
1429 tcg_gen_movi_i32(cpu_psw_c, 0);
1430 /* } */
1431 gen_set_label(done);
1432 tcg_gen_movi_i32(cpu_psw_o, 0);
1433 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]);
1434 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]);
1435 tcg_temp_free(count);
1436 }
1437
1438 /* shar #imm:5, rd */
1439 /* shar #imm:5, rs2, rd */
1440 static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a)
1441 {
1442 shiftr_imm(a->rd, a->rs2, a->imm, 1);
1443 return true;
1444 }
1445
1446 /* shar rs, rd */
1447 static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a)
1448 {
1449 shiftr_reg(a->rd, a->rs, 1);
1450 return true;
1451 }
1452
1453 /* shlr #imm:5, rd */
1454 /* shlr #imm:5, rs2, rd */
1455 static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a)
1456 {
1457 shiftr_imm(a->rd, a->rs2, a->imm, 0);
1458 return true;
1459 }
1460
1461 /* shlr rs, rd */
1462 static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a)
1463 {
1464 shiftr_reg(a->rd, a->rs, 0);
1465 return true;
1466 }
1467
1468 /* rolc rd */
1469 static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a)
1470 {
1471 TCGv tmp;
1472 tmp = tcg_temp_new();
1473 tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31);
1474 tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1);
1475 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c);
1476 tcg_gen_mov_i32(cpu_psw_c, tmp);
1477 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]);
1478 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]);
1479 tcg_temp_free(tmp);
1480 return true;
1481 }
1482
1483 /* rorc rd */
1484 static bool trans_RORC(DisasContext *ctx, arg_RORC *a)
1485 {
1486 TCGv tmp;
1487 tmp = tcg_temp_new();
1488 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001);
1489 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1);
1490 tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31);
1491 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c);
1492 tcg_gen_mov_i32(cpu_psw_c, tmp);
1493 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]);
1494 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]);
1495 return true;
1496 }
1497
1498 enum {ROTR = 0, ROTL = 1};
1499 enum {ROT_IMM = 0, ROT_REG = 1};
1500 static inline void rx_rot(int ir, int dir, int rd, int src)
1501 {
1502 switch (dir) {
1503 case ROTL:
1504 if (ir == ROT_IMM) {
1505 tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src);
1506 } else {
1507 tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]);
1508 }
1509 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001);
1510 break;
1511 case ROTR:
1512 if (ir == ROT_IMM) {
1513 tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src);
1514 } else {
1515 tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]);
1516 }
1517 tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31);
1518 break;
1519 }
1520 tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]);
1521 tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]);
1522 }
1523
1524 /* rotl #imm, rd */
1525 static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a)
1526 {
1527 rx_rot(ROT_IMM, ROTL, a->rd, a->imm);
1528 return true;
1529 }
1530
1531 /* rotl rs, rd */
1532 static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a)
1533 {
1534 rx_rot(ROT_REG, ROTL, a->rd, a->rs);
1535 return true;
1536 }
1537
1538 /* rotr #imm, rd */
1539 static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a)
1540 {
1541 rx_rot(ROT_IMM, ROTR, a->rd, a->imm);
1542 return true;
1543 }
1544
1545 /* rotr rs, rd */
1546 static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a)
1547 {
1548 rx_rot(ROT_REG, ROTR, a->rd, a->rs);
1549 return true;
1550 }
1551
1552 /* revl rs, rd */
1553 static bool trans_REVL(DisasContext *ctx, arg_REVL *a)
1554 {
1555 tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]);
1556 return true;
1557 }
1558
1559 /* revw rs, rd */
1560 static bool trans_REVW(DisasContext *ctx, arg_REVW *a)
1561 {
1562 TCGv tmp;
1563 tmp = tcg_temp_new();
1564 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff);
1565 tcg_gen_shli_i32(tmp, tmp, 8);
1566 tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8);
1567 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff);
1568 tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp);
1569 tcg_temp_free(tmp);
1570 return true;
1571 }
1572
1573 /* conditional branch helper */
1574 static void rx_bcnd_main(DisasContext *ctx, int cd, int dst)
1575 {
1576 DisasCompare dc;
1577 TCGLabel *t, *done;
1578
1579 switch (cd) {
1580 case 0 ... 13:
1581 dc.temp = tcg_temp_new();
1582 psw_cond(&dc, cd);
1583 t = gen_new_label();
1584 done = gen_new_label();
1585 tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t);
1586 gen_goto_tb(ctx, 0, ctx->base.pc_next);
1587 tcg_gen_br(done);
1588 gen_set_label(t);
1589 gen_goto_tb(ctx, 1, ctx->pc + dst);
1590 gen_set_label(done);
1591 tcg_temp_free(dc.temp);
1592 break;
1593 case 14:
1594 /* always true case */
1595 gen_goto_tb(ctx, 0, ctx->pc + dst);
1596 break;
1597 case 15:
1598 /* always false case */
1599 /* Nothing do */
1600 break;
1601 }
1602 }
1603
1604 /* beq dsp:3 / bne dsp:3 */
1605 /* beq dsp:8 / bne dsp:8 */
1606 /* bc dsp:8 / bnc dsp:8 */
1607 /* bgtu dsp:8 / bleu dsp:8 */
1608 /* bpz dsp:8 / bn dsp:8 */
1609 /* bge dsp:8 / blt dsp:8 */
1610 /* bgt dsp:8 / ble dsp:8 */
1611 /* bo dsp:8 / bno dsp:8 */
1612 /* beq dsp:16 / bne dsp:16 */
1613 static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a)
1614 {
1615 rx_bcnd_main(ctx, a->cd, a->dsp);
1616 return true;
1617 }
1618
1619 /* bra dsp:3 */
1620 /* bra dsp:8 */
1621 /* bra dsp:16 */
1622 /* bra dsp:24 */
1623 static bool trans_BRA(DisasContext *ctx, arg_BRA *a)
1624 {
1625 rx_bcnd_main(ctx, 14, a->dsp);
1626 return true;
1627 }
1628
1629 /* bra rs */
1630 static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a)
1631 {
1632 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc);
1633 ctx->base.is_jmp = DISAS_JUMP;
1634 return true;
1635 }
1636
1637 static inline void rx_save_pc(DisasContext *ctx)
1638 {
1639 TCGv pc = tcg_const_i32(ctx->base.pc_next);
1640 push(pc);
1641 tcg_temp_free(pc);
1642 }
1643
1644 /* jmp rs */
1645 static bool trans_JMP(DisasContext *ctx, arg_JMP *a)
1646 {
1647 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]);
1648 ctx->base.is_jmp = DISAS_JUMP;
1649 return true;
1650 }
1651
1652 /* jsr rs */
1653 static bool trans_JSR(DisasContext *ctx, arg_JSR *a)
1654 {
1655 rx_save_pc(ctx);
1656 tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]);
1657 ctx->base.is_jmp = DISAS_JUMP;
1658 return true;
1659 }
1660
1661 /* bsr dsp:16 */
1662 /* bsr dsp:24 */
1663 static bool trans_BSR(DisasContext *ctx, arg_BSR *a)
1664 {
1665 rx_save_pc(ctx);
1666 rx_bcnd_main(ctx, 14, a->dsp);
1667 return true;
1668 }
1669
1670 /* bsr rs */
1671 static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a)
1672 {
1673 rx_save_pc(ctx);
1674 tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc);
1675 ctx->base.is_jmp = DISAS_JUMP;
1676 return true;
1677 }
1678
1679 /* rts */
1680 static bool trans_RTS(DisasContext *ctx, arg_RTS *a)
1681 {
1682 pop(cpu_pc);
1683 ctx->base.is_jmp = DISAS_JUMP;
1684 return true;
1685 }
1686
1687 /* nop */
1688 static bool trans_NOP(DisasContext *ctx, arg_NOP *a)
1689 {
1690 return true;
1691 }
1692
1693 /* scmpu */
1694 static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a)
1695 {
1696 gen_helper_scmpu(cpu_env);
1697 return true;
1698 }
1699
1700 /* smovu */
1701 static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a)
1702 {
1703 gen_helper_smovu(cpu_env);
1704 return true;
1705 }
1706
1707 /* smovf */
1708 static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a)
1709 {
1710 gen_helper_smovf(cpu_env);
1711 return true;
1712 }
1713
1714 /* smovb */
1715 static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
1716 {
1717 gen_helper_smovb(cpu_env);
1718 return true;
1719 }
1720
1721 #define STRING(op) \
1722 do { \
1723 TCGv size = tcg_const_i32(a->sz); \
1724 gen_helper_##op(cpu_env, size); \
1725 tcg_temp_free(size); \
1726 } while (0)
1727
1728 /* suntile.<bwl> */
1729 static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a)
1730 {
1731 STRING(suntil);
1732 return true;
1733 }
1734
1735 /* swhile.<bwl> */
1736 static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a)
1737 {
1738 STRING(swhile);
1739 return true;
1740 }
1741 /* sstr.<bwl> */
1742 static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a)
1743 {
1744 STRING(sstr);
1745 return true;
1746 }
1747
1748 /* rmpa.<bwl> */
1749 static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a)
1750 {
1751 STRING(rmpa);
1752 return true;
1753 }
1754
1755 static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2)
1756 {
1757 TCGv_i64 tmp0, tmp1;
1758 tmp0 = tcg_temp_new_i64();
1759 tmp1 = tcg_temp_new_i64();
1760 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]);
1761 tcg_gen_sari_i64(tmp0, tmp0, 16);
1762 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]);
1763 tcg_gen_sari_i64(tmp1, tmp1, 16);
1764 tcg_gen_mul_i64(ret, tmp0, tmp1);
1765 tcg_gen_shli_i64(ret, ret, 16);
1766 tcg_temp_free_i64(tmp0);
1767 tcg_temp_free_i64(tmp1);
1768 }
1769
1770 static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2)
1771 {
1772 TCGv_i64 tmp0, tmp1;
1773 tmp0 = tcg_temp_new_i64();
1774 tmp1 = tcg_temp_new_i64();
1775 tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]);
1776 tcg_gen_ext16s_i64(tmp0, tmp0);
1777 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]);
1778 tcg_gen_ext16s_i64(tmp1, tmp1);
1779 tcg_gen_mul_i64(ret, tmp0, tmp1);
1780 tcg_gen_shli_i64(ret, ret, 16);
1781 tcg_temp_free_i64(tmp0);
1782 tcg_temp_free_i64(tmp1);
1783 }
1784
1785 /* mulhi rs,rs2 */
1786 static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a)
1787 {
1788 rx_mul64hi(cpu_acc, a->rs, a->rs2);
1789 return true;
1790 }
1791
1792 /* mullo rs,rs2 */
1793 static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a)
1794 {
1795 rx_mul64lo(cpu_acc, a->rs, a->rs2);
1796 return true;
1797 }
1798
1799 /* machi rs,rs2 */
1800 static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a)
1801 {
1802 TCGv_i64 tmp;
1803 tmp = tcg_temp_new_i64();
1804 rx_mul64hi(tmp, a->rs, a->rs2);
1805 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp);
1806 tcg_temp_free_i64(tmp);
1807 return true;
1808 }
1809
1810 /* maclo rs,rs2 */
1811 static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a)
1812 {
1813 TCGv_i64 tmp;
1814 tmp = tcg_temp_new_i64();
1815 rx_mul64lo(tmp, a->rs, a->rs2);
1816 tcg_gen_add_i64(cpu_acc, cpu_acc, tmp);
1817 tcg_temp_free_i64(tmp);
1818 return true;
1819 }
1820
1821 /* mvfachi rd */
1822 static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a)
1823 {
1824 tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc);
1825 return true;
1826 }
1827
1828 /* mvfacmi rd */
1829 static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a)
1830 {
1831 TCGv_i64 rd64;
1832 rd64 = tcg_temp_new_i64();
1833 tcg_gen_extract_i64(rd64, cpu_acc, 16, 32);
1834 tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64);
1835 tcg_temp_free_i64(rd64);
1836 return true;
1837 }
1838
1839 /* mvtachi rs */
1840 static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a)
1841 {
1842 TCGv_i64 rs64;
1843 rs64 = tcg_temp_new_i64();
1844 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]);
1845 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32);
1846 tcg_temp_free_i64(rs64);
1847 return true;
1848 }
1849
1850 /* mvtaclo rs */
1851 static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
1852 {
1853 TCGv_i64 rs64;
1854 rs64 = tcg_temp_new_i64();
1855 tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]);
1856 tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32);
1857 tcg_temp_free_i64(rs64);
1858 return true;
1859 }
1860
1861 /* racw #imm */
1862 static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
1863 {
1864 TCGv imm = tcg_const_i32(a->imm + 1);
1865 gen_helper_racw(cpu_env, imm);
1866 tcg_temp_free(imm);
1867 return true;
1868 }
1869
1870 /* sat rd */
1871 static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
1872 {
1873 TCGv tmp, z;
1874 tmp = tcg_temp_new();
1875 z = tcg_const_i32(0);
1876 /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
1877 tcg_gen_sari_i32(tmp, cpu_psw_s, 31);
1878 /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */
1879 tcg_gen_xori_i32(tmp, tmp, 0x80000000);
1880 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd],
1881 cpu_psw_o, z, tmp, cpu_regs[a->rd]);
1882 tcg_temp_free(tmp);
1883 tcg_temp_free(z);
1884 return true;
1885 }
1886
1887 /* satr */
1888 static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
1889 {
1890 gen_helper_satr(cpu_env);
1891 return true;
1892 }
1893
1894 #define cat3(a, b, c) a##b##c
1895 #define FOP(name, op) \
1896 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
1897 cat3(arg_, name, _ir) * a) \
1898 { \
1899 TCGv imm = tcg_const_i32(li(ctx, 0)); \
1900 gen_helper_##op(cpu_regs[a->rd], cpu_env, \
1901 cpu_regs[a->rd], imm); \
1902 tcg_temp_free(imm); \
1903 return true; \
1904 } \
1905 static bool cat3(trans_, name, _mr)(DisasContext *ctx, \
1906 cat3(arg_, name, _mr) * a) \
1907 { \
1908 TCGv val, mem; \
1909 mem = tcg_temp_new(); \
1910 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1911 gen_helper_##op(cpu_regs[a->rd], cpu_env, \
1912 cpu_regs[a->rd], val); \
1913 tcg_temp_free(mem); \
1914 return true; \
1915 }
1916
1917 #define FCONVOP(name, op) \
1918 static bool trans_##name(DisasContext *ctx, arg_##name * a) \
1919 { \
1920 TCGv val, mem; \
1921 mem = tcg_temp_new(); \
1922 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1923 gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \
1924 tcg_temp_free(mem); \
1925 return true; \
1926 }
1927
1928 FOP(FADD, fadd)
1929 FOP(FSUB, fsub)
1930 FOP(FMUL, fmul)
1931 FOP(FDIV, fdiv)
1932
1933 /* fcmp #imm, rd */
1934 static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
1935 {
1936 TCGv imm = tcg_const_i32(li(ctx, 0));
1937 gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm);
1938 tcg_temp_free(imm);
1939 return true;
1940 }
1941
1942 /* fcmp dsp[rs], rd */
1943 /* fcmp rs, rd */
1944 static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a)
1945 {
1946 TCGv val, mem;
1947 mem = tcg_temp_new();
1948 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs);
1949 gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val);
1950 tcg_temp_free(mem);
1951 return true;
1952 }
1953
1954 FCONVOP(FTOI, ftoi)
1955 FCONVOP(ROUND, round)
1956
1957 /* itof rs, rd */
1958 /* itof dsp[rs], rd */
1959 static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a)
1960 {
1961 TCGv val, mem;
1962 mem = tcg_temp_new();
1963 val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
1964 gen_helper_itof(cpu_regs[a->rd], cpu_env, val);
1965 tcg_temp_free(mem);
1966 return true;
1967 }
1968
1969 static void rx_bsetm(TCGv mem, TCGv mask)
1970 {
1971 TCGv val;
1972 val = tcg_temp_new();
1973 rx_gen_ld(MO_8, val, mem);
1974 tcg_gen_or_i32(val, val, mask);
1975 rx_gen_st(MO_8, val, mem);
1976 tcg_temp_free(val);
1977 }
1978
1979 static void rx_bclrm(TCGv mem, TCGv mask)
1980 {
1981 TCGv val;
1982 val = tcg_temp_new();
1983 rx_gen_ld(MO_8, val, mem);
1984 tcg_gen_andc_i32(val, val, mask);
1985 rx_gen_st(MO_8, val, mem);
1986 tcg_temp_free(val);
1987 }
1988
1989 static void rx_btstm(TCGv mem, TCGv mask)
1990 {
1991 TCGv val;
1992 val = tcg_temp_new();
1993 rx_gen_ld(MO_8, val, mem);
1994 tcg_gen_and_i32(val, val, mask);
1995 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0);
1996 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c);
1997 tcg_temp_free(val);
1998 }
1999
2000 static void rx_bnotm(TCGv mem, TCGv mask)
2001 {
2002 TCGv val;
2003 val = tcg_temp_new();
2004 rx_gen_ld(MO_8, val, mem);
2005 tcg_gen_xor_i32(val, val, mask);
2006 rx_gen_st(MO_8, val, mem);
2007 tcg_temp_free(val);
2008 }
2009
2010 static void rx_bsetr(TCGv reg, TCGv mask)
2011 {
2012 tcg_gen_or_i32(reg, reg, mask);
2013 }
2014
2015 static void rx_bclrr(TCGv reg, TCGv mask)
2016 {
2017 tcg_gen_andc_i32(reg, reg, mask);
2018 }
2019
2020 static inline void rx_btstr(TCGv reg, TCGv mask)
2021 {
2022 TCGv t0;
2023 t0 = tcg_temp_new();
2024 tcg_gen_and_i32(t0, reg, mask);
2025 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0);
2026 tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c);
2027 tcg_temp_free(t0);
2028 }
2029
2030 static inline void rx_bnotr(TCGv reg, TCGv mask)
2031 {
2032 tcg_gen_xor_i32(reg, reg, mask);
2033 }
2034
2035 #define BITOP(name, op) \
2036 static bool cat3(trans_, name, _im)(DisasContext *ctx, \
2037 cat3(arg_, name, _im) * a) \
2038 { \
2039 TCGv mask, mem, addr; \
2040 mem = tcg_temp_new(); \
2041 mask = tcg_const_i32(1 << a->imm); \
2042 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
2043 cat3(rx_, op, m)(addr, mask); \
2044 tcg_temp_free(mask); \
2045 tcg_temp_free(mem); \
2046 return true; \
2047 } \
2048 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
2049 cat3(arg_, name, _ir) * a) \
2050 { \
2051 TCGv mask; \
2052 mask = tcg_const_i32(1 << a->imm); \
2053 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
2054 tcg_temp_free(mask); \
2055 return true; \
2056 } \
2057 static bool cat3(trans_, name, _rr)(DisasContext *ctx, \
2058 cat3(arg_, name, _rr) * a) \
2059 { \
2060 TCGv mask, b; \
2061 mask = tcg_const_i32(1); \
2062 b = tcg_temp_new(); \
2063 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
2064 tcg_gen_shl_i32(mask, mask, b); \
2065 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
2066 tcg_temp_free(mask); \
2067 tcg_temp_free(b); \
2068 return true; \
2069 } \
2070 static bool cat3(trans_, name, _rm)(DisasContext *ctx, \
2071 cat3(arg_, name, _rm) * a) \
2072 { \
2073 TCGv mask, mem, addr, b; \
2074 mask = tcg_const_i32(1); \
2075 b = tcg_temp_new(); \
2076 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
2077 tcg_gen_shl_i32(mask, mask, b); \
2078 mem = tcg_temp_new(); \
2079 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
2080 cat3(rx_, op, m)(addr, mask); \
2081 tcg_temp_free(mem); \
2082 tcg_temp_free(mask); \
2083 tcg_temp_free(b); \
2084 return true; \
2085 }
2086
2087 BITOP(BSET, bset)
2088 BITOP(BCLR, bclr)
2089 BITOP(BTST, btst)
2090 BITOP(BNOT, bnot)
2091
2092 static inline void bmcnd_op(TCGv val, TCGCond cond, int pos)
2093 {
2094 TCGv bit;
2095 DisasCompare dc;
2096 dc.temp = tcg_temp_new();
2097 bit = tcg_temp_new();
2098 psw_cond(&dc, cond);
2099 tcg_gen_andi_i32(val, val, ~(1 << pos));
2100 tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0);
2101 tcg_gen_deposit_i32(val, val, bit, pos, 1);
2102 tcg_temp_free(bit);
2103 tcg_temp_free(dc.temp);
2104 }
2105
2106 /* bmcnd #imm, dsp[rd] */
2107 static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a)
2108 {
2109 TCGv val, mem, addr;
2110 val = tcg_temp_new();
2111 mem = tcg_temp_new();
2112 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd);
2113 rx_gen_ld(MO_8, val, addr);
2114 bmcnd_op(val, a->cd, a->imm);
2115 rx_gen_st(MO_8, val, addr);
2116 tcg_temp_free(val);
2117 tcg_temp_free(mem);
2118 return true;
2119 }
2120
2121 /* bmcond #imm, rd */
2122 static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a)
2123 {
2124 bmcnd_op(cpu_regs[a->rd], a->cd, a->imm);
2125 return true;
2126 }
2127
2128 enum {
2129 PSW_C = 0,
2130 PSW_Z = 1,
2131 PSW_S = 2,
2132 PSW_O = 3,
2133 PSW_I = 8,
2134 PSW_U = 9,
2135 };
2136
2137 static inline void clrsetpsw(DisasContext *ctx, int cb, int val)
2138 {
2139 if (cb < 8) {
2140 switch (cb) {
2141 case PSW_C:
2142 tcg_gen_movi_i32(cpu_psw_c, val);
2143 break;
2144 case PSW_Z:
2145 tcg_gen_movi_i32(cpu_psw_z, val == 0);
2146 break;
2147 case PSW_S:
2148 tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0);
2149 break;
2150 case PSW_O:
2151 tcg_gen_movi_i32(cpu_psw_o, val << 31);
2152 break;
2153 default:
2154 qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb);
2155 break;
2156 }
2157 } else if (is_privileged(ctx, 0)) {
2158 switch (cb) {
2159 case PSW_I:
2160 tcg_gen_movi_i32(cpu_psw_i, val);
2161 ctx->base.is_jmp = DISAS_UPDATE;
2162 break;
2163 case PSW_U:
2164 tcg_gen_movi_i32(cpu_psw_u, val);
2165 break;
2166 default:
2167 qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb);
2168 break;
2169 }
2170 }
2171 }
2172
2173 /* clrpsw psw */
2174 static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a)
2175 {
2176 clrsetpsw(ctx, a->cb, 0);
2177 return true;
2178 }
2179
2180 /* setpsw psw */
2181 static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a)
2182 {
2183 clrsetpsw(ctx, a->cb, 1);
2184 return true;
2185 }
2186
2187 /* mvtipl #imm */
2188 static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a)
2189 {
2190 if (is_privileged(ctx, 1)) {
2191 tcg_gen_movi_i32(cpu_psw_ipl, a->imm);
2192 ctx->base.is_jmp = DISAS_UPDATE;
2193 }
2194 return true;
2195 }
2196
2197 /* mvtc #imm, rd */
2198 static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
2199 {
2200 TCGv imm;
2201
2202 imm = tcg_const_i32(a->imm);
2203 move_to_cr(ctx, imm, a->cr);
2204 if (a->cr == 0 && is_privileged(ctx, 0)) {
2205 ctx->base.is_jmp = DISAS_UPDATE;
2206 }
2207 tcg_temp_free(imm);
2208 return true;
2209 }
2210
2211 /* mvtc rs, rd */
2212 static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a)
2213 {
2214 move_to_cr(ctx, cpu_regs[a->rs], a->cr);
2215 if (a->cr == 0 && is_privileged(ctx, 0)) {
2216 ctx->base.is_jmp = DISAS_UPDATE;
2217 }
2218 return true;
2219 }
2220
2221 /* mvfc rs, rd */
2222 static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a)
2223 {
2224 move_from_cr(cpu_regs[a->rd], a->cr, ctx->pc);
2225 return true;
2226 }
2227
2228 /* rtfi */
2229 static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a)
2230 {
2231 TCGv psw;
2232 if (is_privileged(ctx, 1)) {
2233 psw = tcg_temp_new();
2234 tcg_gen_mov_i32(cpu_pc, cpu_bpc);
2235 tcg_gen_mov_i32(psw, cpu_bpsw);
2236 gen_helper_set_psw_rte(cpu_env, psw);
2237 ctx->base.is_jmp = DISAS_EXIT;
2238 tcg_temp_free(psw);
2239 }
2240 return true;
2241 }
2242
2243 /* rte */
2244 static bool trans_RTE(DisasContext *ctx, arg_RTE *a)
2245 {
2246 TCGv psw;
2247 if (is_privileged(ctx, 1)) {
2248 psw = tcg_temp_new();
2249 pop(cpu_pc);
2250 pop(psw);
2251 gen_helper_set_psw_rte(cpu_env, psw);
2252 ctx->base.is_jmp = DISAS_EXIT;
2253 tcg_temp_free(psw);
2254 }
2255 return true;
2256 }
2257
2258 /* brk */
2259 static bool trans_BRK(DisasContext *ctx, arg_BRK *a)
2260 {
2261 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
2262 gen_helper_rxbrk(cpu_env);
2263 ctx->base.is_jmp = DISAS_NORETURN;
2264 return true;
2265 }
2266
2267 /* int #imm */
2268 static bool trans_INT(DisasContext *ctx, arg_INT *a)
2269 {
2270 TCGv vec;
2271
2272 tcg_debug_assert(a->imm < 0x100);
2273 vec = tcg_const_i32(a->imm);
2274 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
2275 gen_helper_rxint(cpu_env, vec);
2276 tcg_temp_free(vec);
2277 ctx->base.is_jmp = DISAS_NORETURN;
2278 return true;
2279 }
2280
2281 /* wait */
2282 static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a)
2283 {
2284 if (is_privileged(ctx, 1)) {
2285 tcg_gen_addi_i32(cpu_pc, cpu_pc, 2);
2286 gen_helper_wait(cpu_env);
2287 }
2288 return true;
2289 }
2290
2291 static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
2292 {
2293 CPURXState *env = cs->env_ptr;
2294 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2295 ctx->env = env;
2296 ctx->tb_flags = ctx->base.tb->flags;
2297 }
2298
2299 static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
2300 {
2301 }
2302
2303 static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
2304 {
2305 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2306
2307 tcg_gen_insn_start(ctx->base.pc_next);
2308 }
2309
2310 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
2311 {
2312 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2313 uint32_t insn;
2314
2315 ctx->pc = ctx->base.pc_next;
2316 insn = decode_load(ctx);
2317 if (!decode(ctx, insn)) {
2318 gen_helper_raise_illegal_instruction(cpu_env);
2319 }
2320 }
2321
2322 static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
2323 {
2324 DisasContext *ctx = container_of(dcbase, DisasContext, base);
2325
2326 switch (ctx->base.is_jmp) {
2327 case DISAS_NEXT:
2328 case DISAS_TOO_MANY:
2329 gen_goto_tb(ctx, 0, dcbase->pc_next);
2330 break;
2331 case DISAS_JUMP:
2332 tcg_gen_lookup_and_goto_ptr();
2333 break;
2334 case DISAS_UPDATE:
2335 tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
2336 /* fall through */
2337 case DISAS_EXIT:
2338 tcg_gen_exit_tb(NULL, 0);
2339 break;
2340 case DISAS_NORETURN:
2341 break;
2342 default:
2343 g_assert_not_reached();
2344 }
2345 }
2346
2347 static void rx_tr_disas_log(const DisasContextBase *dcbase,
2348 CPUState *cs, FILE *logfile)
2349 {
2350 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
2351 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size);
2352 }
2353
2354 static const TranslatorOps rx_tr_ops = {
2355 .init_disas_context = rx_tr_init_disas_context,
2356 .tb_start = rx_tr_tb_start,
2357 .insn_start = rx_tr_insn_start,
2358 .translate_insn = rx_tr_translate_insn,
2359 .tb_stop = rx_tr_tb_stop,
2360 .disas_log = rx_tr_disas_log,
2361 };
2362
2363 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
2364 {
2365 DisasContext dc;
2366
2367 translator_loop(&rx_tr_ops, &dc.base, cs, tb, max_insns);
2368 }
2369
2370 void restore_state_to_opc(CPURXState *env, TranslationBlock *tb,
2371 target_ulong *data)
2372 {
2373 env->pc = data[0];
2374 }
2375
2376 #define ALLOC_REGISTER(sym, name) \
2377 cpu_##sym = tcg_global_mem_new_i32(cpu_env, \
2378 offsetof(CPURXState, sym), name)
2379
2380 void rx_translate_init(void)
2381 {
2382 static const char * const regnames[NUM_REGS] = {
2383 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
2384 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"
2385 };
2386 int i;
2387
2388 for (i = 0; i < NUM_REGS; i++) {
2389 cpu_regs[i] = tcg_global_mem_new_i32(cpu_env,
2390 offsetof(CPURXState, regs[i]),
2391 regnames[i]);
2392 }
2393 ALLOC_REGISTER(pc, "PC");
2394 ALLOC_REGISTER(psw_o, "PSW(O)");
2395 ALLOC_REGISTER(psw_s, "PSW(S)");
2396 ALLOC_REGISTER(psw_z, "PSW(Z)");
2397 ALLOC_REGISTER(psw_c, "PSW(C)");
2398 ALLOC_REGISTER(psw_u, "PSW(U)");
2399 ALLOC_REGISTER(psw_i, "PSW(I)");
2400 ALLOC_REGISTER(psw_pm, "PSW(PM)");
2401 ALLOC_REGISTER(psw_ipl, "PSW(IPL)");
2402 ALLOC_REGISTER(usp, "USP");
2403 ALLOC_REGISTER(fpsw, "FPSW");
2404 ALLOC_REGISTER(bpsw, "BPSW");
2405 ALLOC_REGISTER(bpc, "BPC");
2406 ALLOC_REGISTER(isp, "ISP");
2407 ALLOC_REGISTER(fintv, "FINTV");
2408 ALLOC_REGISTER(intb, "INTB");
2409 cpu_acc = tcg_global_mem_new_i64(cpu_env,
2410 offsetof(CPURXState, acc), "ACC");
2411 }
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