target/s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright IBM Corp. 2012, 2018
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef S390X_CPU_H
  22 #define S390X_CPU_H
  23
  24 #include "qemu-common.h"
  25 #include "cpu-qom.h"
  26 #include "cpu_models.h"
  27 #include "exec/cpu-defs.h"
  28
  29 #define ELF_MACHINE_UNAME "S390X"
  30
  31 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */
  32 #define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
  33
  34 #define TARGET_INSN_START_EXTRA_WORDS 1
  35
  36 #define MMU_MODE0_SUFFIX _primary
  37 #define MMU_MODE1_SUFFIX _secondary
  38 #define MMU_MODE2_SUFFIX _home
  39 #define MMU_MODE3_SUFFIX _real
  40
  41 #define MMU_USER_IDX 0
  42
  43 #define S390_MAX_CPUS 248
  44
  45 typedef struct PSW {
  46     uint64_t mask;
  47     uint64_t addr;
  48 } PSW;
  49
  50 struct CPUS390XState {
  51     uint64_t regs[16];     /* GP registers */
  52     /*
  53      * The floating point registers are part of the vector registers.
  54      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  55      */
  56     uint64_t vregs[32][2] QEMU_ALIGNED(16);  /* vector registers */
  57     uint32_t aregs[16];    /* access registers */
  58     uint8_t riccb[64];     /* runtime instrumentation control */
  59     uint64_t gscb[4];      /* guarded storage control */
  60     uint64_t etoken;       /* etoken */
  61     uint64_t etoken_extension; /* etoken extension */
  62
  63     /* Fields up to this point are not cleared by initial CPU reset */
  64     struct {} start_initial_reset_fields;
  65
  66     uint32_t fpc;          /* floating-point control register */
  67     uint32_t cc_op;
  68     bool bpbc;             /* branch prediction blocking */
  69
  70     float_status fpu_status; /* passed to softfloat lib */
  71
  72     /* The low part of a 128-bit return, or remainder of a divide.  */
  73     uint64_t retxl;
  74
  75     PSW psw;
  76
  77     S390CrashReason crash_reason;
  78
  79     uint64_t cc_src;
  80     uint64_t cc_dst;
  81     uint64_t cc_vr;
  82
  83     uint64_t ex_value;
  84
  85     uint64_t __excp_addr;
  86     uint64_t psa;
  87
  88     uint32_t int_pgm_code;
  89     uint32_t int_pgm_ilen;
  90
  91     uint32_t int_svc_code;
  92     uint32_t int_svc_ilen;
  93
  94     uint64_t per_address;
  95     uint16_t per_perc_atmid;
  96
  97     uint64_t cregs[16]; /* control registers */
  98
  99     int pending_int;
 100     uint16_t external_call_addr;
 101     DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
 102
 103     uint64_t ckc;
 104     uint64_t cputm;
 105     uint32_t todpr;
 106
 107     uint64_t pfault_token;
 108     uint64_t pfault_compare;
 109     uint64_t pfault_select;
 110
 111     uint64_t gbea;
 112     uint64_t pp;
 113
 114     /* Fields up to this point are cleared by a CPU reset */
 115     struct {} end_reset_fields;
 116
 117     CPU_COMMON
 118
 119 #if !defined(CONFIG_USER_ONLY)
 120     uint32_t core_id; /* PoP "CPU address", same as cpu_index */
 121     uint64_t cpuid;
 122 #endif
 123
 124     QEMUTimer *tod_timer;
 125
 126     QEMUTimer *cpu_timer;
 127
 128     /*
 129      * The cpu state represents the logical state of a cpu. In contrast to other
 130      * architectures, there is a difference between a halt and a stop on s390.
 131      * If all cpus are either stopped (including check stop) or in the disabled
 132      * wait state, the vm can be shut down.
 133      * The acceptable cpu_state values are defined in the CpuInfoS390State
 134      * enum.
 135      */
 136     uint8_t cpu_state;
 137
 138     /* currently processed sigp order */
 139     uint8_t sigp_order;
 140
 141 };
 142
 143 static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
 144 {
 145     return &cs->vregs[nr][0];
 146 }
 147
 148 /**
 149  * S390CPU:
 150  * @env: #CPUS390XState.
 151  *
 152  * An S/390 CPU.
 153  */
 154 struct S390CPU {
 155     /*< private >*/
 156     CPUState parent_obj;
 157     /*< public >*/
 158
 159     CPUS390XState env;
 160     S390CPUModel *model;
 161     /* needed for live migration */
 162     void *irqstate;
 163     uint32_t irqstate_saved_size;
 164 };
 165
 166 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
 167 {
 168     return container_of(env, S390CPU, env);
 169 }
 170
 171 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
 172
 173 #define ENV_OFFSET offsetof(S390CPU, env)
 174
 175 #ifndef CONFIG_USER_ONLY
 176 extern const struct VMStateDescription vmstate_s390_cpu;
 177 #endif
 178
 179 /* distinguish between 24 bit and 31 bit addressing */
 180 #define HIGH_ORDER_BIT 0x80000000
 181
 182 /* Interrupt Codes */
 183 /* Program Interrupts */
 184 #define PGM_OPERATION                   0x0001
 185 #define PGM_PRIVILEGED                  0x0002
 186 #define PGM_EXECUTE                     0x0003
 187 #define PGM_PROTECTION                  0x0004
 188 #define PGM_ADDRESSING                  0x0005
 189 #define PGM_SPECIFICATION               0x0006
 190 #define PGM_DATA                        0x0007
 191 #define PGM_FIXPT_OVERFLOW              0x0008
 192 #define PGM_FIXPT_DIVIDE                0x0009
 193 #define PGM_DEC_OVERFLOW                0x000a
 194 #define PGM_DEC_DIVIDE                  0x000b
 195 #define PGM_HFP_EXP_OVERFLOW            0x000c
 196 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 197 #define PGM_HFP_SIGNIFICANCE            0x000e
 198 #define PGM_HFP_DIVIDE                  0x000f
 199 #define PGM_SEGMENT_TRANS               0x0010
 200 #define PGM_PAGE_TRANS                  0x0011
 201 #define PGM_TRANS_SPEC                  0x0012
 202 #define PGM_SPECIAL_OP                  0x0013
 203 #define PGM_OPERAND                     0x0015
 204 #define PGM_TRACE_TABLE                 0x0016
 205 #define PGM_VECTOR_PROCESSING           0x001b
 206 #define PGM_SPACE_SWITCH                0x001c
 207 #define PGM_HFP_SQRT                    0x001d
 208 #define PGM_PC_TRANS_SPEC               0x001f
 209 #define PGM_AFX_TRANS                   0x0020
 210 #define PGM_ASX_TRANS                   0x0021
 211 #define PGM_LX_TRANS                    0x0022
 212 #define PGM_EX_TRANS                    0x0023
 213 #define PGM_PRIM_AUTH                   0x0024
 214 #define PGM_SEC_AUTH                    0x0025
 215 #define PGM_ALET_SPEC                   0x0028
 216 #define PGM_ALEN_SPEC                   0x0029
 217 #define PGM_ALE_SEQ                     0x002a
 218 #define PGM_ASTE_VALID                  0x002b
 219 #define PGM_ASTE_SEQ                    0x002c
 220 #define PGM_EXT_AUTH                    0x002d
 221 #define PGM_STACK_FULL                  0x0030
 222 #define PGM_STACK_EMPTY                 0x0031
 223 #define PGM_STACK_SPEC                  0x0032
 224 #define PGM_STACK_TYPE                  0x0033
 225 #define PGM_STACK_OP                    0x0034
 226 #define PGM_ASCE_TYPE                   0x0038
 227 #define PGM_REG_FIRST_TRANS             0x0039
 228 #define PGM_REG_SEC_TRANS               0x003a
 229 #define PGM_REG_THIRD_TRANS             0x003b
 230 #define PGM_MONITOR                     0x0040
 231 #define PGM_PER                         0x0080
 232 #define PGM_CRYPTO                      0x0119
 233
 234 /* External Interrupts */
 235 #define EXT_INTERRUPT_KEY               0x0040
 236 #define EXT_CLOCK_COMP                  0x1004
 237 #define EXT_CPU_TIMER                   0x1005
 238 #define EXT_MALFUNCTION                 0x1200
 239 #define EXT_EMERGENCY                   0x1201
 240 #define EXT_EXTERNAL_CALL               0x1202
 241 #define EXT_ETR                         0x1406
 242 #define EXT_SERVICE                     0x2401
 243 #define EXT_VIRTIO                      0x2603
 244
 245 /* PSW defines */
 246 #undef PSW_MASK_PER
 247 #undef PSW_MASK_UNUSED_2
 248 #undef PSW_MASK_UNUSED_3
 249 #undef PSW_MASK_DAT
 250 #undef PSW_MASK_IO
 251 #undef PSW_MASK_EXT
 252 #undef PSW_MASK_KEY
 253 #undef PSW_SHIFT_KEY
 254 #undef PSW_MASK_MCHECK
 255 #undef PSW_MASK_WAIT
 256 #undef PSW_MASK_PSTATE
 257 #undef PSW_MASK_ASC
 258 #undef PSW_SHIFT_ASC
 259 #undef PSW_MASK_CC
 260 #undef PSW_MASK_PM
 261 #undef PSW_SHIFT_MASK_PM
 262 #undef PSW_MASK_64
 263 #undef PSW_MASK_32
 264 #undef PSW_MASK_ESA_ADDR
 265
 266 #define PSW_MASK_PER            0x4000000000000000ULL
 267 #define PSW_MASK_UNUSED_2       0x2000000000000000ULL
 268 #define PSW_MASK_UNUSED_3       0x1000000000000000ULL
 269 #define PSW_MASK_DAT            0x0400000000000000ULL
 270 #define PSW_MASK_IO             0x0200000000000000ULL
 271 #define PSW_MASK_EXT            0x0100000000000000ULL
 272 #define PSW_MASK_KEY            0x00F0000000000000ULL
 273 #define PSW_SHIFT_KEY           52
 274 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 275 #define PSW_MASK_WAIT           0x0002000000000000ULL
 276 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 277 #define PSW_MASK_ASC            0x0000C00000000000ULL
 278 #define PSW_SHIFT_ASC           46
 279 #define PSW_MASK_CC             0x0000300000000000ULL
 280 #define PSW_MASK_PM             0x00000F0000000000ULL
 281 #define PSW_SHIFT_MASK_PM       40
 282 #define PSW_MASK_64             0x0000000100000000ULL
 283 #define PSW_MASK_32             0x0000000080000000ULL
 284 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 285
 286 #undef PSW_ASC_PRIMARY
 287 #undef PSW_ASC_ACCREG
 288 #undef PSW_ASC_SECONDARY
 289 #undef PSW_ASC_HOME
 290
 291 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 292 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 293 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 294 #define PSW_ASC_HOME            0x0000C00000000000ULL
 295
 296 /* the address space values shifted */
 297 #define AS_PRIMARY              0
 298 #define AS_ACCREG               1
 299 #define AS_SECONDARY            2
 300 #define AS_HOME                 3
 301
 302 /* tb flags */
 303
 304 #define FLAG_MASK_PSW_SHIFT     31
 305 #define FLAG_MASK_PER           (PSW_MASK_PER    >> FLAG_MASK_PSW_SHIFT)
 306 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> FLAG_MASK_PSW_SHIFT)
 307 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
 308 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> FLAG_MASK_PSW_SHIFT)
 309 #define FLAG_MASK_64            (PSW_MASK_64     >> FLAG_MASK_PSW_SHIFT)
 310 #define FLAG_MASK_32            (PSW_MASK_32     >> FLAG_MASK_PSW_SHIFT)
 311 #define FLAG_MASK_PSW           (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
 312                                 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
 313
 314 /* we'll use some unused PSW positions to store CR flags in tb flags */
 315 #define FLAG_MASK_AFP           (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
 316 #define FLAG_MASK_VECTOR        (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
 317
 318 /* Control register 0 bits */
 319 #define CR0_LOWPROT             0x0000000010000000ULL
 320 #define CR0_SECONDARY           0x0000000004000000ULL
 321 #define CR0_EDAT                0x0000000000800000ULL
 322 #define CR0_AFP                 0x0000000000040000ULL
 323 #define CR0_VECTOR              0x0000000000020000ULL
 324 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
 325 #define CR0_EXTERNAL_CALL_SC    0x0000000000002000ULL
 326 #define CR0_CKC_SC              0x0000000000000800ULL
 327 #define CR0_CPU_TIMER_SC        0x0000000000000400ULL
 328 #define CR0_SERVICE_SC          0x0000000000000200ULL
 329
 330 /* Control register 14 bits */
 331 #define CR14_CHANNEL_REPORT_SC  0x0000000010000000ULL
 332
 333 /* MMU */
 334 #define MMU_PRIMARY_IDX         0
 335 #define MMU_SECONDARY_IDX       1
 336 #define MMU_HOME_IDX            2
 337 #define MMU_REAL_IDX            3
 338
 339 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
 340 {
 341     if (!(env->psw.mask & PSW_MASK_DAT)) {
 342         return MMU_REAL_IDX;
 343     }
 344
 345     switch (env->psw.mask & PSW_MASK_ASC) {
 346     case PSW_ASC_PRIMARY:
 347         return MMU_PRIMARY_IDX;
 348     case PSW_ASC_SECONDARY:
 349         return MMU_SECONDARY_IDX;
 350     case PSW_ASC_HOME:
 351         return MMU_HOME_IDX;
 352     case PSW_ASC_ACCREG:
 353         /* Fallthrough: access register mode is not yet supported */
 354     default:
 355         abort();
 356     }
 357 }
 358
 359 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 360                                         target_ulong *cs_base, uint32_t *flags)
 361 {
 362     *pc = env->psw.addr;
 363     *cs_base = env->ex_value;
 364     *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
 365     if (env->cregs[0] & CR0_AFP) {
 366         *flags |= FLAG_MASK_AFP;
 367     }
 368     if (env->cregs[0] & CR0_VECTOR) {
 369         *flags |= FLAG_MASK_VECTOR;
 370     }
 371 }
 372
 373 /* PER bits from control register 9 */
 374 #define PER_CR9_EVENT_BRANCH           0x80000000
 375 #define PER_CR9_EVENT_IFETCH           0x40000000
 376 #define PER_CR9_EVENT_STORE            0x20000000
 377 #define PER_CR9_EVENT_STORE_REAL       0x08000000
 378 #define PER_CR9_EVENT_NULLIFICATION    0x01000000
 379 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 380 #define PER_CR9_CONTROL_ALTERATION     0x00200000
 381
 382 /* PER bits from the PER CODE/ATMID/AI in lowcore */
 383 #define PER_CODE_EVENT_BRANCH          0x8000
 384 #define PER_CODE_EVENT_IFETCH          0x4000
 385 #define PER_CODE_EVENT_STORE           0x2000
 386 #define PER_CODE_EVENT_STORE_REAL      0x0800
 387 #define PER_CODE_EVENT_NULLIFICATION   0x0100
 388
 389 #define EXCP_EXT 1 /* external interrupt */
 390 #define EXCP_SVC 2 /* supervisor call (syscall) */
 391 #define EXCP_PGM 3 /* program interruption */
 392 #define EXCP_RESTART 4 /* restart interrupt */
 393 #define EXCP_STOP 5 /* stop interrupt */
 394 #define EXCP_IO  7 /* I/O interrupt */
 395 #define EXCP_MCHK 8 /* machine check */
 396
 397 #define INTERRUPT_EXT_CPU_TIMER          (1 << 3)
 398 #define INTERRUPT_EXT_CLOCK_COMPARATOR   (1 << 4)
 399 #define INTERRUPT_EXTERNAL_CALL          (1 << 5)
 400 #define INTERRUPT_EMERGENCY_SIGNAL       (1 << 6)
 401 #define INTERRUPT_RESTART                (1 << 7)
 402 #define INTERRUPT_STOP                   (1 << 8)
 403
 404 /* Program Status Word.  */
 405 #define S390_PSWM_REGNUM 0
 406 #define S390_PSWA_REGNUM 1
 407 /* General Purpose Registers.  */
 408 #define S390_R0_REGNUM 2
 409 #define S390_R1_REGNUM 3
 410 #define S390_R2_REGNUM 4
 411 #define S390_R3_REGNUM 5
 412 #define S390_R4_REGNUM 6
 413 #define S390_R5_REGNUM 7
 414 #define S390_R6_REGNUM 8
 415 #define S390_R7_REGNUM 9
 416 #define S390_R8_REGNUM 10
 417 #define S390_R9_REGNUM 11
 418 #define S390_R10_REGNUM 12
 419 #define S390_R11_REGNUM 13
 420 #define S390_R12_REGNUM 14
 421 #define S390_R13_REGNUM 15
 422 #define S390_R14_REGNUM 16
 423 #define S390_R15_REGNUM 17
 424 /* Total Core Registers. */
 425 #define S390_NUM_CORE_REGS 18
 426
 427 static inline void setcc(S390CPU *cpu, uint64_t cc)
 428 {
 429     CPUS390XState *env = &cpu->env;
 430
 431     env->psw.mask &= ~(3ull << 44);
 432     env->psw.mask |= (cc & 3) << 44;
 433     env->cc_op = cc;
 434 }
 435
 436 /* STSI */
 437 #define STSI_R0_FC_MASK         0x00000000f0000000ULL
 438 #define STSI_R0_FC_CURRENT      0x0000000000000000ULL
 439 #define STSI_R0_FC_LEVEL_1      0x0000000010000000ULL
 440 #define STSI_R0_FC_LEVEL_2      0x0000000020000000ULL
 441 #define STSI_R0_FC_LEVEL_3      0x0000000030000000ULL
 442 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 443 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 444 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 445 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 446
 447 /* Basic Machine Configuration */
 448 typedef struct SysIB_111 {
 449     uint8_t  res1[32];
 450     uint8_t  manuf[16];
 451     uint8_t  type[4];
 452     uint8_t  res2[12];
 453     uint8_t  model[16];
 454     uint8_t  sequence[16];
 455     uint8_t  plant[4];
 456     uint8_t  res3[3996];
 457 } SysIB_111;
 458 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
 459
 460 /* Basic Machine CPU */
 461 typedef struct SysIB_121 {
 462     uint8_t  res1[80];
 463     uint8_t  sequence[16];
 464     uint8_t  plant[4];
 465     uint8_t  res2[2];
 466     uint16_t cpu_addr;
 467     uint8_t  res3[3992];
 468 } SysIB_121;
 469 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
 470
 471 /* Basic Machine CPUs */
 472 typedef struct SysIB_122 {
 473     uint8_t res1[32];
 474     uint32_t capability;
 475     uint16_t total_cpus;
 476     uint16_t conf_cpus;
 477     uint16_t standby_cpus;
 478     uint16_t reserved_cpus;
 479     uint16_t adjustments[2026];
 480 } SysIB_122;
 481 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
 482
 483 /* LPAR CPU */
 484 typedef struct SysIB_221 {
 485     uint8_t  res1[80];
 486     uint8_t  sequence[16];
 487     uint8_t  plant[4];
 488     uint16_t cpu_id;
 489     uint16_t cpu_addr;
 490     uint8_t  res3[3992];
 491 } SysIB_221;
 492 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
 493
 494 /* LPAR CPUs */
 495 typedef struct SysIB_222 {
 496     uint8_t  res1[32];
 497     uint16_t lpar_num;
 498     uint8_t  res2;
 499     uint8_t  lcpuc;
 500     uint16_t total_cpus;
 501     uint16_t conf_cpus;
 502     uint16_t standby_cpus;
 503     uint16_t reserved_cpus;
 504     uint8_t  name[8];
 505     uint32_t caf;
 506     uint8_t  res3[16];
 507     uint16_t dedicated_cpus;
 508     uint16_t shared_cpus;
 509     uint8_t  res4[4020];
 510 } SysIB_222;
 511 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
 512
 513 /* VM CPUs */
 514 typedef struct SysIB_322 {
 515     uint8_t  res1[31];
 516     uint8_t  count;
 517     struct {
 518         uint8_t  res2[4];
 519         uint16_t total_cpus;
 520         uint16_t conf_cpus;
 521         uint16_t standby_cpus;
 522         uint16_t reserved_cpus;
 523         uint8_t  name[8];
 524         uint32_t caf;
 525         uint8_t  cpi[16];
 526         uint8_t res5[3];
 527         uint8_t ext_name_encoding;
 528         uint32_t res3;
 529         uint8_t uuid[16];
 530     } vm[8];
 531     uint8_t res4[1504];
 532     uint8_t ext_names[8][256];
 533 } SysIB_322;
 534 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
 535
 536 typedef union SysIB {
 537     SysIB_111 sysib_111;
 538     SysIB_121 sysib_121;
 539     SysIB_122 sysib_122;
 540     SysIB_221 sysib_221;
 541     SysIB_222 sysib_222;
 542     SysIB_322 sysib_322;
 543 } SysIB;
 544 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
 545
 546 /* MMU defines */
 547 #define ASCE_ORIGIN           (~0xfffULL) /* segment table origin             */
 548 #define ASCE_SUBSPACE         0x200       /* subspace group control           */
 549 #define ASCE_PRIVATE_SPACE    0x100       /* private space control            */
 550 #define ASCE_ALT_EVENT        0x80        /* storage alteration event control */
 551 #define ASCE_SPACE_SWITCH     0x40        /* space switch event               */
 552 #define ASCE_REAL_SPACE       0x20        /* real space control               */
 553 #define ASCE_TYPE_MASK        0x0c        /* asce table type mask             */
 554 #define ASCE_TYPE_REGION1     0x0c        /* region first table type          */
 555 #define ASCE_TYPE_REGION2     0x08        /* region second table type         */
 556 #define ASCE_TYPE_REGION3     0x04        /* region third table type          */
 557 #define ASCE_TYPE_SEGMENT     0x00        /* segment table type               */
 558 #define ASCE_TABLE_LENGTH     0x03        /* region table length              */
 559
 560 #define REGION_ENTRY_ORIGIN   (~0xfffULL) /* region/segment table origin    */
 561 #define REGION_ENTRY_RO       0x200       /* region/segment protection bit  */
 562 #define REGION_ENTRY_TF       0xc0        /* region/segment table offset    */
 563 #define REGION_ENTRY_INV      0x20        /* invalid region table entry     */
 564 #define REGION_ENTRY_TYPE_MASK 0x0c       /* region/segment table type mask */
 565 #define REGION_ENTRY_TYPE_R1  0x0c        /* region first table type        */
 566 #define REGION_ENTRY_TYPE_R2  0x08        /* region second table type       */
 567 #define REGION_ENTRY_TYPE_R3  0x04        /* region third table type        */
 568 #define REGION_ENTRY_LENGTH   0x03        /* region third length            */
 569
 570 #define SEGMENT_ENTRY_ORIGIN  (~0x7ffULL) /* segment table origin        */
 571 #define SEGMENT_ENTRY_FC      0x400       /* format control              */
 572 #define SEGMENT_ENTRY_RO      0x200       /* page protection bit         */
 573 #define SEGMENT_ENTRY_INV     0x20        /* invalid segment table entry */
 574
 575 #define VADDR_PX              0xff000     /* page index bits   */
 576
 577 #define PAGE_RO               0x200       /* HW read-only bit  */
 578 #define PAGE_INVALID          0x400       /* HW invalid bit    */
 579 #define PAGE_RES0             0x800       /* bit must be zero  */
 580
 581 #define SK_C                    (0x1 << 1)
 582 #define SK_R                    (0x1 << 2)
 583 #define SK_F                    (0x1 << 3)
 584 #define SK_ACC_MASK             (0xf << 4)
 585
 586 /* SIGP order codes */
 587 #define SIGP_SENSE             0x01
 588 #define SIGP_EXTERNAL_CALL     0x02
 589 #define SIGP_EMERGENCY         0x03
 590 #define SIGP_START             0x04
 591 #define SIGP_STOP              0x05
 592 #define SIGP_RESTART           0x06
 593 #define SIGP_STOP_STORE_STATUS 0x09
 594 #define SIGP_INITIAL_CPU_RESET 0x0b
 595 #define SIGP_CPU_RESET         0x0c
 596 #define SIGP_SET_PREFIX        0x0d
 597 #define SIGP_STORE_STATUS_ADDR 0x0e
 598 #define SIGP_SET_ARCH          0x12
 599 #define SIGP_COND_EMERGENCY    0x13
 600 #define SIGP_SENSE_RUNNING     0x15
 601 #define SIGP_STORE_ADTL_STATUS 0x17
 602
 603 /* SIGP condition codes */
 604 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
 605 #define SIGP_CC_STATUS_STORED       1
 606 #define SIGP_CC_BUSY                2
 607 #define SIGP_CC_NOT_OPERATIONAL     3
 608
 609 /* SIGP status bits */
 610 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 611 #define SIGP_STAT_NOT_RUNNING       0x00000400UL
 612 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 613 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 614 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 615 #define SIGP_STAT_STOPPED           0x00000040UL
 616 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 617 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 618 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 619 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 620 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 621
 622 /* SIGP SET ARCHITECTURE modes */
 623 #define SIGP_MODE_ESA_S390 0
 624 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
 625 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
 626
 627 /* SIGP order code mask corresponding to bit positions 56-63 */
 628 #define SIGP_ORDER_MASK 0x000000ff
 629
 630 /* machine check interruption code */
 631
 632 /* subclasses */
 633 #define MCIC_SC_SD 0x8000000000000000ULL
 634 #define MCIC_SC_PD 0x4000000000000000ULL
 635 #define MCIC_SC_SR 0x2000000000000000ULL
 636 #define MCIC_SC_CD 0x0800000000000000ULL
 637 #define MCIC_SC_ED 0x0400000000000000ULL
 638 #define MCIC_SC_DG 0x0100000000000000ULL
 639 #define MCIC_SC_W  0x0080000000000000ULL
 640 #define MCIC_SC_CP 0x0040000000000000ULL
 641 #define MCIC_SC_SP 0x0020000000000000ULL
 642 #define MCIC_SC_CK 0x0010000000000000ULL
 643
 644 /* subclass modifiers */
 645 #define MCIC_SCM_B  0x0002000000000000ULL
 646 #define MCIC_SCM_DA 0x0000000020000000ULL
 647 #define MCIC_SCM_AP 0x0000000000080000ULL
 648
 649 /* storage errors */
 650 #define MCIC_SE_SE 0x0000800000000000ULL
 651 #define MCIC_SE_SC 0x0000400000000000ULL
 652 #define MCIC_SE_KE 0x0000200000000000ULL
 653 #define MCIC_SE_DS 0x0000100000000000ULL
 654 #define MCIC_SE_IE 0x0000000080000000ULL
 655
 656 /* validity bits */
 657 #define MCIC_VB_WP 0x0000080000000000ULL
 658 #define MCIC_VB_MS 0x0000040000000000ULL
 659 #define MCIC_VB_PM 0x0000020000000000ULL
 660 #define MCIC_VB_IA 0x0000010000000000ULL
 661 #define MCIC_VB_FA 0x0000008000000000ULL
 662 #define MCIC_VB_VR 0x0000004000000000ULL
 663 #define MCIC_VB_EC 0x0000002000000000ULL
 664 #define MCIC_VB_FP 0x0000001000000000ULL
 665 #define MCIC_VB_GR 0x0000000800000000ULL
 666 #define MCIC_VB_CR 0x0000000400000000ULL
 667 #define MCIC_VB_ST 0x0000000100000000ULL
 668 #define MCIC_VB_AR 0x0000000040000000ULL
 669 #define MCIC_VB_GS 0x0000000008000000ULL
 670 #define MCIC_VB_PR 0x0000000000200000ULL
 671 #define MCIC_VB_FC 0x0000000000100000ULL
 672 #define MCIC_VB_CT 0x0000000000020000ULL
 673 #define MCIC_VB_CC 0x0000000000010000ULL
 674
 675 static inline uint64_t s390_build_validity_mcic(void)
 676 {
 677     uint64_t mcic;
 678
 679     /*
 680      * Indicate all validity bits (no damage) only. Other bits have to be
 681      * added by the caller. (storage errors, subclasses and subclass modifiers)
 682      */
 683     mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
 684            MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
 685            MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
 686     if (s390_has_feat(S390_FEAT_VECTOR)) {
 687         mcic |= MCIC_VB_VR;
 688     }
 689     if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
 690         mcic |= MCIC_VB_GS;
 691     }
 692     return mcic;
 693 }
 694
 695 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
 696 {
 697     cpu_reset(cs);
 698 }
 699
 700 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
 701 {
 702     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 703
 704     scc->cpu_reset(cs);
 705 }
 706
 707 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
 708 {
 709     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 710
 711     scc->initial_cpu_reset(cs);
 712 }
 713
 714 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
 715 {
 716     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 717
 718     scc->load_normal(cs);
 719 }
 720
 721
 722 /* cpu.c */
 723 void s390_crypto_reset(void);
 724 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
 725 void s390_set_max_pagesize(uint64_t pagesize, Error **errp);
 726 void s390_cmma_reset(void);
 727 void s390_enable_css_support(S390CPU *cpu);
 728 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
 729                                 int vq, bool assign);
 730 #ifndef CONFIG_USER_ONLY
 731 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 732 #else
 733 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 734 {
 735     return 0;
 736 }
 737 #endif /* CONFIG_USER_ONLY */
 738 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 739 {
 740     return cpu->env.cpu_state;
 741 }
 742
 743
 744 /* cpu_models.c */
 745 void s390_cpu_list(void);
 746 #define cpu_list s390_cpu_list
 747 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
 748                              const S390FeatInit feat_init);
 749
 750
 751 /* helper.c */
 752 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
 753 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
 754 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
 755
 756 /* you can call this signal handler from your SIGBUS and SIGSEGV
 757    signal handlers to inform the virtual CPU of exceptions. non zero
 758    is returned if the signal was handled by the virtual CPU.  */
 759 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
 760 #define cpu_signal_handler cpu_s390x_signal_handler
 761
 762
 763 /* interrupt.c */
 764 void s390_crw_mchk(void);
 765 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
 766                        uint32_t io_int_parm, uint32_t io_int_word);
 767 /* automatically detect the instruction length */
 768 #define ILEN_AUTO                   0xff
 769 #define RA_IGNORED                  0
 770 void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen,
 771                             uintptr_t ra);
 772 /* service interrupts are floating therefore we must not pass an cpustate */
 773 void s390_sclp_extint(uint32_t parm);
 774
 775 /* mmu_helper.c */
 776 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 777                          int len, bool is_write);
 778 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
 779         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
 780 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
 781         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
 782 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len)   \
 783         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
 784 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
 785         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
 786 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
 787
 788
 789 /* sigp.c */
 790 int s390_cpu_restart(S390CPU *cpu);
 791 void s390_init_sigp(void);
 792
 793
 794 /* outside of target/s390x/ */
 795 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 796
 797 typedef CPUS390XState CPUArchState;
 798 typedef S390CPU ArchCPU;
 799
 800 #include "exec/cpu-all.h"
 801
 802 #endif