]>
git.proxmox.com Git - mirror_qemu.git/blob - target/s390x/ioinst.c
2 * I/O instructions for S/390
4 * Copyright 2012, 2015 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
12 #include "qemu/osdep.h"
15 #include "hw/s390x/ioinst.h"
17 #include "hw/s390x/s390-pci-bus.h"
19 int ioinst_disassemble_sch_ident(uint32_t value
, int *m
, int *cssid
, int *ssid
,
22 if (!IOINST_SCHID_ONE(value
)) {
25 if (!IOINST_SCHID_M(value
)) {
26 if (IOINST_SCHID_CSSID(value
)) {
32 *cssid
= IOINST_SCHID_CSSID(value
);
35 *ssid
= IOINST_SCHID_SSID(value
);
36 *schid
= IOINST_SCHID_NR(value
);
40 void ioinst_handle_xsch(S390CPU
*cpu
, uint64_t reg1
)
42 int cssid
, ssid
, schid
, m
;
47 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
48 program_interrupt(&cpu
->env
, PGM_OPERAND
, 2);
51 trace_ioinst_sch_id("xsch", cssid
, ssid
, schid
);
52 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
53 if (sch
&& css_subch_visible(sch
)) {
54 ret
= css_do_xsch(sch
);
73 void ioinst_handle_csch(S390CPU
*cpu
, uint64_t reg1
)
75 int cssid
, ssid
, schid
, m
;
80 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
81 program_interrupt(&cpu
->env
, PGM_OPERAND
, 2);
84 trace_ioinst_sch_id("csch", cssid
, ssid
, schid
);
85 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
86 if (sch
&& css_subch_visible(sch
)) {
87 ret
= css_do_csch(sch
);
97 void ioinst_handle_hsch(S390CPU
*cpu
, uint64_t reg1
)
99 int cssid
, ssid
, schid
, m
;
104 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
105 program_interrupt(&cpu
->env
, PGM_OPERAND
, 2);
108 trace_ioinst_sch_id("hsch", cssid
, ssid
, schid
);
109 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
110 if (sch
&& css_subch_visible(sch
)) {
111 ret
= css_do_hsch(sch
);
130 static int ioinst_schib_valid(SCHIB
*schib
)
132 if ((be16_to_cpu(schib
->pmcw
.flags
) & PMCW_FLAGS_MASK_INVALID
) ||
133 (be32_to_cpu(schib
->pmcw
.chars
) & PMCW_CHARS_MASK_INVALID
)) {
136 /* Disallow extended measurements for now. */
137 if (be32_to_cpu(schib
->pmcw
.chars
) & PMCW_CHARS_MASK_XMWME
) {
143 void ioinst_handle_msch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
)
145 int cssid
, ssid
, schid
, m
;
151 CPUS390XState
*env
= &cpu
->env
;
154 addr
= decode_basedisp_s(env
, ipb
, &ar
);
156 program_interrupt(env
, PGM_SPECIFICATION
, 2);
159 if (s390_cpu_virt_mem_read(cpu
, addr
, ar
, &schib
, sizeof(schib
))) {
162 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
) ||
163 !ioinst_schib_valid(&schib
)) {
164 program_interrupt(env
, PGM_OPERAND
, 2);
167 trace_ioinst_sch_id("msch", cssid
, ssid
, schid
);
168 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
169 if (sch
&& css_subch_visible(sch
)) {
170 ret
= css_do_msch(sch
, &schib
);
189 static void copy_orb_from_guest(ORB
*dest
, const ORB
*src
)
191 dest
->intparm
= be32_to_cpu(src
->intparm
);
192 dest
->ctrl0
= be16_to_cpu(src
->ctrl0
);
193 dest
->lpm
= src
->lpm
;
194 dest
->ctrl1
= src
->ctrl1
;
195 dest
->cpa
= be32_to_cpu(src
->cpa
);
198 static int ioinst_orb_valid(ORB
*orb
)
200 if ((orb
->ctrl0
& ORB_CTRL0_MASK_INVALID
) ||
201 (orb
->ctrl1
& ORB_CTRL1_MASK_INVALID
)) {
204 /* We don't support MIDA. */
205 if (orb
->ctrl1
& ORB_CTRL1_MASK_MIDAW
) {
208 if ((orb
->cpa
& HIGH_ORDER_BIT
) != 0) {
214 void ioinst_handle_ssch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
)
216 int cssid
, ssid
, schid
, m
;
222 CPUS390XState
*env
= &cpu
->env
;
225 addr
= decode_basedisp_s(env
, ipb
, &ar
);
227 program_interrupt(env
, PGM_SPECIFICATION
, 2);
230 if (s390_cpu_virt_mem_read(cpu
, addr
, ar
, &orig_orb
, sizeof(orb
))) {
233 copy_orb_from_guest(&orb
, &orig_orb
);
234 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
) ||
235 !ioinst_orb_valid(&orb
)) {
236 program_interrupt(env
, PGM_OPERAND
, 2);
239 trace_ioinst_sch_id("ssch", cssid
, ssid
, schid
);
240 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
241 if (sch
&& css_subch_visible(sch
)) {
242 ret
= css_do_ssch(sch
, &orb
);
254 * I'm wondering whether there is something better
255 * to do for us here (like setting some device or
256 * subchannel status).
258 program_interrupt(env
, PGM_ADDRESSING
, 4);
270 void ioinst_handle_stcrw(S390CPU
*cpu
, uint32_t ipb
)
275 CPUS390XState
*env
= &cpu
->env
;
278 addr
= decode_basedisp_s(env
, ipb
, &ar
);
280 program_interrupt(env
, PGM_SPECIFICATION
, 2);
284 cc
= css_do_stcrw(&crw
);
285 /* 0 - crw stored, 1 - zeroes stored */
287 if (s390_cpu_virt_mem_write(cpu
, addr
, ar
, &crw
, sizeof(crw
)) == 0) {
289 } else if (cc
== 0) {
290 /* Write failed: requeue CRW since STCRW is a suppressing instruction */
291 css_undo_stcrw(&crw
);
295 void ioinst_handle_stsch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
)
297 int cssid
, ssid
, schid
, m
;
302 CPUS390XState
*env
= &cpu
->env
;
305 addr
= decode_basedisp_s(env
, ipb
, &ar
);
307 program_interrupt(env
, PGM_SPECIFICATION
, 2);
311 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
313 * As operand exceptions have a lower priority than access exceptions,
314 * we check whether the memory area is writeable (injecting the
315 * access execption if it is not) first.
317 if (!s390_cpu_virt_mem_check_write(cpu
, addr
, ar
, sizeof(schib
))) {
318 program_interrupt(env
, PGM_OPERAND
, 2);
322 trace_ioinst_sch_id("stsch", cssid
, ssid
, schid
);
323 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
325 if (css_subch_visible(sch
)) {
326 css_do_stsch(sch
, &schib
);
329 /* Indicate no more subchannels in this css/ss */
333 if (css_schid_final(m
, cssid
, ssid
, schid
)) {
334 cc
= 3; /* No more subchannels in this css/ss */
336 /* Store an empty schib. */
337 memset(&schib
, 0, sizeof(schib
));
342 if (s390_cpu_virt_mem_write(cpu
, addr
, ar
, &schib
,
343 sizeof(schib
)) != 0) {
347 /* Access exceptions have a higher priority than cc3 */
348 if (s390_cpu_virt_mem_check_write(cpu
, addr
, ar
, sizeof(schib
)) != 0) {
355 int ioinst_handle_tsch(S390CPU
*cpu
, uint64_t reg1
, uint32_t ipb
)
357 CPUS390XState
*env
= &cpu
->env
;
358 int cssid
, ssid
, schid
, m
;
365 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
366 program_interrupt(env
, PGM_OPERAND
, 2);
369 trace_ioinst_sch_id("tsch", cssid
, ssid
, schid
);
370 addr
= decode_basedisp_s(env
, ipb
, &ar
);
372 program_interrupt(env
, PGM_SPECIFICATION
, 2);
376 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
377 if (sch
&& css_subch_visible(sch
)) {
378 cc
= css_do_tsch_get_irb(sch
, &irb
, &irb_len
);
382 /* 0 - status pending, 1 - not status pending, 3 - not operational */
384 if (s390_cpu_virt_mem_write(cpu
, addr
, ar
, &irb
, irb_len
) != 0) {
387 css_do_tsch_update_subch(sch
);
389 irb_len
= sizeof(irb
) - sizeof(irb
.emw
);
390 /* Access exceptions have a higher priority than cc3 */
391 if (s390_cpu_virt_mem_check_write(cpu
, addr
, ar
, irb_len
) != 0) {
400 typedef struct ChscReq
{
406 } QEMU_PACKED ChscReq
;
408 typedef struct ChscResp
{
413 } QEMU_PACKED ChscResp
;
415 #define CHSC_MIN_RESP_LEN 0x0008
417 #define CHSC_SCPD 0x0002
418 #define CHSC_SCSC 0x0010
419 #define CHSC_SDA 0x0031
420 #define CHSC_SEI 0x000e
422 #define CHSC_SCPD_0_M 0x20000000
423 #define CHSC_SCPD_0_C 0x10000000
424 #define CHSC_SCPD_0_FMT 0x0f000000
425 #define CHSC_SCPD_0_CSSID 0x00ff0000
426 #define CHSC_SCPD_0_RFMT 0x00000f00
427 #define CHSC_SCPD_0_RES 0xc000f000
428 #define CHSC_SCPD_1_RES 0xffffff00
429 #define CHSC_SCPD_01_CHPID 0x000000ff
430 static void ioinst_handle_chsc_scpd(ChscReq
*req
, ChscResp
*res
)
432 uint16_t len
= be16_to_cpu(req
->len
);
433 uint32_t param0
= be32_to_cpu(req
->param0
);
434 uint32_t param1
= be32_to_cpu(req
->param1
);
438 uint8_t f_chpid
, l_chpid
;
442 rfmt
= (param0
& CHSC_SCPD_0_RFMT
) >> 8;
443 if ((rfmt
== 0) || (rfmt
== 1)) {
444 rfmt
= !!(param0
& CHSC_SCPD_0_C
);
446 if ((len
!= 0x0010) || (param0
& CHSC_SCPD_0_RES
) ||
447 (param1
& CHSC_SCPD_1_RES
) || req
->param2
) {
451 if (param0
& CHSC_SCPD_0_FMT
) {
455 cssid
= (param0
& CHSC_SCPD_0_CSSID
) >> 16;
456 m
= param0
& CHSC_SCPD_0_M
;
458 if (!m
|| !css_present(cssid
)) {
463 f_chpid
= param0
& CHSC_SCPD_01_CHPID
;
464 l_chpid
= param1
& CHSC_SCPD_01_CHPID
;
465 if (l_chpid
< f_chpid
) {
469 /* css_collect_chp_desc() is endian-aware */
470 desc_size
= css_collect_chp_desc(m
, cssid
, f_chpid
, l_chpid
, rfmt
,
472 res
->code
= cpu_to_be16(0x0001);
473 res
->len
= cpu_to_be16(8 + desc_size
);
474 res
->param
= cpu_to_be32(rfmt
);
478 res
->code
= cpu_to_be16(resp_code
);
479 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
480 res
->param
= cpu_to_be32(rfmt
);
483 #define CHSC_SCSC_0_M 0x20000000
484 #define CHSC_SCSC_0_FMT 0x000f0000
485 #define CHSC_SCSC_0_CSSID 0x0000ff00
486 #define CHSC_SCSC_0_RES 0xdff000ff
487 static void ioinst_handle_chsc_scsc(ChscReq
*req
, ChscResp
*res
)
489 uint16_t len
= be16_to_cpu(req
->len
);
490 uint32_t param0
= be32_to_cpu(req
->param0
);
493 uint32_t general_chars
[510];
494 uint32_t chsc_chars
[508];
501 if (param0
& CHSC_SCSC_0_FMT
) {
505 cssid
= (param0
& CHSC_SCSC_0_CSSID
) >> 8;
507 if (!(param0
& CHSC_SCSC_0_M
) || !css_present(cssid
)) {
512 if ((param0
& CHSC_SCSC_0_RES
) || req
->param1
|| req
->param2
) {
516 res
->code
= cpu_to_be16(0x0001);
517 res
->len
= cpu_to_be16(4080);
520 memset(general_chars
, 0, sizeof(general_chars
));
521 memset(chsc_chars
, 0, sizeof(chsc_chars
));
523 general_chars
[0] = cpu_to_be32(0x03000000);
524 general_chars
[1] = cpu_to_be32(0x00079000);
525 general_chars
[3] = cpu_to_be32(0x00080000);
527 chsc_chars
[0] = cpu_to_be32(0x40000000);
528 chsc_chars
[3] = cpu_to_be32(0x00040000);
530 memcpy(res
->data
, general_chars
, sizeof(general_chars
));
531 memcpy(res
->data
+ sizeof(general_chars
), chsc_chars
, sizeof(chsc_chars
));
535 res
->code
= cpu_to_be16(resp_code
);
536 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
540 #define CHSC_SDA_0_FMT 0x0f000000
541 #define CHSC_SDA_0_OC 0x0000ffff
542 #define CHSC_SDA_0_RES 0xf0ff0000
543 #define CHSC_SDA_OC_MCSSE 0x0
544 #define CHSC_SDA_OC_MSS 0x2
545 static void ioinst_handle_chsc_sda(ChscReq
*req
, ChscResp
*res
)
547 uint16_t resp_code
= 0x0001;
548 uint16_t len
= be16_to_cpu(req
->len
);
549 uint32_t param0
= be32_to_cpu(req
->param0
);
553 if ((len
!= 0x0400) || (param0
& CHSC_SDA_0_RES
)) {
558 if (param0
& CHSC_SDA_0_FMT
) {
563 oc
= param0
& CHSC_SDA_0_OC
;
565 case CHSC_SDA_OC_MCSSE
:
566 ret
= css_enable_mcsse();
567 if (ret
== -EINVAL
) {
572 case CHSC_SDA_OC_MSS
:
573 ret
= css_enable_mss();
574 if (ret
== -EINVAL
) {
585 res
->code
= cpu_to_be16(resp_code
);
586 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
590 static int chsc_sei_nt0_get_event(void *res
)
596 static int chsc_sei_nt0_have_event(void)
602 #define CHSC_SEI_NT0 (1ULL << 63)
603 #define CHSC_SEI_NT2 (1ULL << 61)
604 static void ioinst_handle_chsc_sei(ChscReq
*req
, ChscResp
*res
)
606 uint64_t selection_mask
= ldq_p(&req
->param1
);
607 uint8_t *res_flags
= (uint8_t *)res
->data
;
611 /* regarding architecture nt0 can not be masked */
612 have_event
= !chsc_sei_nt0_get_event(res
);
613 have_more
= chsc_sei_nt0_have_event();
615 if (selection_mask
& CHSC_SEI_NT2
) {
617 have_event
= !chsc_sei_nt2_get_event(res
);
621 have_more
= chsc_sei_nt2_have_event();
626 res
->code
= cpu_to_be16(0x0001);
628 (*res_flags
) |= 0x80;
630 (*res_flags
) &= ~0x80;
631 css_clear_sei_pending();
634 res
->code
= cpu_to_be16(0x0005);
635 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
639 static void ioinst_handle_chsc_unimplemented(ChscResp
*res
)
641 res
->len
= cpu_to_be16(CHSC_MIN_RESP_LEN
);
642 res
->code
= cpu_to_be16(0x0004);
646 void ioinst_handle_chsc(S390CPU
*cpu
, uint32_t ipb
)
654 CPUS390XState
*env
= &cpu
->env
;
655 uint8_t buf
[TARGET_PAGE_SIZE
];
657 trace_ioinst("chsc");
658 reg
= (ipb
>> 20) & 0x00f;
659 addr
= env
->regs
[reg
];
662 program_interrupt(env
, PGM_SPECIFICATION
, 2);
666 * Reading sizeof(ChscReq) bytes is currently enough for all of our
667 * present CHSC sub-handlers ... if we ever need more, we should take
668 * care of req->len here first.
670 if (s390_cpu_virt_mem_read(cpu
, addr
, reg
, buf
, sizeof(ChscReq
))) {
673 req
= (ChscReq
*)buf
;
674 len
= be16_to_cpu(req
->len
);
675 /* Length field valid? */
676 if ((len
< 16) || (len
> 4088) || (len
& 7)) {
677 program_interrupt(env
, PGM_OPERAND
, 2);
680 memset((char *)req
+ len
, 0, TARGET_PAGE_SIZE
- len
);
681 res
= (void *)((char *)req
+ len
);
682 command
= be16_to_cpu(req
->command
);
683 trace_ioinst_chsc_cmd(command
, len
);
686 ioinst_handle_chsc_scsc(req
, res
);
689 ioinst_handle_chsc_scpd(req
, res
);
692 ioinst_handle_chsc_sda(req
, res
);
695 ioinst_handle_chsc_sei(req
, res
);
698 ioinst_handle_chsc_unimplemented(res
);
702 if (!s390_cpu_virt_mem_write(cpu
, addr
+ len
, reg
, res
,
703 be16_to_cpu(res
->len
))) {
704 setcc(cpu
, 0); /* Command execution complete */
708 int ioinst_handle_tpi(S390CPU
*cpu
, uint32_t ipb
)
710 CPUS390XState
*env
= &cpu
->env
;
719 addr
= decode_basedisp_s(env
, ipb
, &ar
);
721 program_interrupt(env
, PGM_SPECIFICATION
, 2);
725 lowcore
= addr
? 0 : 1;
726 len
= lowcore
? 8 /* two words */ : 12 /* three words */;
727 ret
= css_do_tpi(&int_code
, lowcore
);
729 s390_cpu_virt_mem_write(cpu
, lowcore
? 184 : addr
, ar
, &int_code
, len
);
734 #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
735 #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
736 #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
737 #define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
739 void ioinst_handle_schm(S390CPU
*cpu
, uint64_t reg1
, uint64_t reg2
,
745 CPUS390XState
*env
= &cpu
->env
;
747 trace_ioinst("schm");
749 if (SCHM_REG1_RES(reg1
)) {
750 program_interrupt(env
, PGM_OPERAND
, 2);
754 mbk
= SCHM_REG1_MBK(reg1
);
755 update
= SCHM_REG1_UPD(reg1
);
756 dct
= SCHM_REG1_DCT(reg1
);
758 if (update
&& (reg2
& 0x000000000000001f)) {
759 program_interrupt(env
, PGM_OPERAND
, 2);
763 css_do_schm(mbk
, update
, dct
, update
? reg2
: 0);
766 void ioinst_handle_rsch(S390CPU
*cpu
, uint64_t reg1
)
768 int cssid
, ssid
, schid
, m
;
773 if (ioinst_disassemble_sch_ident(reg1
, &m
, &cssid
, &ssid
, &schid
)) {
774 program_interrupt(&cpu
->env
, PGM_OPERAND
, 2);
777 trace_ioinst_sch_id("rsch", cssid
, ssid
, schid
);
778 sch
= css_find_subch(m
, cssid
, ssid
, schid
);
779 if (sch
&& css_subch_visible(sch
)) {
780 ret
= css_do_rsch(sch
);
799 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
800 #define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
801 #define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
802 void ioinst_handle_rchp(S390CPU
*cpu
, uint64_t reg1
)
808 CPUS390XState
*env
= &cpu
->env
;
810 if (RCHP_REG1_RES(reg1
)) {
811 program_interrupt(env
, PGM_OPERAND
, 2);
815 cssid
= RCHP_REG1_CSSID(reg1
);
816 chpid
= RCHP_REG1_CHPID(reg1
);
818 trace_ioinst_chp_id("rchp", cssid
, chpid
);
820 ret
= css_do_rchp(cssid
, chpid
);
833 /* Invalid channel subsystem. */
834 program_interrupt(env
, PGM_OPERAND
, 2);
840 #define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
841 void ioinst_handle_sal(S390CPU
*cpu
, uint64_t reg1
)
843 /* We do not provide address limit checking, so let's suppress it. */
844 if (SAL_REG1_INVALID(reg1
) || reg1
& 0x000000000000ffff) {
845 program_interrupt(&cpu
->env
, PGM_OPERAND
, 2);