4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
28 # define LOG_DISAS(...) do { } while (0)
31 #include "qemu/osdep.h"
33 #include "s390x-internal.h"
34 #include "disas/disas.h"
35 #include "exec/exec-all.h"
36 #include "tcg/tcg-op.h"
37 #include "tcg/tcg-op-gvec.h"
39 #include "qemu/host-utils.h"
40 #include "exec/cpu_ldst.h"
41 #include "exec/helper-proto.h"
42 #include "exec/helper-gen.h"
44 #include "exec/translator.h"
46 #include "qemu/atomic128.h"
48 #define HELPER_H "helper.h"
49 #include "exec/helper-info.c.inc"
53 /* Information that (most) every instruction needs to manipulate. */
54 typedef struct DisasContext DisasContext
;
55 typedef struct DisasInsn DisasInsn
;
56 typedef struct DisasFields DisasFields
;
59 * Define a structure to hold the decoded fields. We'll store each inside
60 * an array indexed by an enum. In order to conserve memory, we'll arrange
61 * for fields that do not exist at the same time to overlap, thus the "C"
62 * for compact. For checking purposes there is an "O" for original index
63 * as well that will be applied to availability bitmaps.
66 enum DisasFieldIndexO
{
95 enum DisasFieldIndexC
{
136 unsigned presentC
:16;
137 unsigned int presentO
;
141 struct DisasContext
{
142 DisasContextBase base
;
143 const DisasInsn
*insn
;
148 * During translate_one(), pc_tmp is used to determine the instruction
149 * to be executed after base.pc_next - e.g. next sequential instruction
150 * or a branch target.
155 bool exit_to_mainloop
;
158 /* Information carried about a condition to be evaluated. */
163 struct { TCGv_i64 a
, b
; } s64
;
164 struct { TCGv_i32 a
, b
; } s32
;
168 #ifdef DEBUG_INLINE_BRANCHES
169 static uint64_t inline_branch_hit
[CC_OP_MAX
];
170 static uint64_t inline_branch_miss
[CC_OP_MAX
];
173 static void pc_to_link_info(TCGv_i64 out
, DisasContext
*s
, uint64_t pc
)
175 if (s
->base
.tb
->flags
& FLAG_MASK_32
) {
176 if (s
->base
.tb
->flags
& FLAG_MASK_64
) {
177 tcg_gen_movi_i64(out
, pc
);
182 assert(!(s
->base
.tb
->flags
& FLAG_MASK_64
));
183 tcg_gen_deposit_i64(out
, out
, tcg_constant_i64(pc
), 0, 32);
186 static TCGv_i64 psw_addr
;
187 static TCGv_i64 psw_mask
;
188 static TCGv_i64 gbea
;
190 static TCGv_i32 cc_op
;
191 static TCGv_i64 cc_src
;
192 static TCGv_i64 cc_dst
;
193 static TCGv_i64 cc_vr
;
195 static char cpu_reg_names
[16][4];
196 static TCGv_i64 regs
[16];
198 void s390x_translate_init(void)
202 psw_addr
= tcg_global_mem_new_i64(tcg_env
,
203 offsetof(CPUS390XState
, psw
.addr
),
205 psw_mask
= tcg_global_mem_new_i64(tcg_env
,
206 offsetof(CPUS390XState
, psw
.mask
),
208 gbea
= tcg_global_mem_new_i64(tcg_env
,
209 offsetof(CPUS390XState
, gbea
),
212 cc_op
= tcg_global_mem_new_i32(tcg_env
, offsetof(CPUS390XState
, cc_op
),
214 cc_src
= tcg_global_mem_new_i64(tcg_env
, offsetof(CPUS390XState
, cc_src
),
216 cc_dst
= tcg_global_mem_new_i64(tcg_env
, offsetof(CPUS390XState
, cc_dst
),
218 cc_vr
= tcg_global_mem_new_i64(tcg_env
, offsetof(CPUS390XState
, cc_vr
),
221 for (i
= 0; i
< 16; i
++) {
222 snprintf(cpu_reg_names
[i
], sizeof(cpu_reg_names
[0]), "r%d", i
);
223 regs
[i
] = tcg_global_mem_new(tcg_env
,
224 offsetof(CPUS390XState
, regs
[i
]),
229 static inline int vec_full_reg_offset(uint8_t reg
)
232 return offsetof(CPUS390XState
, vregs
[reg
][0]);
235 static inline int vec_reg_offset(uint8_t reg
, uint8_t enr
, MemOp es
)
237 /* Convert element size (es) - e.g. MO_8 - to bytes */
238 const uint8_t bytes
= 1 << es
;
239 int offs
= enr
* bytes
;
242 * vregs[n][0] is the lowest 8 byte and vregs[n][1] the highest 8 byte
243 * of the 16 byte vector, on both, little and big endian systems.
245 * Big Endian (target/possible host)
246 * B: [ 0][ 1][ 2][ 3][ 4][ 5][ 6][ 7] - [ 8][ 9][10][11][12][13][14][15]
247 * HW: [ 0][ 1][ 2][ 3] - [ 4][ 5][ 6][ 7]
248 * W: [ 0][ 1] - [ 2][ 3]
251 * Little Endian (possible host)
252 * B: [ 7][ 6][ 5][ 4][ 3][ 2][ 1][ 0] - [15][14][13][12][11][10][ 9][ 8]
253 * HW: [ 3][ 2][ 1][ 0] - [ 7][ 6][ 5][ 4]
254 * W: [ 1][ 0] - [ 3][ 2]
257 * For 16 byte elements, the two 8 byte halves will not form a host
258 * int128 if the host is little endian, since they're in the wrong order.
259 * Some operations (e.g. xor) do not care. For operations like addition,
260 * the two 8 byte elements have to be loaded separately. Let's force all
261 * 16 byte operations to handle it in a special way.
263 g_assert(es
<= MO_64
);
267 return offs
+ vec_full_reg_offset(reg
);
270 static inline int freg64_offset(uint8_t reg
)
273 return vec_reg_offset(reg
, 0, MO_64
);
276 static inline int freg32_offset(uint8_t reg
)
279 return vec_reg_offset(reg
, 0, MO_32
);
282 static TCGv_i64
load_reg(int reg
)
284 TCGv_i64 r
= tcg_temp_new_i64();
285 tcg_gen_mov_i64(r
, regs
[reg
]);
289 static TCGv_i64
load_freg(int reg
)
291 TCGv_i64 r
= tcg_temp_new_i64();
293 tcg_gen_ld_i64(r
, tcg_env
, freg64_offset(reg
));
297 static TCGv_i64
load_freg32_i64(int reg
)
299 TCGv_i64 r
= tcg_temp_new_i64();
301 tcg_gen_ld32u_i64(r
, tcg_env
, freg32_offset(reg
));
305 static TCGv_i128
load_freg_128(int reg
)
307 TCGv_i64 h
= load_freg(reg
);
308 TCGv_i64 l
= load_freg(reg
+ 2);
309 TCGv_i128 r
= tcg_temp_new_i128();
311 tcg_gen_concat_i64_i128(r
, l
, h
);
315 static void store_reg(int reg
, TCGv_i64 v
)
317 tcg_gen_mov_i64(regs
[reg
], v
);
320 static void store_freg(int reg
, TCGv_i64 v
)
322 tcg_gen_st_i64(v
, tcg_env
, freg64_offset(reg
));
325 static void store_reg32_i64(int reg
, TCGv_i64 v
)
327 /* 32 bit register writes keep the upper half */
328 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 0, 32);
331 static void store_reg32h_i64(int reg
, TCGv_i64 v
)
333 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 32, 32);
336 static void store_freg32_i64(int reg
, TCGv_i64 v
)
338 tcg_gen_st32_i64(v
, tcg_env
, freg32_offset(reg
));
341 static void update_psw_addr(DisasContext
*s
)
344 tcg_gen_movi_i64(psw_addr
, s
->base
.pc_next
);
347 static void per_branch(DisasContext
*s
, bool to_next
)
349 #ifndef CONFIG_USER_ONLY
350 tcg_gen_movi_i64(gbea
, s
->base
.pc_next
);
352 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
353 TCGv_i64 next_pc
= to_next
? tcg_constant_i64(s
->pc_tmp
) : psw_addr
;
354 gen_helper_per_branch(tcg_env
, gbea
, next_pc
);
359 static void per_branch_cond(DisasContext
*s
, TCGCond cond
,
360 TCGv_i64 arg1
, TCGv_i64 arg2
)
362 #ifndef CONFIG_USER_ONLY
363 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
364 TCGLabel
*lab
= gen_new_label();
365 tcg_gen_brcond_i64(tcg_invert_cond(cond
), arg1
, arg2
, lab
);
367 tcg_gen_movi_i64(gbea
, s
->base
.pc_next
);
368 gen_helper_per_branch(tcg_env
, gbea
, psw_addr
);
372 TCGv_i64 pc
= tcg_constant_i64(s
->base
.pc_next
);
373 tcg_gen_movcond_i64(cond
, gbea
, arg1
, arg2
, gbea
, pc
);
378 static void per_breaking_event(DisasContext
*s
)
380 tcg_gen_movi_i64(gbea
, s
->base
.pc_next
);
383 static void update_cc_op(DisasContext
*s
)
385 if (s
->cc_op
!= CC_OP_DYNAMIC
&& s
->cc_op
!= CC_OP_STATIC
) {
386 tcg_gen_movi_i32(cc_op
, s
->cc_op
);
390 static inline uint64_t ld_code2(CPUS390XState
*env
, DisasContext
*s
,
393 return (uint64_t)translator_lduw(env
, &s
->base
, pc
);
396 static inline uint64_t ld_code4(CPUS390XState
*env
, DisasContext
*s
,
399 return (uint64_t)(uint32_t)translator_ldl(env
, &s
->base
, pc
);
402 static int get_mem_index(DisasContext
*s
)
404 #ifdef CONFIG_USER_ONLY
407 if (!(s
->base
.tb
->flags
& FLAG_MASK_DAT
)) {
411 switch (s
->base
.tb
->flags
& FLAG_MASK_ASC
) {
412 case PSW_ASC_PRIMARY
>> FLAG_MASK_PSW_SHIFT
:
413 return MMU_PRIMARY_IDX
;
414 case PSW_ASC_SECONDARY
>> FLAG_MASK_PSW_SHIFT
:
415 return MMU_SECONDARY_IDX
;
416 case PSW_ASC_HOME
>> FLAG_MASK_PSW_SHIFT
:
419 g_assert_not_reached();
425 static void gen_exception(int excp
)
427 gen_helper_exception(tcg_env
, tcg_constant_i32(excp
));
430 static void gen_program_exception(DisasContext
*s
, int code
)
432 /* Remember what pgm exception this was. */
433 tcg_gen_st_i32(tcg_constant_i32(code
), tcg_env
,
434 offsetof(CPUS390XState
, int_pgm_code
));
436 tcg_gen_st_i32(tcg_constant_i32(s
->ilen
), tcg_env
,
437 offsetof(CPUS390XState
, int_pgm_ilen
));
445 /* Trigger exception. */
446 gen_exception(EXCP_PGM
);
449 static inline void gen_illegal_opcode(DisasContext
*s
)
451 gen_program_exception(s
, PGM_OPERATION
);
454 static inline void gen_data_exception(uint8_t dxc
)
456 gen_helper_data_exception(tcg_env
, tcg_constant_i32(dxc
));
459 static inline void gen_trap(DisasContext
*s
)
461 /* Set DXC to 0xff */
462 gen_data_exception(0xff);
465 static void gen_addi_and_wrap_i64(DisasContext
*s
, TCGv_i64 dst
, TCGv_i64 src
,
468 tcg_gen_addi_i64(dst
, src
, imm
);
469 if (!(s
->base
.tb
->flags
& FLAG_MASK_64
)) {
470 if (s
->base
.tb
->flags
& FLAG_MASK_32
) {
471 tcg_gen_andi_i64(dst
, dst
, 0x7fffffff);
473 tcg_gen_andi_i64(dst
, dst
, 0x00ffffff);
478 static TCGv_i64
get_address(DisasContext
*s
, int x2
, int b2
, int d2
)
480 TCGv_i64 tmp
= tcg_temp_new_i64();
483 * Note that d2 is limited to 20 bits, signed. If we crop negative
484 * displacements early we create larger immediate addends.
487 tcg_gen_add_i64(tmp
, regs
[b2
], regs
[x2
]);
488 gen_addi_and_wrap_i64(s
, tmp
, tmp
, d2
);
490 gen_addi_and_wrap_i64(s
, tmp
, regs
[b2
], d2
);
492 gen_addi_and_wrap_i64(s
, tmp
, regs
[x2
], d2
);
493 } else if (!(s
->base
.tb
->flags
& FLAG_MASK_64
)) {
494 if (s
->base
.tb
->flags
& FLAG_MASK_32
) {
495 tcg_gen_movi_i64(tmp
, d2
& 0x7fffffff);
497 tcg_gen_movi_i64(tmp
, d2
& 0x00ffffff);
500 tcg_gen_movi_i64(tmp
, d2
);
506 static inline bool live_cc_data(DisasContext
*s
)
508 return (s
->cc_op
!= CC_OP_DYNAMIC
509 && s
->cc_op
!= CC_OP_STATIC
513 static inline void gen_op_movi_cc(DisasContext
*s
, uint32_t val
)
515 if (live_cc_data(s
)) {
516 tcg_gen_discard_i64(cc_src
);
517 tcg_gen_discard_i64(cc_dst
);
518 tcg_gen_discard_i64(cc_vr
);
520 s
->cc_op
= CC_OP_CONST0
+ val
;
523 static void gen_op_update1_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 dst
)
525 if (live_cc_data(s
)) {
526 tcg_gen_discard_i64(cc_src
);
527 tcg_gen_discard_i64(cc_vr
);
529 tcg_gen_mov_i64(cc_dst
, dst
);
533 static void gen_op_update2_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
536 if (live_cc_data(s
)) {
537 tcg_gen_discard_i64(cc_vr
);
539 tcg_gen_mov_i64(cc_src
, src
);
540 tcg_gen_mov_i64(cc_dst
, dst
);
544 static void gen_op_update3_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
545 TCGv_i64 dst
, TCGv_i64 vr
)
547 tcg_gen_mov_i64(cc_src
, src
);
548 tcg_gen_mov_i64(cc_dst
, dst
);
549 tcg_gen_mov_i64(cc_vr
, vr
);
553 static void set_cc_nz_u64(DisasContext
*s
, TCGv_i64 val
)
555 gen_op_update1_cc_i64(s
, CC_OP_NZ
, val
);
558 /* CC value is in env->cc_op */
559 static void set_cc_static(DisasContext
*s
)
561 if (live_cc_data(s
)) {
562 tcg_gen_discard_i64(cc_src
);
563 tcg_gen_discard_i64(cc_dst
);
564 tcg_gen_discard_i64(cc_vr
);
566 s
->cc_op
= CC_OP_STATIC
;
569 /* calculates cc into cc_op */
570 static void gen_op_calc_cc(DisasContext
*s
)
572 TCGv_i32 local_cc_op
= NULL
;
573 TCGv_i64 dummy
= NULL
;
577 dummy
= tcg_constant_i64(0);
583 local_cc_op
= tcg_constant_i32(s
->cc_op
);
599 /* s->cc_op is the cc value */
600 tcg_gen_movi_i32(cc_op
, s
->cc_op
- CC_OP_CONST0
);
603 /* env->cc_op already is the cc value */
606 tcg_gen_setcondi_i64(TCG_COND_NE
, cc_dst
, cc_dst
, 0);
607 tcg_gen_extrl_i64_i32(cc_op
, cc_dst
);
623 gen_helper_calc_cc(cc_op
, tcg_env
, local_cc_op
, dummy
, cc_dst
, dummy
);
629 case CC_OP_LTUGTU_32
:
630 case CC_OP_LTUGTU_64
:
639 gen_helper_calc_cc(cc_op
, tcg_env
, local_cc_op
, cc_src
, cc_dst
, dummy
);
646 gen_helper_calc_cc(cc_op
, tcg_env
, local_cc_op
, cc_src
, cc_dst
, cc_vr
);
649 /* unknown operation - assume 3 arguments and cc_op in env */
650 gen_helper_calc_cc(cc_op
, tcg_env
, cc_op
, cc_src
, cc_dst
, cc_vr
);
653 g_assert_not_reached();
656 /* We now have cc in cc_op as constant */
660 static bool use_goto_tb(DisasContext
*s
, uint64_t dest
)
662 if (unlikely(s
->base
.tb
->flags
& FLAG_MASK_PER
)) {
665 return translator_use_goto_tb(&s
->base
, dest
);
668 static void account_noninline_branch(DisasContext
*s
, int cc_op
)
670 #ifdef DEBUG_INLINE_BRANCHES
671 inline_branch_miss
[cc_op
]++;
675 static void account_inline_branch(DisasContext
*s
, int cc_op
)
677 #ifdef DEBUG_INLINE_BRANCHES
678 inline_branch_hit
[cc_op
]++;
682 /* Table of mask values to comparison codes, given a comparison as input.
683 For such, CC=3 should not be possible. */
684 static const TCGCond ltgt_cond
[16] = {
685 TCG_COND_NEVER
, TCG_COND_NEVER
, /* | | | x */
686 TCG_COND_GT
, TCG_COND_GT
, /* | | GT | x */
687 TCG_COND_LT
, TCG_COND_LT
, /* | LT | | x */
688 TCG_COND_NE
, TCG_COND_NE
, /* | LT | GT | x */
689 TCG_COND_EQ
, TCG_COND_EQ
, /* EQ | | | x */
690 TCG_COND_GE
, TCG_COND_GE
, /* EQ | | GT | x */
691 TCG_COND_LE
, TCG_COND_LE
, /* EQ | LT | | x */
692 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, /* EQ | LT | GT | x */
695 /* Table of mask values to comparison codes, given a logic op as input.
696 For such, only CC=0 and CC=1 should be possible. */
697 static const TCGCond nz_cond
[16] = {
698 TCG_COND_NEVER
, TCG_COND_NEVER
, /* | | x | x */
699 TCG_COND_NEVER
, TCG_COND_NEVER
,
700 TCG_COND_NE
, TCG_COND_NE
, /* | NE | x | x */
701 TCG_COND_NE
, TCG_COND_NE
,
702 TCG_COND_EQ
, TCG_COND_EQ
, /* EQ | | x | x */
703 TCG_COND_EQ
, TCG_COND_EQ
,
704 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, /* EQ | NE | x | x */
705 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
,
708 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
709 details required to generate a TCG comparison. */
710 static void disas_jcc(DisasContext
*s
, DisasCompare
*c
, uint32_t mask
)
713 enum cc_op old_cc_op
= s
->cc_op
;
715 if (mask
== 15 || mask
== 0) {
716 c
->cond
= (mask
? TCG_COND_ALWAYS
: TCG_COND_NEVER
);
723 /* Find the TCG condition for the mask + cc op. */
729 cond
= ltgt_cond
[mask
];
730 if (cond
== TCG_COND_NEVER
) {
733 account_inline_branch(s
, old_cc_op
);
736 case CC_OP_LTUGTU_32
:
737 case CC_OP_LTUGTU_64
:
738 cond
= tcg_unsigned_cond(ltgt_cond
[mask
]);
739 if (cond
== TCG_COND_NEVER
) {
742 account_inline_branch(s
, old_cc_op
);
746 cond
= nz_cond
[mask
];
747 if (cond
== TCG_COND_NEVER
) {
750 account_inline_branch(s
, old_cc_op
);
765 account_inline_branch(s
, old_cc_op
);
780 account_inline_branch(s
, old_cc_op
);
784 switch (mask
& 0xa) {
785 case 8: /* src == 0 -> no one bit found */
788 case 2: /* src != 0 -> one bit found */
794 account_inline_branch(s
, old_cc_op
);
800 case 8 | 2: /* result == 0 */
803 case 4 | 1: /* result != 0 */
806 case 8 | 4: /* !carry (borrow) */
807 cond
= old_cc_op
== CC_OP_ADDU
? TCG_COND_EQ
: TCG_COND_NE
;
809 case 2 | 1: /* carry (!borrow) */
810 cond
= old_cc_op
== CC_OP_ADDU
? TCG_COND_NE
: TCG_COND_EQ
;
815 account_inline_branch(s
, old_cc_op
);
820 /* Calculate cc value. */
825 /* Jump based on CC. We'll load up the real cond below;
826 the assignment here merely avoids a compiler warning. */
827 account_noninline_branch(s
, old_cc_op
);
828 old_cc_op
= CC_OP_STATIC
;
829 cond
= TCG_COND_NEVER
;
833 /* Load up the arguments of the comparison. */
838 c
->u
.s32
.a
= tcg_temp_new_i32();
839 tcg_gen_extrl_i64_i32(c
->u
.s32
.a
, cc_dst
);
840 c
->u
.s32
.b
= tcg_constant_i32(0);
843 case CC_OP_LTUGTU_32
:
845 c
->u
.s32
.a
= tcg_temp_new_i32();
846 tcg_gen_extrl_i64_i32(c
->u
.s32
.a
, cc_src
);
847 c
->u
.s32
.b
= tcg_temp_new_i32();
848 tcg_gen_extrl_i64_i32(c
->u
.s32
.b
, cc_dst
);
855 c
->u
.s64
.b
= tcg_constant_i64(0);
858 case CC_OP_LTUGTU_64
:
866 c
->u
.s64
.a
= tcg_temp_new_i64();
867 c
->u
.s64
.b
= tcg_constant_i64(0);
868 tcg_gen_and_i64(c
->u
.s64
.a
, cc_src
, cc_dst
);
874 c
->u
.s64
.b
= tcg_constant_i64(0);
877 case 4 | 1: /* result */
881 case 2 | 1: /* carry */
885 g_assert_not_reached();
893 case 0x8 | 0x4 | 0x2: /* cc != 3 */
895 c
->u
.s32
.b
= tcg_constant_i32(3);
897 case 0x8 | 0x4 | 0x1: /* cc != 2 */
899 c
->u
.s32
.b
= tcg_constant_i32(2);
901 case 0x8 | 0x2 | 0x1: /* cc != 1 */
903 c
->u
.s32
.b
= tcg_constant_i32(1);
905 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
907 c
->u
.s32
.a
= tcg_temp_new_i32();
908 c
->u
.s32
.b
= tcg_constant_i32(0);
909 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
911 case 0x8 | 0x4: /* cc < 2 */
913 c
->u
.s32
.b
= tcg_constant_i32(2);
915 case 0x8: /* cc == 0 */
917 c
->u
.s32
.b
= tcg_constant_i32(0);
919 case 0x4 | 0x2 | 0x1: /* cc != 0 */
921 c
->u
.s32
.b
= tcg_constant_i32(0);
923 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
925 c
->u
.s32
.a
= tcg_temp_new_i32();
926 c
->u
.s32
.b
= tcg_constant_i32(0);
927 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
929 case 0x4: /* cc == 1 */
931 c
->u
.s32
.b
= tcg_constant_i32(1);
933 case 0x2 | 0x1: /* cc > 1 */
935 c
->u
.s32
.b
= tcg_constant_i32(1);
937 case 0x2: /* cc == 2 */
939 c
->u
.s32
.b
= tcg_constant_i32(2);
941 case 0x1: /* cc == 3 */
943 c
->u
.s32
.b
= tcg_constant_i32(3);
946 /* CC is masked by something else: (8 >> cc) & mask. */
948 c
->u
.s32
.a
= tcg_temp_new_i32();
949 c
->u
.s32
.b
= tcg_constant_i32(0);
950 tcg_gen_shr_i32(c
->u
.s32
.a
, tcg_constant_i32(8), cc_op
);
951 tcg_gen_andi_i32(c
->u
.s32
.a
, c
->u
.s32
.a
, mask
);
962 /* ====================================================================== */
963 /* Define the insn format enumeration. */
964 #define F0(N) FMT_##N,
965 #define F1(N, X1) F0(N)
966 #define F2(N, X1, X2) F0(N)
967 #define F3(N, X1, X2, X3) F0(N)
968 #define F4(N, X1, X2, X3, X4) F0(N)
969 #define F5(N, X1, X2, X3, X4, X5) F0(N)
970 #define F6(N, X1, X2, X3, X4, X5, X6) F0(N)
973 #include "insn-format.h.inc"
984 /* This is the way fields are to be accessed out of DisasFields. */
985 #define have_field(S, F) have_field1((S), FLD_O_##F)
986 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
988 static bool have_field1(const DisasContext
*s
, enum DisasFieldIndexO c
)
990 return (s
->fields
.presentO
>> c
) & 1;
993 static int get_field1(const DisasContext
*s
, enum DisasFieldIndexO o
,
994 enum DisasFieldIndexC c
)
996 assert(have_field1(s
, o
));
997 return s
->fields
.c
[c
];
1000 /* Describe the layout of each field in each format. */
1001 typedef struct DisasField
{
1003 unsigned int size
:8;
1004 unsigned int type
:2;
1005 unsigned int indexC
:6;
1006 enum DisasFieldIndexO indexO
:8;
1009 typedef struct DisasFormatInfo
{
1010 DisasField op
[NUM_C_FIELD
];
1013 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1014 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1015 #define V(N, B) { B, 4, 3, FLD_C_v##N, FLD_O_v##N }
1016 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1017 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1018 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1019 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1020 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1021 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1022 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1023 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1024 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1025 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1026 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1027 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1029 #define F0(N) { { } },
1030 #define F1(N, X1) { { X1 } },
1031 #define F2(N, X1, X2) { { X1, X2 } },
1032 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1033 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1034 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1035 #define F6(N, X1, X2, X3, X4, X5, X6) { { X1, X2, X3, X4, X5, X6 } },
1037 static const DisasFormatInfo format_info
[] = {
1038 #include "insn-format.h.inc"
1058 /* Generally, we'll extract operands into this structures, operate upon
1059 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1060 of routines below for more details. */
1062 TCGv_i64 out
, out2
, in1
, in2
;
1064 TCGv_i128 out_128
, in1_128
, in2_128
;
1067 /* Instructions can place constraints on their operands, raising specification
1068 exceptions if they are violated. To make this easy to automate, each "in1",
1069 "in2", "prep", "wout" helper will have a SPEC_<name> define that equals one
1070 of the following, or 0. To make this easy to document, we'll put the
1071 SPEC_<name> defines next to <name>. */
1073 #define SPEC_r1_even 1
1074 #define SPEC_r2_even 2
1075 #define SPEC_r3_even 4
1076 #define SPEC_r1_f128 8
1077 #define SPEC_r2_f128 16
1079 /* Return values from translate_one, indicating the state of the TB. */
1081 /* We are not using a goto_tb (for whatever reason), but have updated
1082 the PC (for whatever reason), so there's no need to do it again on
1084 #define DISAS_PC_UPDATED DISAS_TARGET_0
1086 /* We have updated the PC and CC values. */
1087 #define DISAS_PC_CC_UPDATED DISAS_TARGET_2
1090 /* Instruction flags */
1091 #define IF_AFP1 0x0001 /* r1 is a fp reg for HFP/FPS instructions */
1092 #define IF_AFP2 0x0002 /* r2 is a fp reg for HFP/FPS instructions */
1093 #define IF_AFP3 0x0004 /* r3 is a fp reg for HFP/FPS instructions */
1094 #define IF_BFP 0x0008 /* binary floating point instruction */
1095 #define IF_DFP 0x0010 /* decimal floating point instruction */
1096 #define IF_PRIV 0x0020 /* privileged instruction */
1097 #define IF_VEC 0x0040 /* vector instruction */
1098 #define IF_IO 0x0080 /* input/output instruction */
1109 /* Pre-process arguments before HELP_OP. */
1110 void (*help_in1
)(DisasContext
*, DisasOps
*);
1111 void (*help_in2
)(DisasContext
*, DisasOps
*);
1112 void (*help_prep
)(DisasContext
*, DisasOps
*);
1115 * Post-process output after HELP_OP.
1116 * Note that these are not called if HELP_OP returns DISAS_NORETURN.
1118 void (*help_wout
)(DisasContext
*, DisasOps
*);
1119 void (*help_cout
)(DisasContext
*, DisasOps
*);
1121 /* Implement the operation itself. */
1122 DisasJumpType (*help_op
)(DisasContext
*, DisasOps
*);
1127 /* ====================================================================== */
1128 /* Miscellaneous helpers, used by several operations. */
1130 static DisasJumpType
help_goto_direct(DisasContext
*s
, uint64_t dest
)
1132 if (dest
== s
->pc_tmp
) {
1133 per_branch(s
, true);
1136 if (use_goto_tb(s
, dest
)) {
1138 per_breaking_event(s
);
1140 tcg_gen_movi_i64(psw_addr
, dest
);
1141 tcg_gen_exit_tb(s
->base
.tb
, 0);
1142 return DISAS_NORETURN
;
1144 tcg_gen_movi_i64(psw_addr
, dest
);
1145 per_branch(s
, false);
1146 return DISAS_PC_UPDATED
;
1150 static DisasJumpType
help_branch(DisasContext
*s
, DisasCompare
*c
,
1151 bool is_imm
, int imm
, TCGv_i64 cdest
)
1154 uint64_t dest
= s
->base
.pc_next
+ (int64_t)imm
* 2;
1157 /* Take care of the special cases first. */
1158 if (c
->cond
== TCG_COND_NEVER
) {
1163 if (dest
== s
->pc_tmp
) {
1164 /* Branch to next. */
1165 per_branch(s
, true);
1169 if (c
->cond
== TCG_COND_ALWAYS
) {
1170 ret
= help_goto_direct(s
, dest
);
1175 /* E.g. bcr %r0 -> no branch. */
1179 if (c
->cond
== TCG_COND_ALWAYS
) {
1180 tcg_gen_mov_i64(psw_addr
, cdest
);
1181 per_branch(s
, false);
1182 ret
= DISAS_PC_UPDATED
;
1187 if (use_goto_tb(s
, s
->pc_tmp
)) {
1188 if (is_imm
&& use_goto_tb(s
, dest
)) {
1189 /* Both exits can use goto_tb. */
1192 lab
= gen_new_label();
1194 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
1196 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
1199 /* Branch not taken. */
1201 tcg_gen_movi_i64(psw_addr
, s
->pc_tmp
);
1202 tcg_gen_exit_tb(s
->base
.tb
, 0);
1206 per_breaking_event(s
);
1208 tcg_gen_movi_i64(psw_addr
, dest
);
1209 tcg_gen_exit_tb(s
->base
.tb
, 1);
1211 ret
= DISAS_NORETURN
;
1213 /* Fallthru can use goto_tb, but taken branch cannot. */
1214 /* Store taken branch destination before the brcond. This
1215 avoids having to allocate a new local temp to hold it.
1216 We'll overwrite this in the not taken case anyway. */
1218 tcg_gen_mov_i64(psw_addr
, cdest
);
1221 lab
= gen_new_label();
1223 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
1225 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
1228 /* Branch not taken. */
1231 tcg_gen_movi_i64(psw_addr
, s
->pc_tmp
);
1232 tcg_gen_exit_tb(s
->base
.tb
, 0);
1236 tcg_gen_movi_i64(psw_addr
, dest
);
1238 per_breaking_event(s
);
1239 ret
= DISAS_PC_UPDATED
;
1242 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1243 Most commonly we're single-stepping or some other condition that
1244 disables all use of goto_tb. Just update the PC and exit. */
1246 TCGv_i64 next
= tcg_constant_i64(s
->pc_tmp
);
1248 cdest
= tcg_constant_i64(dest
);
1252 tcg_gen_movcond_i64(c
->cond
, psw_addr
, c
->u
.s64
.a
, c
->u
.s64
.b
,
1254 per_branch_cond(s
, c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
);
1256 TCGv_i32 t0
= tcg_temp_new_i32();
1257 TCGv_i64 t1
= tcg_temp_new_i64();
1258 TCGv_i64 z
= tcg_constant_i64(0);
1259 tcg_gen_setcond_i32(c
->cond
, t0
, c
->u
.s32
.a
, c
->u
.s32
.b
);
1260 tcg_gen_extu_i32_i64(t1
, t0
);
1261 tcg_gen_movcond_i64(TCG_COND_NE
, psw_addr
, t1
, z
, cdest
, next
);
1262 per_branch_cond(s
, TCG_COND_NE
, t1
, z
);
1265 ret
= DISAS_PC_UPDATED
;
1272 /* ====================================================================== */
1273 /* The operations. These perform the bulk of the work for any insn,
1274 usually after the operands have been loaded and output initialized. */
1276 static DisasJumpType
op_abs(DisasContext
*s
, DisasOps
*o
)
1278 tcg_gen_abs_i64(o
->out
, o
->in2
);
1282 static DisasJumpType
op_absf32(DisasContext
*s
, DisasOps
*o
)
1284 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffull
);
1288 static DisasJumpType
op_absf64(DisasContext
*s
, DisasOps
*o
)
1290 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffffffffffull
);
1294 static DisasJumpType
op_absf128(DisasContext
*s
, DisasOps
*o
)
1296 tcg_gen_andi_i64(o
->out
, o
->in1
, 0x7fffffffffffffffull
);
1297 tcg_gen_mov_i64(o
->out2
, o
->in2
);
1301 static DisasJumpType
op_add(DisasContext
*s
, DisasOps
*o
)
1303 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1307 static DisasJumpType
op_addu64(DisasContext
*s
, DisasOps
*o
)
1309 tcg_gen_movi_i64(cc_src
, 0);
1310 tcg_gen_add2_i64(o
->out
, cc_src
, o
->in1
, cc_src
, o
->in2
, cc_src
);
1314 /* Compute carry into cc_src. */
1315 static void compute_carry(DisasContext
*s
)
1319 /* The carry value is already in cc_src (1,0). */
1322 tcg_gen_addi_i64(cc_src
, cc_src
, 1);
1328 /* The carry flag is the msb of CC; compute into cc_src. */
1329 tcg_gen_extu_i32_i64(cc_src
, cc_op
);
1330 tcg_gen_shri_i64(cc_src
, cc_src
, 1);
1335 static DisasJumpType
op_addc32(DisasContext
*s
, DisasOps
*o
)
1338 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1339 tcg_gen_add_i64(o
->out
, o
->out
, cc_src
);
1343 static DisasJumpType
op_addc64(DisasContext
*s
, DisasOps
*o
)
1347 TCGv_i64 zero
= tcg_constant_i64(0);
1348 tcg_gen_add2_i64(o
->out
, cc_src
, o
->in1
, zero
, cc_src
, zero
);
1349 tcg_gen_add2_i64(o
->out
, cc_src
, o
->out
, cc_src
, o
->in2
, zero
);
1354 static DisasJumpType
op_asi(DisasContext
*s
, DisasOps
*o
)
1356 bool non_atomic
= !s390_has_feat(S390_FEAT_STFLE_45
);
1358 o
->in1
= tcg_temp_new_i64();
1360 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1362 /* Perform the atomic addition in memory. */
1363 tcg_gen_atomic_fetch_add_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
1367 /* Recompute also for atomic case: needed for setting CC. */
1368 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1371 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1376 static DisasJumpType
op_asiu64(DisasContext
*s
, DisasOps
*o
)
1378 bool non_atomic
= !s390_has_feat(S390_FEAT_STFLE_45
);
1380 o
->in1
= tcg_temp_new_i64();
1382 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1384 /* Perform the atomic addition in memory. */
1385 tcg_gen_atomic_fetch_add_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
1389 /* Recompute also for atomic case: needed for setting CC. */
1390 tcg_gen_movi_i64(cc_src
, 0);
1391 tcg_gen_add2_i64(o
->out
, cc_src
, o
->in1
, cc_src
, o
->in2
, cc_src
);
1394 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1399 static DisasJumpType
op_aeb(DisasContext
*s
, DisasOps
*o
)
1401 gen_helper_aeb(o
->out
, tcg_env
, o
->in1
, o
->in2
);
1405 static DisasJumpType
op_adb(DisasContext
*s
, DisasOps
*o
)
1407 gen_helper_adb(o
->out
, tcg_env
, o
->in1
, o
->in2
);
1411 static DisasJumpType
op_axb(DisasContext
*s
, DisasOps
*o
)
1413 gen_helper_axb(o
->out_128
, tcg_env
, o
->in1_128
, o
->in2_128
);
1417 static DisasJumpType
op_and(DisasContext
*s
, DisasOps
*o
)
1419 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
1423 static DisasJumpType
op_andi(DisasContext
*s
, DisasOps
*o
)
1425 int shift
= s
->insn
->data
& 0xff;
1426 int size
= s
->insn
->data
>> 8;
1427 uint64_t mask
= ((1ull << size
) - 1) << shift
;
1428 TCGv_i64 t
= tcg_temp_new_i64();
1430 tcg_gen_shli_i64(t
, o
->in2
, shift
);
1431 tcg_gen_ori_i64(t
, t
, ~mask
);
1432 tcg_gen_and_i64(o
->out
, o
->in1
, t
);
1434 /* Produce the CC from only the bits manipulated. */
1435 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
1436 set_cc_nz_u64(s
, cc_dst
);
1440 static DisasJumpType
op_andc(DisasContext
*s
, DisasOps
*o
)
1442 tcg_gen_andc_i64(o
->out
, o
->in1
, o
->in2
);
1446 static DisasJumpType
op_orc(DisasContext
*s
, DisasOps
*o
)
1448 tcg_gen_orc_i64(o
->out
, o
->in1
, o
->in2
);
1452 static DisasJumpType
op_nand(DisasContext
*s
, DisasOps
*o
)
1454 tcg_gen_nand_i64(o
->out
, o
->in1
, o
->in2
);
1458 static DisasJumpType
op_nor(DisasContext
*s
, DisasOps
*o
)
1460 tcg_gen_nor_i64(o
->out
, o
->in1
, o
->in2
);
1464 static DisasJumpType
op_nxor(DisasContext
*s
, DisasOps
*o
)
1466 tcg_gen_eqv_i64(o
->out
, o
->in1
, o
->in2
);
1470 static DisasJumpType
op_ni(DisasContext
*s
, DisasOps
*o
)
1472 o
->in1
= tcg_temp_new_i64();
1474 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
1475 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1477 /* Perform the atomic operation in memory. */
1478 tcg_gen_atomic_fetch_and_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
1482 /* Recompute also for atomic case: needed for setting CC. */
1483 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
1485 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
1486 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1491 static DisasJumpType
op_bas(DisasContext
*s
, DisasOps
*o
)
1493 pc_to_link_info(o
->out
, s
, s
->pc_tmp
);
1495 tcg_gen_mov_i64(psw_addr
, o
->in2
);
1496 per_branch(s
, false);
1497 return DISAS_PC_UPDATED
;
1503 static void save_link_info(DisasContext
*s
, DisasOps
*o
)
1507 if (s
->base
.tb
->flags
& (FLAG_MASK_32
| FLAG_MASK_64
)) {
1508 pc_to_link_info(o
->out
, s
, s
->pc_tmp
);
1512 tcg_gen_andi_i64(o
->out
, o
->out
, 0xffffffff00000000ull
);
1513 tcg_gen_ori_i64(o
->out
, o
->out
, ((s
->ilen
/ 2) << 30) | s
->pc_tmp
);
1514 t
= tcg_temp_new_i64();
1515 tcg_gen_shri_i64(t
, psw_mask
, 16);
1516 tcg_gen_andi_i64(t
, t
, 0x0f000000);
1517 tcg_gen_or_i64(o
->out
, o
->out
, t
);
1518 tcg_gen_extu_i32_i64(t
, cc_op
);
1519 tcg_gen_shli_i64(t
, t
, 28);
1520 tcg_gen_or_i64(o
->out
, o
->out
, t
);
1523 static DisasJumpType
op_bal(DisasContext
*s
, DisasOps
*o
)
1525 save_link_info(s
, o
);
1527 tcg_gen_mov_i64(psw_addr
, o
->in2
);
1528 per_branch(s
, false);
1529 return DISAS_PC_UPDATED
;
1536 * Disassemble the target of a branch. The results are returned in a form
1537 * suitable for passing into help_branch():
1539 * - bool IS_IMM reflects whether the target is fixed or computed. Non-EXECUTEd
1540 * branches, whose DisasContext *S contains the relative immediate field RI,
1541 * are considered fixed. All the other branches are considered computed.
1542 * - int IMM is the value of RI.
1543 * - TCGv_i64 CDEST is the address of the computed target.
1545 #define disas_jdest(s, ri, is_imm, imm, cdest) do { \
1546 if (have_field(s, ri)) { \
1547 if (unlikely(s->ex_value)) { \
1548 cdest = tcg_temp_new_i64(); \
1549 tcg_gen_ld_i64(cdest, tcg_env, offsetof(CPUS390XState, ex_target));\
1550 tcg_gen_addi_i64(cdest, cdest, (int64_t)get_field(s, ri) * 2); \
1558 imm = is_imm ? get_field(s, ri) : 0; \
1561 static DisasJumpType
op_basi(DisasContext
*s
, DisasOps
*o
)
1567 pc_to_link_info(o
->out
, s
, s
->pc_tmp
);
1569 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1570 disas_jcc(s
, &c
, 0xf);
1571 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1574 static DisasJumpType
op_bc(DisasContext
*s
, DisasOps
*o
)
1576 int m1
= get_field(s
, m1
);
1581 /* BCR with R2 = 0 causes no branching */
1582 if (have_field(s
, r2
) && get_field(s
, r2
) == 0) {
1584 /* Perform serialization */
1585 /* FIXME: check for fast-BCR-serialization facility */
1586 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1589 /* Perform serialization */
1590 /* FIXME: perform checkpoint-synchronisation */
1591 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1596 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1597 disas_jcc(s
, &c
, m1
);
1598 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1601 static DisasJumpType
op_bct32(DisasContext
*s
, DisasOps
*o
)
1603 int r1
= get_field(s
, r1
);
1609 c
.cond
= TCG_COND_NE
;
1612 t
= tcg_temp_new_i64();
1613 tcg_gen_subi_i64(t
, regs
[r1
], 1);
1614 store_reg32_i64(r1
, t
);
1615 c
.u
.s32
.a
= tcg_temp_new_i32();
1616 c
.u
.s32
.b
= tcg_constant_i32(0);
1617 tcg_gen_extrl_i64_i32(c
.u
.s32
.a
, t
);
1619 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1620 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1623 static DisasJumpType
op_bcth(DisasContext
*s
, DisasOps
*o
)
1625 int r1
= get_field(s
, r1
);
1626 int imm
= get_field(s
, i2
);
1630 c
.cond
= TCG_COND_NE
;
1633 t
= tcg_temp_new_i64();
1634 tcg_gen_shri_i64(t
, regs
[r1
], 32);
1635 tcg_gen_subi_i64(t
, t
, 1);
1636 store_reg32h_i64(r1
, t
);
1637 c
.u
.s32
.a
= tcg_temp_new_i32();
1638 c
.u
.s32
.b
= tcg_constant_i32(0);
1639 tcg_gen_extrl_i64_i32(c
.u
.s32
.a
, t
);
1641 return help_branch(s
, &c
, 1, imm
, o
->in2
);
1644 static DisasJumpType
op_bct64(DisasContext
*s
, DisasOps
*o
)
1646 int r1
= get_field(s
, r1
);
1651 c
.cond
= TCG_COND_NE
;
1654 tcg_gen_subi_i64(regs
[r1
], regs
[r1
], 1);
1655 c
.u
.s64
.a
= regs
[r1
];
1656 c
.u
.s64
.b
= tcg_constant_i64(0);
1658 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1659 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1662 static DisasJumpType
op_bx32(DisasContext
*s
, DisasOps
*o
)
1664 int r1
= get_field(s
, r1
);
1665 int r3
= get_field(s
, r3
);
1671 c
.cond
= (s
->insn
->data
? TCG_COND_LE
: TCG_COND_GT
);
1674 t
= tcg_temp_new_i64();
1675 tcg_gen_add_i64(t
, regs
[r1
], regs
[r3
]);
1676 c
.u
.s32
.a
= tcg_temp_new_i32();
1677 c
.u
.s32
.b
= tcg_temp_new_i32();
1678 tcg_gen_extrl_i64_i32(c
.u
.s32
.a
, t
);
1679 tcg_gen_extrl_i64_i32(c
.u
.s32
.b
, regs
[r3
| 1]);
1680 store_reg32_i64(r1
, t
);
1682 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1683 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1686 static DisasJumpType
op_bx64(DisasContext
*s
, DisasOps
*o
)
1688 int r1
= get_field(s
, r1
);
1689 int r3
= get_field(s
, r3
);
1694 c
.cond
= (s
->insn
->data
? TCG_COND_LE
: TCG_COND_GT
);
1697 if (r1
== (r3
| 1)) {
1698 c
.u
.s64
.b
= load_reg(r3
| 1);
1700 c
.u
.s64
.b
= regs
[r3
| 1];
1703 tcg_gen_add_i64(regs
[r1
], regs
[r1
], regs
[r3
]);
1704 c
.u
.s64
.a
= regs
[r1
];
1706 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1707 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1710 static DisasJumpType
op_cj(DisasContext
*s
, DisasOps
*o
)
1712 int imm
, m3
= get_field(s
, m3
);
1716 c
.cond
= ltgt_cond
[m3
];
1717 if (s
->insn
->data
) {
1718 c
.cond
= tcg_unsigned_cond(c
.cond
);
1725 disas_jdest(s
, i4
, is_imm
, imm
, o
->out
);
1726 if (!is_imm
&& !o
->out
) {
1728 o
->out
= get_address(s
, 0, get_field(s
, b4
),
1732 return help_branch(s
, &c
, is_imm
, imm
, o
->out
);
1735 static DisasJumpType
op_ceb(DisasContext
*s
, DisasOps
*o
)
1737 gen_helper_ceb(cc_op
, tcg_env
, o
->in1
, o
->in2
);
1742 static DisasJumpType
op_cdb(DisasContext
*s
, DisasOps
*o
)
1744 gen_helper_cdb(cc_op
, tcg_env
, o
->in1
, o
->in2
);
1749 static DisasJumpType
op_cxb(DisasContext
*s
, DisasOps
*o
)
1751 gen_helper_cxb(cc_op
, tcg_env
, o
->in1_128
, o
->in2_128
);
1756 static TCGv_i32
fpinst_extract_m34(DisasContext
*s
, bool m3_with_fpe
,
1759 const bool fpe
= s390_has_feat(S390_FEAT_FLOATING_POINT_EXT
);
1760 uint8_t m3
= get_field(s
, m3
);
1761 uint8_t m4
= get_field(s
, m4
);
1763 /* m3 field was introduced with FPE */
1764 if (!fpe
&& m3_with_fpe
) {
1767 /* m4 field was introduced with FPE */
1768 if (!fpe
&& m4_with_fpe
) {
1772 /* Check for valid rounding modes. Mode 3 was introduced later. */
1773 if (m3
== 2 || m3
> 7 || (!fpe
&& m3
== 3)) {
1774 gen_program_exception(s
, PGM_SPECIFICATION
);
1778 return tcg_constant_i32(deposit32(m3
, 4, 4, m4
));
1781 static DisasJumpType
op_cfeb(DisasContext
*s
, DisasOps
*o
)
1783 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1786 return DISAS_NORETURN
;
1788 gen_helper_cfeb(o
->out
, tcg_env
, o
->in2
, m34
);
1793 static DisasJumpType
op_cfdb(DisasContext
*s
, DisasOps
*o
)
1795 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1798 return DISAS_NORETURN
;
1800 gen_helper_cfdb(o
->out
, tcg_env
, o
->in2
, m34
);
1805 static DisasJumpType
op_cfxb(DisasContext
*s
, DisasOps
*o
)
1807 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1810 return DISAS_NORETURN
;
1812 gen_helper_cfxb(o
->out
, tcg_env
, o
->in2_128
, m34
);
1817 static DisasJumpType
op_cgeb(DisasContext
*s
, DisasOps
*o
)
1819 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1822 return DISAS_NORETURN
;
1824 gen_helper_cgeb(o
->out
, tcg_env
, o
->in2
, m34
);
1829 static DisasJumpType
op_cgdb(DisasContext
*s
, DisasOps
*o
)
1831 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1834 return DISAS_NORETURN
;
1836 gen_helper_cgdb(o
->out
, tcg_env
, o
->in2
, m34
);
1841 static DisasJumpType
op_cgxb(DisasContext
*s
, DisasOps
*o
)
1843 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1846 return DISAS_NORETURN
;
1848 gen_helper_cgxb(o
->out
, tcg_env
, o
->in2_128
, m34
);
1853 static DisasJumpType
op_clfeb(DisasContext
*s
, DisasOps
*o
)
1855 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1858 return DISAS_NORETURN
;
1860 gen_helper_clfeb(o
->out
, tcg_env
, o
->in2
, m34
);
1865 static DisasJumpType
op_clfdb(DisasContext
*s
, DisasOps
*o
)
1867 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1870 return DISAS_NORETURN
;
1872 gen_helper_clfdb(o
->out
, tcg_env
, o
->in2
, m34
);
1877 static DisasJumpType
op_clfxb(DisasContext
*s
, DisasOps
*o
)
1879 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1882 return DISAS_NORETURN
;
1884 gen_helper_clfxb(o
->out
, tcg_env
, o
->in2_128
, m34
);
1889 static DisasJumpType
op_clgeb(DisasContext
*s
, DisasOps
*o
)
1891 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1894 return DISAS_NORETURN
;
1896 gen_helper_clgeb(o
->out
, tcg_env
, o
->in2
, m34
);
1901 static DisasJumpType
op_clgdb(DisasContext
*s
, DisasOps
*o
)
1903 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1906 return DISAS_NORETURN
;
1908 gen_helper_clgdb(o
->out
, tcg_env
, o
->in2
, m34
);
1913 static DisasJumpType
op_clgxb(DisasContext
*s
, DisasOps
*o
)
1915 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1918 return DISAS_NORETURN
;
1920 gen_helper_clgxb(o
->out
, tcg_env
, o
->in2_128
, m34
);
1925 static DisasJumpType
op_cegb(DisasContext
*s
, DisasOps
*o
)
1927 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
1930 return DISAS_NORETURN
;
1932 gen_helper_cegb(o
->out
, tcg_env
, o
->in2
, m34
);
1936 static DisasJumpType
op_cdgb(DisasContext
*s
, DisasOps
*o
)
1938 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
1941 return DISAS_NORETURN
;
1943 gen_helper_cdgb(o
->out
, tcg_env
, o
->in2
, m34
);
1947 static DisasJumpType
op_cxgb(DisasContext
*s
, DisasOps
*o
)
1949 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
1952 return DISAS_NORETURN
;
1954 gen_helper_cxgb(o
->out_128
, tcg_env
, o
->in2
, m34
);
1958 static DisasJumpType
op_celgb(DisasContext
*s
, DisasOps
*o
)
1960 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1963 return DISAS_NORETURN
;
1965 gen_helper_celgb(o
->out
, tcg_env
, o
->in2
, m34
);
1969 static DisasJumpType
op_cdlgb(DisasContext
*s
, DisasOps
*o
)
1971 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1974 return DISAS_NORETURN
;
1976 gen_helper_cdlgb(o
->out
, tcg_env
, o
->in2
, m34
);
1980 static DisasJumpType
op_cxlgb(DisasContext
*s
, DisasOps
*o
)
1982 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1985 return DISAS_NORETURN
;
1987 gen_helper_cxlgb(o
->out_128
, tcg_env
, o
->in2
, m34
);
1991 static DisasJumpType
op_cksm(DisasContext
*s
, DisasOps
*o
)
1993 int r2
= get_field(s
, r2
);
1994 TCGv_i128 pair
= tcg_temp_new_i128();
1995 TCGv_i64 len
= tcg_temp_new_i64();
1997 gen_helper_cksm(pair
, tcg_env
, o
->in1
, o
->in2
, regs
[r2
+ 1]);
1999 tcg_gen_extr_i128_i64(o
->out
, len
, pair
);
2001 tcg_gen_add_i64(regs
[r2
], regs
[r2
], len
);
2002 tcg_gen_sub_i64(regs
[r2
+ 1], regs
[r2
+ 1], len
);
2007 static DisasJumpType
op_clc(DisasContext
*s
, DisasOps
*o
)
2009 int l
= get_field(s
, l1
);
2019 mop
= ctz32(l
+ 1) | MO_TE
;
2020 /* Do not update cc_src yet: loading cc_dst may cause an exception. */
2021 src
= tcg_temp_new_i64();
2022 tcg_gen_qemu_ld_tl(src
, o
->addr1
, get_mem_index(s
), mop
);
2023 tcg_gen_qemu_ld_tl(cc_dst
, o
->in2
, get_mem_index(s
), mop
);
2024 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, src
, cc_dst
);
2027 vl
= tcg_constant_i32(l
);
2028 gen_helper_clc(cc_op
, tcg_env
, vl
, o
->addr1
, o
->in2
);
2034 static DisasJumpType
op_clcl(DisasContext
*s
, DisasOps
*o
)
2036 int r1
= get_field(s
, r1
);
2037 int r2
= get_field(s
, r2
);
2040 /* r1 and r2 must be even. */
2041 if (r1
& 1 || r2
& 1) {
2042 gen_program_exception(s
, PGM_SPECIFICATION
);
2043 return DISAS_NORETURN
;
2046 t1
= tcg_constant_i32(r1
);
2047 t2
= tcg_constant_i32(r2
);
2048 gen_helper_clcl(cc_op
, tcg_env
, t1
, t2
);
2053 static DisasJumpType
op_clcle(DisasContext
*s
, DisasOps
*o
)
2055 int r1
= get_field(s
, r1
);
2056 int r3
= get_field(s
, r3
);
2059 /* r1 and r3 must be even. */
2060 if (r1
& 1 || r3
& 1) {
2061 gen_program_exception(s
, PGM_SPECIFICATION
);
2062 return DISAS_NORETURN
;
2065 t1
= tcg_constant_i32(r1
);
2066 t3
= tcg_constant_i32(r3
);
2067 gen_helper_clcle(cc_op
, tcg_env
, t1
, o
->in2
, t3
);
2072 static DisasJumpType
op_clclu(DisasContext
*s
, DisasOps
*o
)
2074 int r1
= get_field(s
, r1
);
2075 int r3
= get_field(s
, r3
);
2078 /* r1 and r3 must be even. */
2079 if (r1
& 1 || r3
& 1) {
2080 gen_program_exception(s
, PGM_SPECIFICATION
);
2081 return DISAS_NORETURN
;
2084 t1
= tcg_constant_i32(r1
);
2085 t3
= tcg_constant_i32(r3
);
2086 gen_helper_clclu(cc_op
, tcg_env
, t1
, o
->in2
, t3
);
2091 static DisasJumpType
op_clm(DisasContext
*s
, DisasOps
*o
)
2093 TCGv_i32 m3
= tcg_constant_i32(get_field(s
, m3
));
2094 TCGv_i32 t1
= tcg_temp_new_i32();
2096 tcg_gen_extrl_i64_i32(t1
, o
->in1
);
2097 gen_helper_clm(cc_op
, tcg_env
, t1
, m3
, o
->in2
);
2102 static DisasJumpType
op_clst(DisasContext
*s
, DisasOps
*o
)
2104 TCGv_i128 pair
= tcg_temp_new_i128();
2106 gen_helper_clst(pair
, tcg_env
, regs
[0], o
->in1
, o
->in2
);
2107 tcg_gen_extr_i128_i64(o
->in2
, o
->in1
, pair
);
2113 static DisasJumpType
op_cps(DisasContext
*s
, DisasOps
*o
)
2115 TCGv_i64 t
= tcg_temp_new_i64();
2116 tcg_gen_andi_i64(t
, o
->in1
, 0x8000000000000000ull
);
2117 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffffffffffull
);
2118 tcg_gen_or_i64(o
->out
, o
->out
, t
);
2122 static DisasJumpType
op_cs(DisasContext
*s
, DisasOps
*o
)
2124 int d2
= get_field(s
, d2
);
2125 int b2
= get_field(s
, b2
);
2128 /* Note that in1 = R3 (new value) and
2129 in2 = (zero-extended) R1 (expected value). */
2131 addr
= get_address(s
, 0, b2
, d2
);
2132 tcg_gen_atomic_cmpxchg_i64(o
->out
, addr
, o
->in2
, o
->in1
,
2133 get_mem_index(s
), s
->insn
->data
| MO_ALIGN
);
2135 /* Are the memory and expected values (un)equal? Note that this setcond
2136 produces the output CC value, thus the NE sense of the test. */
2137 cc
= tcg_temp_new_i64();
2138 tcg_gen_setcond_i64(TCG_COND_NE
, cc
, o
->in2
, o
->out
);
2139 tcg_gen_extrl_i64_i32(cc_op
, cc
);
2145 static DisasJumpType
op_cdsg(DisasContext
*s
, DisasOps
*o
)
2147 int r1
= get_field(s
, r1
);
2149 o
->out_128
= tcg_temp_new_i128();
2150 tcg_gen_concat_i64_i128(o
->out_128
, regs
[r1
+ 1], regs
[r1
]);
2152 /* Note out (R1:R1+1) = expected value and in2 (R3:R3+1) = new value. */
2153 tcg_gen_atomic_cmpxchg_i128(o
->out_128
, o
->addr1
, o
->out_128
, o
->in2_128
,
2154 get_mem_index(s
), MO_BE
| MO_128
| MO_ALIGN
);
2157 * Extract result into cc_dst:cc_src, compare vs the expected value
2158 * in the as yet unmodified input registers, then update CC_OP.
2160 tcg_gen_extr_i128_i64(cc_src
, cc_dst
, o
->out_128
);
2161 tcg_gen_xor_i64(cc_dst
, cc_dst
, regs
[r1
]);
2162 tcg_gen_xor_i64(cc_src
, cc_src
, regs
[r1
+ 1]);
2163 tcg_gen_or_i64(cc_dst
, cc_dst
, cc_src
);
2164 set_cc_nz_u64(s
, cc_dst
);
2169 static DisasJumpType
op_csst(DisasContext
*s
, DisasOps
*o
)
2171 int r3
= get_field(s
, r3
);
2172 TCGv_i32 t_r3
= tcg_constant_i32(r3
);
2174 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2175 gen_helper_csst_parallel(cc_op
, tcg_env
, t_r3
, o
->addr1
, o
->in2
);
2177 gen_helper_csst(cc_op
, tcg_env
, t_r3
, o
->addr1
, o
->in2
);
2184 #ifndef CONFIG_USER_ONLY
2185 static DisasJumpType
op_csp(DisasContext
*s
, DisasOps
*o
)
2187 MemOp mop
= s
->insn
->data
;
2188 TCGv_i64 addr
, old
, cc
;
2189 TCGLabel
*lab
= gen_new_label();
2191 /* Note that in1 = R1 (zero-extended expected value),
2192 out = R1 (original reg), out2 = R1+1 (new value). */
2194 addr
= tcg_temp_new_i64();
2195 old
= tcg_temp_new_i64();
2196 tcg_gen_andi_i64(addr
, o
->in2
, -1ULL << (mop
& MO_SIZE
));
2197 tcg_gen_atomic_cmpxchg_i64(old
, addr
, o
->in1
, o
->out2
,
2198 get_mem_index(s
), mop
| MO_ALIGN
);
2200 /* Are the memory and expected values (un)equal? */
2201 cc
= tcg_temp_new_i64();
2202 tcg_gen_setcond_i64(TCG_COND_NE
, cc
, o
->in1
, old
);
2203 tcg_gen_extrl_i64_i32(cc_op
, cc
);
2205 /* Write back the output now, so that it happens before the
2206 following branch, so that we don't need local temps. */
2207 if ((mop
& MO_SIZE
) == MO_32
) {
2208 tcg_gen_deposit_i64(o
->out
, o
->out
, old
, 0, 32);
2210 tcg_gen_mov_i64(o
->out
, old
);
2213 /* If the comparison was equal, and the LSB of R2 was set,
2214 then we need to flush the TLB (for all cpus). */
2215 tcg_gen_xori_i64(cc
, cc
, 1);
2216 tcg_gen_and_i64(cc
, cc
, o
->in2
);
2217 tcg_gen_brcondi_i64(TCG_COND_EQ
, cc
, 0, lab
);
2219 gen_helper_purge(tcg_env
);
2226 static DisasJumpType
op_cvd(DisasContext
*s
, DisasOps
*o
)
2228 TCGv_i64 t1
= tcg_temp_new_i64();
2229 TCGv_i32 t2
= tcg_temp_new_i32();
2230 tcg_gen_extrl_i64_i32(t2
, o
->in1
);
2231 gen_helper_cvd(t1
, t2
);
2232 tcg_gen_qemu_st_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
2236 static DisasJumpType
op_ct(DisasContext
*s
, DisasOps
*o
)
2238 int m3
= get_field(s
, m3
);
2239 TCGLabel
*lab
= gen_new_label();
2242 c
= tcg_invert_cond(ltgt_cond
[m3
]);
2243 if (s
->insn
->data
) {
2244 c
= tcg_unsigned_cond(c
);
2246 tcg_gen_brcond_i64(c
, o
->in1
, o
->in2
, lab
);
2255 static DisasJumpType
op_cuXX(DisasContext
*s
, DisasOps
*o
)
2257 int m3
= get_field(s
, m3
);
2258 int r1
= get_field(s
, r1
);
2259 int r2
= get_field(s
, r2
);
2260 TCGv_i32 tr1
, tr2
, chk
;
2262 /* R1 and R2 must both be even. */
2263 if ((r1
| r2
) & 1) {
2264 gen_program_exception(s
, PGM_SPECIFICATION
);
2265 return DISAS_NORETURN
;
2267 if (!s390_has_feat(S390_FEAT_ETF3_ENH
)) {
2271 tr1
= tcg_constant_i32(r1
);
2272 tr2
= tcg_constant_i32(r2
);
2273 chk
= tcg_constant_i32(m3
);
2275 switch (s
->insn
->data
) {
2277 gen_helper_cu12(cc_op
, tcg_env
, tr1
, tr2
, chk
);
2280 gen_helper_cu14(cc_op
, tcg_env
, tr1
, tr2
, chk
);
2283 gen_helper_cu21(cc_op
, tcg_env
, tr1
, tr2
, chk
);
2286 gen_helper_cu24(cc_op
, tcg_env
, tr1
, tr2
, chk
);
2289 gen_helper_cu41(cc_op
, tcg_env
, tr1
, tr2
, chk
);
2292 gen_helper_cu42(cc_op
, tcg_env
, tr1
, tr2
, chk
);
2295 g_assert_not_reached();
2302 #ifndef CONFIG_USER_ONLY
2303 static DisasJumpType
op_diag(DisasContext
*s
, DisasOps
*o
)
2305 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
2306 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
2307 TCGv_i32 func_code
= tcg_constant_i32(get_field(s
, i2
));
2309 gen_helper_diag(tcg_env
, r1
, r3
, func_code
);
2314 static DisasJumpType
op_divs32(DisasContext
*s
, DisasOps
*o
)
2316 gen_helper_divs32(o
->out
, tcg_env
, o
->in1
, o
->in2
);
2317 tcg_gen_extr32_i64(o
->out2
, o
->out
, o
->out
);
2321 static DisasJumpType
op_divu32(DisasContext
*s
, DisasOps
*o
)
2323 gen_helper_divu32(o
->out
, tcg_env
, o
->in1
, o
->in2
);
2324 tcg_gen_extr32_i64(o
->out2
, o
->out
, o
->out
);
2328 static DisasJumpType
op_divs64(DisasContext
*s
, DisasOps
*o
)
2330 TCGv_i128 t
= tcg_temp_new_i128();
2332 gen_helper_divs64(t
, tcg_env
, o
->in1
, o
->in2
);
2333 tcg_gen_extr_i128_i64(o
->out2
, o
->out
, t
);
2337 static DisasJumpType
op_divu64(DisasContext
*s
, DisasOps
*o
)
2339 TCGv_i128 t
= tcg_temp_new_i128();
2341 gen_helper_divu64(t
, tcg_env
, o
->out
, o
->out2
, o
->in2
);
2342 tcg_gen_extr_i128_i64(o
->out2
, o
->out
, t
);
2346 static DisasJumpType
op_deb(DisasContext
*s
, DisasOps
*o
)
2348 gen_helper_deb(o
->out
, tcg_env
, o
->in1
, o
->in2
);
2352 static DisasJumpType
op_ddb(DisasContext
*s
, DisasOps
*o
)
2354 gen_helper_ddb(o
->out
, tcg_env
, o
->in1
, o
->in2
);
2358 static DisasJumpType
op_dxb(DisasContext
*s
, DisasOps
*o
)
2360 gen_helper_dxb(o
->out_128
, tcg_env
, o
->in1_128
, o
->in2_128
);
2364 static DisasJumpType
op_ear(DisasContext
*s
, DisasOps
*o
)
2366 int r2
= get_field(s
, r2
);
2367 tcg_gen_ld32u_i64(o
->out
, tcg_env
, offsetof(CPUS390XState
, aregs
[r2
]));
2371 static DisasJumpType
op_ecag(DisasContext
*s
, DisasOps
*o
)
2373 /* No cache information provided. */
2374 tcg_gen_movi_i64(o
->out
, -1);
2378 static DisasJumpType
op_efpc(DisasContext
*s
, DisasOps
*o
)
2380 tcg_gen_ld32u_i64(o
->out
, tcg_env
, offsetof(CPUS390XState
, fpc
));
2384 static DisasJumpType
op_epsw(DisasContext
*s
, DisasOps
*o
)
2386 int r1
= get_field(s
, r1
);
2387 int r2
= get_field(s
, r2
);
2388 TCGv_i64 t
= tcg_temp_new_i64();
2389 TCGv_i64 t_cc
= tcg_temp_new_i64();
2391 /* Note the "subsequently" in the PoO, which implies a defined result
2392 if r1 == r2. Thus we cannot defer these writes to an output hook. */
2394 tcg_gen_extu_i32_i64(t_cc
, cc_op
);
2395 tcg_gen_shri_i64(t
, psw_mask
, 32);
2396 tcg_gen_deposit_i64(t
, t
, t_cc
, 12, 2);
2397 store_reg32_i64(r1
, t
);
2399 store_reg32_i64(r2
, psw_mask
);
2404 static DisasJumpType
op_ex(DisasContext
*s
, DisasOps
*o
)
2406 int r1
= get_field(s
, r1
);
2410 /* Nested EXECUTE is not allowed. */
2411 if (unlikely(s
->ex_value
)) {
2412 gen_program_exception(s
, PGM_EXECUTE
);
2413 return DISAS_NORETURN
;
2420 v1
= tcg_constant_i64(0);
2425 ilen
= tcg_constant_i32(s
->ilen
);
2426 gen_helper_ex(tcg_env
, ilen
, v1
, o
->in2
);
2428 return DISAS_PC_CC_UPDATED
;
2431 static DisasJumpType
op_fieb(DisasContext
*s
, DisasOps
*o
)
2433 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
2436 return DISAS_NORETURN
;
2438 gen_helper_fieb(o
->out
, tcg_env
, o
->in2
, m34
);
2442 static DisasJumpType
op_fidb(DisasContext
*s
, DisasOps
*o
)
2444 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
2447 return DISAS_NORETURN
;
2449 gen_helper_fidb(o
->out
, tcg_env
, o
->in2
, m34
);
2453 static DisasJumpType
op_fixb(DisasContext
*s
, DisasOps
*o
)
2455 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
2458 return DISAS_NORETURN
;
2460 gen_helper_fixb(o
->out_128
, tcg_env
, o
->in2_128
, m34
);
2464 static DisasJumpType
op_flogr(DisasContext
*s
, DisasOps
*o
)
2466 /* We'll use the original input for cc computation, since we get to
2467 compare that against 0, which ought to be better than comparing
2468 the real output against 64. It also lets cc_dst be a convenient
2469 temporary during our computation. */
2470 gen_op_update1_cc_i64(s
, CC_OP_FLOGR
, o
->in2
);
2472 /* R1 = IN ? CLZ(IN) : 64. */
2473 tcg_gen_clzi_i64(o
->out
, o
->in2
, 64);
2475 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2476 value by 64, which is undefined. But since the shift is 64 iff the
2477 input is zero, we still get the correct result after and'ing. */
2478 tcg_gen_movi_i64(o
->out2
, 0x8000000000000000ull
);
2479 tcg_gen_shr_i64(o
->out2
, o
->out2
, o
->out
);
2480 tcg_gen_andc_i64(o
->out2
, cc_dst
, o
->out2
);
2484 static DisasJumpType
op_icm(DisasContext
*s
, DisasOps
*o
)
2486 int m3
= get_field(s
, m3
);
2487 int pos
, len
, base
= s
->insn
->data
;
2488 TCGv_i64 tmp
= tcg_temp_new_i64();
2493 /* Effectively a 32-bit load. */
2494 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_TEUL
);
2501 /* Effectively a 16-bit load. */
2502 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_TEUW
);
2510 /* Effectively an 8-bit load. */
2511 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
2516 pos
= base
+ ctz32(m3
) * 8;
2517 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, len
);
2518 ccm
= ((1ull << len
) - 1) << pos
;
2522 /* Recognize access exceptions for the first byte. */
2523 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
2524 gen_op_movi_cc(s
, 0);
2528 /* This is going to be a sequence of loads and inserts. */
2529 pos
= base
+ 32 - 8;
2533 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
2534 tcg_gen_addi_i64(o
->in2
, o
->in2
, 1);
2535 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, 8);
2536 ccm
|= 0xffull
<< pos
;
2538 m3
= (m3
<< 1) & 0xf;
2544 tcg_gen_movi_i64(tmp
, ccm
);
2545 gen_op_update2_cc_i64(s
, CC_OP_ICM
, tmp
, o
->out
);
2549 static DisasJumpType
op_insi(DisasContext
*s
, DisasOps
*o
)
2551 int shift
= s
->insn
->data
& 0xff;
2552 int size
= s
->insn
->data
>> 8;
2553 tcg_gen_deposit_i64(o
->out
, o
->in1
, o
->in2
, shift
, size
);
2557 static DisasJumpType
op_ipm(DisasContext
*s
, DisasOps
*o
)
2562 t1
= tcg_temp_new_i64();
2563 tcg_gen_extract_i64(t1
, psw_mask
, 40, 4);
2564 t2
= tcg_temp_new_i64();
2565 tcg_gen_extu_i32_i64(t2
, cc_op
);
2566 tcg_gen_deposit_i64(t1
, t1
, t2
, 4, 60);
2567 tcg_gen_deposit_i64(o
->out
, o
->out
, t1
, 24, 8);
2571 #ifndef CONFIG_USER_ONLY
2572 static DisasJumpType
op_idte(DisasContext
*s
, DisasOps
*o
)
2576 if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING
)) {
2577 m4
= tcg_constant_i32(get_field(s
, m4
));
2579 m4
= tcg_constant_i32(0);
2581 gen_helper_idte(tcg_env
, o
->in1
, o
->in2
, m4
);
2585 static DisasJumpType
op_ipte(DisasContext
*s
, DisasOps
*o
)
2589 if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING
)) {
2590 m4
= tcg_constant_i32(get_field(s
, m4
));
2592 m4
= tcg_constant_i32(0);
2594 gen_helper_ipte(tcg_env
, o
->in1
, o
->in2
, m4
);
2598 static DisasJumpType
op_iske(DisasContext
*s
, DisasOps
*o
)
2600 gen_helper_iske(o
->out
, tcg_env
, o
->in2
);
2605 static DisasJumpType
op_msa(DisasContext
*s
, DisasOps
*o
)
2607 int r1
= have_field(s
, r1
) ? get_field(s
, r1
) : 0;
2608 int r2
= have_field(s
, r2
) ? get_field(s
, r2
) : 0;
2609 int r3
= have_field(s
, r3
) ? get_field(s
, r3
) : 0;
2610 TCGv_i32 t_r1
, t_r2
, t_r3
, type
;
2612 switch (s
->insn
->data
) {
2613 case S390_FEAT_TYPE_KMA
:
2614 if (r3
== r1
|| r3
== r2
) {
2615 gen_program_exception(s
, PGM_SPECIFICATION
);
2616 return DISAS_NORETURN
;
2619 case S390_FEAT_TYPE_KMCTR
:
2620 if (r3
& 1 || !r3
) {
2621 gen_program_exception(s
, PGM_SPECIFICATION
);
2622 return DISAS_NORETURN
;
2625 case S390_FEAT_TYPE_PPNO
:
2626 case S390_FEAT_TYPE_KMF
:
2627 case S390_FEAT_TYPE_KMC
:
2628 case S390_FEAT_TYPE_KMO
:
2629 case S390_FEAT_TYPE_KM
:
2630 if (r1
& 1 || !r1
) {
2631 gen_program_exception(s
, PGM_SPECIFICATION
);
2632 return DISAS_NORETURN
;
2635 case S390_FEAT_TYPE_KMAC
:
2636 case S390_FEAT_TYPE_KIMD
:
2637 case S390_FEAT_TYPE_KLMD
:
2638 if (r2
& 1 || !r2
) {
2639 gen_program_exception(s
, PGM_SPECIFICATION
);
2640 return DISAS_NORETURN
;
2643 case S390_FEAT_TYPE_PCKMO
:
2644 case S390_FEAT_TYPE_PCC
:
2647 g_assert_not_reached();
2650 t_r1
= tcg_constant_i32(r1
);
2651 t_r2
= tcg_constant_i32(r2
);
2652 t_r3
= tcg_constant_i32(r3
);
2653 type
= tcg_constant_i32(s
->insn
->data
);
2654 gen_helper_msa(cc_op
, tcg_env
, t_r1
, t_r2
, t_r3
, type
);
2659 static DisasJumpType
op_keb(DisasContext
*s
, DisasOps
*o
)
2661 gen_helper_keb(cc_op
, tcg_env
, o
->in1
, o
->in2
);
2666 static DisasJumpType
op_kdb(DisasContext
*s
, DisasOps
*o
)
2668 gen_helper_kdb(cc_op
, tcg_env
, o
->in1
, o
->in2
);
2673 static DisasJumpType
op_kxb(DisasContext
*s
, DisasOps
*o
)
2675 gen_helper_kxb(cc_op
, tcg_env
, o
->in1_128
, o
->in2_128
);
2680 static DisasJumpType
help_laa(DisasContext
*s
, DisasOps
*o
, bool addu64
)
2682 /* The real output is indeed the original value in memory;
2683 recompute the addition for the computation of CC. */
2684 tcg_gen_atomic_fetch_add_i64(o
->in2
, o
->in2
, o
->in1
, get_mem_index(s
),
2685 s
->insn
->data
| MO_ALIGN
);
2686 /* However, we need to recompute the addition for setting CC. */
2688 tcg_gen_movi_i64(cc_src
, 0);
2689 tcg_gen_add2_i64(o
->out
, cc_src
, o
->in1
, cc_src
, o
->in2
, cc_src
);
2691 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
2696 static DisasJumpType
op_laa(DisasContext
*s
, DisasOps
*o
)
2698 return help_laa(s
, o
, false);
2701 static DisasJumpType
op_laa_addu64(DisasContext
*s
, DisasOps
*o
)
2703 return help_laa(s
, o
, true);
2706 static DisasJumpType
op_lan(DisasContext
*s
, DisasOps
*o
)
2708 /* The real output is indeed the original value in memory;
2709 recompute the addition for the computation of CC. */
2710 tcg_gen_atomic_fetch_and_i64(o
->in2
, o
->in2
, o
->in1
, get_mem_index(s
),
2711 s
->insn
->data
| MO_ALIGN
);
2712 /* However, we need to recompute the operation for setting CC. */
2713 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
2717 static DisasJumpType
op_lao(DisasContext
*s
, DisasOps
*o
)
2719 /* The real output is indeed the original value in memory;
2720 recompute the addition for the computation of CC. */
2721 tcg_gen_atomic_fetch_or_i64(o
->in2
, o
->in2
, o
->in1
, get_mem_index(s
),
2722 s
->insn
->data
| MO_ALIGN
);
2723 /* However, we need to recompute the operation for setting CC. */
2724 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
2728 static DisasJumpType
op_lax(DisasContext
*s
, DisasOps
*o
)
2730 /* The real output is indeed the original value in memory;
2731 recompute the addition for the computation of CC. */
2732 tcg_gen_atomic_fetch_xor_i64(o
->in2
, o
->in2
, o
->in1
, get_mem_index(s
),
2733 s
->insn
->data
| MO_ALIGN
);
2734 /* However, we need to recompute the operation for setting CC. */
2735 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
2739 static DisasJumpType
op_ldeb(DisasContext
*s
, DisasOps
*o
)
2741 gen_helper_ldeb(o
->out
, tcg_env
, o
->in2
);
2745 static DisasJumpType
op_ledb(DisasContext
*s
, DisasOps
*o
)
2747 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
2750 return DISAS_NORETURN
;
2752 gen_helper_ledb(o
->out
, tcg_env
, o
->in2
, m34
);
2756 static DisasJumpType
op_ldxb(DisasContext
*s
, DisasOps
*o
)
2758 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
2761 return DISAS_NORETURN
;
2763 gen_helper_ldxb(o
->out
, tcg_env
, o
->in2_128
, m34
);
2767 static DisasJumpType
op_lexb(DisasContext
*s
, DisasOps
*o
)
2769 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
2772 return DISAS_NORETURN
;
2774 gen_helper_lexb(o
->out
, tcg_env
, o
->in2_128
, m34
);
2778 static DisasJumpType
op_lxdb(DisasContext
*s
, DisasOps
*o
)
2780 gen_helper_lxdb(o
->out_128
, tcg_env
, o
->in2
);
2784 static DisasJumpType
op_lxeb(DisasContext
*s
, DisasOps
*o
)
2786 gen_helper_lxeb(o
->out_128
, tcg_env
, o
->in2
);
2790 static DisasJumpType
op_lde(DisasContext
*s
, DisasOps
*o
)
2792 tcg_gen_shli_i64(o
->out
, o
->in2
, 32);
2796 static DisasJumpType
op_llgt(DisasContext
*s
, DisasOps
*o
)
2798 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffff);
2802 static DisasJumpType
op_ld8s(DisasContext
*s
, DisasOps
*o
)
2804 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_SB
);
2808 static DisasJumpType
op_ld8u(DisasContext
*s
, DisasOps
*o
)
2810 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_UB
);
2814 static DisasJumpType
op_ld16s(DisasContext
*s
, DisasOps
*o
)
2816 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TESW
);
2820 static DisasJumpType
op_ld16u(DisasContext
*s
, DisasOps
*o
)
2822 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TEUW
);
2826 static DisasJumpType
op_ld32s(DisasContext
*s
, DisasOps
*o
)
2828 tcg_gen_qemu_ld_tl(o
->out
, o
->in2
, get_mem_index(s
),
2829 MO_TESL
| s
->insn
->data
);
2833 static DisasJumpType
op_ld32u(DisasContext
*s
, DisasOps
*o
)
2835 tcg_gen_qemu_ld_tl(o
->out
, o
->in2
, get_mem_index(s
),
2836 MO_TEUL
| s
->insn
->data
);
2840 static DisasJumpType
op_ld64(DisasContext
*s
, DisasOps
*o
)
2842 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
),
2843 MO_TEUQ
| s
->insn
->data
);
2847 static DisasJumpType
op_lat(DisasContext
*s
, DisasOps
*o
)
2849 TCGLabel
*lab
= gen_new_label();
2850 store_reg32_i64(get_field(s
, r1
), o
->in2
);
2851 /* The value is stored even in case of trap. */
2852 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->in2
, 0, lab
);
2858 static DisasJumpType
op_lgat(DisasContext
*s
, DisasOps
*o
)
2860 TCGLabel
*lab
= gen_new_label();
2861 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
2862 /* The value is stored even in case of trap. */
2863 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->out
, 0, lab
);
2869 static DisasJumpType
op_lfhat(DisasContext
*s
, DisasOps
*o
)
2871 TCGLabel
*lab
= gen_new_label();
2872 store_reg32h_i64(get_field(s
, r1
), o
->in2
);
2873 /* The value is stored even in case of trap. */
2874 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->in2
, 0, lab
);
2880 static DisasJumpType
op_llgfat(DisasContext
*s
, DisasOps
*o
)
2882 TCGLabel
*lab
= gen_new_label();
2884 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TEUL
);
2885 /* The value is stored even in case of trap. */
2886 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->out
, 0, lab
);
2892 static DisasJumpType
op_llgtat(DisasContext
*s
, DisasOps
*o
)
2894 TCGLabel
*lab
= gen_new_label();
2895 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffff);
2896 /* The value is stored even in case of trap. */
2897 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->out
, 0, lab
);
2903 static DisasJumpType
op_loc(DisasContext
*s
, DisasOps
*o
)
2907 if (have_field(s
, m3
)) {
2908 /* LOAD * ON CONDITION */
2909 disas_jcc(s
, &c
, get_field(s
, m3
));
2912 disas_jcc(s
, &c
, get_field(s
, m4
));
2916 tcg_gen_movcond_i64(c
.cond
, o
->out
, c
.u
.s64
.a
, c
.u
.s64
.b
,
2919 TCGv_i32 t32
= tcg_temp_new_i32();
2922 tcg_gen_setcond_i32(c
.cond
, t32
, c
.u
.s32
.a
, c
.u
.s32
.b
);
2924 t
= tcg_temp_new_i64();
2925 tcg_gen_extu_i32_i64(t
, t32
);
2927 z
= tcg_constant_i64(0);
2928 tcg_gen_movcond_i64(TCG_COND_NE
, o
->out
, t
, z
, o
->in2
, o
->in1
);
2934 #ifndef CONFIG_USER_ONLY
2935 static DisasJumpType
op_lctl(DisasContext
*s
, DisasOps
*o
)
2937 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
2938 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
2940 gen_helper_lctl(tcg_env
, r1
, o
->in2
, r3
);
2941 /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
2942 s
->exit_to_mainloop
= true;
2943 return DISAS_TOO_MANY
;
2946 static DisasJumpType
op_lctlg(DisasContext
*s
, DisasOps
*o
)
2948 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
2949 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
2951 gen_helper_lctlg(tcg_env
, r1
, o
->in2
, r3
);
2952 /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
2953 s
->exit_to_mainloop
= true;
2954 return DISAS_TOO_MANY
;
2957 static DisasJumpType
op_lra(DisasContext
*s
, DisasOps
*o
)
2959 gen_helper_lra(o
->out
, tcg_env
, o
->out
, o
->in2
);
2964 static DisasJumpType
op_lpp(DisasContext
*s
, DisasOps
*o
)
2966 tcg_gen_st_i64(o
->in2
, tcg_env
, offsetof(CPUS390XState
, pp
));
2970 static DisasJumpType
op_lpsw(DisasContext
*s
, DisasOps
*o
)
2972 TCGv_i64 mask
, addr
;
2974 per_breaking_event(s
);
2977 * Convert the short PSW into the normal PSW, similar to what
2978 * s390_cpu_load_normal() does.
2980 mask
= tcg_temp_new_i64();
2981 addr
= tcg_temp_new_i64();
2982 tcg_gen_qemu_ld_i64(mask
, o
->in2
, get_mem_index(s
), MO_TEUQ
| MO_ALIGN_8
);
2983 tcg_gen_andi_i64(addr
, mask
, PSW_MASK_SHORT_ADDR
);
2984 tcg_gen_andi_i64(mask
, mask
, PSW_MASK_SHORT_CTRL
);
2985 tcg_gen_xori_i64(mask
, mask
, PSW_MASK_SHORTPSW
);
2986 gen_helper_load_psw(tcg_env
, mask
, addr
);
2987 return DISAS_NORETURN
;
2990 static DisasJumpType
op_lpswe(DisasContext
*s
, DisasOps
*o
)
2994 per_breaking_event(s
);
2996 t1
= tcg_temp_new_i64();
2997 t2
= tcg_temp_new_i64();
2998 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
),
2999 MO_TEUQ
| MO_ALIGN_8
);
3000 tcg_gen_addi_i64(o
->in2
, o
->in2
, 8);
3001 tcg_gen_qemu_ld_i64(t2
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
3002 gen_helper_load_psw(tcg_env
, t1
, t2
);
3003 return DISAS_NORETURN
;
3007 static DisasJumpType
op_lam(DisasContext
*s
, DisasOps
*o
)
3009 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
3010 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
3012 gen_helper_lam(tcg_env
, r1
, o
->in2
, r3
);
3016 static DisasJumpType
op_lm32(DisasContext
*s
, DisasOps
*o
)
3018 int r1
= get_field(s
, r1
);
3019 int r3
= get_field(s
, r3
);
3022 /* Only one register to read. */
3023 t1
= tcg_temp_new_i64();
3024 if (unlikely(r1
== r3
)) {
3025 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3026 store_reg32_i64(r1
, t1
);
3030 /* First load the values of the first and last registers to trigger
3031 possible page faults. */
3032 t2
= tcg_temp_new_i64();
3033 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3034 tcg_gen_addi_i64(t2
, o
->in2
, 4 * ((r3
- r1
) & 15));
3035 tcg_gen_qemu_ld_i64(t2
, t2
, get_mem_index(s
), MO_TEUL
);
3036 store_reg32_i64(r1
, t1
);
3037 store_reg32_i64(r3
, t2
);
3039 /* Only two registers to read. */
3040 if (((r1
+ 1) & 15) == r3
) {
3044 /* Then load the remaining registers. Page fault can't occur. */
3046 tcg_gen_movi_i64(t2
, 4);
3049 tcg_gen_add_i64(o
->in2
, o
->in2
, t2
);
3050 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3051 store_reg32_i64(r1
, t1
);
3056 static DisasJumpType
op_lmh(DisasContext
*s
, DisasOps
*o
)
3058 int r1
= get_field(s
, r1
);
3059 int r3
= get_field(s
, r3
);
3062 /* Only one register to read. */
3063 t1
= tcg_temp_new_i64();
3064 if (unlikely(r1
== r3
)) {
3065 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3066 store_reg32h_i64(r1
, t1
);
3070 /* First load the values of the first and last registers to trigger
3071 possible page faults. */
3072 t2
= tcg_temp_new_i64();
3073 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3074 tcg_gen_addi_i64(t2
, o
->in2
, 4 * ((r3
- r1
) & 15));
3075 tcg_gen_qemu_ld_i64(t2
, t2
, get_mem_index(s
), MO_TEUL
);
3076 store_reg32h_i64(r1
, t1
);
3077 store_reg32h_i64(r3
, t2
);
3079 /* Only two registers to read. */
3080 if (((r1
+ 1) & 15) == r3
) {
3084 /* Then load the remaining registers. Page fault can't occur. */
3086 tcg_gen_movi_i64(t2
, 4);
3089 tcg_gen_add_i64(o
->in2
, o
->in2
, t2
);
3090 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3091 store_reg32h_i64(r1
, t1
);
3096 static DisasJumpType
op_lm64(DisasContext
*s
, DisasOps
*o
)
3098 int r1
= get_field(s
, r1
);
3099 int r3
= get_field(s
, r3
);
3102 /* Only one register to read. */
3103 if (unlikely(r1
== r3
)) {
3104 tcg_gen_qemu_ld_i64(regs
[r1
], o
->in2
, get_mem_index(s
), MO_TEUQ
);
3108 /* First load the values of the first and last registers to trigger
3109 possible page faults. */
3110 t1
= tcg_temp_new_i64();
3111 t2
= tcg_temp_new_i64();
3112 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
3113 tcg_gen_addi_i64(t2
, o
->in2
, 8 * ((r3
- r1
) & 15));
3114 tcg_gen_qemu_ld_i64(regs
[r3
], t2
, get_mem_index(s
), MO_TEUQ
);
3115 tcg_gen_mov_i64(regs
[r1
], t1
);
3117 /* Only two registers to read. */
3118 if (((r1
+ 1) & 15) == r3
) {
3122 /* Then load the remaining registers. Page fault can't occur. */
3124 tcg_gen_movi_i64(t1
, 8);
3127 tcg_gen_add_i64(o
->in2
, o
->in2
, t1
);
3128 tcg_gen_qemu_ld_i64(regs
[r1
], o
->in2
, get_mem_index(s
), MO_TEUQ
);
3133 static DisasJumpType
op_lpd(DisasContext
*s
, DisasOps
*o
)
3136 MemOp mop
= s
->insn
->data
;
3138 /* In a parallel context, stop the world and single step. */
3139 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
3142 gen_exception(EXCP_ATOMIC
);
3143 return DISAS_NORETURN
;
3146 /* In a serial context, perform the two loads ... */
3147 a1
= get_address(s
, 0, get_field(s
, b1
), get_field(s
, d1
));
3148 a2
= get_address(s
, 0, get_field(s
, b2
), get_field(s
, d2
));
3149 tcg_gen_qemu_ld_i64(o
->out
, a1
, get_mem_index(s
), mop
| MO_ALIGN
);
3150 tcg_gen_qemu_ld_i64(o
->out2
, a2
, get_mem_index(s
), mop
| MO_ALIGN
);
3152 /* ... and indicate that we performed them while interlocked. */
3153 gen_op_movi_cc(s
, 0);
3157 static DisasJumpType
op_lpq(DisasContext
*s
, DisasOps
*o
)
3159 o
->out_128
= tcg_temp_new_i128();
3160 tcg_gen_qemu_ld_i128(o
->out_128
, o
->in2
, get_mem_index(s
),
3161 MO_TE
| MO_128
| MO_ALIGN
);
3165 #ifndef CONFIG_USER_ONLY
3166 static DisasJumpType
op_lura(DisasContext
*s
, DisasOps
*o
)
3168 tcg_gen_qemu_ld_tl(o
->out
, o
->in2
, MMU_REAL_IDX
, s
->insn
->data
);
3173 static DisasJumpType
op_lzrb(DisasContext
*s
, DisasOps
*o
)
3175 tcg_gen_andi_i64(o
->out
, o
->in2
, -256);
3179 static DisasJumpType
op_lcbb(DisasContext
*s
, DisasOps
*o
)
3181 const int64_t block_size
= (1ull << (get_field(s
, m3
) + 6));
3183 if (get_field(s
, m3
) > 6) {
3184 gen_program_exception(s
, PGM_SPECIFICATION
);
3185 return DISAS_NORETURN
;
3188 tcg_gen_ori_i64(o
->addr1
, o
->addr1
, -block_size
);
3189 tcg_gen_neg_i64(o
->addr1
, o
->addr1
);
3190 tcg_gen_movi_i64(o
->out
, 16);
3191 tcg_gen_umin_i64(o
->out
, o
->out
, o
->addr1
);
3192 gen_op_update1_cc_i64(s
, CC_OP_LCBB
, o
->out
);
3196 static DisasJumpType
op_mc(DisasContext
*s
, DisasOps
*o
)
3198 const uint8_t monitor_class
= get_field(s
, i2
);
3200 if (monitor_class
& 0xf0) {
3201 gen_program_exception(s
, PGM_SPECIFICATION
);
3202 return DISAS_NORETURN
;
3205 #if !defined(CONFIG_USER_ONLY)
3206 gen_helper_monitor_call(tcg_env
, o
->addr1
,
3207 tcg_constant_i32(monitor_class
));
3209 /* Defaults to a NOP. */
3213 static DisasJumpType
op_mov2(DisasContext
*s
, DisasOps
*o
)
3220 static DisasJumpType
op_mov2e(DisasContext
*s
, DisasOps
*o
)
3222 int b2
= get_field(s
, b2
);
3223 TCGv ar1
= tcg_temp_new_i64();
3224 int r1
= get_field(s
, r1
);
3229 switch (s
->base
.tb
->flags
& FLAG_MASK_ASC
) {
3230 case PSW_ASC_PRIMARY
>> FLAG_MASK_PSW_SHIFT
:
3231 tcg_gen_movi_i64(ar1
, 0);
3233 case PSW_ASC_ACCREG
>> FLAG_MASK_PSW_SHIFT
:
3234 tcg_gen_movi_i64(ar1
, 1);
3236 case PSW_ASC_SECONDARY
>> FLAG_MASK_PSW_SHIFT
:
3238 tcg_gen_ld32u_i64(ar1
, tcg_env
, offsetof(CPUS390XState
, aregs
[b2
]));
3240 tcg_gen_movi_i64(ar1
, 0);
3243 case PSW_ASC_HOME
>> FLAG_MASK_PSW_SHIFT
:
3244 tcg_gen_movi_i64(ar1
, 2);
3248 tcg_gen_st32_i64(ar1
, tcg_env
, offsetof(CPUS390XState
, aregs
[r1
]));
3252 static DisasJumpType
op_movx(DisasContext
*s
, DisasOps
*o
)
3261 static DisasJumpType
op_mvc(DisasContext
*s
, DisasOps
*o
)
3263 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3265 gen_helper_mvc(tcg_env
, l
, o
->addr1
, o
->in2
);
3269 static DisasJumpType
op_mvcrl(DisasContext
*s
, DisasOps
*o
)
3271 gen_helper_mvcrl(tcg_env
, regs
[0], o
->addr1
, o
->in2
);
3275 static DisasJumpType
op_mvcin(DisasContext
*s
, DisasOps
*o
)
3277 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3279 gen_helper_mvcin(tcg_env
, l
, o
->addr1
, o
->in2
);
3283 static DisasJumpType
op_mvcl(DisasContext
*s
, DisasOps
*o
)
3285 int r1
= get_field(s
, r1
);
3286 int r2
= get_field(s
, r2
);
3289 /* r1 and r2 must be even. */
3290 if (r1
& 1 || r2
& 1) {
3291 gen_program_exception(s
, PGM_SPECIFICATION
);
3292 return DISAS_NORETURN
;
3295 t1
= tcg_constant_i32(r1
);
3296 t2
= tcg_constant_i32(r2
);
3297 gen_helper_mvcl(cc_op
, tcg_env
, t1
, t2
);
3302 static DisasJumpType
op_mvcle(DisasContext
*s
, DisasOps
*o
)
3304 int r1
= get_field(s
, r1
);
3305 int r3
= get_field(s
, r3
);
3308 /* r1 and r3 must be even. */
3309 if (r1
& 1 || r3
& 1) {
3310 gen_program_exception(s
, PGM_SPECIFICATION
);
3311 return DISAS_NORETURN
;
3314 t1
= tcg_constant_i32(r1
);
3315 t3
= tcg_constant_i32(r3
);
3316 gen_helper_mvcle(cc_op
, tcg_env
, t1
, o
->in2
, t3
);
3321 static DisasJumpType
op_mvclu(DisasContext
*s
, DisasOps
*o
)
3323 int r1
= get_field(s
, r1
);
3324 int r3
= get_field(s
, r3
);
3327 /* r1 and r3 must be even. */
3328 if (r1
& 1 || r3
& 1) {
3329 gen_program_exception(s
, PGM_SPECIFICATION
);
3330 return DISAS_NORETURN
;
3333 t1
= tcg_constant_i32(r1
);
3334 t3
= tcg_constant_i32(r3
);
3335 gen_helper_mvclu(cc_op
, tcg_env
, t1
, o
->in2
, t3
);
3340 static DisasJumpType
op_mvcos(DisasContext
*s
, DisasOps
*o
)
3342 int r3
= get_field(s
, r3
);
3343 gen_helper_mvcos(cc_op
, tcg_env
, o
->addr1
, o
->in2
, regs
[r3
]);
3348 #ifndef CONFIG_USER_ONLY
3349 static DisasJumpType
op_mvcp(DisasContext
*s
, DisasOps
*o
)
3351 int r1
= get_field(s
, l1
);
3352 int r3
= get_field(s
, r3
);
3353 gen_helper_mvcp(cc_op
, tcg_env
, regs
[r1
], o
->addr1
, o
->in2
, regs
[r3
]);
3358 static DisasJumpType
op_mvcs(DisasContext
*s
, DisasOps
*o
)
3360 int r1
= get_field(s
, l1
);
3361 int r3
= get_field(s
, r3
);
3362 gen_helper_mvcs(cc_op
, tcg_env
, regs
[r1
], o
->addr1
, o
->in2
, regs
[r3
]);
3368 static DisasJumpType
op_mvn(DisasContext
*s
, DisasOps
*o
)
3370 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3372 gen_helper_mvn(tcg_env
, l
, o
->addr1
, o
->in2
);
3376 static DisasJumpType
op_mvo(DisasContext
*s
, DisasOps
*o
)
3378 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3380 gen_helper_mvo(tcg_env
, l
, o
->addr1
, o
->in2
);
3384 static DisasJumpType
op_mvpg(DisasContext
*s
, DisasOps
*o
)
3386 TCGv_i32 t1
= tcg_constant_i32(get_field(s
, r1
));
3387 TCGv_i32 t2
= tcg_constant_i32(get_field(s
, r2
));
3389 gen_helper_mvpg(cc_op
, tcg_env
, regs
[0], t1
, t2
);
3394 static DisasJumpType
op_mvst(DisasContext
*s
, DisasOps
*o
)
3396 TCGv_i32 t1
= tcg_constant_i32(get_field(s
, r1
));
3397 TCGv_i32 t2
= tcg_constant_i32(get_field(s
, r2
));
3399 gen_helper_mvst(cc_op
, tcg_env
, t1
, t2
);
3404 static DisasJumpType
op_mvz(DisasContext
*s
, DisasOps
*o
)
3406 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3408 gen_helper_mvz(tcg_env
, l
, o
->addr1
, o
->in2
);
3412 static DisasJumpType
op_mul(DisasContext
*s
, DisasOps
*o
)
3414 tcg_gen_mul_i64(o
->out
, o
->in1
, o
->in2
);
3418 static DisasJumpType
op_mul128(DisasContext
*s
, DisasOps
*o
)
3420 tcg_gen_mulu2_i64(o
->out2
, o
->out
, o
->in1
, o
->in2
);
3424 static DisasJumpType
op_muls128(DisasContext
*s
, DisasOps
*o
)
3426 tcg_gen_muls2_i64(o
->out2
, o
->out
, o
->in1
, o
->in2
);
3430 static DisasJumpType
op_meeb(DisasContext
*s
, DisasOps
*o
)
3432 gen_helper_meeb(o
->out
, tcg_env
, o
->in1
, o
->in2
);
3436 static DisasJumpType
op_mdeb(DisasContext
*s
, DisasOps
*o
)
3438 gen_helper_mdeb(o
->out
, tcg_env
, o
->in1
, o
->in2
);
3442 static DisasJumpType
op_mdb(DisasContext
*s
, DisasOps
*o
)
3444 gen_helper_mdb(o
->out
, tcg_env
, o
->in1
, o
->in2
);
3448 static DisasJumpType
op_mxb(DisasContext
*s
, DisasOps
*o
)
3450 gen_helper_mxb(o
->out_128
, tcg_env
, o
->in1_128
, o
->in2_128
);
3454 static DisasJumpType
op_mxdb(DisasContext
*s
, DisasOps
*o
)
3456 gen_helper_mxdb(o
->out_128
, tcg_env
, o
->in1
, o
->in2
);
3460 static DisasJumpType
op_maeb(DisasContext
*s
, DisasOps
*o
)
3462 TCGv_i64 r3
= load_freg32_i64(get_field(s
, r3
));
3463 gen_helper_maeb(o
->out
, tcg_env
, o
->in1
, o
->in2
, r3
);
3467 static DisasJumpType
op_madb(DisasContext
*s
, DisasOps
*o
)
3469 TCGv_i64 r3
= load_freg(get_field(s
, r3
));
3470 gen_helper_madb(o
->out
, tcg_env
, o
->in1
, o
->in2
, r3
);
3474 static DisasJumpType
op_mseb(DisasContext
*s
, DisasOps
*o
)
3476 TCGv_i64 r3
= load_freg32_i64(get_field(s
, r3
));
3477 gen_helper_mseb(o
->out
, tcg_env
, o
->in1
, o
->in2
, r3
);
3481 static DisasJumpType
op_msdb(DisasContext
*s
, DisasOps
*o
)
3483 TCGv_i64 r3
= load_freg(get_field(s
, r3
));
3484 gen_helper_msdb(o
->out
, tcg_env
, o
->in1
, o
->in2
, r3
);
3488 static DisasJumpType
op_nabs(DisasContext
*s
, DisasOps
*o
)
3490 TCGv_i64 z
= tcg_constant_i64(0);
3491 TCGv_i64 n
= tcg_temp_new_i64();
3493 tcg_gen_neg_i64(n
, o
->in2
);
3494 tcg_gen_movcond_i64(TCG_COND_GE
, o
->out
, o
->in2
, z
, n
, o
->in2
);
3498 static DisasJumpType
op_nabsf32(DisasContext
*s
, DisasOps
*o
)
3500 tcg_gen_ori_i64(o
->out
, o
->in2
, 0x80000000ull
);
3504 static DisasJumpType
op_nabsf64(DisasContext
*s
, DisasOps
*o
)
3506 tcg_gen_ori_i64(o
->out
, o
->in2
, 0x8000000000000000ull
);
3510 static DisasJumpType
op_nabsf128(DisasContext
*s
, DisasOps
*o
)
3512 tcg_gen_ori_i64(o
->out
, o
->in1
, 0x8000000000000000ull
);
3513 tcg_gen_mov_i64(o
->out2
, o
->in2
);
3517 static DisasJumpType
op_nc(DisasContext
*s
, DisasOps
*o
)
3519 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3521 gen_helper_nc(cc_op
, tcg_env
, l
, o
->addr1
, o
->in2
);
3526 static DisasJumpType
op_neg(DisasContext
*s
, DisasOps
*o
)
3528 tcg_gen_neg_i64(o
->out
, o
->in2
);
3532 static DisasJumpType
op_negf32(DisasContext
*s
, DisasOps
*o
)
3534 tcg_gen_xori_i64(o
->out
, o
->in2
, 0x80000000ull
);
3538 static DisasJumpType
op_negf64(DisasContext
*s
, DisasOps
*o
)
3540 tcg_gen_xori_i64(o
->out
, o
->in2
, 0x8000000000000000ull
);
3544 static DisasJumpType
op_negf128(DisasContext
*s
, DisasOps
*o
)
3546 tcg_gen_xori_i64(o
->out
, o
->in1
, 0x8000000000000000ull
);
3547 tcg_gen_mov_i64(o
->out2
, o
->in2
);
3551 static DisasJumpType
op_oc(DisasContext
*s
, DisasOps
*o
)
3553 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3555 gen_helper_oc(cc_op
, tcg_env
, l
, o
->addr1
, o
->in2
);
3560 static DisasJumpType
op_or(DisasContext
*s
, DisasOps
*o
)
3562 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
3566 static DisasJumpType
op_ori(DisasContext
*s
, DisasOps
*o
)
3568 int shift
= s
->insn
->data
& 0xff;
3569 int size
= s
->insn
->data
>> 8;
3570 uint64_t mask
= ((1ull << size
) - 1) << shift
;
3571 TCGv_i64 t
= tcg_temp_new_i64();
3573 tcg_gen_shli_i64(t
, o
->in2
, shift
);
3574 tcg_gen_or_i64(o
->out
, o
->in1
, t
);
3576 /* Produce the CC from only the bits manipulated. */
3577 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
3578 set_cc_nz_u64(s
, cc_dst
);
3582 static DisasJumpType
op_oi(DisasContext
*s
, DisasOps
*o
)
3584 o
->in1
= tcg_temp_new_i64();
3586 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
3587 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
3589 /* Perform the atomic operation in memory. */
3590 tcg_gen_atomic_fetch_or_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
3594 /* Recompute also for atomic case: needed for setting CC. */
3595 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
3597 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
3598 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
3603 static DisasJumpType
op_pack(DisasContext
*s
, DisasOps
*o
)
3605 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3607 gen_helper_pack(tcg_env
, l
, o
->addr1
, o
->in2
);
3611 static DisasJumpType
op_pka(DisasContext
*s
, DisasOps
*o
)
3613 int l2
= get_field(s
, l2
) + 1;
3616 /* The length must not exceed 32 bytes. */
3618 gen_program_exception(s
, PGM_SPECIFICATION
);
3619 return DISAS_NORETURN
;
3621 l
= tcg_constant_i32(l2
);
3622 gen_helper_pka(tcg_env
, o
->addr1
, o
->in2
, l
);
3626 static DisasJumpType
op_pku(DisasContext
*s
, DisasOps
*o
)
3628 int l2
= get_field(s
, l2
) + 1;
3631 /* The length must be even and should not exceed 64 bytes. */
3632 if ((l2
& 1) || (l2
> 64)) {
3633 gen_program_exception(s
, PGM_SPECIFICATION
);
3634 return DISAS_NORETURN
;
3636 l
= tcg_constant_i32(l2
);
3637 gen_helper_pku(tcg_env
, o
->addr1
, o
->in2
, l
);
3641 static DisasJumpType
op_popcnt(DisasContext
*s
, DisasOps
*o
)
3643 const uint8_t m3
= get_field(s
, m3
);
3645 if ((m3
& 8) && s390_has_feat(S390_FEAT_MISC_INSTRUCTION_EXT3
)) {
3646 tcg_gen_ctpop_i64(o
->out
, o
->in2
);
3648 gen_helper_popcnt(o
->out
, o
->in2
);
3653 #ifndef CONFIG_USER_ONLY
3654 static DisasJumpType
op_ptlb(DisasContext
*s
, DisasOps
*o
)
3656 gen_helper_ptlb(tcg_env
);
3661 static DisasJumpType
op_risbg(DisasContext
*s
, DisasOps
*o
)
3663 int i3
= get_field(s
, i3
);
3664 int i4
= get_field(s
, i4
);
3665 int i5
= get_field(s
, i5
);
3666 int do_zero
= i4
& 0x80;
3667 uint64_t mask
, imask
, pmask
;
3670 /* Adjust the arguments for the specific insn. */
3671 switch (s
->fields
.op2
) {
3672 case 0x55: /* risbg */
3673 case 0x59: /* risbgn */
3678 case 0x5d: /* risbhg */
3681 pmask
= 0xffffffff00000000ull
;
3683 case 0x51: /* risblg */
3684 i3
= (i3
& 31) + 32;
3685 i4
= (i4
& 31) + 32;
3686 pmask
= 0x00000000ffffffffull
;
3689 g_assert_not_reached();
3692 /* MASK is the set of bits to be inserted from R2. */
3694 /* [0...i3---i4...63] */
3695 mask
= (-1ull >> i3
) & (-1ull << (63 - i4
));
3697 /* [0---i4...i3---63] */
3698 mask
= (-1ull >> i3
) | (-1ull << (63 - i4
));
3700 /* For RISBLG/RISBHG, the wrapping is limited to the high/low doubleword. */
3703 /* IMASK is the set of bits to be kept from R1. In the case of the high/low
3704 insns, we need to keep the other half of the register. */
3705 imask
= ~mask
| ~pmask
;
3714 /* In some cases we can implement this with extract. */
3715 if (imask
== 0 && pos
== 0 && len
> 0 && len
<= rot
) {
3716 tcg_gen_extract_i64(o
->out
, o
->in2
, 64 - rot
, len
);
3720 /* In some cases we can implement this with deposit. */
3721 if (len
> 0 && (imask
== 0 || ~mask
== imask
)) {
3722 /* Note that we rotate the bits to be inserted to the lsb, not to
3723 the position as described in the PoO. */
3724 rot
= (rot
- pos
) & 63;
3729 /* Rotate the input as necessary. */
3730 tcg_gen_rotli_i64(o
->in2
, o
->in2
, rot
);
3732 /* Insert the selected bits into the output. */
3735 tcg_gen_deposit_z_i64(o
->out
, o
->in2
, pos
, len
);
3737 tcg_gen_deposit_i64(o
->out
, o
->out
, o
->in2
, pos
, len
);
3739 } else if (imask
== 0) {
3740 tcg_gen_andi_i64(o
->out
, o
->in2
, mask
);
3742 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
3743 tcg_gen_andi_i64(o
->out
, o
->out
, imask
);
3744 tcg_gen_or_i64(o
->out
, o
->out
, o
->in2
);
3749 static DisasJumpType
op_rosbg(DisasContext
*s
, DisasOps
*o
)
3751 int i3
= get_field(s
, i3
);
3752 int i4
= get_field(s
, i4
);
3753 int i5
= get_field(s
, i5
);
3757 /* If this is a test-only form, arrange to discard the result. */
3759 tcg_debug_assert(o
->out
!= NULL
);
3761 o
->out
= tcg_temp_new_i64();
3762 tcg_gen_mov_i64(o
->out
, orig_out
);
3769 /* MASK is the set of bits to be operated on from R2.
3770 Take care for I3/I4 wraparound. */
3773 mask
^= ~0ull >> i4
>> 1;
3775 mask
|= ~(~0ull >> i4
>> 1);
3778 /* Rotate the input as necessary. */
3779 tcg_gen_rotli_i64(o
->in2
, o
->in2
, i5
);
3782 switch (s
->fields
.op2
) {
3783 case 0x54: /* AND */
3784 tcg_gen_ori_i64(o
->in2
, o
->in2
, ~mask
);
3785 tcg_gen_and_i64(o
->out
, o
->out
, o
->in2
);
3788 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
3789 tcg_gen_or_i64(o
->out
, o
->out
, o
->in2
);
3791 case 0x57: /* XOR */
3792 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
3793 tcg_gen_xor_i64(o
->out
, o
->out
, o
->in2
);
3800 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
3801 set_cc_nz_u64(s
, cc_dst
);
3805 static DisasJumpType
op_rev16(DisasContext
*s
, DisasOps
*o
)
3807 tcg_gen_bswap16_i64(o
->out
, o
->in2
, TCG_BSWAP_IZ
| TCG_BSWAP_OZ
);
3811 static DisasJumpType
op_rev32(DisasContext
*s
, DisasOps
*o
)
3813 tcg_gen_bswap32_i64(o
->out
, o
->in2
, TCG_BSWAP_IZ
| TCG_BSWAP_OZ
);
3817 static DisasJumpType
op_rev64(DisasContext
*s
, DisasOps
*o
)
3819 tcg_gen_bswap64_i64(o
->out
, o
->in2
);
3823 static DisasJumpType
op_rll32(DisasContext
*s
, DisasOps
*o
)
3825 TCGv_i32 t1
= tcg_temp_new_i32();
3826 TCGv_i32 t2
= tcg_temp_new_i32();
3827 TCGv_i32 to
= tcg_temp_new_i32();
3828 tcg_gen_extrl_i64_i32(t1
, o
->in1
);
3829 tcg_gen_extrl_i64_i32(t2
, o
->in2
);
3830 tcg_gen_rotl_i32(to
, t1
, t2
);
3831 tcg_gen_extu_i32_i64(o
->out
, to
);
3835 static DisasJumpType
op_rll64(DisasContext
*s
, DisasOps
*o
)
3837 tcg_gen_rotl_i64(o
->out
, o
->in1
, o
->in2
);
3841 #ifndef CONFIG_USER_ONLY
3842 static DisasJumpType
op_rrbe(DisasContext
*s
, DisasOps
*o
)
3844 gen_helper_rrbe(cc_op
, tcg_env
, o
->in2
);
3849 static DisasJumpType
op_sacf(DisasContext
*s
, DisasOps
*o
)
3851 gen_helper_sacf(tcg_env
, o
->in2
);
3852 /* Addressing mode has changed, so end the block. */
3853 return DISAS_TOO_MANY
;
3857 static DisasJumpType
op_sam(DisasContext
*s
, DisasOps
*o
)
3859 int sam
= s
->insn
->data
;
3875 /* Bizarre but true, we check the address of the current insn for the
3876 specification exception, not the next to be executed. Thus the PoO
3877 documents that Bad Things Happen two bytes before the end. */
3878 if (s
->base
.pc_next
& ~mask
) {
3879 gen_program_exception(s
, PGM_SPECIFICATION
);
3880 return DISAS_NORETURN
;
3884 tsam
= tcg_constant_i64(sam
);
3885 tcg_gen_deposit_i64(psw_mask
, psw_mask
, tsam
, 31, 2);
3887 /* Always exit the TB, since we (may have) changed execution mode. */
3888 return DISAS_TOO_MANY
;
3891 static DisasJumpType
op_sar(DisasContext
*s
, DisasOps
*o
)
3893 int r1
= get_field(s
, r1
);
3894 tcg_gen_st32_i64(o
->in2
, tcg_env
, offsetof(CPUS390XState
, aregs
[r1
]));
3898 static DisasJumpType
op_seb(DisasContext
*s
, DisasOps
*o
)
3900 gen_helper_seb(o
->out
, tcg_env
, o
->in1
, o
->in2
);
3904 static DisasJumpType
op_sdb(DisasContext
*s
, DisasOps
*o
)
3906 gen_helper_sdb(o
->out
, tcg_env
, o
->in1
, o
->in2
);
3910 static DisasJumpType
op_sxb(DisasContext
*s
, DisasOps
*o
)
3912 gen_helper_sxb(o
->out_128
, tcg_env
, o
->in1_128
, o
->in2_128
);
3916 static DisasJumpType
op_sqeb(DisasContext
*s
, DisasOps
*o
)
3918 gen_helper_sqeb(o
->out
, tcg_env
, o
->in2
);
3922 static DisasJumpType
op_sqdb(DisasContext
*s
, DisasOps
*o
)
3924 gen_helper_sqdb(o
->out
, tcg_env
, o
->in2
);
3928 static DisasJumpType
op_sqxb(DisasContext
*s
, DisasOps
*o
)
3930 gen_helper_sqxb(o
->out_128
, tcg_env
, o
->in2_128
);
3934 #ifndef CONFIG_USER_ONLY
3935 static DisasJumpType
op_servc(DisasContext
*s
, DisasOps
*o
)
3937 gen_helper_servc(cc_op
, tcg_env
, o
->in2
, o
->in1
);
3942 static DisasJumpType
op_sigp(DisasContext
*s
, DisasOps
*o
)
3944 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
3945 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
3947 gen_helper_sigp(cc_op
, tcg_env
, o
->in2
, r1
, r3
);
3953 static DisasJumpType
op_soc(DisasContext
*s
, DisasOps
*o
)
3960 disas_jcc(s
, &c
, get_field(s
, m3
));
3962 /* We want to store when the condition is fulfilled, so branch
3963 out when it's not */
3964 c
.cond
= tcg_invert_cond(c
.cond
);
3966 lab
= gen_new_label();
3968 tcg_gen_brcond_i64(c
.cond
, c
.u
.s64
.a
, c
.u
.s64
.b
, lab
);
3970 tcg_gen_brcond_i32(c
.cond
, c
.u
.s32
.a
, c
.u
.s32
.b
, lab
);
3973 r1
= get_field(s
, r1
);
3974 a
= get_address(s
, 0, get_field(s
, b2
), get_field(s
, d2
));
3975 switch (s
->insn
->data
) {
3977 tcg_gen_qemu_st_i64(regs
[r1
], a
, get_mem_index(s
), MO_TEUQ
);
3980 tcg_gen_qemu_st_i64(regs
[r1
], a
, get_mem_index(s
), MO_TEUL
);
3982 case 2: /* STOCFH */
3983 h
= tcg_temp_new_i64();
3984 tcg_gen_shri_i64(h
, regs
[r1
], 32);
3985 tcg_gen_qemu_st_i64(h
, a
, get_mem_index(s
), MO_TEUL
);
3988 g_assert_not_reached();
3995 static DisasJumpType
op_sla(DisasContext
*s
, DisasOps
*o
)
3998 uint64_t sign
= 1ull << s
->insn
->data
;
3999 if (s
->insn
->data
== 31) {
4000 t
= tcg_temp_new_i64();
4001 tcg_gen_shli_i64(t
, o
->in1
, 32);
4005 gen_op_update2_cc_i64(s
, CC_OP_SLA
, t
, o
->in2
);
4006 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
4007 /* The arithmetic left shift is curious in that it does not affect
4008 the sign bit. Copy that over from the source unchanged. */
4009 tcg_gen_andi_i64(o
->out
, o
->out
, ~sign
);
4010 tcg_gen_andi_i64(o
->in1
, o
->in1
, sign
);
4011 tcg_gen_or_i64(o
->out
, o
->out
, o
->in1
);
4015 static DisasJumpType
op_sll(DisasContext
*s
, DisasOps
*o
)
4017 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
4021 static DisasJumpType
op_sra(DisasContext
*s
, DisasOps
*o
)
4023 tcg_gen_sar_i64(o
->out
, o
->in1
, o
->in2
);
4027 static DisasJumpType
op_srl(DisasContext
*s
, DisasOps
*o
)
4029 tcg_gen_shr_i64(o
->out
, o
->in1
, o
->in2
);
4033 static DisasJumpType
op_sfpc(DisasContext
*s
, DisasOps
*o
)
4035 gen_helper_sfpc(tcg_env
, o
->in2
);
4039 static DisasJumpType
op_sfas(DisasContext
*s
, DisasOps
*o
)
4041 gen_helper_sfas(tcg_env
, o
->in2
);
4045 static DisasJumpType
op_srnm(DisasContext
*s
, DisasOps
*o
)
4047 /* Bits other than 62 and 63 are ignored. Bit 29 is set to zero. */
4048 tcg_gen_andi_i64(o
->addr1
, o
->addr1
, 0x3ull
);
4049 gen_helper_srnm(tcg_env
, o
->addr1
);
4053 static DisasJumpType
op_srnmb(DisasContext
*s
, DisasOps
*o
)
4055 /* Bits 0-55 are are ignored. */
4056 tcg_gen_andi_i64(o
->addr1
, o
->addr1
, 0xffull
);
4057 gen_helper_srnm(tcg_env
, o
->addr1
);
4061 static DisasJumpType
op_srnmt(DisasContext
*s
, DisasOps
*o
)
4063 TCGv_i64 tmp
= tcg_temp_new_i64();
4065 /* Bits other than 61-63 are ignored. */
4066 tcg_gen_andi_i64(o
->addr1
, o
->addr1
, 0x7ull
);
4068 /* No need to call a helper, we don't implement dfp */
4069 tcg_gen_ld32u_i64(tmp
, tcg_env
, offsetof(CPUS390XState
, fpc
));
4070 tcg_gen_deposit_i64(tmp
, tmp
, o
->addr1
, 4, 3);
4071 tcg_gen_st32_i64(tmp
, tcg_env
, offsetof(CPUS390XState
, fpc
));
4075 static DisasJumpType
op_spm(DisasContext
*s
, DisasOps
*o
)
4077 tcg_gen_extrl_i64_i32(cc_op
, o
->in1
);
4078 tcg_gen_extract_i32(cc_op
, cc_op
, 28, 2);
4081 tcg_gen_shri_i64(o
->in1
, o
->in1
, 24);
4082 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in1
, PSW_SHIFT_MASK_PM
, 4);
4086 static DisasJumpType
op_ectg(DisasContext
*s
, DisasOps
*o
)
4088 int b1
= get_field(s
, b1
);
4089 int d1
= get_field(s
, d1
);
4090 int b2
= get_field(s
, b2
);
4091 int d2
= get_field(s
, d2
);
4092 int r3
= get_field(s
, r3
);
4093 TCGv_i64 tmp
= tcg_temp_new_i64();
4095 /* fetch all operands first */
4096 o
->in1
= tcg_temp_new_i64();
4097 tcg_gen_addi_i64(o
->in1
, regs
[b1
], d1
);
4098 o
->in2
= tcg_temp_new_i64();
4099 tcg_gen_addi_i64(o
->in2
, regs
[b2
], d2
);
4100 o
->addr1
= tcg_temp_new_i64();
4101 gen_addi_and_wrap_i64(s
, o
->addr1
, regs
[r3
], 0);
4103 /* load the third operand into r3 before modifying anything */
4104 tcg_gen_qemu_ld_i64(regs
[r3
], o
->addr1
, get_mem_index(s
), MO_TEUQ
);
4106 /* subtract CPU timer from first operand and store in GR0 */
4107 gen_helper_stpt(tmp
, tcg_env
);
4108 tcg_gen_sub_i64(regs
[0], o
->in1
, tmp
);
4110 /* store second operand in GR1 */
4111 tcg_gen_mov_i64(regs
[1], o
->in2
);
4115 #ifndef CONFIG_USER_ONLY
4116 static DisasJumpType
op_spka(DisasContext
*s
, DisasOps
*o
)
4118 tcg_gen_shri_i64(o
->in2
, o
->in2
, 4);
4119 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in2
, PSW_SHIFT_KEY
, 4);
4123 static DisasJumpType
op_sske(DisasContext
*s
, DisasOps
*o
)
4125 gen_helper_sske(tcg_env
, o
->in1
, o
->in2
);
4129 static void gen_check_psw_mask(DisasContext
*s
)
4131 TCGv_i64 reserved
= tcg_temp_new_i64();
4132 TCGLabel
*ok
= gen_new_label();
4134 tcg_gen_andi_i64(reserved
, psw_mask
, PSW_MASK_RESERVED
);
4135 tcg_gen_brcondi_i64(TCG_COND_EQ
, reserved
, 0, ok
);
4136 gen_program_exception(s
, PGM_SPECIFICATION
);
4140 static DisasJumpType
op_ssm(DisasContext
*s
, DisasOps
*o
)
4142 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in2
, 56, 8);
4144 gen_check_psw_mask(s
);
4146 /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
4147 s
->exit_to_mainloop
= true;
4148 return DISAS_TOO_MANY
;
4151 static DisasJumpType
op_stap(DisasContext
*s
, DisasOps
*o
)
4153 tcg_gen_ld32u_i64(o
->out
, tcg_env
, offsetof(CPUS390XState
, core_id
));
4158 static DisasJumpType
op_stck(DisasContext
*s
, DisasOps
*o
)
4160 gen_helper_stck(o
->out
, tcg_env
);
4161 /* ??? We don't implement clock states. */
4162 gen_op_movi_cc(s
, 0);
4166 static DisasJumpType
op_stcke(DisasContext
*s
, DisasOps
*o
)
4168 TCGv_i64 c1
= tcg_temp_new_i64();
4169 TCGv_i64 c2
= tcg_temp_new_i64();
4170 TCGv_i64 todpr
= tcg_temp_new_i64();
4171 gen_helper_stck(c1
, tcg_env
);
4172 /* 16 bit value store in an uint32_t (only valid bits set) */
4173 tcg_gen_ld32u_i64(todpr
, tcg_env
, offsetof(CPUS390XState
, todpr
));
4174 /* Shift the 64-bit value into its place as a zero-extended
4175 104-bit value. Note that "bit positions 64-103 are always
4176 non-zero so that they compare differently to STCK"; we set
4177 the least significant bit to 1. */
4178 tcg_gen_shli_i64(c2
, c1
, 56);
4179 tcg_gen_shri_i64(c1
, c1
, 8);
4180 tcg_gen_ori_i64(c2
, c2
, 0x10000);
4181 tcg_gen_or_i64(c2
, c2
, todpr
);
4182 tcg_gen_qemu_st_i64(c1
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
4183 tcg_gen_addi_i64(o
->in2
, o
->in2
, 8);
4184 tcg_gen_qemu_st_i64(c2
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
4185 /* ??? We don't implement clock states. */
4186 gen_op_movi_cc(s
, 0);
4190 #ifndef CONFIG_USER_ONLY
4191 static DisasJumpType
op_sck(DisasContext
*s
, DisasOps
*o
)
4193 gen_helper_sck(cc_op
, tcg_env
, o
->in2
);
4198 static DisasJumpType
op_sckc(DisasContext
*s
, DisasOps
*o
)
4200 gen_helper_sckc(tcg_env
, o
->in2
);
4204 static DisasJumpType
op_sckpf(DisasContext
*s
, DisasOps
*o
)
4206 gen_helper_sckpf(tcg_env
, regs
[0]);
4210 static DisasJumpType
op_stckc(DisasContext
*s
, DisasOps
*o
)
4212 gen_helper_stckc(o
->out
, tcg_env
);
4216 static DisasJumpType
op_stctg(DisasContext
*s
, DisasOps
*o
)
4218 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4219 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
4221 gen_helper_stctg(tcg_env
, r1
, o
->in2
, r3
);
4225 static DisasJumpType
op_stctl(DisasContext
*s
, DisasOps
*o
)
4227 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4228 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
4230 gen_helper_stctl(tcg_env
, r1
, o
->in2
, r3
);
4234 static DisasJumpType
op_stidp(DisasContext
*s
, DisasOps
*o
)
4236 tcg_gen_ld_i64(o
->out
, tcg_env
, offsetof(CPUS390XState
, cpuid
));
4240 static DisasJumpType
op_spt(DisasContext
*s
, DisasOps
*o
)
4242 gen_helper_spt(tcg_env
, o
->in2
);
4246 static DisasJumpType
op_stfl(DisasContext
*s
, DisasOps
*o
)
4248 gen_helper_stfl(tcg_env
);
4252 static DisasJumpType
op_stpt(DisasContext
*s
, DisasOps
*o
)
4254 gen_helper_stpt(o
->out
, tcg_env
);
4258 static DisasJumpType
op_stsi(DisasContext
*s
, DisasOps
*o
)
4260 gen_helper_stsi(cc_op
, tcg_env
, o
->in2
, regs
[0], regs
[1]);
4265 static DisasJumpType
op_spx(DisasContext
*s
, DisasOps
*o
)
4267 gen_helper_spx(tcg_env
, o
->in2
);
4271 static DisasJumpType
op_xsch(DisasContext
*s
, DisasOps
*o
)
4273 gen_helper_xsch(tcg_env
, regs
[1]);
4278 static DisasJumpType
op_csch(DisasContext
*s
, DisasOps
*o
)
4280 gen_helper_csch(tcg_env
, regs
[1]);
4285 static DisasJumpType
op_hsch(DisasContext
*s
, DisasOps
*o
)
4287 gen_helper_hsch(tcg_env
, regs
[1]);
4292 static DisasJumpType
op_msch(DisasContext
*s
, DisasOps
*o
)
4294 gen_helper_msch(tcg_env
, regs
[1], o
->in2
);
4299 static DisasJumpType
op_rchp(DisasContext
*s
, DisasOps
*o
)
4301 gen_helper_rchp(tcg_env
, regs
[1]);
4306 static DisasJumpType
op_rsch(DisasContext
*s
, DisasOps
*o
)
4308 gen_helper_rsch(tcg_env
, regs
[1]);
4313 static DisasJumpType
op_sal(DisasContext
*s
, DisasOps
*o
)
4315 gen_helper_sal(tcg_env
, regs
[1]);
4319 static DisasJumpType
op_schm(DisasContext
*s
, DisasOps
*o
)
4321 gen_helper_schm(tcg_env
, regs
[1], regs
[2], o
->in2
);
4325 static DisasJumpType
op_siga(DisasContext
*s
, DisasOps
*o
)
4327 /* From KVM code: Not provided, set CC = 3 for subchannel not operational */
4328 gen_op_movi_cc(s
, 3);
4332 static DisasJumpType
op_stcps(DisasContext
*s
, DisasOps
*o
)
4334 /* The instruction is suppressed if not provided. */
4338 static DisasJumpType
op_ssch(DisasContext
*s
, DisasOps
*o
)
4340 gen_helper_ssch(tcg_env
, regs
[1], o
->in2
);
4345 static DisasJumpType
op_stsch(DisasContext
*s
, DisasOps
*o
)
4347 gen_helper_stsch(tcg_env
, regs
[1], o
->in2
);
4352 static DisasJumpType
op_stcrw(DisasContext
*s
, DisasOps
*o
)
4354 gen_helper_stcrw(tcg_env
, o
->in2
);
4359 static DisasJumpType
op_tpi(DisasContext
*s
, DisasOps
*o
)
4361 gen_helper_tpi(cc_op
, tcg_env
, o
->addr1
);
4366 static DisasJumpType
op_tsch(DisasContext
*s
, DisasOps
*o
)
4368 gen_helper_tsch(tcg_env
, regs
[1], o
->in2
);
4373 static DisasJumpType
op_chsc(DisasContext
*s
, DisasOps
*o
)
4375 gen_helper_chsc(tcg_env
, o
->in2
);
4380 static DisasJumpType
op_stpx(DisasContext
*s
, DisasOps
*o
)
4382 tcg_gen_ld_i64(o
->out
, tcg_env
, offsetof(CPUS390XState
, psa
));
4383 tcg_gen_andi_i64(o
->out
, o
->out
, 0x7fffe000);
4387 static DisasJumpType
op_stnosm(DisasContext
*s
, DisasOps
*o
)
4389 uint64_t i2
= get_field(s
, i2
);
4392 /* It is important to do what the instruction name says: STORE THEN.
4393 If we let the output hook perform the store then if we fault and
4394 restart, we'll have the wrong SYSTEM MASK in place. */
4395 t
= tcg_temp_new_i64();
4396 tcg_gen_shri_i64(t
, psw_mask
, 56);
4397 tcg_gen_qemu_st_i64(t
, o
->addr1
, get_mem_index(s
), MO_UB
);
4399 if (s
->fields
.op
== 0xac) {
4400 tcg_gen_andi_i64(psw_mask
, psw_mask
,
4401 (i2
<< 56) | 0x00ffffffffffffffull
);
4403 tcg_gen_ori_i64(psw_mask
, psw_mask
, i2
<< 56);
4406 gen_check_psw_mask(s
);
4408 /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
4409 s
->exit_to_mainloop
= true;
4410 return DISAS_TOO_MANY
;
4413 static DisasJumpType
op_stura(DisasContext
*s
, DisasOps
*o
)
4415 tcg_gen_qemu_st_tl(o
->in1
, o
->in2
, MMU_REAL_IDX
, s
->insn
->data
);
4417 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
4419 gen_helper_per_store_real(tcg_env
);
4425 static DisasJumpType
op_stfle(DisasContext
*s
, DisasOps
*o
)
4427 gen_helper_stfle(cc_op
, tcg_env
, o
->in2
);
4432 static DisasJumpType
op_st8(DisasContext
*s
, DisasOps
*o
)
4434 tcg_gen_qemu_st_i64(o
->in1
, o
->in2
, get_mem_index(s
), MO_UB
);
4438 static DisasJumpType
op_st16(DisasContext
*s
, DisasOps
*o
)
4440 tcg_gen_qemu_st_i64(o
->in1
, o
->in2
, get_mem_index(s
), MO_TEUW
);
4444 static DisasJumpType
op_st32(DisasContext
*s
, DisasOps
*o
)
4446 tcg_gen_qemu_st_tl(o
->in1
, o
->in2
, get_mem_index(s
),
4447 MO_TEUL
| s
->insn
->data
);
4451 static DisasJumpType
op_st64(DisasContext
*s
, DisasOps
*o
)
4453 tcg_gen_qemu_st_i64(o
->in1
, o
->in2
, get_mem_index(s
),
4454 MO_TEUQ
| s
->insn
->data
);
4458 static DisasJumpType
op_stam(DisasContext
*s
, DisasOps
*o
)
4460 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4461 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
4463 gen_helper_stam(tcg_env
, r1
, o
->in2
, r3
);
4467 static DisasJumpType
op_stcm(DisasContext
*s
, DisasOps
*o
)
4469 int m3
= get_field(s
, m3
);
4470 int pos
, base
= s
->insn
->data
;
4471 TCGv_i64 tmp
= tcg_temp_new_i64();
4473 pos
= base
+ ctz32(m3
) * 8;
4476 /* Effectively a 32-bit store. */
4477 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
4478 tcg_gen_qemu_st_i64(tmp
, o
->in2
, get_mem_index(s
), MO_TEUL
);
4484 /* Effectively a 16-bit store. */
4485 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
4486 tcg_gen_qemu_st_i64(tmp
, o
->in2
, get_mem_index(s
), MO_TEUW
);
4493 /* Effectively an 8-bit store. */
4494 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
4495 tcg_gen_qemu_st_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
4499 /* This is going to be a sequence of shifts and stores. */
4500 pos
= base
+ 32 - 8;
4503 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
4504 tcg_gen_qemu_st_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
4505 tcg_gen_addi_i64(o
->in2
, o
->in2
, 1);
4507 m3
= (m3
<< 1) & 0xf;
4515 static DisasJumpType
op_stm(DisasContext
*s
, DisasOps
*o
)
4517 int r1
= get_field(s
, r1
);
4518 int r3
= get_field(s
, r3
);
4519 int size
= s
->insn
->data
;
4520 TCGv_i64 tsize
= tcg_constant_i64(size
);
4523 tcg_gen_qemu_st_i64(regs
[r1
], o
->in2
, get_mem_index(s
),
4524 size
== 8 ? MO_TEUQ
: MO_TEUL
);
4528 tcg_gen_add_i64(o
->in2
, o
->in2
, tsize
);
4535 static DisasJumpType
op_stmh(DisasContext
*s
, DisasOps
*o
)
4537 int r1
= get_field(s
, r1
);
4538 int r3
= get_field(s
, r3
);
4539 TCGv_i64 t
= tcg_temp_new_i64();
4540 TCGv_i64 t4
= tcg_constant_i64(4);
4541 TCGv_i64 t32
= tcg_constant_i64(32);
4544 tcg_gen_shl_i64(t
, regs
[r1
], t32
);
4545 tcg_gen_qemu_st_i64(t
, o
->in2
, get_mem_index(s
), MO_TEUL
);
4549 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
4555 static DisasJumpType
op_stpq(DisasContext
*s
, DisasOps
*o
)
4557 TCGv_i128 t16
= tcg_temp_new_i128();
4559 tcg_gen_concat_i64_i128(t16
, o
->out2
, o
->out
);
4560 tcg_gen_qemu_st_i128(t16
, o
->in2
, get_mem_index(s
),
4561 MO_TE
| MO_128
| MO_ALIGN
);
4565 static DisasJumpType
op_srst(DisasContext
*s
, DisasOps
*o
)
4567 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4568 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4570 gen_helper_srst(tcg_env
, r1
, r2
);
4575 static DisasJumpType
op_srstu(DisasContext
*s
, DisasOps
*o
)
4577 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4578 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4580 gen_helper_srstu(tcg_env
, r1
, r2
);
4585 static DisasJumpType
op_sub(DisasContext
*s
, DisasOps
*o
)
4587 tcg_gen_sub_i64(o
->out
, o
->in1
, o
->in2
);
4591 static DisasJumpType
op_subu64(DisasContext
*s
, DisasOps
*o
)
4593 tcg_gen_movi_i64(cc_src
, 0);
4594 tcg_gen_sub2_i64(o
->out
, cc_src
, o
->in1
, cc_src
, o
->in2
, cc_src
);
4598 /* Compute borrow (0, -1) into cc_src. */
4599 static void compute_borrow(DisasContext
*s
)
4603 /* The borrow value is already in cc_src (0,-1). */
4609 /* The carry flag is the msb of CC; compute into cc_src. */
4610 tcg_gen_extu_i32_i64(cc_src
, cc_op
);
4611 tcg_gen_shri_i64(cc_src
, cc_src
, 1);
4614 /* Convert carry (1,0) to borrow (0,-1). */
4615 tcg_gen_subi_i64(cc_src
, cc_src
, 1);
4620 static DisasJumpType
op_subb32(DisasContext
*s
, DisasOps
*o
)
4624 /* Borrow is {0, -1}, so add to subtract. */
4625 tcg_gen_add_i64(o
->out
, o
->in1
, cc_src
);
4626 tcg_gen_sub_i64(o
->out
, o
->out
, o
->in2
);
4630 static DisasJumpType
op_subb64(DisasContext
*s
, DisasOps
*o
)
4635 * Borrow is {0, -1}, so add to subtract; replicate the
4636 * borrow input to produce 128-bit -1 for the addition.
4638 TCGv_i64 zero
= tcg_constant_i64(0);
4639 tcg_gen_add2_i64(o
->out
, cc_src
, o
->in1
, zero
, cc_src
, cc_src
);
4640 tcg_gen_sub2_i64(o
->out
, cc_src
, o
->out
, cc_src
, o
->in2
, zero
);
4645 static DisasJumpType
op_svc(DisasContext
*s
, DisasOps
*o
)
4652 t
= tcg_constant_i32(get_field(s
, i1
) & 0xff);
4653 tcg_gen_st_i32(t
, tcg_env
, offsetof(CPUS390XState
, int_svc_code
));
4655 t
= tcg_constant_i32(s
->ilen
);
4656 tcg_gen_st_i32(t
, tcg_env
, offsetof(CPUS390XState
, int_svc_ilen
));
4658 gen_exception(EXCP_SVC
);
4659 return DISAS_NORETURN
;
4662 static DisasJumpType
op_tam(DisasContext
*s
, DisasOps
*o
)
4666 cc
|= (s
->base
.tb
->flags
& FLAG_MASK_64
) ? 2 : 0;
4667 cc
|= (s
->base
.tb
->flags
& FLAG_MASK_32
) ? 1 : 0;
4668 gen_op_movi_cc(s
, cc
);
4672 static DisasJumpType
op_tceb(DisasContext
*s
, DisasOps
*o
)
4674 gen_helper_tceb(cc_op
, tcg_env
, o
->in1
, o
->in2
);
4679 static DisasJumpType
op_tcdb(DisasContext
*s
, DisasOps
*o
)
4681 gen_helper_tcdb(cc_op
, tcg_env
, o
->in1
, o
->in2
);
4686 static DisasJumpType
op_tcxb(DisasContext
*s
, DisasOps
*o
)
4688 gen_helper_tcxb(cc_op
, tcg_env
, o
->in1_128
, o
->in2
);
4693 #ifndef CONFIG_USER_ONLY
4695 static DisasJumpType
op_testblock(DisasContext
*s
, DisasOps
*o
)
4697 gen_helper_testblock(cc_op
, tcg_env
, o
->in2
);
4702 static DisasJumpType
op_tprot(DisasContext
*s
, DisasOps
*o
)
4704 gen_helper_tprot(cc_op
, tcg_env
, o
->addr1
, o
->in2
);
4711 static DisasJumpType
op_tp(DisasContext
*s
, DisasOps
*o
)
4713 TCGv_i32 l1
= tcg_constant_i32(get_field(s
, l1
) + 1);
4715 gen_helper_tp(cc_op
, tcg_env
, o
->addr1
, l1
);
4720 static DisasJumpType
op_tr(DisasContext
*s
, DisasOps
*o
)
4722 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
4724 gen_helper_tr(tcg_env
, l
, o
->addr1
, o
->in2
);
4729 static DisasJumpType
op_tre(DisasContext
*s
, DisasOps
*o
)
4731 TCGv_i128 pair
= tcg_temp_new_i128();
4733 gen_helper_tre(pair
, tcg_env
, o
->out
, o
->out2
, o
->in2
);
4734 tcg_gen_extr_i128_i64(o
->out2
, o
->out
, pair
);
4739 static DisasJumpType
op_trt(DisasContext
*s
, DisasOps
*o
)
4741 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
4743 gen_helper_trt(cc_op
, tcg_env
, l
, o
->addr1
, o
->in2
);
4748 static DisasJumpType
op_trtr(DisasContext
*s
, DisasOps
*o
)
4750 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
4752 gen_helper_trtr(cc_op
, tcg_env
, l
, o
->addr1
, o
->in2
);
4757 static DisasJumpType
op_trXX(DisasContext
*s
, DisasOps
*o
)
4759 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4760 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4761 TCGv_i32 sizes
= tcg_constant_i32(s
->insn
->opc
& 3);
4762 TCGv_i32 tst
= tcg_temp_new_i32();
4763 int m3
= get_field(s
, m3
);
4765 if (!s390_has_feat(S390_FEAT_ETF2_ENH
)) {
4769 tcg_gen_movi_i32(tst
, -1);
4771 tcg_gen_extrl_i64_i32(tst
, regs
[0]);
4772 if (s
->insn
->opc
& 3) {
4773 tcg_gen_ext8u_i32(tst
, tst
);
4775 tcg_gen_ext16u_i32(tst
, tst
);
4778 gen_helper_trXX(cc_op
, tcg_env
, r1
, r2
, tst
, sizes
);
4784 static DisasJumpType
op_ts(DisasContext
*s
, DisasOps
*o
)
4786 TCGv_i32 t1
= tcg_constant_i32(0xff);
4788 tcg_gen_atomic_xchg_i32(t1
, o
->in2
, t1
, get_mem_index(s
), MO_UB
);
4789 tcg_gen_extract_i32(cc_op
, t1
, 7, 1);
4794 static DisasJumpType
op_unpk(DisasContext
*s
, DisasOps
*o
)
4796 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
4798 gen_helper_unpk(tcg_env
, l
, o
->addr1
, o
->in2
);
4802 static DisasJumpType
op_unpka(DisasContext
*s
, DisasOps
*o
)
4804 int l1
= get_field(s
, l1
) + 1;
4807 /* The length must not exceed 32 bytes. */
4809 gen_program_exception(s
, PGM_SPECIFICATION
);
4810 return DISAS_NORETURN
;
4812 l
= tcg_constant_i32(l1
);
4813 gen_helper_unpka(cc_op
, tcg_env
, o
->addr1
, l
, o
->in2
);
4818 static DisasJumpType
op_unpku(DisasContext
*s
, DisasOps
*o
)
4820 int l1
= get_field(s
, l1
) + 1;
4823 /* The length must be even and should not exceed 64 bytes. */
4824 if ((l1
& 1) || (l1
> 64)) {
4825 gen_program_exception(s
, PGM_SPECIFICATION
);
4826 return DISAS_NORETURN
;
4828 l
= tcg_constant_i32(l1
);
4829 gen_helper_unpku(cc_op
, tcg_env
, o
->addr1
, l
, o
->in2
);
4835 static DisasJumpType
op_xc(DisasContext
*s
, DisasOps
*o
)
4837 int d1
= get_field(s
, d1
);
4838 int d2
= get_field(s
, d2
);
4839 int b1
= get_field(s
, b1
);
4840 int b2
= get_field(s
, b2
);
4841 int l
= get_field(s
, l1
);
4844 o
->addr1
= get_address(s
, 0, b1
, d1
);
4846 /* If the addresses are identical, this is a store/memset of zero. */
4847 if (b1
== b2
&& d1
== d2
&& (l
+ 1) <= 32) {
4848 o
->in2
= tcg_constant_i64(0);
4852 tcg_gen_qemu_st_i64(o
->in2
, o
->addr1
, get_mem_index(s
), MO_UQ
);
4855 tcg_gen_addi_i64(o
->addr1
, o
->addr1
, 8);
4859 tcg_gen_qemu_st_i64(o
->in2
, o
->addr1
, get_mem_index(s
), MO_UL
);
4862 tcg_gen_addi_i64(o
->addr1
, o
->addr1
, 4);
4866 tcg_gen_qemu_st_i64(o
->in2
, o
->addr1
, get_mem_index(s
), MO_UW
);
4869 tcg_gen_addi_i64(o
->addr1
, o
->addr1
, 2);
4873 tcg_gen_qemu_st_i64(o
->in2
, o
->addr1
, get_mem_index(s
), MO_UB
);
4875 gen_op_movi_cc(s
, 0);
4879 /* But in general we'll defer to a helper. */
4880 o
->in2
= get_address(s
, 0, b2
, d2
);
4881 t32
= tcg_constant_i32(l
);
4882 gen_helper_xc(cc_op
, tcg_env
, t32
, o
->addr1
, o
->in2
);
4887 static DisasJumpType
op_xor(DisasContext
*s
, DisasOps
*o
)
4889 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
4893 static DisasJumpType
op_xori(DisasContext
*s
, DisasOps
*o
)
4895 int shift
= s
->insn
->data
& 0xff;
4896 int size
= s
->insn
->data
>> 8;
4897 uint64_t mask
= ((1ull << size
) - 1) << shift
;
4898 TCGv_i64 t
= tcg_temp_new_i64();
4900 tcg_gen_shli_i64(t
, o
->in2
, shift
);
4901 tcg_gen_xor_i64(o
->out
, o
->in1
, t
);
4903 /* Produce the CC from only the bits manipulated. */
4904 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
4905 set_cc_nz_u64(s
, cc_dst
);
4909 static DisasJumpType
op_xi(DisasContext
*s
, DisasOps
*o
)
4911 o
->in1
= tcg_temp_new_i64();
4913 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
4914 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
4916 /* Perform the atomic operation in memory. */
4917 tcg_gen_atomic_fetch_xor_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
4921 /* Recompute also for atomic case: needed for setting CC. */
4922 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
4924 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
4925 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
4930 static DisasJumpType
op_zero(DisasContext
*s
, DisasOps
*o
)
4932 o
->out
= tcg_constant_i64(0);
4936 static DisasJumpType
op_zero2(DisasContext
*s
, DisasOps
*o
)
4938 o
->out
= tcg_constant_i64(0);
4943 #ifndef CONFIG_USER_ONLY
4944 static DisasJumpType
op_clp(DisasContext
*s
, DisasOps
*o
)
4946 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4948 gen_helper_clp(tcg_env
, r2
);
4953 static DisasJumpType
op_pcilg(DisasContext
*s
, DisasOps
*o
)
4955 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4956 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4958 gen_helper_pcilg(tcg_env
, r1
, r2
);
4963 static DisasJumpType
op_pcistg(DisasContext
*s
, DisasOps
*o
)
4965 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4966 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4968 gen_helper_pcistg(tcg_env
, r1
, r2
);
4973 static DisasJumpType
op_stpcifc(DisasContext
*s
, DisasOps
*o
)
4975 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4976 TCGv_i32 ar
= tcg_constant_i32(get_field(s
, b2
));
4978 gen_helper_stpcifc(tcg_env
, r1
, o
->addr1
, ar
);
4983 static DisasJumpType
op_sic(DisasContext
*s
, DisasOps
*o
)
4985 gen_helper_sic(tcg_env
, o
->in1
, o
->in2
);
4989 static DisasJumpType
op_rpcit(DisasContext
*s
, DisasOps
*o
)
4991 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4992 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4994 gen_helper_rpcit(tcg_env
, r1
, r2
);
4999 static DisasJumpType
op_pcistb(DisasContext
*s
, DisasOps
*o
)
5001 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
5002 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
5003 TCGv_i32 ar
= tcg_constant_i32(get_field(s
, b2
));
5005 gen_helper_pcistb(tcg_env
, r1
, r3
, o
->addr1
, ar
);
5010 static DisasJumpType
op_mpcifc(DisasContext
*s
, DisasOps
*o
)
5012 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
5013 TCGv_i32 ar
= tcg_constant_i32(get_field(s
, b2
));
5015 gen_helper_mpcifc(tcg_env
, r1
, o
->addr1
, ar
);
5021 #include "translate_vx.c.inc"
5023 /* ====================================================================== */
5024 /* The "Cc OUTput" generators. Given the generated output (and in some cases
5025 the original inputs), update the various cc data structures in order to
5026 be able to compute the new condition code. */
5028 static void cout_abs32(DisasContext
*s
, DisasOps
*o
)
5030 gen_op_update1_cc_i64(s
, CC_OP_ABS_32
, o
->out
);
5033 static void cout_abs64(DisasContext
*s
, DisasOps
*o
)
5035 gen_op_update1_cc_i64(s
, CC_OP_ABS_64
, o
->out
);
5038 static void cout_adds32(DisasContext
*s
, DisasOps
*o
)
5040 gen_op_update3_cc_i64(s
, CC_OP_ADD_32
, o
->in1
, o
->in2
, o
->out
);
5043 static void cout_adds64(DisasContext
*s
, DisasOps
*o
)
5045 gen_op_update3_cc_i64(s
, CC_OP_ADD_64
, o
->in1
, o
->in2
, o
->out
);
5048 static void cout_addu32(DisasContext
*s
, DisasOps
*o
)
5050 tcg_gen_shri_i64(cc_src
, o
->out
, 32);
5051 tcg_gen_ext32u_i64(cc_dst
, o
->out
);
5052 gen_op_update2_cc_i64(s
, CC_OP_ADDU
, cc_src
, cc_dst
);
5055 static void cout_addu64(DisasContext
*s
, DisasOps
*o
)
5057 gen_op_update2_cc_i64(s
, CC_OP_ADDU
, cc_src
, o
->out
);
5060 static void cout_cmps32(DisasContext
*s
, DisasOps
*o
)
5062 gen_op_update2_cc_i64(s
, CC_OP_LTGT_32
, o
->in1
, o
->in2
);
5065 static void cout_cmps64(DisasContext
*s
, DisasOps
*o
)
5067 gen_op_update2_cc_i64(s
, CC_OP_LTGT_64
, o
->in1
, o
->in2
);
5070 static void cout_cmpu32(DisasContext
*s
, DisasOps
*o
)
5072 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_32
, o
->in1
, o
->in2
);
5075 static void cout_cmpu64(DisasContext
*s
, DisasOps
*o
)
5077 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, o
->in1
, o
->in2
);
5080 static void cout_f32(DisasContext
*s
, DisasOps
*o
)
5082 gen_op_update1_cc_i64(s
, CC_OP_NZ_F32
, o
->out
);
5085 static void cout_f64(DisasContext
*s
, DisasOps
*o
)
5087 gen_op_update1_cc_i64(s
, CC_OP_NZ_F64
, o
->out
);
5090 static void cout_f128(DisasContext
*s
, DisasOps
*o
)
5092 gen_op_update2_cc_i64(s
, CC_OP_NZ_F128
, o
->out
, o
->out2
);
5095 static void cout_nabs32(DisasContext
*s
, DisasOps
*o
)
5097 gen_op_update1_cc_i64(s
, CC_OP_NABS_32
, o
->out
);
5100 static void cout_nabs64(DisasContext
*s
, DisasOps
*o
)
5102 gen_op_update1_cc_i64(s
, CC_OP_NABS_64
, o
->out
);
5105 static void cout_neg32(DisasContext
*s
, DisasOps
*o
)
5107 gen_op_update1_cc_i64(s
, CC_OP_COMP_32
, o
->out
);
5110 static void cout_neg64(DisasContext
*s
, DisasOps
*o
)
5112 gen_op_update1_cc_i64(s
, CC_OP_COMP_64
, o
->out
);
5115 static void cout_nz32(DisasContext
*s
, DisasOps
*o
)
5117 tcg_gen_ext32u_i64(cc_dst
, o
->out
);
5118 gen_op_update1_cc_i64(s
, CC_OP_NZ
, cc_dst
);
5121 static void cout_nz64(DisasContext
*s
, DisasOps
*o
)
5123 gen_op_update1_cc_i64(s
, CC_OP_NZ
, o
->out
);
5126 static void cout_s32(DisasContext
*s
, DisasOps
*o
)
5128 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_32
, o
->out
);
5131 static void cout_s64(DisasContext
*s
, DisasOps
*o
)
5133 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_64
, o
->out
);
5136 static void cout_subs32(DisasContext
*s
, DisasOps
*o
)
5138 gen_op_update3_cc_i64(s
, CC_OP_SUB_32
, o
->in1
, o
->in2
, o
->out
);
5141 static void cout_subs64(DisasContext
*s
, DisasOps
*o
)
5143 gen_op_update3_cc_i64(s
, CC_OP_SUB_64
, o
->in1
, o
->in2
, o
->out
);
5146 static void cout_subu32(DisasContext
*s
, DisasOps
*o
)
5148 tcg_gen_sari_i64(cc_src
, o
->out
, 32);
5149 tcg_gen_ext32u_i64(cc_dst
, o
->out
);
5150 gen_op_update2_cc_i64(s
, CC_OP_SUBU
, cc_src
, cc_dst
);
5153 static void cout_subu64(DisasContext
*s
, DisasOps
*o
)
5155 gen_op_update2_cc_i64(s
, CC_OP_SUBU
, cc_src
, o
->out
);
5158 static void cout_tm32(DisasContext
*s
, DisasOps
*o
)
5160 gen_op_update2_cc_i64(s
, CC_OP_TM_32
, o
->in1
, o
->in2
);
5163 static void cout_tm64(DisasContext
*s
, DisasOps
*o
)
5165 gen_op_update2_cc_i64(s
, CC_OP_TM_64
, o
->in1
, o
->in2
);
5168 static void cout_muls32(DisasContext
*s
, DisasOps
*o
)
5170 gen_op_update1_cc_i64(s
, CC_OP_MULS_32
, o
->out
);
5173 static void cout_muls64(DisasContext
*s
, DisasOps
*o
)
5175 /* out contains "high" part, out2 contains "low" part of 128 bit result */
5176 gen_op_update2_cc_i64(s
, CC_OP_MULS_64
, o
->out
, o
->out2
);
5179 /* ====================================================================== */
5180 /* The "PREParation" generators. These initialize the DisasOps.OUT fields
5181 with the TCG register to which we will write. Used in combination with
5182 the "wout" generators, in some cases we need a new temporary, and in
5183 some cases we can write to a TCG global. */
5185 static void prep_new(DisasContext
*s
, DisasOps
*o
)
5187 o
->out
= tcg_temp_new_i64();
5189 #define SPEC_prep_new 0
5191 static void prep_new_P(DisasContext
*s
, DisasOps
*o
)
5193 o
->out
= tcg_temp_new_i64();
5194 o
->out2
= tcg_temp_new_i64();
5196 #define SPEC_prep_new_P 0
5198 static void prep_new_x(DisasContext
*s
, DisasOps
*o
)
5200 o
->out_128
= tcg_temp_new_i128();
5202 #define SPEC_prep_new_x 0
5204 static void prep_r1(DisasContext
*s
, DisasOps
*o
)
5206 o
->out
= regs
[get_field(s
, r1
)];
5208 #define SPEC_prep_r1 0
5210 static void prep_r1_P(DisasContext
*s
, DisasOps
*o
)
5212 int r1
= get_field(s
, r1
);
5214 o
->out2
= regs
[r1
+ 1];
5216 #define SPEC_prep_r1_P SPEC_r1_even
5218 /* ====================================================================== */
5219 /* The "Write OUTput" generators. These generally perform some non-trivial
5220 copy of data to TCG globals, or to main memory. The trivial cases are
5221 generally handled by having a "prep" generator install the TCG global
5222 as the destination of the operation. */
5224 static void wout_r1(DisasContext
*s
, DisasOps
*o
)
5226 store_reg(get_field(s
, r1
), o
->out
);
5228 #define SPEC_wout_r1 0
5230 static void wout_out2_r1(DisasContext
*s
, DisasOps
*o
)
5232 store_reg(get_field(s
, r1
), o
->out2
);
5234 #define SPEC_wout_out2_r1 0
5236 static void wout_r1_8(DisasContext
*s
, DisasOps
*o
)
5238 int r1
= get_field(s
, r1
);
5239 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], o
->out
, 0, 8);
5241 #define SPEC_wout_r1_8 0
5243 static void wout_r1_16(DisasContext
*s
, DisasOps
*o
)
5245 int r1
= get_field(s
, r1
);
5246 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], o
->out
, 0, 16);
5248 #define SPEC_wout_r1_16 0
5250 static void wout_r1_32(DisasContext
*s
, DisasOps
*o
)
5252 store_reg32_i64(get_field(s
, r1
), o
->out
);
5254 #define SPEC_wout_r1_32 0
5256 static void wout_r1_32h(DisasContext
*s
, DisasOps
*o
)
5258 store_reg32h_i64(get_field(s
, r1
), o
->out
);
5260 #define SPEC_wout_r1_32h 0
5262 static void wout_r1_P32(DisasContext
*s
, DisasOps
*o
)
5264 int r1
= get_field(s
, r1
);
5265 store_reg32_i64(r1
, o
->out
);
5266 store_reg32_i64(r1
+ 1, o
->out2
);
5268 #define SPEC_wout_r1_P32 SPEC_r1_even
5270 static void wout_r1_D32(DisasContext
*s
, DisasOps
*o
)
5272 int r1
= get_field(s
, r1
);
5273 TCGv_i64 t
= tcg_temp_new_i64();
5274 store_reg32_i64(r1
+ 1, o
->out
);
5275 tcg_gen_shri_i64(t
, o
->out
, 32);
5276 store_reg32_i64(r1
, t
);
5278 #define SPEC_wout_r1_D32 SPEC_r1_even
5280 static void wout_r1_D64(DisasContext
*s
, DisasOps
*o
)
5282 int r1
= get_field(s
, r1
);
5283 tcg_gen_extr_i128_i64(regs
[r1
+ 1], regs
[r1
], o
->out_128
);
5285 #define SPEC_wout_r1_D64 SPEC_r1_even
5287 static void wout_r3_P32(DisasContext
*s
, DisasOps
*o
)
5289 int r3
= get_field(s
, r3
);
5290 store_reg32_i64(r3
, o
->out
);
5291 store_reg32_i64(r3
+ 1, o
->out2
);
5293 #define SPEC_wout_r3_P32 SPEC_r3_even
5295 static void wout_r3_P64(DisasContext
*s
, DisasOps
*o
)
5297 int r3
= get_field(s
, r3
);
5298 store_reg(r3
, o
->out
);
5299 store_reg(r3
+ 1, o
->out2
);
5301 #define SPEC_wout_r3_P64 SPEC_r3_even
5303 static void wout_e1(DisasContext
*s
, DisasOps
*o
)
5305 store_freg32_i64(get_field(s
, r1
), o
->out
);
5307 #define SPEC_wout_e1 0
5309 static void wout_f1(DisasContext
*s
, DisasOps
*o
)
5311 store_freg(get_field(s
, r1
), o
->out
);
5313 #define SPEC_wout_f1 0
5315 static void wout_x1(DisasContext
*s
, DisasOps
*o
)
5317 int f1
= get_field(s
, r1
);
5319 /* Split out_128 into out+out2 for cout_f128. */
5320 tcg_debug_assert(o
->out
== NULL
);
5321 o
->out
= tcg_temp_new_i64();
5322 o
->out2
= tcg_temp_new_i64();
5324 tcg_gen_extr_i128_i64(o
->out2
, o
->out
, o
->out_128
);
5325 store_freg(f1
, o
->out
);
5326 store_freg(f1
+ 2, o
->out2
);
5328 #define SPEC_wout_x1 SPEC_r1_f128
5330 static void wout_x1_P(DisasContext
*s
, DisasOps
*o
)
5332 int f1
= get_field(s
, r1
);
5333 store_freg(f1
, o
->out
);
5334 store_freg(f1
+ 2, o
->out2
);
5336 #define SPEC_wout_x1_P SPEC_r1_f128
5338 static void wout_cond_r1r2_32(DisasContext
*s
, DisasOps
*o
)
5340 if (get_field(s
, r1
) != get_field(s
, r2
)) {
5341 store_reg32_i64(get_field(s
, r1
), o
->out
);
5344 #define SPEC_wout_cond_r1r2_32 0
5346 static void wout_cond_e1e2(DisasContext
*s
, DisasOps
*o
)
5348 if (get_field(s
, r1
) != get_field(s
, r2
)) {
5349 store_freg32_i64(get_field(s
, r1
), o
->out
);
5352 #define SPEC_wout_cond_e1e2 0
5354 static void wout_m1_8(DisasContext
*s
, DisasOps
*o
)
5356 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_UB
);
5358 #define SPEC_wout_m1_8 0
5360 static void wout_m1_16(DisasContext
*s
, DisasOps
*o
)
5362 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUW
);
5364 #define SPEC_wout_m1_16 0
5366 #ifndef CONFIG_USER_ONLY
5367 static void wout_m1_16a(DisasContext
*s
, DisasOps
*o
)
5369 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUW
| MO_ALIGN
);
5371 #define SPEC_wout_m1_16a 0
5374 static void wout_m1_32(DisasContext
*s
, DisasOps
*o
)
5376 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUL
);
5378 #define SPEC_wout_m1_32 0
5380 #ifndef CONFIG_USER_ONLY
5381 static void wout_m1_32a(DisasContext
*s
, DisasOps
*o
)
5383 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUL
| MO_ALIGN
);
5385 #define SPEC_wout_m1_32a 0
5388 static void wout_m1_64(DisasContext
*s
, DisasOps
*o
)
5390 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUQ
);
5392 #define SPEC_wout_m1_64 0
5394 #ifndef CONFIG_USER_ONLY
5395 static void wout_m1_64a(DisasContext
*s
, DisasOps
*o
)
5397 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUQ
| MO_ALIGN
);
5399 #define SPEC_wout_m1_64a 0
5402 static void wout_m2_32(DisasContext
*s
, DisasOps
*o
)
5404 tcg_gen_qemu_st_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TEUL
);
5406 #define SPEC_wout_m2_32 0
5408 static void wout_in2_r1(DisasContext
*s
, DisasOps
*o
)
5410 store_reg(get_field(s
, r1
), o
->in2
);
5412 #define SPEC_wout_in2_r1 0
5414 static void wout_in2_r1_32(DisasContext
*s
, DisasOps
*o
)
5416 store_reg32_i64(get_field(s
, r1
), o
->in2
);
5418 #define SPEC_wout_in2_r1_32 0
5420 /* ====================================================================== */
5421 /* The "INput 1" generators. These load the first operand to an insn. */
5423 static void in1_r1(DisasContext
*s
, DisasOps
*o
)
5425 o
->in1
= load_reg(get_field(s
, r1
));
5427 #define SPEC_in1_r1 0
5429 static void in1_r1_o(DisasContext
*s
, DisasOps
*o
)
5431 o
->in1
= regs
[get_field(s
, r1
)];
5433 #define SPEC_in1_r1_o 0
5435 static void in1_r1_32s(DisasContext
*s
, DisasOps
*o
)
5437 o
->in1
= tcg_temp_new_i64();
5438 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(s
, r1
)]);
5440 #define SPEC_in1_r1_32s 0
5442 static void in1_r1_32u(DisasContext
*s
, DisasOps
*o
)
5444 o
->in1
= tcg_temp_new_i64();
5445 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(s
, r1
)]);
5447 #define SPEC_in1_r1_32u 0
5449 static void in1_r1_sr32(DisasContext
*s
, DisasOps
*o
)
5451 o
->in1
= tcg_temp_new_i64();
5452 tcg_gen_shri_i64(o
->in1
, regs
[get_field(s
, r1
)], 32);
5454 #define SPEC_in1_r1_sr32 0
5456 static void in1_r1p1(DisasContext
*s
, DisasOps
*o
)
5458 o
->in1
= load_reg(get_field(s
, r1
) + 1);
5460 #define SPEC_in1_r1p1 SPEC_r1_even
5462 static void in1_r1p1_o(DisasContext
*s
, DisasOps
*o
)
5464 o
->in1
= regs
[get_field(s
, r1
) + 1];
5466 #define SPEC_in1_r1p1_o SPEC_r1_even
5468 static void in1_r1p1_32s(DisasContext
*s
, DisasOps
*o
)
5470 o
->in1
= tcg_temp_new_i64();
5471 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(s
, r1
) + 1]);
5473 #define SPEC_in1_r1p1_32s SPEC_r1_even
5475 static void in1_r1p1_32u(DisasContext
*s
, DisasOps
*o
)
5477 o
->in1
= tcg_temp_new_i64();
5478 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(s
, r1
) + 1]);
5480 #define SPEC_in1_r1p1_32u SPEC_r1_even
5482 static void in1_r1_D32(DisasContext
*s
, DisasOps
*o
)
5484 int r1
= get_field(s
, r1
);
5485 o
->in1
= tcg_temp_new_i64();
5486 tcg_gen_concat32_i64(o
->in1
, regs
[r1
+ 1], regs
[r1
]);
5488 #define SPEC_in1_r1_D32 SPEC_r1_even
5490 static void in1_r2(DisasContext
*s
, DisasOps
*o
)
5492 o
->in1
= load_reg(get_field(s
, r2
));
5494 #define SPEC_in1_r2 0
5496 static void in1_r2_sr32(DisasContext
*s
, DisasOps
*o
)
5498 o
->in1
= tcg_temp_new_i64();
5499 tcg_gen_shri_i64(o
->in1
, regs
[get_field(s
, r2
)], 32);
5501 #define SPEC_in1_r2_sr32 0
5503 static void in1_r2_32u(DisasContext
*s
, DisasOps
*o
)
5505 o
->in1
= tcg_temp_new_i64();
5506 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(s
, r2
)]);
5508 #define SPEC_in1_r2_32u 0
5510 static void in1_r3(DisasContext
*s
, DisasOps
*o
)
5512 o
->in1
= load_reg(get_field(s
, r3
));
5514 #define SPEC_in1_r3 0
5516 static void in1_r3_o(DisasContext
*s
, DisasOps
*o
)
5518 o
->in1
= regs
[get_field(s
, r3
)];
5520 #define SPEC_in1_r3_o 0
5522 static void in1_r3_32s(DisasContext
*s
, DisasOps
*o
)
5524 o
->in1
= tcg_temp_new_i64();
5525 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(s
, r3
)]);
5527 #define SPEC_in1_r3_32s 0
5529 static void in1_r3_32u(DisasContext
*s
, DisasOps
*o
)
5531 o
->in1
= tcg_temp_new_i64();
5532 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(s
, r3
)]);
5534 #define SPEC_in1_r3_32u 0
5536 static void in1_r3_D32(DisasContext
*s
, DisasOps
*o
)
5538 int r3
= get_field(s
, r3
);
5539 o
->in1
= tcg_temp_new_i64();
5540 tcg_gen_concat32_i64(o
->in1
, regs
[r3
+ 1], regs
[r3
]);
5542 #define SPEC_in1_r3_D32 SPEC_r3_even
5544 static void in1_r3_sr32(DisasContext
*s
, DisasOps
*o
)
5546 o
->in1
= tcg_temp_new_i64();
5547 tcg_gen_shri_i64(o
->in1
, regs
[get_field(s
, r3
)], 32);
5549 #define SPEC_in1_r3_sr32 0
5551 static void in1_e1(DisasContext
*s
, DisasOps
*o
)
5553 o
->in1
= load_freg32_i64(get_field(s
, r1
));
5555 #define SPEC_in1_e1 0
5557 static void in1_f1(DisasContext
*s
, DisasOps
*o
)
5559 o
->in1
= load_freg(get_field(s
, r1
));
5561 #define SPEC_in1_f1 0
5563 static void in1_x1(DisasContext
*s
, DisasOps
*o
)
5565 o
->in1_128
= load_freg_128(get_field(s
, r1
));
5567 #define SPEC_in1_x1 SPEC_r1_f128
5569 /* Load the high double word of an extended (128-bit) format FP number */
5570 static void in1_x2h(DisasContext
*s
, DisasOps
*o
)
5572 o
->in1
= load_freg(get_field(s
, r2
));
5574 #define SPEC_in1_x2h SPEC_r2_f128
5576 static void in1_f3(DisasContext
*s
, DisasOps
*o
)
5578 o
->in1
= load_freg(get_field(s
, r3
));
5580 #define SPEC_in1_f3 0
5582 static void in1_la1(DisasContext
*s
, DisasOps
*o
)
5584 o
->addr1
= get_address(s
, 0, get_field(s
, b1
), get_field(s
, d1
));
5586 #define SPEC_in1_la1 0
5588 static void in1_la2(DisasContext
*s
, DisasOps
*o
)
5590 int x2
= have_field(s
, x2
) ? get_field(s
, x2
) : 0;
5591 o
->addr1
= get_address(s
, x2
, get_field(s
, b2
), get_field(s
, d2
));
5593 #define SPEC_in1_la2 0
5595 static void in1_m1_8u(DisasContext
*s
, DisasOps
*o
)
5598 o
->in1
= tcg_temp_new_i64();
5599 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_UB
);
5601 #define SPEC_in1_m1_8u 0
5603 static void in1_m1_16s(DisasContext
*s
, DisasOps
*o
)
5606 o
->in1
= tcg_temp_new_i64();
5607 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TESW
);
5609 #define SPEC_in1_m1_16s 0
5611 static void in1_m1_16u(DisasContext
*s
, DisasOps
*o
)
5614 o
->in1
= tcg_temp_new_i64();
5615 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TEUW
);
5617 #define SPEC_in1_m1_16u 0
5619 static void in1_m1_32s(DisasContext
*s
, DisasOps
*o
)
5622 o
->in1
= tcg_temp_new_i64();
5623 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TESL
);
5625 #define SPEC_in1_m1_32s 0
5627 static void in1_m1_32u(DisasContext
*s
, DisasOps
*o
)
5630 o
->in1
= tcg_temp_new_i64();
5631 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TEUL
);
5633 #define SPEC_in1_m1_32u 0
5635 static void in1_m1_64(DisasContext
*s
, DisasOps
*o
)
5638 o
->in1
= tcg_temp_new_i64();
5639 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TEUQ
);
5641 #define SPEC_in1_m1_64 0
5643 /* ====================================================================== */
5644 /* The "INput 2" generators. These load the second operand to an insn. */
5646 static void in2_r1_o(DisasContext
*s
, DisasOps
*o
)
5648 o
->in2
= regs
[get_field(s
, r1
)];
5650 #define SPEC_in2_r1_o 0
5652 static void in2_r1_16u(DisasContext
*s
, DisasOps
*o
)
5654 o
->in2
= tcg_temp_new_i64();
5655 tcg_gen_ext16u_i64(o
->in2
, regs
[get_field(s
, r1
)]);
5657 #define SPEC_in2_r1_16u 0
5659 static void in2_r1_32u(DisasContext
*s
, DisasOps
*o
)
5661 o
->in2
= tcg_temp_new_i64();
5662 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(s
, r1
)]);
5664 #define SPEC_in2_r1_32u 0
5666 static void in2_r1_D32(DisasContext
*s
, DisasOps
*o
)
5668 int r1
= get_field(s
, r1
);
5669 o
->in2
= tcg_temp_new_i64();
5670 tcg_gen_concat32_i64(o
->in2
, regs
[r1
+ 1], regs
[r1
]);
5672 #define SPEC_in2_r1_D32 SPEC_r1_even
5674 static void in2_r2(DisasContext
*s
, DisasOps
*o
)
5676 o
->in2
= load_reg(get_field(s
, r2
));
5678 #define SPEC_in2_r2 0
5680 static void in2_r2_o(DisasContext
*s
, DisasOps
*o
)
5682 o
->in2
= regs
[get_field(s
, r2
)];
5684 #define SPEC_in2_r2_o 0
5686 static void in2_r2_nz(DisasContext
*s
, DisasOps
*o
)
5688 int r2
= get_field(s
, r2
);
5690 o
->in2
= load_reg(r2
);
5693 #define SPEC_in2_r2_nz 0
5695 static void in2_r2_8s(DisasContext
*s
, DisasOps
*o
)
5697 o
->in2
= tcg_temp_new_i64();
5698 tcg_gen_ext8s_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5700 #define SPEC_in2_r2_8s 0
5702 static void in2_r2_8u(DisasContext
*s
, DisasOps
*o
)
5704 o
->in2
= tcg_temp_new_i64();
5705 tcg_gen_ext8u_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5707 #define SPEC_in2_r2_8u 0
5709 static void in2_r2_16s(DisasContext
*s
, DisasOps
*o
)
5711 o
->in2
= tcg_temp_new_i64();
5712 tcg_gen_ext16s_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5714 #define SPEC_in2_r2_16s 0
5716 static void in2_r2_16u(DisasContext
*s
, DisasOps
*o
)
5718 o
->in2
= tcg_temp_new_i64();
5719 tcg_gen_ext16u_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5721 #define SPEC_in2_r2_16u 0
5723 static void in2_r3(DisasContext
*s
, DisasOps
*o
)
5725 o
->in2
= load_reg(get_field(s
, r3
));
5727 #define SPEC_in2_r3 0
5729 static void in2_r3_D64(DisasContext
*s
, DisasOps
*o
)
5731 int r3
= get_field(s
, r3
);
5732 o
->in2_128
= tcg_temp_new_i128();
5733 tcg_gen_concat_i64_i128(o
->in2_128
, regs
[r3
+ 1], regs
[r3
]);
5735 #define SPEC_in2_r3_D64 SPEC_r3_even
5737 static void in2_r3_sr32(DisasContext
*s
, DisasOps
*o
)
5739 o
->in2
= tcg_temp_new_i64();
5740 tcg_gen_shri_i64(o
->in2
, regs
[get_field(s
, r3
)], 32);
5742 #define SPEC_in2_r3_sr32 0
5744 static void in2_r3_32u(DisasContext
*s
, DisasOps
*o
)
5746 o
->in2
= tcg_temp_new_i64();
5747 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(s
, r3
)]);
5749 #define SPEC_in2_r3_32u 0
5751 static void in2_r2_32s(DisasContext
*s
, DisasOps
*o
)
5753 o
->in2
= tcg_temp_new_i64();
5754 tcg_gen_ext32s_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5756 #define SPEC_in2_r2_32s 0
5758 static void in2_r2_32u(DisasContext
*s
, DisasOps
*o
)
5760 o
->in2
= tcg_temp_new_i64();
5761 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5763 #define SPEC_in2_r2_32u 0
5765 static void in2_r2_sr32(DisasContext
*s
, DisasOps
*o
)
5767 o
->in2
= tcg_temp_new_i64();
5768 tcg_gen_shri_i64(o
->in2
, regs
[get_field(s
, r2
)], 32);
5770 #define SPEC_in2_r2_sr32 0
5772 static void in2_e2(DisasContext
*s
, DisasOps
*o
)
5774 o
->in2
= load_freg32_i64(get_field(s
, r2
));
5776 #define SPEC_in2_e2 0
5778 static void in2_f2(DisasContext
*s
, DisasOps
*o
)
5780 o
->in2
= load_freg(get_field(s
, r2
));
5782 #define SPEC_in2_f2 0
5784 static void in2_x2(DisasContext
*s
, DisasOps
*o
)
5786 o
->in2_128
= load_freg_128(get_field(s
, r2
));
5788 #define SPEC_in2_x2 SPEC_r2_f128
5790 /* Load the low double word of an extended (128-bit) format FP number */
5791 static void in2_x2l(DisasContext
*s
, DisasOps
*o
)
5793 o
->in2
= load_freg(get_field(s
, r2
) + 2);
5795 #define SPEC_in2_x2l SPEC_r2_f128
5797 static void in2_ra2(DisasContext
*s
, DisasOps
*o
)
5799 int r2
= get_field(s
, r2
);
5801 /* Note: *don't* treat !r2 as 0, use the reg value. */
5802 o
->in2
= tcg_temp_new_i64();
5803 gen_addi_and_wrap_i64(s
, o
->in2
, regs
[r2
], 0);
5805 #define SPEC_in2_ra2 0
5807 static void in2_ra2_E(DisasContext
*s
, DisasOps
*o
)
5809 return in2_ra2(s
, o
);
5811 #define SPEC_in2_ra2_E SPEC_r2_even
5813 static void in2_a2(DisasContext
*s
, DisasOps
*o
)
5815 int x2
= have_field(s
, x2
) ? get_field(s
, x2
) : 0;
5816 o
->in2
= get_address(s
, x2
, get_field(s
, b2
), get_field(s
, d2
));
5818 #define SPEC_in2_a2 0
5820 static TCGv
gen_ri2(DisasContext
*s
)
5826 disas_jdest(s
, i2
, is_imm
, imm
, ri2
);
5828 ri2
= tcg_constant_i64(s
->base
.pc_next
+ (int64_t)imm
* 2);
5834 static void in2_ri2(DisasContext
*s
, DisasOps
*o
)
5836 o
->in2
= gen_ri2(s
);
5838 #define SPEC_in2_ri2 0
5840 static void in2_sh(DisasContext
*s
, DisasOps
*o
)
5842 int b2
= get_field(s
, b2
);
5843 int d2
= get_field(s
, d2
);
5846 o
->in2
= tcg_constant_i64(d2
& 0x3f);
5848 o
->in2
= get_address(s
, 0, b2
, d2
);
5849 tcg_gen_andi_i64(o
->in2
, o
->in2
, 0x3f);
5852 #define SPEC_in2_sh 0
5854 static void in2_m2_8u(DisasContext
*s
, DisasOps
*o
)
5857 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_UB
);
5859 #define SPEC_in2_m2_8u 0
5861 static void in2_m2_16s(DisasContext
*s
, DisasOps
*o
)
5864 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TESW
);
5866 #define SPEC_in2_m2_16s 0
5868 static void in2_m2_16u(DisasContext
*s
, DisasOps
*o
)
5871 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUW
);
5873 #define SPEC_in2_m2_16u 0
5875 static void in2_m2_32s(DisasContext
*s
, DisasOps
*o
)
5878 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TESL
);
5880 #define SPEC_in2_m2_32s 0
5882 static void in2_m2_32u(DisasContext
*s
, DisasOps
*o
)
5885 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUL
);
5887 #define SPEC_in2_m2_32u 0
5889 #ifndef CONFIG_USER_ONLY
5890 static void in2_m2_32ua(DisasContext
*s
, DisasOps
*o
)
5893 tcg_gen_qemu_ld_tl(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUL
| MO_ALIGN
);
5895 #define SPEC_in2_m2_32ua 0
5898 static void in2_m2_64(DisasContext
*s
, DisasOps
*o
)
5901 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
5903 #define SPEC_in2_m2_64 0
5905 static void in2_m2_64w(DisasContext
*s
, DisasOps
*o
)
5908 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
5909 gen_addi_and_wrap_i64(s
, o
->in2
, o
->in2
, 0);
5911 #define SPEC_in2_m2_64w 0
5913 #ifndef CONFIG_USER_ONLY
5914 static void in2_m2_64a(DisasContext
*s
, DisasOps
*o
)
5917 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUQ
| MO_ALIGN
);
5919 #define SPEC_in2_m2_64a 0
5922 static void in2_mri2_16s(DisasContext
*s
, DisasOps
*o
)
5924 o
->in2
= tcg_temp_new_i64();
5925 tcg_gen_qemu_ld_i64(o
->in2
, gen_ri2(s
), get_mem_index(s
), MO_TESW
);
5927 #define SPEC_in2_mri2_16s 0
5929 static void in2_mri2_16u(DisasContext
*s
, DisasOps
*o
)
5931 o
->in2
= tcg_temp_new_i64();
5932 tcg_gen_qemu_ld_i64(o
->in2
, gen_ri2(s
), get_mem_index(s
), MO_TEUW
);
5934 #define SPEC_in2_mri2_16u 0
5936 static void in2_mri2_32s(DisasContext
*s
, DisasOps
*o
)
5938 o
->in2
= tcg_temp_new_i64();
5939 tcg_gen_qemu_ld_tl(o
->in2
, gen_ri2(s
), get_mem_index(s
),
5940 MO_TESL
| MO_ALIGN
);
5942 #define SPEC_in2_mri2_32s 0
5944 static void in2_mri2_32u(DisasContext
*s
, DisasOps
*o
)
5946 o
->in2
= tcg_temp_new_i64();
5947 tcg_gen_qemu_ld_tl(o
->in2
, gen_ri2(s
), get_mem_index(s
),
5948 MO_TEUL
| MO_ALIGN
);
5950 #define SPEC_in2_mri2_32u 0
5952 static void in2_mri2_64(DisasContext
*s
, DisasOps
*o
)
5954 o
->in2
= tcg_temp_new_i64();
5955 tcg_gen_qemu_ld_i64(o
->in2
, gen_ri2(s
), get_mem_index(s
),
5956 MO_TEUQ
| MO_ALIGN
);
5958 #define SPEC_in2_mri2_64 0
5960 static void in2_i2(DisasContext
*s
, DisasOps
*o
)
5962 o
->in2
= tcg_constant_i64(get_field(s
, i2
));
5964 #define SPEC_in2_i2 0
5966 static void in2_i2_8u(DisasContext
*s
, DisasOps
*o
)
5968 o
->in2
= tcg_constant_i64((uint8_t)get_field(s
, i2
));
5970 #define SPEC_in2_i2_8u 0
5972 static void in2_i2_16u(DisasContext
*s
, DisasOps
*o
)
5974 o
->in2
= tcg_constant_i64((uint16_t)get_field(s
, i2
));
5976 #define SPEC_in2_i2_16u 0
5978 static void in2_i2_32u(DisasContext
*s
, DisasOps
*o
)
5980 o
->in2
= tcg_constant_i64((uint32_t)get_field(s
, i2
));
5982 #define SPEC_in2_i2_32u 0
5984 static void in2_i2_16u_shl(DisasContext
*s
, DisasOps
*o
)
5986 uint64_t i2
= (uint16_t)get_field(s
, i2
);
5987 o
->in2
= tcg_constant_i64(i2
<< s
->insn
->data
);
5989 #define SPEC_in2_i2_16u_shl 0
5991 static void in2_i2_32u_shl(DisasContext
*s
, DisasOps
*o
)
5993 uint64_t i2
= (uint32_t)get_field(s
, i2
);
5994 o
->in2
= tcg_constant_i64(i2
<< s
->insn
->data
);
5996 #define SPEC_in2_i2_32u_shl 0
5998 #ifndef CONFIG_USER_ONLY
5999 static void in2_insn(DisasContext
*s
, DisasOps
*o
)
6001 o
->in2
= tcg_constant_i64(s
->fields
.raw_insn
);
6003 #define SPEC_in2_insn 0
6006 /* ====================================================================== */
6008 /* Find opc within the table of insns. This is formulated as a switch
6009 statement so that (1) we get compile-time notice of cut-paste errors
6010 for duplicated opcodes, and (2) the compiler generates the binary
6011 search tree, rather than us having to post-process the table. */
6013 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
6014 E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0, 0)
6016 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
6017 E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, 0)
6019 #define F(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, FL) \
6020 E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0, FL)
6022 #define E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, FL) insn_ ## NM,
6024 enum DisasInsnEnum
{
6025 #include "insn-data.h.inc"
6029 #define E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, FL) { \
6034 .spec = SPEC_in1_##I1 | SPEC_in2_##I2 | SPEC_prep_##P | SPEC_wout_##W, \
6036 .help_in1 = in1_##I1, \
6037 .help_in2 = in2_##I2, \
6038 .help_prep = prep_##P, \
6039 .help_wout = wout_##W, \
6040 .help_cout = cout_##CC, \
6041 .help_op = op_##OP, \
6045 /* Allow 0 to be used for NULL in the table below. */
6053 #define SPEC_in1_0 0
6054 #define SPEC_in2_0 0
6055 #define SPEC_prep_0 0
6056 #define SPEC_wout_0 0
6058 /* Give smaller names to the various facilities. */
6059 #define FAC_Z S390_FEAT_ZARCH
6060 #define FAC_CASS S390_FEAT_COMPARE_AND_SWAP_AND_STORE
6061 #define FAC_DFP S390_FEAT_DFP
6062 #define FAC_DFPR S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* DFP-rounding */
6063 #define FAC_DO S390_FEAT_STFLE_45 /* distinct-operands */
6064 #define FAC_EE S390_FEAT_EXECUTE_EXT
6065 #define FAC_EI S390_FEAT_EXTENDED_IMMEDIATE
6066 #define FAC_FPE S390_FEAT_FLOATING_POINT_EXT
6067 #define FAC_FPSSH S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* FPS-sign-handling */
6068 #define FAC_FPRGR S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* FPR-GR-transfer */
6069 #define FAC_GIE S390_FEAT_GENERAL_INSTRUCTIONS_EXT
6070 #define FAC_HFP_MA S390_FEAT_HFP_MADDSUB
6071 #define FAC_HW S390_FEAT_STFLE_45 /* high-word */
6072 #define FAC_IEEEE_SIM S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* IEEE-exception-simulation */
6073 #define FAC_MIE S390_FEAT_STFLE_49 /* misc-instruction-extensions */
6074 #define FAC_LAT S390_FEAT_STFLE_49 /* load-and-trap */
6075 #define FAC_LOC S390_FEAT_STFLE_45 /* load/store on condition 1 */
6076 #define FAC_LOC2 S390_FEAT_STFLE_53 /* load/store on condition 2 */
6077 #define FAC_LD S390_FEAT_LONG_DISPLACEMENT
6078 #define FAC_PC S390_FEAT_STFLE_45 /* population count */
6079 #define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
6080 #define FAC_SFLE S390_FEAT_STFLE
6081 #define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
6082 #define FAC_MVCOS S390_FEAT_MOVE_WITH_OPTIONAL_SPEC
6083 #define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
6084 #define FAC_DAT_ENH S390_FEAT_DAT_ENH
6085 #define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
6086 #define FAC_EH S390_FEAT_STFLE_49 /* execution-hint */
6087 #define FAC_PPA S390_FEAT_STFLE_49 /* processor-assist */
6088 #define FAC_LZRB S390_FEAT_STFLE_53 /* load-and-zero-rightmost-byte */
6089 #define FAC_ETF3 S390_FEAT_EXTENDED_TRANSLATION_3
6090 #define FAC_MSA S390_FEAT_MSA /* message-security-assist facility */
6091 #define FAC_MSA3 S390_FEAT_MSA_EXT_3 /* msa-extension-3 facility */
6092 #define FAC_MSA4 S390_FEAT_MSA_EXT_4 /* msa-extension-4 facility */
6093 #define FAC_MSA5 S390_FEAT_MSA_EXT_5 /* msa-extension-5 facility */
6094 #define FAC_MSA8 S390_FEAT_MSA_EXT_8 /* msa-extension-8 facility */
6095 #define FAC_ECT S390_FEAT_EXTRACT_CPU_TIME
6096 #define FAC_PCI S390_FEAT_ZPCI /* z/PCI facility */
6097 #define FAC_AIS S390_FEAT_ADAPTER_INT_SUPPRESSION
6098 #define FAC_V S390_FEAT_VECTOR /* vector facility */
6099 #define FAC_VE S390_FEAT_VECTOR_ENH /* vector enhancements facility 1 */
6100 #define FAC_VE2 S390_FEAT_VECTOR_ENH2 /* vector enhancements facility 2 */
6101 #define FAC_MIE2 S390_FEAT_MISC_INSTRUCTION_EXT2 /* miscellaneous-instruction-extensions facility 2 */
6102 #define FAC_MIE3 S390_FEAT_MISC_INSTRUCTION_EXT3 /* miscellaneous-instruction-extensions facility 3 */
6104 static const DisasInsn insn_info
[] = {
6105 #include "insn-data.h.inc"
6109 #define E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, FL) \
6110 case OPC: return &insn_info[insn_ ## NM];
6112 static const DisasInsn
*lookup_opc(uint16_t opc
)
6115 #include "insn-data.h.inc"
6126 /* Extract a field from the insn. The INSN should be left-aligned in
6127 the uint64_t so that we can more easily utilize the big-bit-endian
6128 definitions we extract from the Principals of Operation. */
6130 static void extract_field(DisasFields
*o
, const DisasField
*f
, uint64_t insn
)
6138 /* Zero extract the field from the insn. */
6139 r
= (insn
<< f
->beg
) >> (64 - f
->size
);
6141 /* Sign-extend, or un-swap the field as necessary. */
6143 case 0: /* unsigned */
6145 case 1: /* signed */
6146 assert(f
->size
<= 32);
6147 m
= 1u << (f
->size
- 1);
6150 case 2: /* dl+dh split, signed 20 bit. */
6151 r
= ((int8_t)r
<< 12) | (r
>> 8);
6153 case 3: /* MSB stored in RXB */
6154 g_assert(f
->size
== 4);
6157 r
|= extract64(insn
, 63 - 36, 1) << 4;
6160 r
|= extract64(insn
, 63 - 37, 1) << 4;
6163 r
|= extract64(insn
, 63 - 38, 1) << 4;
6166 r
|= extract64(insn
, 63 - 39, 1) << 4;
6169 g_assert_not_reached();
6177 * Validate that the "compressed" encoding we selected above is valid.
6178 * I.e. we haven't made two different original fields overlap.
6180 assert(((o
->presentC
>> f
->indexC
) & 1) == 0);
6181 o
->presentC
|= 1 << f
->indexC
;
6182 o
->presentO
|= 1 << f
->indexO
;
6184 o
->c
[f
->indexC
] = r
;
6187 /* Lookup the insn at the current PC, extracting the operands into O and
6188 returning the info struct for the insn. Returns NULL for invalid insn. */
6190 static const DisasInsn
*extract_insn(CPUS390XState
*env
, DisasContext
*s
)
6192 uint64_t insn
, pc
= s
->base
.pc_next
;
6194 const DisasInsn
*info
;
6196 if (unlikely(s
->ex_value
)) {
6197 /* Drop the EX data now, so that it's clear on exception paths. */
6198 tcg_gen_st_i64(tcg_constant_i64(0), tcg_env
,
6199 offsetof(CPUS390XState
, ex_value
));
6201 /* Extract the values saved by EXECUTE. */
6202 insn
= s
->ex_value
& 0xffffffffffff0000ull
;
6203 ilen
= s
->ex_value
& 0xf;
6205 /* Register insn bytes with translator so plugins work. */
6206 for (int i
= 0; i
< ilen
; i
++) {
6207 uint8_t byte
= extract64(insn
, 56 - (i
* 8), 8);
6208 translator_fake_ldb(byte
, pc
+ i
);
6212 insn
= ld_code2(env
, s
, pc
);
6213 op
= (insn
>> 8) & 0xff;
6214 ilen
= get_ilen(op
);
6220 insn
= ld_code4(env
, s
, pc
) << 32;
6223 insn
= (insn
<< 48) | (ld_code4(env
, s
, pc
+ 2) << 16);
6226 g_assert_not_reached();
6229 s
->pc_tmp
= s
->base
.pc_next
+ ilen
;
6232 /* We can't actually determine the insn format until we've looked up
6233 the full insn opcode. Which we can't do without locating the
6234 secondary opcode. Assume by default that OP2 is at bit 40; for
6235 those smaller insns that don't actually have a secondary opcode
6236 this will correctly result in OP2 = 0. */
6242 case 0xb2: /* S, RRF, RRE, IE */
6243 case 0xb3: /* RRE, RRD, RRF */
6244 case 0xb9: /* RRE, RRF */
6245 case 0xe5: /* SSE, SIL */
6246 op2
= (insn
<< 8) >> 56;
6250 case 0xc0: /* RIL */
6251 case 0xc2: /* RIL */
6252 case 0xc4: /* RIL */
6253 case 0xc6: /* RIL */
6254 case 0xc8: /* SSF */
6255 case 0xcc: /* RIL */
6256 op2
= (insn
<< 12) >> 60;
6258 case 0xc5: /* MII */
6259 case 0xc7: /* SMI */
6260 case 0xd0 ... 0xdf: /* SS */
6266 case 0xee ... 0xf3: /* SS */
6267 case 0xf8 ... 0xfd: /* SS */
6271 op2
= (insn
<< 40) >> 56;
6275 memset(&s
->fields
, 0, sizeof(s
->fields
));
6276 s
->fields
.raw_insn
= insn
;
6278 s
->fields
.op2
= op2
;
6280 /* Lookup the instruction. */
6281 info
= lookup_opc(op
<< 8 | op2
);
6284 /* If we found it, extract the operands. */
6286 DisasFormat fmt
= info
->fmt
;
6289 for (i
= 0; i
< NUM_C_FIELD
; ++i
) {
6290 extract_field(&s
->fields
, &format_info
[fmt
].op
[i
], insn
);
6296 static bool is_afp_reg(int reg
)
6298 return reg
% 2 || reg
> 6;
6301 static bool is_fp_pair(int reg
)
6303 /* 0,1,4,5,8,9,12,13: to exclude the others, check for single bit */
6304 return !(reg
& 0x2);
6307 static DisasJumpType
translate_one(CPUS390XState
*env
, DisasContext
*s
)
6309 const DisasInsn
*insn
;
6310 DisasJumpType ret
= DISAS_NEXT
;
6312 bool icount
= false;
6314 /* Search for the insn in the table. */
6315 insn
= extract_insn(env
, s
);
6317 /* Update insn_start now that we know the ILEN. */
6318 tcg_set_insn_start_param(s
->insn_start
, 2, s
->ilen
);
6320 /* Not found means unimplemented/illegal opcode. */
6322 qemu_log_mask(LOG_UNIMP
, "unimplemented opcode 0x%02x%02x\n",
6323 s
->fields
.op
, s
->fields
.op2
);
6324 gen_illegal_opcode(s
);
6325 ret
= DISAS_NORETURN
;
6329 #ifndef CONFIG_USER_ONLY
6330 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
6331 TCGv_i64 addr
= tcg_constant_i64(s
->base
.pc_next
);
6332 gen_helper_per_ifetch(tcg_env
, addr
);
6338 /* privileged instruction */
6339 if ((s
->base
.tb
->flags
& FLAG_MASK_PSTATE
) && (insn
->flags
& IF_PRIV
)) {
6340 gen_program_exception(s
, PGM_PRIVILEGED
);
6341 ret
= DISAS_NORETURN
;
6345 /* if AFP is not enabled, instructions and registers are forbidden */
6346 if (!(s
->base
.tb
->flags
& FLAG_MASK_AFP
)) {
6349 if ((insn
->flags
& IF_AFP1
) && is_afp_reg(get_field(s
, r1
))) {
6352 if ((insn
->flags
& IF_AFP2
) && is_afp_reg(get_field(s
, r2
))) {
6355 if ((insn
->flags
& IF_AFP3
) && is_afp_reg(get_field(s
, r3
))) {
6358 if (insn
->flags
& IF_BFP
) {
6361 if (insn
->flags
& IF_DFP
) {
6364 if (insn
->flags
& IF_VEC
) {
6368 gen_data_exception(dxc
);
6369 ret
= DISAS_NORETURN
;
6374 /* if vector instructions not enabled, executing them is forbidden */
6375 if (insn
->flags
& IF_VEC
) {
6376 if (!((s
->base
.tb
->flags
& FLAG_MASK_VECTOR
))) {
6377 gen_data_exception(0xfe);
6378 ret
= DISAS_NORETURN
;
6383 /* input/output is the special case for icount mode */
6384 if (unlikely(insn
->flags
& IF_IO
)) {
6385 icount
= translator_io_start(&s
->base
);
6389 /* Check for insn specification exceptions. */
6391 if ((insn
->spec
& SPEC_r1_even
&& get_field(s
, r1
) & 1) ||
6392 (insn
->spec
& SPEC_r2_even
&& get_field(s
, r2
) & 1) ||
6393 (insn
->spec
& SPEC_r3_even
&& get_field(s
, r3
) & 1) ||
6394 (insn
->spec
& SPEC_r1_f128
&& !is_fp_pair(get_field(s
, r1
))) ||
6395 (insn
->spec
& SPEC_r2_f128
&& !is_fp_pair(get_field(s
, r2
)))) {
6396 gen_program_exception(s
, PGM_SPECIFICATION
);
6397 ret
= DISAS_NORETURN
;
6402 /* Implement the instruction. */
6403 if (insn
->help_in1
) {
6404 insn
->help_in1(s
, &o
);
6406 if (insn
->help_in2
) {
6407 insn
->help_in2(s
, &o
);
6409 if (insn
->help_prep
) {
6410 insn
->help_prep(s
, &o
);
6412 if (insn
->help_op
) {
6413 ret
= insn
->help_op(s
, &o
);
6415 if (ret
!= DISAS_NORETURN
) {
6416 if (insn
->help_wout
) {
6417 insn
->help_wout(s
, &o
);
6419 if (insn
->help_cout
) {
6420 insn
->help_cout(s
, &o
);
6424 /* io should be the last instruction in tb when icount is enabled */
6425 if (unlikely(icount
&& ret
== DISAS_NEXT
)) {
6426 ret
= DISAS_TOO_MANY
;
6429 #ifndef CONFIG_USER_ONLY
6430 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
6431 /* An exception might be triggered, save PSW if not already done. */
6432 if (ret
== DISAS_NEXT
|| ret
== DISAS_TOO_MANY
) {
6433 tcg_gen_movi_i64(psw_addr
, s
->pc_tmp
);
6436 /* Call the helper to check for a possible PER exception. */
6437 gen_helper_per_check_exception(tcg_env
);
6442 /* Advance to the next instruction. */
6443 s
->base
.pc_next
= s
->pc_tmp
;
6447 static void s390x_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
6449 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6452 if (!(dc
->base
.tb
->flags
& FLAG_MASK_64
)) {
6453 dc
->base
.pc_first
&= 0x7fffffff;
6454 dc
->base
.pc_next
= dc
->base
.pc_first
;
6457 dc
->cc_op
= CC_OP_DYNAMIC
;
6458 dc
->ex_value
= dc
->base
.tb
->cs_base
;
6459 dc
->exit_to_mainloop
= (dc
->base
.tb
->flags
& FLAG_MASK_PER
) || dc
->ex_value
;
6462 static void s390x_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
6466 static void s390x_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
6468 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6470 /* Delay the set of ilen until we've read the insn. */
6471 tcg_gen_insn_start(dc
->base
.pc_next
, dc
->cc_op
, 0);
6472 dc
->insn_start
= tcg_last_op();
6475 static target_ulong
get_next_pc(CPUS390XState
*env
, DisasContext
*s
,
6478 uint64_t insn
= cpu_lduw_code(env
, pc
);
6480 return pc
+ get_ilen((insn
>> 8) & 0xff);
6483 static void s390x_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
6485 CPUS390XState
*env
= cpu_env(cs
);
6486 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6488 dc
->base
.is_jmp
= translate_one(env
, dc
);
6489 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
6491 !is_same_page(dcbase
, dc
->base
.pc_next
) ||
6492 !is_same_page(dcbase
, get_next_pc(env
, dc
, dc
->base
.pc_next
))) {
6493 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
6498 static void s390x_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
6500 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6502 switch (dc
->base
.is_jmp
) {
6503 case DISAS_NORETURN
:
6505 case DISAS_TOO_MANY
:
6506 update_psw_addr(dc
);
6508 case DISAS_PC_UPDATED
:
6509 /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
6510 cc op type is in env */
6513 case DISAS_PC_CC_UPDATED
:
6514 /* Exit the TB, either by raising a debug exception or by return. */
6515 if (dc
->exit_to_mainloop
) {
6516 tcg_gen_exit_tb(NULL
, 0);
6518 tcg_gen_lookup_and_goto_ptr();
6522 g_assert_not_reached();
6526 static void s390x_tr_disas_log(const DisasContextBase
*dcbase
,
6527 CPUState
*cs
, FILE *logfile
)
6529 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6531 if (unlikely(dc
->ex_value
)) {
6532 /* ??? Unfortunately target_disas can't use host memory. */
6533 fprintf(logfile
, "IN: EXECUTE %016" PRIx64
, dc
->ex_value
);
6535 fprintf(logfile
, "IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
6536 target_disas(logfile
, cs
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
6540 static const TranslatorOps s390x_tr_ops
= {
6541 .init_disas_context
= s390x_tr_init_disas_context
,
6542 .tb_start
= s390x_tr_tb_start
,
6543 .insn_start
= s390x_tr_insn_start
,
6544 .translate_insn
= s390x_tr_translate_insn
,
6545 .tb_stop
= s390x_tr_tb_stop
,
6546 .disas_log
= s390x_tr_disas_log
,
6549 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
6550 target_ulong pc
, void *host_pc
)
6554 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &s390x_tr_ops
, &dc
.base
);
6557 void s390x_restore_state_to_opc(CPUState
*cs
,
6558 const TranslationBlock
*tb
,
6559 const uint64_t *data
)
6561 S390CPU
*cpu
= S390_CPU(cs
);
6562 CPUS390XState
*env
= &cpu
->env
;
6563 int cc_op
= data
[1];
6565 env
->psw
.addr
= data
[0];
6567 /* Update the CC opcode if it is not already up-to-date. */
6568 if ((cc_op
!= CC_OP_DYNAMIC
) && (cc_op
!= CC_OP_STATIC
)) {
6573 env
->int_pgm_ilen
= data
[2];