target/sh4/cpu.c

   1 /*
   2  * QEMU SuperH CPU
   3  *
   4  * Copyright (c) 2005 Samuel Tardieu
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "qemu/qemu-print.h"
  25 #include "cpu.h"
  26 #include "migration/vmstate.h"
  27 #include "exec/exec-all.h"
  28 #include "fpu/softfloat-helpers.h"
  29 #include "tcg/tcg.h"
  30
  31 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
  32 {
  33     SuperHCPU *cpu = SUPERH_CPU(cs);
  34
  35     cpu->env.pc = value;
  36 }
  37
  38 static vaddr superh_cpu_get_pc(CPUState *cs)
  39 {
  40     SuperHCPU *cpu = SUPERH_CPU(cs);
  41
  42     return cpu->env.pc;
  43 }
  44
  45 static void superh_cpu_synchronize_from_tb(CPUState *cs,
  46                                            const TranslationBlock *tb)
  47 {
  48     SuperHCPU *cpu = SUPERH_CPU(cs);
  49
  50     tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
  51     cpu->env.pc = tb->pc;
  52     cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
  53 }
  54
  55 static void superh_restore_state_to_opc(CPUState *cs,
  56                                         const TranslationBlock *tb,
  57                                         const uint64_t *data)
  58 {
  59     SuperHCPU *cpu = SUPERH_CPU(cs);
  60
  61     cpu->env.pc = data[0];
  62     cpu->env.flags = data[1];
  63     /*
  64      * Theoretically delayed_pc should also be restored. In practice the
  65      * branch instruction is re-executed after exception, so the delayed
  66      * branch target will be recomputed.
  67      */
  68 }
  69
  70 #ifndef CONFIG_USER_ONLY
  71 static bool superh_io_recompile_replay_branch(CPUState *cs,
  72                                               const TranslationBlock *tb)
  73 {
  74     CPUSH4State *env = cpu_env(cs);
  75
  76     if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
  77         && !tcg_cflags_has(cs, CF_PCREL) && env->pc != tb->pc) {
  78         env->pc -= 2;
  79         env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
  80         return true;
  81     }
  82     return false;
  83 }
  84 #endif
  85
  86 static bool superh_cpu_has_work(CPUState *cs)
  87 {
  88     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  89 }
  90
  91 static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
  92 {
  93     CPUSH4State *env = cpu_env(cs);
  94
  95     /*
  96      * The instruction in a RTE delay slot is fetched in privileged mode,
  97      * but executed in user mode.
  98      */
  99     if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
 100         return 0;
 101     } else {
 102         return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
 103     }
 104 }
 105
 106 static void superh_cpu_reset_hold(Object *obj, ResetType type)
 107 {
 108     CPUState *cs = CPU(obj);
 109     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj);
 110     CPUSH4State *env = cpu_env(cs);
 111
 112     if (scc->parent_phases.hold) {
 113         scc->parent_phases.hold(obj, type);
 114     }
 115
 116     memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
 117
 118     env->pc = 0xA0000000;
 119 #if defined(CONFIG_USER_ONLY)
 120     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
 121     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
 122 #else
 123     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
 124               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
 125     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
 126     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 127     set_flush_to_zero(1, &env->fp_status);
 128 #endif
 129     set_default_nan_mode(1, &env->fp_status);
 130 }
 131
 132 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 133 {
 134     info->mach = bfd_mach_sh4;
 135     info->print_insn = print_insn_sh;
 136 }
 137
 138 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
 139 {
 140     ObjectClass *oc;
 141     char *s, *typename = NULL;
 142
 143     s = g_ascii_strdown(cpu_model, -1);
 144     if (strcmp(s, "any") == 0) {
 145         oc = object_class_by_name(TYPE_SH7750R_CPU);
 146         goto out;
 147     }
 148
 149     typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
 150     oc = object_class_by_name(typename);
 151
 152 out:
 153     g_free(s);
 154     g_free(typename);
 155     return oc;
 156 }
 157
 158 static void sh7750r_cpu_initfn(Object *obj)
 159 {
 160     CPUSH4State *env = cpu_env(CPU(obj));
 161
 162     env->id = SH_CPU_SH7750R;
 163     env->features = SH_FEATURE_BCR3_AND_BCR4;
 164 }
 165
 166 static void sh7750r_class_init(ObjectClass *oc, void *data)
 167 {
 168     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 169
 170     scc->pvr = 0x00050000;
 171     scc->prr = 0x00000100;
 172     scc->cvr = 0x00110000;
 173 }
 174
 175 static void sh7751r_cpu_initfn(Object *obj)
 176 {
 177     CPUSH4State *env = cpu_env(CPU(obj));
 178
 179     env->id = SH_CPU_SH7751R;
 180     env->features = SH_FEATURE_BCR3_AND_BCR4;
 181 }
 182
 183 static void sh7751r_class_init(ObjectClass *oc, void *data)
 184 {
 185     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 186
 187     scc->pvr = 0x04050005;
 188     scc->prr = 0x00000113;
 189     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
 190 }
 191
 192 static void sh7785_cpu_initfn(Object *obj)
 193 {
 194     CPUSH4State *env = cpu_env(CPU(obj));
 195
 196     env->id = SH_CPU_SH7785;
 197     env->features = SH_FEATURE_SH4A;
 198 }
 199
 200 static void sh7785_class_init(ObjectClass *oc, void *data)
 201 {
 202     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 203
 204     scc->pvr = 0x10300700;
 205     scc->prr = 0x00000200;
 206     scc->cvr = 0x71440211;
 207 }
 208
 209 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
 210 {
 211     CPUState *cs = CPU(dev);
 212     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
 213     Error *local_err = NULL;
 214
 215     cpu_exec_realizefn(cs, &local_err);
 216     if (local_err != NULL) {
 217         error_propagate(errp, local_err);
 218         return;
 219     }
 220
 221     cpu_reset(cs);
 222     qemu_init_vcpu(cs);
 223
 224     scc->parent_realize(dev, errp);
 225 }
 226
 227 static void superh_cpu_initfn(Object *obj)
 228 {
 229     CPUSH4State *env = cpu_env(CPU(obj));
 230
 231     env->movcal_backup_tail = &(env->movcal_backup);
 232 }
 233
 234 #ifndef CONFIG_USER_ONLY
 235 static const VMStateDescription vmstate_sh_cpu = {
 236     .name = "cpu",
 237     .unmigratable = 1,
 238 };
 239
 240 #include "hw/core/sysemu-cpu-ops.h"
 241
 242 static const struct SysemuCPUOps sh4_sysemu_ops = {
 243     .get_phys_page_debug = superh_cpu_get_phys_page_debug,
 244 };
 245 #endif
 246
 247 #include "hw/core/tcg-cpu-ops.h"
 248
 249 static const TCGCPUOps superh_tcg_ops = {
 250     .initialize = sh4_translate_init,
 251     .synchronize_from_tb = superh_cpu_synchronize_from_tb,
 252     .restore_state_to_opc = superh_restore_state_to_opc,
 253
 254 #ifndef CONFIG_USER_ONLY
 255     .tlb_fill = superh_cpu_tlb_fill,
 256     .cpu_exec_interrupt = superh_cpu_exec_interrupt,
 257     .do_interrupt = superh_cpu_do_interrupt,
 258     .do_unaligned_access = superh_cpu_do_unaligned_access,
 259     .io_recompile_replay_branch = superh_io_recompile_replay_branch,
 260 #endif /* !CONFIG_USER_ONLY */
 261 };
 262
 263 static void superh_cpu_class_init(ObjectClass *oc, void *data)
 264 {
 265     DeviceClass *dc = DEVICE_CLASS(oc);
 266     CPUClass *cc = CPU_CLASS(oc);
 267     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 268     ResettableClass *rc = RESETTABLE_CLASS(oc);
 269
 270     device_class_set_parent_realize(dc, superh_cpu_realizefn,
 271                                     &scc->parent_realize);
 272
 273     resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL,
 274                                        &scc->parent_phases);
 275
 276     cc->class_by_name = superh_cpu_class_by_name;
 277     cc->has_work = superh_cpu_has_work;
 278     cc->mmu_index = sh4_cpu_mmu_index;
 279     cc->dump_state = superh_cpu_dump_state;
 280     cc->set_pc = superh_cpu_set_pc;
 281     cc->get_pc = superh_cpu_get_pc;
 282     cc->gdb_read_register = superh_cpu_gdb_read_register;
 283     cc->gdb_write_register = superh_cpu_gdb_write_register;
 284 #ifndef CONFIG_USER_ONLY
 285     cc->sysemu_ops = &sh4_sysemu_ops;
 286     dc->vmsd = &vmstate_sh_cpu;
 287 #endif
 288     cc->disas_set_info = superh_cpu_disas_set_info;
 289
 290     cc->gdb_num_core_regs = 59;
 291     cc->tcg_ops = &superh_tcg_ops;
 292 }
 293
 294 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
 295     {                                                    \
 296         .name = type_name,                               \
 297         .parent = TYPE_SUPERH_CPU,                       \
 298         .class_init = cinit,                             \
 299         .instance_init = initfn,                         \
 300     }
 301 static const TypeInfo superh_cpu_type_infos[] = {
 302     {
 303         .name = TYPE_SUPERH_CPU,
 304         .parent = TYPE_CPU,
 305         .instance_size = sizeof(SuperHCPU),
 306         .instance_align = __alignof(SuperHCPU),
 307         .instance_init = superh_cpu_initfn,
 308         .abstract = true,
 309         .class_size = sizeof(SuperHCPUClass),
 310         .class_init = superh_cpu_class_init,
 311     },
 312     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init,
 313                            sh7750r_cpu_initfn),
 314     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init,
 315                            sh7751r_cpu_initfn),
 316     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init,
 317                            sh7785_cpu_initfn),
 318
 319 };
 320
 321 DEFINE_TYPES(superh_cpu_type_infos)