target/sparc/cpu.c

   1 /*
   2  * Sparc CPU init helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu/module.h"
  24 #include "qemu/qemu-print.h"
  25 #include "exec/exec-all.h"
  26 #include "hw/qdev-properties.h"
  27 #include "qapi/visitor.h"
  28 #include "tcg/tcg.h"
  29
  30 //#define DEBUG_FEATURES
  31
  32 static void sparc_cpu_reset_hold(Object *obj)
  33 {
  34     CPUState *s = CPU(obj);
  35     SPARCCPU *cpu = SPARC_CPU(s);
  36     SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
  37     CPUSPARCState *env = &cpu->env;
  38
  39     if (scc->parent_phases.hold) {
  40         scc->parent_phases.hold(obj);
  41     }
  42
  43     memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
  44     env->cwp = 0;
  45 #ifndef TARGET_SPARC64
  46     env->wim = 1;
  47 #endif
  48     env->regwptr = env->regbase + (env->cwp * 16);
  49     CC_OP = CC_OP_FLAGS;
  50 #if defined(CONFIG_USER_ONLY)
  51 #ifdef TARGET_SPARC64
  52     env->cleanwin = env->nwindows - 2;
  53     env->cansave = env->nwindows - 2;
  54     env->pstate = PS_RMO | PS_PEF | PS_IE;
  55     env->asi = 0x82; /* Primary no-fault */
  56 #endif
  57 #else
  58 #if !defined(TARGET_SPARC64)
  59     env->psret = 0;
  60     env->psrs = 1;
  61     env->psrps = 1;
  62 #endif
  63 #ifdef TARGET_SPARC64
  64     env->pstate = PS_PRIV | PS_RED | PS_PEF;
  65     if (!cpu_has_hypervisor(env)) {
  66         env->pstate |= PS_AG;
  67     }
  68     env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
  69     env->tl = env->maxtl;
  70     env->gl = 2;
  71     cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
  72     env->lsu = 0;
  73 #else
  74     env->mmuregs[0] &= ~(MMU_E | MMU_NF);
  75     env->mmuregs[0] |= env->def.mmu_bm;
  76 #endif
  77     env->pc = 0;
  78     env->npc = env->pc + 4;
  79 #endif
  80     env->cache_control = 0;
  81 }
  82
  83 #ifndef CONFIG_USER_ONLY
  84 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  85 {
  86     if (interrupt_request & CPU_INTERRUPT_HARD) {
  87         SPARCCPU *cpu = SPARC_CPU(cs);
  88         CPUSPARCState *env = &cpu->env;
  89
  90         if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
  91             int pil = env->interrupt_index & 0xf;
  92             int type = env->interrupt_index & 0xf0;
  93
  94             if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
  95                 cs->exception_index = env->interrupt_index;
  96                 sparc_cpu_do_interrupt(cs);
  97                 return true;
  98             }
  99         }
 100     }
 101     return false;
 102 }
 103 #endif /* !CONFIG_USER_ONLY */
 104
 105 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
 106 {
 107     info->print_insn = print_insn_sparc;
 108 #ifdef TARGET_SPARC64
 109     info->mach = bfd_mach_sparc_v9b;
 110 #endif
 111 }
 112
 113 static void
 114 cpu_add_feat_as_prop(const char *typename, const char *name, const char *val)
 115 {
 116     GlobalProperty *prop = g_new0(typeof(*prop), 1);
 117     prop->driver = typename;
 118     prop->property = g_strdup(name);
 119     prop->value = g_strdup(val);
 120     qdev_prop_register_global(prop);
 121 }
 122
 123 /* Parse "+feature,-feature,feature=foo" CPU feature string */
 124 static void sparc_cpu_parse_features(const char *typename, char *features,
 125                                      Error **errp)
 126 {
 127     GList *l, *plus_features = NULL, *minus_features = NULL;
 128     char *featurestr; /* Single 'key=value" string being parsed */
 129     static bool cpu_globals_initialized;
 130
 131     if (cpu_globals_initialized) {
 132         return;
 133     }
 134     cpu_globals_initialized = true;
 135
 136     if (!features) {
 137         return;
 138     }
 139
 140     for (featurestr = strtok(features, ",");
 141          featurestr;
 142          featurestr = strtok(NULL, ",")) {
 143         const char *name;
 144         const char *val = NULL;
 145         char *eq = NULL;
 146
 147         /* Compatibility syntax: */
 148         if (featurestr[0] == '+') {
 149             plus_features = g_list_append(plus_features,
 150                                           g_strdup(featurestr + 1));
 151             continue;
 152         } else if (featurestr[0] == '-') {
 153             minus_features = g_list_append(minus_features,
 154                                            g_strdup(featurestr + 1));
 155             continue;
 156         }
 157
 158         eq = strchr(featurestr, '=');
 159         name = featurestr;
 160         if (eq) {
 161             *eq++ = 0;
 162             val = eq;
 163
 164             /*
 165              * Temporarily, only +feat/-feat will be supported
 166              * for boolean properties until we remove the
 167              * minus-overrides-plus semantics and just follow
 168              * the order options appear on the command-line.
 169              *
 170              * TODO: warn if user is relying on minus-override-plus semantics
 171              * TODO: remove minus-override-plus semantics after
 172              *       warning for a few releases
 173              */
 174             if (!strcasecmp(val, "on") ||
 175                 !strcasecmp(val, "off") ||
 176                 !strcasecmp(val, "true") ||
 177                 !strcasecmp(val, "false")) {
 178                 error_setg(errp, "Boolean properties in format %s=%s"
 179                                  " are not supported", name, val);
 180                 return;
 181             }
 182         } else {
 183             error_setg(errp, "Unsupported property format: %s", name);
 184             return;
 185         }
 186         cpu_add_feat_as_prop(typename, name, val);
 187     }
 188
 189     for (l = plus_features; l; l = l->next) {
 190         const char *name = l->data;
 191         cpu_add_feat_as_prop(typename, name, "on");
 192     }
 193     g_list_free_full(plus_features, g_free);
 194
 195     for (l = minus_features; l; l = l->next) {
 196         const char *name = l->data;
 197         cpu_add_feat_as_prop(typename, name, "off");
 198     }
 199     g_list_free_full(minus_features, g_free);
 200 }
 201
 202 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
 203 {
 204 #if !defined(TARGET_SPARC64)
 205     env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
 206 #endif
 207 }
 208
 209 static const sparc_def_t sparc_defs[] = {
 210 #ifdef TARGET_SPARC64
 211     {
 212         .name = "Fujitsu Sparc64",
 213         .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
 214         .fpu_version = 0x00000000,
 215         .mmu_version = mmu_us_12,
 216         .nwindows = 4,
 217         .maxtl = 4,
 218         .features = CPU_DEFAULT_FEATURES,
 219     },
 220     {
 221         .name = "Fujitsu Sparc64 III",
 222         .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
 223         .fpu_version = 0x00000000,
 224         .mmu_version = mmu_us_12,
 225         .nwindows = 5,
 226         .maxtl = 4,
 227         .features = CPU_DEFAULT_FEATURES,
 228     },
 229     {
 230         .name = "Fujitsu Sparc64 IV",
 231         .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
 232         .fpu_version = 0x00000000,
 233         .mmu_version = mmu_us_12,
 234         .nwindows = 8,
 235         .maxtl = 5,
 236         .features = CPU_DEFAULT_FEATURES,
 237     },
 238     {
 239         .name = "Fujitsu Sparc64 V",
 240         .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
 241         .fpu_version = 0x00000000,
 242         .mmu_version = mmu_us_12,
 243         .nwindows = 8,
 244         .maxtl = 5,
 245         .features = CPU_DEFAULT_FEATURES,
 246     },
 247     {
 248         .name = "TI UltraSparc I",
 249         .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
 250         .fpu_version = 0x00000000,
 251         .mmu_version = mmu_us_12,
 252         .nwindows = 8,
 253         .maxtl = 5,
 254         .features = CPU_DEFAULT_FEATURES,
 255     },
 256     {
 257         .name = "TI UltraSparc II",
 258         .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
 259         .fpu_version = 0x00000000,
 260         .mmu_version = mmu_us_12,
 261         .nwindows = 8,
 262         .maxtl = 5,
 263         .features = CPU_DEFAULT_FEATURES,
 264     },
 265     {
 266         .name = "TI UltraSparc IIi",
 267         .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
 268         .fpu_version = 0x00000000,
 269         .mmu_version = mmu_us_12,
 270         .nwindows = 8,
 271         .maxtl = 5,
 272         .features = CPU_DEFAULT_FEATURES,
 273     },
 274     {
 275         .name = "TI UltraSparc IIe",
 276         .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
 277         .fpu_version = 0x00000000,
 278         .mmu_version = mmu_us_12,
 279         .nwindows = 8,
 280         .maxtl = 5,
 281         .features = CPU_DEFAULT_FEATURES,
 282     },
 283     {
 284         .name = "Sun UltraSparc III",
 285         .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
 286         .fpu_version = 0x00000000,
 287         .mmu_version = mmu_us_12,
 288         .nwindows = 8,
 289         .maxtl = 5,
 290         .features = CPU_DEFAULT_FEATURES,
 291     },
 292     {
 293         .name = "Sun UltraSparc III Cu",
 294         .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
 295         .fpu_version = 0x00000000,
 296         .mmu_version = mmu_us_3,
 297         .nwindows = 8,
 298         .maxtl = 5,
 299         .features = CPU_DEFAULT_FEATURES,
 300     },
 301     {
 302         .name = "Sun UltraSparc IIIi",
 303         .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
 304         .fpu_version = 0x00000000,
 305         .mmu_version = mmu_us_12,
 306         .nwindows = 8,
 307         .maxtl = 5,
 308         .features = CPU_DEFAULT_FEATURES,
 309     },
 310     {
 311         .name = "Sun UltraSparc IV",
 312         .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
 313         .fpu_version = 0x00000000,
 314         .mmu_version = mmu_us_4,
 315         .nwindows = 8,
 316         .maxtl = 5,
 317         .features = CPU_DEFAULT_FEATURES,
 318     },
 319     {
 320         .name = "Sun UltraSparc IV+",
 321         .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
 322         .fpu_version = 0x00000000,
 323         .mmu_version = mmu_us_12,
 324         .nwindows = 8,
 325         .maxtl = 5,
 326         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
 327     },
 328     {
 329         .name = "Sun UltraSparc IIIi+",
 330         .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
 331         .fpu_version = 0x00000000,
 332         .mmu_version = mmu_us_3,
 333         .nwindows = 8,
 334         .maxtl = 5,
 335         .features = CPU_DEFAULT_FEATURES,
 336     },
 337     {
 338         .name = "Sun UltraSparc T1",
 339         /* defined in sparc_ifu_fdp.v and ctu.h */
 340         .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
 341         .fpu_version = 0x00000000,
 342         .mmu_version = mmu_sun4v,
 343         .nwindows = 8,
 344         .maxtl = 6,
 345         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
 346         | CPU_FEATURE_GL,
 347     },
 348     {
 349         .name = "Sun UltraSparc T2",
 350         /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
 351         .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
 352         .fpu_version = 0x00000000,
 353         .mmu_version = mmu_sun4v,
 354         .nwindows = 8,
 355         .maxtl = 6,
 356         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
 357         | CPU_FEATURE_GL,
 358     },
 359     {
 360         .name = "NEC UltraSparc I",
 361         .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
 362         .fpu_version = 0x00000000,
 363         .mmu_version = mmu_us_12,
 364         .nwindows = 8,
 365         .maxtl = 5,
 366         .features = CPU_DEFAULT_FEATURES,
 367     },
 368 #else
 369     {
 370         .name = "Fujitsu MB86904",
 371         .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
 372         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 373         .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
 374         .mmu_bm = 0x00004000,
 375         .mmu_ctpr_mask = 0x00ffffc0,
 376         .mmu_cxr_mask = 0x000000ff,
 377         .mmu_sfsr_mask = 0x00016fff,
 378         .mmu_trcr_mask = 0x00ffffff,
 379         .nwindows = 8,
 380         .features = CPU_DEFAULT_FEATURES,
 381     },
 382     {
 383         .name = "Fujitsu MB86907",
 384         .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
 385         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 386         .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
 387         .mmu_bm = 0x00004000,
 388         .mmu_ctpr_mask = 0xffffffc0,
 389         .mmu_cxr_mask = 0x000000ff,
 390         .mmu_sfsr_mask = 0x00016fff,
 391         .mmu_trcr_mask = 0xffffffff,
 392         .nwindows = 8,
 393         .features = CPU_DEFAULT_FEATURES,
 394     },
 395     {
 396         .name = "TI MicroSparc I",
 397         .iu_version = 0x41000000,
 398         .fpu_version = 4 << 17,
 399         .mmu_version = 0x41000000,
 400         .mmu_bm = 0x00004000,
 401         .mmu_ctpr_mask = 0x007ffff0,
 402         .mmu_cxr_mask = 0x0000003f,
 403         .mmu_sfsr_mask = 0x00016fff,
 404         .mmu_trcr_mask = 0x0000003f,
 405         .nwindows = 7,
 406         .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
 407         CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
 408         CPU_FEATURE_FMUL,
 409     },
 410     {
 411         .name = "TI MicroSparc II",
 412         .iu_version = 0x42000000,
 413         .fpu_version = 4 << 17,
 414         .mmu_version = 0x02000000,
 415         .mmu_bm = 0x00004000,
 416         .mmu_ctpr_mask = 0x00ffffc0,
 417         .mmu_cxr_mask = 0x000000ff,
 418         .mmu_sfsr_mask = 0x00016fff,
 419         .mmu_trcr_mask = 0x00ffffff,
 420         .nwindows = 8,
 421         .features = CPU_DEFAULT_FEATURES,
 422     },
 423     {
 424         .name = "TI MicroSparc IIep",
 425         .iu_version = 0x42000000,
 426         .fpu_version = 4 << 17,
 427         .mmu_version = 0x04000000,
 428         .mmu_bm = 0x00004000,
 429         .mmu_ctpr_mask = 0x00ffffc0,
 430         .mmu_cxr_mask = 0x000000ff,
 431         .mmu_sfsr_mask = 0x00016bff,
 432         .mmu_trcr_mask = 0x00ffffff,
 433         .nwindows = 8,
 434         .features = CPU_DEFAULT_FEATURES,
 435     },
 436     {
 437         .name = "TI SuperSparc 40", /* STP1020NPGA */
 438         .iu_version = 0x41000000, /* SuperSPARC 2.x */
 439         .fpu_version = 0 << 17,
 440         .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
 441         .mmu_bm = 0x00002000,
 442         .mmu_ctpr_mask = 0xffffffc0,
 443         .mmu_cxr_mask = 0x0000ffff,
 444         .mmu_sfsr_mask = 0xffffffff,
 445         .mmu_trcr_mask = 0xffffffff,
 446         .nwindows = 8,
 447         .features = CPU_DEFAULT_FEATURES,
 448     },
 449     {
 450         .name = "TI SuperSparc 50", /* STP1020PGA */
 451         .iu_version = 0x40000000, /* SuperSPARC 3.x */
 452         .fpu_version = 0 << 17,
 453         .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
 454         .mmu_bm = 0x00002000,
 455         .mmu_ctpr_mask = 0xffffffc0,
 456         .mmu_cxr_mask = 0x0000ffff,
 457         .mmu_sfsr_mask = 0xffffffff,
 458         .mmu_trcr_mask = 0xffffffff,
 459         .nwindows = 8,
 460         .features = CPU_DEFAULT_FEATURES,
 461     },
 462     {
 463         .name = "TI SuperSparc 51",
 464         .iu_version = 0x40000000, /* SuperSPARC 3.x */
 465         .fpu_version = 0 << 17,
 466         .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
 467         .mmu_bm = 0x00002000,
 468         .mmu_ctpr_mask = 0xffffffc0,
 469         .mmu_cxr_mask = 0x0000ffff,
 470         .mmu_sfsr_mask = 0xffffffff,
 471         .mmu_trcr_mask = 0xffffffff,
 472         .mxcc_version = 0x00000104,
 473         .nwindows = 8,
 474         .features = CPU_DEFAULT_FEATURES,
 475     },
 476     {
 477         .name = "TI SuperSparc 60", /* STP1020APGA */
 478         .iu_version = 0x40000000, /* SuperSPARC 3.x */
 479         .fpu_version = 0 << 17,
 480         .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
 481         .mmu_bm = 0x00002000,
 482         .mmu_ctpr_mask = 0xffffffc0,
 483         .mmu_cxr_mask = 0x0000ffff,
 484         .mmu_sfsr_mask = 0xffffffff,
 485         .mmu_trcr_mask = 0xffffffff,
 486         .nwindows = 8,
 487         .features = CPU_DEFAULT_FEATURES,
 488     },
 489     {
 490         .name = "TI SuperSparc 61",
 491         .iu_version = 0x44000000, /* SuperSPARC 3.x */
 492         .fpu_version = 0 << 17,
 493         .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
 494         .mmu_bm = 0x00002000,
 495         .mmu_ctpr_mask = 0xffffffc0,
 496         .mmu_cxr_mask = 0x0000ffff,
 497         .mmu_sfsr_mask = 0xffffffff,
 498         .mmu_trcr_mask = 0xffffffff,
 499         .mxcc_version = 0x00000104,
 500         .nwindows = 8,
 501         .features = CPU_DEFAULT_FEATURES,
 502     },
 503     {
 504         .name = "TI SuperSparc II",
 505         .iu_version = 0x40000000, /* SuperSPARC II 1.x */
 506         .fpu_version = 0 << 17,
 507         .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
 508         .mmu_bm = 0x00002000,
 509         .mmu_ctpr_mask = 0xffffffc0,
 510         .mmu_cxr_mask = 0x0000ffff,
 511         .mmu_sfsr_mask = 0xffffffff,
 512         .mmu_trcr_mask = 0xffffffff,
 513         .mxcc_version = 0x00000104,
 514         .nwindows = 8,
 515         .features = CPU_DEFAULT_FEATURES,
 516     },
 517     {
 518         .name = "LEON2",
 519         .iu_version = 0xf2000000,
 520         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 521         .mmu_version = 0xf2000000,
 522         .mmu_bm = 0x00004000,
 523         .mmu_ctpr_mask = 0x007ffff0,
 524         .mmu_cxr_mask = 0x0000003f,
 525         .mmu_sfsr_mask = 0xffffffff,
 526         .mmu_trcr_mask = 0xffffffff,
 527         .nwindows = 8,
 528         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
 529     },
 530     {
 531         .name = "LEON3",
 532         .iu_version = 0xf3000000,
 533         .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
 534         .mmu_version = 0xf3000000,
 535         .mmu_bm = 0x00000000,
 536         .mmu_ctpr_mask = 0xfffffffc,
 537         .mmu_cxr_mask = 0x000000ff,
 538         .mmu_sfsr_mask = 0xffffffff,
 539         .mmu_trcr_mask = 0xffffffff,
 540         .nwindows = 8,
 541         .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
 542         CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
 543         CPU_FEATURE_CASA,
 544     },
 545 #endif
 546 };
 547
 548 static const char * const feature_name[] = {
 549     "float",
 550     "float128",
 551     "swap",
 552     "mul",
 553     "div",
 554     "flush",
 555     "fsqrt",
 556     "fmul",
 557     "vis1",
 558     "vis2",
 559     "fsmuld",
 560     "hypv",
 561     "cmt",
 562     "gl",
 563 };
 564
 565 static void print_features(uint32_t features, const char *prefix)
 566 {
 567     unsigned int i;
 568
 569     for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
 570         if (feature_name[i] && (features & (1 << i))) {
 571             if (prefix) {
 572                 qemu_printf("%s", prefix);
 573             }
 574             qemu_printf("%s ", feature_name[i]);
 575         }
 576     }
 577 }
 578
 579 void sparc_cpu_list(void)
 580 {
 581     unsigned int i;
 582
 583     for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
 584         qemu_printf("Sparc %16s IU " TARGET_FMT_lx
 585                     " FPU %08x MMU %08x NWINS %d ",
 586                     sparc_defs[i].name,
 587                     sparc_defs[i].iu_version,
 588                     sparc_defs[i].fpu_version,
 589                     sparc_defs[i].mmu_version,
 590                     sparc_defs[i].nwindows);
 591         print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
 592         print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
 593         qemu_printf("\n");
 594     }
 595     qemu_printf("Default CPU feature flags (use '-' to remove): ");
 596     print_features(CPU_DEFAULT_FEATURES, NULL);
 597     qemu_printf("\n");
 598     qemu_printf("Available CPU feature flags (use '+' to add): ");
 599     print_features(~CPU_DEFAULT_FEATURES, NULL);
 600     qemu_printf("\n");
 601     qemu_printf("Numerical features (use '=' to set): iu_version "
 602                 "fpu_version mmu_version nwindows\n");
 603 }
 604
 605 static void cpu_print_cc(FILE *f, uint32_t cc)
 606 {
 607     qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
 608                  cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
 609                  cc & PSR_CARRY ? 'C' : '-');
 610 }
 611
 612 #ifdef TARGET_SPARC64
 613 #define REGS_PER_LINE 4
 614 #else
 615 #define REGS_PER_LINE 8
 616 #endif
 617
 618 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 619 {
 620     SPARCCPU *cpu = SPARC_CPU(cs);
 621     CPUSPARCState *env = &cpu->env;
 622     int i, x;
 623
 624     qemu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc,
 625                  env->npc);
 626
 627     for (i = 0; i < 8; i++) {
 628         if (i % REGS_PER_LINE == 0) {
 629             qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
 630         }
 631         qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
 632         if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
 633             qemu_fprintf(f, "\n");
 634         }
 635     }
 636     for (x = 0; x < 3; x++) {
 637         for (i = 0; i < 8; i++) {
 638             if (i % REGS_PER_LINE == 0) {
 639                 qemu_fprintf(f, "%%%c%d-%d: ",
 640                              x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
 641                              i, i + REGS_PER_LINE - 1);
 642             }
 643             qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
 644             if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
 645                 qemu_fprintf(f, "\n");
 646             }
 647         }
 648     }
 649
 650     if (flags & CPU_DUMP_FPU) {
 651         for (i = 0; i < TARGET_DPREGS; i++) {
 652             if ((i & 3) == 0) {
 653                 qemu_fprintf(f, "%%f%02d: ", i * 2);
 654             }
 655             qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
 656             if ((i & 3) == 3) {
 657                 qemu_fprintf(f, "\n");
 658             }
 659         }
 660     }
 661
 662 #ifdef TARGET_SPARC64
 663     qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
 664                  (unsigned)cpu_get_ccr(env));
 665     cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
 666     qemu_fprintf(f, " xcc: ");
 667     cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
 668     qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl,
 669                  env->psrpil, env->gl);
 670     qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: "
 671                  TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba);
 672     qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
 673                  "cleanwin: %d cwp: %d\n",
 674                  env->cansave, env->canrestore, env->otherwin, env->wstate,
 675                  env->cleanwin, env->nwindows - 1 - env->cwp);
 676     qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n",
 677                  env->fsr, env->y, env->fprs);
 678
 679 #else
 680     qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
 681     cpu_print_cc(f, cpu_get_psr(env));
 682     qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
 683                  env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
 684                  env->wim);
 685     qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
 686                  env->fsr, env->y);
 687 #endif
 688     qemu_fprintf(f, "\n");
 689 }
 690
 691 static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
 692 {
 693     SPARCCPU *cpu = SPARC_CPU(cs);
 694
 695     cpu->env.pc = value;
 696     cpu->env.npc = value + 4;
 697 }
 698
 699 static vaddr sparc_cpu_get_pc(CPUState *cs)
 700 {
 701     SPARCCPU *cpu = SPARC_CPU(cs);
 702
 703     return cpu->env.pc;
 704 }
 705
 706 static void sparc_cpu_synchronize_from_tb(CPUState *cs,
 707                                           const TranslationBlock *tb)
 708 {
 709     SPARCCPU *cpu = SPARC_CPU(cs);
 710
 711     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
 712     cpu->env.pc = tb->pc;
 713     cpu->env.npc = tb->cs_base;
 714 }
 715
 716 static bool sparc_cpu_has_work(CPUState *cs)
 717 {
 718     SPARCCPU *cpu = SPARC_CPU(cs);
 719     CPUSPARCState *env = &cpu->env;
 720
 721     return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 722            cpu_interrupts_enabled(env);
 723 }
 724
 725 static char *sparc_cpu_type_name(const char *cpu_model)
 726 {
 727     char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model);
 728     char *s = name;
 729
 730     /* SPARC cpu model names happen to have whitespaces,
 731      * as type names shouldn't have spaces replace them with '-'
 732      */
 733     while ((s = strchr(s, ' '))) {
 734         *s = '-';
 735     }
 736
 737     return name;
 738 }
 739
 740 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model)
 741 {
 742     ObjectClass *oc;
 743     char *typename;
 744
 745     typename = sparc_cpu_type_name(cpu_model);
 746     oc = object_class_by_name(typename);
 747     g_free(typename);
 748     return oc;
 749 }
 750
 751 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
 752 {
 753     CPUState *cs = CPU(dev);
 754     SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
 755     Error *local_err = NULL;
 756     SPARCCPU *cpu = SPARC_CPU(dev);
 757     CPUSPARCState *env = &cpu->env;
 758
 759 #if defined(CONFIG_USER_ONLY)
 760     if ((env->def.features & CPU_FEATURE_FLOAT)) {
 761         env->def.features |= CPU_FEATURE_FLOAT128;
 762     }
 763 #endif
 764
 765     env->version = env->def.iu_version;
 766     env->fsr = env->def.fpu_version;
 767     env->nwindows = env->def.nwindows;
 768 #if !defined(TARGET_SPARC64)
 769     env->mmuregs[0] |= env->def.mmu_version;
 770     cpu_sparc_set_id(env, 0);
 771     env->mxccregs[7] |= env->def.mxcc_version;
 772 #else
 773     env->mmu_version = env->def.mmu_version;
 774     env->maxtl = env->def.maxtl;
 775     env->version |= env->def.maxtl << 8;
 776     env->version |= env->def.nwindows - 1;
 777 #endif
 778
 779     cpu_exec_realizefn(cs, &local_err);
 780     if (local_err != NULL) {
 781         error_propagate(errp, local_err);
 782         return;
 783     }
 784
 785     qemu_init_vcpu(cs);
 786
 787     scc->parent_realize(dev, errp);
 788 }
 789
 790 static void sparc_cpu_initfn(Object *obj)
 791 {
 792     SPARCCPU *cpu = SPARC_CPU(obj);
 793     SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
 794     CPUSPARCState *env = &cpu->env;
 795
 796     cpu_set_cpustate_pointers(cpu);
 797
 798     if (scc->cpu_def) {
 799         env->def = *scc->cpu_def;
 800     }
 801 }
 802
 803 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name,
 804                                void *opaque, Error **errp)
 805 {
 806     SPARCCPU *cpu = SPARC_CPU(obj);
 807     int64_t value = cpu->env.def.nwindows;
 808
 809     visit_type_int(v, name, &value, errp);
 810 }
 811
 812 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name,
 813                                void *opaque, Error **errp)
 814 {
 815     const int64_t min = MIN_NWINDOWS;
 816     const int64_t max = MAX_NWINDOWS;
 817     SPARCCPU *cpu = SPARC_CPU(obj);
 818     int64_t value;
 819
 820     if (!visit_type_int(v, name, &value, errp)) {
 821         return;
 822     }
 823
 824     if (value < min || value > max) {
 825         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
 826                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
 827                    object_get_typename(obj), name ? name : "null",
 828                    value, min, max);
 829         return;
 830     }
 831     cpu->env.def.nwindows = value;
 832 }
 833
 834 static PropertyInfo qdev_prop_nwindows = {
 835     .name  = "int",
 836     .get   = sparc_get_nwindows,
 837     .set   = sparc_set_nwindows,
 838 };
 839
 840 static Property sparc_cpu_properties[] = {
 841     DEFINE_PROP_BIT("float",    SPARCCPU, env.def.features, 0, false),
 842     DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 1, false),
 843     DEFINE_PROP_BIT("swap",     SPARCCPU, env.def.features, 2, false),
 844     DEFINE_PROP_BIT("mul",      SPARCCPU, env.def.features, 3, false),
 845     DEFINE_PROP_BIT("div",      SPARCCPU, env.def.features, 4, false),
 846     DEFINE_PROP_BIT("flush",    SPARCCPU, env.def.features, 5, false),
 847     DEFINE_PROP_BIT("fsqrt",    SPARCCPU, env.def.features, 6, false),
 848     DEFINE_PROP_BIT("fmul",     SPARCCPU, env.def.features, 7, false),
 849     DEFINE_PROP_BIT("vis1",     SPARCCPU, env.def.features, 8, false),
 850     DEFINE_PROP_BIT("vis2",     SPARCCPU, env.def.features, 9, false),
 851     DEFINE_PROP_BIT("fsmuld",   SPARCCPU, env.def.features, 10, false),
 852     DEFINE_PROP_BIT("hypv",     SPARCCPU, env.def.features, 11, false),
 853     DEFINE_PROP_BIT("cmt",      SPARCCPU, env.def.features, 12, false),
 854     DEFINE_PROP_BIT("gl",       SPARCCPU, env.def.features, 13, false),
 855     DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
 856                          qdev_prop_uint64, target_ulong),
 857     DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
 858     DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
 859     DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows,
 860                 qdev_prop_nwindows, uint32_t),
 861     DEFINE_PROP_END_OF_LIST()
 862 };
 863
 864 #ifndef CONFIG_USER_ONLY
 865 #include "hw/core/sysemu-cpu-ops.h"
 866
 867 static const struct SysemuCPUOps sparc_sysemu_ops = {
 868     .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
 869     .legacy_vmsd = &vmstate_sparc_cpu,
 870 };
 871 #endif
 872
 873 #ifdef CONFIG_TCG
 874 #include "hw/core/tcg-cpu-ops.h"
 875
 876 static const struct TCGCPUOps sparc_tcg_ops = {
 877     .initialize = sparc_tcg_init,
 878     .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
 879     .restore_state_to_opc = sparc_restore_state_to_opc,
 880
 881 #ifndef CONFIG_USER_ONLY
 882     .tlb_fill = sparc_cpu_tlb_fill,
 883     .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
 884     .do_interrupt = sparc_cpu_do_interrupt,
 885     .do_transaction_failed = sparc_cpu_do_transaction_failed,
 886     .do_unaligned_access = sparc_cpu_do_unaligned_access,
 887 #endif /* !CONFIG_USER_ONLY */
 888 };
 889 #endif /* CONFIG_TCG */
 890
 891 static void sparc_cpu_class_init(ObjectClass *oc, void *data)
 892 {
 893     SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
 894     CPUClass *cc = CPU_CLASS(oc);
 895     DeviceClass *dc = DEVICE_CLASS(oc);
 896     ResettableClass *rc = RESETTABLE_CLASS(oc);
 897
 898     device_class_set_parent_realize(dc, sparc_cpu_realizefn,
 899                                     &scc->parent_realize);
 900     device_class_set_props(dc, sparc_cpu_properties);
 901
 902     resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL,
 903                                        &scc->parent_phases);
 904
 905     cc->class_by_name = sparc_cpu_class_by_name;
 906     cc->parse_features = sparc_cpu_parse_features;
 907     cc->has_work = sparc_cpu_has_work;
 908     cc->dump_state = sparc_cpu_dump_state;
 909 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 910     cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
 911 #endif
 912     cc->set_pc = sparc_cpu_set_pc;
 913     cc->get_pc = sparc_cpu_get_pc;
 914     cc->gdb_read_register = sparc_cpu_gdb_read_register;
 915     cc->gdb_write_register = sparc_cpu_gdb_write_register;
 916 #ifndef CONFIG_USER_ONLY
 917     cc->sysemu_ops = &sparc_sysemu_ops;
 918 #endif
 919     cc->disas_set_info = cpu_sparc_disas_set_info;
 920
 921 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
 922     cc->gdb_num_core_regs = 86;
 923 #else
 924     cc->gdb_num_core_regs = 72;
 925 #endif
 926     cc->tcg_ops = &sparc_tcg_ops;
 927 }
 928
 929 static const TypeInfo sparc_cpu_type_info = {
 930     .name = TYPE_SPARC_CPU,
 931     .parent = TYPE_CPU,
 932     .instance_size = sizeof(SPARCCPU),
 933     .instance_init = sparc_cpu_initfn,
 934     .abstract = true,
 935     .class_size = sizeof(SPARCCPUClass),
 936     .class_init = sparc_cpu_class_init,
 937 };
 938
 939 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 940 {
 941     SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
 942     scc->cpu_def = data;
 943 }
 944
 945 static void sparc_register_cpudef_type(const struct sparc_def_t *def)
 946 {
 947     char *typename = sparc_cpu_type_name(def->name);
 948     TypeInfo ti = {
 949         .name = typename,
 950         .parent = TYPE_SPARC_CPU,
 951         .class_init = sparc_cpu_cpudef_class_init,
 952         .class_data = (void *)def,
 953     };
 954
 955     type_register(&ti);
 956     g_free(typename);
 957 }
 958
 959 static void sparc_cpu_register_types(void)
 960 {
 961     int i;
 962
 963     type_register_static(&sparc_cpu_type_info);
 964     for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
 965         sparc_register_cpudef_type(&sparc_defs[i]);
 966     }
 967 }
 968
 969 type_init(sparc_cpu_register_types)