2 * Sparc CPU init helpers
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
23 #include "qemu/module.h"
24 #include "qemu/qemu-print.h"
25 #include "exec/exec-all.h"
26 #include "hw/qdev-properties.h"
27 #include "qapi/visitor.h"
30 //#define DEBUG_FEATURES
32 static void sparc_cpu_reset_hold(Object
*obj
)
34 CPUState
*s
= CPU(obj
);
35 SPARCCPU
*cpu
= SPARC_CPU(s
);
36 SPARCCPUClass
*scc
= SPARC_CPU_GET_CLASS(cpu
);
37 CPUSPARCState
*env
= &cpu
->env
;
39 if (scc
->parent_phases
.hold
) {
40 scc
->parent_phases
.hold(obj
);
43 memset(env
, 0, offsetof(CPUSPARCState
, end_reset_fields
));
45 #ifndef TARGET_SPARC64
48 env
->regwptr
= env
->regbase
+ (env
->cwp
* 16);
49 #if defined(CONFIG_USER_ONLY)
51 env
->cleanwin
= env
->nwindows
- 2;
52 env
->cansave
= env
->nwindows
- 2;
53 env
->pstate
= PS_RMO
| PS_PEF
| PS_IE
;
54 env
->asi
= 0x82; /* Primary no-fault */
57 #if !defined(TARGET_SPARC64)
63 env
->pstate
= PS_PRIV
| PS_RED
| PS_PEF
;
64 if (!cpu_has_hypervisor(env
)) {
67 env
->hpstate
= cpu_has_hypervisor(env
) ? HS_PRIV
: 0;
70 cpu_tsptr(env
)->tt
= TT_POWER_ON_RESET
;
73 env
->mmuregs
[0] &= ~(MMU_E
| MMU_NF
);
74 env
->mmuregs
[0] |= env
->def
.mmu_bm
;
77 env
->npc
= env
->pc
+ 4;
79 env
->cache_control
= 0;
82 #ifndef CONFIG_USER_ONLY
83 static bool sparc_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
85 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
86 SPARCCPU
*cpu
= SPARC_CPU(cs
);
87 CPUSPARCState
*env
= &cpu
->env
;
89 if (cpu_interrupts_enabled(env
) && env
->interrupt_index
> 0) {
90 int pil
= env
->interrupt_index
& 0xf;
91 int type
= env
->interrupt_index
& 0xf0;
93 if (type
!= TT_EXTINT
|| cpu_pil_allowed(env
, pil
)) {
94 cs
->exception_index
= env
->interrupt_index
;
95 sparc_cpu_do_interrupt(cs
);
102 #endif /* !CONFIG_USER_ONLY */
104 static void cpu_sparc_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
106 info
->print_insn
= print_insn_sparc
;
107 #ifdef TARGET_SPARC64
108 info
->mach
= bfd_mach_sparc_v9b
;
113 cpu_add_feat_as_prop(const char *typename
, const char *name
, const char *val
)
115 GlobalProperty
*prop
= g_new0(typeof(*prop
), 1);
116 prop
->driver
= typename
;
117 prop
->property
= g_strdup(name
);
118 prop
->value
= g_strdup(val
);
119 qdev_prop_register_global(prop
);
122 /* Parse "+feature,-feature,feature=foo" CPU feature string */
123 static void sparc_cpu_parse_features(const char *typename
, char *features
,
126 GList
*l
, *plus_features
= NULL
, *minus_features
= NULL
;
127 char *featurestr
; /* Single 'key=value" string being parsed */
128 static bool cpu_globals_initialized
;
130 if (cpu_globals_initialized
) {
133 cpu_globals_initialized
= true;
139 for (featurestr
= strtok(features
, ",");
141 featurestr
= strtok(NULL
, ",")) {
143 const char *val
= NULL
;
146 /* Compatibility syntax: */
147 if (featurestr
[0] == '+') {
148 plus_features
= g_list_append(plus_features
,
149 g_strdup(featurestr
+ 1));
151 } else if (featurestr
[0] == '-') {
152 minus_features
= g_list_append(minus_features
,
153 g_strdup(featurestr
+ 1));
157 eq
= strchr(featurestr
, '=');
164 * Temporarily, only +feat/-feat will be supported
165 * for boolean properties until we remove the
166 * minus-overrides-plus semantics and just follow
167 * the order options appear on the command-line.
169 * TODO: warn if user is relying on minus-override-plus semantics
170 * TODO: remove minus-override-plus semantics after
171 * warning for a few releases
173 if (!strcasecmp(val
, "on") ||
174 !strcasecmp(val
, "off") ||
175 !strcasecmp(val
, "true") ||
176 !strcasecmp(val
, "false")) {
177 error_setg(errp
, "Boolean properties in format %s=%s"
178 " are not supported", name
, val
);
182 error_setg(errp
, "Unsupported property format: %s", name
);
185 cpu_add_feat_as_prop(typename
, name
, val
);
188 for (l
= plus_features
; l
; l
= l
->next
) {
189 const char *name
= l
->data
;
190 cpu_add_feat_as_prop(typename
, name
, "on");
192 g_list_free_full(plus_features
, g_free
);
194 for (l
= minus_features
; l
; l
= l
->next
) {
195 const char *name
= l
->data
;
196 cpu_add_feat_as_prop(typename
, name
, "off");
198 g_list_free_full(minus_features
, g_free
);
201 void cpu_sparc_set_id(CPUSPARCState
*env
, unsigned int cpu
)
203 #if !defined(TARGET_SPARC64)
204 env
->mxccregs
[7] = ((cpu
+ 8) & 0xf) << 24;
208 static const sparc_def_t sparc_defs
[] = {
209 #ifdef TARGET_SPARC64
211 .name
= "Fujitsu Sparc64",
212 .iu_version
= ((0x04ULL
<< 48) | (0x02ULL
<< 32) | (0ULL << 24)),
213 .fpu_version
= 0x00000000,
214 .mmu_version
= mmu_us_12
,
217 .features
= CPU_DEFAULT_FEATURES
,
220 .name
= "Fujitsu Sparc64 III",
221 .iu_version
= ((0x04ULL
<< 48) | (0x03ULL
<< 32) | (0ULL << 24)),
222 .fpu_version
= 0x00000000,
223 .mmu_version
= mmu_us_12
,
226 .features
= CPU_DEFAULT_FEATURES
,
229 .name
= "Fujitsu Sparc64 IV",
230 .iu_version
= ((0x04ULL
<< 48) | (0x04ULL
<< 32) | (0ULL << 24)),
231 .fpu_version
= 0x00000000,
232 .mmu_version
= mmu_us_12
,
235 .features
= CPU_DEFAULT_FEATURES
,
238 .name
= "Fujitsu Sparc64 V",
239 .iu_version
= ((0x04ULL
<< 48) | (0x05ULL
<< 32) | (0x51ULL
<< 24)),
240 .fpu_version
= 0x00000000,
241 .mmu_version
= mmu_us_12
,
244 .features
= CPU_DEFAULT_FEATURES
,
247 .name
= "TI UltraSparc I",
248 .iu_version
= ((0x17ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)),
249 .fpu_version
= 0x00000000,
250 .mmu_version
= mmu_us_12
,
253 .features
= CPU_DEFAULT_FEATURES
,
256 .name
= "TI UltraSparc II",
257 .iu_version
= ((0x17ULL
<< 48) | (0x11ULL
<< 32) | (0x20ULL
<< 24)),
258 .fpu_version
= 0x00000000,
259 .mmu_version
= mmu_us_12
,
262 .features
= CPU_DEFAULT_FEATURES
,
265 .name
= "TI UltraSparc IIi",
266 .iu_version
= ((0x17ULL
<< 48) | (0x12ULL
<< 32) | (0x91ULL
<< 24)),
267 .fpu_version
= 0x00000000,
268 .mmu_version
= mmu_us_12
,
271 .features
= CPU_DEFAULT_FEATURES
,
274 .name
= "TI UltraSparc IIe",
275 .iu_version
= ((0x17ULL
<< 48) | (0x13ULL
<< 32) | (0x14ULL
<< 24)),
276 .fpu_version
= 0x00000000,
277 .mmu_version
= mmu_us_12
,
280 .features
= CPU_DEFAULT_FEATURES
,
283 .name
= "Sun UltraSparc III",
284 .iu_version
= ((0x3eULL
<< 48) | (0x14ULL
<< 32) | (0x34ULL
<< 24)),
285 .fpu_version
= 0x00000000,
286 .mmu_version
= mmu_us_12
,
289 .features
= CPU_DEFAULT_FEATURES
,
292 .name
= "Sun UltraSparc III Cu",
293 .iu_version
= ((0x3eULL
<< 48) | (0x15ULL
<< 32) | (0x41ULL
<< 24)),
294 .fpu_version
= 0x00000000,
295 .mmu_version
= mmu_us_3
,
298 .features
= CPU_DEFAULT_FEATURES
,
301 .name
= "Sun UltraSparc IIIi",
302 .iu_version
= ((0x3eULL
<< 48) | (0x16ULL
<< 32) | (0x34ULL
<< 24)),
303 .fpu_version
= 0x00000000,
304 .mmu_version
= mmu_us_12
,
307 .features
= CPU_DEFAULT_FEATURES
,
310 .name
= "Sun UltraSparc IV",
311 .iu_version
= ((0x3eULL
<< 48) | (0x18ULL
<< 32) | (0x31ULL
<< 24)),
312 .fpu_version
= 0x00000000,
313 .mmu_version
= mmu_us_4
,
316 .features
= CPU_DEFAULT_FEATURES
,
319 .name
= "Sun UltraSparc IV+",
320 .iu_version
= ((0x3eULL
<< 48) | (0x19ULL
<< 32) | (0x22ULL
<< 24)),
321 .fpu_version
= 0x00000000,
322 .mmu_version
= mmu_us_12
,
325 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_CMT
,
328 .name
= "Sun UltraSparc IIIi+",
329 .iu_version
= ((0x3eULL
<< 48) | (0x22ULL
<< 32) | (0ULL << 24)),
330 .fpu_version
= 0x00000000,
331 .mmu_version
= mmu_us_3
,
334 .features
= CPU_DEFAULT_FEATURES
,
337 .name
= "Sun UltraSparc T1",
338 /* defined in sparc_ifu_fdp.v and ctu.h */
339 .iu_version
= ((0x3eULL
<< 48) | (0x23ULL
<< 32) | (0x02ULL
<< 24)),
340 .fpu_version
= 0x00000000,
341 .mmu_version
= mmu_sun4v
,
344 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_HYPV
| CPU_FEATURE_CMT
348 .name
= "Sun UltraSparc T2",
349 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
350 .iu_version
= ((0x3eULL
<< 48) | (0x24ULL
<< 32) | (0x02ULL
<< 24)),
351 .fpu_version
= 0x00000000,
352 .mmu_version
= mmu_sun4v
,
355 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_HYPV
| CPU_FEATURE_CMT
359 .name
= "NEC UltraSparc I",
360 .iu_version
= ((0x22ULL
<< 48) | (0x10ULL
<< 32) | (0x40ULL
<< 24)),
361 .fpu_version
= 0x00000000,
362 .mmu_version
= mmu_us_12
,
365 .features
= CPU_DEFAULT_FEATURES
,
369 .name
= "Fujitsu MB86904",
370 .iu_version
= 0x04 << 24, /* Impl 0, ver 4 */
371 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
372 .mmu_version
= 0x04 << 24, /* Impl 0, ver 4 */
373 .mmu_bm
= 0x00004000,
374 .mmu_ctpr_mask
= 0x00ffffc0,
375 .mmu_cxr_mask
= 0x000000ff,
376 .mmu_sfsr_mask
= 0x00016fff,
377 .mmu_trcr_mask
= 0x00ffffff,
379 .features
= CPU_DEFAULT_FEATURES
,
382 .name
= "Fujitsu MB86907",
383 .iu_version
= 0x05 << 24, /* Impl 0, ver 5 */
384 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
385 .mmu_version
= 0x05 << 24, /* Impl 0, ver 5 */
386 .mmu_bm
= 0x00004000,
387 .mmu_ctpr_mask
= 0xffffffc0,
388 .mmu_cxr_mask
= 0x000000ff,
389 .mmu_sfsr_mask
= 0x00016fff,
390 .mmu_trcr_mask
= 0xffffffff,
392 .features
= CPU_DEFAULT_FEATURES
,
395 .name
= "TI MicroSparc I",
396 .iu_version
= 0x41000000,
397 .fpu_version
= 4 << 17,
398 .mmu_version
= 0x41000000,
399 .mmu_bm
= 0x00004000,
400 .mmu_ctpr_mask
= 0x007ffff0,
401 .mmu_cxr_mask
= 0x0000003f,
402 .mmu_sfsr_mask
= 0x00016fff,
403 .mmu_trcr_mask
= 0x0000003f,
405 .features
= CPU_FEATURE_MUL
| CPU_FEATURE_DIV
,
408 .name
= "TI MicroSparc II",
409 .iu_version
= 0x42000000,
410 .fpu_version
= 4 << 17,
411 .mmu_version
= 0x02000000,
412 .mmu_bm
= 0x00004000,
413 .mmu_ctpr_mask
= 0x00ffffc0,
414 .mmu_cxr_mask
= 0x000000ff,
415 .mmu_sfsr_mask
= 0x00016fff,
416 .mmu_trcr_mask
= 0x00ffffff,
418 .features
= CPU_DEFAULT_FEATURES
,
421 .name
= "TI MicroSparc IIep",
422 .iu_version
= 0x42000000,
423 .fpu_version
= 4 << 17,
424 .mmu_version
= 0x04000000,
425 .mmu_bm
= 0x00004000,
426 .mmu_ctpr_mask
= 0x00ffffc0,
427 .mmu_cxr_mask
= 0x000000ff,
428 .mmu_sfsr_mask
= 0x00016bff,
429 .mmu_trcr_mask
= 0x00ffffff,
431 .features
= CPU_DEFAULT_FEATURES
,
434 .name
= "TI SuperSparc 40", /* STP1020NPGA */
435 .iu_version
= 0x41000000, /* SuperSPARC 2.x */
436 .fpu_version
= 0 << 17,
437 .mmu_version
= 0x00000800, /* SuperSPARC 2.x, no MXCC */
438 .mmu_bm
= 0x00002000,
439 .mmu_ctpr_mask
= 0xffffffc0,
440 .mmu_cxr_mask
= 0x0000ffff,
441 .mmu_sfsr_mask
= 0xffffffff,
442 .mmu_trcr_mask
= 0xffffffff,
444 .features
= CPU_DEFAULT_FEATURES
,
447 .name
= "TI SuperSparc 50", /* STP1020PGA */
448 .iu_version
= 0x40000000, /* SuperSPARC 3.x */
449 .fpu_version
= 0 << 17,
450 .mmu_version
= 0x01000800, /* SuperSPARC 3.x, no MXCC */
451 .mmu_bm
= 0x00002000,
452 .mmu_ctpr_mask
= 0xffffffc0,
453 .mmu_cxr_mask
= 0x0000ffff,
454 .mmu_sfsr_mask
= 0xffffffff,
455 .mmu_trcr_mask
= 0xffffffff,
457 .features
= CPU_DEFAULT_FEATURES
,
460 .name
= "TI SuperSparc 51",
461 .iu_version
= 0x40000000, /* SuperSPARC 3.x */
462 .fpu_version
= 0 << 17,
463 .mmu_version
= 0x01000000, /* SuperSPARC 3.x, MXCC */
464 .mmu_bm
= 0x00002000,
465 .mmu_ctpr_mask
= 0xffffffc0,
466 .mmu_cxr_mask
= 0x0000ffff,
467 .mmu_sfsr_mask
= 0xffffffff,
468 .mmu_trcr_mask
= 0xffffffff,
469 .mxcc_version
= 0x00000104,
471 .features
= CPU_DEFAULT_FEATURES
,
474 .name
= "TI SuperSparc 60", /* STP1020APGA */
475 .iu_version
= 0x40000000, /* SuperSPARC 3.x */
476 .fpu_version
= 0 << 17,
477 .mmu_version
= 0x01000800, /* SuperSPARC 3.x, no MXCC */
478 .mmu_bm
= 0x00002000,
479 .mmu_ctpr_mask
= 0xffffffc0,
480 .mmu_cxr_mask
= 0x0000ffff,
481 .mmu_sfsr_mask
= 0xffffffff,
482 .mmu_trcr_mask
= 0xffffffff,
484 .features
= CPU_DEFAULT_FEATURES
,
487 .name
= "TI SuperSparc 61",
488 .iu_version
= 0x44000000, /* SuperSPARC 3.x */
489 .fpu_version
= 0 << 17,
490 .mmu_version
= 0x01000000, /* SuperSPARC 3.x, MXCC */
491 .mmu_bm
= 0x00002000,
492 .mmu_ctpr_mask
= 0xffffffc0,
493 .mmu_cxr_mask
= 0x0000ffff,
494 .mmu_sfsr_mask
= 0xffffffff,
495 .mmu_trcr_mask
= 0xffffffff,
496 .mxcc_version
= 0x00000104,
498 .features
= CPU_DEFAULT_FEATURES
,
501 .name
= "TI SuperSparc II",
502 .iu_version
= 0x40000000, /* SuperSPARC II 1.x */
503 .fpu_version
= 0 << 17,
504 .mmu_version
= 0x08000000, /* SuperSPARC II 1.x, MXCC */
505 .mmu_bm
= 0x00002000,
506 .mmu_ctpr_mask
= 0xffffffc0,
507 .mmu_cxr_mask
= 0x0000ffff,
508 .mmu_sfsr_mask
= 0xffffffff,
509 .mmu_trcr_mask
= 0xffffffff,
510 .mxcc_version
= 0x00000104,
512 .features
= CPU_DEFAULT_FEATURES
,
516 .iu_version
= 0xf2000000,
517 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
518 .mmu_version
= 0xf2000000,
519 .mmu_bm
= 0x00004000,
520 .mmu_ctpr_mask
= 0x007ffff0,
521 .mmu_cxr_mask
= 0x0000003f,
522 .mmu_sfsr_mask
= 0xffffffff,
523 .mmu_trcr_mask
= 0xffffffff,
525 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_TA0_SHUTDOWN
,
529 .iu_version
= 0xf3000000,
530 .fpu_version
= 4 << 17, /* FPU version 4 (Meiko) */
531 .mmu_version
= 0xf3000000,
532 .mmu_bm
= 0x00000000,
533 .mmu_ctpr_mask
= 0xfffffffc,
534 .mmu_cxr_mask
= 0x000000ff,
535 .mmu_sfsr_mask
= 0xffffffff,
536 .mmu_trcr_mask
= 0xffffffff,
538 .features
= CPU_DEFAULT_FEATURES
| CPU_FEATURE_TA0_SHUTDOWN
|
539 CPU_FEATURE_ASR17
| CPU_FEATURE_CACHE_CTRL
| CPU_FEATURE_POWERDOWN
|
545 /* This must match sparc_cpu_properties[]. */
546 static const char * const feature_name
[] = {
547 [CPU_FEATURE_BIT_FLOAT128
] = "float128",
548 #ifdef TARGET_SPARC64
549 [CPU_FEATURE_BIT_CMT
] = "cmt",
550 [CPU_FEATURE_BIT_GL
] = "gl",
551 [CPU_FEATURE_BIT_HYPV
] = "hypv",
552 [CPU_FEATURE_BIT_VIS1
] = "vis1",
553 [CPU_FEATURE_BIT_VIS2
] = "vis2",
555 [CPU_FEATURE_BIT_MUL
] = "mul",
556 [CPU_FEATURE_BIT_DIV
] = "div",
557 [CPU_FEATURE_BIT_FSMULD
] = "fsmuld",
561 static void print_features(uint32_t features
, const char *prefix
)
565 for (i
= 0; i
< ARRAY_SIZE(feature_name
); i
++) {
566 if (feature_name
[i
] && (features
& (1 << i
))) {
568 qemu_printf("%s", prefix
);
570 qemu_printf("%s ", feature_name
[i
]);
575 void sparc_cpu_list(void)
579 for (i
= 0; i
< ARRAY_SIZE(sparc_defs
); i
++) {
580 qemu_printf("Sparc %16s IU " TARGET_FMT_lx
581 " FPU %08x MMU %08x NWINS %d ",
583 sparc_defs
[i
].iu_version
,
584 sparc_defs
[i
].fpu_version
,
585 sparc_defs
[i
].mmu_version
,
586 sparc_defs
[i
].nwindows
);
587 print_features(CPU_DEFAULT_FEATURES
& ~sparc_defs
[i
].features
, "-");
588 print_features(~CPU_DEFAULT_FEATURES
& sparc_defs
[i
].features
, "+");
591 qemu_printf("Default CPU feature flags (use '-' to remove): ");
592 print_features(CPU_DEFAULT_FEATURES
, NULL
);
594 qemu_printf("Available CPU feature flags (use '+' to add): ");
595 print_features(~CPU_DEFAULT_FEATURES
, NULL
);
597 qemu_printf("Numerical features (use '=' to set): iu_version "
598 "fpu_version mmu_version nwindows\n");
601 static void cpu_print_cc(FILE *f
, uint32_t cc
)
603 qemu_fprintf(f
, "%c%c%c%c", cc
& PSR_NEG
? 'N' : '-',
604 cc
& PSR_ZERO
? 'Z' : '-', cc
& PSR_OVF
? 'V' : '-',
605 cc
& PSR_CARRY
? 'C' : '-');
608 #ifdef TARGET_SPARC64
609 #define REGS_PER_LINE 4
611 #define REGS_PER_LINE 8
614 static void sparc_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
616 SPARCCPU
*cpu
= SPARC_CPU(cs
);
617 CPUSPARCState
*env
= &cpu
->env
;
620 qemu_fprintf(f
, "pc: " TARGET_FMT_lx
" npc: " TARGET_FMT_lx
"\n", env
->pc
,
623 for (i
= 0; i
< 8; i
++) {
624 if (i
% REGS_PER_LINE
== 0) {
625 qemu_fprintf(f
, "%%g%d-%d:", i
, i
+ REGS_PER_LINE
- 1);
627 qemu_fprintf(f
, " " TARGET_FMT_lx
, env
->gregs
[i
]);
628 if (i
% REGS_PER_LINE
== REGS_PER_LINE
- 1) {
629 qemu_fprintf(f
, "\n");
632 for (x
= 0; x
< 3; x
++) {
633 for (i
= 0; i
< 8; i
++) {
634 if (i
% REGS_PER_LINE
== 0) {
635 qemu_fprintf(f
, "%%%c%d-%d: ",
636 x
== 0 ? 'o' : (x
== 1 ? 'l' : 'i'),
637 i
, i
+ REGS_PER_LINE
- 1);
639 qemu_fprintf(f
, TARGET_FMT_lx
" ", env
->regwptr
[i
+ x
* 8]);
640 if (i
% REGS_PER_LINE
== REGS_PER_LINE
- 1) {
641 qemu_fprintf(f
, "\n");
646 if (flags
& CPU_DUMP_FPU
) {
647 for (i
= 0; i
< TARGET_DPREGS
; i
++) {
649 qemu_fprintf(f
, "%%f%02d: ", i
* 2);
651 qemu_fprintf(f
, " %016" PRIx64
, env
->fpr
[i
].ll
);
653 qemu_fprintf(f
, "\n");
658 #ifdef TARGET_SPARC64
659 qemu_fprintf(f
, "pstate: %08x ccr: %02x (icc: ", env
->pstate
,
660 (unsigned)cpu_get_ccr(env
));
661 cpu_print_cc(f
, cpu_get_ccr(env
) << PSR_CARRY_SHIFT
);
662 qemu_fprintf(f
, " xcc: ");
663 cpu_print_cc(f
, cpu_get_ccr(env
) << (PSR_CARRY_SHIFT
- 4));
664 qemu_fprintf(f
, ") asi: %02x tl: %d pil: %x gl: %d\n", env
->asi
, env
->tl
,
665 env
->psrpil
, env
->gl
);
666 qemu_fprintf(f
, "tbr: " TARGET_FMT_lx
" hpstate: " TARGET_FMT_lx
" htba: "
667 TARGET_FMT_lx
"\n", env
->tbr
, env
->hpstate
, env
->htba
);
668 qemu_fprintf(f
, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
669 "cleanwin: %d cwp: %d\n",
670 env
->cansave
, env
->canrestore
, env
->otherwin
, env
->wstate
,
671 env
->cleanwin
, env
->nwindows
- 1 - env
->cwp
);
672 qemu_fprintf(f
, "fsr: " TARGET_FMT_lx
" y: " TARGET_FMT_lx
" fprs: %016x\n",
673 env
->fsr
, env
->y
, env
->fprs
);
676 qemu_fprintf(f
, "psr: %08x (icc: ", cpu_get_psr(env
));
677 cpu_print_cc(f
, cpu_get_psr(env
));
678 qemu_fprintf(f
, " SPE: %c%c%c) wim: %08x\n", env
->psrs
? 'S' : '-',
679 env
->psrps
? 'P' : '-', env
->psret
? 'E' : '-',
681 qemu_fprintf(f
, "fsr: " TARGET_FMT_lx
" y: " TARGET_FMT_lx
"\n",
684 qemu_fprintf(f
, "\n");
687 static void sparc_cpu_set_pc(CPUState
*cs
, vaddr value
)
689 SPARCCPU
*cpu
= SPARC_CPU(cs
);
692 cpu
->env
.npc
= value
+ 4;
695 static vaddr
sparc_cpu_get_pc(CPUState
*cs
)
697 SPARCCPU
*cpu
= SPARC_CPU(cs
);
702 static void sparc_cpu_synchronize_from_tb(CPUState
*cs
,
703 const TranslationBlock
*tb
)
705 SPARCCPU
*cpu
= SPARC_CPU(cs
);
707 tcg_debug_assert(!(cs
->tcg_cflags
& CF_PCREL
));
708 cpu
->env
.pc
= tb
->pc
;
709 cpu
->env
.npc
= tb
->cs_base
;
712 static bool sparc_cpu_has_work(CPUState
*cs
)
714 SPARCCPU
*cpu
= SPARC_CPU(cs
);
715 CPUSPARCState
*env
= &cpu
->env
;
717 return (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
718 cpu_interrupts_enabled(env
);
721 static char *sparc_cpu_type_name(const char *cpu_model
)
723 char *name
= g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model
);
726 /* SPARC cpu model names happen to have whitespaces,
727 * as type names shouldn't have spaces replace them with '-'
729 while ((s
= strchr(s
, ' '))) {
736 static ObjectClass
*sparc_cpu_class_by_name(const char *cpu_model
)
741 typename
= sparc_cpu_type_name(cpu_model
);
742 oc
= object_class_by_name(typename
);
747 static void sparc_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
749 CPUState
*cs
= CPU(dev
);
750 SPARCCPUClass
*scc
= SPARC_CPU_GET_CLASS(dev
);
751 Error
*local_err
= NULL
;
752 SPARCCPU
*cpu
= SPARC_CPU(dev
);
753 CPUSPARCState
*env
= &cpu
->env
;
755 #if defined(CONFIG_USER_ONLY)
756 /* We are emulating the kernel, which will trap and emulate float128. */
757 env
->def
.features
|= CPU_FEATURE_FLOAT128
;
760 env
->version
= env
->def
.iu_version
;
761 env
->fsr
= env
->def
.fpu_version
;
762 env
->nwindows
= env
->def
.nwindows
;
763 #if !defined(TARGET_SPARC64)
764 env
->mmuregs
[0] |= env
->def
.mmu_version
;
765 cpu_sparc_set_id(env
, 0);
766 env
->mxccregs
[7] |= env
->def
.mxcc_version
;
768 env
->mmu_version
= env
->def
.mmu_version
;
769 env
->maxtl
= env
->def
.maxtl
;
770 env
->version
|= env
->def
.maxtl
<< 8;
771 env
->version
|= env
->def
.nwindows
- 1;
774 cpu_exec_realizefn(cs
, &local_err
);
775 if (local_err
!= NULL
) {
776 error_propagate(errp
, local_err
);
782 scc
->parent_realize(dev
, errp
);
785 static void sparc_cpu_initfn(Object
*obj
)
787 SPARCCPU
*cpu
= SPARC_CPU(obj
);
788 SPARCCPUClass
*scc
= SPARC_CPU_GET_CLASS(obj
);
789 CPUSPARCState
*env
= &cpu
->env
;
792 env
->def
= *scc
->cpu_def
;
796 static void sparc_get_nwindows(Object
*obj
, Visitor
*v
, const char *name
,
797 void *opaque
, Error
**errp
)
799 SPARCCPU
*cpu
= SPARC_CPU(obj
);
800 int64_t value
= cpu
->env
.def
.nwindows
;
802 visit_type_int(v
, name
, &value
, errp
);
805 static void sparc_set_nwindows(Object
*obj
, Visitor
*v
, const char *name
,
806 void *opaque
, Error
**errp
)
808 const int64_t min
= MIN_NWINDOWS
;
809 const int64_t max
= MAX_NWINDOWS
;
810 SPARCCPU
*cpu
= SPARC_CPU(obj
);
813 if (!visit_type_int(v
, name
, &value
, errp
)) {
817 if (value
< min
|| value
> max
) {
818 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
819 " (minimum: %" PRId64
", maximum: %" PRId64
")",
820 object_get_typename(obj
), name
? name
: "null",
824 cpu
->env
.def
.nwindows
= value
;
827 static PropertyInfo qdev_prop_nwindows
= {
829 .get
= sparc_get_nwindows
,
830 .set
= sparc_set_nwindows
,
833 /* This must match feature_name[]. */
834 static Property sparc_cpu_properties
[] = {
835 DEFINE_PROP_BIT("float128", SPARCCPU
, env
.def
.features
,
836 CPU_FEATURE_BIT_FLOAT128
, false),
837 #ifdef TARGET_SPARC64
838 DEFINE_PROP_BIT("cmt", SPARCCPU
, env
.def
.features
,
839 CPU_FEATURE_BIT_CMT
, false),
840 DEFINE_PROP_BIT("gl", SPARCCPU
, env
.def
.features
,
841 CPU_FEATURE_BIT_GL
, false),
842 DEFINE_PROP_BIT("hypv", SPARCCPU
, env
.def
.features
,
843 CPU_FEATURE_BIT_HYPV
, false),
844 DEFINE_PROP_BIT("vis1", SPARCCPU
, env
.def
.features
,
845 CPU_FEATURE_BIT_VIS1
, false),
846 DEFINE_PROP_BIT("vis2", SPARCCPU
, env
.def
.features
,
847 CPU_FEATURE_BIT_VIS2
, false),
849 DEFINE_PROP_BIT("mul", SPARCCPU
, env
.def
.features
,
850 CPU_FEATURE_BIT_MUL
, false),
851 DEFINE_PROP_BIT("div", SPARCCPU
, env
.def
.features
,
852 CPU_FEATURE_BIT_DIV
, false),
853 DEFINE_PROP_BIT("fsmuld", SPARCCPU
, env
.def
.features
,
854 CPU_FEATURE_BIT_FSMULD
, false),
856 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU
, env
.def
.iu_version
, 0,
857 qdev_prop_uint64
, target_ulong
),
858 DEFINE_PROP_UINT32("fpu-version", SPARCCPU
, env
.def
.fpu_version
, 0),
859 DEFINE_PROP_UINT32("mmu-version", SPARCCPU
, env
.def
.mmu_version
, 0),
860 DEFINE_PROP("nwindows", SPARCCPU
, env
.def
.nwindows
,
861 qdev_prop_nwindows
, uint32_t),
862 DEFINE_PROP_END_OF_LIST()
865 #ifndef CONFIG_USER_ONLY
866 #include "hw/core/sysemu-cpu-ops.h"
868 static const struct SysemuCPUOps sparc_sysemu_ops
= {
869 .get_phys_page_debug
= sparc_cpu_get_phys_page_debug
,
870 .legacy_vmsd
= &vmstate_sparc_cpu
,
875 #include "hw/core/tcg-cpu-ops.h"
877 static const TCGCPUOps sparc_tcg_ops
= {
878 .initialize
= sparc_tcg_init
,
879 .synchronize_from_tb
= sparc_cpu_synchronize_from_tb
,
880 .restore_state_to_opc
= sparc_restore_state_to_opc
,
882 #ifndef CONFIG_USER_ONLY
883 .tlb_fill
= sparc_cpu_tlb_fill
,
884 .cpu_exec_interrupt
= sparc_cpu_exec_interrupt
,
885 .do_interrupt
= sparc_cpu_do_interrupt
,
886 .do_transaction_failed
= sparc_cpu_do_transaction_failed
,
887 .do_unaligned_access
= sparc_cpu_do_unaligned_access
,
888 #endif /* !CONFIG_USER_ONLY */
890 #endif /* CONFIG_TCG */
892 static void sparc_cpu_class_init(ObjectClass
*oc
, void *data
)
894 SPARCCPUClass
*scc
= SPARC_CPU_CLASS(oc
);
895 CPUClass
*cc
= CPU_CLASS(oc
);
896 DeviceClass
*dc
= DEVICE_CLASS(oc
);
897 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
899 device_class_set_parent_realize(dc
, sparc_cpu_realizefn
,
900 &scc
->parent_realize
);
901 device_class_set_props(dc
, sparc_cpu_properties
);
903 resettable_class_set_parent_phases(rc
, NULL
, sparc_cpu_reset_hold
, NULL
,
904 &scc
->parent_phases
);
906 cc
->class_by_name
= sparc_cpu_class_by_name
;
907 cc
->parse_features
= sparc_cpu_parse_features
;
908 cc
->has_work
= sparc_cpu_has_work
;
909 cc
->dump_state
= sparc_cpu_dump_state
;
910 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
911 cc
->memory_rw_debug
= sparc_cpu_memory_rw_debug
;
913 cc
->set_pc
= sparc_cpu_set_pc
;
914 cc
->get_pc
= sparc_cpu_get_pc
;
915 cc
->gdb_read_register
= sparc_cpu_gdb_read_register
;
916 cc
->gdb_write_register
= sparc_cpu_gdb_write_register
;
917 #ifndef CONFIG_USER_ONLY
918 cc
->sysemu_ops
= &sparc_sysemu_ops
;
920 cc
->disas_set_info
= cpu_sparc_disas_set_info
;
922 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
923 cc
->gdb_num_core_regs
= 86;
925 cc
->gdb_num_core_regs
= 72;
927 cc
->tcg_ops
= &sparc_tcg_ops
;
930 static const TypeInfo sparc_cpu_type_info
= {
931 .name
= TYPE_SPARC_CPU
,
933 .instance_size
= sizeof(SPARCCPU
),
934 .instance_align
= __alignof(SPARCCPU
),
935 .instance_init
= sparc_cpu_initfn
,
937 .class_size
= sizeof(SPARCCPUClass
),
938 .class_init
= sparc_cpu_class_init
,
941 static void sparc_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
943 SPARCCPUClass
*scc
= SPARC_CPU_CLASS(oc
);
947 static void sparc_register_cpudef_type(const struct sparc_def_t
*def
)
949 char *typename
= sparc_cpu_type_name(def
->name
);
952 .parent
= TYPE_SPARC_CPU
,
953 .class_init
= sparc_cpu_cpudef_class_init
,
954 .class_data
= (void *)def
,
961 static void sparc_cpu_register_types(void)
965 type_register_static(&sparc_cpu_type_info
);
966 for (i
= 0; i
< ARRAY_SIZE(sparc_defs
); i
++) {
967 sparc_register_cpudef_type(&sparc_defs
[i
]);
971 type_init(sparc_cpu_register_types
)