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target-sparc: implement auto-demapping for UA2005 CPUs
[mirror_qemu.git] / target / sparc / ldst_helper.c
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "tcg.h"
23 #include "exec/helper-proto.h"
24 #include "exec/exec-all.h"
25 #include "exec/cpu_ldst.h"
26 #include "asi.h"
27
28 //#define DEBUG_MMU
29 //#define DEBUG_MXCC
30 //#define DEBUG_UNALIGNED
31 //#define DEBUG_UNASSIGNED
32 //#define DEBUG_ASI
33 //#define DEBUG_CACHE_CONTROL
34
35 #ifdef DEBUG_MMU
36 #define DPRINTF_MMU(fmt, ...) \
37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
38 #else
39 #define DPRINTF_MMU(fmt, ...) do {} while (0)
40 #endif
41
42 #ifdef DEBUG_MXCC
43 #define DPRINTF_MXCC(fmt, ...) \
44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
47 #endif
48
49 #ifdef DEBUG_ASI
50 #define DPRINTF_ASI(fmt, ...) \
51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
52 #endif
53
54 #ifdef DEBUG_CACHE_CONTROL
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
57 #else
58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
59 #endif
60
61 #ifdef TARGET_SPARC64
62 #ifndef TARGET_ABI32
63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
64 #else
65 #define AM_CHECK(env1) (1)
66 #endif
67 #endif
68
69 #define QT0 (env->qt0)
70 #define QT1 (env->qt1)
71
72 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
73 /* Calculates TSB pointer value for fault page size
74 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers
75 * UA2005 holds the page size configuration in mmu_ctx registers */
76 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env,
77 const SparcV9MMU *mmu, const int idx)
78 {
79 uint64_t tsb_register;
80 int page_size;
81 if (cpu_has_hypervisor(env)) {
82 int tsb_index = 0;
83 int ctx = mmu->tag_access & 0x1fffULL;
84 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0];
85 tsb_index = idx;
86 tsb_index |= ctx ? 2 : 0;
87 page_size = idx ? ctx_register >> 8 : ctx_register;
88 page_size &= 7;
89 tsb_register = mmu->sun4v_tsb_pointers[tsb_index];
90 } else {
91 page_size = idx;
92 tsb_register = mmu->tsb;
93 }
94 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
95 int tsb_size = tsb_register & 0xf;
96
97 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size;
98
99 /* move va bits to correct position,
100 * the context bits will be masked out later */
101 uint64_t va = mmu->tag_access >> (3 * page_size + 9);
102
103 /* calculate tsb_base mask and adjust va if split is in use */
104 if (tsb_split) {
105 if (idx == 0) {
106 va &= ~(1ULL << (13 + tsb_size));
107 } else {
108 va |= (1ULL << (13 + tsb_size));
109 }
110 tsb_base_mask <<= 1;
111 }
112
113 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
114 }
115
116 /* Calculates tag target register value by reordering bits
117 in tag access register */
118 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
119 {
120 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
121 }
122
123 static void replace_tlb_entry(SparcTLBEntry *tlb,
124 uint64_t tlb_tag, uint64_t tlb_tte,
125 CPUSPARCState *env1)
126 {
127 target_ulong mask, size, va, offset;
128
129 /* flush page range if translation is valid */
130 if (TTE_IS_VALID(tlb->tte)) {
131 CPUState *cs = CPU(sparc_env_get_cpu(env1));
132
133 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte);
134 mask = 1ULL + ~size;
135
136 va = tlb->tag & mask;
137
138 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
139 tlb_flush_page(cs, va + offset);
140 }
141 }
142
143 tlb->tag = tlb_tag;
144 tlb->tte = tlb_tte;
145 }
146
147 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
148 const char *strmmu, CPUSPARCState *env1)
149 {
150 unsigned int i;
151 target_ulong mask;
152 uint64_t context;
153
154 int is_demap_context = (demap_addr >> 6) & 1;
155
156 /* demap context */
157 switch ((demap_addr >> 4) & 3) {
158 case 0: /* primary */
159 context = env1->dmmu.mmu_primary_context;
160 break;
161 case 1: /* secondary */
162 context = env1->dmmu.mmu_secondary_context;
163 break;
164 case 2: /* nucleus */
165 context = 0;
166 break;
167 case 3: /* reserved */
168 default:
169 return;
170 }
171
172 for (i = 0; i < 64; i++) {
173 if (TTE_IS_VALID(tlb[i].tte)) {
174
175 if (is_demap_context) {
176 /* will remove non-global entries matching context value */
177 if (TTE_IS_GLOBAL(tlb[i].tte) ||
178 !tlb_compare_context(&tlb[i], context)) {
179 continue;
180 }
181 } else {
182 /* demap page
183 will remove any entry matching VA */
184 mask = 0xffffffffffffe000ULL;
185 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
186
187 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
188 continue;
189 }
190
191 /* entry should be global or matching context value */
192 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
193 !tlb_compare_context(&tlb[i], context)) {
194 continue;
195 }
196 }
197
198 replace_tlb_entry(&tlb[i], 0, 0, env1);
199 #ifdef DEBUG_MMU
200 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
201 dump_mmu(stdout, fprintf, env1);
202 #endif
203 }
204 }
205 }
206
207 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
208 uint64_t tlb_tag, uint64_t tlb_tte,
209 const char *strmmu, CPUSPARCState *env1)
210 {
211 unsigned int i, replace_used;
212
213 if (cpu_has_hypervisor(env1)) {
214 uint64_t new_vaddr = tlb_tag & ~0x1fffULL;
215 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte);
216 uint32_t new_ctx = tlb_tag & 0x1fffU;
217 for (i = 0; i < 64; i++) {
218 uint32_t ctx = tlb[i].tag & 0x1fffU;
219 /* check if new mapping overlaps an existing one */
220 if (new_ctx == ctx) {
221 uint64_t vaddr = tlb[i].tag & ~0x1fffULL;
222 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte);
223 if (new_vaddr == vaddr
224 || (new_vaddr < vaddr + size
225 && vaddr < new_vaddr + new_size)) {
226 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr,
227 new_vaddr);
228 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
229 return;
230 }
231 }
232
233 }
234 }
235 /* Try replacing invalid entry */
236 for (i = 0; i < 64; i++) {
237 if (!TTE_IS_VALID(tlb[i].tte)) {
238 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
239 #ifdef DEBUG_MMU
240 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
241 dump_mmu(stdout, fprintf, env1);
242 #endif
243 return;
244 }
245 }
246
247 /* All entries are valid, try replacing unlocked entry */
248
249 for (replace_used = 0; replace_used < 2; ++replace_used) {
250
251 /* Used entries are not replaced on first pass */
252
253 for (i = 0; i < 64; i++) {
254 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
255
256 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
257 #ifdef DEBUG_MMU
258 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
259 strmmu, (replace_used ? "used" : "unused"), i);
260 dump_mmu(stdout, fprintf, env1);
261 #endif
262 return;
263 }
264 }
265
266 /* Now reset used bit and search for unused entries again */
267
268 for (i = 0; i < 64; i++) {
269 TTE_SET_UNUSED(tlb[i].tte);
270 }
271 }
272
273 #ifdef DEBUG_MMU
274 DPRINTF_MMU("%s lru replacement: no free entries available, "
275 "replacing the last one\n", strmmu);
276 #endif
277 /* corner case: the last entry is replaced anyway */
278 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1);
279 }
280
281 #endif
282
283 #ifdef TARGET_SPARC64
284 /* returns true if access using this ASI is to have address translated by MMU
285 otherwise access is to raw physical address */
286 /* TODO: check sparc32 bits */
287 static inline int is_translating_asi(int asi)
288 {
289 /* Ultrasparc IIi translating asi
290 - note this list is defined by cpu implementation
291 */
292 switch (asi) {
293 case 0x04 ... 0x11:
294 case 0x16 ... 0x19:
295 case 0x1E ... 0x1F:
296 case 0x24 ... 0x2C:
297 case 0x70 ... 0x73:
298 case 0x78 ... 0x79:
299 case 0x80 ... 0xFF:
300 return 1;
301
302 default:
303 return 0;
304 }
305 }
306
307 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
308 {
309 if (AM_CHECK(env1)) {
310 addr &= 0xffffffffULL;
311 }
312 return addr;
313 }
314
315 static inline target_ulong asi_address_mask(CPUSPARCState *env,
316 int asi, target_ulong addr)
317 {
318 if (is_translating_asi(asi)) {
319 addr = address_mask(env, addr);
320 }
321 return addr;
322 }
323
324 #ifndef CONFIG_USER_ONLY
325 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra)
326 {
327 /* ASIs >= 0x80 are user mode.
328 * ASIs >= 0x30 are hyper mode (or super if hyper is not available).
329 * ASIs <= 0x2f are super mode.
330 */
331 if (asi < 0x80
332 && !cpu_hypervisor_mode(env)
333 && (!cpu_supervisor_mode(env)
334 || (asi >= 0x30 && cpu_has_hypervisor(env)))) {
335 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra);
336 }
337 }
338 #endif /* !CONFIG_USER_ONLY */
339 #endif
340
341 static void do_check_align(CPUSPARCState *env, target_ulong addr,
342 uint32_t align, uintptr_t ra)
343 {
344 if (addr & align) {
345 #ifdef DEBUG_UNALIGNED
346 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
347 "\n", addr, env->pc);
348 #endif
349 cpu_raise_exception_ra(env, TT_UNALIGNED, ra);
350 }
351 }
352
353 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
354 {
355 do_check_align(env, addr, align, GETPC());
356 }
357
358 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
359 defined(DEBUG_MXCC)
360 static void dump_mxcc(CPUSPARCState *env)
361 {
362 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
363 "\n",
364 env->mxccdata[0], env->mxccdata[1],
365 env->mxccdata[2], env->mxccdata[3]);
366 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
367 "\n"
368 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
369 "\n",
370 env->mxccregs[0], env->mxccregs[1],
371 env->mxccregs[2], env->mxccregs[3],
372 env->mxccregs[4], env->mxccregs[5],
373 env->mxccregs[6], env->mxccregs[7]);
374 }
375 #endif
376
377 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
378 && defined(DEBUG_ASI)
379 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
380 uint64_t r1)
381 {
382 switch (size) {
383 case 1:
384 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
385 addr, asi, r1 & 0xff);
386 break;
387 case 2:
388 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
389 addr, asi, r1 & 0xffff);
390 break;
391 case 4:
392 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
393 addr, asi, r1 & 0xffffffff);
394 break;
395 case 8:
396 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
397 addr, asi, r1);
398 break;
399 }
400 }
401 #endif
402
403 #ifndef TARGET_SPARC64
404 #ifndef CONFIG_USER_ONLY
405
406
407 /* Leon3 cache control */
408
409 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
410 uint64_t val, int size)
411 {
412 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
413 addr, val, size);
414
415 if (size != 4) {
416 DPRINTF_CACHE_CONTROL("32bits only\n");
417 return;
418 }
419
420 switch (addr) {
421 case 0x00: /* Cache control */
422
423 /* These values must always be read as zeros */
424 val &= ~CACHE_CTRL_FD;
425 val &= ~CACHE_CTRL_FI;
426 val &= ~CACHE_CTRL_IB;
427 val &= ~CACHE_CTRL_IP;
428 val &= ~CACHE_CTRL_DP;
429
430 env->cache_control = val;
431 break;
432 case 0x04: /* Instruction cache configuration */
433 case 0x08: /* Data cache configuration */
434 /* Read Only */
435 break;
436 default:
437 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
438 break;
439 };
440 }
441
442 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
443 int size)
444 {
445 uint64_t ret = 0;
446
447 if (size != 4) {
448 DPRINTF_CACHE_CONTROL("32bits only\n");
449 return 0;
450 }
451
452 switch (addr) {
453 case 0x00: /* Cache control */
454 ret = env->cache_control;
455 break;
456
457 /* Configuration registers are read and only always keep those
458 predefined values */
459
460 case 0x04: /* Instruction cache configuration */
461 ret = 0x10220000;
462 break;
463 case 0x08: /* Data cache configuration */
464 ret = 0x18220000;
465 break;
466 default:
467 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
468 break;
469 };
470 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
471 addr, ret, size);
472 return ret;
473 }
474
475 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
476 int asi, uint32_t memop)
477 {
478 int size = 1 << (memop & MO_SIZE);
479 int sign = memop & MO_SIGN;
480 CPUState *cs = CPU(sparc_env_get_cpu(env));
481 uint64_t ret = 0;
482 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
483 uint32_t last_addr = addr;
484 #endif
485
486 do_check_align(env, addr, size - 1, GETPC());
487 switch (asi) {
488 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
489 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
490 switch (addr) {
491 case 0x00: /* Leon3 Cache Control */
492 case 0x08: /* Leon3 Instruction Cache config */
493 case 0x0C: /* Leon3 Date Cache config */
494 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
495 ret = leon3_cache_control_ld(env, addr, size);
496 }
497 break;
498 case 0x01c00a00: /* MXCC control register */
499 if (size == 8) {
500 ret = env->mxccregs[3];
501 } else {
502 qemu_log_mask(LOG_UNIMP,
503 "%08x: unimplemented access size: %d\n", addr,
504 size);
505 }
506 break;
507 case 0x01c00a04: /* MXCC control register */
508 if (size == 4) {
509 ret = env->mxccregs[3];
510 } else {
511 qemu_log_mask(LOG_UNIMP,
512 "%08x: unimplemented access size: %d\n", addr,
513 size);
514 }
515 break;
516 case 0x01c00c00: /* Module reset register */
517 if (size == 8) {
518 ret = env->mxccregs[5];
519 /* should we do something here? */
520 } else {
521 qemu_log_mask(LOG_UNIMP,
522 "%08x: unimplemented access size: %d\n", addr,
523 size);
524 }
525 break;
526 case 0x01c00f00: /* MBus port address register */
527 if (size == 8) {
528 ret = env->mxccregs[7];
529 } else {
530 qemu_log_mask(LOG_UNIMP,
531 "%08x: unimplemented access size: %d\n", addr,
532 size);
533 }
534 break;
535 default:
536 qemu_log_mask(LOG_UNIMP,
537 "%08x: unimplemented address, size: %d\n", addr,
538 size);
539 break;
540 }
541 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
542 "addr = %08x -> ret = %" PRIx64 ","
543 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
544 #ifdef DEBUG_MXCC
545 dump_mxcc(env);
546 #endif
547 break;
548 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */
549 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */
550 {
551 int mmulev;
552
553 mmulev = (addr >> 8) & 15;
554 if (mmulev > 4) {
555 ret = 0;
556 } else {
557 ret = mmu_probe(env, addr, mmulev);
558 }
559 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
560 addr, mmulev, ret);
561 }
562 break;
563 case ASI_M_MMUREGS: /* SuperSparc MMU regs */
564 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */
565 {
566 int reg = (addr >> 8) & 0x1f;
567
568 ret = env->mmuregs[reg];
569 if (reg == 3) { /* Fault status cleared on read */
570 env->mmuregs[3] = 0;
571 } else if (reg == 0x13) { /* Fault status read */
572 ret = env->mmuregs[3];
573 } else if (reg == 0x14) { /* Fault address read */
574 ret = env->mmuregs[4];
575 }
576 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
577 }
578 break;
579 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
580 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
581 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
582 break;
583 case ASI_KERNELTXT: /* Supervisor code access */
584 switch (size) {
585 case 1:
586 ret = cpu_ldub_code(env, addr);
587 break;
588 case 2:
589 ret = cpu_lduw_code(env, addr);
590 break;
591 default:
592 case 4:
593 ret = cpu_ldl_code(env, addr);
594 break;
595 case 8:
596 ret = cpu_ldq_code(env, addr);
597 break;
598 }
599 break;
600 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */
601 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */
602 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */
603 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */
604 break;
605 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
606 switch (size) {
607 case 1:
608 ret = ldub_phys(cs->as, (hwaddr)addr
609 | ((hwaddr)(asi & 0xf) << 32));
610 break;
611 case 2:
612 ret = lduw_phys(cs->as, (hwaddr)addr
613 | ((hwaddr)(asi & 0xf) << 32));
614 break;
615 default:
616 case 4:
617 ret = ldl_phys(cs->as, (hwaddr)addr
618 | ((hwaddr)(asi & 0xf) << 32));
619 break;
620 case 8:
621 ret = ldq_phys(cs->as, (hwaddr)addr
622 | ((hwaddr)(asi & 0xf) << 32));
623 break;
624 }
625 break;
626 case 0x30: /* Turbosparc secondary cache diagnostic */
627 case 0x31: /* Turbosparc RAM snoop */
628 case 0x32: /* Turbosparc page table descriptor diagnostic */
629 case 0x39: /* data cache diagnostic register */
630 ret = 0;
631 break;
632 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
633 {
634 int reg = (addr >> 8) & 3;
635
636 switch (reg) {
637 case 0: /* Breakpoint Value (Addr) */
638 ret = env->mmubpregs[reg];
639 break;
640 case 1: /* Breakpoint Mask */
641 ret = env->mmubpregs[reg];
642 break;
643 case 2: /* Breakpoint Control */
644 ret = env->mmubpregs[reg];
645 break;
646 case 3: /* Breakpoint Status */
647 ret = env->mmubpregs[reg];
648 env->mmubpregs[reg] = 0ULL;
649 break;
650 }
651 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
652 ret);
653 }
654 break;
655 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
656 ret = env->mmubpctrv;
657 break;
658 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
659 ret = env->mmubpctrc;
660 break;
661 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
662 ret = env->mmubpctrs;
663 break;
664 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
665 ret = env->mmubpaction;
666 break;
667 case ASI_USERTXT: /* User code access, XXX */
668 default:
669 cpu_unassigned_access(cs, addr, false, false, asi, size);
670 ret = 0;
671 break;
672
673 case ASI_USERDATA: /* User data access */
674 case ASI_KERNELDATA: /* Supervisor data access */
675 case ASI_P: /* Implicit primary context data access (v9 only?) */
676 case ASI_M_BYPASS: /* MMU passthrough */
677 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
678 /* These are always handled inline. */
679 g_assert_not_reached();
680 }
681 if (sign) {
682 switch (size) {
683 case 1:
684 ret = (int8_t) ret;
685 break;
686 case 2:
687 ret = (int16_t) ret;
688 break;
689 case 4:
690 ret = (int32_t) ret;
691 break;
692 default:
693 break;
694 }
695 }
696 #ifdef DEBUG_ASI
697 dump_asi("read ", last_addr, asi, size, ret);
698 #endif
699 return ret;
700 }
701
702 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
703 int asi, uint32_t memop)
704 {
705 int size = 1 << (memop & MO_SIZE);
706 SPARCCPU *cpu = sparc_env_get_cpu(env);
707 CPUState *cs = CPU(cpu);
708
709 do_check_align(env, addr, size - 1, GETPC());
710 switch (asi) {
711 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
712 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
713 switch (addr) {
714 case 0x00: /* Leon3 Cache Control */
715 case 0x08: /* Leon3 Instruction Cache config */
716 case 0x0C: /* Leon3 Date Cache config */
717 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
718 leon3_cache_control_st(env, addr, val, size);
719 }
720 break;
721
722 case 0x01c00000: /* MXCC stream data register 0 */
723 if (size == 8) {
724 env->mxccdata[0] = val;
725 } else {
726 qemu_log_mask(LOG_UNIMP,
727 "%08x: unimplemented access size: %d\n", addr,
728 size);
729 }
730 break;
731 case 0x01c00008: /* MXCC stream data register 1 */
732 if (size == 8) {
733 env->mxccdata[1] = val;
734 } else {
735 qemu_log_mask(LOG_UNIMP,
736 "%08x: unimplemented access size: %d\n", addr,
737 size);
738 }
739 break;
740 case 0x01c00010: /* MXCC stream data register 2 */
741 if (size == 8) {
742 env->mxccdata[2] = val;
743 } else {
744 qemu_log_mask(LOG_UNIMP,
745 "%08x: unimplemented access size: %d\n", addr,
746 size);
747 }
748 break;
749 case 0x01c00018: /* MXCC stream data register 3 */
750 if (size == 8) {
751 env->mxccdata[3] = val;
752 } else {
753 qemu_log_mask(LOG_UNIMP,
754 "%08x: unimplemented access size: %d\n", addr,
755 size);
756 }
757 break;
758 case 0x01c00100: /* MXCC stream source */
759 if (size == 8) {
760 env->mxccregs[0] = val;
761 } else {
762 qemu_log_mask(LOG_UNIMP,
763 "%08x: unimplemented access size: %d\n", addr,
764 size);
765 }
766 env->mxccdata[0] = ldq_phys(cs->as,
767 (env->mxccregs[0] & 0xffffffffULL) +
768 0);
769 env->mxccdata[1] = ldq_phys(cs->as,
770 (env->mxccregs[0] & 0xffffffffULL) +
771 8);
772 env->mxccdata[2] = ldq_phys(cs->as,
773 (env->mxccregs[0] & 0xffffffffULL) +
774 16);
775 env->mxccdata[3] = ldq_phys(cs->as,
776 (env->mxccregs[0] & 0xffffffffULL) +
777 24);
778 break;
779 case 0x01c00200: /* MXCC stream destination */
780 if (size == 8) {
781 env->mxccregs[1] = val;
782 } else {
783 qemu_log_mask(LOG_UNIMP,
784 "%08x: unimplemented access size: %d\n", addr,
785 size);
786 }
787 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
788 env->mxccdata[0]);
789 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
790 env->mxccdata[1]);
791 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
792 env->mxccdata[2]);
793 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
794 env->mxccdata[3]);
795 break;
796 case 0x01c00a00: /* MXCC control register */
797 if (size == 8) {
798 env->mxccregs[3] = val;
799 } else {
800 qemu_log_mask(LOG_UNIMP,
801 "%08x: unimplemented access size: %d\n", addr,
802 size);
803 }
804 break;
805 case 0x01c00a04: /* MXCC control register */
806 if (size == 4) {
807 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
808 | val;
809 } else {
810 qemu_log_mask(LOG_UNIMP,
811 "%08x: unimplemented access size: %d\n", addr,
812 size);
813 }
814 break;
815 case 0x01c00e00: /* MXCC error register */
816 /* writing a 1 bit clears the error */
817 if (size == 8) {
818 env->mxccregs[6] &= ~val;
819 } else {
820 qemu_log_mask(LOG_UNIMP,
821 "%08x: unimplemented access size: %d\n", addr,
822 size);
823 }
824 break;
825 case 0x01c00f00: /* MBus port address register */
826 if (size == 8) {
827 env->mxccregs[7] = val;
828 } else {
829 qemu_log_mask(LOG_UNIMP,
830 "%08x: unimplemented access size: %d\n", addr,
831 size);
832 }
833 break;
834 default:
835 qemu_log_mask(LOG_UNIMP,
836 "%08x: unimplemented address, size: %d\n", addr,
837 size);
838 break;
839 }
840 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
841 asi, size, addr, val);
842 #ifdef DEBUG_MXCC
843 dump_mxcc(env);
844 #endif
845 break;
846 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */
847 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */
848 {
849 int mmulev;
850
851 mmulev = (addr >> 8) & 15;
852 DPRINTF_MMU("mmu flush level %d\n", mmulev);
853 switch (mmulev) {
854 case 0: /* flush page */
855 tlb_flush_page(CPU(cpu), addr & 0xfffff000);
856 break;
857 case 1: /* flush segment (256k) */
858 case 2: /* flush region (16M) */
859 case 3: /* flush context (4G) */
860 case 4: /* flush entire */
861 tlb_flush(CPU(cpu));
862 break;
863 default:
864 break;
865 }
866 #ifdef DEBUG_MMU
867 dump_mmu(stdout, fprintf, env);
868 #endif
869 }
870 break;
871 case ASI_M_MMUREGS: /* write MMU regs */
872 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */
873 {
874 int reg = (addr >> 8) & 0x1f;
875 uint32_t oldreg;
876
877 oldreg = env->mmuregs[reg];
878 switch (reg) {
879 case 0: /* Control Register */
880 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
881 (val & 0x00ffffff);
882 /* Mappings generated during no-fault mode
883 are invalid in normal mode. */
884 if ((oldreg ^ env->mmuregs[reg])
885 & (MMU_NF | env->def->mmu_bm)) {
886 tlb_flush(CPU(cpu));
887 }
888 break;
889 case 1: /* Context Table Pointer Register */
890 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
891 break;
892 case 2: /* Context Register */
893 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
894 if (oldreg != env->mmuregs[reg]) {
895 /* we flush when the MMU context changes because
896 QEMU has no MMU context support */
897 tlb_flush(CPU(cpu));
898 }
899 break;
900 case 3: /* Synchronous Fault Status Register with Clear */
901 case 4: /* Synchronous Fault Address Register */
902 break;
903 case 0x10: /* TLB Replacement Control Register */
904 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
905 break;
906 case 0x13: /* Synchronous Fault Status Register with Read
907 and Clear */
908 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
909 break;
910 case 0x14: /* Synchronous Fault Address Register */
911 env->mmuregs[4] = val;
912 break;
913 default:
914 env->mmuregs[reg] = val;
915 break;
916 }
917 if (oldreg != env->mmuregs[reg]) {
918 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
919 reg, oldreg, env->mmuregs[reg]);
920 }
921 #ifdef DEBUG_MMU
922 dump_mmu(stdout, fprintf, env);
923 #endif
924 }
925 break;
926 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
927 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
928 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
929 break;
930 case ASI_M_TXTC_TAG: /* I-cache tag */
931 case ASI_M_TXTC_DATA: /* I-cache data */
932 case ASI_M_DATAC_TAG: /* D-cache tag */
933 case ASI_M_DATAC_DATA: /* D-cache data */
934 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */
935 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */
936 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */
937 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */
938 case ASI_M_FLUSH_USER: /* I/D-cache flush user */
939 break;
940 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
941 {
942 switch (size) {
943 case 1:
944 stb_phys(cs->as, (hwaddr)addr
945 | ((hwaddr)(asi & 0xf) << 32), val);
946 break;
947 case 2:
948 stw_phys(cs->as, (hwaddr)addr
949 | ((hwaddr)(asi & 0xf) << 32), val);
950 break;
951 case 4:
952 default:
953 stl_phys(cs->as, (hwaddr)addr
954 | ((hwaddr)(asi & 0xf) << 32), val);
955 break;
956 case 8:
957 stq_phys(cs->as, (hwaddr)addr
958 | ((hwaddr)(asi & 0xf) << 32), val);
959 break;
960 }
961 }
962 break;
963 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
964 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
965 Turbosparc snoop RAM */
966 case 0x32: /* store buffer control or Turbosparc page table
967 descriptor diagnostic */
968 case 0x36: /* I-cache flash clear */
969 case 0x37: /* D-cache flash clear */
970 break;
971 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
972 {
973 int reg = (addr >> 8) & 3;
974
975 switch (reg) {
976 case 0: /* Breakpoint Value (Addr) */
977 env->mmubpregs[reg] = (val & 0xfffffffffULL);
978 break;
979 case 1: /* Breakpoint Mask */
980 env->mmubpregs[reg] = (val & 0xfffffffffULL);
981 break;
982 case 2: /* Breakpoint Control */
983 env->mmubpregs[reg] = (val & 0x7fULL);
984 break;
985 case 3: /* Breakpoint Status */
986 env->mmubpregs[reg] = (val & 0xfULL);
987 break;
988 }
989 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
990 env->mmuregs[reg]);
991 }
992 break;
993 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
994 env->mmubpctrv = val & 0xffffffff;
995 break;
996 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
997 env->mmubpctrc = val & 0x3;
998 break;
999 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1000 env->mmubpctrs = val & 0x3;
1001 break;
1002 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1003 env->mmubpaction = val & 0x1fff;
1004 break;
1005 case ASI_USERTXT: /* User code access, XXX */
1006 case ASI_KERNELTXT: /* Supervisor code access, XXX */
1007 default:
1008 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1009 addr, true, false, asi, size);
1010 break;
1011
1012 case ASI_USERDATA: /* User data access */
1013 case ASI_KERNELDATA: /* Supervisor data access */
1014 case ASI_P:
1015 case ASI_M_BYPASS: /* MMU passthrough */
1016 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
1017 case ASI_M_BCOPY: /* Block copy, sta access */
1018 case ASI_M_BFILL: /* Block fill, stda access */
1019 /* These are always handled inline. */
1020 g_assert_not_reached();
1021 }
1022 #ifdef DEBUG_ASI
1023 dump_asi("write", addr, asi, size, val);
1024 #endif
1025 }
1026
1027 #endif /* CONFIG_USER_ONLY */
1028 #else /* TARGET_SPARC64 */
1029
1030 #ifdef CONFIG_USER_ONLY
1031 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
1032 int asi, uint32_t memop)
1033 {
1034 int size = 1 << (memop & MO_SIZE);
1035 int sign = memop & MO_SIGN;
1036 uint64_t ret = 0;
1037
1038 if (asi < 0x80) {
1039 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
1040 }
1041 do_check_align(env, addr, size - 1, GETPC());
1042 addr = asi_address_mask(env, asi, addr);
1043
1044 switch (asi) {
1045 case ASI_PNF: /* Primary no-fault */
1046 case ASI_PNFL: /* Primary no-fault LE */
1047 case ASI_SNF: /* Secondary no-fault */
1048 case ASI_SNFL: /* Secondary no-fault LE */
1049 if (page_check_range(addr, size, PAGE_READ) == -1) {
1050 ret = 0;
1051 break;
1052 }
1053 switch (size) {
1054 case 1:
1055 ret = cpu_ldub_data(env, addr);
1056 break;
1057 case 2:
1058 ret = cpu_lduw_data(env, addr);
1059 break;
1060 case 4:
1061 ret = cpu_ldl_data(env, addr);
1062 break;
1063 case 8:
1064 ret = cpu_ldq_data(env, addr);
1065 break;
1066 default:
1067 g_assert_not_reached();
1068 }
1069 break;
1070 break;
1071
1072 case ASI_P: /* Primary */
1073 case ASI_PL: /* Primary LE */
1074 case ASI_S: /* Secondary */
1075 case ASI_SL: /* Secondary LE */
1076 /* These are always handled inline. */
1077 g_assert_not_reached();
1078
1079 default:
1080 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
1081 }
1082
1083 /* Convert from little endian */
1084 switch (asi) {
1085 case ASI_PNFL: /* Primary no-fault LE */
1086 case ASI_SNFL: /* Secondary no-fault LE */
1087 switch (size) {
1088 case 2:
1089 ret = bswap16(ret);
1090 break;
1091 case 4:
1092 ret = bswap32(ret);
1093 break;
1094 case 8:
1095 ret = bswap64(ret);
1096 break;
1097 }
1098 }
1099
1100 /* Convert to signed number */
1101 if (sign) {
1102 switch (size) {
1103 case 1:
1104 ret = (int8_t) ret;
1105 break;
1106 case 2:
1107 ret = (int16_t) ret;
1108 break;
1109 case 4:
1110 ret = (int32_t) ret;
1111 break;
1112 }
1113 }
1114 #ifdef DEBUG_ASI
1115 dump_asi("read", addr, asi, size, ret);
1116 #endif
1117 return ret;
1118 }
1119
1120 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1121 int asi, uint32_t memop)
1122 {
1123 int size = 1 << (memop & MO_SIZE);
1124 #ifdef DEBUG_ASI
1125 dump_asi("write", addr, asi, size, val);
1126 #endif
1127 if (asi < 0x80) {
1128 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
1129 }
1130 do_check_align(env, addr, size - 1, GETPC());
1131
1132 switch (asi) {
1133 case ASI_P: /* Primary */
1134 case ASI_PL: /* Primary LE */
1135 case ASI_S: /* Secondary */
1136 case ASI_SL: /* Secondary LE */
1137 /* These are always handled inline. */
1138 g_assert_not_reached();
1139
1140 case ASI_PNF: /* Primary no-fault, RO */
1141 case ASI_SNF: /* Secondary no-fault, RO */
1142 case ASI_PNFL: /* Primary no-fault LE, RO */
1143 case ASI_SNFL: /* Secondary no-fault LE, RO */
1144 default:
1145 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
1146 }
1147 }
1148
1149 #else /* CONFIG_USER_ONLY */
1150
1151 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
1152 int asi, uint32_t memop)
1153 {
1154 int size = 1 << (memop & MO_SIZE);
1155 int sign = memop & MO_SIGN;
1156 CPUState *cs = CPU(sparc_env_get_cpu(env));
1157 uint64_t ret = 0;
1158 #if defined(DEBUG_ASI)
1159 target_ulong last_addr = addr;
1160 #endif
1161
1162 asi &= 0xff;
1163
1164 do_check_asi(env, asi, GETPC());
1165 do_check_align(env, addr, size - 1, GETPC());
1166 addr = asi_address_mask(env, asi, addr);
1167
1168 switch (asi) {
1169 case ASI_PNF:
1170 case ASI_PNFL:
1171 case ASI_SNF:
1172 case ASI_SNFL:
1173 {
1174 TCGMemOpIdx oi;
1175 int idx = (env->pstate & PS_PRIV
1176 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX)
1177 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX));
1178
1179 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) {
1180 #ifdef DEBUG_ASI
1181 dump_asi("read ", last_addr, asi, size, ret);
1182 #endif
1183 /* exception_index is set in get_physical_address_data. */
1184 cpu_raise_exception_ra(env, cs->exception_index, GETPC());
1185 }
1186 oi = make_memop_idx(memop, idx);
1187 switch (size) {
1188 case 1:
1189 ret = helper_ret_ldub_mmu(env, addr, oi, GETPC());
1190 break;
1191 case 2:
1192 if (asi & 8) {
1193 ret = helper_le_lduw_mmu(env, addr, oi, GETPC());
1194 } else {
1195 ret = helper_be_lduw_mmu(env, addr, oi, GETPC());
1196 }
1197 break;
1198 case 4:
1199 if (asi & 8) {
1200 ret = helper_le_ldul_mmu(env, addr, oi, GETPC());
1201 } else {
1202 ret = helper_be_ldul_mmu(env, addr, oi, GETPC());
1203 }
1204 break;
1205 case 8:
1206 if (asi & 8) {
1207 ret = helper_le_ldq_mmu(env, addr, oi, GETPC());
1208 } else {
1209 ret = helper_be_ldq_mmu(env, addr, oi, GETPC());
1210 }
1211 break;
1212 default:
1213 g_assert_not_reached();
1214 }
1215 }
1216 break;
1217
1218 case ASI_AIUP: /* As if user primary */
1219 case ASI_AIUS: /* As if user secondary */
1220 case ASI_AIUPL: /* As if user primary LE */
1221 case ASI_AIUSL: /* As if user secondary LE */
1222 case ASI_P: /* Primary */
1223 case ASI_S: /* Secondary */
1224 case ASI_PL: /* Primary LE */
1225 case ASI_SL: /* Secondary LE */
1226 case ASI_REAL: /* Bypass */
1227 case ASI_REAL_IO: /* Bypass, non-cacheable */
1228 case ASI_REAL_L: /* Bypass LE */
1229 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1230 case ASI_N: /* Nucleus */
1231 case ASI_NL: /* Nucleus Little Endian (LE) */
1232 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1233 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1234 case ASI_TWINX_AIUP: /* As if user primary, twinx */
1235 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
1236 case ASI_TWINX_REAL: /* Real address, twinx */
1237 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
1238 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
1239 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1240 case ASI_TWINX_N: /* Nucleus, twinx */
1241 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
1242 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1243 case ASI_TWINX_P: /* Primary, twinx */
1244 case ASI_TWINX_PL: /* Primary, twinx, LE */
1245 case ASI_TWINX_S: /* Secondary, twinx */
1246 case ASI_TWINX_SL: /* Secondary, twinx, LE */
1247 /* These are always handled inline. */
1248 g_assert_not_reached();
1249
1250 case ASI_UPA_CONFIG: /* UPA config */
1251 /* XXX */
1252 break;
1253 case ASI_LSU_CONTROL: /* LSU */
1254 ret = env->lsu;
1255 break;
1256 case ASI_IMMU: /* I-MMU regs */
1257 {
1258 int reg = (addr >> 3) & 0xf;
1259 switch (reg) {
1260 case 0:
1261 /* 0x00 I-TSB Tag Target register */
1262 ret = ultrasparc_tag_target(env->immu.tag_access);
1263 break;
1264 case 3: /* SFSR */
1265 ret = env->immu.sfsr;
1266 break;
1267 case 5: /* TSB access */
1268 ret = env->immu.tsb;
1269 break;
1270 case 6:
1271 /* 0x30 I-TSB Tag Access register */
1272 ret = env->immu.tag_access;
1273 break;
1274 default:
1275 cpu_unassigned_access(cs, addr, false, false, 1, size);
1276 ret = 0;
1277 }
1278 break;
1279 }
1280 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */
1281 {
1282 /* env->immuregs[5] holds I-MMU TSB register value
1283 env->immuregs[6] holds I-MMU Tag Access register value */
1284 ret = ultrasparc_tsb_pointer(env, &env->immu, 0);
1285 break;
1286 }
1287 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */
1288 {
1289 /* env->immuregs[5] holds I-MMU TSB register value
1290 env->immuregs[6] holds I-MMU Tag Access register value */
1291 ret = ultrasparc_tsb_pointer(env, &env->immu, 1);
1292 break;
1293 }
1294 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1295 {
1296 int reg = (addr >> 3) & 0x3f;
1297
1298 ret = env->itlb[reg].tte;
1299 break;
1300 }
1301 case ASI_ITLB_TAG_READ: /* I-MMU tag read */
1302 {
1303 int reg = (addr >> 3) & 0x3f;
1304
1305 ret = env->itlb[reg].tag;
1306 break;
1307 }
1308 case ASI_DMMU: /* D-MMU regs */
1309 {
1310 int reg = (addr >> 3) & 0xf;
1311 switch (reg) {
1312 case 0:
1313 /* 0x00 D-TSB Tag Target register */
1314 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1315 break;
1316 case 1: /* 0x08 Primary Context */
1317 ret = env->dmmu.mmu_primary_context;
1318 break;
1319 case 2: /* 0x10 Secondary Context */
1320 ret = env->dmmu.mmu_secondary_context;
1321 break;
1322 case 3: /* SFSR */
1323 ret = env->dmmu.sfsr;
1324 break;
1325 case 4: /* 0x20 SFAR */
1326 ret = env->dmmu.sfar;
1327 break;
1328 case 5: /* 0x28 TSB access */
1329 ret = env->dmmu.tsb;
1330 break;
1331 case 6: /* 0x30 D-TSB Tag Access register */
1332 ret = env->dmmu.tag_access;
1333 break;
1334 case 7:
1335 ret = env->dmmu.virtual_watchpoint;
1336 break;
1337 case 8:
1338 ret = env->dmmu.physical_watchpoint;
1339 break;
1340 default:
1341 cpu_unassigned_access(cs, addr, false, false, 1, size);
1342 ret = 0;
1343 }
1344 break;
1345 }
1346 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */
1347 {
1348 /* env->dmmuregs[5] holds D-MMU TSB register value
1349 env->dmmuregs[6] holds D-MMU Tag Access register value */
1350 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0);
1351 break;
1352 }
1353 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */
1354 {
1355 /* env->dmmuregs[5] holds D-MMU TSB register value
1356 env->dmmuregs[6] holds D-MMU Tag Access register value */
1357 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1);
1358 break;
1359 }
1360 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1361 {
1362 int reg = (addr >> 3) & 0x3f;
1363
1364 ret = env->dtlb[reg].tte;
1365 break;
1366 }
1367 case ASI_DTLB_TAG_READ: /* D-MMU tag read */
1368 {
1369 int reg = (addr >> 3) & 0x3f;
1370
1371 ret = env->dtlb[reg].tag;
1372 break;
1373 }
1374 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
1375 break;
1376 case ASI_INTR_RECEIVE: /* Interrupt data receive */
1377 ret = env->ivec_status;
1378 break;
1379 case ASI_INTR_R: /* Incoming interrupt vector, RO */
1380 {
1381 int reg = (addr >> 4) & 0x3;
1382 if (reg < 3) {
1383 ret = env->ivec_data[reg];
1384 }
1385 break;
1386 }
1387 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
1388 if (unlikely((addr >= 0x20) && (addr < 0x30))) {
1389 /* Hyperprivileged access only */
1390 cpu_unassigned_access(cs, addr, false, false, 1, size);
1391 }
1392 /* fall through */
1393 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
1394 {
1395 unsigned int i = (addr >> 3) & 0x7;
1396 ret = env->scratch[i];
1397 break;
1398 }
1399 case ASI_DCACHE_DATA: /* D-cache data */
1400 case ASI_DCACHE_TAG: /* D-cache tag access */
1401 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1402 case ASI_AFSR: /* E-cache asynchronous fault status */
1403 case ASI_AFAR: /* E-cache asynchronous fault address */
1404 case ASI_EC_TAG_DATA: /* E-cache tag data */
1405 case ASI_IC_INSTR: /* I-cache instruction access */
1406 case ASI_IC_TAG: /* I-cache tag access */
1407 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1408 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1409 case ASI_EC_W: /* E-cache tag */
1410 case ASI_EC_R: /* E-cache tag */
1411 break;
1412 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */
1413 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */
1414 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */
1415 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */
1416 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */
1417 case ASI_INTR_W: /* Interrupt vector, WO */
1418 default:
1419 cpu_unassigned_access(cs, addr, false, false, 1, size);
1420 ret = 0;
1421 break;
1422 }
1423
1424 /* Convert to signed number */
1425 if (sign) {
1426 switch (size) {
1427 case 1:
1428 ret = (int8_t) ret;
1429 break;
1430 case 2:
1431 ret = (int16_t) ret;
1432 break;
1433 case 4:
1434 ret = (int32_t) ret;
1435 break;
1436 default:
1437 break;
1438 }
1439 }
1440 #ifdef DEBUG_ASI
1441 dump_asi("read ", last_addr, asi, size, ret);
1442 #endif
1443 return ret;
1444 }
1445
1446 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1447 int asi, uint32_t memop)
1448 {
1449 int size = 1 << (memop & MO_SIZE);
1450 SPARCCPU *cpu = sparc_env_get_cpu(env);
1451 CPUState *cs = CPU(cpu);
1452
1453 #ifdef DEBUG_ASI
1454 dump_asi("write", addr, asi, size, val);
1455 #endif
1456
1457 asi &= 0xff;
1458
1459 do_check_asi(env, asi, GETPC());
1460 do_check_align(env, addr, size - 1, GETPC());
1461 addr = asi_address_mask(env, asi, addr);
1462
1463 switch (asi) {
1464 case ASI_AIUP: /* As if user primary */
1465 case ASI_AIUS: /* As if user secondary */
1466 case ASI_AIUPL: /* As if user primary LE */
1467 case ASI_AIUSL: /* As if user secondary LE */
1468 case ASI_P: /* Primary */
1469 case ASI_S: /* Secondary */
1470 case ASI_PL: /* Primary LE */
1471 case ASI_SL: /* Secondary LE */
1472 case ASI_REAL: /* Bypass */
1473 case ASI_REAL_IO: /* Bypass, non-cacheable */
1474 case ASI_REAL_L: /* Bypass LE */
1475 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1476 case ASI_N: /* Nucleus */
1477 case ASI_NL: /* Nucleus Little Endian (LE) */
1478 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1479 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1480 case ASI_TWINX_AIUP: /* As if user primary, twinx */
1481 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
1482 case ASI_TWINX_REAL: /* Real address, twinx */
1483 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
1484 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
1485 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1486 case ASI_TWINX_N: /* Nucleus, twinx */
1487 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
1488 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1489 case ASI_TWINX_P: /* Primary, twinx */
1490 case ASI_TWINX_PL: /* Primary, twinx, LE */
1491 case ASI_TWINX_S: /* Secondary, twinx */
1492 case ASI_TWINX_SL: /* Secondary, twinx, LE */
1493 /* These are always handled inline. */
1494 g_assert_not_reached();
1495 /* these ASIs have different functions on UltraSPARC-IIIi
1496 * and UA2005 CPUs. Use the explicit numbers to avoid confusion
1497 */
1498 case 0x31:
1499 case 0x32:
1500 case 0x39:
1501 case 0x3a:
1502 if (cpu_has_hypervisor(env)) {
1503 /* UA2005
1504 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0
1505 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1
1506 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0
1507 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1
1508 */
1509 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
1510 env->dmmu.sun4v_tsb_pointers[idx] = val;
1511 } else {
1512 helper_raise_exception(env, TT_ILL_INSN);
1513 }
1514 break;
1515 case 0x33:
1516 case 0x3b:
1517 if (cpu_has_hypervisor(env)) {
1518 /* UA2005
1519 * ASI_DMMU_CTX_ZERO_CONFIG
1520 * ASI_DMMU_CTX_NONZERO_CONFIG
1521 */
1522 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val;
1523 } else {
1524 helper_raise_exception(env, TT_ILL_INSN);
1525 }
1526 break;
1527 case 0x35:
1528 case 0x36:
1529 case 0x3d:
1530 case 0x3e:
1531 if (cpu_has_hypervisor(env)) {
1532 /* UA2005
1533 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0
1534 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1
1535 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0
1536 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1
1537 */
1538 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
1539 env->immu.sun4v_tsb_pointers[idx] = val;
1540 } else {
1541 helper_raise_exception(env, TT_ILL_INSN);
1542 }
1543 break;
1544 case 0x37:
1545 case 0x3f:
1546 if (cpu_has_hypervisor(env)) {
1547 /* UA2005
1548 * ASI_IMMU_CTX_ZERO_CONFIG
1549 * ASI_IMMU_CTX_NONZERO_CONFIG
1550 */
1551 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val;
1552 } else {
1553 helper_raise_exception(env, TT_ILL_INSN);
1554 }
1555 break;
1556 case ASI_UPA_CONFIG: /* UPA config */
1557 /* XXX */
1558 return;
1559 case ASI_LSU_CONTROL: /* LSU */
1560 env->lsu = val & (DMMU_E | IMMU_E);
1561 return;
1562 case ASI_IMMU: /* I-MMU regs */
1563 {
1564 int reg = (addr >> 3) & 0xf;
1565 uint64_t oldreg;
1566
1567 oldreg = env->immu.mmuregs[reg];
1568 switch (reg) {
1569 case 0: /* RO */
1570 return;
1571 case 1: /* Not in I-MMU */
1572 case 2:
1573 return;
1574 case 3: /* SFSR */
1575 if ((val & 1) == 0) {
1576 val = 0; /* Clear SFSR */
1577 }
1578 env->immu.sfsr = val;
1579 break;
1580 case 4: /* RO */
1581 return;
1582 case 5: /* TSB access */
1583 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1584 PRIx64 "\n", env->immu.tsb, val);
1585 env->immu.tsb = val;
1586 break;
1587 case 6: /* Tag access */
1588 env->immu.tag_access = val;
1589 break;
1590 case 7:
1591 case 8:
1592 return;
1593 default:
1594 cpu_unassigned_access(cs, addr, true, false, 1, size);
1595 break;
1596 }
1597
1598 if (oldreg != env->immu.mmuregs[reg]) {
1599 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1600 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1601 }
1602 #ifdef DEBUG_MMU
1603 dump_mmu(stdout, fprintf, env);
1604 #endif
1605 return;
1606 }
1607 case ASI_ITLB_DATA_IN: /* I-MMU data in */
1608 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1609 return;
1610 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1611 {
1612 /* TODO: auto demap */
1613
1614 unsigned int i = (addr >> 3) & 0x3f;
1615
1616 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1617
1618 #ifdef DEBUG_MMU
1619 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1620 dump_mmu(stdout, fprintf, env);
1621 #endif
1622 return;
1623 }
1624 case ASI_IMMU_DEMAP: /* I-MMU demap */
1625 demap_tlb(env->itlb, addr, "immu", env);
1626 return;
1627 case ASI_DMMU: /* D-MMU regs */
1628 {
1629 int reg = (addr >> 3) & 0xf;
1630 uint64_t oldreg;
1631
1632 oldreg = env->dmmu.mmuregs[reg];
1633 switch (reg) {
1634 case 0: /* RO */
1635 case 4:
1636 return;
1637 case 3: /* SFSR */
1638 if ((val & 1) == 0) {
1639 val = 0; /* Clear SFSR, Fault address */
1640 env->dmmu.sfar = 0;
1641 }
1642 env->dmmu.sfsr = val;
1643 break;
1644 case 1: /* Primary context */
1645 env->dmmu.mmu_primary_context = val;
1646 /* can be optimized to only flush MMU_USER_IDX
1647 and MMU_KERNEL_IDX entries */
1648 tlb_flush(CPU(cpu));
1649 break;
1650 case 2: /* Secondary context */
1651 env->dmmu.mmu_secondary_context = val;
1652 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1653 and MMU_KERNEL_SECONDARY_IDX entries */
1654 tlb_flush(CPU(cpu));
1655 break;
1656 case 5: /* TSB access */
1657 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1658 PRIx64 "\n", env->dmmu.tsb, val);
1659 env->dmmu.tsb = val;
1660 break;
1661 case 6: /* Tag access */
1662 env->dmmu.tag_access = val;
1663 break;
1664 case 7: /* Virtual Watchpoint */
1665 env->dmmu.virtual_watchpoint = val;
1666 break;
1667 case 8: /* Physical Watchpoint */
1668 env->dmmu.physical_watchpoint = val;
1669 break;
1670 default:
1671 cpu_unassigned_access(cs, addr, true, false, 1, size);
1672 break;
1673 }
1674
1675 if (oldreg != env->dmmu.mmuregs[reg]) {
1676 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1677 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1678 }
1679 #ifdef DEBUG_MMU
1680 dump_mmu(stdout, fprintf, env);
1681 #endif
1682 return;
1683 }
1684 case ASI_DTLB_DATA_IN: /* D-MMU data in */
1685 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1686 return;
1687 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1688 {
1689 unsigned int i = (addr >> 3) & 0x3f;
1690
1691 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1692
1693 #ifdef DEBUG_MMU
1694 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1695 dump_mmu(stdout, fprintf, env);
1696 #endif
1697 return;
1698 }
1699 case ASI_DMMU_DEMAP: /* D-MMU demap */
1700 demap_tlb(env->dtlb, addr, "dmmu", env);
1701 return;
1702 case ASI_INTR_RECEIVE: /* Interrupt data receive */
1703 env->ivec_status = val & 0x20;
1704 return;
1705 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
1706 if (unlikely((addr >= 0x20) && (addr < 0x30))) {
1707 /* Hyperprivileged access only */
1708 cpu_unassigned_access(cs, addr, true, false, 1, size);
1709 }
1710 /* fall through */
1711 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
1712 {
1713 unsigned int i = (addr >> 3) & 0x7;
1714 env->scratch[i] = val;
1715 return;
1716 }
1717 case ASI_QUEUE: /* UA2005 CPU mondo queue */
1718 case ASI_DCACHE_DATA: /* D-cache data */
1719 case ASI_DCACHE_TAG: /* D-cache tag access */
1720 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1721 case ASI_AFSR: /* E-cache asynchronous fault status */
1722 case ASI_AFAR: /* E-cache asynchronous fault address */
1723 case ASI_EC_TAG_DATA: /* E-cache tag data */
1724 case ASI_IC_INSTR: /* I-cache instruction access */
1725 case ASI_IC_TAG: /* I-cache tag access */
1726 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1727 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1728 case ASI_EC_W: /* E-cache tag */
1729 case ASI_EC_R: /* E-cache tag */
1730 return;
1731 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */
1732 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */
1733 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */
1734 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */
1735 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */
1736 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */
1737 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */
1738 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
1739 case ASI_INTR_R: /* Incoming interrupt vector, RO */
1740 case ASI_PNF: /* Primary no-fault, RO */
1741 case ASI_SNF: /* Secondary no-fault, RO */
1742 case ASI_PNFL: /* Primary no-fault LE, RO */
1743 case ASI_SNFL: /* Secondary no-fault LE, RO */
1744 default:
1745 cpu_unassigned_access(cs, addr, true, false, 1, size);
1746 return;
1747 }
1748 }
1749 #endif /* CONFIG_USER_ONLY */
1750 #endif /* TARGET_SPARC64 */
1751
1752 #if !defined(CONFIG_USER_ONLY)
1753 #ifndef TARGET_SPARC64
1754 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
1755 bool is_write, bool is_exec, int is_asi,
1756 unsigned size)
1757 {
1758 SPARCCPU *cpu = SPARC_CPU(cs);
1759 CPUSPARCState *env = &cpu->env;
1760 int fault_type;
1761
1762 #ifdef DEBUG_UNASSIGNED
1763 if (is_asi) {
1764 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
1765 " asi 0x%02x from " TARGET_FMT_lx "\n",
1766 is_exec ? "exec" : is_write ? "write" : "read", size,
1767 size == 1 ? "" : "s", addr, is_asi, env->pc);
1768 } else {
1769 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
1770 " from " TARGET_FMT_lx "\n",
1771 is_exec ? "exec" : is_write ? "write" : "read", size,
1772 size == 1 ? "" : "s", addr, env->pc);
1773 }
1774 #endif
1775 /* Don't overwrite translation and access faults */
1776 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
1777 if ((fault_type > 4) || (fault_type == 0)) {
1778 env->mmuregs[3] = 0; /* Fault status register */
1779 if (is_asi) {
1780 env->mmuregs[3] |= 1 << 16;
1781 }
1782 if (env->psrs) {
1783 env->mmuregs[3] |= 1 << 5;
1784 }
1785 if (is_exec) {
1786 env->mmuregs[3] |= 1 << 6;
1787 }
1788 if (is_write) {
1789 env->mmuregs[3] |= 1 << 7;
1790 }
1791 env->mmuregs[3] |= (5 << 2) | 2;
1792 /* SuperSPARC will never place instruction fault addresses in the FAR */
1793 if (!is_exec) {
1794 env->mmuregs[4] = addr; /* Fault address register */
1795 }
1796 }
1797 /* overflow (same type fault was not read before another fault) */
1798 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
1799 env->mmuregs[3] |= 1;
1800 }
1801
1802 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1803 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS;
1804 cpu_raise_exception_ra(env, tt, GETPC());
1805 }
1806
1807 /* flush neverland mappings created during no-fault mode,
1808 so the sequential MMU faults report proper fault types */
1809 if (env->mmuregs[0] & MMU_NF) {
1810 tlb_flush(cs);
1811 }
1812 }
1813 #else
1814 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
1815 bool is_write, bool is_exec, int is_asi,
1816 unsigned size)
1817 {
1818 SPARCCPU *cpu = SPARC_CPU(cs);
1819 CPUSPARCState *env = &cpu->env;
1820
1821 #ifdef DEBUG_UNASSIGNED
1822 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
1823 "\n", addr, env->pc);
1824 #endif
1825
1826 if (is_exec) { /* XXX has_hypervisor */
1827 if (env->lsu & (IMMU_E)) {
1828 cpu_raise_exception_ra(env, TT_CODE_ACCESS, GETPC());
1829 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
1830 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, GETPC());
1831 }
1832 } else {
1833 if (env->lsu & (DMMU_E)) {
1834 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
1835 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
1836 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, GETPC());
1837 }
1838 }
1839 }
1840 #endif
1841 #endif
1842
1843 #if !defined(CONFIG_USER_ONLY)
1844 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
1845 MMUAccessType access_type,
1846 int mmu_idx,
1847 uintptr_t retaddr)
1848 {
1849 SPARCCPU *cpu = SPARC_CPU(cs);
1850 CPUSPARCState *env = &cpu->env;
1851
1852 #ifdef DEBUG_UNALIGNED
1853 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
1854 "\n", addr, env->pc);
1855 #endif
1856 cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
1857 }
1858
1859 /* try to fill the TLB and return an exception if error. If retaddr is
1860 NULL, it means that the function was called in C code (i.e. not
1861 from generated code or from helper.c) */
1862 /* XXX: fix it to restore all registers */
1863 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
1864 int mmu_idx, uintptr_t retaddr)
1865 {
1866 int ret;
1867
1868 ret = sparc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
1869 if (ret) {
1870 cpu_loop_exit_restore(cs, retaddr);
1871 }
1872 }
1873 #endif
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