2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/helper-proto.h"
24 #include "exec/exec-all.h"
25 #include "exec/cpu_ldst.h"
30 //#define DEBUG_UNASSIGNED
32 //#define DEBUG_CACHE_CONTROL
35 #define DPRINTF_MMU(fmt, ...) \
36 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
38 #define DPRINTF_MMU(fmt, ...) do {} while (0)
42 #define DPRINTF_MXCC(fmt, ...) \
43 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
45 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
49 #define DPRINTF_ASI(fmt, ...) \
50 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
53 #ifdef DEBUG_CACHE_CONTROL
54 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
55 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
57 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
62 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
64 #define AM_CHECK(env1) (1)
68 #define QT0 (env->qt0)
69 #define QT1 (env->qt1)
71 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
72 /* Calculates TSB pointer value for fault page size
73 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers
74 * UA2005 holds the page size configuration in mmu_ctx registers */
75 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState
*env
,
76 const SparcV9MMU
*mmu
, const int idx
)
78 uint64_t tsb_register
;
80 if (cpu_has_hypervisor(env
)) {
82 int ctx
= mmu
->tag_access
& 0x1fffULL
;
83 uint64_t ctx_register
= mmu
->sun4v_ctx_config
[ctx
? 1 : 0];
85 tsb_index
|= ctx
? 2 : 0;
86 page_size
= idx
? ctx_register
>> 8 : ctx_register
;
88 tsb_register
= mmu
->sun4v_tsb_pointers
[tsb_index
];
91 tsb_register
= mmu
->tsb
;
93 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
94 int tsb_size
= tsb_register
& 0xf;
96 uint64_t tsb_base_mask
= (~0x1fffULL
) << tsb_size
;
98 /* move va bits to correct position,
99 * the context bits will be masked out later */
100 uint64_t va
= mmu
->tag_access
>> (3 * page_size
+ 9);
102 /* calculate tsb_base mask and adjust va if split is in use */
105 va
&= ~(1ULL << (13 + tsb_size
));
107 va
|= (1ULL << (13 + tsb_size
));
112 return ((tsb_register
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
115 /* Calculates tag target register value by reordering bits
116 in tag access register */
117 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
119 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
122 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
123 uint64_t tlb_tag
, uint64_t tlb_tte
,
126 target_ulong mask
, size
, va
, offset
;
128 /* flush page range if translation is valid */
129 if (TTE_IS_VALID(tlb
->tte
)) {
130 CPUState
*cs
= env_cpu(env
);
132 size
= 8192ULL << 3 * TTE_PGSIZE(tlb
->tte
);
135 va
= tlb
->tag
& mask
;
137 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
138 tlb_flush_page(cs
, va
+ offset
);
146 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
147 const char *strmmu
, CPUSPARCState
*env1
)
153 int is_demap_context
= (demap_addr
>> 6) & 1;
156 switch ((demap_addr
>> 4) & 3) {
157 case 0: /* primary */
158 context
= env1
->dmmu
.mmu_primary_context
;
160 case 1: /* secondary */
161 context
= env1
->dmmu
.mmu_secondary_context
;
163 case 2: /* nucleus */
166 case 3: /* reserved */
171 for (i
= 0; i
< 64; i
++) {
172 if (TTE_IS_VALID(tlb
[i
].tte
)) {
174 if (is_demap_context
) {
175 /* will remove non-global entries matching context value */
176 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
177 !tlb_compare_context(&tlb
[i
], context
)) {
182 will remove any entry matching VA */
183 mask
= 0xffffffffffffe000ULL
;
184 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
186 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
190 /* entry should be global or matching context value */
191 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
192 !tlb_compare_context(&tlb
[i
], context
)) {
197 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
199 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
206 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState
*env
, uint64_t tag
,
210 if (!(cpu_has_hypervisor(env
) && (tag
& TLB_UST1_IS_SUN4V_BIT
))) {
211 /* is already in the sun4u format */
214 sun4u_tte
= TTE_PA(sun4v_tte
) | (sun4v_tte
& TTE_VALID_BIT
);
215 sun4u_tte
|= (sun4v_tte
& 3ULL) << 61; /* TTE_PGSIZE */
216 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_NFO_BIT_UA2005
, TTE_NFO_BIT
);
217 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_USED_BIT_UA2005
, TTE_USED_BIT
);
218 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_W_OK_BIT_UA2005
, TTE_W_OK_BIT
);
219 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_SIDEEFFECT_BIT_UA2005
,
221 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_PRIV_BIT_UA2005
, TTE_PRIV_BIT
);
222 sun4u_tte
|= CONVERT_BIT(sun4v_tte
, TTE_LOCKED_BIT_UA2005
, TTE_LOCKED_BIT
);
226 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
227 uint64_t tlb_tag
, uint64_t tlb_tte
,
228 const char *strmmu
, CPUSPARCState
*env1
,
231 unsigned int i
, replace_used
;
233 tlb_tte
= sun4v_tte_to_sun4u(env1
, addr
, tlb_tte
);
234 if (cpu_has_hypervisor(env1
)) {
235 uint64_t new_vaddr
= tlb_tag
& ~0x1fffULL
;
236 uint64_t new_size
= 8192ULL << 3 * TTE_PGSIZE(tlb_tte
);
237 uint32_t new_ctx
= tlb_tag
& 0x1fffU
;
238 for (i
= 0; i
< 64; i
++) {
239 uint32_t ctx
= tlb
[i
].tag
& 0x1fffU
;
240 /* check if new mapping overlaps an existing one */
241 if (new_ctx
== ctx
) {
242 uint64_t vaddr
= tlb
[i
].tag
& ~0x1fffULL
;
243 uint64_t size
= 8192ULL << 3 * TTE_PGSIZE(tlb
[i
].tte
);
244 if (new_vaddr
== vaddr
245 || (new_vaddr
< vaddr
+ size
246 && vaddr
< new_vaddr
+ new_size
)) {
247 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i
, vaddr
,
249 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
256 /* Try replacing invalid entry */
257 for (i
= 0; i
< 64; i
++) {
258 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
259 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
261 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
268 /* All entries are valid, try replacing unlocked entry */
270 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
272 /* Used entries are not replaced on first pass */
274 for (i
= 0; i
< 64; i
++) {
275 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
277 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
279 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
280 strmmu
, (replace_used
? "used" : "unused"), i
);
287 /* Now reset used bit and search for unused entries again */
289 for (i
= 0; i
< 64; i
++) {
290 TTE_SET_UNUSED(tlb
[i
].tte
);
295 DPRINTF_MMU("%s lru replacement: no free entries available, "
296 "replacing the last one\n", strmmu
);
298 /* corner case: the last entry is replaced anyway */
299 replace_tlb_entry(&tlb
[63], tlb_tag
, tlb_tte
, env1
);
304 #ifdef TARGET_SPARC64
305 /* returns true if access using this ASI is to have address translated by MMU
306 otherwise access is to raw physical address */
307 /* TODO: check sparc32 bits */
308 static inline int is_translating_asi(int asi
)
310 /* Ultrasparc IIi translating asi
311 - note this list is defined by cpu implementation
328 static inline target_ulong
address_mask(CPUSPARCState
*env1
, target_ulong addr
)
330 if (AM_CHECK(env1
)) {
331 addr
&= 0xffffffffULL
;
336 static inline target_ulong
asi_address_mask(CPUSPARCState
*env
,
337 int asi
, target_ulong addr
)
339 if (is_translating_asi(asi
)) {
340 addr
= address_mask(env
, addr
);
345 #ifndef CONFIG_USER_ONLY
346 static inline void do_check_asi(CPUSPARCState
*env
, int asi
, uintptr_t ra
)
348 /* ASIs >= 0x80 are user mode.
349 * ASIs >= 0x30 are hyper mode (or super if hyper is not available).
350 * ASIs <= 0x2f are super mode.
353 && !cpu_hypervisor_mode(env
)
354 && (!cpu_supervisor_mode(env
)
355 || (asi
>= 0x30 && cpu_has_hypervisor(env
)))) {
356 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, ra
);
359 #endif /* !CONFIG_USER_ONLY */
362 static void do_check_align(CPUSPARCState
*env
, target_ulong addr
,
363 uint32_t align
, uintptr_t ra
)
366 cpu_raise_exception_ra(env
, TT_UNALIGNED
, ra
);
370 void helper_check_align(CPUSPARCState
*env
, target_ulong addr
, uint32_t align
)
372 do_check_align(env
, addr
, align
, GETPC());
375 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
377 static void dump_mxcc(CPUSPARCState
*env
)
379 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
381 env
->mxccdata
[0], env
->mxccdata
[1],
382 env
->mxccdata
[2], env
->mxccdata
[3]);
383 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
385 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
387 env
->mxccregs
[0], env
->mxccregs
[1],
388 env
->mxccregs
[2], env
->mxccregs
[3],
389 env
->mxccregs
[4], env
->mxccregs
[5],
390 env
->mxccregs
[6], env
->mxccregs
[7]);
394 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
395 && defined(DEBUG_ASI)
396 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
401 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
402 addr
, asi
, r1
& 0xff);
405 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
406 addr
, asi
, r1
& 0xffff);
409 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
410 addr
, asi
, r1
& 0xffffffff);
413 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
420 #ifndef CONFIG_USER_ONLY
421 #ifndef TARGET_SPARC64
422 static void sparc_raise_mmu_fault(CPUState
*cs
, hwaddr addr
,
423 bool is_write
, bool is_exec
, int is_asi
,
424 unsigned size
, uintptr_t retaddr
)
426 SPARCCPU
*cpu
= SPARC_CPU(cs
);
427 CPUSPARCState
*env
= &cpu
->env
;
430 #ifdef DEBUG_UNASSIGNED
432 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
433 " asi 0x%02x from " TARGET_FMT_lx
"\n",
434 is_exec
? "exec" : is_write
? "write" : "read", size
,
435 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
437 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
438 " from " TARGET_FMT_lx
"\n",
439 is_exec
? "exec" : is_write
? "write" : "read", size
,
440 size
== 1 ? "" : "s", addr
, env
->pc
);
443 /* Don't overwrite translation and access faults */
444 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
445 if ((fault_type
> 4) || (fault_type
== 0)) {
446 env
->mmuregs
[3] = 0; /* Fault status register */
448 env
->mmuregs
[3] |= 1 << 16;
451 env
->mmuregs
[3] |= 1 << 5;
454 env
->mmuregs
[3] |= 1 << 6;
457 env
->mmuregs
[3] |= 1 << 7;
459 env
->mmuregs
[3] |= (5 << 2) | 2;
460 /* SuperSPARC will never place instruction fault addresses in the FAR */
462 env
->mmuregs
[4] = addr
; /* Fault address register */
465 /* overflow (same type fault was not read before another fault) */
466 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
467 env
->mmuregs
[3] |= 1;
470 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
471 int tt
= is_exec
? TT_CODE_ACCESS
: TT_DATA_ACCESS
;
472 cpu_raise_exception_ra(env
, tt
, retaddr
);
476 * flush neverland mappings created during no-fault mode,
477 * so the sequential MMU faults report proper fault types
479 if (env
->mmuregs
[0] & MMU_NF
) {
484 static void sparc_raise_mmu_fault(CPUState
*cs
, hwaddr addr
,
485 bool is_write
, bool is_exec
, int is_asi
,
486 unsigned size
, uintptr_t retaddr
)
488 SPARCCPU
*cpu
= SPARC_CPU(cs
);
489 CPUSPARCState
*env
= &cpu
->env
;
491 #ifdef DEBUG_UNASSIGNED
492 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
493 "\n", addr
, env
->pc
);
496 if (is_exec
) { /* XXX has_hypervisor */
497 if (env
->lsu
& (IMMU_E
)) {
498 cpu_raise_exception_ra(env
, TT_CODE_ACCESS
, retaddr
);
499 } else if (cpu_has_hypervisor(env
) && !(env
->hpstate
& HS_PRIV
)) {
500 cpu_raise_exception_ra(env
, TT_INSN_REAL_TRANSLATION_MISS
, retaddr
);
503 if (env
->lsu
& (DMMU_E
)) {
504 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, retaddr
);
505 } else if (cpu_has_hypervisor(env
) && !(env
->hpstate
& HS_PRIV
)) {
506 cpu_raise_exception_ra(env
, TT_DATA_REAL_TRANSLATION_MISS
, retaddr
);
513 #ifndef TARGET_SPARC64
514 #ifndef CONFIG_USER_ONLY
517 /* Leon3 cache control */
519 static void leon3_cache_control_st(CPUSPARCState
*env
, target_ulong addr
,
520 uint64_t val
, int size
)
522 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
526 DPRINTF_CACHE_CONTROL("32bits only\n");
531 case 0x00: /* Cache control */
533 /* These values must always be read as zeros */
534 val
&= ~CACHE_CTRL_FD
;
535 val
&= ~CACHE_CTRL_FI
;
536 val
&= ~CACHE_CTRL_IB
;
537 val
&= ~CACHE_CTRL_IP
;
538 val
&= ~CACHE_CTRL_DP
;
540 env
->cache_control
= val
;
542 case 0x04: /* Instruction cache configuration */
543 case 0x08: /* Data cache configuration */
547 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
552 static uint64_t leon3_cache_control_ld(CPUSPARCState
*env
, target_ulong addr
,
558 DPRINTF_CACHE_CONTROL("32bits only\n");
563 case 0x00: /* Cache control */
564 ret
= env
->cache_control
;
567 /* Configuration registers are read and only always keep those
570 case 0x04: /* Instruction cache configuration */
573 case 0x08: /* Data cache configuration */
577 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
580 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
585 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
586 int asi
, uint32_t memop
)
588 int size
= 1 << (memop
& MO_SIZE
);
589 int sign
= memop
& MO_SIGN
;
590 CPUState
*cs
= env_cpu(env
);
592 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
593 uint32_t last_addr
= addr
;
596 do_check_align(env
, addr
, size
- 1, GETPC());
598 case ASI_M_MXCC
: /* SuperSparc MXCC registers, or... */
599 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
601 case 0x00: /* Leon3 Cache Control */
602 case 0x08: /* Leon3 Instruction Cache config */
603 case 0x0C: /* Leon3 Date Cache config */
604 if (env
->def
.features
& CPU_FEATURE_CACHE_CTRL
) {
605 ret
= leon3_cache_control_ld(env
, addr
, size
);
608 case 0x01c00a00: /* MXCC control register */
610 ret
= env
->mxccregs
[3];
612 qemu_log_mask(LOG_UNIMP
,
613 "%08x: unimplemented access size: %d\n", addr
,
617 case 0x01c00a04: /* MXCC control register */
619 ret
= env
->mxccregs
[3];
621 qemu_log_mask(LOG_UNIMP
,
622 "%08x: unimplemented access size: %d\n", addr
,
626 case 0x01c00c00: /* Module reset register */
628 ret
= env
->mxccregs
[5];
629 /* should we do something here? */
631 qemu_log_mask(LOG_UNIMP
,
632 "%08x: unimplemented access size: %d\n", addr
,
636 case 0x01c00f00: /* MBus port address register */
638 ret
= env
->mxccregs
[7];
640 qemu_log_mask(LOG_UNIMP
,
641 "%08x: unimplemented access size: %d\n", addr
,
646 qemu_log_mask(LOG_UNIMP
,
647 "%08x: unimplemented address, size: %d\n", addr
,
651 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
652 "addr = %08x -> ret = %" PRIx64
","
653 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
658 case ASI_M_FLUSH_PROBE
: /* SuperSparc MMU probe */
659 case ASI_LEON_MMUFLUSH
: /* LEON3 MMU probe */
663 mmulev
= (addr
>> 8) & 15;
667 ret
= mmu_probe(env
, addr
, mmulev
);
669 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
673 case ASI_M_MMUREGS
: /* SuperSparc MMU regs */
674 case ASI_LEON_MMUREGS
: /* LEON3 MMU regs */
676 int reg
= (addr
>> 8) & 0x1f;
678 ret
= env
->mmuregs
[reg
];
679 if (reg
== 3) { /* Fault status cleared on read */
681 } else if (reg
== 0x13) { /* Fault status read */
682 ret
= env
->mmuregs
[3];
683 } else if (reg
== 0x14) { /* Fault address read */
684 ret
= env
->mmuregs
[4];
686 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
689 case ASI_M_TLBDIAG
: /* Turbosparc ITLB Diagnostic */
690 case ASI_M_DIAGS
: /* Turbosparc DTLB Diagnostic */
691 case ASI_M_IODIAG
: /* Turbosparc IOTLB Diagnostic */
693 case ASI_KERNELTXT
: /* Supervisor code access */
696 ret
= cpu_ldub_code(env
, addr
);
699 ret
= cpu_lduw_code(env
, addr
);
703 ret
= cpu_ldl_code(env
, addr
);
706 ret
= cpu_ldq_code(env
, addr
);
710 case ASI_M_TXTC_TAG
: /* SparcStation 5 I-cache tag */
711 case ASI_M_TXTC_DATA
: /* SparcStation 5 I-cache data */
712 case ASI_M_DATAC_TAG
: /* SparcStation 5 D-cache tag */
713 case ASI_M_DATAC_DATA
: /* SparcStation 5 D-cache data */
715 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
718 hwaddr access_addr
= (hwaddr
)addr
| ((hwaddr
)(asi
& 0xf) << 32);
722 ret
= address_space_ldub(cs
->as
, access_addr
,
723 MEMTXATTRS_UNSPECIFIED
, &result
);
726 ret
= address_space_lduw(cs
->as
, access_addr
,
727 MEMTXATTRS_UNSPECIFIED
, &result
);
731 ret
= address_space_ldl(cs
->as
, access_addr
,
732 MEMTXATTRS_UNSPECIFIED
, &result
);
735 ret
= address_space_ldq(cs
->as
, access_addr
,
736 MEMTXATTRS_UNSPECIFIED
, &result
);
740 if (result
!= MEMTX_OK
) {
741 sparc_raise_mmu_fault(cs
, access_addr
, false, false, false,
746 case 0x30: /* Turbosparc secondary cache diagnostic */
747 case 0x31: /* Turbosparc RAM snoop */
748 case 0x32: /* Turbosparc page table descriptor diagnostic */
749 case 0x39: /* data cache diagnostic register */
752 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
754 int reg
= (addr
>> 8) & 3;
757 case 0: /* Breakpoint Value (Addr) */
758 ret
= env
->mmubpregs
[reg
];
760 case 1: /* Breakpoint Mask */
761 ret
= env
->mmubpregs
[reg
];
763 case 2: /* Breakpoint Control */
764 ret
= env
->mmubpregs
[reg
];
766 case 3: /* Breakpoint Status */
767 ret
= env
->mmubpregs
[reg
];
768 env
->mmubpregs
[reg
] = 0ULL;
771 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
775 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
776 ret
= env
->mmubpctrv
;
778 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
779 ret
= env
->mmubpctrc
;
781 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
782 ret
= env
->mmubpctrs
;
784 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
785 ret
= env
->mmubpaction
;
787 case ASI_USERTXT
: /* User code access, XXX */
789 sparc_raise_mmu_fault(cs
, addr
, false, false, asi
, size
, GETPC());
793 case ASI_USERDATA
: /* User data access */
794 case ASI_KERNELDATA
: /* Supervisor data access */
795 case ASI_P
: /* Implicit primary context data access (v9 only?) */
796 case ASI_M_BYPASS
: /* MMU passthrough */
797 case ASI_LEON_BYPASS
: /* LEON MMU passthrough */
798 /* These are always handled inline. */
799 g_assert_not_reached();
817 dump_asi("read ", last_addr
, asi
, size
, ret
);
822 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, uint64_t val
,
823 int asi
, uint32_t memop
)
825 int size
= 1 << (memop
& MO_SIZE
);
826 CPUState
*cs
= env_cpu(env
);
828 do_check_align(env
, addr
, size
- 1, GETPC());
830 case ASI_M_MXCC
: /* SuperSparc MXCC registers, or... */
831 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
833 case 0x00: /* Leon3 Cache Control */
834 case 0x08: /* Leon3 Instruction Cache config */
835 case 0x0C: /* Leon3 Date Cache config */
836 if (env
->def
.features
& CPU_FEATURE_CACHE_CTRL
) {
837 leon3_cache_control_st(env
, addr
, val
, size
);
841 case 0x01c00000: /* MXCC stream data register 0 */
843 env
->mxccdata
[0] = val
;
845 qemu_log_mask(LOG_UNIMP
,
846 "%08x: unimplemented access size: %d\n", addr
,
850 case 0x01c00008: /* MXCC stream data register 1 */
852 env
->mxccdata
[1] = val
;
854 qemu_log_mask(LOG_UNIMP
,
855 "%08x: unimplemented access size: %d\n", addr
,
859 case 0x01c00010: /* MXCC stream data register 2 */
861 env
->mxccdata
[2] = val
;
863 qemu_log_mask(LOG_UNIMP
,
864 "%08x: unimplemented access size: %d\n", addr
,
868 case 0x01c00018: /* MXCC stream data register 3 */
870 env
->mxccdata
[3] = val
;
872 qemu_log_mask(LOG_UNIMP
,
873 "%08x: unimplemented access size: %d\n", addr
,
877 case 0x01c00100: /* MXCC stream source */
882 env
->mxccregs
[0] = val
;
884 qemu_log_mask(LOG_UNIMP
,
885 "%08x: unimplemented access size: %d\n", addr
,
889 for (i
= 0; i
< 4; i
++) {
891 hwaddr access_addr
= (env
->mxccregs
[0] & 0xffffffffULL
) + 8 * i
;
893 env
->mxccdata
[i
] = address_space_ldq(cs
->as
,
895 MEMTXATTRS_UNSPECIFIED
,
897 if (result
!= MEMTX_OK
) {
898 /* TODO: investigate whether this is the right behaviour */
899 sparc_raise_mmu_fault(cs
, access_addr
, false, false,
900 false, size
, GETPC());
905 case 0x01c00200: /* MXCC stream destination */
910 env
->mxccregs
[1] = val
;
912 qemu_log_mask(LOG_UNIMP
,
913 "%08x: unimplemented access size: %d\n", addr
,
917 for (i
= 0; i
< 4; i
++) {
919 hwaddr access_addr
= (env
->mxccregs
[1] & 0xffffffffULL
) + 8 * i
;
921 address_space_stq(cs
->as
, access_addr
, env
->mxccdata
[i
],
922 MEMTXATTRS_UNSPECIFIED
, &result
);
924 if (result
!= MEMTX_OK
) {
925 /* TODO: investigate whether this is the right behaviour */
926 sparc_raise_mmu_fault(cs
, access_addr
, true, false,
927 false, size
, GETPC());
932 case 0x01c00a00: /* MXCC control register */
934 env
->mxccregs
[3] = val
;
936 qemu_log_mask(LOG_UNIMP
,
937 "%08x: unimplemented access size: %d\n", addr
,
941 case 0x01c00a04: /* MXCC control register */
943 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
946 qemu_log_mask(LOG_UNIMP
,
947 "%08x: unimplemented access size: %d\n", addr
,
951 case 0x01c00e00: /* MXCC error register */
952 /* writing a 1 bit clears the error */
954 env
->mxccregs
[6] &= ~val
;
956 qemu_log_mask(LOG_UNIMP
,
957 "%08x: unimplemented access size: %d\n", addr
,
961 case 0x01c00f00: /* MBus port address register */
963 env
->mxccregs
[7] = val
;
965 qemu_log_mask(LOG_UNIMP
,
966 "%08x: unimplemented access size: %d\n", addr
,
971 qemu_log_mask(LOG_UNIMP
,
972 "%08x: unimplemented address, size: %d\n", addr
,
976 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
977 asi
, size
, addr
, val
);
982 case ASI_M_FLUSH_PROBE
: /* SuperSparc MMU flush */
983 case ASI_LEON_MMUFLUSH
: /* LEON3 MMU flush */
987 mmulev
= (addr
>> 8) & 15;
988 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
990 case 0: /* flush page */
991 tlb_flush_page(cs
, addr
& 0xfffff000);
993 case 1: /* flush segment (256k) */
994 case 2: /* flush region (16M) */
995 case 3: /* flush context (4G) */
996 case 4: /* flush entire */
1007 case ASI_M_MMUREGS
: /* write MMU regs */
1008 case ASI_LEON_MMUREGS
: /* LEON3 write MMU regs */
1010 int reg
= (addr
>> 8) & 0x1f;
1013 oldreg
= env
->mmuregs
[reg
];
1015 case 0: /* Control Register */
1016 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
1018 /* Mappings generated during no-fault mode
1019 are invalid in normal mode. */
1020 if ((oldreg
^ env
->mmuregs
[reg
])
1021 & (MMU_NF
| env
->def
.mmu_bm
)) {
1025 case 1: /* Context Table Pointer Register */
1026 env
->mmuregs
[reg
] = val
& env
->def
.mmu_ctpr_mask
;
1028 case 2: /* Context Register */
1029 env
->mmuregs
[reg
] = val
& env
->def
.mmu_cxr_mask
;
1030 if (oldreg
!= env
->mmuregs
[reg
]) {
1031 /* we flush when the MMU context changes because
1032 QEMU has no MMU context support */
1036 case 3: /* Synchronous Fault Status Register with Clear */
1037 case 4: /* Synchronous Fault Address Register */
1039 case 0x10: /* TLB Replacement Control Register */
1040 env
->mmuregs
[reg
] = val
& env
->def
.mmu_trcr_mask
;
1042 case 0x13: /* Synchronous Fault Status Register with Read
1044 env
->mmuregs
[3] = val
& env
->def
.mmu_sfsr_mask
;
1046 case 0x14: /* Synchronous Fault Address Register */
1047 env
->mmuregs
[4] = val
;
1050 env
->mmuregs
[reg
] = val
;
1053 if (oldreg
!= env
->mmuregs
[reg
]) {
1054 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1055 reg
, oldreg
, env
->mmuregs
[reg
]);
1062 case ASI_M_TLBDIAG
: /* Turbosparc ITLB Diagnostic */
1063 case ASI_M_DIAGS
: /* Turbosparc DTLB Diagnostic */
1064 case ASI_M_IODIAG
: /* Turbosparc IOTLB Diagnostic */
1066 case ASI_M_TXTC_TAG
: /* I-cache tag */
1067 case ASI_M_TXTC_DATA
: /* I-cache data */
1068 case ASI_M_DATAC_TAG
: /* D-cache tag */
1069 case ASI_M_DATAC_DATA
: /* D-cache data */
1070 case ASI_M_FLUSH_PAGE
: /* I/D-cache flush page */
1071 case ASI_M_FLUSH_SEG
: /* I/D-cache flush segment */
1072 case ASI_M_FLUSH_REGION
: /* I/D-cache flush region */
1073 case ASI_M_FLUSH_CTX
: /* I/D-cache flush context */
1074 case ASI_M_FLUSH_USER
: /* I/D-cache flush user */
1076 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1079 hwaddr access_addr
= (hwaddr
)addr
| ((hwaddr
)(asi
& 0xf) << 32);
1083 address_space_stb(cs
->as
, access_addr
, val
,
1084 MEMTXATTRS_UNSPECIFIED
, &result
);
1087 address_space_stw(cs
->as
, access_addr
, val
,
1088 MEMTXATTRS_UNSPECIFIED
, &result
);
1092 address_space_stl(cs
->as
, access_addr
, val
,
1093 MEMTXATTRS_UNSPECIFIED
, &result
);
1096 address_space_stq(cs
->as
, access_addr
, val
,
1097 MEMTXATTRS_UNSPECIFIED
, &result
);
1100 if (result
!= MEMTX_OK
) {
1101 sparc_raise_mmu_fault(cs
, access_addr
, true, false, false,
1106 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1107 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1108 Turbosparc snoop RAM */
1109 case 0x32: /* store buffer control or Turbosparc page table
1110 descriptor diagnostic */
1111 case 0x36: /* I-cache flash clear */
1112 case 0x37: /* D-cache flash clear */
1114 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1116 int reg
= (addr
>> 8) & 3;
1119 case 0: /* Breakpoint Value (Addr) */
1120 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1122 case 1: /* Breakpoint Mask */
1123 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1125 case 2: /* Breakpoint Control */
1126 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1128 case 3: /* Breakpoint Status */
1129 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1132 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1136 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1137 env
->mmubpctrv
= val
& 0xffffffff;
1139 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1140 env
->mmubpctrc
= val
& 0x3;
1142 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1143 env
->mmubpctrs
= val
& 0x3;
1145 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1146 env
->mmubpaction
= val
& 0x1fff;
1148 case ASI_USERTXT
: /* User code access, XXX */
1149 case ASI_KERNELTXT
: /* Supervisor code access, XXX */
1151 sparc_raise_mmu_fault(cs
, addr
, true, false, asi
, size
, GETPC());
1154 case ASI_USERDATA
: /* User data access */
1155 case ASI_KERNELDATA
: /* Supervisor data access */
1157 case ASI_M_BYPASS
: /* MMU passthrough */
1158 case ASI_LEON_BYPASS
: /* LEON MMU passthrough */
1159 case ASI_M_BCOPY
: /* Block copy, sta access */
1160 case ASI_M_BFILL
: /* Block fill, stda access */
1161 /* These are always handled inline. */
1162 g_assert_not_reached();
1165 dump_asi("write", addr
, asi
, size
, val
);
1169 #endif /* CONFIG_USER_ONLY */
1170 #else /* TARGET_SPARC64 */
1172 #ifdef CONFIG_USER_ONLY
1173 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
1174 int asi
, uint32_t memop
)
1176 int size
= 1 << (memop
& MO_SIZE
);
1177 int sign
= memop
& MO_SIGN
;
1181 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, GETPC());
1183 do_check_align(env
, addr
, size
- 1, GETPC());
1184 addr
= asi_address_mask(env
, asi
, addr
);
1187 case ASI_PNF
: /* Primary no-fault */
1188 case ASI_PNFL
: /* Primary no-fault LE */
1189 case ASI_SNF
: /* Secondary no-fault */
1190 case ASI_SNFL
: /* Secondary no-fault LE */
1191 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1197 ret
= cpu_ldub_data(env
, addr
);
1200 ret
= cpu_lduw_data(env
, addr
);
1203 ret
= cpu_ldl_data(env
, addr
);
1206 ret
= cpu_ldq_data(env
, addr
);
1209 g_assert_not_reached();
1214 case ASI_P
: /* Primary */
1215 case ASI_PL
: /* Primary LE */
1216 case ASI_S
: /* Secondary */
1217 case ASI_SL
: /* Secondary LE */
1218 /* These are always handled inline. */
1219 g_assert_not_reached();
1222 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, GETPC());
1225 /* Convert from little endian */
1227 case ASI_PNFL
: /* Primary no-fault LE */
1228 case ASI_SNFL
: /* Secondary no-fault LE */
1242 /* Convert to signed number */
1249 ret
= (int16_t) ret
;
1252 ret
= (int32_t) ret
;
1257 dump_asi("read", addr
, asi
, size
, ret
);
1262 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1263 int asi
, uint32_t memop
)
1265 int size
= 1 << (memop
& MO_SIZE
);
1267 dump_asi("write", addr
, asi
, size
, val
);
1270 cpu_raise_exception_ra(env
, TT_PRIV_ACT
, GETPC());
1272 do_check_align(env
, addr
, size
- 1, GETPC());
1275 case ASI_P
: /* Primary */
1276 case ASI_PL
: /* Primary LE */
1277 case ASI_S
: /* Secondary */
1278 case ASI_SL
: /* Secondary LE */
1279 /* These are always handled inline. */
1280 g_assert_not_reached();
1282 case ASI_PNF
: /* Primary no-fault, RO */
1283 case ASI_SNF
: /* Secondary no-fault, RO */
1284 case ASI_PNFL
: /* Primary no-fault LE, RO */
1285 case ASI_SNFL
: /* Secondary no-fault LE, RO */
1287 cpu_raise_exception_ra(env
, TT_DATA_ACCESS
, GETPC());
1291 #else /* CONFIG_USER_ONLY */
1293 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
,
1294 int asi
, uint32_t memop
)
1296 int size
= 1 << (memop
& MO_SIZE
);
1297 int sign
= memop
& MO_SIGN
;
1298 CPUState
*cs
= env_cpu(env
);
1300 #if defined(DEBUG_ASI)
1301 target_ulong last_addr
= addr
;
1306 do_check_asi(env
, asi
, GETPC());
1307 do_check_align(env
, addr
, size
- 1, GETPC());
1308 addr
= asi_address_mask(env
, asi
, addr
);
1317 int idx
= (env
->pstate
& PS_PRIV
1318 ? (asi
& 1 ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
)
1319 : (asi
& 1 ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
));
1321 if (cpu_get_phys_page_nofault(env
, addr
, idx
) == -1ULL) {
1323 dump_asi("read ", last_addr
, asi
, size
, ret
);
1325 /* exception_index is set in get_physical_address_data. */
1326 cpu_raise_exception_ra(env
, cs
->exception_index
, GETPC());
1328 oi
= make_memop_idx(memop
, idx
);
1331 ret
= cpu_ldb_mmu(env
, addr
, oi
, GETPC());
1335 ret
= cpu_ldw_le_mmu(env
, addr
, oi
, GETPC());
1337 ret
= cpu_ldw_be_mmu(env
, addr
, oi
, GETPC());
1342 ret
= cpu_ldl_le_mmu(env
, addr
, oi
, GETPC());
1344 ret
= cpu_ldl_be_mmu(env
, addr
, oi
, GETPC());
1349 ret
= cpu_ldq_le_mmu(env
, addr
, oi
, GETPC());
1351 ret
= cpu_ldq_be_mmu(env
, addr
, oi
, GETPC());
1355 g_assert_not_reached();
1360 case ASI_AIUP
: /* As if user primary */
1361 case ASI_AIUS
: /* As if user secondary */
1362 case ASI_AIUPL
: /* As if user primary LE */
1363 case ASI_AIUSL
: /* As if user secondary LE */
1364 case ASI_P
: /* Primary */
1365 case ASI_S
: /* Secondary */
1366 case ASI_PL
: /* Primary LE */
1367 case ASI_SL
: /* Secondary LE */
1368 case ASI_REAL
: /* Bypass */
1369 case ASI_REAL_IO
: /* Bypass, non-cacheable */
1370 case ASI_REAL_L
: /* Bypass LE */
1371 case ASI_REAL_IO_L
: /* Bypass, non-cacheable LE */
1372 case ASI_N
: /* Nucleus */
1373 case ASI_NL
: /* Nucleus Little Endian (LE) */
1374 case ASI_NUCLEUS_QUAD_LDD
: /* Nucleus quad LDD 128 bit atomic */
1375 case ASI_NUCLEUS_QUAD_LDD_L
: /* Nucleus quad LDD 128 bit atomic LE */
1376 case ASI_TWINX_AIUP
: /* As if user primary, twinx */
1377 case ASI_TWINX_AIUS
: /* As if user secondary, twinx */
1378 case ASI_TWINX_REAL
: /* Real address, twinx */
1379 case ASI_TWINX_AIUP_L
: /* As if user primary, twinx, LE */
1380 case ASI_TWINX_AIUS_L
: /* As if user secondary, twinx, LE */
1381 case ASI_TWINX_REAL_L
: /* Real address, twinx, LE */
1382 case ASI_TWINX_N
: /* Nucleus, twinx */
1383 case ASI_TWINX_NL
: /* Nucleus, twinx, LE */
1384 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1385 case ASI_TWINX_P
: /* Primary, twinx */
1386 case ASI_TWINX_PL
: /* Primary, twinx, LE */
1387 case ASI_TWINX_S
: /* Secondary, twinx */
1388 case ASI_TWINX_SL
: /* Secondary, twinx, LE */
1389 /* These are always handled inline. */
1390 g_assert_not_reached();
1392 case ASI_UPA_CONFIG
: /* UPA config */
1395 case ASI_LSU_CONTROL
: /* LSU */
1398 case ASI_IMMU
: /* I-MMU regs */
1400 int reg
= (addr
>> 3) & 0xf;
1403 /* 0x00 I-TSB Tag Target register */
1404 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1407 ret
= env
->immu
.sfsr
;
1409 case 5: /* TSB access */
1410 ret
= env
->immu
.tsb
;
1413 /* 0x30 I-TSB Tag Access register */
1414 ret
= env
->immu
.tag_access
;
1417 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1422 case ASI_IMMU_TSB_8KB_PTR
: /* I-MMU 8k TSB pointer */
1424 /* env->immuregs[5] holds I-MMU TSB register value
1425 env->immuregs[6] holds I-MMU Tag Access register value */
1426 ret
= ultrasparc_tsb_pointer(env
, &env
->immu
, 0);
1429 case ASI_IMMU_TSB_64KB_PTR
: /* I-MMU 64k TSB pointer */
1431 /* env->immuregs[5] holds I-MMU TSB register value
1432 env->immuregs[6] holds I-MMU Tag Access register value */
1433 ret
= ultrasparc_tsb_pointer(env
, &env
->immu
, 1);
1436 case ASI_ITLB_DATA_ACCESS
: /* I-MMU data access */
1438 int reg
= (addr
>> 3) & 0x3f;
1440 ret
= env
->itlb
[reg
].tte
;
1443 case ASI_ITLB_TAG_READ
: /* I-MMU tag read */
1445 int reg
= (addr
>> 3) & 0x3f;
1447 ret
= env
->itlb
[reg
].tag
;
1450 case ASI_DMMU
: /* D-MMU regs */
1452 int reg
= (addr
>> 3) & 0xf;
1455 /* 0x00 D-TSB Tag Target register */
1456 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1458 case 1: /* 0x08 Primary Context */
1459 ret
= env
->dmmu
.mmu_primary_context
;
1461 case 2: /* 0x10 Secondary Context */
1462 ret
= env
->dmmu
.mmu_secondary_context
;
1465 ret
= env
->dmmu
.sfsr
;
1467 case 4: /* 0x20 SFAR */
1468 ret
= env
->dmmu
.sfar
;
1470 case 5: /* 0x28 TSB access */
1471 ret
= env
->dmmu
.tsb
;
1473 case 6: /* 0x30 D-TSB Tag Access register */
1474 ret
= env
->dmmu
.tag_access
;
1477 ret
= env
->dmmu
.virtual_watchpoint
;
1480 ret
= env
->dmmu
.physical_watchpoint
;
1483 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1488 case ASI_DMMU_TSB_8KB_PTR
: /* D-MMU 8k TSB pointer */
1490 /* env->dmmuregs[5] holds D-MMU TSB register value
1491 env->dmmuregs[6] holds D-MMU Tag Access register value */
1492 ret
= ultrasparc_tsb_pointer(env
, &env
->dmmu
, 0);
1495 case ASI_DMMU_TSB_64KB_PTR
: /* D-MMU 64k TSB pointer */
1497 /* env->dmmuregs[5] holds D-MMU TSB register value
1498 env->dmmuregs[6] holds D-MMU Tag Access register value */
1499 ret
= ultrasparc_tsb_pointer(env
, &env
->dmmu
, 1);
1502 case ASI_DTLB_DATA_ACCESS
: /* D-MMU data access */
1504 int reg
= (addr
>> 3) & 0x3f;
1506 ret
= env
->dtlb
[reg
].tte
;
1509 case ASI_DTLB_TAG_READ
: /* D-MMU tag read */
1511 int reg
= (addr
>> 3) & 0x3f;
1513 ret
= env
->dtlb
[reg
].tag
;
1516 case ASI_INTR_DISPATCH_STAT
: /* Interrupt dispatch, RO */
1518 case ASI_INTR_RECEIVE
: /* Interrupt data receive */
1519 ret
= env
->ivec_status
;
1521 case ASI_INTR_R
: /* Incoming interrupt vector, RO */
1523 int reg
= (addr
>> 4) & 0x3;
1525 ret
= env
->ivec_data
[reg
];
1529 case ASI_SCRATCHPAD
: /* UA2005 privileged scratchpad */
1530 if (unlikely((addr
>= 0x20) && (addr
< 0x30))) {
1531 /* Hyperprivileged access only */
1532 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1535 case ASI_HYP_SCRATCHPAD
: /* UA2005 hyperprivileged scratchpad */
1537 unsigned int i
= (addr
>> 3) & 0x7;
1538 ret
= env
->scratch
[i
];
1541 case ASI_MMU
: /* UA2005 Context ID registers */
1542 switch ((addr
>> 3) & 0x3) {
1544 ret
= env
->dmmu
.mmu_primary_context
;
1547 ret
= env
->dmmu
.mmu_secondary_context
;
1550 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1553 case ASI_DCACHE_DATA
: /* D-cache data */
1554 case ASI_DCACHE_TAG
: /* D-cache tag access */
1555 case ASI_ESTATE_ERROR_EN
: /* E-cache error enable */
1556 case ASI_AFSR
: /* E-cache asynchronous fault status */
1557 case ASI_AFAR
: /* E-cache asynchronous fault address */
1558 case ASI_EC_TAG_DATA
: /* E-cache tag data */
1559 case ASI_IC_INSTR
: /* I-cache instruction access */
1560 case ASI_IC_TAG
: /* I-cache tag access */
1561 case ASI_IC_PRE_DECODE
: /* I-cache predecode */
1562 case ASI_IC_NEXT_FIELD
: /* I-cache LRU etc. */
1563 case ASI_EC_W
: /* E-cache tag */
1564 case ASI_EC_R
: /* E-cache tag */
1566 case ASI_DMMU_TSB_DIRECT_PTR
: /* D-MMU data pointer */
1567 case ASI_ITLB_DATA_IN
: /* I-MMU data in, WO */
1568 case ASI_IMMU_DEMAP
: /* I-MMU demap, WO */
1569 case ASI_DTLB_DATA_IN
: /* D-MMU data in, WO */
1570 case ASI_DMMU_DEMAP
: /* D-MMU demap, WO */
1571 case ASI_INTR_W
: /* Interrupt vector, WO */
1573 sparc_raise_mmu_fault(cs
, addr
, false, false, 1, size
, GETPC());
1578 /* Convert to signed number */
1585 ret
= (int16_t) ret
;
1588 ret
= (int32_t) ret
;
1595 dump_asi("read ", last_addr
, asi
, size
, ret
);
1600 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1601 int asi
, uint32_t memop
)
1603 int size
= 1 << (memop
& MO_SIZE
);
1604 CPUState
*cs
= env_cpu(env
);
1607 dump_asi("write", addr
, asi
, size
, val
);
1612 do_check_asi(env
, asi
, GETPC());
1613 do_check_align(env
, addr
, size
- 1, GETPC());
1614 addr
= asi_address_mask(env
, asi
, addr
);
1617 case ASI_AIUP
: /* As if user primary */
1618 case ASI_AIUS
: /* As if user secondary */
1619 case ASI_AIUPL
: /* As if user primary LE */
1620 case ASI_AIUSL
: /* As if user secondary LE */
1621 case ASI_P
: /* Primary */
1622 case ASI_S
: /* Secondary */
1623 case ASI_PL
: /* Primary LE */
1624 case ASI_SL
: /* Secondary LE */
1625 case ASI_REAL
: /* Bypass */
1626 case ASI_REAL_IO
: /* Bypass, non-cacheable */
1627 case ASI_REAL_L
: /* Bypass LE */
1628 case ASI_REAL_IO_L
: /* Bypass, non-cacheable LE */
1629 case ASI_N
: /* Nucleus */
1630 case ASI_NL
: /* Nucleus Little Endian (LE) */
1631 case ASI_NUCLEUS_QUAD_LDD
: /* Nucleus quad LDD 128 bit atomic */
1632 case ASI_NUCLEUS_QUAD_LDD_L
: /* Nucleus quad LDD 128 bit atomic LE */
1633 case ASI_TWINX_AIUP
: /* As if user primary, twinx */
1634 case ASI_TWINX_AIUS
: /* As if user secondary, twinx */
1635 case ASI_TWINX_REAL
: /* Real address, twinx */
1636 case ASI_TWINX_AIUP_L
: /* As if user primary, twinx, LE */
1637 case ASI_TWINX_AIUS_L
: /* As if user secondary, twinx, LE */
1638 case ASI_TWINX_REAL_L
: /* Real address, twinx, LE */
1639 case ASI_TWINX_N
: /* Nucleus, twinx */
1640 case ASI_TWINX_NL
: /* Nucleus, twinx, LE */
1641 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1642 case ASI_TWINX_P
: /* Primary, twinx */
1643 case ASI_TWINX_PL
: /* Primary, twinx, LE */
1644 case ASI_TWINX_S
: /* Secondary, twinx */
1645 case ASI_TWINX_SL
: /* Secondary, twinx, LE */
1646 /* These are always handled inline. */
1647 g_assert_not_reached();
1648 /* these ASIs have different functions on UltraSPARC-IIIi
1649 * and UA2005 CPUs. Use the explicit numbers to avoid confusion
1655 if (cpu_has_hypervisor(env
)) {
1657 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0
1658 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1
1659 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0
1660 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1
1662 int idx
= ((asi
& 2) >> 1) | ((asi
& 8) >> 2);
1663 env
->dmmu
.sun4v_tsb_pointers
[idx
] = val
;
1665 helper_raise_exception(env
, TT_ILL_INSN
);
1670 if (cpu_has_hypervisor(env
)) {
1672 * ASI_DMMU_CTX_ZERO_CONFIG
1673 * ASI_DMMU_CTX_NONZERO_CONFIG
1675 env
->dmmu
.sun4v_ctx_config
[(asi
& 8) >> 3] = val
;
1677 helper_raise_exception(env
, TT_ILL_INSN
);
1684 if (cpu_has_hypervisor(env
)) {
1686 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0
1687 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1
1688 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0
1689 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1
1691 int idx
= ((asi
& 2) >> 1) | ((asi
& 8) >> 2);
1692 env
->immu
.sun4v_tsb_pointers
[idx
] = val
;
1694 helper_raise_exception(env
, TT_ILL_INSN
);
1699 if (cpu_has_hypervisor(env
)) {
1701 * ASI_IMMU_CTX_ZERO_CONFIG
1702 * ASI_IMMU_CTX_NONZERO_CONFIG
1704 env
->immu
.sun4v_ctx_config
[(asi
& 8) >> 3] = val
;
1706 helper_raise_exception(env
, TT_ILL_INSN
);
1709 case ASI_UPA_CONFIG
: /* UPA config */
1712 case ASI_LSU_CONTROL
: /* LSU */
1713 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1715 case ASI_IMMU
: /* I-MMU regs */
1717 int reg
= (addr
>> 3) & 0xf;
1720 oldreg
= env
->immu
.mmuregs
[reg
];
1724 case 1: /* Not in I-MMU */
1728 if ((val
& 1) == 0) {
1729 val
= 0; /* Clear SFSR */
1731 env
->immu
.sfsr
= val
;
1735 case 5: /* TSB access */
1736 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1737 PRIx64
"\n", env
->immu
.tsb
, val
);
1738 env
->immu
.tsb
= val
;
1740 case 6: /* Tag access */
1741 env
->immu
.tag_access
= val
;
1747 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1751 if (oldreg
!= env
->immu
.mmuregs
[reg
]) {
1752 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1753 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1760 case ASI_ITLB_DATA_IN
: /* I-MMU data in */
1761 /* ignore real translation entries */
1762 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1763 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
,
1764 val
, "immu", env
, addr
);
1767 case ASI_ITLB_DATA_ACCESS
: /* I-MMU data access */
1769 /* TODO: auto demap */
1771 unsigned int i
= (addr
>> 3) & 0x3f;
1773 /* ignore real translation entries */
1774 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1775 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
,
1776 sun4v_tte_to_sun4u(env
, addr
, val
), env
);
1779 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1784 case ASI_IMMU_DEMAP
: /* I-MMU demap */
1785 demap_tlb(env
->itlb
, addr
, "immu", env
);
1787 case ASI_DMMU
: /* D-MMU regs */
1789 int reg
= (addr
>> 3) & 0xf;
1792 oldreg
= env
->dmmu
.mmuregs
[reg
];
1798 if ((val
& 1) == 0) {
1799 val
= 0; /* Clear SFSR, Fault address */
1802 env
->dmmu
.sfsr
= val
;
1804 case 1: /* Primary context */
1805 env
->dmmu
.mmu_primary_context
= val
;
1806 /* can be optimized to only flush MMU_USER_IDX
1807 and MMU_KERNEL_IDX entries */
1810 case 2: /* Secondary context */
1811 env
->dmmu
.mmu_secondary_context
= val
;
1812 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1813 and MMU_KERNEL_SECONDARY_IDX entries */
1816 case 5: /* TSB access */
1817 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1818 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1819 env
->dmmu
.tsb
= val
;
1821 case 6: /* Tag access */
1822 env
->dmmu
.tag_access
= val
;
1824 case 7: /* Virtual Watchpoint */
1825 env
->dmmu
.virtual_watchpoint
= val
;
1827 case 8: /* Physical Watchpoint */
1828 env
->dmmu
.physical_watchpoint
= val
;
1831 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1835 if (oldreg
!= env
->dmmu
.mmuregs
[reg
]) {
1836 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1837 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1844 case ASI_DTLB_DATA_IN
: /* D-MMU data in */
1845 /* ignore real translation entries */
1846 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1847 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
,
1848 val
, "dmmu", env
, addr
);
1851 case ASI_DTLB_DATA_ACCESS
: /* D-MMU data access */
1853 unsigned int i
= (addr
>> 3) & 0x3f;
1855 /* ignore real translation entries */
1856 if (!(addr
& TLB_UST1_IS_REAL_BIT
)) {
1857 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
,
1858 sun4v_tte_to_sun4u(env
, addr
, val
), env
);
1861 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
1866 case ASI_DMMU_DEMAP
: /* D-MMU demap */
1867 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
1869 case ASI_INTR_RECEIVE
: /* Interrupt data receive */
1870 env
->ivec_status
= val
& 0x20;
1872 case ASI_SCRATCHPAD
: /* UA2005 privileged scratchpad */
1873 if (unlikely((addr
>= 0x20) && (addr
< 0x30))) {
1874 /* Hyperprivileged access only */
1875 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1878 case ASI_HYP_SCRATCHPAD
: /* UA2005 hyperprivileged scratchpad */
1880 unsigned int i
= (addr
>> 3) & 0x7;
1881 env
->scratch
[i
] = val
;
1884 case ASI_MMU
: /* UA2005 Context ID registers */
1886 switch ((addr
>> 3) & 0x3) {
1888 env
->dmmu
.mmu_primary_context
= val
;
1889 env
->immu
.mmu_primary_context
= val
;
1890 tlb_flush_by_mmuidx(cs
,
1891 (1 << MMU_USER_IDX
) | (1 << MMU_KERNEL_IDX
));
1894 env
->dmmu
.mmu_secondary_context
= val
;
1895 env
->immu
.mmu_secondary_context
= val
;
1896 tlb_flush_by_mmuidx(cs
,
1897 (1 << MMU_USER_SECONDARY_IDX
) |
1898 (1 << MMU_KERNEL_SECONDARY_IDX
));
1901 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1905 case ASI_QUEUE
: /* UA2005 CPU mondo queue */
1906 case ASI_DCACHE_DATA
: /* D-cache data */
1907 case ASI_DCACHE_TAG
: /* D-cache tag access */
1908 case ASI_ESTATE_ERROR_EN
: /* E-cache error enable */
1909 case ASI_AFSR
: /* E-cache asynchronous fault status */
1910 case ASI_AFAR
: /* E-cache asynchronous fault address */
1911 case ASI_EC_TAG_DATA
: /* E-cache tag data */
1912 case ASI_IC_INSTR
: /* I-cache instruction access */
1913 case ASI_IC_TAG
: /* I-cache tag access */
1914 case ASI_IC_PRE_DECODE
: /* I-cache predecode */
1915 case ASI_IC_NEXT_FIELD
: /* I-cache LRU etc. */
1916 case ASI_EC_W
: /* E-cache tag */
1917 case ASI_EC_R
: /* E-cache tag */
1919 case ASI_IMMU_TSB_8KB_PTR
: /* I-MMU 8k TSB pointer, RO */
1920 case ASI_IMMU_TSB_64KB_PTR
: /* I-MMU 64k TSB pointer, RO */
1921 case ASI_ITLB_TAG_READ
: /* I-MMU tag read, RO */
1922 case ASI_DMMU_TSB_8KB_PTR
: /* D-MMU 8k TSB pointer, RO */
1923 case ASI_DMMU_TSB_64KB_PTR
: /* D-MMU 64k TSB pointer, RO */
1924 case ASI_DMMU_TSB_DIRECT_PTR
: /* D-MMU data pointer, RO */
1925 case ASI_DTLB_TAG_READ
: /* D-MMU tag read, RO */
1926 case ASI_INTR_DISPATCH_STAT
: /* Interrupt dispatch, RO */
1927 case ASI_INTR_R
: /* Incoming interrupt vector, RO */
1928 case ASI_PNF
: /* Primary no-fault, RO */
1929 case ASI_SNF
: /* Secondary no-fault, RO */
1930 case ASI_PNFL
: /* Primary no-fault LE, RO */
1931 case ASI_SNFL
: /* Secondary no-fault LE, RO */
1933 sparc_raise_mmu_fault(cs
, addr
, true, false, 1, size
, GETPC());
1937 #endif /* CONFIG_USER_ONLY */
1938 #endif /* TARGET_SPARC64 */
1940 #if !defined(CONFIG_USER_ONLY)
1942 void sparc_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
1943 vaddr addr
, unsigned size
,
1944 MMUAccessType access_type
,
1945 int mmu_idx
, MemTxAttrs attrs
,
1946 MemTxResult response
, uintptr_t retaddr
)
1948 bool is_write
= access_type
== MMU_DATA_STORE
;
1949 bool is_exec
= access_type
== MMU_INST_FETCH
;
1950 bool is_asi
= false;
1952 sparc_raise_mmu_fault(cs
, physaddr
, is_write
, is_exec
,
1953 is_asi
, size
, retaddr
);
1957 #if !defined(CONFIG_USER_ONLY)
1958 void QEMU_NORETURN
sparc_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
1959 MMUAccessType access_type
,
1963 SPARCCPU
*cpu
= SPARC_CPU(cs
);
1964 CPUSPARCState
*env
= &cpu
->env
;
1966 cpu_raise_exception_ra(env
, TT_UNALIGNED
, retaddr
);