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Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into...
[mirror_qemu.git] / target / sparc / ldst_helper.c
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "tcg/tcg.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "asi.h"
28
29 //#define DEBUG_MMU
30 //#define DEBUG_MXCC
31 //#define DEBUG_UNASSIGNED
32 //#define DEBUG_ASI
33 //#define DEBUG_CACHE_CONTROL
34
35 #ifdef DEBUG_MMU
36 #define DPRINTF_MMU(fmt, ...) \
37 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
38 #else
39 #define DPRINTF_MMU(fmt, ...) do {} while (0)
40 #endif
41
42 #ifdef DEBUG_MXCC
43 #define DPRINTF_MXCC(fmt, ...) \
44 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
47 #endif
48
49 #ifdef DEBUG_ASI
50 #define DPRINTF_ASI(fmt, ...) \
51 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
52 #endif
53
54 #ifdef DEBUG_CACHE_CONTROL
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
56 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
57 #else
58 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
59 #endif
60
61 #ifdef TARGET_SPARC64
62 #ifndef TARGET_ABI32
63 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
64 #else
65 #define AM_CHECK(env1) (1)
66 #endif
67 #endif
68
69 #define QT0 (env->qt0)
70 #define QT1 (env->qt1)
71
72 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
73 /* Calculates TSB pointer value for fault page size
74 * UltraSPARC IIi has fixed sizes (8k or 64k) for the page pointers
75 * UA2005 holds the page size configuration in mmu_ctx registers */
76 static uint64_t ultrasparc_tsb_pointer(CPUSPARCState *env,
77 const SparcV9MMU *mmu, const int idx)
78 {
79 uint64_t tsb_register;
80 int page_size;
81 if (cpu_has_hypervisor(env)) {
82 int tsb_index = 0;
83 int ctx = mmu->tag_access & 0x1fffULL;
84 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0];
85 tsb_index = idx;
86 tsb_index |= ctx ? 2 : 0;
87 page_size = idx ? ctx_register >> 8 : ctx_register;
88 page_size &= 7;
89 tsb_register = mmu->sun4v_tsb_pointers[tsb_index];
90 } else {
91 page_size = idx;
92 tsb_register = mmu->tsb;
93 }
94 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
95 int tsb_size = tsb_register & 0xf;
96
97 uint64_t tsb_base_mask = (~0x1fffULL) << tsb_size;
98
99 /* move va bits to correct position,
100 * the context bits will be masked out later */
101 uint64_t va = mmu->tag_access >> (3 * page_size + 9);
102
103 /* calculate tsb_base mask and adjust va if split is in use */
104 if (tsb_split) {
105 if (idx == 0) {
106 va &= ~(1ULL << (13 + tsb_size));
107 } else {
108 va |= (1ULL << (13 + tsb_size));
109 }
110 tsb_base_mask <<= 1;
111 }
112
113 return ((tsb_register & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
114 }
115
116 /* Calculates tag target register value by reordering bits
117 in tag access register */
118 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
119 {
120 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
121 }
122
123 static void replace_tlb_entry(SparcTLBEntry *tlb,
124 uint64_t tlb_tag, uint64_t tlb_tte,
125 CPUSPARCState *env)
126 {
127 target_ulong mask, size, va, offset;
128
129 /* flush page range if translation is valid */
130 if (TTE_IS_VALID(tlb->tte)) {
131 CPUState *cs = env_cpu(env);
132
133 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte);
134 mask = 1ULL + ~size;
135
136 va = tlb->tag & mask;
137
138 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
139 tlb_flush_page(cs, va + offset);
140 }
141 }
142
143 tlb->tag = tlb_tag;
144 tlb->tte = tlb_tte;
145 }
146
147 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
148 const char *strmmu, CPUSPARCState *env1)
149 {
150 unsigned int i;
151 target_ulong mask;
152 uint64_t context;
153
154 int is_demap_context = (demap_addr >> 6) & 1;
155
156 /* demap context */
157 switch ((demap_addr >> 4) & 3) {
158 case 0: /* primary */
159 context = env1->dmmu.mmu_primary_context;
160 break;
161 case 1: /* secondary */
162 context = env1->dmmu.mmu_secondary_context;
163 break;
164 case 2: /* nucleus */
165 context = 0;
166 break;
167 case 3: /* reserved */
168 default:
169 return;
170 }
171
172 for (i = 0; i < 64; i++) {
173 if (TTE_IS_VALID(tlb[i].tte)) {
174
175 if (is_demap_context) {
176 /* will remove non-global entries matching context value */
177 if (TTE_IS_GLOBAL(tlb[i].tte) ||
178 !tlb_compare_context(&tlb[i], context)) {
179 continue;
180 }
181 } else {
182 /* demap page
183 will remove any entry matching VA */
184 mask = 0xffffffffffffe000ULL;
185 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
186
187 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
188 continue;
189 }
190
191 /* entry should be global or matching context value */
192 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
193 !tlb_compare_context(&tlb[i], context)) {
194 continue;
195 }
196 }
197
198 replace_tlb_entry(&tlb[i], 0, 0, env1);
199 #ifdef DEBUG_MMU
200 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
201 dump_mmu(env1);
202 #endif
203 }
204 }
205 }
206
207 static uint64_t sun4v_tte_to_sun4u(CPUSPARCState *env, uint64_t tag,
208 uint64_t sun4v_tte)
209 {
210 uint64_t sun4u_tte;
211 if (!(cpu_has_hypervisor(env) && (tag & TLB_UST1_IS_SUN4V_BIT))) {
212 /* is already in the sun4u format */
213 return sun4v_tte;
214 }
215 sun4u_tte = TTE_PA(sun4v_tte) | (sun4v_tte & TTE_VALID_BIT);
216 sun4u_tte |= (sun4v_tte & 3ULL) << 61; /* TTE_PGSIZE */
217 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_NFO_BIT_UA2005, TTE_NFO_BIT);
218 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_USED_BIT_UA2005, TTE_USED_BIT);
219 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_W_OK_BIT_UA2005, TTE_W_OK_BIT);
220 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_SIDEEFFECT_BIT_UA2005,
221 TTE_SIDEEFFECT_BIT);
222 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_PRIV_BIT_UA2005, TTE_PRIV_BIT);
223 sun4u_tte |= CONVERT_BIT(sun4v_tte, TTE_LOCKED_BIT_UA2005, TTE_LOCKED_BIT);
224 return sun4u_tte;
225 }
226
227 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
228 uint64_t tlb_tag, uint64_t tlb_tte,
229 const char *strmmu, CPUSPARCState *env1,
230 uint64_t addr)
231 {
232 unsigned int i, replace_used;
233
234 tlb_tte = sun4v_tte_to_sun4u(env1, addr, tlb_tte);
235 if (cpu_has_hypervisor(env1)) {
236 uint64_t new_vaddr = tlb_tag & ~0x1fffULL;
237 uint64_t new_size = 8192ULL << 3 * TTE_PGSIZE(tlb_tte);
238 uint32_t new_ctx = tlb_tag & 0x1fffU;
239 for (i = 0; i < 64; i++) {
240 uint32_t ctx = tlb[i].tag & 0x1fffU;
241 /* check if new mapping overlaps an existing one */
242 if (new_ctx == ctx) {
243 uint64_t vaddr = tlb[i].tag & ~0x1fffULL;
244 uint64_t size = 8192ULL << 3 * TTE_PGSIZE(tlb[i].tte);
245 if (new_vaddr == vaddr
246 || (new_vaddr < vaddr + size
247 && vaddr < new_vaddr + new_size)) {
248 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr,
249 new_vaddr);
250 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
251 return;
252 }
253 }
254
255 }
256 }
257 /* Try replacing invalid entry */
258 for (i = 0; i < 64; i++) {
259 if (!TTE_IS_VALID(tlb[i].tte)) {
260 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
261 #ifdef DEBUG_MMU
262 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
263 dump_mmu(env1);
264 #endif
265 return;
266 }
267 }
268
269 /* All entries are valid, try replacing unlocked entry */
270
271 for (replace_used = 0; replace_used < 2; ++replace_used) {
272
273 /* Used entries are not replaced on first pass */
274
275 for (i = 0; i < 64; i++) {
276 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
277
278 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
279 #ifdef DEBUG_MMU
280 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
281 strmmu, (replace_used ? "used" : "unused"), i);
282 dump_mmu(env1);
283 #endif
284 return;
285 }
286 }
287
288 /* Now reset used bit and search for unused entries again */
289
290 for (i = 0; i < 64; i++) {
291 TTE_SET_UNUSED(tlb[i].tte);
292 }
293 }
294
295 #ifdef DEBUG_MMU
296 DPRINTF_MMU("%s lru replacement: no free entries available, "
297 "replacing the last one\n", strmmu);
298 #endif
299 /* corner case: the last entry is replaced anyway */
300 replace_tlb_entry(&tlb[63], tlb_tag, tlb_tte, env1);
301 }
302
303 #endif
304
305 #ifdef TARGET_SPARC64
306 /* returns true if access using this ASI is to have address translated by MMU
307 otherwise access is to raw physical address */
308 /* TODO: check sparc32 bits */
309 static inline int is_translating_asi(int asi)
310 {
311 /* Ultrasparc IIi translating asi
312 - note this list is defined by cpu implementation
313 */
314 switch (asi) {
315 case 0x04 ... 0x11:
316 case 0x16 ... 0x19:
317 case 0x1E ... 0x1F:
318 case 0x24 ... 0x2C:
319 case 0x70 ... 0x73:
320 case 0x78 ... 0x79:
321 case 0x80 ... 0xFF:
322 return 1;
323
324 default:
325 return 0;
326 }
327 }
328
329 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
330 {
331 if (AM_CHECK(env1)) {
332 addr &= 0xffffffffULL;
333 }
334 return addr;
335 }
336
337 static inline target_ulong asi_address_mask(CPUSPARCState *env,
338 int asi, target_ulong addr)
339 {
340 if (is_translating_asi(asi)) {
341 addr = address_mask(env, addr);
342 }
343 return addr;
344 }
345
346 #ifndef CONFIG_USER_ONLY
347 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra)
348 {
349 /* ASIs >= 0x80 are user mode.
350 * ASIs >= 0x30 are hyper mode (or super if hyper is not available).
351 * ASIs <= 0x2f are super mode.
352 */
353 if (asi < 0x80
354 && !cpu_hypervisor_mode(env)
355 && (!cpu_supervisor_mode(env)
356 || (asi >= 0x30 && cpu_has_hypervisor(env)))) {
357 cpu_raise_exception_ra(env, TT_PRIV_ACT, ra);
358 }
359 }
360 #endif /* !CONFIG_USER_ONLY */
361 #endif
362
363 static void do_check_align(CPUSPARCState *env, target_ulong addr,
364 uint32_t align, uintptr_t ra)
365 {
366 if (addr & align) {
367 cpu_raise_exception_ra(env, TT_UNALIGNED, ra);
368 }
369 }
370
371 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
372 {
373 do_check_align(env, addr, align, GETPC());
374 }
375
376 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
377 defined(DEBUG_MXCC)
378 static void dump_mxcc(CPUSPARCState *env)
379 {
380 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
381 "\n",
382 env->mxccdata[0], env->mxccdata[1],
383 env->mxccdata[2], env->mxccdata[3]);
384 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
385 "\n"
386 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
387 "\n",
388 env->mxccregs[0], env->mxccregs[1],
389 env->mxccregs[2], env->mxccregs[3],
390 env->mxccregs[4], env->mxccregs[5],
391 env->mxccregs[6], env->mxccregs[7]);
392 }
393 #endif
394
395 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
396 && defined(DEBUG_ASI)
397 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
398 uint64_t r1)
399 {
400 switch (size) {
401 case 1:
402 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
403 addr, asi, r1 & 0xff);
404 break;
405 case 2:
406 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
407 addr, asi, r1 & 0xffff);
408 break;
409 case 4:
410 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
411 addr, asi, r1 & 0xffffffff);
412 break;
413 case 8:
414 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
415 addr, asi, r1);
416 break;
417 }
418 }
419 #endif
420
421 #ifndef CONFIG_USER_ONLY
422 #ifndef TARGET_SPARC64
423 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
424 bool is_write, bool is_exec, int is_asi,
425 unsigned size, uintptr_t retaddr)
426 {
427 SPARCCPU *cpu = SPARC_CPU(cs);
428 CPUSPARCState *env = &cpu->env;
429 int fault_type;
430
431 #ifdef DEBUG_UNASSIGNED
432 if (is_asi) {
433 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
434 " asi 0x%02x from " TARGET_FMT_lx "\n",
435 is_exec ? "exec" : is_write ? "write" : "read", size,
436 size == 1 ? "" : "s", addr, is_asi, env->pc);
437 } else {
438 printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
439 " from " TARGET_FMT_lx "\n",
440 is_exec ? "exec" : is_write ? "write" : "read", size,
441 size == 1 ? "" : "s", addr, env->pc);
442 }
443 #endif
444 /* Don't overwrite translation and access faults */
445 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
446 if ((fault_type > 4) || (fault_type == 0)) {
447 env->mmuregs[3] = 0; /* Fault status register */
448 if (is_asi) {
449 env->mmuregs[3] |= 1 << 16;
450 }
451 if (env->psrs) {
452 env->mmuregs[3] |= 1 << 5;
453 }
454 if (is_exec) {
455 env->mmuregs[3] |= 1 << 6;
456 }
457 if (is_write) {
458 env->mmuregs[3] |= 1 << 7;
459 }
460 env->mmuregs[3] |= (5 << 2) | 2;
461 /* SuperSPARC will never place instruction fault addresses in the FAR */
462 if (!is_exec) {
463 env->mmuregs[4] = addr; /* Fault address register */
464 }
465 }
466 /* overflow (same type fault was not read before another fault) */
467 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
468 env->mmuregs[3] |= 1;
469 }
470
471 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
472 int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS;
473 cpu_raise_exception_ra(env, tt, retaddr);
474 }
475
476 /*
477 * flush neverland mappings created during no-fault mode,
478 * so the sequential MMU faults report proper fault types
479 */
480 if (env->mmuregs[0] & MMU_NF) {
481 tlb_flush(cs);
482 }
483 }
484 #else
485 static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
486 bool is_write, bool is_exec, int is_asi,
487 unsigned size, uintptr_t retaddr)
488 {
489 SPARCCPU *cpu = SPARC_CPU(cs);
490 CPUSPARCState *env = &cpu->env;
491
492 #ifdef DEBUG_UNASSIGNED
493 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx
494 "\n", addr, env->pc);
495 #endif
496
497 if (is_exec) { /* XXX has_hypervisor */
498 if (env->lsu & (IMMU_E)) {
499 cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr);
500 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
501 cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr);
502 }
503 } else {
504 if (env->lsu & (DMMU_E)) {
505 cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr);
506 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
507 cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr);
508 }
509 }
510 }
511 #endif
512 #endif
513
514 #ifndef TARGET_SPARC64
515 #ifndef CONFIG_USER_ONLY
516
517
518 /* Leon3 cache control */
519
520 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
521 uint64_t val, int size)
522 {
523 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
524 addr, val, size);
525
526 if (size != 4) {
527 DPRINTF_CACHE_CONTROL("32bits only\n");
528 return;
529 }
530
531 switch (addr) {
532 case 0x00: /* Cache control */
533
534 /* These values must always be read as zeros */
535 val &= ~CACHE_CTRL_FD;
536 val &= ~CACHE_CTRL_FI;
537 val &= ~CACHE_CTRL_IB;
538 val &= ~CACHE_CTRL_IP;
539 val &= ~CACHE_CTRL_DP;
540
541 env->cache_control = val;
542 break;
543 case 0x04: /* Instruction cache configuration */
544 case 0x08: /* Data cache configuration */
545 /* Read Only */
546 break;
547 default:
548 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
549 break;
550 };
551 }
552
553 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
554 int size)
555 {
556 uint64_t ret = 0;
557
558 if (size != 4) {
559 DPRINTF_CACHE_CONTROL("32bits only\n");
560 return 0;
561 }
562
563 switch (addr) {
564 case 0x00: /* Cache control */
565 ret = env->cache_control;
566 break;
567
568 /* Configuration registers are read and only always keep those
569 predefined values */
570
571 case 0x04: /* Instruction cache configuration */
572 ret = 0x10220000;
573 break;
574 case 0x08: /* Data cache configuration */
575 ret = 0x18220000;
576 break;
577 default:
578 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
579 break;
580 };
581 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
582 addr, ret, size);
583 return ret;
584 }
585
586 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
587 int asi, uint32_t memop)
588 {
589 int size = 1 << (memop & MO_SIZE);
590 int sign = memop & MO_SIGN;
591 CPUState *cs = env_cpu(env);
592 uint64_t ret = 0;
593 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
594 uint32_t last_addr = addr;
595 #endif
596 MemOpIdx oi;
597
598 do_check_align(env, addr, size - 1, GETPC());
599 switch (asi) {
600 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
601 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
602 switch (addr) {
603 case 0x00: /* Leon3 Cache Control */
604 case 0x08: /* Leon3 Instruction Cache config */
605 case 0x0C: /* Leon3 Date Cache config */
606 if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
607 ret = leon3_cache_control_ld(env, addr, size);
608 }
609 break;
610 case 0x01c00a00: /* MXCC control register */
611 if (size == 8) {
612 ret = env->mxccregs[3];
613 } else {
614 qemu_log_mask(LOG_UNIMP,
615 "%08x: unimplemented access size: %d\n", addr,
616 size);
617 }
618 break;
619 case 0x01c00a04: /* MXCC control register */
620 if (size == 4) {
621 ret = env->mxccregs[3];
622 } else {
623 qemu_log_mask(LOG_UNIMP,
624 "%08x: unimplemented access size: %d\n", addr,
625 size);
626 }
627 break;
628 case 0x01c00c00: /* Module reset register */
629 if (size == 8) {
630 ret = env->mxccregs[5];
631 /* should we do something here? */
632 } else {
633 qemu_log_mask(LOG_UNIMP,
634 "%08x: unimplemented access size: %d\n", addr,
635 size);
636 }
637 break;
638 case 0x01c00f00: /* MBus port address register */
639 if (size == 8) {
640 ret = env->mxccregs[7];
641 } else {
642 qemu_log_mask(LOG_UNIMP,
643 "%08x: unimplemented access size: %d\n", addr,
644 size);
645 }
646 break;
647 default:
648 qemu_log_mask(LOG_UNIMP,
649 "%08x: unimplemented address, size: %d\n", addr,
650 size);
651 break;
652 }
653 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
654 "addr = %08x -> ret = %" PRIx64 ","
655 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
656 #ifdef DEBUG_MXCC
657 dump_mxcc(env);
658 #endif
659 break;
660 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */
661 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */
662 {
663 int mmulev;
664
665 mmulev = (addr >> 8) & 15;
666 if (mmulev > 4) {
667 ret = 0;
668 } else {
669 ret = mmu_probe(env, addr, mmulev);
670 }
671 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
672 addr, mmulev, ret);
673 }
674 break;
675 case ASI_M_MMUREGS: /* SuperSparc MMU regs */
676 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */
677 {
678 int reg = (addr >> 8) & 0x1f;
679
680 ret = env->mmuregs[reg];
681 if (reg == 3) { /* Fault status cleared on read */
682 env->mmuregs[3] = 0;
683 } else if (reg == 0x13) { /* Fault status read */
684 ret = env->mmuregs[3];
685 } else if (reg == 0x14) { /* Fault address read */
686 ret = env->mmuregs[4];
687 }
688 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
689 }
690 break;
691 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
692 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
693 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
694 break;
695 case ASI_KERNELTXT: /* Supervisor code access */
696 oi = make_memop_idx(memop, cpu_mmu_index(env, true));
697 switch (size) {
698 case 1:
699 ret = cpu_ldb_code_mmu(env, addr, oi, GETPC());
700 break;
701 case 2:
702 ret = cpu_ldw_code_mmu(env, addr, oi, GETPC());
703 break;
704 default:
705 case 4:
706 ret = cpu_ldl_code_mmu(env, addr, oi, GETPC());
707 break;
708 case 8:
709 ret = cpu_ldq_code_mmu(env, addr, oi, GETPC());
710 break;
711 }
712 break;
713 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */
714 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */
715 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */
716 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */
717 break;
718 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
719 {
720 MemTxResult result;
721 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32);
722
723 switch (size) {
724 case 1:
725 ret = address_space_ldub(cs->as, access_addr,
726 MEMTXATTRS_UNSPECIFIED, &result);
727 break;
728 case 2:
729 ret = address_space_lduw(cs->as, access_addr,
730 MEMTXATTRS_UNSPECIFIED, &result);
731 break;
732 default:
733 case 4:
734 ret = address_space_ldl(cs->as, access_addr,
735 MEMTXATTRS_UNSPECIFIED, &result);
736 break;
737 case 8:
738 ret = address_space_ldq(cs->as, access_addr,
739 MEMTXATTRS_UNSPECIFIED, &result);
740 break;
741 }
742
743 if (result != MEMTX_OK) {
744 sparc_raise_mmu_fault(cs, access_addr, false, false, false,
745 size, GETPC());
746 }
747 break;
748 }
749 case 0x30: /* Turbosparc secondary cache diagnostic */
750 case 0x31: /* Turbosparc RAM snoop */
751 case 0x32: /* Turbosparc page table descriptor diagnostic */
752 case 0x39: /* data cache diagnostic register */
753 ret = 0;
754 break;
755 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
756 {
757 int reg = (addr >> 8) & 3;
758
759 switch (reg) {
760 case 0: /* Breakpoint Value (Addr) */
761 ret = env->mmubpregs[reg];
762 break;
763 case 1: /* Breakpoint Mask */
764 ret = env->mmubpregs[reg];
765 break;
766 case 2: /* Breakpoint Control */
767 ret = env->mmubpregs[reg];
768 break;
769 case 3: /* Breakpoint Status */
770 ret = env->mmubpregs[reg];
771 env->mmubpregs[reg] = 0ULL;
772 break;
773 }
774 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
775 ret);
776 }
777 break;
778 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
779 ret = env->mmubpctrv;
780 break;
781 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
782 ret = env->mmubpctrc;
783 break;
784 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
785 ret = env->mmubpctrs;
786 break;
787 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
788 ret = env->mmubpaction;
789 break;
790 case ASI_USERTXT: /* User code access, XXX */
791 default:
792 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC());
793 ret = 0;
794 break;
795
796 case ASI_USERDATA: /* User data access */
797 case ASI_KERNELDATA: /* Supervisor data access */
798 case ASI_P: /* Implicit primary context data access (v9 only?) */
799 case ASI_M_BYPASS: /* MMU passthrough */
800 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
801 /* These are always handled inline. */
802 g_assert_not_reached();
803 }
804 if (sign) {
805 switch (size) {
806 case 1:
807 ret = (int8_t) ret;
808 break;
809 case 2:
810 ret = (int16_t) ret;
811 break;
812 case 4:
813 ret = (int32_t) ret;
814 break;
815 default:
816 break;
817 }
818 }
819 #ifdef DEBUG_ASI
820 dump_asi("read ", last_addr, asi, size, ret);
821 #endif
822 return ret;
823 }
824
825 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
826 int asi, uint32_t memop)
827 {
828 int size = 1 << (memop & MO_SIZE);
829 CPUState *cs = env_cpu(env);
830
831 do_check_align(env, addr, size - 1, GETPC());
832 switch (asi) {
833 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
834 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
835 switch (addr) {
836 case 0x00: /* Leon3 Cache Control */
837 case 0x08: /* Leon3 Instruction Cache config */
838 case 0x0C: /* Leon3 Date Cache config */
839 if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
840 leon3_cache_control_st(env, addr, val, size);
841 }
842 break;
843
844 case 0x01c00000: /* MXCC stream data register 0 */
845 if (size == 8) {
846 env->mxccdata[0] = val;
847 } else {
848 qemu_log_mask(LOG_UNIMP,
849 "%08x: unimplemented access size: %d\n", addr,
850 size);
851 }
852 break;
853 case 0x01c00008: /* MXCC stream data register 1 */
854 if (size == 8) {
855 env->mxccdata[1] = val;
856 } else {
857 qemu_log_mask(LOG_UNIMP,
858 "%08x: unimplemented access size: %d\n", addr,
859 size);
860 }
861 break;
862 case 0x01c00010: /* MXCC stream data register 2 */
863 if (size == 8) {
864 env->mxccdata[2] = val;
865 } else {
866 qemu_log_mask(LOG_UNIMP,
867 "%08x: unimplemented access size: %d\n", addr,
868 size);
869 }
870 break;
871 case 0x01c00018: /* MXCC stream data register 3 */
872 if (size == 8) {
873 env->mxccdata[3] = val;
874 } else {
875 qemu_log_mask(LOG_UNIMP,
876 "%08x: unimplemented access size: %d\n", addr,
877 size);
878 }
879 break;
880 case 0x01c00100: /* MXCC stream source */
881 {
882 int i;
883
884 if (size == 8) {
885 env->mxccregs[0] = val;
886 } else {
887 qemu_log_mask(LOG_UNIMP,
888 "%08x: unimplemented access size: %d\n", addr,
889 size);
890 }
891
892 for (i = 0; i < 4; i++) {
893 MemTxResult result;
894 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i;
895
896 env->mxccdata[i] = address_space_ldq(cs->as,
897 access_addr,
898 MEMTXATTRS_UNSPECIFIED,
899 &result);
900 if (result != MEMTX_OK) {
901 /* TODO: investigate whether this is the right behaviour */
902 sparc_raise_mmu_fault(cs, access_addr, false, false,
903 false, size, GETPC());
904 }
905 }
906 break;
907 }
908 case 0x01c00200: /* MXCC stream destination */
909 {
910 int i;
911
912 if (size == 8) {
913 env->mxccregs[1] = val;
914 } else {
915 qemu_log_mask(LOG_UNIMP,
916 "%08x: unimplemented access size: %d\n", addr,
917 size);
918 }
919
920 for (i = 0; i < 4; i++) {
921 MemTxResult result;
922 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i;
923
924 address_space_stq(cs->as, access_addr, env->mxccdata[i],
925 MEMTXATTRS_UNSPECIFIED, &result);
926
927 if (result != MEMTX_OK) {
928 /* TODO: investigate whether this is the right behaviour */
929 sparc_raise_mmu_fault(cs, access_addr, true, false,
930 false, size, GETPC());
931 }
932 }
933 break;
934 }
935 case 0x01c00a00: /* MXCC control register */
936 if (size == 8) {
937 env->mxccregs[3] = val;
938 } else {
939 qemu_log_mask(LOG_UNIMP,
940 "%08x: unimplemented access size: %d\n", addr,
941 size);
942 }
943 break;
944 case 0x01c00a04: /* MXCC control register */
945 if (size == 4) {
946 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
947 | val;
948 } else {
949 qemu_log_mask(LOG_UNIMP,
950 "%08x: unimplemented access size: %d\n", addr,
951 size);
952 }
953 break;
954 case 0x01c00e00: /* MXCC error register */
955 /* writing a 1 bit clears the error */
956 if (size == 8) {
957 env->mxccregs[6] &= ~val;
958 } else {
959 qemu_log_mask(LOG_UNIMP,
960 "%08x: unimplemented access size: %d\n", addr,
961 size);
962 }
963 break;
964 case 0x01c00f00: /* MBus port address register */
965 if (size == 8) {
966 env->mxccregs[7] = val;
967 } else {
968 qemu_log_mask(LOG_UNIMP,
969 "%08x: unimplemented access size: %d\n", addr,
970 size);
971 }
972 break;
973 default:
974 qemu_log_mask(LOG_UNIMP,
975 "%08x: unimplemented address, size: %d\n", addr,
976 size);
977 break;
978 }
979 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
980 asi, size, addr, val);
981 #ifdef DEBUG_MXCC
982 dump_mxcc(env);
983 #endif
984 break;
985 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */
986 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */
987 {
988 int mmulev;
989
990 mmulev = (addr >> 8) & 15;
991 DPRINTF_MMU("mmu flush level %d\n", mmulev);
992 switch (mmulev) {
993 case 0: /* flush page */
994 tlb_flush_page(cs, addr & 0xfffff000);
995 break;
996 case 1: /* flush segment (256k) */
997 case 2: /* flush region (16M) */
998 case 3: /* flush context (4G) */
999 case 4: /* flush entire */
1000 tlb_flush(cs);
1001 break;
1002 default:
1003 break;
1004 }
1005 #ifdef DEBUG_MMU
1006 dump_mmu(env);
1007 #endif
1008 }
1009 break;
1010 case ASI_M_MMUREGS: /* write MMU regs */
1011 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */
1012 {
1013 int reg = (addr >> 8) & 0x1f;
1014 uint32_t oldreg;
1015
1016 oldreg = env->mmuregs[reg];
1017 switch (reg) {
1018 case 0: /* Control Register */
1019 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1020 (val & 0x00ffffff);
1021 /* Mappings generated during no-fault mode
1022 are invalid in normal mode. */
1023 if ((oldreg ^ env->mmuregs[reg])
1024 & (MMU_NF | env->def.mmu_bm)) {
1025 tlb_flush(cs);
1026 }
1027 break;
1028 case 1: /* Context Table Pointer Register */
1029 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask;
1030 break;
1031 case 2: /* Context Register */
1032 env->mmuregs[reg] = val & env->def.mmu_cxr_mask;
1033 if (oldreg != env->mmuregs[reg]) {
1034 /* we flush when the MMU context changes because
1035 QEMU has no MMU context support */
1036 tlb_flush(cs);
1037 }
1038 break;
1039 case 3: /* Synchronous Fault Status Register with Clear */
1040 case 4: /* Synchronous Fault Address Register */
1041 break;
1042 case 0x10: /* TLB Replacement Control Register */
1043 env->mmuregs[reg] = val & env->def.mmu_trcr_mask;
1044 break;
1045 case 0x13: /* Synchronous Fault Status Register with Read
1046 and Clear */
1047 env->mmuregs[3] = val & env->def.mmu_sfsr_mask;
1048 break;
1049 case 0x14: /* Synchronous Fault Address Register */
1050 env->mmuregs[4] = val;
1051 break;
1052 default:
1053 env->mmuregs[reg] = val;
1054 break;
1055 }
1056 if (oldreg != env->mmuregs[reg]) {
1057 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1058 reg, oldreg, env->mmuregs[reg]);
1059 }
1060 #ifdef DEBUG_MMU
1061 dump_mmu(env);
1062 #endif
1063 }
1064 break;
1065 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
1066 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
1067 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
1068 break;
1069 case ASI_M_TXTC_TAG: /* I-cache tag */
1070 case ASI_M_TXTC_DATA: /* I-cache data */
1071 case ASI_M_DATAC_TAG: /* D-cache tag */
1072 case ASI_M_DATAC_DATA: /* D-cache data */
1073 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */
1074 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */
1075 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */
1076 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */
1077 case ASI_M_FLUSH_USER: /* I/D-cache flush user */
1078 break;
1079 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1080 {
1081 MemTxResult result;
1082 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32);
1083
1084 switch (size) {
1085 case 1:
1086 address_space_stb(cs->as, access_addr, val,
1087 MEMTXATTRS_UNSPECIFIED, &result);
1088 break;
1089 case 2:
1090 address_space_stw(cs->as, access_addr, val,
1091 MEMTXATTRS_UNSPECIFIED, &result);
1092 break;
1093 case 4:
1094 default:
1095 address_space_stl(cs->as, access_addr, val,
1096 MEMTXATTRS_UNSPECIFIED, &result);
1097 break;
1098 case 8:
1099 address_space_stq(cs->as, access_addr, val,
1100 MEMTXATTRS_UNSPECIFIED, &result);
1101 break;
1102 }
1103 if (result != MEMTX_OK) {
1104 sparc_raise_mmu_fault(cs, access_addr, true, false, false,
1105 size, GETPC());
1106 }
1107 }
1108 break;
1109 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1110 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1111 Turbosparc snoop RAM */
1112 case 0x32: /* store buffer control or Turbosparc page table
1113 descriptor diagnostic */
1114 case 0x36: /* I-cache flash clear */
1115 case 0x37: /* D-cache flash clear */
1116 break;
1117 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1118 {
1119 int reg = (addr >> 8) & 3;
1120
1121 switch (reg) {
1122 case 0: /* Breakpoint Value (Addr) */
1123 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1124 break;
1125 case 1: /* Breakpoint Mask */
1126 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1127 break;
1128 case 2: /* Breakpoint Control */
1129 env->mmubpregs[reg] = (val & 0x7fULL);
1130 break;
1131 case 3: /* Breakpoint Status */
1132 env->mmubpregs[reg] = (val & 0xfULL);
1133 break;
1134 }
1135 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1136 env->mmuregs[reg]);
1137 }
1138 break;
1139 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1140 env->mmubpctrv = val & 0xffffffff;
1141 break;
1142 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1143 env->mmubpctrc = val & 0x3;
1144 break;
1145 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1146 env->mmubpctrs = val & 0x3;
1147 break;
1148 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1149 env->mmubpaction = val & 0x1fff;
1150 break;
1151 case ASI_USERTXT: /* User code access, XXX */
1152 case ASI_KERNELTXT: /* Supervisor code access, XXX */
1153 default:
1154 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC());
1155 break;
1156
1157 case ASI_USERDATA: /* User data access */
1158 case ASI_KERNELDATA: /* Supervisor data access */
1159 case ASI_P:
1160 case ASI_M_BYPASS: /* MMU passthrough */
1161 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
1162 case ASI_M_BCOPY: /* Block copy, sta access */
1163 case ASI_M_BFILL: /* Block fill, stda access */
1164 /* These are always handled inline. */
1165 g_assert_not_reached();
1166 }
1167 #ifdef DEBUG_ASI
1168 dump_asi("write", addr, asi, size, val);
1169 #endif
1170 }
1171
1172 #endif /* CONFIG_USER_ONLY */
1173 #else /* TARGET_SPARC64 */
1174
1175 #ifdef CONFIG_USER_ONLY
1176 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
1177 int asi, uint32_t memop)
1178 {
1179 int size = 1 << (memop & MO_SIZE);
1180 int sign = memop & MO_SIGN;
1181 uint64_t ret = 0;
1182
1183 if (asi < 0x80) {
1184 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
1185 }
1186 do_check_align(env, addr, size - 1, GETPC());
1187 addr = asi_address_mask(env, asi, addr);
1188
1189 switch (asi) {
1190 case ASI_PNF: /* Primary no-fault */
1191 case ASI_PNFL: /* Primary no-fault LE */
1192 case ASI_SNF: /* Secondary no-fault */
1193 case ASI_SNFL: /* Secondary no-fault LE */
1194 if (!page_check_range(addr, size, PAGE_READ)) {
1195 ret = 0;
1196 break;
1197 }
1198 switch (size) {
1199 case 1:
1200 ret = cpu_ldub_data(env, addr);
1201 break;
1202 case 2:
1203 ret = cpu_lduw_data(env, addr);
1204 break;
1205 case 4:
1206 ret = cpu_ldl_data(env, addr);
1207 break;
1208 case 8:
1209 ret = cpu_ldq_data(env, addr);
1210 break;
1211 default:
1212 g_assert_not_reached();
1213 }
1214 break;
1215 break;
1216
1217 case ASI_P: /* Primary */
1218 case ASI_PL: /* Primary LE */
1219 case ASI_S: /* Secondary */
1220 case ASI_SL: /* Secondary LE */
1221 /* These are always handled inline. */
1222 g_assert_not_reached();
1223
1224 default:
1225 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
1226 }
1227
1228 /* Convert from little endian */
1229 switch (asi) {
1230 case ASI_PNFL: /* Primary no-fault LE */
1231 case ASI_SNFL: /* Secondary no-fault LE */
1232 switch (size) {
1233 case 2:
1234 ret = bswap16(ret);
1235 break;
1236 case 4:
1237 ret = bswap32(ret);
1238 break;
1239 case 8:
1240 ret = bswap64(ret);
1241 break;
1242 }
1243 }
1244
1245 /* Convert to signed number */
1246 if (sign) {
1247 switch (size) {
1248 case 1:
1249 ret = (int8_t) ret;
1250 break;
1251 case 2:
1252 ret = (int16_t) ret;
1253 break;
1254 case 4:
1255 ret = (int32_t) ret;
1256 break;
1257 }
1258 }
1259 #ifdef DEBUG_ASI
1260 dump_asi("read", addr, asi, size, ret);
1261 #endif
1262 return ret;
1263 }
1264
1265 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1266 int asi, uint32_t memop)
1267 {
1268 int size = 1 << (memop & MO_SIZE);
1269 #ifdef DEBUG_ASI
1270 dump_asi("write", addr, asi, size, val);
1271 #endif
1272 if (asi < 0x80) {
1273 cpu_raise_exception_ra(env, TT_PRIV_ACT, GETPC());
1274 }
1275 do_check_align(env, addr, size - 1, GETPC());
1276
1277 switch (asi) {
1278 case ASI_P: /* Primary */
1279 case ASI_PL: /* Primary LE */
1280 case ASI_S: /* Secondary */
1281 case ASI_SL: /* Secondary LE */
1282 /* These are always handled inline. */
1283 g_assert_not_reached();
1284
1285 case ASI_PNF: /* Primary no-fault, RO */
1286 case ASI_SNF: /* Secondary no-fault, RO */
1287 case ASI_PNFL: /* Primary no-fault LE, RO */
1288 case ASI_SNFL: /* Secondary no-fault LE, RO */
1289 default:
1290 cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
1291 }
1292 }
1293
1294 #else /* CONFIG_USER_ONLY */
1295
1296 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
1297 int asi, uint32_t memop)
1298 {
1299 int size = 1 << (memop & MO_SIZE);
1300 int sign = memop & MO_SIGN;
1301 CPUState *cs = env_cpu(env);
1302 uint64_t ret = 0;
1303 #if defined(DEBUG_ASI)
1304 target_ulong last_addr = addr;
1305 #endif
1306
1307 asi &= 0xff;
1308
1309 do_check_asi(env, asi, GETPC());
1310 do_check_align(env, addr, size - 1, GETPC());
1311 addr = asi_address_mask(env, asi, addr);
1312
1313 switch (asi) {
1314 case ASI_PNF:
1315 case ASI_PNFL:
1316 case ASI_SNF:
1317 case ASI_SNFL:
1318 {
1319 MemOpIdx oi;
1320 int idx = (env->pstate & PS_PRIV
1321 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX)
1322 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX));
1323
1324 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) {
1325 #ifdef DEBUG_ASI
1326 dump_asi("read ", last_addr, asi, size, ret);
1327 #endif
1328 /* exception_index is set in get_physical_address_data. */
1329 cpu_raise_exception_ra(env, cs->exception_index, GETPC());
1330 }
1331 oi = make_memop_idx(memop, idx);
1332 switch (size) {
1333 case 1:
1334 ret = cpu_ldb_mmu(env, addr, oi, GETPC());
1335 break;
1336 case 2:
1337 ret = cpu_ldw_mmu(env, addr, oi, GETPC());
1338 break;
1339 case 4:
1340 ret = cpu_ldl_mmu(env, addr, oi, GETPC());
1341 break;
1342 case 8:
1343 ret = cpu_ldq_mmu(env, addr, oi, GETPC());
1344 break;
1345 default:
1346 g_assert_not_reached();
1347 }
1348 }
1349 break;
1350
1351 case ASI_AIUP: /* As if user primary */
1352 case ASI_AIUS: /* As if user secondary */
1353 case ASI_AIUPL: /* As if user primary LE */
1354 case ASI_AIUSL: /* As if user secondary LE */
1355 case ASI_P: /* Primary */
1356 case ASI_S: /* Secondary */
1357 case ASI_PL: /* Primary LE */
1358 case ASI_SL: /* Secondary LE */
1359 case ASI_REAL: /* Bypass */
1360 case ASI_REAL_IO: /* Bypass, non-cacheable */
1361 case ASI_REAL_L: /* Bypass LE */
1362 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1363 case ASI_N: /* Nucleus */
1364 case ASI_NL: /* Nucleus Little Endian (LE) */
1365 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1366 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1367 case ASI_TWINX_AIUP: /* As if user primary, twinx */
1368 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
1369 case ASI_TWINX_REAL: /* Real address, twinx */
1370 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
1371 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
1372 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1373 case ASI_TWINX_N: /* Nucleus, twinx */
1374 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
1375 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1376 case ASI_TWINX_P: /* Primary, twinx */
1377 case ASI_TWINX_PL: /* Primary, twinx, LE */
1378 case ASI_TWINX_S: /* Secondary, twinx */
1379 case ASI_TWINX_SL: /* Secondary, twinx, LE */
1380 /* These are always handled inline. */
1381 g_assert_not_reached();
1382
1383 case ASI_UPA_CONFIG: /* UPA config */
1384 /* XXX */
1385 break;
1386 case ASI_LSU_CONTROL: /* LSU */
1387 ret = env->lsu;
1388 break;
1389 case ASI_IMMU: /* I-MMU regs */
1390 {
1391 int reg = (addr >> 3) & 0xf;
1392 switch (reg) {
1393 case 0:
1394 /* 0x00 I-TSB Tag Target register */
1395 ret = ultrasparc_tag_target(env->immu.tag_access);
1396 break;
1397 case 3: /* SFSR */
1398 ret = env->immu.sfsr;
1399 break;
1400 case 5: /* TSB access */
1401 ret = env->immu.tsb;
1402 break;
1403 case 6:
1404 /* 0x30 I-TSB Tag Access register */
1405 ret = env->immu.tag_access;
1406 break;
1407 default:
1408 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1409 ret = 0;
1410 }
1411 break;
1412 }
1413 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */
1414 {
1415 /* env->immuregs[5] holds I-MMU TSB register value
1416 env->immuregs[6] holds I-MMU Tag Access register value */
1417 ret = ultrasparc_tsb_pointer(env, &env->immu, 0);
1418 break;
1419 }
1420 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */
1421 {
1422 /* env->immuregs[5] holds I-MMU TSB register value
1423 env->immuregs[6] holds I-MMU Tag Access register value */
1424 ret = ultrasparc_tsb_pointer(env, &env->immu, 1);
1425 break;
1426 }
1427 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1428 {
1429 int reg = (addr >> 3) & 0x3f;
1430
1431 ret = env->itlb[reg].tte;
1432 break;
1433 }
1434 case ASI_ITLB_TAG_READ: /* I-MMU tag read */
1435 {
1436 int reg = (addr >> 3) & 0x3f;
1437
1438 ret = env->itlb[reg].tag;
1439 break;
1440 }
1441 case ASI_DMMU: /* D-MMU regs */
1442 {
1443 int reg = (addr >> 3) & 0xf;
1444 switch (reg) {
1445 case 0:
1446 /* 0x00 D-TSB Tag Target register */
1447 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1448 break;
1449 case 1: /* 0x08 Primary Context */
1450 ret = env->dmmu.mmu_primary_context;
1451 break;
1452 case 2: /* 0x10 Secondary Context */
1453 ret = env->dmmu.mmu_secondary_context;
1454 break;
1455 case 3: /* SFSR */
1456 ret = env->dmmu.sfsr;
1457 break;
1458 case 4: /* 0x20 SFAR */
1459 ret = env->dmmu.sfar;
1460 break;
1461 case 5: /* 0x28 TSB access */
1462 ret = env->dmmu.tsb;
1463 break;
1464 case 6: /* 0x30 D-TSB Tag Access register */
1465 ret = env->dmmu.tag_access;
1466 break;
1467 case 7:
1468 ret = env->dmmu.virtual_watchpoint;
1469 break;
1470 case 8:
1471 ret = env->dmmu.physical_watchpoint;
1472 break;
1473 default:
1474 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1475 ret = 0;
1476 }
1477 break;
1478 }
1479 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */
1480 {
1481 /* env->dmmuregs[5] holds D-MMU TSB register value
1482 env->dmmuregs[6] holds D-MMU Tag Access register value */
1483 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0);
1484 break;
1485 }
1486 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */
1487 {
1488 /* env->dmmuregs[5] holds D-MMU TSB register value
1489 env->dmmuregs[6] holds D-MMU Tag Access register value */
1490 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1);
1491 break;
1492 }
1493 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1494 {
1495 int reg = (addr >> 3) & 0x3f;
1496
1497 ret = env->dtlb[reg].tte;
1498 break;
1499 }
1500 case ASI_DTLB_TAG_READ: /* D-MMU tag read */
1501 {
1502 int reg = (addr >> 3) & 0x3f;
1503
1504 ret = env->dtlb[reg].tag;
1505 break;
1506 }
1507 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
1508 break;
1509 case ASI_INTR_RECEIVE: /* Interrupt data receive */
1510 ret = env->ivec_status;
1511 break;
1512 case ASI_INTR_R: /* Incoming interrupt vector, RO */
1513 {
1514 int reg = (addr >> 4) & 0x3;
1515 if (reg < 3) {
1516 ret = env->ivec_data[reg];
1517 }
1518 break;
1519 }
1520 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
1521 if (unlikely((addr >= 0x20) && (addr < 0x30))) {
1522 /* Hyperprivileged access only */
1523 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1524 }
1525 /* fall through */
1526 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
1527 {
1528 unsigned int i = (addr >> 3) & 0x7;
1529 ret = env->scratch[i];
1530 break;
1531 }
1532 case ASI_MMU: /* UA2005 Context ID registers */
1533 switch ((addr >> 3) & 0x3) {
1534 case 1:
1535 ret = env->dmmu.mmu_primary_context;
1536 break;
1537 case 2:
1538 ret = env->dmmu.mmu_secondary_context;
1539 break;
1540 default:
1541 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1542 }
1543 break;
1544 case ASI_DCACHE_DATA: /* D-cache data */
1545 case ASI_DCACHE_TAG: /* D-cache tag access */
1546 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1547 case ASI_AFSR: /* E-cache asynchronous fault status */
1548 case ASI_AFAR: /* E-cache asynchronous fault address */
1549 case ASI_EC_TAG_DATA: /* E-cache tag data */
1550 case ASI_IC_INSTR: /* I-cache instruction access */
1551 case ASI_IC_TAG: /* I-cache tag access */
1552 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1553 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1554 case ASI_EC_W: /* E-cache tag */
1555 case ASI_EC_R: /* E-cache tag */
1556 break;
1557 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */
1558 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */
1559 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */
1560 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */
1561 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */
1562 case ASI_INTR_W: /* Interrupt vector, WO */
1563 default:
1564 sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC());
1565 ret = 0;
1566 break;
1567 }
1568
1569 /* Convert to signed number */
1570 if (sign) {
1571 switch (size) {
1572 case 1:
1573 ret = (int8_t) ret;
1574 break;
1575 case 2:
1576 ret = (int16_t) ret;
1577 break;
1578 case 4:
1579 ret = (int32_t) ret;
1580 break;
1581 default:
1582 break;
1583 }
1584 }
1585 #ifdef DEBUG_ASI
1586 dump_asi("read ", last_addr, asi, size, ret);
1587 #endif
1588 return ret;
1589 }
1590
1591 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1592 int asi, uint32_t memop)
1593 {
1594 int size = 1 << (memop & MO_SIZE);
1595 CPUState *cs = env_cpu(env);
1596
1597 #ifdef DEBUG_ASI
1598 dump_asi("write", addr, asi, size, val);
1599 #endif
1600
1601 asi &= 0xff;
1602
1603 do_check_asi(env, asi, GETPC());
1604 do_check_align(env, addr, size - 1, GETPC());
1605 addr = asi_address_mask(env, asi, addr);
1606
1607 switch (asi) {
1608 case ASI_AIUP: /* As if user primary */
1609 case ASI_AIUS: /* As if user secondary */
1610 case ASI_AIUPL: /* As if user primary LE */
1611 case ASI_AIUSL: /* As if user secondary LE */
1612 case ASI_P: /* Primary */
1613 case ASI_S: /* Secondary */
1614 case ASI_PL: /* Primary LE */
1615 case ASI_SL: /* Secondary LE */
1616 case ASI_REAL: /* Bypass */
1617 case ASI_REAL_IO: /* Bypass, non-cacheable */
1618 case ASI_REAL_L: /* Bypass LE */
1619 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1620 case ASI_N: /* Nucleus */
1621 case ASI_NL: /* Nucleus Little Endian (LE) */
1622 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1623 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1624 case ASI_TWINX_AIUP: /* As if user primary, twinx */
1625 case ASI_TWINX_AIUS: /* As if user secondary, twinx */
1626 case ASI_TWINX_REAL: /* Real address, twinx */
1627 case ASI_TWINX_AIUP_L: /* As if user primary, twinx, LE */
1628 case ASI_TWINX_AIUS_L: /* As if user secondary, twinx, LE */
1629 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
1630 case ASI_TWINX_N: /* Nucleus, twinx */
1631 case ASI_TWINX_NL: /* Nucleus, twinx, LE */
1632 /* ??? From the UA2011 document; overlaps BLK_INIT_QUAD_LDD_* */
1633 case ASI_TWINX_P: /* Primary, twinx */
1634 case ASI_TWINX_PL: /* Primary, twinx, LE */
1635 case ASI_TWINX_S: /* Secondary, twinx */
1636 case ASI_TWINX_SL: /* Secondary, twinx, LE */
1637 /* These are always handled inline. */
1638 g_assert_not_reached();
1639 /* these ASIs have different functions on UltraSPARC-IIIi
1640 * and UA2005 CPUs. Use the explicit numbers to avoid confusion
1641 */
1642 case 0x31:
1643 case 0x32:
1644 case 0x39:
1645 case 0x3a:
1646 if (cpu_has_hypervisor(env)) {
1647 /* UA2005
1648 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS0
1649 * ASI_DMMU_CTX_ZERO_TSB_BASE_PS1
1650 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS0
1651 * ASI_DMMU_CTX_NONZERO_TSB_BASE_PS1
1652 */
1653 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
1654 env->dmmu.sun4v_tsb_pointers[idx] = val;
1655 } else {
1656 helper_raise_exception(env, TT_ILL_INSN);
1657 }
1658 break;
1659 case 0x33:
1660 case 0x3b:
1661 if (cpu_has_hypervisor(env)) {
1662 /* UA2005
1663 * ASI_DMMU_CTX_ZERO_CONFIG
1664 * ASI_DMMU_CTX_NONZERO_CONFIG
1665 */
1666 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val;
1667 } else {
1668 helper_raise_exception(env, TT_ILL_INSN);
1669 }
1670 break;
1671 case 0x35:
1672 case 0x36:
1673 case 0x3d:
1674 case 0x3e:
1675 if (cpu_has_hypervisor(env)) {
1676 /* UA2005
1677 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS0
1678 * ASI_IMMU_CTX_ZERO_TSB_BASE_PS1
1679 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS0
1680 * ASI_IMMU_CTX_NONZERO_TSB_BASE_PS1
1681 */
1682 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2);
1683 env->immu.sun4v_tsb_pointers[idx] = val;
1684 } else {
1685 helper_raise_exception(env, TT_ILL_INSN);
1686 }
1687 break;
1688 case 0x37:
1689 case 0x3f:
1690 if (cpu_has_hypervisor(env)) {
1691 /* UA2005
1692 * ASI_IMMU_CTX_ZERO_CONFIG
1693 * ASI_IMMU_CTX_NONZERO_CONFIG
1694 */
1695 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val;
1696 } else {
1697 helper_raise_exception(env, TT_ILL_INSN);
1698 }
1699 break;
1700 case ASI_UPA_CONFIG: /* UPA config */
1701 /* XXX */
1702 return;
1703 case ASI_LSU_CONTROL: /* LSU */
1704 env->lsu = val & (DMMU_E | IMMU_E);
1705 return;
1706 case ASI_IMMU: /* I-MMU regs */
1707 {
1708 int reg = (addr >> 3) & 0xf;
1709 uint64_t oldreg;
1710
1711 oldreg = env->immu.mmuregs[reg];
1712 switch (reg) {
1713 case 0: /* RO */
1714 return;
1715 case 1: /* Not in I-MMU */
1716 case 2:
1717 return;
1718 case 3: /* SFSR */
1719 if ((val & 1) == 0) {
1720 val = 0; /* Clear SFSR */
1721 }
1722 env->immu.sfsr = val;
1723 break;
1724 case 4: /* RO */
1725 return;
1726 case 5: /* TSB access */
1727 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1728 PRIx64 "\n", env->immu.tsb, val);
1729 env->immu.tsb = val;
1730 break;
1731 case 6: /* Tag access */
1732 env->immu.tag_access = val;
1733 break;
1734 case 7:
1735 case 8:
1736 return;
1737 default:
1738 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1739 break;
1740 }
1741
1742 if (oldreg != env->immu.mmuregs[reg]) {
1743 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1744 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1745 }
1746 #ifdef DEBUG_MMU
1747 dump_mmu(env);
1748 #endif
1749 return;
1750 }
1751 case ASI_ITLB_DATA_IN: /* I-MMU data in */
1752 /* ignore real translation entries */
1753 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1754 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access,
1755 val, "immu", env, addr);
1756 }
1757 return;
1758 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
1759 {
1760 /* TODO: auto demap */
1761
1762 unsigned int i = (addr >> 3) & 0x3f;
1763
1764 /* ignore real translation entries */
1765 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1766 replace_tlb_entry(&env->itlb[i], env->immu.tag_access,
1767 sun4v_tte_to_sun4u(env, addr, val), env);
1768 }
1769 #ifdef DEBUG_MMU
1770 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1771 dump_mmu(env);
1772 #endif
1773 return;
1774 }
1775 case ASI_IMMU_DEMAP: /* I-MMU demap */
1776 demap_tlb(env->itlb, addr, "immu", env);
1777 return;
1778 case ASI_DMMU: /* D-MMU regs */
1779 {
1780 int reg = (addr >> 3) & 0xf;
1781 uint64_t oldreg;
1782
1783 oldreg = env->dmmu.mmuregs[reg];
1784 switch (reg) {
1785 case 0: /* RO */
1786 case 4:
1787 return;
1788 case 3: /* SFSR */
1789 if ((val & 1) == 0) {
1790 val = 0; /* Clear SFSR, Fault address */
1791 env->dmmu.sfar = 0;
1792 }
1793 env->dmmu.sfsr = val;
1794 break;
1795 case 1: /* Primary context */
1796 env->dmmu.mmu_primary_context = val;
1797 /* can be optimized to only flush MMU_USER_IDX
1798 and MMU_KERNEL_IDX entries */
1799 tlb_flush(cs);
1800 break;
1801 case 2: /* Secondary context */
1802 env->dmmu.mmu_secondary_context = val;
1803 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1804 and MMU_KERNEL_SECONDARY_IDX entries */
1805 tlb_flush(cs);
1806 break;
1807 case 5: /* TSB access */
1808 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1809 PRIx64 "\n", env->dmmu.tsb, val);
1810 env->dmmu.tsb = val;
1811 break;
1812 case 6: /* Tag access */
1813 env->dmmu.tag_access = val;
1814 break;
1815 case 7: /* Virtual Watchpoint */
1816 env->dmmu.virtual_watchpoint = val;
1817 break;
1818 case 8: /* Physical Watchpoint */
1819 env->dmmu.physical_watchpoint = val;
1820 break;
1821 default:
1822 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1823 break;
1824 }
1825
1826 if (oldreg != env->dmmu.mmuregs[reg]) {
1827 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1828 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1829 }
1830 #ifdef DEBUG_MMU
1831 dump_mmu(env);
1832 #endif
1833 return;
1834 }
1835 case ASI_DTLB_DATA_IN: /* D-MMU data in */
1836 /* ignore real translation entries */
1837 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1838 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access,
1839 val, "dmmu", env, addr);
1840 }
1841 return;
1842 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
1843 {
1844 unsigned int i = (addr >> 3) & 0x3f;
1845
1846 /* ignore real translation entries */
1847 if (!(addr & TLB_UST1_IS_REAL_BIT)) {
1848 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access,
1849 sun4v_tte_to_sun4u(env, addr, val), env);
1850 }
1851 #ifdef DEBUG_MMU
1852 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1853 dump_mmu(env);
1854 #endif
1855 return;
1856 }
1857 case ASI_DMMU_DEMAP: /* D-MMU demap */
1858 demap_tlb(env->dtlb, addr, "dmmu", env);
1859 return;
1860 case ASI_INTR_RECEIVE: /* Interrupt data receive */
1861 env->ivec_status = val & 0x20;
1862 return;
1863 case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */
1864 if (unlikely((addr >= 0x20) && (addr < 0x30))) {
1865 /* Hyperprivileged access only */
1866 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1867 }
1868 /* fall through */
1869 case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */
1870 {
1871 unsigned int i = (addr >> 3) & 0x7;
1872 env->scratch[i] = val;
1873 return;
1874 }
1875 case ASI_MMU: /* UA2005 Context ID registers */
1876 {
1877 switch ((addr >> 3) & 0x3) {
1878 case 1:
1879 env->dmmu.mmu_primary_context = val;
1880 env->immu.mmu_primary_context = val;
1881 tlb_flush_by_mmuidx(cs,
1882 (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX));
1883 break;
1884 case 2:
1885 env->dmmu.mmu_secondary_context = val;
1886 env->immu.mmu_secondary_context = val;
1887 tlb_flush_by_mmuidx(cs,
1888 (1 << MMU_USER_SECONDARY_IDX) |
1889 (1 << MMU_KERNEL_SECONDARY_IDX));
1890 break;
1891 default:
1892 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1893 }
1894 }
1895 return;
1896 case ASI_QUEUE: /* UA2005 CPU mondo queue */
1897 case ASI_DCACHE_DATA: /* D-cache data */
1898 case ASI_DCACHE_TAG: /* D-cache tag access */
1899 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1900 case ASI_AFSR: /* E-cache asynchronous fault status */
1901 case ASI_AFAR: /* E-cache asynchronous fault address */
1902 case ASI_EC_TAG_DATA: /* E-cache tag data */
1903 case ASI_IC_INSTR: /* I-cache instruction access */
1904 case ASI_IC_TAG: /* I-cache tag access */
1905 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1906 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1907 case ASI_EC_W: /* E-cache tag */
1908 case ASI_EC_R: /* E-cache tag */
1909 return;
1910 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */
1911 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */
1912 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */
1913 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */
1914 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */
1915 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */
1916 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */
1917 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
1918 case ASI_INTR_R: /* Incoming interrupt vector, RO */
1919 case ASI_PNF: /* Primary no-fault, RO */
1920 case ASI_SNF: /* Secondary no-fault, RO */
1921 case ASI_PNFL: /* Primary no-fault LE, RO */
1922 case ASI_SNFL: /* Secondary no-fault LE, RO */
1923 default:
1924 sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC());
1925 return;
1926 }
1927 }
1928 #endif /* CONFIG_USER_ONLY */
1929 #endif /* TARGET_SPARC64 */
1930
1931 #if !defined(CONFIG_USER_ONLY)
1932
1933 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
1934 vaddr addr, unsigned size,
1935 MMUAccessType access_type,
1936 int mmu_idx, MemTxAttrs attrs,
1937 MemTxResult response, uintptr_t retaddr)
1938 {
1939 bool is_write = access_type == MMU_DATA_STORE;
1940 bool is_exec = access_type == MMU_INST_FETCH;
1941 bool is_asi = false;
1942
1943 sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec,
1944 is_asi, size, retaddr);
1945 }
1946 #endif
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