4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2.1 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "disas/disas.h"
25 #include "exec/helper-proto.h"
26 #include "exec/exec-all.h"
27 #include "tcg/tcg-op.h"
28 #include "tcg/tcg-op-gvec.h"
29 #include "exec/helper-gen.h"
30 #include "exec/translator.h"
34 #define HELPER_H "helper.h"
35 #include "exec/helper-info.c.inc"
39 # define gen_helper_rdpsr(D, E) qemu_build_not_reached()
40 # define gen_helper_rett(E) qemu_build_not_reached()
41 # define gen_helper_power_down(E) qemu_build_not_reached()
42 # define gen_helper_wrpsr(E, S) qemu_build_not_reached()
44 # define gen_helper_clear_softint(E, S) qemu_build_not_reached()
45 # define gen_helper_done(E) qemu_build_not_reached()
46 # define gen_helper_flushw(E) qemu_build_not_reached()
47 # define gen_helper_rdccr(D, E) qemu_build_not_reached()
48 # define gen_helper_rdcwp(D, E) qemu_build_not_reached()
49 # define gen_helper_restored(E) qemu_build_not_reached()
50 # define gen_helper_retry(E) qemu_build_not_reached()
51 # define gen_helper_saved(E) qemu_build_not_reached()
52 # define gen_helper_set_softint(E, S) qemu_build_not_reached()
53 # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached()
54 # define gen_helper_tick_set_count(P, S) qemu_build_not_reached()
55 # define gen_helper_tick_set_limit(P, S) qemu_build_not_reached()
56 # define gen_helper_wrccr(E, S) qemu_build_not_reached()
57 # define gen_helper_wrcwp(E, S) qemu_build_not_reached()
58 # define gen_helper_wrgl(E, S) qemu_build_not_reached()
59 # define gen_helper_write_softint(E, S) qemu_build_not_reached()
60 # define gen_helper_wrpil(E, S) qemu_build_not_reached()
61 # define gen_helper_wrpstate(E, S) qemu_build_not_reached()
62 # define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL; })
63 # define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL; })
64 # define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL; })
65 # define gen_helper_fcmpgt32 ({ qemu_build_not_reached(); NULL; })
66 # define gen_helper_fcmple16 ({ qemu_build_not_reached(); NULL; })
67 # define gen_helper_fcmple32 ({ qemu_build_not_reached(); NULL; })
68 # define gen_helper_fcmpne16 ({ qemu_build_not_reached(); NULL; })
69 # define gen_helper_fcmpne32 ({ qemu_build_not_reached(); NULL; })
70 # define gen_helper_fdtox ({ qemu_build_not_reached(); NULL; })
71 # define gen_helper_fexpand ({ qemu_build_not_reached(); NULL; })
72 # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL; })
73 # define gen_helper_fmul8ulx16 ({ qemu_build_not_reached(); NULL; })
74 # define gen_helper_fmul8x16al ({ qemu_build_not_reached(); NULL; })
75 # define gen_helper_fmul8x16au ({ qemu_build_not_reached(); NULL; })
76 # define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL; })
77 # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL; })
78 # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL; })
79 # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL; })
80 # define gen_helper_fqtox ({ qemu_build_not_reached(); NULL; })
81 # define gen_helper_fstox ({ qemu_build_not_reached(); NULL; })
82 # define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; })
83 # define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL; })
84 # define gen_helper_fxtos ({ qemu_build_not_reached(); NULL; })
85 # define gen_helper_pdist ({ qemu_build_not_reached(); NULL; })
86 # define FSR_LDXFSR_MASK 0
87 # define FSR_LDXFSR_OLDMASK 0
91 /* Dynamic PC, must exit to main loop. */
93 /* Dynamic PC, one of two values according to jump_pc[T2]. */
95 /* Dynamic PC, may lookup next TB. */
96 #define DYNAMIC_PC_LOOKUP 3
98 #define DISAS_EXIT DISAS_TARGET_0
100 /* global register indexes */
101 static TCGv_ptr cpu_regwptr
;
102 static TCGv cpu_fsr
, cpu_pc
, cpu_npc
;
103 static TCGv cpu_regs
[32];
106 static TCGv cpu_cond
;
107 static TCGv cpu_cc_N
;
108 static TCGv cpu_cc_V
;
109 static TCGv cpu_icc_Z
;
110 static TCGv cpu_icc_C
;
111 #ifdef TARGET_SPARC64
112 static TCGv cpu_xcc_Z
;
113 static TCGv cpu_xcc_C
;
114 static TCGv_i32 cpu_fprs
;
117 # define cpu_fprs ({ qemu_build_not_reached(); (TCGv)NULL; })
118 # define cpu_gsr ({ qemu_build_not_reached(); (TCGv)NULL; })
121 #ifdef TARGET_SPARC64
122 #define cpu_cc_Z cpu_xcc_Z
123 #define cpu_cc_C cpu_xcc_C
125 #define cpu_cc_Z cpu_icc_Z
126 #define cpu_cc_C cpu_icc_C
127 #define cpu_xcc_Z ({ qemu_build_not_reached(); NULL; })
128 #define cpu_xcc_C ({ qemu_build_not_reached(); NULL; })
131 /* Floating point registers */
132 static TCGv_i64 cpu_fpr
[TARGET_DPREGS
];
134 #define env_field_offsetof(X) offsetof(CPUSPARCState, X)
135 #ifdef TARGET_SPARC64
136 # define env32_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
137 # define env64_field_offsetof(X) env_field_offsetof(X)
139 # define env32_field_offsetof(X) env_field_offsetof(X)
140 # define env64_field_offsetof(X) ({ qemu_build_not_reached(); 0; })
143 typedef struct DisasCompare
{
149 typedef struct DisasDelayException
{
150 struct DisasDelayException
*next
;
153 /* Saved state at parent insn. */
156 } DisasDelayException
;
158 typedef struct DisasContext
{
159 DisasContextBase base
;
160 target_ulong pc
; /* current Program Counter: integer or DYNAMIC_PC */
161 target_ulong npc
; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
163 /* Used when JUMP_PC value is used. */
165 target_ulong jump_pc
[2];
170 bool address_mask_32bit
;
171 #ifndef CONFIG_USER_ONLY
173 #ifdef TARGET_SPARC64
179 #ifdef TARGET_SPARC64
183 DisasDelayException
*delay_excp_list
;
186 // This function uses non-native bit order
187 #define GET_FIELD(X, FROM, TO) \
188 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
190 // This function uses the order in the manuals, i.e. bit 0 is 2^0
191 #define GET_FIELD_SP(X, FROM, TO) \
192 GET_FIELD(X, 31 - (TO), 31 - (FROM))
194 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
195 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
197 #ifdef TARGET_SPARC64
198 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
199 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
201 #define DFPREG(r) (r & 0x1e)
202 #define QFPREG(r) (r & 0x1c)
205 #define UA2005_HTRAP_MASK 0xff
206 #define V8_TRAP_MASK 0x7f
208 #define IS_IMM (insn & (1<<13))
210 static void gen_update_fprs_dirty(DisasContext
*dc
, int rd
)
212 #if defined(TARGET_SPARC64)
213 int bit
= (rd
< 32) ? 1 : 2;
214 /* If we know we've already set this bit within the TB,
215 we can avoid setting it again. */
216 if (!(dc
->fprs_dirty
& bit
)) {
217 dc
->fprs_dirty
|= bit
;
218 tcg_gen_ori_i32(cpu_fprs
, cpu_fprs
, bit
);
223 /* floating point registers moves */
224 static TCGv_i32
gen_load_fpr_F(DisasContext
*dc
, unsigned int src
)
226 TCGv_i32 ret
= tcg_temp_new_i32();
228 tcg_gen_extrl_i64_i32(ret
, cpu_fpr
[src
/ 2]);
230 tcg_gen_extrh_i64_i32(ret
, cpu_fpr
[src
/ 2]);
235 static void gen_store_fpr_F(DisasContext
*dc
, unsigned int dst
, TCGv_i32 v
)
237 TCGv_i64 t
= tcg_temp_new_i64();
239 tcg_gen_extu_i32_i64(t
, v
);
240 tcg_gen_deposit_i64(cpu_fpr
[dst
/ 2], cpu_fpr
[dst
/ 2], t
,
241 (dst
& 1 ? 0 : 32), 32);
242 gen_update_fprs_dirty(dc
, dst
);
245 static TCGv_i64
gen_load_fpr_D(DisasContext
*dc
, unsigned int src
)
248 return cpu_fpr
[src
/ 2];
251 static void gen_store_fpr_D(DisasContext
*dc
, unsigned int dst
, TCGv_i64 v
)
254 tcg_gen_mov_i64(cpu_fpr
[dst
/ 2], v
);
255 gen_update_fprs_dirty(dc
, dst
);
258 static TCGv_i64
gen_dest_fpr_D(DisasContext
*dc
, unsigned int dst
)
260 return cpu_fpr
[DFPREG(dst
) / 2];
263 static TCGv_i128
gen_load_fpr_Q(DisasContext
*dc
, unsigned int src
)
265 TCGv_i128 ret
= tcg_temp_new_i128();
268 tcg_gen_concat_i64_i128(ret
, cpu_fpr
[src
/ 2 + 1], cpu_fpr
[src
/ 2]);
272 static void gen_store_fpr_Q(DisasContext
*dc
, unsigned int dst
, TCGv_i128 v
)
275 tcg_gen_extr_i128_i64(cpu_fpr
[dst
/ 2 + 1], cpu_fpr
[dst
/ 2], v
);
276 gen_update_fprs_dirty(dc
, dst
);
280 #ifdef CONFIG_USER_ONLY
281 #define supervisor(dc) 0
282 #define hypervisor(dc) 0
284 #ifdef TARGET_SPARC64
285 #define hypervisor(dc) (dc->hypervisor)
286 #define supervisor(dc) (dc->supervisor | dc->hypervisor)
288 #define supervisor(dc) (dc->supervisor)
289 #define hypervisor(dc) 0
293 #if !defined(TARGET_SPARC64)
294 # define AM_CHECK(dc) false
295 #elif defined(TARGET_ABI32)
296 # define AM_CHECK(dc) true
297 #elif defined(CONFIG_USER_ONLY)
298 # define AM_CHECK(dc) false
300 # define AM_CHECK(dc) ((dc)->address_mask_32bit)
303 static void gen_address_mask(DisasContext
*dc
, TCGv addr
)
306 tcg_gen_andi_tl(addr
, addr
, 0xffffffffULL
);
310 static target_ulong
address_mask_i(DisasContext
*dc
, target_ulong addr
)
312 return AM_CHECK(dc
) ? (uint32_t)addr
: addr
;
315 static TCGv
gen_load_gpr(DisasContext
*dc
, int reg
)
319 return cpu_regs
[reg
];
321 TCGv t
= tcg_temp_new();
322 tcg_gen_movi_tl(t
, 0);
327 static void gen_store_gpr(DisasContext
*dc
, int reg
, TCGv v
)
331 tcg_gen_mov_tl(cpu_regs
[reg
], v
);
335 static TCGv
gen_dest_gpr(DisasContext
*dc
, int reg
)
339 return cpu_regs
[reg
];
341 return tcg_temp_new();
345 static bool use_goto_tb(DisasContext
*s
, target_ulong pc
, target_ulong npc
)
347 return translator_use_goto_tb(&s
->base
, pc
) &&
348 translator_use_goto_tb(&s
->base
, npc
);
351 static void gen_goto_tb(DisasContext
*s
, int tb_num
,
352 target_ulong pc
, target_ulong npc
)
354 if (use_goto_tb(s
, pc
, npc
)) {
355 /* jump to same page: we can use a direct jump */
356 tcg_gen_goto_tb(tb_num
);
357 tcg_gen_movi_tl(cpu_pc
, pc
);
358 tcg_gen_movi_tl(cpu_npc
, npc
);
359 tcg_gen_exit_tb(s
->base
.tb
, tb_num
);
361 /* jump to another page: we can use an indirect jump */
362 tcg_gen_movi_tl(cpu_pc
, pc
);
363 tcg_gen_movi_tl(cpu_npc
, npc
);
364 tcg_gen_lookup_and_goto_ptr();
368 static TCGv
gen_carry32(void)
370 if (TARGET_LONG_BITS
== 64) {
371 TCGv t
= tcg_temp_new();
372 tcg_gen_extract_tl(t
, cpu_icc_C
, 32, 1);
378 static void gen_op_addcc_int(TCGv dst
, TCGv src1
, TCGv src2
, TCGv cin
)
380 TCGv z
= tcg_constant_tl(0);
383 tcg_gen_add2_tl(cpu_cc_N
, cpu_cc_C
, src1
, z
, cin
, z
);
384 tcg_gen_add2_tl(cpu_cc_N
, cpu_cc_C
, cpu_cc_N
, cpu_cc_C
, src2
, z
);
386 tcg_gen_add2_tl(cpu_cc_N
, cpu_cc_C
, src1
, z
, src2
, z
);
388 tcg_gen_xor_tl(cpu_cc_Z
, src1
, src2
);
389 tcg_gen_xor_tl(cpu_cc_V
, cpu_cc_N
, src2
);
390 tcg_gen_andc_tl(cpu_cc_V
, cpu_cc_V
, cpu_cc_Z
);
391 if (TARGET_LONG_BITS
== 64) {
393 * Carry-in to bit 32 is result ^ src1 ^ src2.
394 * We already have the src xor term in Z, from computation of V.
396 tcg_gen_xor_tl(cpu_icc_C
, cpu_cc_Z
, cpu_cc_N
);
397 tcg_gen_mov_tl(cpu_icc_Z
, cpu_cc_N
);
399 tcg_gen_mov_tl(cpu_cc_Z
, cpu_cc_N
);
400 tcg_gen_mov_tl(dst
, cpu_cc_N
);
403 static void gen_op_addcc(TCGv dst
, TCGv src1
, TCGv src2
)
405 gen_op_addcc_int(dst
, src1
, src2
, NULL
);
408 static void gen_op_taddcc(TCGv dst
, TCGv src1
, TCGv src2
)
410 TCGv t
= tcg_temp_new();
412 /* Save the tag bits around modification of dst. */
413 tcg_gen_or_tl(t
, src1
, src2
);
415 gen_op_addcc(dst
, src1
, src2
);
417 /* Incorprate tag bits into icc.V */
418 tcg_gen_andi_tl(t
, t
, 3);
419 tcg_gen_neg_tl(t
, t
);
420 tcg_gen_ext32u_tl(t
, t
);
421 tcg_gen_or_tl(cpu_cc_V
, cpu_cc_V
, t
);
424 static void gen_op_addc(TCGv dst
, TCGv src1
, TCGv src2
)
426 tcg_gen_add_tl(dst
, src1
, src2
);
427 tcg_gen_add_tl(dst
, dst
, gen_carry32());
430 static void gen_op_addccc(TCGv dst
, TCGv src1
, TCGv src2
)
432 gen_op_addcc_int(dst
, src1
, src2
, gen_carry32());
435 static void gen_op_subcc_int(TCGv dst
, TCGv src1
, TCGv src2
, TCGv cin
)
437 TCGv z
= tcg_constant_tl(0);
440 tcg_gen_sub2_tl(cpu_cc_N
, cpu_cc_C
, src1
, z
, cin
, z
);
441 tcg_gen_sub2_tl(cpu_cc_N
, cpu_cc_C
, cpu_cc_N
, cpu_cc_C
, src2
, z
);
443 tcg_gen_sub2_tl(cpu_cc_N
, cpu_cc_C
, src1
, z
, src2
, z
);
445 tcg_gen_neg_tl(cpu_cc_C
, cpu_cc_C
);
446 tcg_gen_xor_tl(cpu_cc_Z
, src1
, src2
);
447 tcg_gen_xor_tl(cpu_cc_V
, cpu_cc_N
, src1
);
448 tcg_gen_and_tl(cpu_cc_V
, cpu_cc_V
, cpu_cc_Z
);
449 #ifdef TARGET_SPARC64
450 tcg_gen_xor_tl(cpu_icc_C
, cpu_cc_Z
, cpu_cc_N
);
451 tcg_gen_mov_tl(cpu_icc_Z
, cpu_cc_N
);
453 tcg_gen_mov_tl(cpu_cc_Z
, cpu_cc_N
);
454 tcg_gen_mov_tl(dst
, cpu_cc_N
);
457 static void gen_op_subcc(TCGv dst
, TCGv src1
, TCGv src2
)
459 gen_op_subcc_int(dst
, src1
, src2
, NULL
);
462 static void gen_op_tsubcc(TCGv dst
, TCGv src1
, TCGv src2
)
464 TCGv t
= tcg_temp_new();
466 /* Save the tag bits around modification of dst. */
467 tcg_gen_or_tl(t
, src1
, src2
);
469 gen_op_subcc(dst
, src1
, src2
);
471 /* Incorprate tag bits into icc.V */
472 tcg_gen_andi_tl(t
, t
, 3);
473 tcg_gen_neg_tl(t
, t
);
474 tcg_gen_ext32u_tl(t
, t
);
475 tcg_gen_or_tl(cpu_cc_V
, cpu_cc_V
, t
);
478 static void gen_op_subc(TCGv dst
, TCGv src1
, TCGv src2
)
480 tcg_gen_sub_tl(dst
, src1
, src2
);
481 tcg_gen_sub_tl(dst
, dst
, gen_carry32());
484 static void gen_op_subccc(TCGv dst
, TCGv src1
, TCGv src2
)
486 gen_op_subcc_int(dst
, src1
, src2
, gen_carry32());
489 static void gen_op_mulscc(TCGv dst
, TCGv src1
, TCGv src2
)
491 TCGv zero
= tcg_constant_tl(0);
492 TCGv t_src1
= tcg_temp_new();
493 TCGv t_src2
= tcg_temp_new();
494 TCGv t0
= tcg_temp_new();
496 tcg_gen_ext32u_tl(t_src1
, src1
);
497 tcg_gen_ext32u_tl(t_src2
, src2
);
503 tcg_gen_andi_tl(t0
, cpu_y
, 0x1);
504 tcg_gen_movcond_tl(TCG_COND_EQ
, t_src2
, t0
, zero
, zero
, t_src2
);
508 * y = (b2 << 31) | (y >> 1);
510 tcg_gen_extract_tl(t0
, cpu_y
, 1, 31);
511 tcg_gen_deposit_tl(cpu_y
, t0
, src1
, 31, 1);
514 tcg_gen_xor_tl(t0
, cpu_cc_N
, cpu_cc_V
);
517 * src1 = (b1 << 31) | (src1 >> 1)
519 tcg_gen_andi_tl(t0
, t0
, 1u << 31);
520 tcg_gen_shri_tl(t_src1
, t_src1
, 1);
521 tcg_gen_or_tl(t_src1
, t_src1
, t0
);
523 gen_op_addcc(dst
, t_src1
, t_src2
);
526 static void gen_op_multiply(TCGv dst
, TCGv src1
, TCGv src2
, int sign_ext
)
528 #if TARGET_LONG_BITS == 32
530 tcg_gen_muls2_tl(dst
, cpu_y
, src1
, src2
);
532 tcg_gen_mulu2_tl(dst
, cpu_y
, src1
, src2
);
535 TCGv t0
= tcg_temp_new_i64();
536 TCGv t1
= tcg_temp_new_i64();
539 tcg_gen_ext32s_i64(t0
, src1
);
540 tcg_gen_ext32s_i64(t1
, src2
);
542 tcg_gen_ext32u_i64(t0
, src1
);
543 tcg_gen_ext32u_i64(t1
, src2
);
546 tcg_gen_mul_i64(dst
, t0
, t1
);
547 tcg_gen_shri_i64(cpu_y
, dst
, 32);
551 static void gen_op_umul(TCGv dst
, TCGv src1
, TCGv src2
)
553 /* zero-extend truncated operands before multiplication */
554 gen_op_multiply(dst
, src1
, src2
, 0);
557 static void gen_op_smul(TCGv dst
, TCGv src1
, TCGv src2
)
559 /* sign-extend truncated operands before multiplication */
560 gen_op_multiply(dst
, src1
, src2
, 1);
563 static void gen_op_sdiv(TCGv dst
, TCGv src1
, TCGv src2
)
565 #ifdef TARGET_SPARC64
566 gen_helper_sdiv(dst
, tcg_env
, src1
, src2
);
567 tcg_gen_ext32s_tl(dst
, dst
);
569 TCGv_i64 t64
= tcg_temp_new_i64();
570 gen_helper_sdiv(t64
, tcg_env
, src1
, src2
);
571 tcg_gen_trunc_i64_tl(dst
, t64
);
575 static void gen_op_udivcc(TCGv dst
, TCGv src1
, TCGv src2
)
579 #ifdef TARGET_SPARC64
582 t64
= tcg_temp_new_i64();
585 gen_helper_udiv(t64
, tcg_env
, src1
, src2
);
587 #ifdef TARGET_SPARC64
588 tcg_gen_ext32u_tl(cpu_cc_N
, t64
);
589 tcg_gen_shri_tl(cpu_cc_V
, t64
, 32);
590 tcg_gen_mov_tl(cpu_icc_Z
, cpu_cc_N
);
591 tcg_gen_movi_tl(cpu_icc_C
, 0);
593 tcg_gen_extr_i64_tl(cpu_cc_N
, cpu_cc_V
, t64
);
595 tcg_gen_mov_tl(cpu_cc_Z
, cpu_cc_N
);
596 tcg_gen_movi_tl(cpu_cc_C
, 0);
597 tcg_gen_mov_tl(dst
, cpu_cc_N
);
600 static void gen_op_sdivcc(TCGv dst
, TCGv src1
, TCGv src2
)
604 #ifdef TARGET_SPARC64
607 t64
= tcg_temp_new_i64();
610 gen_helper_sdiv(t64
, tcg_env
, src1
, src2
);
612 #ifdef TARGET_SPARC64
613 tcg_gen_ext32s_tl(cpu_cc_N
, t64
);
614 tcg_gen_shri_tl(cpu_cc_V
, t64
, 32);
615 tcg_gen_mov_tl(cpu_icc_Z
, cpu_cc_N
);
616 tcg_gen_movi_tl(cpu_icc_C
, 0);
618 tcg_gen_extr_i64_tl(cpu_cc_N
, cpu_cc_V
, t64
);
620 tcg_gen_mov_tl(cpu_cc_Z
, cpu_cc_N
);
621 tcg_gen_movi_tl(cpu_cc_C
, 0);
622 tcg_gen_mov_tl(dst
, cpu_cc_N
);
625 static void gen_op_taddcctv(TCGv dst
, TCGv src1
, TCGv src2
)
627 gen_helper_taddcctv(dst
, tcg_env
, src1
, src2
);
630 static void gen_op_tsubcctv(TCGv dst
, TCGv src1
, TCGv src2
)
632 gen_helper_tsubcctv(dst
, tcg_env
, src1
, src2
);
635 static void gen_op_popc(TCGv dst
, TCGv src1
, TCGv src2
)
637 tcg_gen_ctpop_tl(dst
, src2
);
640 #ifndef TARGET_SPARC64
641 static void gen_helper_array8(TCGv dst
, TCGv src1
, TCGv src2
)
643 g_assert_not_reached();
647 static void gen_op_array16(TCGv dst
, TCGv src1
, TCGv src2
)
649 gen_helper_array8(dst
, src1
, src2
);
650 tcg_gen_shli_tl(dst
, dst
, 1);
653 static void gen_op_array32(TCGv dst
, TCGv src1
, TCGv src2
)
655 gen_helper_array8(dst
, src1
, src2
);
656 tcg_gen_shli_tl(dst
, dst
, 2);
659 static void gen_op_fpack16(TCGv_i32 dst
, TCGv_i64 src
)
661 #ifdef TARGET_SPARC64
662 gen_helper_fpack16(dst
, cpu_gsr
, src
);
664 g_assert_not_reached();
668 static void gen_op_fpackfix(TCGv_i32 dst
, TCGv_i64 src
)
670 #ifdef TARGET_SPARC64
671 gen_helper_fpackfix(dst
, cpu_gsr
, src
);
673 g_assert_not_reached();
677 static void gen_op_fpack32(TCGv_i64 dst
, TCGv_i64 src1
, TCGv_i64 src2
)
679 #ifdef TARGET_SPARC64
680 gen_helper_fpack32(dst
, cpu_gsr
, src1
, src2
);
682 g_assert_not_reached();
686 static void gen_op_faligndata(TCGv_i64 dst
, TCGv_i64 s1
, TCGv_i64 s2
)
688 #ifdef TARGET_SPARC64
693 shift
= tcg_temp_new();
695 tcg_gen_andi_tl(shift
, cpu_gsr
, 7);
696 tcg_gen_shli_tl(shift
, shift
, 3);
697 tcg_gen_shl_tl(t1
, s1
, shift
);
700 * A shift of 64 does not produce 0 in TCG. Divide this into a
701 * shift of (up to 63) followed by a constant shift of 1.
703 tcg_gen_xori_tl(shift
, shift
, 63);
704 tcg_gen_shr_tl(t2
, s2
, shift
);
705 tcg_gen_shri_tl(t2
, t2
, 1);
707 tcg_gen_or_tl(dst
, t1
, t2
);
709 g_assert_not_reached();
713 static void gen_op_bshuffle(TCGv_i64 dst
, TCGv_i64 src1
, TCGv_i64 src2
)
715 #ifdef TARGET_SPARC64
716 gen_helper_bshuffle(dst
, cpu_gsr
, src1
, src2
);
718 g_assert_not_reached();
723 static void gen_op_eval_ba(TCGv dst
)
725 tcg_gen_movi_tl(dst
, 1);
729 static void gen_op_eval_bn(TCGv dst
)
731 tcg_gen_movi_tl(dst
, 0);
735 FPSR bit field FCC1 | FCC0:
741 static void gen_mov_reg_FCC0(TCGv reg
, TCGv src
,
742 unsigned int fcc_offset
)
744 tcg_gen_shri_tl(reg
, src
, FSR_FCC0_SHIFT
+ fcc_offset
);
745 tcg_gen_andi_tl(reg
, reg
, 0x1);
748 static void gen_mov_reg_FCC1(TCGv reg
, TCGv src
, unsigned int fcc_offset
)
750 tcg_gen_shri_tl(reg
, src
, FSR_FCC1_SHIFT
+ fcc_offset
);
751 tcg_gen_andi_tl(reg
, reg
, 0x1);
755 static void gen_op_eval_fbne(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
757 TCGv t0
= tcg_temp_new();
758 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
759 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
760 tcg_gen_or_tl(dst
, dst
, t0
);
763 // 1 or 2: FCC0 ^ FCC1
764 static void gen_op_eval_fblg(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
766 TCGv t0
= tcg_temp_new();
767 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
768 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
769 tcg_gen_xor_tl(dst
, dst
, t0
);
773 static void gen_op_eval_fbul(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
775 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
779 static void gen_op_eval_fbl(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
781 TCGv t0
= tcg_temp_new();
782 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
783 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
784 tcg_gen_andc_tl(dst
, dst
, t0
);
788 static void gen_op_eval_fbug(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
790 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
794 static void gen_op_eval_fbg(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
796 TCGv t0
= tcg_temp_new();
797 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
798 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
799 tcg_gen_andc_tl(dst
, t0
, dst
);
803 static void gen_op_eval_fbu(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
805 TCGv t0
= tcg_temp_new();
806 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
807 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
808 tcg_gen_and_tl(dst
, dst
, t0
);
812 static void gen_op_eval_fbe(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
814 TCGv t0
= tcg_temp_new();
815 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
816 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
817 tcg_gen_or_tl(dst
, dst
, t0
);
818 tcg_gen_xori_tl(dst
, dst
, 0x1);
821 // 0 or 3: !(FCC0 ^ FCC1)
822 static void gen_op_eval_fbue(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
824 TCGv t0
= tcg_temp_new();
825 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
826 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
827 tcg_gen_xor_tl(dst
, dst
, t0
);
828 tcg_gen_xori_tl(dst
, dst
, 0x1);
832 static void gen_op_eval_fbge(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
834 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
835 tcg_gen_xori_tl(dst
, dst
, 0x1);
838 // !1: !(FCC0 & !FCC1)
839 static void gen_op_eval_fbuge(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
841 TCGv t0
= tcg_temp_new();
842 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
843 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
844 tcg_gen_andc_tl(dst
, dst
, t0
);
845 tcg_gen_xori_tl(dst
, dst
, 0x1);
849 static void gen_op_eval_fble(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
851 gen_mov_reg_FCC1(dst
, src
, fcc_offset
);
852 tcg_gen_xori_tl(dst
, dst
, 0x1);
855 // !2: !(!FCC0 & FCC1)
856 static void gen_op_eval_fbule(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
858 TCGv t0
= tcg_temp_new();
859 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
860 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
861 tcg_gen_andc_tl(dst
, t0
, dst
);
862 tcg_gen_xori_tl(dst
, dst
, 0x1);
865 // !3: !(FCC0 & FCC1)
866 static void gen_op_eval_fbo(TCGv dst
, TCGv src
, unsigned int fcc_offset
)
868 TCGv t0
= tcg_temp_new();
869 gen_mov_reg_FCC0(dst
, src
, fcc_offset
);
870 gen_mov_reg_FCC1(t0
, src
, fcc_offset
);
871 tcg_gen_and_tl(dst
, dst
, t0
);
872 tcg_gen_xori_tl(dst
, dst
, 0x1);
875 static void finishing_insn(DisasContext
*dc
)
878 * From here, there is no future path through an unwinding exception.
879 * If the current insn cannot raise an exception, the computation of
880 * cpu_cond may be able to be elided.
882 if (dc
->cpu_cond_live
) {
883 tcg_gen_discard_tl(cpu_cond
);
884 dc
->cpu_cond_live
= false;
888 static void gen_generic_branch(DisasContext
*dc
)
890 TCGv npc0
= tcg_constant_tl(dc
->jump_pc
[0]);
891 TCGv npc1
= tcg_constant_tl(dc
->jump_pc
[1]);
892 TCGv c2
= tcg_constant_tl(dc
->jump
.c2
);
894 tcg_gen_movcond_tl(dc
->jump
.cond
, cpu_npc
, dc
->jump
.c1
, c2
, npc0
, npc1
);
897 /* call this function before using the condition register as it may
898 have been set for a jump */
899 static void flush_cond(DisasContext
*dc
)
901 if (dc
->npc
== JUMP_PC
) {
902 gen_generic_branch(dc
);
903 dc
->npc
= DYNAMIC_PC_LOOKUP
;
907 static void save_npc(DisasContext
*dc
)
912 gen_generic_branch(dc
);
913 dc
->npc
= DYNAMIC_PC_LOOKUP
;
916 case DYNAMIC_PC_LOOKUP
:
919 g_assert_not_reached();
922 tcg_gen_movi_tl(cpu_npc
, dc
->npc
);
926 static void save_state(DisasContext
*dc
)
928 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
932 static void gen_exception(DisasContext
*dc
, int which
)
936 gen_helper_raise_exception(tcg_env
, tcg_constant_i32(which
));
937 dc
->base
.is_jmp
= DISAS_NORETURN
;
940 static TCGLabel
*delay_exceptionv(DisasContext
*dc
, TCGv_i32 excp
)
942 DisasDelayException
*e
= g_new0(DisasDelayException
, 1);
944 e
->next
= dc
->delay_excp_list
;
945 dc
->delay_excp_list
= e
;
947 e
->lab
= gen_new_label();
950 /* Caller must have used flush_cond before branch. */
951 assert(e
->npc
!= JUMP_PC
);
957 static TCGLabel
*delay_exception(DisasContext
*dc
, int excp
)
959 return delay_exceptionv(dc
, tcg_constant_i32(excp
));
962 static void gen_check_align(DisasContext
*dc
, TCGv addr
, int mask
)
964 TCGv t
= tcg_temp_new();
967 tcg_gen_andi_tl(t
, addr
, mask
);
970 lab
= delay_exception(dc
, TT_UNALIGNED
);
971 tcg_gen_brcondi_tl(TCG_COND_NE
, t
, 0, lab
);
974 static void gen_mov_pc_npc(DisasContext
*dc
)
981 gen_generic_branch(dc
);
982 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
983 dc
->pc
= DYNAMIC_PC_LOOKUP
;
986 case DYNAMIC_PC_LOOKUP
:
987 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
991 g_assert_not_reached();
998 static void gen_compare(DisasCompare
*cmp
, bool xcc
, unsigned int cond
,
1003 cmp
->c1
= t1
= tcg_temp_new();
1007 case 0x0: /* never */
1008 cmp
->cond
= TCG_COND_NEVER
;
1009 cmp
->c1
= tcg_constant_tl(0);
1012 case 0x1: /* eq: Z */
1013 cmp
->cond
= TCG_COND_EQ
;
1014 if (TARGET_LONG_BITS
== 32 || xcc
) {
1015 tcg_gen_mov_tl(t1
, cpu_cc_Z
);
1017 tcg_gen_ext32u_tl(t1
, cpu_icc_Z
);
1021 case 0x2: /* le: Z | (N ^ V) */
1024 * cc_Z || (N ^ V) < 0 NE
1025 * cc_Z && !((N ^ V) < 0) EQ
1026 * cc_Z & ~((N ^ V) >> TLB) EQ
1028 cmp
->cond
= TCG_COND_EQ
;
1029 tcg_gen_xor_tl(t1
, cpu_cc_N
, cpu_cc_V
);
1030 tcg_gen_sextract_tl(t1
, t1
, xcc
? 63 : 31, 1);
1031 tcg_gen_andc_tl(t1
, xcc
? cpu_cc_Z
: cpu_icc_Z
, t1
);
1032 if (TARGET_LONG_BITS
== 64 && !xcc
) {
1033 tcg_gen_ext32u_tl(t1
, t1
);
1037 case 0x3: /* lt: N ^ V */
1038 cmp
->cond
= TCG_COND_LT
;
1039 tcg_gen_xor_tl(t1
, cpu_cc_N
, cpu_cc_V
);
1040 if (TARGET_LONG_BITS
== 64 && !xcc
) {
1041 tcg_gen_ext32s_tl(t1
, t1
);
1045 case 0x4: /* leu: Z | C */
1048 * cc_Z == 0 || cc_C != 0 NE
1049 * cc_Z != 0 && cc_C == 0 EQ
1050 * cc_Z & (cc_C ? 0 : -1) EQ
1051 * cc_Z & (cc_C - 1) EQ
1053 cmp
->cond
= TCG_COND_EQ
;
1054 if (TARGET_LONG_BITS
== 32 || xcc
) {
1055 tcg_gen_subi_tl(t1
, cpu_cc_C
, 1);
1056 tcg_gen_and_tl(t1
, t1
, cpu_cc_Z
);
1058 tcg_gen_extract_tl(t1
, cpu_icc_C
, 32, 1);
1059 tcg_gen_subi_tl(t1
, t1
, 1);
1060 tcg_gen_and_tl(t1
, t1
, cpu_icc_Z
);
1061 tcg_gen_ext32u_tl(t1
, t1
);
1065 case 0x5: /* ltu: C */
1066 cmp
->cond
= TCG_COND_NE
;
1067 if (TARGET_LONG_BITS
== 32 || xcc
) {
1068 tcg_gen_mov_tl(t1
, cpu_cc_C
);
1070 tcg_gen_extract_tl(t1
, cpu_icc_C
, 32, 1);
1074 case 0x6: /* neg: N */
1075 cmp
->cond
= TCG_COND_LT
;
1076 if (TARGET_LONG_BITS
== 32 || xcc
) {
1077 tcg_gen_mov_tl(t1
, cpu_cc_N
);
1079 tcg_gen_ext32s_tl(t1
, cpu_cc_N
);
1083 case 0x7: /* vs: V */
1084 cmp
->cond
= TCG_COND_LT
;
1085 if (TARGET_LONG_BITS
== 32 || xcc
) {
1086 tcg_gen_mov_tl(t1
, cpu_cc_V
);
1088 tcg_gen_ext32s_tl(t1
, cpu_cc_V
);
1093 cmp
->cond
= tcg_invert_cond(cmp
->cond
);
1097 static void gen_fcompare(DisasCompare
*cmp
, unsigned int cc
, unsigned int cond
)
1099 unsigned int offset
;
1102 /* For now we still generate a straight boolean result. */
1103 cmp
->cond
= TCG_COND_NE
;
1104 cmp
->c1
= r_dst
= tcg_temp_new();
1125 gen_op_eval_bn(r_dst
);
1128 gen_op_eval_fbne(r_dst
, cpu_fsr
, offset
);
1131 gen_op_eval_fblg(r_dst
, cpu_fsr
, offset
);
1134 gen_op_eval_fbul(r_dst
, cpu_fsr
, offset
);
1137 gen_op_eval_fbl(r_dst
, cpu_fsr
, offset
);
1140 gen_op_eval_fbug(r_dst
, cpu_fsr
, offset
);
1143 gen_op_eval_fbg(r_dst
, cpu_fsr
, offset
);
1146 gen_op_eval_fbu(r_dst
, cpu_fsr
, offset
);
1149 gen_op_eval_ba(r_dst
);
1152 gen_op_eval_fbe(r_dst
, cpu_fsr
, offset
);
1155 gen_op_eval_fbue(r_dst
, cpu_fsr
, offset
);
1158 gen_op_eval_fbge(r_dst
, cpu_fsr
, offset
);
1161 gen_op_eval_fbuge(r_dst
, cpu_fsr
, offset
);
1164 gen_op_eval_fble(r_dst
, cpu_fsr
, offset
);
1167 gen_op_eval_fbule(r_dst
, cpu_fsr
, offset
);
1170 gen_op_eval_fbo(r_dst
, cpu_fsr
, offset
);
1175 static bool gen_compare_reg(DisasCompare
*cmp
, int cond
, TCGv r_src
)
1177 static const TCGCond cond_reg
[4] = {
1178 TCG_COND_NEVER
, /* reserved */
1185 if ((cond
& 3) == 0) {
1188 tcond
= cond_reg
[cond
& 3];
1190 tcond
= tcg_invert_cond(tcond
);
1194 cmp
->c1
= tcg_temp_new();
1196 tcg_gen_mov_tl(cmp
->c1
, r_src
);
1200 static void gen_op_clear_ieee_excp_and_FTT(void)
1202 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, FSR_FTT_CEXC_NMASK
);
1205 static void gen_op_fmovs(TCGv_i32 dst
, TCGv_i32 src
)
1207 gen_op_clear_ieee_excp_and_FTT();
1208 tcg_gen_mov_i32(dst
, src
);
1211 static void gen_op_fnegs(TCGv_i32 dst
, TCGv_i32 src
)
1213 gen_op_clear_ieee_excp_and_FTT();
1214 tcg_gen_xori_i32(dst
, src
, 1u << 31);
1217 static void gen_op_fabss(TCGv_i32 dst
, TCGv_i32 src
)
1219 gen_op_clear_ieee_excp_and_FTT();
1220 tcg_gen_andi_i32(dst
, src
, ~(1u << 31));
1223 static void gen_op_fmovd(TCGv_i64 dst
, TCGv_i64 src
)
1225 gen_op_clear_ieee_excp_and_FTT();
1226 tcg_gen_mov_i64(dst
, src
);
1229 static void gen_op_fnegd(TCGv_i64 dst
, TCGv_i64 src
)
1231 gen_op_clear_ieee_excp_and_FTT();
1232 tcg_gen_xori_i64(dst
, src
, 1ull << 63);
1235 static void gen_op_fabsd(TCGv_i64 dst
, TCGv_i64 src
)
1237 gen_op_clear_ieee_excp_and_FTT();
1238 tcg_gen_andi_i64(dst
, src
, ~(1ull << 63));
1241 static void gen_op_fnegq(TCGv_i128 dst
, TCGv_i128 src
)
1243 TCGv_i64 l
= tcg_temp_new_i64();
1244 TCGv_i64 h
= tcg_temp_new_i64();
1246 tcg_gen_extr_i128_i64(l
, h
, src
);
1247 tcg_gen_xori_i64(h
, h
, 1ull << 63);
1248 tcg_gen_concat_i64_i128(dst
, l
, h
);
1251 static void gen_op_fabsq(TCGv_i128 dst
, TCGv_i128 src
)
1253 TCGv_i64 l
= tcg_temp_new_i64();
1254 TCGv_i64 h
= tcg_temp_new_i64();
1256 tcg_gen_extr_i128_i64(l
, h
, src
);
1257 tcg_gen_andi_i64(h
, h
, ~(1ull << 63));
1258 tcg_gen_concat_i64_i128(dst
, l
, h
);
1261 #ifdef TARGET_SPARC64
1262 static void gen_op_fcmps(int fccno
, TCGv_i32 r_rs1
, TCGv_i32 r_rs2
)
1266 gen_helper_fcmps(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1269 gen_helper_fcmps_fcc1(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1272 gen_helper_fcmps_fcc2(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1275 gen_helper_fcmps_fcc3(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1280 static void gen_op_fcmpd(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1284 gen_helper_fcmpd(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1287 gen_helper_fcmpd_fcc1(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1290 gen_helper_fcmpd_fcc2(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1293 gen_helper_fcmpd_fcc3(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1298 static void gen_op_fcmpq(int fccno
, TCGv_i128 r_rs1
, TCGv_i128 r_rs2
)
1302 gen_helper_fcmpq(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1305 gen_helper_fcmpq_fcc1(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1308 gen_helper_fcmpq_fcc2(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1311 gen_helper_fcmpq_fcc3(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1316 static void gen_op_fcmpes(int fccno
, TCGv_i32 r_rs1
, TCGv_i32 r_rs2
)
1320 gen_helper_fcmpes(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1323 gen_helper_fcmpes_fcc1(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1326 gen_helper_fcmpes_fcc2(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1329 gen_helper_fcmpes_fcc3(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1334 static void gen_op_fcmped(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1338 gen_helper_fcmped(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1341 gen_helper_fcmped_fcc1(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1344 gen_helper_fcmped_fcc2(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1347 gen_helper_fcmped_fcc3(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1352 static void gen_op_fcmpeq(int fccno
, TCGv_i128 r_rs1
, TCGv_i128 r_rs2
)
1356 gen_helper_fcmpeq(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1359 gen_helper_fcmpeq_fcc1(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1362 gen_helper_fcmpeq_fcc2(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1365 gen_helper_fcmpeq_fcc3(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1372 static void gen_op_fcmps(int fccno
, TCGv r_rs1
, TCGv r_rs2
)
1374 gen_helper_fcmps(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1377 static void gen_op_fcmpd(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1379 gen_helper_fcmpd(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1382 static void gen_op_fcmpq(int fccno
, TCGv_i128 r_rs1
, TCGv_i128 r_rs2
)
1384 gen_helper_fcmpq(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1387 static void gen_op_fcmpes(int fccno
, TCGv r_rs1
, TCGv r_rs2
)
1389 gen_helper_fcmpes(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1392 static void gen_op_fcmped(int fccno
, TCGv_i64 r_rs1
, TCGv_i64 r_rs2
)
1394 gen_helper_fcmped(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1397 static void gen_op_fcmpeq(int fccno
, TCGv_i128 r_rs1
, TCGv_i128 r_rs2
)
1399 gen_helper_fcmpeq(cpu_fsr
, tcg_env
, r_rs1
, r_rs2
);
1403 static void gen_op_fpexception_im(DisasContext
*dc
, int fsr_flags
)
1405 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, FSR_FTT_NMASK
);
1406 tcg_gen_ori_tl(cpu_fsr
, cpu_fsr
, fsr_flags
);
1407 gen_exception(dc
, TT_FP_EXCP
);
1410 static int gen_trap_ifnofpu(DisasContext
*dc
)
1412 #if !defined(CONFIG_USER_ONLY)
1413 if (!dc
->fpu_enabled
) {
1414 gen_exception(dc
, TT_NFPU_INSN
);
1442 * For asi == -1, treat as non-asi.
1443 * For ask == -2, treat as immediate offset (v8 error, v9 %asi).
1445 static DisasASI
resolve_asi(DisasContext
*dc
, int asi
, MemOp memop
)
1447 ASIType type
= GET_ASI_HELPER
;
1448 int mem_idx
= dc
->mem_idx
;
1451 /* Artificial "non-asi" case. */
1452 type
= GET_ASI_DIRECT
;
1456 #ifndef TARGET_SPARC64
1457 /* Before v9, all asis are immediate and privileged. */
1459 gen_exception(dc
, TT_ILL_INSN
);
1460 type
= GET_ASI_EXCP
;
1461 } else if (supervisor(dc
)
1462 /* Note that LEON accepts ASI_USERDATA in user mode, for
1463 use with CASA. Also note that previous versions of
1464 QEMU allowed (and old versions of gcc emitted) ASI_P
1465 for LEON, which is incorrect. */
1466 || (asi
== ASI_USERDATA
1467 && (dc
->def
->features
& CPU_FEATURE_CASA
))) {
1469 case ASI_USERDATA
: /* User data access */
1470 mem_idx
= MMU_USER_IDX
;
1471 type
= GET_ASI_DIRECT
;
1473 case ASI_KERNELDATA
: /* Supervisor data access */
1474 mem_idx
= MMU_KERNEL_IDX
;
1475 type
= GET_ASI_DIRECT
;
1477 case ASI_M_BYPASS
: /* MMU passthrough */
1478 case ASI_LEON_BYPASS
: /* LEON MMU passthrough */
1479 mem_idx
= MMU_PHYS_IDX
;
1480 type
= GET_ASI_DIRECT
;
1482 case ASI_M_BCOPY
: /* Block copy, sta access */
1483 mem_idx
= MMU_KERNEL_IDX
;
1484 type
= GET_ASI_BCOPY
;
1486 case ASI_M_BFILL
: /* Block fill, stda access */
1487 mem_idx
= MMU_KERNEL_IDX
;
1488 type
= GET_ASI_BFILL
;
1492 /* MMU_PHYS_IDX is used when the MMU is disabled to passthrough the
1493 * permissions check in get_physical_address(..).
1495 mem_idx
= (dc
->mem_idx
== MMU_PHYS_IDX
) ? MMU_PHYS_IDX
: mem_idx
;
1497 gen_exception(dc
, TT_PRIV_INSN
);
1498 type
= GET_ASI_EXCP
;
1504 /* With v9, all asis below 0x80 are privileged. */
1505 /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
1506 down that bit into DisasContext. For the moment that's ok,
1507 since the direct implementations below doesn't have any ASIs
1508 in the restricted [0x30, 0x7f] range, and the check will be
1509 done properly in the helper. */
1510 if (!supervisor(dc
) && asi
< 0x80) {
1511 gen_exception(dc
, TT_PRIV_ACT
);
1512 type
= GET_ASI_EXCP
;
1515 case ASI_REAL
: /* Bypass */
1516 case ASI_REAL_IO
: /* Bypass, non-cacheable */
1517 case ASI_REAL_L
: /* Bypass LE */
1518 case ASI_REAL_IO_L
: /* Bypass, non-cacheable LE */
1519 case ASI_TWINX_REAL
: /* Real address, twinx */
1520 case ASI_TWINX_REAL_L
: /* Real address, twinx, LE */
1521 case ASI_QUAD_LDD_PHYS
:
1522 case ASI_QUAD_LDD_PHYS_L
:
1523 mem_idx
= MMU_PHYS_IDX
;
1525 case ASI_N
: /* Nucleus */
1526 case ASI_NL
: /* Nucleus LE */
1529 case ASI_NUCLEUS_QUAD_LDD
:
1530 case ASI_NUCLEUS_QUAD_LDD_L
:
1531 if (hypervisor(dc
)) {
1532 mem_idx
= MMU_PHYS_IDX
;
1534 mem_idx
= MMU_NUCLEUS_IDX
;
1537 case ASI_AIUP
: /* As if user primary */
1538 case ASI_AIUPL
: /* As if user primary LE */
1539 case ASI_TWINX_AIUP
:
1540 case ASI_TWINX_AIUP_L
:
1541 case ASI_BLK_AIUP_4V
:
1542 case ASI_BLK_AIUP_L_4V
:
1545 mem_idx
= MMU_USER_IDX
;
1547 case ASI_AIUS
: /* As if user secondary */
1548 case ASI_AIUSL
: /* As if user secondary LE */
1549 case ASI_TWINX_AIUS
:
1550 case ASI_TWINX_AIUS_L
:
1551 case ASI_BLK_AIUS_4V
:
1552 case ASI_BLK_AIUS_L_4V
:
1555 mem_idx
= MMU_USER_SECONDARY_IDX
;
1557 case ASI_S
: /* Secondary */
1558 case ASI_SL
: /* Secondary LE */
1561 case ASI_BLK_COMMIT_S
:
1568 if (mem_idx
== MMU_USER_IDX
) {
1569 mem_idx
= MMU_USER_SECONDARY_IDX
;
1570 } else if (mem_idx
== MMU_KERNEL_IDX
) {
1571 mem_idx
= MMU_KERNEL_SECONDARY_IDX
;
1574 case ASI_P
: /* Primary */
1575 case ASI_PL
: /* Primary LE */
1578 case ASI_BLK_COMMIT_P
:
1602 type
= GET_ASI_DIRECT
;
1604 case ASI_TWINX_REAL
:
1605 case ASI_TWINX_REAL_L
:
1608 case ASI_TWINX_AIUP
:
1609 case ASI_TWINX_AIUP_L
:
1610 case ASI_TWINX_AIUS
:
1611 case ASI_TWINX_AIUS_L
:
1616 case ASI_QUAD_LDD_PHYS
:
1617 case ASI_QUAD_LDD_PHYS_L
:
1618 case ASI_NUCLEUS_QUAD_LDD
:
1619 case ASI_NUCLEUS_QUAD_LDD_L
:
1620 type
= GET_ASI_DTWINX
;
1622 case ASI_BLK_COMMIT_P
:
1623 case ASI_BLK_COMMIT_S
:
1624 case ASI_BLK_AIUP_4V
:
1625 case ASI_BLK_AIUP_L_4V
:
1628 case ASI_BLK_AIUS_4V
:
1629 case ASI_BLK_AIUS_L_4V
:
1636 type
= GET_ASI_BLOCK
;
1643 type
= GET_ASI_SHORT
;
1650 type
= GET_ASI_SHORT
;
1653 /* The little-endian asis all have bit 3 set. */
1661 return (DisasASI
){ type
, asi
, mem_idx
, memop
};
1664 #if defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
1665 static void gen_helper_ld_asi(TCGv_i64 r
, TCGv_env e
, TCGv a
,
1666 TCGv_i32 asi
, TCGv_i32 mop
)
1668 g_assert_not_reached();
1671 static void gen_helper_st_asi(TCGv_env e
, TCGv a
, TCGv_i64 r
,
1672 TCGv_i32 asi
, TCGv_i32 mop
)
1674 g_assert_not_reached();
1678 static void gen_ld_asi(DisasContext
*dc
, DisasASI
*da
, TCGv dst
, TCGv addr
)
1683 case GET_ASI_DTWINX
: /* Reserved for ldda. */
1684 gen_exception(dc
, TT_ILL_INSN
);
1686 case GET_ASI_DIRECT
:
1687 tcg_gen_qemu_ld_tl(dst
, addr
, da
->mem_idx
, da
->memop
| MO_ALIGN
);
1691 TCGv_i32 r_asi
= tcg_constant_i32(da
->asi
);
1692 TCGv_i32 r_mop
= tcg_constant_i32(da
->memop
| MO_ALIGN
);
1695 #ifdef TARGET_SPARC64
1696 gen_helper_ld_asi(dst
, tcg_env
, addr
, r_asi
, r_mop
);
1699 TCGv_i64 t64
= tcg_temp_new_i64();
1700 gen_helper_ld_asi(t64
, tcg_env
, addr
, r_asi
, r_mop
);
1701 tcg_gen_trunc_i64_tl(dst
, t64
);
1709 static void gen_st_asi(DisasContext
*dc
, DisasASI
*da
, TCGv src
, TCGv addr
)
1715 case GET_ASI_DTWINX
: /* Reserved for stda. */
1716 if (TARGET_LONG_BITS
== 32) {
1717 gen_exception(dc
, TT_ILL_INSN
);
1719 } else if (!(dc
->def
->features
& CPU_FEATURE_HYPV
)) {
1720 /* Pre OpenSPARC CPUs don't have these */
1721 gen_exception(dc
, TT_ILL_INSN
);
1724 /* In OpenSPARC T1+ CPUs TWINX ASIs in store are ST_BLKINIT_ ASIs */
1727 case GET_ASI_DIRECT
:
1728 tcg_gen_qemu_st_tl(src
, addr
, da
->mem_idx
, da
->memop
| MO_ALIGN
);
1732 assert(TARGET_LONG_BITS
== 32);
1734 * Copy 32 bytes from the address in SRC to ADDR.
1736 * From Ross RT625 hyperSPARC manual, section 4.6:
1737 * "Block Copy and Block Fill will work only on cache line boundaries."
1739 * It does not specify if an unaliged address is truncated or trapped.
1740 * Previous qemu behaviour was to truncate to 4 byte alignment, which
1741 * is obviously wrong. The only place I can see this used is in the
1742 * Linux kernel which begins with page alignment, advancing by 32,
1743 * so is always aligned. Assume truncation as the simpler option.
1745 * Since the loads and stores are paired, allow the copy to happen
1746 * in the host endianness. The copy need not be atomic.
1749 MemOp mop
= MO_128
| MO_ATOM_IFALIGN_PAIR
;
1750 TCGv saddr
= tcg_temp_new();
1751 TCGv daddr
= tcg_temp_new();
1752 TCGv_i128 tmp
= tcg_temp_new_i128();
1754 tcg_gen_andi_tl(saddr
, src
, -32);
1755 tcg_gen_andi_tl(daddr
, addr
, -32);
1756 tcg_gen_qemu_ld_i128(tmp
, saddr
, da
->mem_idx
, mop
);
1757 tcg_gen_qemu_st_i128(tmp
, daddr
, da
->mem_idx
, mop
);
1758 tcg_gen_addi_tl(saddr
, saddr
, 16);
1759 tcg_gen_addi_tl(daddr
, daddr
, 16);
1760 tcg_gen_qemu_ld_i128(tmp
, saddr
, da
->mem_idx
, mop
);
1761 tcg_gen_qemu_st_i128(tmp
, daddr
, da
->mem_idx
, mop
);
1767 TCGv_i32 r_asi
= tcg_constant_i32(da
->asi
);
1768 TCGv_i32 r_mop
= tcg_constant_i32(da
->memop
| MO_ALIGN
);
1771 #ifdef TARGET_SPARC64
1772 gen_helper_st_asi(tcg_env
, addr
, src
, r_asi
, r_mop
);
1775 TCGv_i64 t64
= tcg_temp_new_i64();
1776 tcg_gen_extu_tl_i64(t64
, src
);
1777 gen_helper_st_asi(tcg_env
, addr
, t64
, r_asi
, r_mop
);
1781 /* A write to a TLB register may alter page maps. End the TB. */
1782 dc
->npc
= DYNAMIC_PC
;
1788 static void gen_swap_asi(DisasContext
*dc
, DisasASI
*da
,
1789 TCGv dst
, TCGv src
, TCGv addr
)
1794 case GET_ASI_DIRECT
:
1795 tcg_gen_atomic_xchg_tl(dst
, addr
, src
,
1796 da
->mem_idx
, da
->memop
| MO_ALIGN
);
1799 /* ??? Should be DAE_invalid_asi. */
1800 gen_exception(dc
, TT_DATA_ACCESS
);
1805 static void gen_cas_asi(DisasContext
*dc
, DisasASI
*da
,
1806 TCGv oldv
, TCGv newv
, TCGv cmpv
, TCGv addr
)
1811 case GET_ASI_DIRECT
:
1812 tcg_gen_atomic_cmpxchg_tl(oldv
, addr
, cmpv
, newv
,
1813 da
->mem_idx
, da
->memop
| MO_ALIGN
);
1816 /* ??? Should be DAE_invalid_asi. */
1817 gen_exception(dc
, TT_DATA_ACCESS
);
1822 static void gen_ldstub_asi(DisasContext
*dc
, DisasASI
*da
, TCGv dst
, TCGv addr
)
1827 case GET_ASI_DIRECT
:
1828 tcg_gen_atomic_xchg_tl(dst
, addr
, tcg_constant_tl(0xff),
1829 da
->mem_idx
, MO_UB
);
1832 /* ??? In theory, this should be raise DAE_invalid_asi.
1833 But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
1834 if (tb_cflags(dc
->base
.tb
) & CF_PARALLEL
) {
1835 gen_helper_exit_atomic(tcg_env
);
1837 TCGv_i32 r_asi
= tcg_constant_i32(da
->asi
);
1838 TCGv_i32 r_mop
= tcg_constant_i32(MO_UB
);
1842 t64
= tcg_temp_new_i64();
1843 gen_helper_ld_asi(t64
, tcg_env
, addr
, r_asi
, r_mop
);
1845 s64
= tcg_constant_i64(0xff);
1846 gen_helper_st_asi(tcg_env
, addr
, s64
, r_asi
, r_mop
);
1848 tcg_gen_trunc_i64_tl(dst
, t64
);
1851 dc
->npc
= DYNAMIC_PC
;
1857 static void gen_ldf_asi(DisasContext
*dc
, DisasASI
*da
, MemOp orig_size
,
1860 MemOp memop
= da
->memop
;
1861 MemOp size
= memop
& MO_SIZE
;
1866 /* TODO: Use 128-bit load/store below. */
1867 if (size
== MO_128
) {
1868 memop
= (memop
& ~MO_SIZE
) | MO_64
;
1875 case GET_ASI_DIRECT
:
1876 memop
|= MO_ALIGN_4
;
1879 d32
= tcg_temp_new_i32();
1880 tcg_gen_qemu_ld_i32(d32
, addr
, da
->mem_idx
, memop
);
1881 gen_store_fpr_F(dc
, rd
, d32
);
1885 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
/ 2], addr
, da
->mem_idx
, memop
);
1889 d64
= tcg_temp_new_i64();
1890 tcg_gen_qemu_ld_i64(d64
, addr
, da
->mem_idx
, memop
);
1891 addr_tmp
= tcg_temp_new();
1892 tcg_gen_addi_tl(addr_tmp
, addr
, 8);
1893 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
/ 2 + 1], addr_tmp
, da
->mem_idx
, memop
);
1894 tcg_gen_mov_i64(cpu_fpr
[rd
/ 2], d64
);
1897 g_assert_not_reached();
1902 /* Valid for lddfa on aligned registers only. */
1903 if (orig_size
== MO_64
&& (rd
& 7) == 0) {
1904 /* The first operation checks required alignment. */
1905 addr_tmp
= tcg_temp_new();
1906 for (int i
= 0; ; ++i
) {
1907 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
/ 2 + i
], addr
, da
->mem_idx
,
1908 memop
| (i
== 0 ? MO_ALIGN_64
: 0));
1912 tcg_gen_addi_tl(addr_tmp
, addr
, 8);
1916 gen_exception(dc
, TT_ILL_INSN
);
1921 /* Valid for lddfa only. */
1922 if (orig_size
== MO_64
) {
1923 tcg_gen_qemu_ld_i64(cpu_fpr
[rd
/ 2], addr
, da
->mem_idx
,
1926 gen_exception(dc
, TT_ILL_INSN
);
1932 TCGv_i32 r_asi
= tcg_constant_i32(da
->asi
);
1933 TCGv_i32 r_mop
= tcg_constant_i32(memop
| MO_ALIGN
);
1936 /* According to the table in the UA2011 manual, the only
1937 other asis that are valid for ldfa/lddfa/ldqfa are
1938 the NO_FAULT asis. We still need a helper for these,
1939 but we can just use the integer asi helper for them. */
1942 d64
= tcg_temp_new_i64();
1943 gen_helper_ld_asi(d64
, tcg_env
, addr
, r_asi
, r_mop
);
1944 d32
= tcg_temp_new_i32();
1945 tcg_gen_extrl_i64_i32(d32
, d64
);
1946 gen_store_fpr_F(dc
, rd
, d32
);
1949 gen_helper_ld_asi(cpu_fpr
[rd
/ 2], tcg_env
, addr
,
1953 d64
= tcg_temp_new_i64();
1954 gen_helper_ld_asi(d64
, tcg_env
, addr
, r_asi
, r_mop
);
1955 addr_tmp
= tcg_temp_new();
1956 tcg_gen_addi_tl(addr_tmp
, addr
, 8);
1957 gen_helper_ld_asi(cpu_fpr
[rd
/ 2 + 1], tcg_env
, addr_tmp
,
1959 tcg_gen_mov_i64(cpu_fpr
[rd
/ 2], d64
);
1962 g_assert_not_reached();
1969 static void gen_stf_asi(DisasContext
*dc
, DisasASI
*da
, MemOp orig_size
,
1972 MemOp memop
= da
->memop
;
1973 MemOp size
= memop
& MO_SIZE
;
1977 /* TODO: Use 128-bit load/store below. */
1978 if (size
== MO_128
) {
1979 memop
= (memop
& ~MO_SIZE
) | MO_64
;
1986 case GET_ASI_DIRECT
:
1987 memop
|= MO_ALIGN_4
;
1990 d32
= gen_load_fpr_F(dc
, rd
);
1991 tcg_gen_qemu_st_i32(d32
, addr
, da
->mem_idx
, memop
| MO_ALIGN
);
1994 tcg_gen_qemu_st_i64(cpu_fpr
[rd
/ 2], addr
, da
->mem_idx
,
1995 memop
| MO_ALIGN_4
);
1998 /* Only 4-byte alignment required. However, it is legal for the
1999 cpu to signal the alignment fault, and the OS trap handler is
2000 required to fix it up. Requiring 16-byte alignment here avoids
2001 having to probe the second page before performing the first
2003 tcg_gen_qemu_st_i64(cpu_fpr
[rd
/ 2], addr
, da
->mem_idx
,
2004 memop
| MO_ALIGN_16
);
2005 addr_tmp
= tcg_temp_new();
2006 tcg_gen_addi_tl(addr_tmp
, addr
, 8);
2007 tcg_gen_qemu_st_i64(cpu_fpr
[rd
/ 2 + 1], addr_tmp
, da
->mem_idx
, memop
);
2010 g_assert_not_reached();
2015 /* Valid for stdfa on aligned registers only. */
2016 if (orig_size
== MO_64
&& (rd
& 7) == 0) {
2017 /* The first operation checks required alignment. */
2018 addr_tmp
= tcg_temp_new();
2019 for (int i
= 0; ; ++i
) {
2020 tcg_gen_qemu_st_i64(cpu_fpr
[rd
/ 2 + i
], addr
, da
->mem_idx
,
2021 memop
| (i
== 0 ? MO_ALIGN_64
: 0));
2025 tcg_gen_addi_tl(addr_tmp
, addr
, 8);
2029 gen_exception(dc
, TT_ILL_INSN
);
2034 /* Valid for stdfa only. */
2035 if (orig_size
== MO_64
) {
2036 tcg_gen_qemu_st_i64(cpu_fpr
[rd
/ 2], addr
, da
->mem_idx
,
2039 gen_exception(dc
, TT_ILL_INSN
);
2044 /* According to the table in the UA2011 manual, the only
2045 other asis that are valid for ldfa/lddfa/ldqfa are
2046 the PST* asis, which aren't currently handled. */
2047 gen_exception(dc
, TT_ILL_INSN
);
2052 static void gen_ldda_asi(DisasContext
*dc
, DisasASI
*da
, TCGv addr
, int rd
)
2054 TCGv hi
= gen_dest_gpr(dc
, rd
);
2055 TCGv lo
= gen_dest_gpr(dc
, rd
+ 1);
2061 case GET_ASI_DTWINX
:
2062 #ifdef TARGET_SPARC64
2064 MemOp mop
= (da
->memop
& MO_BSWAP
) | MO_128
| MO_ALIGN_16
;
2065 TCGv_i128 t
= tcg_temp_new_i128();
2067 tcg_gen_qemu_ld_i128(t
, addr
, da
->mem_idx
, mop
);
2069 * Note that LE twinx acts as if each 64-bit register result is
2070 * byte swapped. We perform one 128-bit LE load, so must swap
2071 * the order of the writebacks.
2073 if ((mop
& MO_BSWAP
) == MO_TE
) {
2074 tcg_gen_extr_i128_i64(lo
, hi
, t
);
2076 tcg_gen_extr_i128_i64(hi
, lo
, t
);
2081 g_assert_not_reached();
2084 case GET_ASI_DIRECT
:
2086 TCGv_i64 tmp
= tcg_temp_new_i64();
2088 tcg_gen_qemu_ld_i64(tmp
, addr
, da
->mem_idx
, da
->memop
| MO_ALIGN
);
2090 /* Note that LE ldda acts as if each 32-bit register
2091 result is byte swapped. Having just performed one
2092 64-bit bswap, we need now to swap the writebacks. */
2093 if ((da
->memop
& MO_BSWAP
) == MO_TE
) {
2094 tcg_gen_extr_i64_tl(lo
, hi
, tmp
);
2096 tcg_gen_extr_i64_tl(hi
, lo
, tmp
);
2102 /* ??? In theory we've handled all of the ASIs that are valid
2103 for ldda, and this should raise DAE_invalid_asi. However,
2104 real hardware allows others. This can be seen with e.g.
2105 FreeBSD 10.3 wrt ASI_IC_TAG. */
2107 TCGv_i32 r_asi
= tcg_constant_i32(da
->asi
);
2108 TCGv_i32 r_mop
= tcg_constant_i32(da
->memop
);
2109 TCGv_i64 tmp
= tcg_temp_new_i64();
2112 gen_helper_ld_asi(tmp
, tcg_env
, addr
, r_asi
, r_mop
);
2115 if ((da
->memop
& MO_BSWAP
) == MO_TE
) {
2116 tcg_gen_extr_i64_tl(lo
, hi
, tmp
);
2118 tcg_gen_extr_i64_tl(hi
, lo
, tmp
);
2124 gen_store_gpr(dc
, rd
, hi
);
2125 gen_store_gpr(dc
, rd
+ 1, lo
);
2128 static void gen_stda_asi(DisasContext
*dc
, DisasASI
*da
, TCGv addr
, int rd
)
2130 TCGv hi
= gen_load_gpr(dc
, rd
);
2131 TCGv lo
= gen_load_gpr(dc
, rd
+ 1);
2137 case GET_ASI_DTWINX
:
2138 #ifdef TARGET_SPARC64
2140 MemOp mop
= (da
->memop
& MO_BSWAP
) | MO_128
| MO_ALIGN_16
;
2141 TCGv_i128 t
= tcg_temp_new_i128();
2144 * Note that LE twinx acts as if each 64-bit register result is
2145 * byte swapped. We perform one 128-bit LE store, so must swap
2146 * the order of the construction.
2148 if ((mop
& MO_BSWAP
) == MO_TE
) {
2149 tcg_gen_concat_i64_i128(t
, lo
, hi
);
2151 tcg_gen_concat_i64_i128(t
, hi
, lo
);
2153 tcg_gen_qemu_st_i128(t
, addr
, da
->mem_idx
, mop
);
2157 g_assert_not_reached();
2160 case GET_ASI_DIRECT
:
2162 TCGv_i64 t64
= tcg_temp_new_i64();
2164 /* Note that LE stda acts as if each 32-bit register result is
2165 byte swapped. We will perform one 64-bit LE store, so now
2166 we must swap the order of the construction. */
2167 if ((da
->memop
& MO_BSWAP
) == MO_TE
) {
2168 tcg_gen_concat_tl_i64(t64
, lo
, hi
);
2170 tcg_gen_concat_tl_i64(t64
, hi
, lo
);
2172 tcg_gen_qemu_st_i64(t64
, addr
, da
->mem_idx
, da
->memop
| MO_ALIGN
);
2177 assert(TARGET_LONG_BITS
== 32);
2179 * Store 32 bytes of [rd:rd+1] to ADDR.
2180 * See comments for GET_ASI_COPY above.
2183 MemOp mop
= MO_TE
| MO_128
| MO_ATOM_IFALIGN_PAIR
;
2184 TCGv_i64 t8
= tcg_temp_new_i64();
2185 TCGv_i128 t16
= tcg_temp_new_i128();
2186 TCGv daddr
= tcg_temp_new();
2188 tcg_gen_concat_tl_i64(t8
, lo
, hi
);
2189 tcg_gen_concat_i64_i128(t16
, t8
, t8
);
2190 tcg_gen_andi_tl(daddr
, addr
, -32);
2191 tcg_gen_qemu_st_i128(t16
, daddr
, da
->mem_idx
, mop
);
2192 tcg_gen_addi_tl(daddr
, daddr
, 16);
2193 tcg_gen_qemu_st_i128(t16
, daddr
, da
->mem_idx
, mop
);
2198 /* ??? In theory we've handled all of the ASIs that are valid
2199 for stda, and this should raise DAE_invalid_asi. */
2201 TCGv_i32 r_asi
= tcg_constant_i32(da
->asi
);
2202 TCGv_i32 r_mop
= tcg_constant_i32(da
->memop
);
2203 TCGv_i64 t64
= tcg_temp_new_i64();
2206 if ((da
->memop
& MO_BSWAP
) == MO_TE
) {
2207 tcg_gen_concat_tl_i64(t64
, lo
, hi
);
2209 tcg_gen_concat_tl_i64(t64
, hi
, lo
);
2213 gen_helper_st_asi(tcg_env
, addr
, t64
, r_asi
, r_mop
);
2219 static void gen_fmovs(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2221 #ifdef TARGET_SPARC64
2222 TCGv_i32 c32
, zero
, dst
, s1
, s2
;
2223 TCGv_i64 c64
= tcg_temp_new_i64();
2225 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2226 or fold the comparison down to 32 bits and use movcond_i32. Choose
2228 c32
= tcg_temp_new_i32();
2229 tcg_gen_setcondi_i64(cmp
->cond
, c64
, cmp
->c1
, cmp
->c2
);
2230 tcg_gen_extrl_i64_i32(c32
, c64
);
2232 s1
= gen_load_fpr_F(dc
, rs
);
2233 s2
= gen_load_fpr_F(dc
, rd
);
2234 dst
= tcg_temp_new_i32();
2235 zero
= tcg_constant_i32(0);
2237 tcg_gen_movcond_i32(TCG_COND_NE
, dst
, c32
, zero
, s1
, s2
);
2239 gen_store_fpr_F(dc
, rd
, dst
);
2241 qemu_build_not_reached();
2245 static void gen_fmovd(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2247 #ifdef TARGET_SPARC64
2248 TCGv_i64 dst
= gen_dest_fpr_D(dc
, rd
);
2249 tcg_gen_movcond_i64(cmp
->cond
, dst
, cmp
->c1
, tcg_constant_tl(cmp
->c2
),
2250 gen_load_fpr_D(dc
, rs
),
2251 gen_load_fpr_D(dc
, rd
));
2252 gen_store_fpr_D(dc
, rd
, dst
);
2254 qemu_build_not_reached();
2258 static void gen_fmovq(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, int rs
)
2260 #ifdef TARGET_SPARC64
2261 int qd
= QFPREG(rd
);
2262 int qs
= QFPREG(rs
);
2263 TCGv c2
= tcg_constant_tl(cmp
->c2
);
2265 tcg_gen_movcond_i64(cmp
->cond
, cpu_fpr
[qd
/ 2], cmp
->c1
, c2
,
2266 cpu_fpr
[qs
/ 2], cpu_fpr
[qd
/ 2]);
2267 tcg_gen_movcond_i64(cmp
->cond
, cpu_fpr
[qd
/ 2 + 1], cmp
->c1
, c2
,
2268 cpu_fpr
[qs
/ 2 + 1], cpu_fpr
[qd
/ 2 + 1]);
2270 gen_update_fprs_dirty(dc
, qd
);
2272 qemu_build_not_reached();
2276 #ifdef TARGET_SPARC64
2277 static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr
)
2279 TCGv_i32 r_tl
= tcg_temp_new_i32();
2281 /* load env->tl into r_tl */
2282 tcg_gen_ld_i32(r_tl
, tcg_env
, offsetof(CPUSPARCState
, tl
));
2284 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
2285 tcg_gen_andi_i32(r_tl
, r_tl
, MAXTL_MASK
);
2287 /* calculate offset to current trap state from env->ts, reuse r_tl */
2288 tcg_gen_muli_i32(r_tl
, r_tl
, sizeof (trap_state
));
2289 tcg_gen_addi_ptr(r_tsptr
, tcg_env
, offsetof(CPUSPARCState
, ts
));
2291 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
2293 TCGv_ptr r_tl_tmp
= tcg_temp_new_ptr();
2294 tcg_gen_ext_i32_ptr(r_tl_tmp
, r_tl
);
2295 tcg_gen_add_ptr(r_tsptr
, r_tsptr
, r_tl_tmp
);
2300 static int extract_dfpreg(DisasContext
*dc
, int x
)
2305 static int extract_qfpreg(DisasContext
*dc
, int x
)
2310 /* Include the auto-generated decoder. */
2311 #include "decode-insns.c.inc"
2313 #define TRANS(NAME, AVAIL, FUNC, ...) \
2314 static bool trans_##NAME(DisasContext *dc, arg_##NAME *a) \
2315 { return avail_##AVAIL(dc) && FUNC(dc, __VA_ARGS__); }
2317 #define avail_ALL(C) true
2318 #ifdef TARGET_SPARC64
2319 # define avail_32(C) false
2320 # define avail_ASR17(C) false
2321 # define avail_CASA(C) true
2322 # define avail_DIV(C) true
2323 # define avail_MUL(C) true
2324 # define avail_POWERDOWN(C) false
2325 # define avail_64(C) true
2326 # define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL)
2327 # define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
2328 # define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1)
2329 # define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2)
2331 # define avail_32(C) true
2332 # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
2333 # define avail_CASA(C) ((C)->def->features & CPU_FEATURE_CASA)
2334 # define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV)
2335 # define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL)
2336 # define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN)
2337 # define avail_64(C) false
2338 # define avail_GL(C) false
2339 # define avail_HYPV(C) false
2340 # define avail_VIS1(C) false
2341 # define avail_VIS2(C) false
2344 /* Default case for non jump instructions. */
2345 static bool advance_pc(DisasContext
*dc
)
2354 case DYNAMIC_PC_LOOKUP
:
2356 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
2357 tcg_gen_addi_tl(cpu_npc
, cpu_npc
, 4);
2361 /* we can do a static jump */
2362 l1
= gen_new_label();
2363 tcg_gen_brcondi_tl(dc
->jump
.cond
, dc
->jump
.c1
, dc
->jump
.c2
, l1
);
2365 /* jump not taken */
2366 gen_goto_tb(dc
, 1, dc
->jump_pc
[1], dc
->jump_pc
[1] + 4);
2370 gen_goto_tb(dc
, 0, dc
->jump_pc
[0], dc
->jump_pc
[0] + 4);
2372 dc
->base
.is_jmp
= DISAS_NORETURN
;
2376 g_assert_not_reached();
2380 dc
->npc
= dc
->npc
+ 4;
2386 * Major opcodes 00 and 01 -- branches, call, and sethi
2389 static bool advance_jump_cond(DisasContext
*dc
, DisasCompare
*cmp
,
2390 bool annul
, int disp
)
2392 target_ulong dest
= address_mask_i(dc
, dc
->pc
+ disp
* 4);
2397 if (cmp
->cond
== TCG_COND_ALWAYS
) {
2408 if (cmp
->cond
== TCG_COND_NEVER
) {
2413 tcg_gen_addi_tl(cpu_pc
, cpu_pc
, 4);
2415 tcg_gen_addi_tl(cpu_npc
, cpu_pc
, 4);
2417 dc
->pc
= npc
+ (annul
? 4 : 0);
2418 dc
->npc
= dc
->pc
+ 4;
2427 TCGLabel
*l1
= gen_new_label();
2429 tcg_gen_brcondi_tl(tcg_invert_cond(cmp
->cond
), cmp
->c1
, cmp
->c2
, l1
);
2430 gen_goto_tb(dc
, 0, npc
, dest
);
2432 gen_goto_tb(dc
, 1, npc
+ 4, npc
+ 8);
2434 dc
->base
.is_jmp
= DISAS_NORETURN
;
2439 case DYNAMIC_PC_LOOKUP
:
2440 tcg_gen_mov_tl(cpu_pc
, cpu_npc
);
2441 tcg_gen_addi_tl(cpu_npc
, cpu_npc
, 4);
2442 tcg_gen_movcond_tl(cmp
->cond
, cpu_npc
,
2443 cmp
->c1
, tcg_constant_tl(cmp
->c2
),
2444 tcg_constant_tl(dest
), cpu_npc
);
2448 g_assert_not_reached();
2454 dc
->jump_pc
[0] = dest
;
2455 dc
->jump_pc
[1] = npc
+ 4;
2457 /* The condition for cpu_cond is always NE -- normalize. */
2458 if (cmp
->cond
== TCG_COND_NE
) {
2459 tcg_gen_xori_tl(cpu_cond
, cmp
->c1
, cmp
->c2
);
2461 tcg_gen_setcondi_tl(cmp
->cond
, cpu_cond
, cmp
->c1
, cmp
->c2
);
2463 dc
->cpu_cond_live
= true;
2469 static bool raise_priv(DisasContext
*dc
)
2471 gen_exception(dc
, TT_PRIV_INSN
);
2475 static bool raise_unimpfpop(DisasContext
*dc
)
2477 gen_op_fpexception_im(dc
, FSR_FTT_UNIMPFPOP
);
2481 static bool gen_trap_float128(DisasContext
*dc
)
2483 if (dc
->def
->features
& CPU_FEATURE_FLOAT128
) {
2486 return raise_unimpfpop(dc
);
2489 static bool do_bpcc(DisasContext
*dc
, arg_bcc
*a
)
2493 gen_compare(&cmp
, a
->cc
, a
->cond
, dc
);
2494 return advance_jump_cond(dc
, &cmp
, a
->a
, a
->i
);
2497 TRANS(Bicc
, ALL
, do_bpcc
, a
)
2498 TRANS(BPcc
, 64, do_bpcc
, a
)
2500 static bool do_fbpfcc(DisasContext
*dc
, arg_bcc
*a
)
2504 if (gen_trap_ifnofpu(dc
)) {
2507 gen_fcompare(&cmp
, a
->cc
, a
->cond
);
2508 return advance_jump_cond(dc
, &cmp
, a
->a
, a
->i
);
2511 TRANS(FBPfcc
, 64, do_fbpfcc
, a
)
2512 TRANS(FBfcc
, ALL
, do_fbpfcc
, a
)
2514 static bool trans_BPr(DisasContext
*dc
, arg_BPr
*a
)
2518 if (!avail_64(dc
)) {
2521 if (!gen_compare_reg(&cmp
, a
->cond
, gen_load_gpr(dc
, a
->rs1
))) {
2524 return advance_jump_cond(dc
, &cmp
, a
->a
, a
->i
);
2527 static bool trans_CALL(DisasContext
*dc
, arg_CALL
*a
)
2529 target_long target
= address_mask_i(dc
, dc
->pc
+ a
->i
* 4);
2531 gen_store_gpr(dc
, 15, tcg_constant_tl(dc
->pc
));
2537 static bool trans_NCP(DisasContext
*dc
, arg_NCP
*a
)
2540 * For sparc32, always generate the no-coprocessor exception.
2541 * For sparc64, always generate illegal instruction.
2543 #ifdef TARGET_SPARC64
2546 gen_exception(dc
, TT_NCP_INSN
);
2551 static bool trans_SETHI(DisasContext
*dc
, arg_SETHI
*a
)
2553 /* Special-case %g0 because that's the canonical nop. */
2555 gen_store_gpr(dc
, a
->rd
, tcg_constant_tl((uint32_t)a
->i
<< 10));
2557 return advance_pc(dc
);
2561 * Major Opcode 10 -- integer, floating-point, vis, and system insns.
2564 static bool do_tcc(DisasContext
*dc
, int cond
, int cc
,
2565 int rs1
, bool imm
, int rs2_or_imm
)
2567 int mask
= ((dc
->def
->features
& CPU_FEATURE_HYPV
) && supervisor(dc
)
2568 ? UA2005_HTRAP_MASK
: V8_TRAP_MASK
);
2575 return advance_pc(dc
);
2579 * Immediate traps are the most common case. Since this value is
2580 * live across the branch, it really pays to evaluate the constant.
2582 if (rs1
== 0 && (imm
|| rs2_or_imm
== 0)) {
2583 trap
= tcg_constant_i32((rs2_or_imm
& mask
) + TT_TRAP
);
2585 trap
= tcg_temp_new_i32();
2586 tcg_gen_trunc_tl_i32(trap
, gen_load_gpr(dc
, rs1
));
2588 tcg_gen_addi_i32(trap
, trap
, rs2_or_imm
);
2590 TCGv_i32 t2
= tcg_temp_new_i32();
2591 tcg_gen_trunc_tl_i32(t2
, gen_load_gpr(dc
, rs2_or_imm
));
2592 tcg_gen_add_i32(trap
, trap
, t2
);
2594 tcg_gen_andi_i32(trap
, trap
, mask
);
2595 tcg_gen_addi_i32(trap
, trap
, TT_TRAP
);
2603 gen_helper_raise_exception(tcg_env
, trap
);
2604 dc
->base
.is_jmp
= DISAS_NORETURN
;
2608 /* Conditional trap. */
2610 lab
= delay_exceptionv(dc
, trap
);
2611 gen_compare(&cmp
, cc
, cond
, dc
);
2612 tcg_gen_brcondi_tl(cmp
.cond
, cmp
.c1
, cmp
.c2
, lab
);
2614 return advance_pc(dc
);
2617 static bool trans_Tcc_r(DisasContext
*dc
, arg_Tcc_r
*a
)
2619 if (avail_32(dc
) && a
->cc
) {
2622 return do_tcc(dc
, a
->cond
, a
->cc
, a
->rs1
, false, a
->rs2
);
2625 static bool trans_Tcc_i_v7(DisasContext
*dc
, arg_Tcc_i_v7
*a
)
2630 return do_tcc(dc
, a
->cond
, 0, a
->rs1
, true, a
->i
);
2633 static bool trans_Tcc_i_v9(DisasContext
*dc
, arg_Tcc_i_v9
*a
)
2638 return do_tcc(dc
, a
->cond
, a
->cc
, a
->rs1
, true, a
->i
);
2641 static bool trans_STBAR(DisasContext
*dc
, arg_STBAR
*a
)
2643 tcg_gen_mb(TCG_MO_ST_ST
| TCG_BAR_SC
);
2644 return advance_pc(dc
);
2647 static bool trans_MEMBAR(DisasContext
*dc
, arg_MEMBAR
*a
)
2653 /* Note TCG_MO_* was modeled on sparc64, so mmask matches. */
2654 tcg_gen_mb(a
->mmask
| TCG_BAR_SC
);
2657 /* For #Sync, etc, end the TB to recognize interrupts. */
2658 dc
->base
.is_jmp
= DISAS_EXIT
;
2660 return advance_pc(dc
);
2663 static bool do_rd_special(DisasContext
*dc
, bool priv
, int rd
,
2664 TCGv (*func
)(DisasContext
*, TCGv
))
2667 return raise_priv(dc
);
2669 gen_store_gpr(dc
, rd
, func(dc
, gen_dest_gpr(dc
, rd
)));
2670 return advance_pc(dc
);
2673 static TCGv
do_rdy(DisasContext
*dc
, TCGv dst
)
2678 static bool trans_RDY(DisasContext
*dc
, arg_RDY
*a
)
2681 * TODO: Need a feature bit for sparcv8. In the meantime, treat all
2682 * 32-bit cpus like sparcv7, which ignores the rs1 field.
2683 * This matches after all other ASR, so Leon3 Asr17 is handled first.
2685 if (avail_64(dc
) && a
->rs1
!= 0) {
2688 return do_rd_special(dc
, true, a
->rd
, do_rdy
);
2691 static TCGv
do_rd_leon3_config(DisasContext
*dc
, TCGv dst
)
2696 * TODO: There are many more fields to be filled,
2697 * some of which are writable.
2699 val
= dc
->def
->nwindows
- 1; /* [4:0] NWIN */
2700 val
|= 1 << 8; /* [8] V8 */
2702 return tcg_constant_tl(val
);
2705 TRANS(RDASR17
, ASR17
, do_rd_special
, true, a
->rd
, do_rd_leon3_config
)
2707 static TCGv
do_rdccr(DisasContext
*dc
, TCGv dst
)
2709 gen_helper_rdccr(dst
, tcg_env
);
2713 TRANS(RDCCR
, 64, do_rd_special
, true, a
->rd
, do_rdccr
)
2715 static TCGv
do_rdasi(DisasContext
*dc
, TCGv dst
)
2717 #ifdef TARGET_SPARC64
2718 return tcg_constant_tl(dc
->asi
);
2720 qemu_build_not_reached();
2724 TRANS(RDASI
, 64, do_rd_special
, true, a
->rd
, do_rdasi
)
2726 static TCGv
do_rdtick(DisasContext
*dc
, TCGv dst
)
2728 TCGv_ptr r_tickptr
= tcg_temp_new_ptr();
2730 tcg_gen_ld_ptr(r_tickptr
, tcg_env
, env64_field_offsetof(tick
));
2731 if (translator_io_start(&dc
->base
)) {
2732 dc
->base
.is_jmp
= DISAS_EXIT
;
2734 gen_helper_tick_get_count(dst
, tcg_env
, r_tickptr
,
2735 tcg_constant_i32(dc
->mem_idx
));
2739 /* TODO: non-priv access only allowed when enabled. */
2740 TRANS(RDTICK
, 64, do_rd_special
, true, a
->rd
, do_rdtick
)
2742 static TCGv
do_rdpc(DisasContext
*dc
, TCGv dst
)
2744 return tcg_constant_tl(address_mask_i(dc
, dc
->pc
));
2747 TRANS(RDPC
, 64, do_rd_special
, true, a
->rd
, do_rdpc
)
2749 static TCGv
do_rdfprs(DisasContext
*dc
, TCGv dst
)
2751 tcg_gen_ext_i32_tl(dst
, cpu_fprs
);
2755 TRANS(RDFPRS
, 64, do_rd_special
, true, a
->rd
, do_rdfprs
)
2757 static TCGv
do_rdgsr(DisasContext
*dc
, TCGv dst
)
2759 gen_trap_ifnofpu(dc
);
2763 TRANS(RDGSR
, 64, do_rd_special
, true, a
->rd
, do_rdgsr
)
2765 static TCGv
do_rdsoftint(DisasContext
*dc
, TCGv dst
)
2767 tcg_gen_ld32s_tl(dst
, tcg_env
, env64_field_offsetof(softint
));
2771 TRANS(RDSOFTINT
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdsoftint
)
2773 static TCGv
do_rdtick_cmpr(DisasContext
*dc
, TCGv dst
)
2775 tcg_gen_ld_tl(dst
, tcg_env
, env64_field_offsetof(tick_cmpr
));
2779 /* TODO: non-priv access only allowed when enabled. */
2780 TRANS(RDTICK_CMPR
, 64, do_rd_special
, true, a
->rd
, do_rdtick_cmpr
)
2782 static TCGv
do_rdstick(DisasContext
*dc
, TCGv dst
)
2784 TCGv_ptr r_tickptr
= tcg_temp_new_ptr();
2786 tcg_gen_ld_ptr(r_tickptr
, tcg_env
, env64_field_offsetof(stick
));
2787 if (translator_io_start(&dc
->base
)) {
2788 dc
->base
.is_jmp
= DISAS_EXIT
;
2790 gen_helper_tick_get_count(dst
, tcg_env
, r_tickptr
,
2791 tcg_constant_i32(dc
->mem_idx
));
2795 /* TODO: non-priv access only allowed when enabled. */
2796 TRANS(RDSTICK
, 64, do_rd_special
, true, a
->rd
, do_rdstick
)
2798 static TCGv
do_rdstick_cmpr(DisasContext
*dc
, TCGv dst
)
2800 tcg_gen_ld_tl(dst
, tcg_env
, env64_field_offsetof(stick_cmpr
));
2804 /* TODO: supervisor access only allowed when enabled by hypervisor. */
2805 TRANS(RDSTICK_CMPR
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdstick_cmpr
)
2808 * UltraSPARC-T1 Strand status.
2809 * HYPV check maybe not enough, UA2005 & UA2007 describe
2810 * this ASR as impl. dep
2812 static TCGv
do_rdstrand_status(DisasContext
*dc
, TCGv dst
)
2814 return tcg_constant_tl(1);
2817 TRANS(RDSTRAND_STATUS
, HYPV
, do_rd_special
, true, a
->rd
, do_rdstrand_status
)
2819 static TCGv
do_rdpsr(DisasContext
*dc
, TCGv dst
)
2821 gen_helper_rdpsr(dst
, tcg_env
);
2825 TRANS(RDPSR
, 32, do_rd_special
, supervisor(dc
), a
->rd
, do_rdpsr
)
2827 static TCGv
do_rdhpstate(DisasContext
*dc
, TCGv dst
)
2829 tcg_gen_ld_tl(dst
, tcg_env
, env64_field_offsetof(hpstate
));
2833 TRANS(RDHPR_hpstate
, HYPV
, do_rd_special
, hypervisor(dc
), a
->rd
, do_rdhpstate
)
2835 static TCGv
do_rdhtstate(DisasContext
*dc
, TCGv dst
)
2837 TCGv_i32 tl
= tcg_temp_new_i32();
2838 TCGv_ptr tp
= tcg_temp_new_ptr();
2840 tcg_gen_ld_i32(tl
, tcg_env
, env64_field_offsetof(tl
));
2841 tcg_gen_andi_i32(tl
, tl
, MAXTL_MASK
);
2842 tcg_gen_shli_i32(tl
, tl
, 3);
2843 tcg_gen_ext_i32_ptr(tp
, tl
);
2844 tcg_gen_add_ptr(tp
, tp
, tcg_env
);
2846 tcg_gen_ld_tl(dst
, tp
, env64_field_offsetof(htstate
));
2850 TRANS(RDHPR_htstate
, HYPV
, do_rd_special
, hypervisor(dc
), a
->rd
, do_rdhtstate
)
2852 static TCGv
do_rdhintp(DisasContext
*dc
, TCGv dst
)
2854 tcg_gen_ld_tl(dst
, tcg_env
, env64_field_offsetof(hintp
));
2858 TRANS(RDHPR_hintp
, HYPV
, do_rd_special
, hypervisor(dc
), a
->rd
, do_rdhintp
)
2860 static TCGv
do_rdhtba(DisasContext
*dc
, TCGv dst
)
2862 tcg_gen_ld_tl(dst
, tcg_env
, env64_field_offsetof(htba
));
2866 TRANS(RDHPR_htba
, HYPV
, do_rd_special
, hypervisor(dc
), a
->rd
, do_rdhtba
)
2868 static TCGv
do_rdhver(DisasContext
*dc
, TCGv dst
)
2870 tcg_gen_ld_tl(dst
, tcg_env
, env64_field_offsetof(hver
));
2874 TRANS(RDHPR_hver
, HYPV
, do_rd_special
, hypervisor(dc
), a
->rd
, do_rdhver
)
2876 static TCGv
do_rdhstick_cmpr(DisasContext
*dc
, TCGv dst
)
2878 tcg_gen_ld_tl(dst
, tcg_env
, env64_field_offsetof(hstick_cmpr
));
2882 TRANS(RDHPR_hstick_cmpr
, HYPV
, do_rd_special
, hypervisor(dc
), a
->rd
,
2885 static TCGv
do_rdwim(DisasContext
*dc
, TCGv dst
)
2887 tcg_gen_ld_tl(dst
, tcg_env
, env32_field_offsetof(wim
));
2891 TRANS(RDWIM
, 32, do_rd_special
, supervisor(dc
), a
->rd
, do_rdwim
)
2893 static TCGv
do_rdtpc(DisasContext
*dc
, TCGv dst
)
2895 #ifdef TARGET_SPARC64
2896 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
2898 gen_load_trap_state_at_tl(r_tsptr
);
2899 tcg_gen_ld_tl(dst
, r_tsptr
, offsetof(trap_state
, tpc
));
2902 qemu_build_not_reached();
2906 TRANS(RDPR_tpc
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdtpc
)
2908 static TCGv
do_rdtnpc(DisasContext
*dc
, TCGv dst
)
2910 #ifdef TARGET_SPARC64
2911 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
2913 gen_load_trap_state_at_tl(r_tsptr
);
2914 tcg_gen_ld_tl(dst
, r_tsptr
, offsetof(trap_state
, tnpc
));
2917 qemu_build_not_reached();
2921 TRANS(RDPR_tnpc
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdtnpc
)
2923 static TCGv
do_rdtstate(DisasContext
*dc
, TCGv dst
)
2925 #ifdef TARGET_SPARC64
2926 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
2928 gen_load_trap_state_at_tl(r_tsptr
);
2929 tcg_gen_ld_tl(dst
, r_tsptr
, offsetof(trap_state
, tstate
));
2932 qemu_build_not_reached();
2936 TRANS(RDPR_tstate
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdtstate
)
2938 static TCGv
do_rdtt(DisasContext
*dc
, TCGv dst
)
2940 #ifdef TARGET_SPARC64
2941 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
2943 gen_load_trap_state_at_tl(r_tsptr
);
2944 tcg_gen_ld32s_tl(dst
, r_tsptr
, offsetof(trap_state
, tt
));
2947 qemu_build_not_reached();
2951 TRANS(RDPR_tt
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdtt
)
2952 TRANS(RDPR_tick
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdtick
)
2954 static TCGv
do_rdtba(DisasContext
*dc
, TCGv dst
)
2959 TRANS(RDTBR
, 32, do_rd_special
, supervisor(dc
), a
->rd
, do_rdtba
)
2960 TRANS(RDPR_tba
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdtba
)
2962 static TCGv
do_rdpstate(DisasContext
*dc
, TCGv dst
)
2964 tcg_gen_ld32s_tl(dst
, tcg_env
, env64_field_offsetof(pstate
));
2968 TRANS(RDPR_pstate
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdpstate
)
2970 static TCGv
do_rdtl(DisasContext
*dc
, TCGv dst
)
2972 tcg_gen_ld32s_tl(dst
, tcg_env
, env64_field_offsetof(tl
));
2976 TRANS(RDPR_tl
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdtl
)
2978 static TCGv
do_rdpil(DisasContext
*dc
, TCGv dst
)
2980 tcg_gen_ld32s_tl(dst
, tcg_env
, env_field_offsetof(psrpil
));
2984 TRANS(RDPR_pil
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdpil
)
2986 static TCGv
do_rdcwp(DisasContext
*dc
, TCGv dst
)
2988 gen_helper_rdcwp(dst
, tcg_env
);
2992 TRANS(RDPR_cwp
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdcwp
)
2994 static TCGv
do_rdcansave(DisasContext
*dc
, TCGv dst
)
2996 tcg_gen_ld32s_tl(dst
, tcg_env
, env64_field_offsetof(cansave
));
3000 TRANS(RDPR_cansave
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdcansave
)
3002 static TCGv
do_rdcanrestore(DisasContext
*dc
, TCGv dst
)
3004 tcg_gen_ld32s_tl(dst
, tcg_env
, env64_field_offsetof(canrestore
));
3008 TRANS(RDPR_canrestore
, 64, do_rd_special
, supervisor(dc
), a
->rd
,
3011 static TCGv
do_rdcleanwin(DisasContext
*dc
, TCGv dst
)
3013 tcg_gen_ld32s_tl(dst
, tcg_env
, env64_field_offsetof(cleanwin
));
3017 TRANS(RDPR_cleanwin
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdcleanwin
)
3019 static TCGv
do_rdotherwin(DisasContext
*dc
, TCGv dst
)
3021 tcg_gen_ld32s_tl(dst
, tcg_env
, env64_field_offsetof(otherwin
));
3025 TRANS(RDPR_otherwin
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdotherwin
)
3027 static TCGv
do_rdwstate(DisasContext
*dc
, TCGv dst
)
3029 tcg_gen_ld32s_tl(dst
, tcg_env
, env64_field_offsetof(wstate
));
3033 TRANS(RDPR_wstate
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdwstate
)
3035 static TCGv
do_rdgl(DisasContext
*dc
, TCGv dst
)
3037 tcg_gen_ld32s_tl(dst
, tcg_env
, env64_field_offsetof(gl
));
3041 TRANS(RDPR_gl
, GL
, do_rd_special
, supervisor(dc
), a
->rd
, do_rdgl
)
3043 /* UA2005 strand status */
3044 static TCGv
do_rdssr(DisasContext
*dc
, TCGv dst
)
3046 tcg_gen_ld_tl(dst
, tcg_env
, env64_field_offsetof(ssr
));
3050 TRANS(RDPR_strand_status
, HYPV
, do_rd_special
, hypervisor(dc
), a
->rd
, do_rdssr
)
3052 static TCGv
do_rdver(DisasContext
*dc
, TCGv dst
)
3054 tcg_gen_ld_tl(dst
, tcg_env
, env64_field_offsetof(version
));
3058 TRANS(RDPR_ver
, 64, do_rd_special
, supervisor(dc
), a
->rd
, do_rdver
)
3060 static bool trans_FLUSHW(DisasContext
*dc
, arg_FLUSHW
*a
)
3063 gen_helper_flushw(tcg_env
);
3064 return advance_pc(dc
);
3069 static bool do_wr_special(DisasContext
*dc
, arg_r_r_ri
*a
, bool priv
,
3070 void (*func
)(DisasContext
*, TCGv
))
3074 /* For simplicity, we under-decoded the rs2 form. */
3075 if (!a
->imm
&& (a
->rs2_or_imm
& ~0x1f)) {
3079 return raise_priv(dc
);
3082 if (a
->rs1
== 0 && (a
->imm
|| a
->rs2_or_imm
== 0)) {
3083 src
= tcg_constant_tl(a
->rs2_or_imm
);
3085 TCGv src1
= gen_load_gpr(dc
, a
->rs1
);
3086 if (a
->rs2_or_imm
== 0) {
3089 src
= tcg_temp_new();
3091 tcg_gen_xori_tl(src
, src1
, a
->rs2_or_imm
);
3093 tcg_gen_xor_tl(src
, src1
, gen_load_gpr(dc
, a
->rs2_or_imm
));
3098 return advance_pc(dc
);
3101 static void do_wry(DisasContext
*dc
, TCGv src
)
3103 tcg_gen_ext32u_tl(cpu_y
, src
);
3106 TRANS(WRY
, ALL
, do_wr_special
, a
, true, do_wry
)
3108 static void do_wrccr(DisasContext
*dc
, TCGv src
)
3110 gen_helper_wrccr(tcg_env
, src
);
3113 TRANS(WRCCR
, 64, do_wr_special
, a
, true, do_wrccr
)
3115 static void do_wrasi(DisasContext
*dc
, TCGv src
)
3117 TCGv tmp
= tcg_temp_new();
3119 tcg_gen_ext8u_tl(tmp
, src
);
3120 tcg_gen_st32_tl(tmp
, tcg_env
, env64_field_offsetof(asi
));
3121 /* End TB to notice changed ASI. */
3122 dc
->base
.is_jmp
= DISAS_EXIT
;
3125 TRANS(WRASI
, 64, do_wr_special
, a
, true, do_wrasi
)
3127 static void do_wrfprs(DisasContext
*dc
, TCGv src
)
3129 #ifdef TARGET_SPARC64
3130 tcg_gen_trunc_tl_i32(cpu_fprs
, src
);
3132 dc
->base
.is_jmp
= DISAS_EXIT
;
3134 qemu_build_not_reached();
3138 TRANS(WRFPRS
, 64, do_wr_special
, a
, true, do_wrfprs
)
3140 static void do_wrgsr(DisasContext
*dc
, TCGv src
)
3142 gen_trap_ifnofpu(dc
);
3143 tcg_gen_mov_tl(cpu_gsr
, src
);
3146 TRANS(WRGSR
, 64, do_wr_special
, a
, true, do_wrgsr
)
3148 static void do_wrsoftint_set(DisasContext
*dc
, TCGv src
)
3150 gen_helper_set_softint(tcg_env
, src
);
3153 TRANS(WRSOFTINT_SET
, 64, do_wr_special
, a
, supervisor(dc
), do_wrsoftint_set
)
3155 static void do_wrsoftint_clr(DisasContext
*dc
, TCGv src
)
3157 gen_helper_clear_softint(tcg_env
, src
);
3160 TRANS(WRSOFTINT_CLR
, 64, do_wr_special
, a
, supervisor(dc
), do_wrsoftint_clr
)
3162 static void do_wrsoftint(DisasContext
*dc
, TCGv src
)
3164 gen_helper_write_softint(tcg_env
, src
);
3167 TRANS(WRSOFTINT
, 64, do_wr_special
, a
, supervisor(dc
), do_wrsoftint
)
3169 static void do_wrtick_cmpr(DisasContext
*dc
, TCGv src
)
3171 TCGv_ptr r_tickptr
= tcg_temp_new_ptr();
3173 tcg_gen_st_tl(src
, tcg_env
, env64_field_offsetof(tick_cmpr
));
3174 tcg_gen_ld_ptr(r_tickptr
, tcg_env
, env64_field_offsetof(tick
));
3175 translator_io_start(&dc
->base
);
3176 gen_helper_tick_set_limit(r_tickptr
, src
);
3177 /* End TB to handle timer interrupt */
3178 dc
->base
.is_jmp
= DISAS_EXIT
;
3181 TRANS(WRTICK_CMPR
, 64, do_wr_special
, a
, supervisor(dc
), do_wrtick_cmpr
)
3183 static void do_wrstick(DisasContext
*dc
, TCGv src
)
3185 #ifdef TARGET_SPARC64
3186 TCGv_ptr r_tickptr
= tcg_temp_new_ptr();
3188 tcg_gen_ld_ptr(r_tickptr
, tcg_env
, offsetof(CPUSPARCState
, stick
));
3189 translator_io_start(&dc
->base
);
3190 gen_helper_tick_set_count(r_tickptr
, src
);
3191 /* End TB to handle timer interrupt */
3192 dc
->base
.is_jmp
= DISAS_EXIT
;
3194 qemu_build_not_reached();
3198 TRANS(WRSTICK
, 64, do_wr_special
, a
, supervisor(dc
), do_wrstick
)
3200 static void do_wrstick_cmpr(DisasContext
*dc
, TCGv src
)
3202 TCGv_ptr r_tickptr
= tcg_temp_new_ptr();
3204 tcg_gen_st_tl(src
, tcg_env
, env64_field_offsetof(stick_cmpr
));
3205 tcg_gen_ld_ptr(r_tickptr
, tcg_env
, env64_field_offsetof(stick
));
3206 translator_io_start(&dc
->base
);
3207 gen_helper_tick_set_limit(r_tickptr
, src
);
3208 /* End TB to handle timer interrupt */
3209 dc
->base
.is_jmp
= DISAS_EXIT
;
3212 TRANS(WRSTICK_CMPR
, 64, do_wr_special
, a
, supervisor(dc
), do_wrstick_cmpr
)
3214 static void do_wrpowerdown(DisasContext
*dc
, TCGv src
)
3218 gen_helper_power_down(tcg_env
);
3221 TRANS(WRPOWERDOWN
, POWERDOWN
, do_wr_special
, a
, supervisor(dc
), do_wrpowerdown
)
3223 static void do_wrpsr(DisasContext
*dc
, TCGv src
)
3225 gen_helper_wrpsr(tcg_env
, src
);
3226 dc
->base
.is_jmp
= DISAS_EXIT
;
3229 TRANS(WRPSR
, 32, do_wr_special
, a
, supervisor(dc
), do_wrpsr
)
3231 static void do_wrwim(DisasContext
*dc
, TCGv src
)
3233 target_ulong mask
= MAKE_64BIT_MASK(0, dc
->def
->nwindows
);
3234 TCGv tmp
= tcg_temp_new();
3236 tcg_gen_andi_tl(tmp
, src
, mask
);
3237 tcg_gen_st_tl(tmp
, tcg_env
, env32_field_offsetof(wim
));
3240 TRANS(WRWIM
, 32, do_wr_special
, a
, supervisor(dc
), do_wrwim
)
3242 static void do_wrtpc(DisasContext
*dc
, TCGv src
)
3244 #ifdef TARGET_SPARC64
3245 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
3247 gen_load_trap_state_at_tl(r_tsptr
);
3248 tcg_gen_st_tl(src
, r_tsptr
, offsetof(trap_state
, tpc
));
3250 qemu_build_not_reached();
3254 TRANS(WRPR_tpc
, 64, do_wr_special
, a
, supervisor(dc
), do_wrtpc
)
3256 static void do_wrtnpc(DisasContext
*dc
, TCGv src
)
3258 #ifdef TARGET_SPARC64
3259 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
3261 gen_load_trap_state_at_tl(r_tsptr
);
3262 tcg_gen_st_tl(src
, r_tsptr
, offsetof(trap_state
, tnpc
));
3264 qemu_build_not_reached();
3268 TRANS(WRPR_tnpc
, 64, do_wr_special
, a
, supervisor(dc
), do_wrtnpc
)
3270 static void do_wrtstate(DisasContext
*dc
, TCGv src
)
3272 #ifdef TARGET_SPARC64
3273 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
3275 gen_load_trap_state_at_tl(r_tsptr
);
3276 tcg_gen_st_tl(src
, r_tsptr
, offsetof(trap_state
, tstate
));
3278 qemu_build_not_reached();
3282 TRANS(WRPR_tstate
, 64, do_wr_special
, a
, supervisor(dc
), do_wrtstate
)
3284 static void do_wrtt(DisasContext
*dc
, TCGv src
)
3286 #ifdef TARGET_SPARC64
3287 TCGv_ptr r_tsptr
= tcg_temp_new_ptr();
3289 gen_load_trap_state_at_tl(r_tsptr
);
3290 tcg_gen_st32_tl(src
, r_tsptr
, offsetof(trap_state
, tt
));
3292 qemu_build_not_reached();
3296 TRANS(WRPR_tt
, 64, do_wr_special
, a
, supervisor(dc
), do_wrtt
)
3298 static void do_wrtick(DisasContext
*dc
, TCGv src
)
3300 TCGv_ptr r_tickptr
= tcg_temp_new_ptr();
3302 tcg_gen_ld_ptr(r_tickptr
, tcg_env
, env64_field_offsetof(tick
));
3303 translator_io_start(&dc
->base
);
3304 gen_helper_tick_set_count(r_tickptr
, src
);
3305 /* End TB to handle timer interrupt */
3306 dc
->base
.is_jmp
= DISAS_EXIT
;
3309 TRANS(WRPR_tick
, 64, do_wr_special
, a
, supervisor(dc
), do_wrtick
)
3311 static void do_wrtba(DisasContext
*dc
, TCGv src
)
3313 tcg_gen_mov_tl(cpu_tbr
, src
);
3316 TRANS(WRPR_tba
, 64, do_wr_special
, a
, supervisor(dc
), do_wrtba
)
3318 static void do_wrpstate(DisasContext
*dc
, TCGv src
)
3321 if (translator_io_start(&dc
->base
)) {
3322 dc
->base
.is_jmp
= DISAS_EXIT
;
3324 gen_helper_wrpstate(tcg_env
, src
);
3325 dc
->npc
= DYNAMIC_PC
;
3328 TRANS(WRPR_pstate
, 64, do_wr_special
, a
, supervisor(dc
), do_wrpstate
)
3330 static void do_wrtl(DisasContext
*dc
, TCGv src
)
3333 tcg_gen_st32_tl(src
, tcg_env
, env64_field_offsetof(tl
));
3334 dc
->npc
= DYNAMIC_PC
;
3337 TRANS(WRPR_tl
, 64, do_wr_special
, a
, supervisor(dc
), do_wrtl
)
3339 static void do_wrpil(DisasContext
*dc
, TCGv src
)
3341 if (translator_io_start(&dc
->base
)) {
3342 dc
->base
.is_jmp
= DISAS_EXIT
;
3344 gen_helper_wrpil(tcg_env
, src
);
3347 TRANS(WRPR_pil
, 64, do_wr_special
, a
, supervisor(dc
), do_wrpil
)
3349 static void do_wrcwp(DisasContext
*dc
, TCGv src
)
3351 gen_helper_wrcwp(tcg_env
, src
);
3354 TRANS(WRPR_cwp
, 64, do_wr_special
, a
, supervisor(dc
), do_wrcwp
)
3356 static void do_wrcansave(DisasContext
*dc
, TCGv src
)
3358 tcg_gen_st32_tl(src
, tcg_env
, env64_field_offsetof(cansave
));
3361 TRANS(WRPR_cansave
, 64, do_wr_special
, a
, supervisor(dc
), do_wrcansave
)
3363 static void do_wrcanrestore(DisasContext
*dc
, TCGv src
)
3365 tcg_gen_st32_tl(src
, tcg_env
, env64_field_offsetof(canrestore
));
3368 TRANS(WRPR_canrestore
, 64, do_wr_special
, a
, supervisor(dc
), do_wrcanrestore
)
3370 static void do_wrcleanwin(DisasContext
*dc
, TCGv src
)
3372 tcg_gen_st32_tl(src
, tcg_env
, env64_field_offsetof(cleanwin
));
3375 TRANS(WRPR_cleanwin
, 64, do_wr_special
, a
, supervisor(dc
), do_wrcleanwin
)
3377 static void do_wrotherwin(DisasContext
*dc
, TCGv src
)
3379 tcg_gen_st32_tl(src
, tcg_env
, env64_field_offsetof(otherwin
));
3382 TRANS(WRPR_otherwin
, 64, do_wr_special
, a
, supervisor(dc
), do_wrotherwin
)
3384 static void do_wrwstate(DisasContext
*dc
, TCGv src
)
3386 tcg_gen_st32_tl(src
, tcg_env
, env64_field_offsetof(wstate
));
3389 TRANS(WRPR_wstate
, 64, do_wr_special
, a
, supervisor(dc
), do_wrwstate
)
3391 static void do_wrgl(DisasContext
*dc
, TCGv src
)
3393 gen_helper_wrgl(tcg_env
, src
);
3396 TRANS(WRPR_gl
, GL
, do_wr_special
, a
, supervisor(dc
), do_wrgl
)
3398 /* UA2005 strand status */
3399 static void do_wrssr(DisasContext
*dc
, TCGv src
)
3401 tcg_gen_st_tl(src
, tcg_env
, env64_field_offsetof(ssr
));
3404 TRANS(WRPR_strand_status
, HYPV
, do_wr_special
, a
, hypervisor(dc
), do_wrssr
)
3406 TRANS(WRTBR
, 32, do_wr_special
, a
, supervisor(dc
), do_wrtba
)
3408 static void do_wrhpstate(DisasContext
*dc
, TCGv src
)
3410 tcg_gen_st_tl(src
, tcg_env
, env64_field_offsetof(hpstate
));
3411 dc
->base
.is_jmp
= DISAS_EXIT
;
3414 TRANS(WRHPR_hpstate
, HYPV
, do_wr_special
, a
, hypervisor(dc
), do_wrhpstate
)
3416 static void do_wrhtstate(DisasContext
*dc
, TCGv src
)
3418 TCGv_i32 tl
= tcg_temp_new_i32();
3419 TCGv_ptr tp
= tcg_temp_new_ptr();
3421 tcg_gen_ld_i32(tl
, tcg_env
, env64_field_offsetof(tl
));
3422 tcg_gen_andi_i32(tl
, tl
, MAXTL_MASK
);
3423 tcg_gen_shli_i32(tl
, tl
, 3);
3424 tcg_gen_ext_i32_ptr(tp
, tl
);
3425 tcg_gen_add_ptr(tp
, tp
, tcg_env
);
3427 tcg_gen_st_tl(src
, tp
, env64_field_offsetof(htstate
));
3430 TRANS(WRHPR_htstate
, HYPV
, do_wr_special
, a
, hypervisor(dc
), do_wrhtstate
)
3432 static void do_wrhintp(DisasContext
*dc
, TCGv src
)
3434 tcg_gen_st_tl(src
, tcg_env
, env64_field_offsetof(hintp
));
3437 TRANS(WRHPR_hintp
, HYPV
, do_wr_special
, a
, hypervisor(dc
), do_wrhintp
)
3439 static void do_wrhtba(DisasContext
*dc
, TCGv src
)
3441 tcg_gen_st_tl(src
, tcg_env
, env64_field_offsetof(htba
));
3444 TRANS(WRHPR_htba
, HYPV
, do_wr_special
, a
, hypervisor(dc
), do_wrhtba
)
3446 static void do_wrhstick_cmpr(DisasContext
*dc
, TCGv src
)
3448 TCGv_ptr r_tickptr
= tcg_temp_new_ptr();
3450 tcg_gen_st_tl(src
, tcg_env
, env64_field_offsetof(hstick_cmpr
));
3451 tcg_gen_ld_ptr(r_tickptr
, tcg_env
, env64_field_offsetof(hstick
));
3452 translator_io_start(&dc
->base
);
3453 gen_helper_tick_set_limit(r_tickptr
, src
);
3454 /* End TB to handle timer interrupt */
3455 dc
->base
.is_jmp
= DISAS_EXIT
;
3458 TRANS(WRHPR_hstick_cmpr
, HYPV
, do_wr_special
, a
, hypervisor(dc
),
3461 static bool do_saved_restored(DisasContext
*dc
, bool saved
)
3463 if (!supervisor(dc
)) {
3464 return raise_priv(dc
);
3467 gen_helper_saved(tcg_env
);
3469 gen_helper_restored(tcg_env
);
3471 return advance_pc(dc
);
3474 TRANS(SAVED
, 64, do_saved_restored
, true)
3475 TRANS(RESTORED
, 64, do_saved_restored
, false)
3477 static bool trans_NOP(DisasContext
*dc
, arg_NOP
*a
)
3479 return advance_pc(dc
);
3483 * TODO: Need a feature bit for sparcv8.
3484 * In the meantime, treat all 32-bit cpus like sparcv7.
3486 TRANS(NOP_v7
, 32, trans_NOP
, a
)
3487 TRANS(NOP_v9
, 64, trans_NOP
, a
)
3489 static bool do_arith_int(DisasContext
*dc
, arg_r_r_ri_cc
*a
,
3490 void (*func
)(TCGv
, TCGv
, TCGv
),
3491 void (*funci
)(TCGv
, TCGv
, target_long
),
3496 /* For simplicity, we under-decoded the rs2 form. */
3497 if (!a
->imm
&& a
->rs2_or_imm
& ~0x1f) {
3504 dst
= gen_dest_gpr(dc
, a
->rd
);
3506 src1
= gen_load_gpr(dc
, a
->rs1
);
3508 if (a
->imm
|| a
->rs2_or_imm
== 0) {
3510 funci(dst
, src1
, a
->rs2_or_imm
);
3512 func(dst
, src1
, tcg_constant_tl(a
->rs2_or_imm
));
3515 func(dst
, src1
, cpu_regs
[a
->rs2_or_imm
]);
3519 if (TARGET_LONG_BITS
== 64) {
3520 tcg_gen_mov_tl(cpu_icc_Z
, cpu_cc_N
);
3521 tcg_gen_movi_tl(cpu_icc_C
, 0);
3523 tcg_gen_mov_tl(cpu_cc_Z
, cpu_cc_N
);
3524 tcg_gen_movi_tl(cpu_cc_C
, 0);
3525 tcg_gen_movi_tl(cpu_cc_V
, 0);
3528 gen_store_gpr(dc
, a
->rd
, dst
);
3529 return advance_pc(dc
);
3532 static bool do_arith(DisasContext
*dc
, arg_r_r_ri_cc
*a
,
3533 void (*func
)(TCGv
, TCGv
, TCGv
),
3534 void (*funci
)(TCGv
, TCGv
, target_long
),
3535 void (*func_cc
)(TCGv
, TCGv
, TCGv
))
3538 return do_arith_int(dc
, a
, func_cc
, NULL
, false);
3540 return do_arith_int(dc
, a
, func
, funci
, false);
3543 static bool do_logic(DisasContext
*dc
, arg_r_r_ri_cc
*a
,
3544 void (*func
)(TCGv
, TCGv
, TCGv
),
3545 void (*funci
)(TCGv
, TCGv
, target_long
))
3547 return do_arith_int(dc
, a
, func
, funci
, a
->cc
);
3550 TRANS(ADD
, ALL
, do_arith
, a
, tcg_gen_add_tl
, tcg_gen_addi_tl
, gen_op_addcc
)
3551 TRANS(SUB
, ALL
, do_arith
, a
, tcg_gen_sub_tl
, tcg_gen_subi_tl
, gen_op_subcc
)
3552 TRANS(ADDC
, ALL
, do_arith
, a
, gen_op_addc
, NULL
, gen_op_addccc
)
3553 TRANS(SUBC
, ALL
, do_arith
, a
, gen_op_subc
, NULL
, gen_op_subccc
)
3555 TRANS(TADDcc
, ALL
, do_arith
, a
, NULL
, NULL
, gen_op_taddcc
)
3556 TRANS(TSUBcc
, ALL
, do_arith
, a
, NULL
, NULL
, gen_op_tsubcc
)
3557 TRANS(TADDccTV
, ALL
, do_arith
, a
, NULL
, NULL
, gen_op_taddcctv
)
3558 TRANS(TSUBccTV
, ALL
, do_arith
, a
, NULL
, NULL
, gen_op_tsubcctv
)
3560 TRANS(AND
, ALL
, do_logic
, a
, tcg_gen_and_tl
, tcg_gen_andi_tl
)
3561 TRANS(XOR
, ALL
, do_logic
, a
, tcg_gen_xor_tl
, tcg_gen_xori_tl
)
3562 TRANS(ANDN
, ALL
, do_logic
, a
, tcg_gen_andc_tl
, NULL
)
3563 TRANS(ORN
, ALL
, do_logic
, a
, tcg_gen_orc_tl
, NULL
)
3564 TRANS(XORN
, ALL
, do_logic
, a
, tcg_gen_eqv_tl
, NULL
)
3566 TRANS(MULX
, 64, do_arith
, a
, tcg_gen_mul_tl
, tcg_gen_muli_tl
, NULL
)
3567 TRANS(UMUL
, MUL
, do_logic
, a
, gen_op_umul
, NULL
)
3568 TRANS(SMUL
, MUL
, do_logic
, a
, gen_op_smul
, NULL
)
3569 TRANS(MULScc
, ALL
, do_arith
, a
, NULL
, NULL
, gen_op_mulscc
)
3571 TRANS(UDIVcc
, DIV
, do_arith
, a
, NULL
, NULL
, gen_op_udivcc
)
3572 TRANS(SDIV
, DIV
, do_arith
, a
, gen_op_sdiv
, NULL
, gen_op_sdivcc
)
3574 /* TODO: Should have feature bit -- comes in with UltraSparc T2. */
3575 TRANS(POPC
, 64, do_arith
, a
, gen_op_popc
, NULL
, NULL
)
3577 static bool trans_OR(DisasContext
*dc
, arg_r_r_ri_cc
*a
)
3579 /* OR with %g0 is the canonical alias for MOV. */
3580 if (!a
->cc
&& a
->rs1
== 0) {
3581 if (a
->imm
|| a
->rs2_or_imm
== 0) {
3582 gen_store_gpr(dc
, a
->rd
, tcg_constant_tl(a
->rs2_or_imm
));
3583 } else if (a
->rs2_or_imm
& ~0x1f) {
3584 /* For simplicity, we under-decoded the rs2 form. */
3587 gen_store_gpr(dc
, a
->rd
, cpu_regs
[a
->rs2_or_imm
]);
3589 return advance_pc(dc
);
3591 return do_logic(dc
, a
, tcg_gen_or_tl
, tcg_gen_ori_tl
);
3594 static bool trans_UDIV(DisasContext
*dc
, arg_r_r_ri
*a
)
3599 if (!avail_DIV(dc
)) {
3602 /* For simplicity, we under-decoded the rs2 form. */
3603 if (!a
->imm
&& a
->rs2_or_imm
& ~0x1f) {
3607 if (unlikely(a
->rs2_or_imm
== 0)) {
3608 gen_exception(dc
, TT_DIV_ZERO
);
3613 t2
= tcg_constant_i64((uint32_t)a
->rs2_or_imm
);
3621 n2
= tcg_temp_new_i32();
3622 tcg_gen_trunc_tl_i32(n2
, cpu_regs
[a
->rs2_or_imm
]);
3624 lab
= delay_exception(dc
, TT_DIV_ZERO
);
3625 tcg_gen_brcondi_i32(TCG_COND_EQ
, n2
, 0, lab
);
3627 t2
= tcg_temp_new_i64();
3628 #ifdef TARGET_SPARC64
3629 tcg_gen_ext32u_i64(t2
, cpu_regs
[a
->rs2_or_imm
]);
3631 tcg_gen_extu_i32_i64(t2
, cpu_regs
[a
->rs2_or_imm
]);
3635 t1
= tcg_temp_new_i64();
3636 tcg_gen_concat_tl_i64(t1
, gen_load_gpr(dc
, a
->rs1
), cpu_y
);
3638 tcg_gen_divu_i64(t1
, t1
, t2
);
3639 tcg_gen_umin_i64(t1
, t1
, tcg_constant_i64(UINT32_MAX
));
3641 dst
= gen_dest_gpr(dc
, a
->rd
);
3642 tcg_gen_trunc_i64_tl(dst
, t1
);
3643 gen_store_gpr(dc
, a
->rd
, dst
);
3644 return advance_pc(dc
);
3647 static bool trans_UDIVX(DisasContext
*dc
, arg_r_r_ri
*a
)
3649 TCGv dst
, src1
, src2
;
3651 if (!avail_64(dc
)) {
3654 /* For simplicity, we under-decoded the rs2 form. */
3655 if (!a
->imm
&& a
->rs2_or_imm
& ~0x1f) {
3659 if (unlikely(a
->rs2_or_imm
== 0)) {
3660 gen_exception(dc
, TT_DIV_ZERO
);
3665 src2
= tcg_constant_tl(a
->rs2_or_imm
);
3672 lab
= delay_exception(dc
, TT_DIV_ZERO
);
3673 src2
= cpu_regs
[a
->rs2_or_imm
];
3674 tcg_gen_brcondi_tl(TCG_COND_EQ
, src2
, 0, lab
);
3677 dst
= gen_dest_gpr(dc
, a
->rd
);
3678 src1
= gen_load_gpr(dc
, a
->rs1
);
3680 tcg_gen_divu_tl(dst
, src1
, src2
);
3681 gen_store_gpr(dc
, a
->rd
, dst
);
3682 return advance_pc(dc
);
3685 static bool trans_SDIVX(DisasContext
*dc
, arg_r_r_ri
*a
)
3687 TCGv dst
, src1
, src2
;
3689 if (!avail_64(dc
)) {
3692 /* For simplicity, we under-decoded the rs2 form. */
3693 if (!a
->imm
&& a
->rs2_or_imm
& ~0x1f) {
3697 if (unlikely(a
->rs2_or_imm
== 0)) {
3698 gen_exception(dc
, TT_DIV_ZERO
);
3702 dst
= gen_dest_gpr(dc
, a
->rd
);
3703 src1
= gen_load_gpr(dc
, a
->rs1
);
3706 if (unlikely(a
->rs2_or_imm
== -1)) {
3707 tcg_gen_neg_tl(dst
, src1
);
3708 gen_store_gpr(dc
, a
->rd
, dst
);
3709 return advance_pc(dc
);
3711 src2
= tcg_constant_tl(a
->rs2_or_imm
);
3719 lab
= delay_exception(dc
, TT_DIV_ZERO
);
3720 src2
= cpu_regs
[a
->rs2_or_imm
];
3721 tcg_gen_brcondi_tl(TCG_COND_EQ
, src2
, 0, lab
);
3724 * Need to avoid INT64_MIN / -1, which will trap on x86 host.
3725 * Set SRC2 to 1 as a new divisor, to produce the correct result.
3727 t1
= tcg_temp_new();
3728 t2
= tcg_temp_new();
3729 tcg_gen_setcondi_tl(TCG_COND_EQ
, t1
, src1
, (target_long
)INT64_MIN
);
3730 tcg_gen_setcondi_tl(TCG_COND_EQ
, t2
, src2
, -1);
3731 tcg_gen_and_tl(t1
, t1
, t2
);
3732 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t1
, tcg_constant_tl(0),
3733 tcg_constant_tl(1), src2
);
3737 tcg_gen_div_tl(dst
, src1
, src2
);
3738 gen_store_gpr(dc
, a
->rd
, dst
);
3739 return advance_pc(dc
);
3742 static bool gen_edge(DisasContext
*dc
, arg_r_r_r
*a
,
3743 int width
, bool cc
, bool left
)
3745 TCGv dst
, s1
, s2
, lo1
, lo2
;
3746 uint64_t amask
, tabl
, tabr
;
3747 int shift
, imask
, omask
;
3749 dst
= gen_dest_gpr(dc
, a
->rd
);
3750 s1
= gen_load_gpr(dc
, a
->rs1
);
3751 s2
= gen_load_gpr(dc
, a
->rs2
);
3754 gen_op_subcc(cpu_cc_N
, s1
, s2
);
3758 * Theory of operation: there are two tables, left and right (not to
3759 * be confused with the left and right versions of the opcode). These
3760 * are indexed by the low 3 bits of the inputs. To make things "easy",
3761 * these tables are loaded into two constants, TABL and TABR below.
3762 * The operation index = (input & imask) << shift calculates the index
3763 * into the constant, while val = (table >> index) & omask calculates
3764 * the value we're looking for.
3772 tabl
= 0x80c0e0f0f8fcfeffULL
;
3773 tabr
= 0xff7f3f1f0f070301ULL
;
3775 tabl
= 0x0103070f1f3f7fffULL
;
3776 tabr
= 0xfffefcf8f0e0c080ULL
;
3796 tabl
= (2 << 2) | 3;
3797 tabr
= (3 << 2) | 1;
3799 tabl
= (1 << 2) | 3;
3800 tabr
= (3 << 2) | 2;
3807 lo1
= tcg_temp_new();
3808 lo2
= tcg_temp_new();
3809 tcg_gen_andi_tl(lo1
, s1
, imask
);
3810 tcg_gen_andi_tl(lo2
, s2
, imask
);
3811 tcg_gen_shli_tl(lo1
, lo1
, shift
);
3812 tcg_gen_shli_tl(lo2
, lo2
, shift
);
3814 tcg_gen_shr_tl(lo1
, tcg_constant_tl(tabl
), lo1
);
3815 tcg_gen_shr_tl(lo2
, tcg_constant_tl(tabr
), lo2
);
3816 tcg_gen_andi_tl(lo1
, lo1
, omask
);
3817 tcg_gen_andi_tl(lo2
, lo2
, omask
);
3819 amask
= address_mask_i(dc
, -8);
3820 tcg_gen_andi_tl(s1
, s1
, amask
);
3821 tcg_gen_andi_tl(s2
, s2
, amask
);
3823 /* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */
3824 tcg_gen_and_tl(lo2
, lo2
, lo1
);
3825 tcg_gen_movcond_tl(TCG_COND_EQ
, dst
, s1
, s2
, lo1
, lo2
);
3827 gen_store_gpr(dc
, a
->rd
, dst
);
3828 return advance_pc(dc
);
3831 TRANS(EDGE8cc
, VIS1
, gen_edge
, a
, 8, 1, 0)
3832 TRANS(EDGE8Lcc
, VIS1
, gen_edge
, a
, 8, 1, 1)
3833 TRANS(EDGE16cc
, VIS1
, gen_edge
, a
, 16, 1, 0)
3834 TRANS(EDGE16Lcc
, VIS1
, gen_edge
, a
, 16, 1, 1)
3835 TRANS(EDGE32cc
, VIS1
, gen_edge
, a
, 32, 1, 0)
3836 TRANS(EDGE32Lcc
, VIS1
, gen_edge
, a
, 32, 1, 1)
3838 TRANS(EDGE8N
, VIS2
, gen_edge
, a
, 8, 0, 0)
3839 TRANS(EDGE8LN
, VIS2
, gen_edge
, a
, 8, 0, 1)
3840 TRANS(EDGE16N
, VIS2
, gen_edge
, a
, 16, 0, 0)
3841 TRANS(EDGE16LN
, VIS2
, gen_edge
, a
, 16, 0, 1)
3842 TRANS(EDGE32N
, VIS2
, gen_edge
, a
, 32, 0, 0)
3843 TRANS(EDGE32LN
, VIS2
, gen_edge
, a
, 32, 0, 1)
3845 static bool do_rrr(DisasContext
*dc
, arg_r_r_r
*a
,
3846 void (*func
)(TCGv
, TCGv
, TCGv
))
3848 TCGv dst
= gen_dest_gpr(dc
, a
->rd
);
3849 TCGv src1
= gen_load_gpr(dc
, a
->rs1
);
3850 TCGv src2
= gen_load_gpr(dc
, a
->rs2
);
3852 func(dst
, src1
, src2
);
3853 gen_store_gpr(dc
, a
->rd
, dst
);
3854 return advance_pc(dc
);
3857 TRANS(ARRAY8
, VIS1
, do_rrr
, a
, gen_helper_array8
)
3858 TRANS(ARRAY16
, VIS1
, do_rrr
, a
, gen_op_array16
)
3859 TRANS(ARRAY32
, VIS1
, do_rrr
, a
, gen_op_array32
)
3861 static void gen_op_alignaddr(TCGv dst
, TCGv s1
, TCGv s2
)
3863 #ifdef TARGET_SPARC64
3864 TCGv tmp
= tcg_temp_new();
3866 tcg_gen_add_tl(tmp
, s1
, s2
);
3867 tcg_gen_andi_tl(dst
, tmp
, -8);
3868 tcg_gen_deposit_tl(cpu_gsr
, cpu_gsr
, tmp
, 0, 3);
3870 g_assert_not_reached();
3874 static void gen_op_alignaddrl(TCGv dst
, TCGv s1
, TCGv s2
)
3876 #ifdef TARGET_SPARC64
3877 TCGv tmp
= tcg_temp_new();
3879 tcg_gen_add_tl(tmp
, s1
, s2
);
3880 tcg_gen_andi_tl(dst
, tmp
, -8);
3881 tcg_gen_neg_tl(tmp
, tmp
);
3882 tcg_gen_deposit_tl(cpu_gsr
, cpu_gsr
, tmp
, 0, 3);
3884 g_assert_not_reached();
3888 TRANS(ALIGNADDR
, VIS1
, do_rrr
, a
, gen_op_alignaddr
)
3889 TRANS(ALIGNADDRL
, VIS1
, do_rrr
, a
, gen_op_alignaddrl
)
3891 static void gen_op_bmask(TCGv dst
, TCGv s1
, TCGv s2
)
3893 #ifdef TARGET_SPARC64
3894 tcg_gen_add_tl(dst
, s1
, s2
);
3895 tcg_gen_deposit_tl(cpu_gsr
, cpu_gsr
, dst
, 32, 32);
3897 g_assert_not_reached();
3901 TRANS(BMASK
, VIS2
, do_rrr
, a
, gen_op_bmask
)
3903 static bool do_shift_r(DisasContext
*dc
, arg_shiftr
*a
, bool l
, bool u
)
3905 TCGv dst
, src1
, src2
;
3907 /* Reject 64-bit shifts for sparc32. */
3908 if (avail_32(dc
) && a
->x
) {
3912 src2
= tcg_temp_new();
3913 tcg_gen_andi_tl(src2
, gen_load_gpr(dc
, a
->rs2
), a
->x
? 63 : 31);
3914 src1
= gen_load_gpr(dc
, a
->rs1
);
3915 dst
= gen_dest_gpr(dc
, a
->rd
);
3918 tcg_gen_shl_tl(dst
, src1
, src2
);
3920 tcg_gen_ext32u_tl(dst
, dst
);
3924 tcg_gen_ext32u_tl(dst
, src1
);
3927 tcg_gen_shr_tl(dst
, src1
, src2
);
3930 tcg_gen_ext32s_tl(dst
, src1
);
3933 tcg_gen_sar_tl(dst
, src1
, src2
);
3935 gen_store_gpr(dc
, a
->rd
, dst
);
3936 return advance_pc(dc
);
3939 TRANS(SLL_r
, ALL
, do_shift_r
, a
, true, true)
3940 TRANS(SRL_r
, ALL
, do_shift_r
, a
, false, true)
3941 TRANS(SRA_r
, ALL
, do_shift_r
, a
, false, false)
3943 static bool do_shift_i(DisasContext
*dc
, arg_shifti
*a
, bool l
, bool u
)
3947 /* Reject 64-bit shifts for sparc32. */
3948 if (avail_32(dc
) && (a
->x
|| a
->i
>= 32)) {
3952 src1
= gen_load_gpr(dc
, a
->rs1
);
3953 dst
= gen_dest_gpr(dc
, a
->rd
);
3955 if (avail_32(dc
) || a
->x
) {
3957 tcg_gen_shli_tl(dst
, src1
, a
->i
);
3959 tcg_gen_shri_tl(dst
, src1
, a
->i
);
3961 tcg_gen_sari_tl(dst
, src1
, a
->i
);
3965 tcg_gen_deposit_z_tl(dst
, src1
, a
->i
, 32 - a
->i
);
3967 tcg_gen_extract_tl(dst
, src1
, a
->i
, 32 - a
->i
);
3969 tcg_gen_sextract_tl(dst
, src1
, a
->i
, 32 - a
->i
);
3972 gen_store_gpr(dc
, a
->rd
, dst
);
3973 return advance_pc(dc
);
3976 TRANS(SLL_i
, ALL
, do_shift_i
, a
, true, true)
3977 TRANS(SRL_i
, ALL
, do_shift_i
, a
, false, true)
3978 TRANS(SRA_i
, ALL
, do_shift_i
, a
, false, false)
3980 static TCGv
gen_rs2_or_imm(DisasContext
*dc
, bool imm
, int rs2_or_imm
)
3982 /* For simplicity, we under-decoded the rs2 form. */
3983 if (!imm
&& rs2_or_imm
& ~0x1f) {
3986 if (imm
|| rs2_or_imm
== 0) {
3987 return tcg_constant_tl(rs2_or_imm
);
3989 return cpu_regs
[rs2_or_imm
];
3993 static bool do_mov_cond(DisasContext
*dc
, DisasCompare
*cmp
, int rd
, TCGv src2
)
3995 TCGv dst
= gen_load_gpr(dc
, rd
);
3996 TCGv c2
= tcg_constant_tl(cmp
->c2
);
3998 tcg_gen_movcond_tl(cmp
->cond
, dst
, cmp
->c1
, c2
, src2
, dst
);
3999 gen_store_gpr(dc
, rd
, dst
);
4000 return advance_pc(dc
);
4003 static bool trans_MOVcc(DisasContext
*dc
, arg_MOVcc
*a
)
4005 TCGv src2
= gen_rs2_or_imm(dc
, a
->imm
, a
->rs2_or_imm
);
4011 gen_compare(&cmp
, a
->cc
, a
->cond
, dc
);
4012 return do_mov_cond(dc
, &cmp
, a
->rd
, src2
);
4015 static bool trans_MOVfcc(DisasContext
*dc
, arg_MOVfcc
*a
)
4017 TCGv src2
= gen_rs2_or_imm(dc
, a
->imm
, a
->rs2_or_imm
);
4023 gen_fcompare(&cmp
, a
->cc
, a
->cond
);
4024 return do_mov_cond(dc
, &cmp
, a
->rd
, src2
);
4027 static bool trans_MOVR(DisasContext
*dc
, arg_MOVR
*a
)
4029 TCGv src2
= gen_rs2_or_imm(dc
, a
->imm
, a
->rs2_or_imm
);
4035 if (!gen_compare_reg(&cmp
, a
->cond
, gen_load_gpr(dc
, a
->rs1
))) {
4038 return do_mov_cond(dc
, &cmp
, a
->rd
, src2
);
4041 static bool do_add_special(DisasContext
*dc
, arg_r_r_ri
*a
,
4042 bool (*func
)(DisasContext
*dc
, int rd
, TCGv src
))
4046 /* For simplicity, we under-decoded the rs2 form. */
4047 if (!a
->imm
&& a
->rs2_or_imm
& ~0x1f) {
4052 * Always load the sum into a new temporary.
4053 * This is required to capture the value across a window change,
4054 * e.g. SAVE and RESTORE, and may be optimized away otherwise.
4056 sum
= tcg_temp_new();
4057 src1
= gen_load_gpr(dc
, a
->rs1
);
4058 if (a
->imm
|| a
->rs2_or_imm
== 0) {
4059 tcg_gen_addi_tl(sum
, src1
, a
->rs2_or_imm
);
4061 tcg_gen_add_tl(sum
, src1
, cpu_regs
[a
->rs2_or_imm
]);
4063 return func(dc
, a
->rd
, sum
);
4066 static bool do_jmpl(DisasContext
*dc
, int rd
, TCGv src
)
4069 * Preserve pc across advance, so that we can delay
4070 * the writeback to rd until after src is consumed.
4072 target_ulong cur_pc
= dc
->pc
;
4074 gen_check_align(dc
, src
, 3);
4077 tcg_gen_mov_tl(cpu_npc
, src
);
4078 gen_address_mask(dc
, cpu_npc
);
4079 gen_store_gpr(dc
, rd
, tcg_constant_tl(cur_pc
));
4081 dc
->npc
= DYNAMIC_PC_LOOKUP
;
4085 TRANS(JMPL
, ALL
, do_add_special
, a
, do_jmpl
)
4087 static bool do_rett(DisasContext
*dc
, int rd
, TCGv src
)
4089 if (!supervisor(dc
)) {
4090 return raise_priv(dc
);
4093 gen_check_align(dc
, src
, 3);
4096 tcg_gen_mov_tl(cpu_npc
, src
);
4097 gen_helper_rett(tcg_env
);
4099 dc
->npc
= DYNAMIC_PC
;
4103 TRANS(RETT
, 32, do_add_special
, a
, do_rett
)
4105 static bool do_return(DisasContext
*dc
, int rd
, TCGv src
)
4107 gen_check_align(dc
, src
, 3);
4108 gen_helper_restore(tcg_env
);
4111 tcg_gen_mov_tl(cpu_npc
, src
);
4112 gen_address_mask(dc
, cpu_npc
);
4114 dc
->npc
= DYNAMIC_PC_LOOKUP
;
4118 TRANS(RETURN
, 64, do_add_special
, a
, do_return
)
4120 static bool do_save(DisasContext
*dc
, int rd
, TCGv src
)
4122 gen_helper_save(tcg_env
);
4123 gen_store_gpr(dc
, rd
, src
);
4124 return advance_pc(dc
);
4127 TRANS(SAVE
, ALL
, do_add_special
, a
, do_save
)
4129 static bool do_restore(DisasContext
*dc
, int rd
, TCGv src
)
4131 gen_helper_restore(tcg_env
);
4132 gen_store_gpr(dc
, rd
, src
);
4133 return advance_pc(dc
);
4136 TRANS(RESTORE
, ALL
, do_add_special
, a
, do_restore
)
4138 static bool do_done_retry(DisasContext
*dc
, bool done
)
4140 if (!supervisor(dc
)) {
4141 return raise_priv(dc
);
4143 dc
->npc
= DYNAMIC_PC
;
4144 dc
->pc
= DYNAMIC_PC
;
4145 translator_io_start(&dc
->base
);
4147 gen_helper_done(tcg_env
);
4149 gen_helper_retry(tcg_env
);
4154 TRANS(DONE
, 64, do_done_retry
, true)
4155 TRANS(RETRY
, 64, do_done_retry
, false)
4158 * Major opcode 11 -- load and store instructions
4161 static TCGv
gen_ldst_addr(DisasContext
*dc
, int rs1
, bool imm
, int rs2_or_imm
)
4163 TCGv addr
, tmp
= NULL
;
4165 /* For simplicity, we under-decoded the rs2 form. */
4166 if (!imm
&& rs2_or_imm
& ~0x1f) {
4170 addr
= gen_load_gpr(dc
, rs1
);
4172 tmp
= tcg_temp_new();
4174 tcg_gen_addi_tl(tmp
, addr
, rs2_or_imm
);
4176 tcg_gen_add_tl(tmp
, addr
, cpu_regs
[rs2_or_imm
]);
4182 tmp
= tcg_temp_new();
4184 tcg_gen_ext32u_tl(tmp
, addr
);
4190 static bool do_ld_gpr(DisasContext
*dc
, arg_r_r_ri_asi
*a
, MemOp mop
)
4192 TCGv reg
, addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4198 da
= resolve_asi(dc
, a
->asi
, mop
);
4200 reg
= gen_dest_gpr(dc
, a
->rd
);
4201 gen_ld_asi(dc
, &da
, reg
, addr
);
4202 gen_store_gpr(dc
, a
->rd
, reg
);
4203 return advance_pc(dc
);
4206 TRANS(LDUW
, ALL
, do_ld_gpr
, a
, MO_TEUL
)
4207 TRANS(LDUB
, ALL
, do_ld_gpr
, a
, MO_UB
)
4208 TRANS(LDUH
, ALL
, do_ld_gpr
, a
, MO_TEUW
)
4209 TRANS(LDSB
, ALL
, do_ld_gpr
, a
, MO_SB
)
4210 TRANS(LDSH
, ALL
, do_ld_gpr
, a
, MO_TESW
)
4211 TRANS(LDSW
, 64, do_ld_gpr
, a
, MO_TESL
)
4212 TRANS(LDX
, 64, do_ld_gpr
, a
, MO_TEUQ
)
4214 static bool do_st_gpr(DisasContext
*dc
, arg_r_r_ri_asi
*a
, MemOp mop
)
4216 TCGv reg
, addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4222 da
= resolve_asi(dc
, a
->asi
, mop
);
4224 reg
= gen_load_gpr(dc
, a
->rd
);
4225 gen_st_asi(dc
, &da
, reg
, addr
);
4226 return advance_pc(dc
);
4229 TRANS(STW
, ALL
, do_st_gpr
, a
, MO_TEUL
)
4230 TRANS(STB
, ALL
, do_st_gpr
, a
, MO_UB
)
4231 TRANS(STH
, ALL
, do_st_gpr
, a
, MO_TEUW
)
4232 TRANS(STX
, 64, do_st_gpr
, a
, MO_TEUQ
)
4234 static bool trans_LDD(DisasContext
*dc
, arg_r_r_ri_asi
*a
)
4242 addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4246 da
= resolve_asi(dc
, a
->asi
, MO_TEUQ
);
4247 gen_ldda_asi(dc
, &da
, addr
, a
->rd
);
4248 return advance_pc(dc
);
4251 static bool trans_STD(DisasContext
*dc
, arg_r_r_ri_asi
*a
)
4259 addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4263 da
= resolve_asi(dc
, a
->asi
, MO_TEUQ
);
4264 gen_stda_asi(dc
, &da
, addr
, a
->rd
);
4265 return advance_pc(dc
);
4268 static bool trans_LDSTUB(DisasContext
*dc
, arg_r_r_ri_asi
*a
)
4273 addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4277 da
= resolve_asi(dc
, a
->asi
, MO_UB
);
4279 reg
= gen_dest_gpr(dc
, a
->rd
);
4280 gen_ldstub_asi(dc
, &da
, reg
, addr
);
4281 gen_store_gpr(dc
, a
->rd
, reg
);
4282 return advance_pc(dc
);
4285 static bool trans_SWAP(DisasContext
*dc
, arg_r_r_ri_asi
*a
)
4287 TCGv addr
, dst
, src
;
4290 addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4294 da
= resolve_asi(dc
, a
->asi
, MO_TEUL
);
4296 dst
= gen_dest_gpr(dc
, a
->rd
);
4297 src
= gen_load_gpr(dc
, a
->rd
);
4298 gen_swap_asi(dc
, &da
, dst
, src
, addr
);
4299 gen_store_gpr(dc
, a
->rd
, dst
);
4300 return advance_pc(dc
);
4303 static bool do_casa(DisasContext
*dc
, arg_r_r_ri_asi
*a
, MemOp mop
)
4308 addr
= gen_ldst_addr(dc
, a
->rs1
, true, 0);
4312 da
= resolve_asi(dc
, a
->asi
, mop
);
4314 o
= gen_dest_gpr(dc
, a
->rd
);
4315 n
= gen_load_gpr(dc
, a
->rd
);
4316 c
= gen_load_gpr(dc
, a
->rs2_or_imm
);
4317 gen_cas_asi(dc
, &da
, o
, n
, c
, addr
);
4318 gen_store_gpr(dc
, a
->rd
, o
);
4319 return advance_pc(dc
);
4322 TRANS(CASA
, CASA
, do_casa
, a
, MO_TEUL
)
4323 TRANS(CASXA
, 64, do_casa
, a
, MO_TEUQ
)
4325 static bool do_ld_fpr(DisasContext
*dc
, arg_r_r_ri_asi
*a
, MemOp sz
)
4327 TCGv addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4333 if (gen_trap_ifnofpu(dc
)) {
4336 if (sz
== MO_128
&& gen_trap_float128(dc
)) {
4339 da
= resolve_asi(dc
, a
->asi
, MO_TE
| sz
);
4340 gen_ldf_asi(dc
, &da
, sz
, addr
, a
->rd
);
4341 gen_update_fprs_dirty(dc
, a
->rd
);
4342 return advance_pc(dc
);
4345 TRANS(LDF
, ALL
, do_ld_fpr
, a
, MO_32
)
4346 TRANS(LDDF
, ALL
, do_ld_fpr
, a
, MO_64
)
4347 TRANS(LDQF
, ALL
, do_ld_fpr
, a
, MO_128
)
4349 TRANS(LDFA
, 64, do_ld_fpr
, a
, MO_32
)
4350 TRANS(LDDFA
, 64, do_ld_fpr
, a
, MO_64
)
4351 TRANS(LDQFA
, 64, do_ld_fpr
, a
, MO_128
)
4353 static bool do_st_fpr(DisasContext
*dc
, arg_r_r_ri_asi
*a
, MemOp sz
)
4355 TCGv addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4361 if (gen_trap_ifnofpu(dc
)) {
4364 if (sz
== MO_128
&& gen_trap_float128(dc
)) {
4367 da
= resolve_asi(dc
, a
->asi
, MO_TE
| sz
);
4368 gen_stf_asi(dc
, &da
, sz
, addr
, a
->rd
);
4369 return advance_pc(dc
);
4372 TRANS(STF
, ALL
, do_st_fpr
, a
, MO_32
)
4373 TRANS(STDF
, ALL
, do_st_fpr
, a
, MO_64
)
4374 TRANS(STQF
, ALL
, do_st_fpr
, a
, MO_128
)
4376 TRANS(STFA
, 64, do_st_fpr
, a
, MO_32
)
4377 TRANS(STDFA
, 64, do_st_fpr
, a
, MO_64
)
4378 TRANS(STQFA
, 64, do_st_fpr
, a
, MO_128
)
4380 static bool trans_STDFQ(DisasContext
*dc
, arg_STDFQ
*a
)
4382 if (!avail_32(dc
)) {
4385 if (!supervisor(dc
)) {
4386 return raise_priv(dc
);
4388 if (gen_trap_ifnofpu(dc
)) {
4391 gen_op_fpexception_im(dc
, FSR_FTT_SEQ_ERROR
);
4395 static bool do_ldfsr(DisasContext
*dc
, arg_r_r_ri
*a
, MemOp mop
,
4396 target_ulong new_mask
, target_ulong old_mask
)
4398 TCGv tmp
, addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4402 if (gen_trap_ifnofpu(dc
)) {
4405 tmp
= tcg_temp_new();
4406 tcg_gen_qemu_ld_tl(tmp
, addr
, dc
->mem_idx
, mop
| MO_ALIGN
);
4407 tcg_gen_andi_tl(tmp
, tmp
, new_mask
);
4408 tcg_gen_andi_tl(cpu_fsr
, cpu_fsr
, old_mask
);
4409 tcg_gen_or_tl(cpu_fsr
, cpu_fsr
, tmp
);
4410 gen_helper_set_fsr(tcg_env
, cpu_fsr
);
4411 return advance_pc(dc
);
4414 TRANS(LDFSR
, ALL
, do_ldfsr
, a
, MO_TEUL
, FSR_LDFSR_MASK
, FSR_LDFSR_OLDMASK
)
4415 TRANS(LDXFSR
, 64, do_ldfsr
, a
, MO_TEUQ
, FSR_LDXFSR_MASK
, FSR_LDXFSR_OLDMASK
)
4417 static bool do_stfsr(DisasContext
*dc
, arg_r_r_ri
*a
, MemOp mop
)
4419 TCGv addr
= gen_ldst_addr(dc
, a
->rs1
, a
->imm
, a
->rs2_or_imm
);
4425 if (gen_trap_ifnofpu(dc
)) {
4429 fsr
= tcg_temp_new();
4430 gen_helper_get_fsr(fsr
, tcg_env
);
4431 tcg_gen_qemu_st_tl(fsr
, addr
, dc
->mem_idx
, mop
| MO_ALIGN
);
4432 return advance_pc(dc
);
4435 TRANS(STFSR
, ALL
, do_stfsr
, a
, MO_TEUL
)
4436 TRANS(STXFSR
, 64, do_stfsr
, a
, MO_TEUQ
)
4438 static bool do_fc(DisasContext
*dc
, int rd
, bool c
)
4442 if (gen_trap_ifnofpu(dc
)) {
4447 mask
= MAKE_64BIT_MASK(0, 32);
4449 mask
= MAKE_64BIT_MASK(32, 32);
4452 tcg_gen_ori_i64(cpu_fpr
[rd
/ 2], cpu_fpr
[rd
/ 2], mask
);
4454 tcg_gen_andi_i64(cpu_fpr
[rd
/ 2], cpu_fpr
[rd
/ 2], ~mask
);
4456 gen_update_fprs_dirty(dc
, rd
);
4457 return advance_pc(dc
);
4460 TRANS(FZEROs
, VIS1
, do_fc
, a
->rd
, 0)
4461 TRANS(FONEs
, VIS1
, do_fc
, a
->rd
, 1)
4463 static bool do_dc(DisasContext
*dc
, int rd
, int64_t c
)
4465 if (gen_trap_ifnofpu(dc
)) {
4469 tcg_gen_movi_i64(cpu_fpr
[rd
/ 2], c
);
4470 gen_update_fprs_dirty(dc
, rd
);
4471 return advance_pc(dc
);
4474 TRANS(FZEROd
, VIS1
, do_dc
, a
->rd
, 0)
4475 TRANS(FONEd
, VIS1
, do_dc
, a
->rd
, -1)
4477 static bool do_ff(DisasContext
*dc
, arg_r_r
*a
,
4478 void (*func
)(TCGv_i32
, TCGv_i32
))
4482 if (gen_trap_ifnofpu(dc
)) {
4486 tmp
= gen_load_fpr_F(dc
, a
->rs
);
4488 gen_store_fpr_F(dc
, a
->rd
, tmp
);
4489 return advance_pc(dc
);
4492 TRANS(FMOVs
, ALL
, do_ff
, a
, gen_op_fmovs
)
4493 TRANS(FNEGs
, ALL
, do_ff
, a
, gen_op_fnegs
)
4494 TRANS(FABSs
, ALL
, do_ff
, a
, gen_op_fabss
)
4495 TRANS(FSRCs
, VIS1
, do_ff
, a
, tcg_gen_mov_i32
)
4496 TRANS(FNOTs
, VIS1
, do_ff
, a
, tcg_gen_not_i32
)
4498 static bool do_fd(DisasContext
*dc
, arg_r_r
*a
,
4499 void (*func
)(TCGv_i32
, TCGv_i64
))
4504 if (gen_trap_ifnofpu(dc
)) {
4508 dst
= tcg_temp_new_i32();
4509 src
= gen_load_fpr_D(dc
, a
->rs
);
4511 gen_store_fpr_F(dc
, a
->rd
, dst
);
4512 return advance_pc(dc
);
4515 TRANS(FPACK16
, VIS1
, do_fd
, a
, gen_op_fpack16
)
4516 TRANS(FPACKFIX
, VIS1
, do_fd
, a
, gen_op_fpackfix
)
4518 static bool do_env_ff(DisasContext
*dc
, arg_r_r
*a
,
4519 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
))
4523 if (gen_trap_ifnofpu(dc
)) {
4527 gen_op_clear_ieee_excp_and_FTT();
4528 tmp
= gen_load_fpr_F(dc
, a
->rs
);
4529 func(tmp
, tcg_env
, tmp
);
4530 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4531 gen_store_fpr_F(dc
, a
->rd
, tmp
);
4532 return advance_pc(dc
);
4535 TRANS(FSQRTs
, ALL
, do_env_ff
, a
, gen_helper_fsqrts
)
4536 TRANS(FiTOs
, ALL
, do_env_ff
, a
, gen_helper_fitos
)
4537 TRANS(FsTOi
, ALL
, do_env_ff
, a
, gen_helper_fstoi
)
4539 static bool do_env_fd(DisasContext
*dc
, arg_r_r
*a
,
4540 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i64
))
4545 if (gen_trap_ifnofpu(dc
)) {
4549 gen_op_clear_ieee_excp_and_FTT();
4550 dst
= tcg_temp_new_i32();
4551 src
= gen_load_fpr_D(dc
, a
->rs
);
4552 func(dst
, tcg_env
, src
);
4553 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4554 gen_store_fpr_F(dc
, a
->rd
, dst
);
4555 return advance_pc(dc
);
4558 TRANS(FdTOs
, ALL
, do_env_fd
, a
, gen_helper_fdtos
)
4559 TRANS(FdTOi
, ALL
, do_env_fd
, a
, gen_helper_fdtoi
)
4560 TRANS(FxTOs
, 64, do_env_fd
, a
, gen_helper_fxtos
)
4562 static bool do_dd(DisasContext
*dc
, arg_r_r
*a
,
4563 void (*func
)(TCGv_i64
, TCGv_i64
))
4567 if (gen_trap_ifnofpu(dc
)) {
4571 dst
= gen_dest_fpr_D(dc
, a
->rd
);
4572 src
= gen_load_fpr_D(dc
, a
->rs
);
4574 gen_store_fpr_D(dc
, a
->rd
, dst
);
4575 return advance_pc(dc
);
4578 TRANS(FMOVd
, 64, do_dd
, a
, gen_op_fmovd
)
4579 TRANS(FNEGd
, 64, do_dd
, a
, gen_op_fnegd
)
4580 TRANS(FABSd
, 64, do_dd
, a
, gen_op_fabsd
)
4581 TRANS(FSRCd
, VIS1
, do_dd
, a
, tcg_gen_mov_i64
)
4582 TRANS(FNOTd
, VIS1
, do_dd
, a
, tcg_gen_not_i64
)
4584 static bool do_env_dd(DisasContext
*dc
, arg_r_r
*a
,
4585 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
))
4589 if (gen_trap_ifnofpu(dc
)) {
4593 gen_op_clear_ieee_excp_and_FTT();
4594 dst
= gen_dest_fpr_D(dc
, a
->rd
);
4595 src
= gen_load_fpr_D(dc
, a
->rs
);
4596 func(dst
, tcg_env
, src
);
4597 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4598 gen_store_fpr_D(dc
, a
->rd
, dst
);
4599 return advance_pc(dc
);
4602 TRANS(FSQRTd
, ALL
, do_env_dd
, a
, gen_helper_fsqrtd
)
4603 TRANS(FxTOd
, 64, do_env_dd
, a
, gen_helper_fxtod
)
4604 TRANS(FdTOx
, 64, do_env_dd
, a
, gen_helper_fdtox
)
4606 static bool do_env_df(DisasContext
*dc
, arg_r_r
*a
,
4607 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i32
))
4612 if (gen_trap_ifnofpu(dc
)) {
4616 gen_op_clear_ieee_excp_and_FTT();
4617 dst
= gen_dest_fpr_D(dc
, a
->rd
);
4618 src
= gen_load_fpr_F(dc
, a
->rs
);
4619 func(dst
, tcg_env
, src
);
4620 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4621 gen_store_fpr_D(dc
, a
->rd
, dst
);
4622 return advance_pc(dc
);
4625 TRANS(FiTOd
, ALL
, do_env_df
, a
, gen_helper_fitod
)
4626 TRANS(FsTOd
, ALL
, do_env_df
, a
, gen_helper_fstod
)
4627 TRANS(FsTOx
, 64, do_env_df
, a
, gen_helper_fstox
)
4629 static bool do_qq(DisasContext
*dc
, arg_r_r
*a
,
4630 void (*func
)(TCGv_i128
, TCGv_i128
))
4634 if (gen_trap_ifnofpu(dc
)) {
4637 if (gen_trap_float128(dc
)) {
4641 gen_op_clear_ieee_excp_and_FTT();
4642 t
= gen_load_fpr_Q(dc
, a
->rs
);
4644 gen_store_fpr_Q(dc
, a
->rd
, t
);
4645 return advance_pc(dc
);
4648 TRANS(FMOVq
, 64, do_qq
, a
, tcg_gen_mov_i128
)
4649 TRANS(FNEGq
, 64, do_qq
, a
, gen_op_fnegq
)
4650 TRANS(FABSq
, 64, do_qq
, a
, gen_op_fabsq
)
4652 static bool do_env_qq(DisasContext
*dc
, arg_r_r
*a
,
4653 void (*func
)(TCGv_i128
, TCGv_env
, TCGv_i128
))
4657 if (gen_trap_ifnofpu(dc
)) {
4660 if (gen_trap_float128(dc
)) {
4664 gen_op_clear_ieee_excp_and_FTT();
4666 t
= gen_load_fpr_Q(dc
, a
->rs
);
4667 func(t
, tcg_env
, t
);
4668 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4669 gen_store_fpr_Q(dc
, a
->rd
, t
);
4670 return advance_pc(dc
);
4673 TRANS(FSQRTq
, ALL
, do_env_qq
, a
, gen_helper_fsqrtq
)
4675 static bool do_env_fq(DisasContext
*dc
, arg_r_r
*a
,
4676 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i128
))
4681 if (gen_trap_ifnofpu(dc
)) {
4684 if (gen_trap_float128(dc
)) {
4688 gen_op_clear_ieee_excp_and_FTT();
4689 src
= gen_load_fpr_Q(dc
, a
->rs
);
4690 dst
= tcg_temp_new_i32();
4691 func(dst
, tcg_env
, src
);
4692 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4693 gen_store_fpr_F(dc
, a
->rd
, dst
);
4694 return advance_pc(dc
);
4697 TRANS(FqTOs
, ALL
, do_env_fq
, a
, gen_helper_fqtos
)
4698 TRANS(FqTOi
, ALL
, do_env_fq
, a
, gen_helper_fqtoi
)
4700 static bool do_env_dq(DisasContext
*dc
, arg_r_r
*a
,
4701 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i128
))
4706 if (gen_trap_ifnofpu(dc
)) {
4709 if (gen_trap_float128(dc
)) {
4713 gen_op_clear_ieee_excp_and_FTT();
4714 src
= gen_load_fpr_Q(dc
, a
->rs
);
4715 dst
= gen_dest_fpr_D(dc
, a
->rd
);
4716 func(dst
, tcg_env
, src
);
4717 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4718 gen_store_fpr_D(dc
, a
->rd
, dst
);
4719 return advance_pc(dc
);
4722 TRANS(FqTOd
, ALL
, do_env_dq
, a
, gen_helper_fqtod
)
4723 TRANS(FqTOx
, 64, do_env_dq
, a
, gen_helper_fqtox
)
4725 static bool do_env_qf(DisasContext
*dc
, arg_r_r
*a
,
4726 void (*func
)(TCGv_i128
, TCGv_env
, TCGv_i32
))
4731 if (gen_trap_ifnofpu(dc
)) {
4734 if (gen_trap_float128(dc
)) {
4738 gen_op_clear_ieee_excp_and_FTT();
4739 src
= gen_load_fpr_F(dc
, a
->rs
);
4740 dst
= tcg_temp_new_i128();
4741 func(dst
, tcg_env
, src
);
4742 gen_store_fpr_Q(dc
, a
->rd
, dst
);
4743 return advance_pc(dc
);
4746 TRANS(FiTOq
, ALL
, do_env_qf
, a
, gen_helper_fitoq
)
4747 TRANS(FsTOq
, ALL
, do_env_qf
, a
, gen_helper_fstoq
)
4749 static bool do_env_qd(DisasContext
*dc
, arg_r_r
*a
,
4750 void (*func
)(TCGv_i128
, TCGv_env
, TCGv_i64
))
4755 if (gen_trap_ifnofpu(dc
)) {
4758 if (gen_trap_float128(dc
)) {
4762 gen_op_clear_ieee_excp_and_FTT();
4763 src
= gen_load_fpr_D(dc
, a
->rs
);
4764 dst
= tcg_temp_new_i128();
4765 func(dst
, tcg_env
, src
);
4766 gen_store_fpr_Q(dc
, a
->rd
, dst
);
4767 return advance_pc(dc
);
4770 TRANS(FdTOq
, ALL
, do_env_qd
, a
, gen_helper_fdtoq
)
4771 TRANS(FxTOq
, 64, do_env_qd
, a
, gen_helper_fxtoq
)
4773 static bool do_fff(DisasContext
*dc
, arg_r_r_r
*a
,
4774 void (*func
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
4776 TCGv_i32 src1
, src2
;
4778 if (gen_trap_ifnofpu(dc
)) {
4782 src1
= gen_load_fpr_F(dc
, a
->rs1
);
4783 src2
= gen_load_fpr_F(dc
, a
->rs2
);
4784 func(src1
, src1
, src2
);
4785 gen_store_fpr_F(dc
, a
->rd
, src1
);
4786 return advance_pc(dc
);
4789 TRANS(FPADD16s
, VIS1
, do_fff
, a
, tcg_gen_vec_add16_i32
)
4790 TRANS(FPADD32s
, VIS1
, do_fff
, a
, tcg_gen_add_i32
)
4791 TRANS(FPSUB16s
, VIS1
, do_fff
, a
, tcg_gen_vec_sub16_i32
)
4792 TRANS(FPSUB32s
, VIS1
, do_fff
, a
, tcg_gen_sub_i32
)
4793 TRANS(FNORs
, VIS1
, do_fff
, a
, tcg_gen_nor_i32
)
4794 TRANS(FANDNOTs
, VIS1
, do_fff
, a
, tcg_gen_andc_i32
)
4795 TRANS(FXORs
, VIS1
, do_fff
, a
, tcg_gen_xor_i32
)
4796 TRANS(FNANDs
, VIS1
, do_fff
, a
, tcg_gen_nand_i32
)
4797 TRANS(FANDs
, VIS1
, do_fff
, a
, tcg_gen_and_i32
)
4798 TRANS(FXNORs
, VIS1
, do_fff
, a
, tcg_gen_eqv_i32
)
4799 TRANS(FORNOTs
, VIS1
, do_fff
, a
, tcg_gen_orc_i32
)
4800 TRANS(FORs
, VIS1
, do_fff
, a
, tcg_gen_or_i32
)
4802 static bool do_env_fff(DisasContext
*dc
, arg_r_r_r
*a
,
4803 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
, TCGv_i32
))
4805 TCGv_i32 src1
, src2
;
4807 if (gen_trap_ifnofpu(dc
)) {
4811 gen_op_clear_ieee_excp_and_FTT();
4812 src1
= gen_load_fpr_F(dc
, a
->rs1
);
4813 src2
= gen_load_fpr_F(dc
, a
->rs2
);
4814 func(src1
, tcg_env
, src1
, src2
);
4815 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4816 gen_store_fpr_F(dc
, a
->rd
, src1
);
4817 return advance_pc(dc
);
4820 TRANS(FADDs
, ALL
, do_env_fff
, a
, gen_helper_fadds
)
4821 TRANS(FSUBs
, ALL
, do_env_fff
, a
, gen_helper_fsubs
)
4822 TRANS(FMULs
, ALL
, do_env_fff
, a
, gen_helper_fmuls
)
4823 TRANS(FDIVs
, ALL
, do_env_fff
, a
, gen_helper_fdivs
)
4825 static bool do_ddd(DisasContext
*dc
, arg_r_r_r
*a
,
4826 void (*func
)(TCGv_i64
, TCGv_i64
, TCGv_i64
))
4828 TCGv_i64 dst
, src1
, src2
;
4830 if (gen_trap_ifnofpu(dc
)) {
4834 dst
= gen_dest_fpr_D(dc
, a
->rd
);
4835 src1
= gen_load_fpr_D(dc
, a
->rs1
);
4836 src2
= gen_load_fpr_D(dc
, a
->rs2
);
4837 func(dst
, src1
, src2
);
4838 gen_store_fpr_D(dc
, a
->rd
, dst
);
4839 return advance_pc(dc
);
4842 TRANS(FMUL8x16
, VIS1
, do_ddd
, a
, gen_helper_fmul8x16
)
4843 TRANS(FMUL8x16AU
, VIS1
, do_ddd
, a
, gen_helper_fmul8x16au
)
4844 TRANS(FMUL8x16AL
, VIS1
, do_ddd
, a
, gen_helper_fmul8x16al
)
4845 TRANS(FMUL8SUx16
, VIS1
, do_ddd
, a
, gen_helper_fmul8sux16
)
4846 TRANS(FMUL8ULx16
, VIS1
, do_ddd
, a
, gen_helper_fmul8ulx16
)
4847 TRANS(FMULD8SUx16
, VIS1
, do_ddd
, a
, gen_helper_fmuld8sux16
)
4848 TRANS(FMULD8ULx16
, VIS1
, do_ddd
, a
, gen_helper_fmuld8ulx16
)
4849 TRANS(FPMERGE
, VIS1
, do_ddd
, a
, gen_helper_fpmerge
)
4850 TRANS(FEXPAND
, VIS1
, do_ddd
, a
, gen_helper_fexpand
)
4852 TRANS(FPADD16
, VIS1
, do_ddd
, a
, tcg_gen_vec_add16_i64
)
4853 TRANS(FPADD32
, VIS1
, do_ddd
, a
, tcg_gen_vec_add32_i64
)
4854 TRANS(FPSUB16
, VIS1
, do_ddd
, a
, tcg_gen_vec_sub16_i64
)
4855 TRANS(FPSUB32
, VIS1
, do_ddd
, a
, tcg_gen_vec_sub32_i64
)
4856 TRANS(FNORd
, VIS1
, do_ddd
, a
, tcg_gen_nor_i64
)
4857 TRANS(FANDNOTd
, VIS1
, do_ddd
, a
, tcg_gen_andc_i64
)
4858 TRANS(FXORd
, VIS1
, do_ddd
, a
, tcg_gen_xor_i64
)
4859 TRANS(FNANDd
, VIS1
, do_ddd
, a
, tcg_gen_nand_i64
)
4860 TRANS(FANDd
, VIS1
, do_ddd
, a
, tcg_gen_and_i64
)
4861 TRANS(FXNORd
, VIS1
, do_ddd
, a
, tcg_gen_eqv_i64
)
4862 TRANS(FORNOTd
, VIS1
, do_ddd
, a
, tcg_gen_orc_i64
)
4863 TRANS(FORd
, VIS1
, do_ddd
, a
, tcg_gen_or_i64
)
4865 TRANS(FPACK32
, VIS1
, do_ddd
, a
, gen_op_fpack32
)
4866 TRANS(FALIGNDATAg
, VIS1
, do_ddd
, a
, gen_op_faligndata
)
4867 TRANS(BSHUFFLE
, VIS2
, do_ddd
, a
, gen_op_bshuffle
)
4869 static bool do_rdd(DisasContext
*dc
, arg_r_r_r
*a
,
4870 void (*func
)(TCGv
, TCGv_i64
, TCGv_i64
))
4872 TCGv_i64 src1
, src2
;
4875 if (gen_trap_ifnofpu(dc
)) {
4879 dst
= gen_dest_gpr(dc
, a
->rd
);
4880 src1
= gen_load_fpr_D(dc
, a
->rs1
);
4881 src2
= gen_load_fpr_D(dc
, a
->rs2
);
4882 func(dst
, src1
, src2
);
4883 gen_store_gpr(dc
, a
->rd
, dst
);
4884 return advance_pc(dc
);
4887 TRANS(FPCMPLE16
, VIS1
, do_rdd
, a
, gen_helper_fcmple16
)
4888 TRANS(FPCMPNE16
, VIS1
, do_rdd
, a
, gen_helper_fcmpne16
)
4889 TRANS(FPCMPGT16
, VIS1
, do_rdd
, a
, gen_helper_fcmpgt16
)
4890 TRANS(FPCMPEQ16
, VIS1
, do_rdd
, a
, gen_helper_fcmpeq16
)
4892 TRANS(FPCMPLE32
, VIS1
, do_rdd
, a
, gen_helper_fcmple32
)
4893 TRANS(FPCMPNE32
, VIS1
, do_rdd
, a
, gen_helper_fcmpne32
)
4894 TRANS(FPCMPGT32
, VIS1
, do_rdd
, a
, gen_helper_fcmpgt32
)
4895 TRANS(FPCMPEQ32
, VIS1
, do_rdd
, a
, gen_helper_fcmpeq32
)
4897 static bool do_env_ddd(DisasContext
*dc
, arg_r_r_r
*a
,
4898 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
, TCGv_i64
))
4900 TCGv_i64 dst
, src1
, src2
;
4902 if (gen_trap_ifnofpu(dc
)) {
4906 gen_op_clear_ieee_excp_and_FTT();
4907 dst
= gen_dest_fpr_D(dc
, a
->rd
);
4908 src1
= gen_load_fpr_D(dc
, a
->rs1
);
4909 src2
= gen_load_fpr_D(dc
, a
->rs2
);
4910 func(dst
, tcg_env
, src1
, src2
);
4911 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4912 gen_store_fpr_D(dc
, a
->rd
, dst
);
4913 return advance_pc(dc
);
4916 TRANS(FADDd
, ALL
, do_env_ddd
, a
, gen_helper_faddd
)
4917 TRANS(FSUBd
, ALL
, do_env_ddd
, a
, gen_helper_fsubd
)
4918 TRANS(FMULd
, ALL
, do_env_ddd
, a
, gen_helper_fmuld
)
4919 TRANS(FDIVd
, ALL
, do_env_ddd
, a
, gen_helper_fdivd
)
4921 static bool trans_FsMULd(DisasContext
*dc
, arg_r_r_r
*a
)
4924 TCGv_i32 src1
, src2
;
4926 if (gen_trap_ifnofpu(dc
)) {
4929 if (!(dc
->def
->features
& CPU_FEATURE_FSMULD
)) {
4930 return raise_unimpfpop(dc
);
4933 gen_op_clear_ieee_excp_and_FTT();
4934 dst
= gen_dest_fpr_D(dc
, a
->rd
);
4935 src1
= gen_load_fpr_F(dc
, a
->rs1
);
4936 src2
= gen_load_fpr_F(dc
, a
->rs2
);
4937 gen_helper_fsmuld(dst
, tcg_env
, src1
, src2
);
4938 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4939 gen_store_fpr_D(dc
, a
->rd
, dst
);
4940 return advance_pc(dc
);
4943 static bool do_dddd(DisasContext
*dc
, arg_r_r_r
*a
,
4944 void (*func
)(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_i64
))
4946 TCGv_i64 dst
, src0
, src1
, src2
;
4948 if (gen_trap_ifnofpu(dc
)) {
4952 dst
= gen_dest_fpr_D(dc
, a
->rd
);
4953 src0
= gen_load_fpr_D(dc
, a
->rd
);
4954 src1
= gen_load_fpr_D(dc
, a
->rs1
);
4955 src2
= gen_load_fpr_D(dc
, a
->rs2
);
4956 func(dst
, src0
, src1
, src2
);
4957 gen_store_fpr_D(dc
, a
->rd
, dst
);
4958 return advance_pc(dc
);
4961 TRANS(PDIST
, VIS1
, do_dddd
, a
, gen_helper_pdist
)
4963 static bool do_env_qqq(DisasContext
*dc
, arg_r_r_r
*a
,
4964 void (*func
)(TCGv_i128
, TCGv_env
, TCGv_i128
, TCGv_i128
))
4966 TCGv_i128 src1
, src2
;
4968 if (gen_trap_ifnofpu(dc
)) {
4971 if (gen_trap_float128(dc
)) {
4975 gen_op_clear_ieee_excp_and_FTT();
4976 src1
= gen_load_fpr_Q(dc
, a
->rs1
);
4977 src2
= gen_load_fpr_Q(dc
, a
->rs2
);
4978 func(src1
, tcg_env
, src1
, src2
);
4979 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
4980 gen_store_fpr_Q(dc
, a
->rd
, src1
);
4981 return advance_pc(dc
);
4984 TRANS(FADDq
, ALL
, do_env_qqq
, a
, gen_helper_faddq
)
4985 TRANS(FSUBq
, ALL
, do_env_qqq
, a
, gen_helper_fsubq
)
4986 TRANS(FMULq
, ALL
, do_env_qqq
, a
, gen_helper_fmulq
)
4987 TRANS(FDIVq
, ALL
, do_env_qqq
, a
, gen_helper_fdivq
)
4989 static bool trans_FdMULq(DisasContext
*dc
, arg_r_r_r
*a
)
4991 TCGv_i64 src1
, src2
;
4994 if (gen_trap_ifnofpu(dc
)) {
4997 if (gen_trap_float128(dc
)) {
5001 gen_op_clear_ieee_excp_and_FTT();
5002 src1
= gen_load_fpr_D(dc
, a
->rs1
);
5003 src2
= gen_load_fpr_D(dc
, a
->rs2
);
5004 dst
= tcg_temp_new_i128();
5005 gen_helper_fdmulq(dst
, tcg_env
, src1
, src2
);
5006 gen_helper_check_ieee_exceptions(cpu_fsr
, tcg_env
);
5007 gen_store_fpr_Q(dc
, a
->rd
, dst
);
5008 return advance_pc(dc
);
5011 static bool do_fmovr(DisasContext
*dc
, arg_FMOVRs
*a
, bool is_128
,
5012 void (*func
)(DisasContext
*, DisasCompare
*, int, int))
5016 if (!gen_compare_reg(&cmp
, a
->cond
, gen_load_gpr(dc
, a
->rs1
))) {
5019 if (gen_trap_ifnofpu(dc
)) {
5022 if (is_128
&& gen_trap_float128(dc
)) {
5026 gen_op_clear_ieee_excp_and_FTT();
5027 func(dc
, &cmp
, a
->rd
, a
->rs2
);
5028 return advance_pc(dc
);
5031 TRANS(FMOVRs
, 64, do_fmovr
, a
, false, gen_fmovs
)
5032 TRANS(FMOVRd
, 64, do_fmovr
, a
, false, gen_fmovd
)
5033 TRANS(FMOVRq
, 64, do_fmovr
, a
, true, gen_fmovq
)
5035 static bool do_fmovcc(DisasContext
*dc
, arg_FMOVscc
*a
, bool is_128
,
5036 void (*func
)(DisasContext
*, DisasCompare
*, int, int))
5040 if (gen_trap_ifnofpu(dc
)) {
5043 if (is_128
&& gen_trap_float128(dc
)) {
5047 gen_op_clear_ieee_excp_and_FTT();
5048 gen_compare(&cmp
, a
->cc
, a
->cond
, dc
);
5049 func(dc
, &cmp
, a
->rd
, a
->rs2
);
5050 return advance_pc(dc
);
5053 TRANS(FMOVscc
, 64, do_fmovcc
, a
, false, gen_fmovs
)
5054 TRANS(FMOVdcc
, 64, do_fmovcc
, a
, false, gen_fmovd
)
5055 TRANS(FMOVqcc
, 64, do_fmovcc
, a
, true, gen_fmovq
)
5057 static bool do_fmovfcc(DisasContext
*dc
, arg_FMOVsfcc
*a
, bool is_128
,
5058 void (*func
)(DisasContext
*, DisasCompare
*, int, int))
5062 if (gen_trap_ifnofpu(dc
)) {
5065 if (is_128
&& gen_trap_float128(dc
)) {
5069 gen_op_clear_ieee_excp_and_FTT();
5070 gen_fcompare(&cmp
, a
->cc
, a
->cond
);
5071 func(dc
, &cmp
, a
->rd
, a
->rs2
);
5072 return advance_pc(dc
);
5075 TRANS(FMOVsfcc
, 64, do_fmovfcc
, a
, false, gen_fmovs
)
5076 TRANS(FMOVdfcc
, 64, do_fmovfcc
, a
, false, gen_fmovd
)
5077 TRANS(FMOVqfcc
, 64, do_fmovfcc
, a
, true, gen_fmovq
)
5079 static bool do_fcmps(DisasContext
*dc
, arg_FCMPs
*a
, bool e
)
5081 TCGv_i32 src1
, src2
;
5083 if (avail_32(dc
) && a
->cc
!= 0) {
5086 if (gen_trap_ifnofpu(dc
)) {
5090 gen_op_clear_ieee_excp_and_FTT();
5091 src1
= gen_load_fpr_F(dc
, a
->rs1
);
5092 src2
= gen_load_fpr_F(dc
, a
->rs2
);
5094 gen_op_fcmpes(a
->cc
, src1
, src2
);
5096 gen_op_fcmps(a
->cc
, src1
, src2
);
5098 return advance_pc(dc
);
5101 TRANS(FCMPs
, ALL
, do_fcmps
, a
, false)
5102 TRANS(FCMPEs
, ALL
, do_fcmps
, a
, true)
5104 static bool do_fcmpd(DisasContext
*dc
, arg_FCMPd
*a
, bool e
)
5106 TCGv_i64 src1
, src2
;
5108 if (avail_32(dc
) && a
->cc
!= 0) {
5111 if (gen_trap_ifnofpu(dc
)) {
5115 gen_op_clear_ieee_excp_and_FTT();
5116 src1
= gen_load_fpr_D(dc
, a
->rs1
);
5117 src2
= gen_load_fpr_D(dc
, a
->rs2
);
5119 gen_op_fcmped(a
->cc
, src1
, src2
);
5121 gen_op_fcmpd(a
->cc
, src1
, src2
);
5123 return advance_pc(dc
);
5126 TRANS(FCMPd
, ALL
, do_fcmpd
, a
, false)
5127 TRANS(FCMPEd
, ALL
, do_fcmpd
, a
, true)
5129 static bool do_fcmpq(DisasContext
*dc
, arg_FCMPq
*a
, bool e
)
5131 TCGv_i128 src1
, src2
;
5133 if (avail_32(dc
) && a
->cc
!= 0) {
5136 if (gen_trap_ifnofpu(dc
)) {
5139 if (gen_trap_float128(dc
)) {
5143 gen_op_clear_ieee_excp_and_FTT();
5144 src1
= gen_load_fpr_Q(dc
, a
->rs1
);
5145 src2
= gen_load_fpr_Q(dc
, a
->rs2
);
5147 gen_op_fcmpeq(a
->cc
, src1
, src2
);
5149 gen_op_fcmpq(a
->cc
, src1
, src2
);
5151 return advance_pc(dc
);
5154 TRANS(FCMPq
, ALL
, do_fcmpq
, a
, false)
5155 TRANS(FCMPEq
, ALL
, do_fcmpq
, a
, true)
5157 static void sparc_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
5159 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
5160 CPUSPARCState
*env
= cpu_env(cs
);
5163 dc
->pc
= dc
->base
.pc_first
;
5164 dc
->npc
= (target_ulong
)dc
->base
.tb
->cs_base
;
5165 dc
->mem_idx
= dc
->base
.tb
->flags
& TB_FLAG_MMU_MASK
;
5166 dc
->def
= &env
->def
;
5167 dc
->fpu_enabled
= tb_fpu_enabled(dc
->base
.tb
->flags
);
5168 dc
->address_mask_32bit
= tb_am_enabled(dc
->base
.tb
->flags
);
5169 #ifndef CONFIG_USER_ONLY
5170 dc
->supervisor
= (dc
->base
.tb
->flags
& TB_FLAG_SUPER
) != 0;
5172 #ifdef TARGET_SPARC64
5174 dc
->asi
= (dc
->base
.tb
->flags
>> TB_FLAG_ASI_SHIFT
) & 0xff;
5175 #ifndef CONFIG_USER_ONLY
5176 dc
->hypervisor
= (dc
->base
.tb
->flags
& TB_FLAG_HYPER
) != 0;
5180 * if we reach a page boundary, we stop generation so that the
5181 * PC of a TT_TFAULT exception is always in the right page
5183 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
5184 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
5187 static void sparc_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
5191 static void sparc_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
5193 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
5194 target_ulong npc
= dc
->npc
;
5199 assert(dc
->jump_pc
[1] == dc
->pc
+ 4);
5200 npc
= dc
->jump_pc
[0] | JUMP_PC
;
5203 case DYNAMIC_PC_LOOKUP
:
5207 g_assert_not_reached();
5210 tcg_gen_insn_start(dc
->pc
, npc
);
5213 static void sparc_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
5215 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
5216 CPUSPARCState
*env
= cpu_env(cs
);
5219 insn
= translator_ldl(env
, &dc
->base
, dc
->pc
);
5220 dc
->base
.pc_next
+= 4;
5222 if (!decode(dc
, insn
)) {
5223 gen_exception(dc
, TT_ILL_INSN
);
5226 if (dc
->base
.is_jmp
== DISAS_NORETURN
) {
5229 if (dc
->pc
!= dc
->base
.pc_next
) {
5230 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
5234 static void sparc_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
5236 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
5237 DisasDelayException
*e
, *e_next
;
5242 switch (dc
->base
.is_jmp
) {
5244 case DISAS_TOO_MANY
:
5245 if (((dc
->pc
| dc
->npc
) & 3) == 0) {
5246 /* static PC and NPC: we can use direct chaining */
5247 gen_goto_tb(dc
, 0, dc
->pc
, dc
->npc
);
5254 case DYNAMIC_PC_LOOKUP
:
5260 g_assert_not_reached();
5263 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
5269 gen_generic_branch(dc
);
5274 case DYNAMIC_PC_LOOKUP
:
5277 g_assert_not_reached();
5280 tcg_gen_movi_tl(cpu_npc
, dc
->npc
);
5283 tcg_gen_lookup_and_goto_ptr();
5285 tcg_gen_exit_tb(NULL
, 0);
5289 case DISAS_NORETURN
:
5295 tcg_gen_exit_tb(NULL
, 0);
5299 g_assert_not_reached();
5302 for (e
= dc
->delay_excp_list
; e
; e
= e_next
) {
5303 gen_set_label(e
->lab
);
5305 tcg_gen_movi_tl(cpu_pc
, e
->pc
);
5306 if (e
->npc
% 4 == 0) {
5307 tcg_gen_movi_tl(cpu_npc
, e
->npc
);
5309 gen_helper_raise_exception(tcg_env
, e
->excp
);
5316 static void sparc_tr_disas_log(const DisasContextBase
*dcbase
,
5317 CPUState
*cpu
, FILE *logfile
)
5319 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
5320 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
5323 static const TranslatorOps sparc_tr_ops
= {
5324 .init_disas_context
= sparc_tr_init_disas_context
,
5325 .tb_start
= sparc_tr_tb_start
,
5326 .insn_start
= sparc_tr_insn_start
,
5327 .translate_insn
= sparc_tr_translate_insn
,
5328 .tb_stop
= sparc_tr_tb_stop
,
5329 .disas_log
= sparc_tr_disas_log
,
5332 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
5333 vaddr pc
, void *host_pc
)
5335 DisasContext dc
= {};
5337 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &sparc_tr_ops
, &dc
.base
);
5340 void sparc_tcg_init(void)
5342 static const char gregnames
[32][4] = {
5343 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
5344 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5345 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5346 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
5348 static const char fregnames
[32][4] = {
5349 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5350 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5351 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5352 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
5355 static const struct { TCGv
*ptr
; int off
; const char *name
; } rtl
[] = {
5356 #ifdef TARGET_SPARC64
5357 { &cpu_gsr
, offsetof(CPUSPARCState
, gsr
), "gsr" },
5358 { &cpu_xcc_Z
, offsetof(CPUSPARCState
, xcc_Z
), "xcc_Z" },
5359 { &cpu_xcc_C
, offsetof(CPUSPARCState
, xcc_C
), "xcc_C" },
5361 { &cpu_cc_N
, offsetof(CPUSPARCState
, cc_N
), "cc_N" },
5362 { &cpu_cc_V
, offsetof(CPUSPARCState
, cc_V
), "cc_V" },
5363 { &cpu_icc_Z
, offsetof(CPUSPARCState
, icc_Z
), "icc_Z" },
5364 { &cpu_icc_C
, offsetof(CPUSPARCState
, icc_C
), "icc_C" },
5365 { &cpu_cond
, offsetof(CPUSPARCState
, cond
), "cond" },
5366 { &cpu_fsr
, offsetof(CPUSPARCState
, fsr
), "fsr" },
5367 { &cpu_pc
, offsetof(CPUSPARCState
, pc
), "pc" },
5368 { &cpu_npc
, offsetof(CPUSPARCState
, npc
), "npc" },
5369 { &cpu_y
, offsetof(CPUSPARCState
, y
), "y" },
5370 { &cpu_tbr
, offsetof(CPUSPARCState
, tbr
), "tbr" },
5375 cpu_regwptr
= tcg_global_mem_new_ptr(tcg_env
,
5376 offsetof(CPUSPARCState
, regwptr
),
5379 for (i
= 0; i
< ARRAY_SIZE(rtl
); ++i
) {
5380 *rtl
[i
].ptr
= tcg_global_mem_new(tcg_env
, rtl
[i
].off
, rtl
[i
].name
);
5384 for (i
= 1; i
< 8; ++i
) {
5385 cpu_regs
[i
] = tcg_global_mem_new(tcg_env
,
5386 offsetof(CPUSPARCState
, gregs
[i
]),
5390 for (i
= 8; i
< 32; ++i
) {
5391 cpu_regs
[i
] = tcg_global_mem_new(cpu_regwptr
,
5392 (i
- 8) * sizeof(target_ulong
),
5396 for (i
= 0; i
< TARGET_DPREGS
; i
++) {
5397 cpu_fpr
[i
] = tcg_global_mem_new_i64(tcg_env
,
5398 offsetof(CPUSPARCState
, fpr
[i
]),
5402 #ifdef TARGET_SPARC64
5403 cpu_fprs
= tcg_global_mem_new_i32(tcg_env
,
5404 offsetof(CPUSPARCState
, fprs
), "fprs");
5408 void sparc_restore_state_to_opc(CPUState
*cs
,
5409 const TranslationBlock
*tb
,
5410 const uint64_t *data
)
5412 SPARCCPU
*cpu
= SPARC_CPU(cs
);
5413 CPUSPARCState
*env
= &cpu
->env
;
5414 target_ulong pc
= data
[0];
5415 target_ulong npc
= data
[1];
5418 if (npc
== DYNAMIC_PC
) {
5419 /* dynamic NPC: already stored */
5420 } else if (npc
& JUMP_PC
) {
5421 /* jump PC: use 'cond' and the jump targets of the translation */
5423 env
->npc
= npc
& ~3;