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target/tricore: Use setcondi instead of explicit allocation
[mirror_qemu.git] / target / tricore / translate.c
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "exec/cpu_ldst.h"
27 #include "qemu/qemu-print.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "tricore-opcodes.h"
33 #include "exec/translator.h"
34 #include "exec/log.h"
35
36 /*
37 * TCG registers
38 */
39 static TCGv cpu_PC;
40 static TCGv cpu_PCXI;
41 static TCGv cpu_PSW;
42 static TCGv cpu_ICR;
43 /* GPR registers */
44 static TCGv cpu_gpr_a[16];
45 static TCGv cpu_gpr_d[16];
46 /* PSW Flag cache */
47 static TCGv cpu_PSW_C;
48 static TCGv cpu_PSW_V;
49 static TCGv cpu_PSW_SV;
50 static TCGv cpu_PSW_AV;
51 static TCGv cpu_PSW_SAV;
52
53 #include "exec/gen-icount.h"
54
55 static const char *regnames_a[] = {
56 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
57 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
58 "a12" , "a13" , "a14" , "a15",
59 };
60
61 static const char *regnames_d[] = {
62 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
63 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
64 "d12" , "d13" , "d14" , "d15",
65 };
66
67 typedef struct DisasContext {
68 DisasContextBase base;
69 target_ulong pc_succ_insn;
70 uint32_t opcode;
71 /* Routine used to access memory */
72 int mem_idx;
73 uint32_t hflags, saved_hflags;
74 uint64_t features;
75 } DisasContext;
76
77 static int has_feature(DisasContext *ctx, int feature)
78 {
79 return (ctx->features & (1ULL << feature)) != 0;
80 }
81
82 enum {
83 MODE_LL = 0,
84 MODE_LU = 1,
85 MODE_UL = 2,
86 MODE_UU = 3,
87 };
88
89 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
90 {
91 TriCoreCPU *cpu = TRICORE_CPU(cs);
92 CPUTriCoreState *env = &cpu->env;
93 uint32_t psw;
94 int i;
95
96 psw = psw_read(env);
97
98 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
99 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
100 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
101 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
102 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
103 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
104
105 for (i = 0; i < 16; ++i) {
106 if ((i & 3) == 0) {
107 qemu_fprintf(f, "\nGPR A%02d:", i);
108 }
109 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
110 }
111 for (i = 0; i < 16; ++i) {
112 if ((i & 3) == 0) {
113 qemu_fprintf(f, "\nGPR D%02d:", i);
114 }
115 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
116 }
117 qemu_fprintf(f, "\n");
118 }
119
120 /*
121 * Functions to generate micro-ops
122 */
123
124 /* Makros for generating helpers */
125
126 #define gen_helper_1arg(name, arg) do { \
127 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
128 gen_helper_##name(cpu_env, helper_tmp); \
129 } while (0)
130
131 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
132 TCGv arg00 = tcg_temp_new(); \
133 TCGv arg01 = tcg_temp_new(); \
134 TCGv arg11 = tcg_temp_new(); \
135 tcg_gen_sari_tl(arg00, arg0, 16); \
136 tcg_gen_ext16s_tl(arg01, arg0); \
137 tcg_gen_ext16s_tl(arg11, arg1); \
138 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
139 } while (0)
140
141 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
142 TCGv arg00 = tcg_temp_new(); \
143 TCGv arg01 = tcg_temp_new(); \
144 TCGv arg10 = tcg_temp_new(); \
145 TCGv arg11 = tcg_temp_new(); \
146 tcg_gen_sari_tl(arg00, arg0, 16); \
147 tcg_gen_ext16s_tl(arg01, arg0); \
148 tcg_gen_sari_tl(arg11, arg1, 16); \
149 tcg_gen_ext16s_tl(arg10, arg1); \
150 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
151 } while (0)
152
153 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
154 TCGv arg00 = tcg_temp_new(); \
155 TCGv arg01 = tcg_temp_new(); \
156 TCGv arg10 = tcg_temp_new(); \
157 TCGv arg11 = tcg_temp_new(); \
158 tcg_gen_sari_tl(arg00, arg0, 16); \
159 tcg_gen_ext16s_tl(arg01, arg0); \
160 tcg_gen_sari_tl(arg10, arg1, 16); \
161 tcg_gen_ext16s_tl(arg11, arg1); \
162 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
163 } while (0)
164
165 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
166 TCGv arg00 = tcg_temp_new(); \
167 TCGv arg01 = tcg_temp_new(); \
168 TCGv arg11 = tcg_temp_new(); \
169 tcg_gen_sari_tl(arg01, arg0, 16); \
170 tcg_gen_ext16s_tl(arg00, arg0); \
171 tcg_gen_sari_tl(arg11, arg1, 16); \
172 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
173 } while (0)
174
175 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
176 TCGv_i64 ret = tcg_temp_new_i64(); \
177 TCGv_i64 arg1 = tcg_temp_new_i64(); \
178 \
179 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
180 gen_helper_##name(ret, arg1, arg2); \
181 tcg_gen_extr_i64_i32(rl, rh, ret); \
182 } while (0)
183
184 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
185 TCGv_i64 ret = tcg_temp_new_i64(); \
186 \
187 gen_helper_##name(ret, cpu_env, arg1, arg2); \
188 tcg_gen_extr_i64_i32(rl, rh, ret); \
189 } while (0)
190
191 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
192 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
193 ((offset & 0x0fffff) << 1))
194
195 /* For two 32-bit registers used a 64-bit register, the first
196 registernumber needs to be even. Otherwise we trap. */
197 static inline void generate_trap(DisasContext *ctx, int class, int tin);
198 #define CHECK_REG_PAIR(reg) do { \
199 if (reg & 0x1) { \
200 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
201 } \
202 } while (0)
203
204 /* Functions for load/save to/from memory */
205
206 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
207 int16_t con, MemOp mop)
208 {
209 TCGv temp = tcg_temp_new();
210 tcg_gen_addi_tl(temp, r2, con);
211 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
212 }
213
214 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
215 int16_t con, MemOp mop)
216 {
217 TCGv temp = tcg_temp_new();
218 tcg_gen_addi_tl(temp, r2, con);
219 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
220 }
221
222 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
223 {
224 TCGv_i64 temp = tcg_temp_new_i64();
225
226 tcg_gen_concat_i32_i64(temp, rl, rh);
227 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ);
228 }
229
230 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
231 DisasContext *ctx)
232 {
233 TCGv temp = tcg_temp_new();
234 tcg_gen_addi_tl(temp, base, con);
235 gen_st_2regs_64(rh, rl, temp, ctx);
236 }
237
238 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
239 {
240 TCGv_i64 temp = tcg_temp_new_i64();
241
242 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ);
243 /* write back to two 32 bit regs */
244 tcg_gen_extr_i64_i32(rl, rh, temp);
245 }
246
247 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
248 DisasContext *ctx)
249 {
250 TCGv temp = tcg_temp_new();
251 tcg_gen_addi_tl(temp, base, con);
252 gen_ld_2regs_64(rh, rl, temp, ctx);
253 }
254
255 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
256 MemOp mop)
257 {
258 TCGv temp = tcg_temp_new();
259 tcg_gen_addi_tl(temp, r2, off);
260 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
261 tcg_gen_mov_tl(r2, temp);
262 }
263
264 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
265 MemOp mop)
266 {
267 TCGv temp = tcg_temp_new();
268 tcg_gen_addi_tl(temp, r2, off);
269 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
270 tcg_gen_mov_tl(r2, temp);
271 }
272
273 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
274 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
275 {
276 TCGv temp = tcg_temp_new();
277 TCGv temp2 = tcg_temp_new();
278
279 CHECK_REG_PAIR(ereg);
280 /* temp = (M(EA, word) */
281 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
282 /* temp = temp & ~E[a][63:32]) */
283 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
284 /* temp2 = (E[a][31:0] & E[a][63:32]); */
285 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
286 /* temp = temp | temp2; */
287 tcg_gen_or_tl(temp, temp, temp2);
288 /* M(EA, word) = temp; */
289 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
290 }
291
292 /* tmp = M(EA, word);
293 M(EA, word) = D[a];
294 D[a] = tmp[31:0];*/
295 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
296 {
297 TCGv temp = tcg_temp_new();
298
299 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
300 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
301 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
302 }
303
304 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
305 {
306 TCGv temp = tcg_temp_new();
307 TCGv temp2 = tcg_temp_new();
308 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
309 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
310 cpu_gpr_d[reg], temp);
311 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
312 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
313 }
314
315 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
316 {
317 TCGv temp = tcg_temp_new();
318 TCGv temp2 = tcg_temp_new();
319 TCGv temp3 = tcg_temp_new();
320
321 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
322 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
323 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
324 tcg_gen_or_tl(temp2, temp2, temp3);
325 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
326 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
327 }
328
329
330 /* We generate loads and store to core special function register (csfr) through
331 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
332 makros R, A and E, which allow read-only, all and endinit protected access.
333 These makros also specify in which ISA version the csfr was introduced. */
334 #define R(ADDRESS, REG, FEATURE) \
335 case ADDRESS: \
336 if (has_feature(ctx, FEATURE)) { \
337 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
338 } \
339 break;
340 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
341 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
342 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
343 {
344 /* since we're caching PSW make this a special case */
345 if (offset == 0xfe04) {
346 gen_helper_psw_read(ret, cpu_env);
347 } else {
348 switch (offset) {
349 #include "csfr.h.inc"
350 }
351 }
352 }
353 #undef R
354 #undef A
355 #undef E
356
357 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
358 since no execption occurs */
359 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
360 case ADDRESS: \
361 if (has_feature(ctx, FEATURE)) { \
362 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
363 } \
364 break;
365 /* Endinit protected registers
366 TODO: Since the endinit bit is in a register of a not yet implemented
367 watchdog device, we handle endinit protected registers like
368 all-access registers for now. */
369 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
370 static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
371 int32_t offset)
372 {
373 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
374 /* since we're caching PSW make this a special case */
375 if (offset == 0xfe04) {
376 gen_helper_psw_write(cpu_env, r1);
377 } else {
378 switch (offset) {
379 #include "csfr.h.inc"
380 }
381 }
382 } else {
383 /* generate privilege trap */
384 }
385 }
386
387 /* Functions for arithmetic instructions */
388
389 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
390 {
391 TCGv t0 = tcg_temp_new_i32();
392 TCGv result = tcg_temp_new_i32();
393 /* Addition and set V/SV bits */
394 tcg_gen_add_tl(result, r1, r2);
395 /* calc V bit */
396 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
397 tcg_gen_xor_tl(t0, r1, r2);
398 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
399 /* Calc SV bit */
400 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
401 /* Calc AV/SAV bits */
402 tcg_gen_add_tl(cpu_PSW_AV, result, result);
403 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
404 /* calc SAV */
405 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
406 /* write back result */
407 tcg_gen_mov_tl(ret, result);
408 }
409
410 static inline void
411 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
412 {
413 TCGv temp = tcg_temp_new();
414 TCGv_i64 t0 = tcg_temp_new_i64();
415 TCGv_i64 t1 = tcg_temp_new_i64();
416 TCGv_i64 result = tcg_temp_new_i64();
417
418 tcg_gen_add_i64(result, r1, r2);
419 /* calc v bit */
420 tcg_gen_xor_i64(t1, result, r1);
421 tcg_gen_xor_i64(t0, r1, r2);
422 tcg_gen_andc_i64(t1, t1, t0);
423 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
424 /* calc SV bit */
425 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
426 /* calc AV/SAV bits */
427 tcg_gen_extrh_i64_i32(temp, result);
428 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
429 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
430 /* calc SAV */
431 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
432 /* write back result */
433 tcg_gen_mov_i64(ret, result);
434 }
435
436 static inline void
437 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
438 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
439 void(*op2)(TCGv, TCGv, TCGv))
440 {
441 TCGv temp = tcg_temp_new();
442 TCGv temp2 = tcg_temp_new();
443 TCGv temp3 = tcg_temp_new();
444 TCGv temp4 = tcg_temp_new();
445
446 (*op1)(temp, r1_low, r2);
447 /* calc V0 bit */
448 tcg_gen_xor_tl(temp2, temp, r1_low);
449 tcg_gen_xor_tl(temp3, r1_low, r2);
450 if (op1 == tcg_gen_add_tl) {
451 tcg_gen_andc_tl(temp2, temp2, temp3);
452 } else {
453 tcg_gen_and_tl(temp2, temp2, temp3);
454 }
455
456 (*op2)(temp3, r1_high, r3);
457 /* calc V1 bit */
458 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
459 tcg_gen_xor_tl(temp4, r1_high, r3);
460 if (op2 == tcg_gen_add_tl) {
461 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
462 } else {
463 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
464 }
465 /* combine V0/V1 bits */
466 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
467 /* calc sv bit */
468 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
469 /* write result */
470 tcg_gen_mov_tl(ret_low, temp);
471 tcg_gen_mov_tl(ret_high, temp3);
472 /* calc AV bit */
473 tcg_gen_add_tl(temp, ret_low, ret_low);
474 tcg_gen_xor_tl(temp, temp, ret_low);
475 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
476 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
477 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
478 /* calc SAV bit */
479 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
480 }
481
482 /* ret = r2 + (r1 * r3); */
483 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
484 {
485 TCGv_i64 t1 = tcg_temp_new_i64();
486 TCGv_i64 t2 = tcg_temp_new_i64();
487 TCGv_i64 t3 = tcg_temp_new_i64();
488
489 tcg_gen_ext_i32_i64(t1, r1);
490 tcg_gen_ext_i32_i64(t2, r2);
491 tcg_gen_ext_i32_i64(t3, r3);
492
493 tcg_gen_mul_i64(t1, t1, t3);
494 tcg_gen_add_i64(t1, t2, t1);
495
496 tcg_gen_extrl_i64_i32(ret, t1);
497 /* calc V
498 t1 > 0x7fffffff */
499 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
500 /* t1 < -0x80000000 */
501 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
502 tcg_gen_or_i64(t2, t2, t3);
503 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
504 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
505 /* Calc SV bit */
506 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
507 /* Calc AV/SAV bits */
508 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
509 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
510 /* calc SAV */
511 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
512 }
513
514 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
515 {
516 TCGv temp = tcg_const_i32(con);
517 gen_madd32_d(ret, r1, r2, temp);
518 }
519
520 static inline void
521 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
522 TCGv r3)
523 {
524 TCGv t1 = tcg_temp_new();
525 TCGv t2 = tcg_temp_new();
526 TCGv t3 = tcg_temp_new();
527 TCGv t4 = tcg_temp_new();
528
529 tcg_gen_muls2_tl(t1, t2, r1, r3);
530 /* only the add can overflow */
531 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
532 /* calc V bit */
533 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
534 tcg_gen_xor_tl(t1, r2_high, t2);
535 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
536 /* Calc SV bit */
537 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
538 /* Calc AV/SAV bits */
539 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
540 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
541 /* calc SAV */
542 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
543 /* write back the result */
544 tcg_gen_mov_tl(ret_low, t3);
545 tcg_gen_mov_tl(ret_high, t4);
546 }
547
548 static inline void
549 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
550 TCGv r3)
551 {
552 TCGv_i64 t1 = tcg_temp_new_i64();
553 TCGv_i64 t2 = tcg_temp_new_i64();
554 TCGv_i64 t3 = tcg_temp_new_i64();
555
556 tcg_gen_extu_i32_i64(t1, r1);
557 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
558 tcg_gen_extu_i32_i64(t3, r3);
559
560 tcg_gen_mul_i64(t1, t1, t3);
561 tcg_gen_add_i64(t2, t2, t1);
562 /* write back result */
563 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
564 /* only the add overflows, if t2 < t1
565 calc V bit */
566 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
567 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
568 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
569 /* Calc SV bit */
570 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
571 /* Calc AV/SAV bits */
572 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
573 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
574 /* calc SAV */
575 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
576 }
577
578 static inline void
579 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
580 int32_t con)
581 {
582 TCGv temp = tcg_const_i32(con);
583 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
584 }
585
586 static inline void
587 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
588 int32_t con)
589 {
590 TCGv temp = tcg_const_i32(con);
591 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
592 }
593
594 static inline void
595 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
596 TCGv r3, uint32_t n, uint32_t mode)
597 {
598 TCGv t_n = tcg_constant_i32(n);
599 TCGv temp = tcg_temp_new();
600 TCGv temp2 = tcg_temp_new();
601 TCGv_i64 temp64 = tcg_temp_new_i64();
602 switch (mode) {
603 case MODE_LL:
604 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
605 break;
606 case MODE_LU:
607 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
608 break;
609 case MODE_UL:
610 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
611 break;
612 case MODE_UU:
613 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
614 break;
615 }
616 tcg_gen_extr_i64_i32(temp, temp2, temp64);
617 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
618 tcg_gen_add_tl, tcg_gen_add_tl);
619 }
620
621 static inline void
622 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
623 TCGv r3, uint32_t n, uint32_t mode)
624 {
625 TCGv t_n = tcg_constant_i32(n);
626 TCGv temp = tcg_temp_new();
627 TCGv temp2 = tcg_temp_new();
628 TCGv_i64 temp64 = tcg_temp_new_i64();
629 switch (mode) {
630 case MODE_LL:
631 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
632 break;
633 case MODE_LU:
634 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
635 break;
636 case MODE_UL:
637 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
638 break;
639 case MODE_UU:
640 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
641 break;
642 }
643 tcg_gen_extr_i64_i32(temp, temp2, temp64);
644 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
645 tcg_gen_sub_tl, tcg_gen_add_tl);
646 }
647
648 static inline void
649 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
650 TCGv r3, uint32_t n, uint32_t mode)
651 {
652 TCGv t_n = tcg_constant_i32(n);
653 TCGv_i64 temp64 = tcg_temp_new_i64();
654 TCGv_i64 temp64_2 = tcg_temp_new_i64();
655 TCGv_i64 temp64_3 = tcg_temp_new_i64();
656 switch (mode) {
657 case MODE_LL:
658 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
659 break;
660 case MODE_LU:
661 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
662 break;
663 case MODE_UL:
664 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
665 break;
666 case MODE_UU:
667 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
668 break;
669 }
670 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
671 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
672 tcg_gen_ext32s_i64(temp64, temp64); /* low */
673 tcg_gen_sub_i64(temp64, temp64_2, temp64);
674 tcg_gen_shli_i64(temp64, temp64, 16);
675
676 gen_add64_d(temp64_2, temp64_3, temp64);
677 /* write back result */
678 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
679 }
680
681 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
682
683 static inline void
684 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
685 TCGv r3, uint32_t n, uint32_t mode)
686 {
687 TCGv t_n = tcg_constant_i32(n);
688 TCGv temp = tcg_temp_new();
689 TCGv temp2 = tcg_temp_new();
690 TCGv temp3 = tcg_temp_new();
691 TCGv_i64 temp64 = tcg_temp_new_i64();
692
693 switch (mode) {
694 case MODE_LL:
695 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
696 break;
697 case MODE_LU:
698 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
699 break;
700 case MODE_UL:
701 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
702 break;
703 case MODE_UU:
704 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
705 break;
706 }
707 tcg_gen_extr_i64_i32(temp, temp2, temp64);
708 gen_adds(ret_low, r1_low, temp);
709 tcg_gen_mov_tl(temp, cpu_PSW_V);
710 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
711 gen_adds(ret_high, r1_high, temp2);
712 /* combine v bits */
713 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
714 /* combine av bits */
715 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
716 }
717
718 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
719
720 static inline void
721 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
722 TCGv r3, uint32_t n, uint32_t mode)
723 {
724 TCGv t_n = tcg_constant_i32(n);
725 TCGv temp = tcg_temp_new();
726 TCGv temp2 = tcg_temp_new();
727 TCGv temp3 = tcg_temp_new();
728 TCGv_i64 temp64 = tcg_temp_new_i64();
729
730 switch (mode) {
731 case MODE_LL:
732 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
733 break;
734 case MODE_LU:
735 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
736 break;
737 case MODE_UL:
738 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
739 break;
740 case MODE_UU:
741 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
742 break;
743 }
744 tcg_gen_extr_i64_i32(temp, temp2, temp64);
745 gen_subs(ret_low, r1_low, temp);
746 tcg_gen_mov_tl(temp, cpu_PSW_V);
747 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
748 gen_adds(ret_high, r1_high, temp2);
749 /* combine v bits */
750 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
751 /* combine av bits */
752 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
753 }
754
755 static inline void
756 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
757 TCGv r3, uint32_t n, uint32_t mode)
758 {
759 TCGv t_n = tcg_constant_i32(n);
760 TCGv_i64 temp64 = tcg_temp_new_i64();
761 TCGv_i64 temp64_2 = tcg_temp_new_i64();
762
763 switch (mode) {
764 case MODE_LL:
765 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
766 break;
767 case MODE_LU:
768 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
769 break;
770 case MODE_UL:
771 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
772 break;
773 case MODE_UU:
774 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
775 break;
776 }
777 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
778 tcg_gen_ext32s_i64(temp64, temp64); /* low */
779 tcg_gen_sub_i64(temp64, temp64_2, temp64);
780 tcg_gen_shli_i64(temp64, temp64, 16);
781 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
782
783 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
784 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
785 }
786
787
788 static inline void
789 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
790 TCGv r3, uint32_t n, uint32_t mode)
791 {
792 TCGv t_n = tcg_constant_i32(n);
793 TCGv_i64 temp64 = tcg_temp_new_i64();
794 TCGv_i64 temp64_2 = tcg_temp_new_i64();
795 TCGv_i64 temp64_3 = tcg_temp_new_i64();
796 switch (mode) {
797 case MODE_LL:
798 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
799 break;
800 case MODE_LU:
801 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
802 break;
803 case MODE_UL:
804 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
805 break;
806 case MODE_UU:
807 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
808 break;
809 }
810 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
811 gen_add64_d(temp64_3, temp64_2, temp64);
812 /* write back result */
813 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
814 }
815
816 static inline void
817 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
818 TCGv r3, uint32_t n, uint32_t mode)
819 {
820 TCGv t_n = tcg_constant_i32(n);
821 TCGv_i64 temp64 = tcg_temp_new_i64();
822 TCGv_i64 temp64_2 = tcg_temp_new_i64();
823 switch (mode) {
824 case MODE_LL:
825 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
826 break;
827 case MODE_LU:
828 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
829 break;
830 case MODE_UL:
831 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
832 break;
833 case MODE_UU:
834 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
835 break;
836 }
837 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
838 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
839 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
840 }
841
842 static inline void
843 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
844 uint32_t mode)
845 {
846 TCGv t_n = tcg_constant_i32(n);
847 TCGv_i64 temp64 = tcg_temp_new_i64();
848 switch (mode) {
849 case MODE_LL:
850 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
851 break;
852 case MODE_LU:
853 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
854 break;
855 case MODE_UL:
856 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
857 break;
858 case MODE_UU:
859 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
860 break;
861 }
862 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
863 }
864
865 static inline void
866 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
867 {
868 TCGv temp = tcg_temp_new();
869 TCGv temp2 = tcg_temp_new();
870
871 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
872 tcg_gen_shli_tl(temp, r1, 16);
873 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
874 }
875
876 static inline void
877 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
878 {
879 TCGv t_n = tcg_constant_i32(n);
880 TCGv temp = tcg_temp_new();
881 TCGv temp2 = tcg_temp_new();
882 TCGv_i64 temp64 = tcg_temp_new_i64();
883 switch (mode) {
884 case MODE_LL:
885 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
886 break;
887 case MODE_LU:
888 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
889 break;
890 case MODE_UL:
891 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
892 break;
893 case MODE_UU:
894 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
895 break;
896 }
897 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
898 tcg_gen_shli_tl(temp, r1, 16);
899 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
900 }
901
902
903 static inline void
904 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
905 uint32_t n, uint32_t mode)
906 {
907 TCGv t_n = tcg_constant_i32(n);
908 TCGv_i64 temp64 = tcg_temp_new_i64();
909 switch (mode) {
910 case MODE_LL:
911 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
912 break;
913 case MODE_LU:
914 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
915 break;
916 case MODE_UL:
917 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
918 break;
919 case MODE_UU:
920 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
921 break;
922 }
923 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
924 }
925
926 static inline void
927 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
928 {
929 TCGv temp = tcg_temp_new();
930 TCGv temp2 = tcg_temp_new();
931
932 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
933 tcg_gen_shli_tl(temp, r1, 16);
934 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
935 }
936
937 static inline void
938 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
939 {
940 TCGv t_n = tcg_constant_i32(n);
941 TCGv temp = tcg_temp_new();
942 TCGv temp2 = tcg_temp_new();
943 TCGv_i64 temp64 = tcg_temp_new_i64();
944 switch (mode) {
945 case MODE_LL:
946 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
947 break;
948 case MODE_LU:
949 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
950 break;
951 case MODE_UL:
952 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
953 break;
954 case MODE_UU:
955 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
956 break;
957 }
958 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
959 tcg_gen_shli_tl(temp, r1, 16);
960 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
961 }
962
963 static inline void
964 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
965 {
966 TCGv t_n = tcg_constant_i32(n);
967 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n);
968 }
969
970 static inline void
971 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
972 {
973 TCGv t_n = tcg_constant_i32(n);
974 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n);
975 }
976
977 static inline void
978 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
979 uint32_t up_shift)
980 {
981 TCGv temp = tcg_temp_new();
982 TCGv temp2 = tcg_temp_new();
983 TCGv temp3 = tcg_temp_new();
984 TCGv_i64 t1 = tcg_temp_new_i64();
985 TCGv_i64 t2 = tcg_temp_new_i64();
986 TCGv_i64 t3 = tcg_temp_new_i64();
987
988 tcg_gen_ext_i32_i64(t2, arg2);
989 tcg_gen_ext_i32_i64(t3, arg3);
990
991 tcg_gen_mul_i64(t2, t2, t3);
992 tcg_gen_shli_i64(t2, t2, n);
993
994 tcg_gen_ext_i32_i64(t1, arg1);
995 tcg_gen_sari_i64(t2, t2, up_shift);
996
997 tcg_gen_add_i64(t3, t1, t2);
998 tcg_gen_extrl_i64_i32(temp3, t3);
999 /* calc v bit */
1000 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1001 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1002 tcg_gen_or_i64(t1, t1, t2);
1003 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1004 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1005 /* We produce an overflow on the host if the mul before was
1006 (0x80000000 * 0x80000000) << 1). If this is the
1007 case, we negate the ovf. */
1008 if (n == 1) {
1009 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1010 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1011 tcg_gen_and_tl(temp, temp, temp2);
1012 tcg_gen_shli_tl(temp, temp, 31);
1013 /* negate v bit, if special condition */
1014 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1015 }
1016 /* Calc SV bit */
1017 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1018 /* Calc AV/SAV bits */
1019 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1020 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1021 /* calc SAV */
1022 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1023 /* write back result */
1024 tcg_gen_mov_tl(ret, temp3);
1025 }
1026
1027 static inline void
1028 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1029 {
1030 TCGv temp = tcg_temp_new();
1031 TCGv temp2 = tcg_temp_new();
1032 if (n == 0) {
1033 tcg_gen_mul_tl(temp, arg2, arg3);
1034 } else { /* n is expected to be 1 */
1035 tcg_gen_mul_tl(temp, arg2, arg3);
1036 tcg_gen_shli_tl(temp, temp, 1);
1037 /* catch special case r1 = r2 = 0x8000 */
1038 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1039 tcg_gen_sub_tl(temp, temp, temp2);
1040 }
1041 gen_add_d(ret, arg1, temp);
1042 }
1043
1044 static inline void
1045 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1046 {
1047 TCGv temp = tcg_temp_new();
1048 TCGv temp2 = tcg_temp_new();
1049 if (n == 0) {
1050 tcg_gen_mul_tl(temp, arg2, arg3);
1051 } else { /* n is expected to be 1 */
1052 tcg_gen_mul_tl(temp, arg2, arg3);
1053 tcg_gen_shli_tl(temp, temp, 1);
1054 /* catch special case r1 = r2 = 0x8000 */
1055 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1056 tcg_gen_sub_tl(temp, temp, temp2);
1057 }
1058 gen_adds(ret, arg1, temp);
1059 }
1060
1061 static inline void
1062 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1063 TCGv arg3, uint32_t n)
1064 {
1065 TCGv temp = tcg_temp_new();
1066 TCGv temp2 = tcg_temp_new();
1067 TCGv_i64 t1 = tcg_temp_new_i64();
1068 TCGv_i64 t2 = tcg_temp_new_i64();
1069 TCGv_i64 t3 = tcg_temp_new_i64();
1070
1071 if (n == 0) {
1072 tcg_gen_mul_tl(temp, arg2, arg3);
1073 } else { /* n is expected to be 1 */
1074 tcg_gen_mul_tl(temp, arg2, arg3);
1075 tcg_gen_shli_tl(temp, temp, 1);
1076 /* catch special case r1 = r2 = 0x8000 */
1077 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1078 tcg_gen_sub_tl(temp, temp, temp2);
1079 }
1080 tcg_gen_ext_i32_i64(t2, temp);
1081 tcg_gen_shli_i64(t2, t2, 16);
1082 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1083 gen_add64_d(t3, t1, t2);
1084 /* write back result */
1085 tcg_gen_extr_i64_i32(rl, rh, t3);
1086 }
1087
1088 static inline void
1089 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1090 TCGv arg3, uint32_t n)
1091 {
1092 TCGv temp = tcg_temp_new();
1093 TCGv temp2 = tcg_temp_new();
1094 TCGv_i64 t1 = tcg_temp_new_i64();
1095 TCGv_i64 t2 = tcg_temp_new_i64();
1096
1097 if (n == 0) {
1098 tcg_gen_mul_tl(temp, arg2, arg3);
1099 } else { /* n is expected to be 1 */
1100 tcg_gen_mul_tl(temp, arg2, arg3);
1101 tcg_gen_shli_tl(temp, temp, 1);
1102 /* catch special case r1 = r2 = 0x8000 */
1103 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1104 tcg_gen_sub_tl(temp, temp, temp2);
1105 }
1106 tcg_gen_ext_i32_i64(t2, temp);
1107 tcg_gen_shli_i64(t2, t2, 16);
1108 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1109
1110 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1111 tcg_gen_extr_i64_i32(rl, rh, t1);
1112 }
1113
1114 static inline void
1115 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1116 TCGv arg3, uint32_t n)
1117 {
1118 TCGv_i64 t1 = tcg_temp_new_i64();
1119 TCGv_i64 t2 = tcg_temp_new_i64();
1120 TCGv_i64 t3 = tcg_temp_new_i64();
1121 TCGv_i64 t4 = tcg_temp_new_i64();
1122 TCGv temp, temp2;
1123
1124 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1125 tcg_gen_ext_i32_i64(t2, arg2);
1126 tcg_gen_ext_i32_i64(t3, arg3);
1127
1128 tcg_gen_mul_i64(t2, t2, t3);
1129 if (n != 0) {
1130 tcg_gen_shli_i64(t2, t2, 1);
1131 }
1132 tcg_gen_add_i64(t4, t1, t2);
1133 /* calc v bit */
1134 tcg_gen_xor_i64(t3, t4, t1);
1135 tcg_gen_xor_i64(t2, t1, t2);
1136 tcg_gen_andc_i64(t3, t3, t2);
1137 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1138 /* We produce an overflow on the host if the mul before was
1139 (0x80000000 * 0x80000000) << 1). If this is the
1140 case, we negate the ovf. */
1141 if (n == 1) {
1142 temp = tcg_temp_new();
1143 temp2 = tcg_temp_new();
1144 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1145 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1146 tcg_gen_and_tl(temp, temp, temp2);
1147 tcg_gen_shli_tl(temp, temp, 31);
1148 /* negate v bit, if special condition */
1149 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1150 }
1151 /* write back result */
1152 tcg_gen_extr_i64_i32(rl, rh, t4);
1153 /* Calc SV bit */
1154 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1155 /* Calc AV/SAV bits */
1156 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1157 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1158 /* calc SAV */
1159 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1160 }
1161
1162 static inline void
1163 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1164 uint32_t up_shift)
1165 {
1166 TCGv_i64 t1 = tcg_temp_new_i64();
1167 TCGv_i64 t2 = tcg_temp_new_i64();
1168 TCGv_i64 t3 = tcg_temp_new_i64();
1169
1170 tcg_gen_ext_i32_i64(t1, arg1);
1171 tcg_gen_ext_i32_i64(t2, arg2);
1172 tcg_gen_ext_i32_i64(t3, arg3);
1173
1174 tcg_gen_mul_i64(t2, t2, t3);
1175 tcg_gen_sari_i64(t2, t2, up_shift - n);
1176
1177 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1178 }
1179
1180 static inline void
1181 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1182 TCGv arg3, uint32_t n)
1183 {
1184 TCGv_i64 r1 = tcg_temp_new_i64();
1185 TCGv t_n = tcg_constant_i32(n);
1186
1187 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1188 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
1189 tcg_gen_extr_i64_i32(rl, rh, r1);
1190 }
1191
1192 /* ret = r2 - (r1 * r3); */
1193 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1194 {
1195 TCGv_i64 t1 = tcg_temp_new_i64();
1196 TCGv_i64 t2 = tcg_temp_new_i64();
1197 TCGv_i64 t3 = tcg_temp_new_i64();
1198
1199 tcg_gen_ext_i32_i64(t1, r1);
1200 tcg_gen_ext_i32_i64(t2, r2);
1201 tcg_gen_ext_i32_i64(t3, r3);
1202
1203 tcg_gen_mul_i64(t1, t1, t3);
1204 tcg_gen_sub_i64(t1, t2, t1);
1205
1206 tcg_gen_extrl_i64_i32(ret, t1);
1207 /* calc V
1208 t2 > 0x7fffffff */
1209 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1210 /* result < -0x80000000 */
1211 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1212 tcg_gen_or_i64(t2, t2, t3);
1213 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
1214 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1215
1216 /* Calc SV bit */
1217 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1218 /* Calc AV/SAV bits */
1219 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1220 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1221 /* calc SAV */
1222 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1223 }
1224
1225 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1226 {
1227 TCGv temp = tcg_const_i32(con);
1228 gen_msub32_d(ret, r1, r2, temp);
1229 }
1230
1231 static inline void
1232 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1233 TCGv r3)
1234 {
1235 TCGv t1 = tcg_temp_new();
1236 TCGv t2 = tcg_temp_new();
1237 TCGv t3 = tcg_temp_new();
1238 TCGv t4 = tcg_temp_new();
1239
1240 tcg_gen_muls2_tl(t1, t2, r1, r3);
1241 /* only the sub can overflow */
1242 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1243 /* calc V bit */
1244 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1245 tcg_gen_xor_tl(t1, r2_high, t2);
1246 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1247 /* Calc SV bit */
1248 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1249 /* Calc AV/SAV bits */
1250 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1251 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1252 /* calc SAV */
1253 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1254 /* write back the result */
1255 tcg_gen_mov_tl(ret_low, t3);
1256 tcg_gen_mov_tl(ret_high, t4);
1257 }
1258
1259 static inline void
1260 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1261 int32_t con)
1262 {
1263 TCGv temp = tcg_const_i32(con);
1264 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1265 }
1266
1267 static inline void
1268 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1269 TCGv r3)
1270 {
1271 TCGv_i64 t1 = tcg_temp_new_i64();
1272 TCGv_i64 t2 = tcg_temp_new_i64();
1273 TCGv_i64 t3 = tcg_temp_new_i64();
1274
1275 tcg_gen_extu_i32_i64(t1, r1);
1276 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1277 tcg_gen_extu_i32_i64(t3, r3);
1278
1279 tcg_gen_mul_i64(t1, t1, t3);
1280 tcg_gen_sub_i64(t3, t2, t1);
1281 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1282 /* calc V bit, only the sub can overflow, if t1 > t2 */
1283 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1284 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1285 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1286 /* Calc SV bit */
1287 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1288 /* Calc AV/SAV bits */
1289 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1290 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1291 /* calc SAV */
1292 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1293 }
1294
1295 static inline void
1296 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1297 int32_t con)
1298 {
1299 TCGv temp = tcg_const_i32(con);
1300 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1301 }
1302
1303 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1304 {
1305 TCGv temp = tcg_const_i32(r2);
1306 gen_add_d(ret, r1, temp);
1307 }
1308
1309 /* calculate the carry bit too */
1310 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1311 {
1312 TCGv t0 = tcg_temp_new_i32();
1313 TCGv result = tcg_temp_new_i32();
1314
1315 tcg_gen_movi_tl(t0, 0);
1316 /* Addition and set C/V/SV bits */
1317 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1318 /* calc V bit */
1319 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1320 tcg_gen_xor_tl(t0, r1, r2);
1321 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1322 /* Calc SV bit */
1323 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1324 /* Calc AV/SAV bits */
1325 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1326 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1327 /* calc SAV */
1328 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1329 /* write back result */
1330 tcg_gen_mov_tl(ret, result);
1331 }
1332
1333 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1334 {
1335 TCGv temp = tcg_const_i32(con);
1336 gen_add_CC(ret, r1, temp);
1337 }
1338
1339 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1340 {
1341 TCGv carry = tcg_temp_new_i32();
1342 TCGv t0 = tcg_temp_new_i32();
1343 TCGv result = tcg_temp_new_i32();
1344
1345 tcg_gen_movi_tl(t0, 0);
1346 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1347 /* Addition, carry and set C/V/SV bits */
1348 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1349 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1350 /* calc V bit */
1351 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1352 tcg_gen_xor_tl(t0, r1, r2);
1353 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1354 /* Calc SV bit */
1355 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1356 /* Calc AV/SAV bits */
1357 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1358 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1359 /* calc SAV */
1360 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1361 /* write back result */
1362 tcg_gen_mov_tl(ret, result);
1363 }
1364
1365 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1366 {
1367 TCGv temp = tcg_const_i32(con);
1368 gen_addc_CC(ret, r1, temp);
1369 }
1370
1371 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1372 TCGv r4)
1373 {
1374 TCGv temp = tcg_temp_new();
1375 TCGv temp2 = tcg_temp_new();
1376 TCGv result = tcg_temp_new();
1377 TCGv mask = tcg_temp_new();
1378 TCGv t0 = tcg_const_i32(0);
1379
1380 /* create mask for sticky bits */
1381 tcg_gen_setcond_tl(cond, mask, r4, t0);
1382 tcg_gen_shli_tl(mask, mask, 31);
1383
1384 tcg_gen_add_tl(result, r1, r2);
1385 /* Calc PSW_V */
1386 tcg_gen_xor_tl(temp, result, r1);
1387 tcg_gen_xor_tl(temp2, r1, r2);
1388 tcg_gen_andc_tl(temp, temp, temp2);
1389 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1390 /* Set PSW_SV */
1391 tcg_gen_and_tl(temp, temp, mask);
1392 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1393 /* calc AV bit */
1394 tcg_gen_add_tl(temp, result, result);
1395 tcg_gen_xor_tl(temp, temp, result);
1396 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1397 /* calc SAV bit */
1398 tcg_gen_and_tl(temp, temp, mask);
1399 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1400 /* write back result */
1401 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1402 }
1403
1404 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1405 TCGv r3, TCGv r4)
1406 {
1407 TCGv temp = tcg_const_i32(r2);
1408 gen_cond_add(cond, r1, temp, r3, r4);
1409 }
1410
1411 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1412 {
1413 TCGv temp = tcg_temp_new_i32();
1414 TCGv result = tcg_temp_new_i32();
1415
1416 tcg_gen_sub_tl(result, r1, r2);
1417 /* calc V bit */
1418 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1419 tcg_gen_xor_tl(temp, r1, r2);
1420 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1421 /* calc SV bit */
1422 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1423 /* Calc AV bit */
1424 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1425 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1426 /* calc SAV bit */
1427 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1428 /* write back result */
1429 tcg_gen_mov_tl(ret, result);
1430 }
1431
1432 static inline void
1433 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1434 {
1435 TCGv temp = tcg_temp_new();
1436 TCGv_i64 t0 = tcg_temp_new_i64();
1437 TCGv_i64 t1 = tcg_temp_new_i64();
1438 TCGv_i64 result = tcg_temp_new_i64();
1439
1440 tcg_gen_sub_i64(result, r1, r2);
1441 /* calc v bit */
1442 tcg_gen_xor_i64(t1, result, r1);
1443 tcg_gen_xor_i64(t0, r1, r2);
1444 tcg_gen_and_i64(t1, t1, t0);
1445 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
1446 /* calc SV bit */
1447 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1448 /* calc AV/SAV bits */
1449 tcg_gen_extrh_i64_i32(temp, result);
1450 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1451 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1452 /* calc SAV */
1453 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1454 /* write back result */
1455 tcg_gen_mov_i64(ret, result);
1456 }
1457
1458 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1459 {
1460 TCGv result = tcg_temp_new();
1461 TCGv temp = tcg_temp_new();
1462
1463 tcg_gen_sub_tl(result, r1, r2);
1464 /* calc C bit */
1465 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1466 /* calc V bit */
1467 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1468 tcg_gen_xor_tl(temp, r1, r2);
1469 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1470 /* calc SV bit */
1471 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1472 /* Calc AV bit */
1473 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1474 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1475 /* calc SAV bit */
1476 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1477 /* write back result */
1478 tcg_gen_mov_tl(ret, result);
1479 }
1480
1481 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1482 {
1483 TCGv temp = tcg_temp_new();
1484 tcg_gen_not_tl(temp, r2);
1485 gen_addc_CC(ret, r1, temp);
1486 }
1487
1488 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1489 TCGv r4)
1490 {
1491 TCGv temp = tcg_temp_new();
1492 TCGv temp2 = tcg_temp_new();
1493 TCGv result = tcg_temp_new();
1494 TCGv mask = tcg_temp_new();
1495 TCGv t0 = tcg_const_i32(0);
1496
1497 /* create mask for sticky bits */
1498 tcg_gen_setcond_tl(cond, mask, r4, t0);
1499 tcg_gen_shli_tl(mask, mask, 31);
1500
1501 tcg_gen_sub_tl(result, r1, r2);
1502 /* Calc PSW_V */
1503 tcg_gen_xor_tl(temp, result, r1);
1504 tcg_gen_xor_tl(temp2, r1, r2);
1505 tcg_gen_and_tl(temp, temp, temp2);
1506 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1507 /* Set PSW_SV */
1508 tcg_gen_and_tl(temp, temp, mask);
1509 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1510 /* calc AV bit */
1511 tcg_gen_add_tl(temp, result, result);
1512 tcg_gen_xor_tl(temp, temp, result);
1513 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1514 /* calc SAV bit */
1515 tcg_gen_and_tl(temp, temp, mask);
1516 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1517 /* write back result */
1518 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1519 }
1520
1521 static inline void
1522 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1523 TCGv r3, uint32_t n, uint32_t mode)
1524 {
1525 TCGv t_n = tcg_constant_i32(n);
1526 TCGv temp = tcg_temp_new();
1527 TCGv temp2 = tcg_temp_new();
1528 TCGv_i64 temp64 = tcg_temp_new_i64();
1529 switch (mode) {
1530 case MODE_LL:
1531 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1532 break;
1533 case MODE_LU:
1534 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1535 break;
1536 case MODE_UL:
1537 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1538 break;
1539 case MODE_UU:
1540 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1541 break;
1542 }
1543 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1544 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1545 tcg_gen_sub_tl, tcg_gen_sub_tl);
1546 }
1547
1548 static inline void
1549 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1550 TCGv r3, uint32_t n, uint32_t mode)
1551 {
1552 TCGv t_n = tcg_constant_i32(n);
1553 TCGv temp = tcg_temp_new();
1554 TCGv temp2 = tcg_temp_new();
1555 TCGv temp3 = tcg_temp_new();
1556 TCGv_i64 temp64 = tcg_temp_new_i64();
1557
1558 switch (mode) {
1559 case MODE_LL:
1560 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1561 break;
1562 case MODE_LU:
1563 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1564 break;
1565 case MODE_UL:
1566 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1567 break;
1568 case MODE_UU:
1569 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1570 break;
1571 }
1572 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1573 gen_subs(ret_low, r1_low, temp);
1574 tcg_gen_mov_tl(temp, cpu_PSW_V);
1575 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1576 gen_subs(ret_high, r1_high, temp2);
1577 /* combine v bits */
1578 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1579 /* combine av bits */
1580 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1581 }
1582
1583 static inline void
1584 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1585 TCGv r3, uint32_t n, uint32_t mode)
1586 {
1587 TCGv t_n = tcg_constant_i32(n);
1588 TCGv_i64 temp64 = tcg_temp_new_i64();
1589 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1590 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1591 switch (mode) {
1592 case MODE_LL:
1593 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
1594 break;
1595 case MODE_LU:
1596 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
1597 break;
1598 case MODE_UL:
1599 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
1600 break;
1601 case MODE_UU:
1602 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
1603 break;
1604 }
1605 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1606 gen_sub64_d(temp64_3, temp64_2, temp64);
1607 /* write back result */
1608 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1609 }
1610
1611 static inline void
1612 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1613 TCGv r3, uint32_t n, uint32_t mode)
1614 {
1615 TCGv t_n = tcg_constant_i32(n);
1616 TCGv_i64 temp64 = tcg_temp_new_i64();
1617 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1618 switch (mode) {
1619 case MODE_LL:
1620 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
1621 break;
1622 case MODE_LU:
1623 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
1624 break;
1625 case MODE_UL:
1626 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
1627 break;
1628 case MODE_UU:
1629 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
1630 break;
1631 }
1632 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1633 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1634 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1635 }
1636
1637 static inline void
1638 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1639 uint32_t mode)
1640 {
1641 TCGv t_n = tcg_constant_i32(n);
1642 TCGv_i64 temp64 = tcg_temp_new_i64();
1643 switch (mode) {
1644 case MODE_LL:
1645 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1646 break;
1647 case MODE_LU:
1648 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1649 break;
1650 case MODE_UL:
1651 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1652 break;
1653 case MODE_UU:
1654 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1655 break;
1656 }
1657 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1658 }
1659
1660 static inline void
1661 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1662 {
1663 TCGv temp = tcg_temp_new();
1664 TCGv temp2 = tcg_temp_new();
1665
1666 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1667 tcg_gen_shli_tl(temp, r1, 16);
1668 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1669 }
1670
1671 static inline void
1672 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1673 uint32_t n, uint32_t mode)
1674 {
1675 TCGv t_n = tcg_constant_i32(n);
1676 TCGv_i64 temp64 = tcg_temp_new_i64();
1677 switch (mode) {
1678 case MODE_LL:
1679 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1680 break;
1681 case MODE_LU:
1682 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1683 break;
1684 case MODE_UL:
1685 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1686 break;
1687 case MODE_UU:
1688 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1689 break;
1690 }
1691 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1692 }
1693
1694 static inline void
1695 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1696 {
1697 TCGv temp = tcg_temp_new();
1698 TCGv temp2 = tcg_temp_new();
1699
1700 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1701 tcg_gen_shli_tl(temp, r1, 16);
1702 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1703 }
1704
1705 static inline void
1706 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1707 {
1708 TCGv temp = tcg_const_i32(n);
1709 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1710 }
1711
1712 static inline void
1713 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1714 {
1715 TCGv temp = tcg_const_i32(n);
1716 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1717 }
1718
1719 static inline void
1720 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1721 uint32_t up_shift)
1722 {
1723 TCGv temp3 = tcg_temp_new();
1724 TCGv_i64 t1 = tcg_temp_new_i64();
1725 TCGv_i64 t2 = tcg_temp_new_i64();
1726 TCGv_i64 t3 = tcg_temp_new_i64();
1727 TCGv_i64 t4 = tcg_temp_new_i64();
1728
1729 tcg_gen_ext_i32_i64(t2, arg2);
1730 tcg_gen_ext_i32_i64(t3, arg3);
1731
1732 tcg_gen_mul_i64(t2, t2, t3);
1733
1734 tcg_gen_ext_i32_i64(t1, arg1);
1735 /* if we shift part of the fraction out, we need to round up */
1736 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1737 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1738 tcg_gen_sari_i64(t2, t2, up_shift - n);
1739 tcg_gen_add_i64(t2, t2, t4);
1740
1741 tcg_gen_sub_i64(t3, t1, t2);
1742 tcg_gen_extrl_i64_i32(temp3, t3);
1743 /* calc v bit */
1744 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1745 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1746 tcg_gen_or_i64(t1, t1, t2);
1747 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1748 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1749 /* Calc SV bit */
1750 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1751 /* Calc AV/SAV bits */
1752 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1753 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1754 /* calc SAV */
1755 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1756 /* write back result */
1757 tcg_gen_mov_tl(ret, temp3);
1758 }
1759
1760 static inline void
1761 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1762 {
1763 TCGv temp = tcg_temp_new();
1764 TCGv temp2 = tcg_temp_new();
1765 if (n == 0) {
1766 tcg_gen_mul_tl(temp, arg2, arg3);
1767 } else { /* n is expected to be 1 */
1768 tcg_gen_mul_tl(temp, arg2, arg3);
1769 tcg_gen_shli_tl(temp, temp, 1);
1770 /* catch special case r1 = r2 = 0x8000 */
1771 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1772 tcg_gen_sub_tl(temp, temp, temp2);
1773 }
1774 gen_sub_d(ret, arg1, temp);
1775 }
1776
1777 static inline void
1778 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1779 {
1780 TCGv temp = tcg_temp_new();
1781 TCGv temp2 = tcg_temp_new();
1782 if (n == 0) {
1783 tcg_gen_mul_tl(temp, arg2, arg3);
1784 } else { /* n is expected to be 1 */
1785 tcg_gen_mul_tl(temp, arg2, arg3);
1786 tcg_gen_shli_tl(temp, temp, 1);
1787 /* catch special case r1 = r2 = 0x8000 */
1788 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1789 tcg_gen_sub_tl(temp, temp, temp2);
1790 }
1791 gen_subs(ret, arg1, temp);
1792 }
1793
1794 static inline void
1795 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1796 TCGv arg3, uint32_t n)
1797 {
1798 TCGv temp = tcg_temp_new();
1799 TCGv temp2 = tcg_temp_new();
1800 TCGv_i64 t1 = tcg_temp_new_i64();
1801 TCGv_i64 t2 = tcg_temp_new_i64();
1802 TCGv_i64 t3 = tcg_temp_new_i64();
1803
1804 if (n == 0) {
1805 tcg_gen_mul_tl(temp, arg2, arg3);
1806 } else { /* n is expected to be 1 */
1807 tcg_gen_mul_tl(temp, arg2, arg3);
1808 tcg_gen_shli_tl(temp, temp, 1);
1809 /* catch special case r1 = r2 = 0x8000 */
1810 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1811 tcg_gen_sub_tl(temp, temp, temp2);
1812 }
1813 tcg_gen_ext_i32_i64(t2, temp);
1814 tcg_gen_shli_i64(t2, t2, 16);
1815 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1816 gen_sub64_d(t3, t1, t2);
1817 /* write back result */
1818 tcg_gen_extr_i64_i32(rl, rh, t3);
1819 }
1820
1821 static inline void
1822 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1823 TCGv arg3, uint32_t n)
1824 {
1825 TCGv temp = tcg_temp_new();
1826 TCGv temp2 = tcg_temp_new();
1827 TCGv_i64 t1 = tcg_temp_new_i64();
1828 TCGv_i64 t2 = tcg_temp_new_i64();
1829
1830 if (n == 0) {
1831 tcg_gen_mul_tl(temp, arg2, arg3);
1832 } else { /* n is expected to be 1 */
1833 tcg_gen_mul_tl(temp, arg2, arg3);
1834 tcg_gen_shli_tl(temp, temp, 1);
1835 /* catch special case r1 = r2 = 0x8000 */
1836 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1837 tcg_gen_sub_tl(temp, temp, temp2);
1838 }
1839 tcg_gen_ext_i32_i64(t2, temp);
1840 tcg_gen_shli_i64(t2, t2, 16);
1841 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1842
1843 gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
1844 tcg_gen_extr_i64_i32(rl, rh, t1);
1845 }
1846
1847 static inline void
1848 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1849 TCGv arg3, uint32_t n)
1850 {
1851 TCGv_i64 t1 = tcg_temp_new_i64();
1852 TCGv_i64 t2 = tcg_temp_new_i64();
1853 TCGv_i64 t3 = tcg_temp_new_i64();
1854 TCGv_i64 t4 = tcg_temp_new_i64();
1855 TCGv temp, temp2;
1856
1857 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1858 tcg_gen_ext_i32_i64(t2, arg2);
1859 tcg_gen_ext_i32_i64(t3, arg3);
1860
1861 tcg_gen_mul_i64(t2, t2, t3);
1862 if (n != 0) {
1863 tcg_gen_shli_i64(t2, t2, 1);
1864 }
1865 tcg_gen_sub_i64(t4, t1, t2);
1866 /* calc v bit */
1867 tcg_gen_xor_i64(t3, t4, t1);
1868 tcg_gen_xor_i64(t2, t1, t2);
1869 tcg_gen_and_i64(t3, t3, t2);
1870 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1871 /* We produce an overflow on the host if the mul before was
1872 (0x80000000 * 0x80000000) << 1). If this is the
1873 case, we negate the ovf. */
1874 if (n == 1) {
1875 temp = tcg_temp_new();
1876 temp2 = tcg_temp_new();
1877 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1878 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1879 tcg_gen_and_tl(temp, temp, temp2);
1880 tcg_gen_shli_tl(temp, temp, 31);
1881 /* negate v bit, if special condition */
1882 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1883 }
1884 /* write back result */
1885 tcg_gen_extr_i64_i32(rl, rh, t4);
1886 /* Calc SV bit */
1887 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1888 /* Calc AV/SAV bits */
1889 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1890 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1891 /* calc SAV */
1892 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1893 }
1894
1895 static inline void
1896 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1897 uint32_t up_shift)
1898 {
1899 TCGv_i64 t1 = tcg_temp_new_i64();
1900 TCGv_i64 t2 = tcg_temp_new_i64();
1901 TCGv_i64 t3 = tcg_temp_new_i64();
1902 TCGv_i64 t4 = tcg_temp_new_i64();
1903
1904 tcg_gen_ext_i32_i64(t1, arg1);
1905 tcg_gen_ext_i32_i64(t2, arg2);
1906 tcg_gen_ext_i32_i64(t3, arg3);
1907
1908 tcg_gen_mul_i64(t2, t2, t3);
1909 /* if we shift part of the fraction out, we need to round up */
1910 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1911 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1912 tcg_gen_sari_i64(t3, t2, up_shift - n);
1913 tcg_gen_add_i64(t3, t3, t4);
1914
1915 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
1916 }
1917
1918 static inline void
1919 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1920 TCGv arg3, uint32_t n)
1921 {
1922 TCGv_i64 r1 = tcg_temp_new_i64();
1923 TCGv t_n = tcg_constant_i32(n);
1924
1925 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1926 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
1927 tcg_gen_extr_i64_i32(rl, rh, r1);
1928 }
1929
1930 static inline void
1931 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1932 TCGv r3, uint32_t n, uint32_t mode)
1933 {
1934 TCGv t_n = tcg_constant_i32(n);
1935 TCGv temp = tcg_temp_new();
1936 TCGv temp2 = tcg_temp_new();
1937 TCGv_i64 temp64 = tcg_temp_new_i64();
1938 switch (mode) {
1939 case MODE_LL:
1940 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1941 break;
1942 case MODE_LU:
1943 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1944 break;
1945 case MODE_UL:
1946 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1947 break;
1948 case MODE_UU:
1949 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1950 break;
1951 }
1952 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1953 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1954 tcg_gen_add_tl, tcg_gen_sub_tl);
1955 }
1956
1957 static inline void
1958 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1959 TCGv r3, uint32_t n, uint32_t mode)
1960 {
1961 TCGv t_n = tcg_constant_i32(n);
1962 TCGv_i64 temp64 = tcg_temp_new_i64();
1963 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1964 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1965 switch (mode) {
1966 case MODE_LL:
1967 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1968 break;
1969 case MODE_LU:
1970 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1971 break;
1972 case MODE_UL:
1973 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1974 break;
1975 case MODE_UU:
1976 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1977 break;
1978 }
1979 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
1980 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
1981 tcg_gen_ext32s_i64(temp64, temp64); /* low */
1982 tcg_gen_sub_i64(temp64, temp64_2, temp64);
1983 tcg_gen_shli_i64(temp64, temp64, 16);
1984
1985 gen_sub64_d(temp64_2, temp64_3, temp64);
1986 /* write back result */
1987 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
1988 }
1989
1990 static inline void
1991 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1992 {
1993 TCGv t_n = tcg_constant_i32(n);
1994 TCGv temp = tcg_temp_new();
1995 TCGv temp2 = tcg_temp_new();
1996 TCGv_i64 temp64 = tcg_temp_new_i64();
1997 switch (mode) {
1998 case MODE_LL:
1999 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2000 break;
2001 case MODE_LU:
2002 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2003 break;
2004 case MODE_UL:
2005 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2006 break;
2007 case MODE_UU:
2008 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2009 break;
2010 }
2011 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2012 tcg_gen_shli_tl(temp, r1, 16);
2013 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2014 }
2015
2016 static inline void
2017 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2018 TCGv r3, uint32_t n, uint32_t mode)
2019 {
2020 TCGv t_n = tcg_constant_i32(n);
2021 TCGv temp = tcg_temp_new();
2022 TCGv temp2 = tcg_temp_new();
2023 TCGv temp3 = tcg_temp_new();
2024 TCGv_i64 temp64 = tcg_temp_new_i64();
2025
2026 switch (mode) {
2027 case MODE_LL:
2028 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2029 break;
2030 case MODE_LU:
2031 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2032 break;
2033 case MODE_UL:
2034 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2035 break;
2036 case MODE_UU:
2037 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2038 break;
2039 }
2040 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2041 gen_adds(ret_low, r1_low, temp);
2042 tcg_gen_mov_tl(temp, cpu_PSW_V);
2043 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2044 gen_subs(ret_high, r1_high, temp2);
2045 /* combine v bits */
2046 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2047 /* combine av bits */
2048 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2049 }
2050
2051 static inline void
2052 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2053 TCGv r3, uint32_t n, uint32_t mode)
2054 {
2055 TCGv t_n = tcg_constant_i32(n);
2056 TCGv_i64 temp64 = tcg_temp_new_i64();
2057 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2058
2059 switch (mode) {
2060 case MODE_LL:
2061 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2062 break;
2063 case MODE_LU:
2064 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2065 break;
2066 case MODE_UL:
2067 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2068 break;
2069 case MODE_UU:
2070 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2071 break;
2072 }
2073 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2074 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2075 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2076 tcg_gen_shli_i64(temp64, temp64, 16);
2077 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2078
2079 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2080 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2081 }
2082
2083 static inline void
2084 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2085 {
2086 TCGv t_n = tcg_constant_i32(n);
2087 TCGv temp = tcg_temp_new();
2088 TCGv temp2 = tcg_temp_new();
2089 TCGv_i64 temp64 = tcg_temp_new_i64();
2090 switch (mode) {
2091 case MODE_LL:
2092 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2093 break;
2094 case MODE_LU:
2095 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2096 break;
2097 case MODE_UL:
2098 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2099 break;
2100 case MODE_UU:
2101 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2102 break;
2103 }
2104 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2105 tcg_gen_shli_tl(temp, r1, 16);
2106 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2107 }
2108
2109 static inline void gen_abs(TCGv ret, TCGv r1)
2110 {
2111 tcg_gen_abs_tl(ret, r1);
2112 /* overflow can only happen, if r1 = 0x80000000 */
2113 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2114 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2115 /* calc SV bit */
2116 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2117 /* Calc AV bit */
2118 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2119 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2120 /* calc SAV bit */
2121 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2122 }
2123
2124 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2125 {
2126 TCGv temp = tcg_temp_new_i32();
2127 TCGv result = tcg_temp_new_i32();
2128
2129 tcg_gen_sub_tl(result, r1, r2);
2130 tcg_gen_sub_tl(temp, r2, r1);
2131 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2132
2133 /* calc V bit */
2134 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2135 tcg_gen_xor_tl(temp, result, r2);
2136 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2137 tcg_gen_xor_tl(temp, r1, r2);
2138 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2139 /* calc SV bit */
2140 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2141 /* Calc AV bit */
2142 tcg_gen_add_tl(cpu_PSW_AV, result, result);
2143 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2144 /* calc SAV bit */
2145 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2146 /* write back result */
2147 tcg_gen_mov_tl(ret, result);
2148 }
2149
2150 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2151 {
2152 TCGv temp = tcg_const_i32(con);
2153 gen_absdif(ret, r1, temp);
2154 }
2155
2156 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2157 {
2158 TCGv temp = tcg_const_i32(con);
2159 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2160 }
2161
2162 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2163 {
2164 TCGv high = tcg_temp_new();
2165 TCGv low = tcg_temp_new();
2166
2167 tcg_gen_muls2_tl(low, high, r1, r2);
2168 tcg_gen_mov_tl(ret, low);
2169 /* calc V bit */
2170 tcg_gen_sari_tl(low, low, 31);
2171 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2172 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2173 /* calc SV bit */
2174 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2175 /* Calc AV bit */
2176 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2177 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2178 /* calc SAV bit */
2179 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2180 }
2181
2182 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2183 {
2184 TCGv temp = tcg_const_i32(con);
2185 gen_mul_i32s(ret, r1, temp);
2186 }
2187
2188 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2189 {
2190 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2191 /* clear V bit */
2192 tcg_gen_movi_tl(cpu_PSW_V, 0);
2193 /* calc SV bit */
2194 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2195 /* Calc AV bit */
2196 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2197 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2198 /* calc SAV bit */
2199 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2200 }
2201
2202 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2203 int32_t con)
2204 {
2205 TCGv temp = tcg_const_i32(con);
2206 gen_mul_i64s(ret_low, ret_high, r1, temp);
2207 }
2208
2209 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2210 {
2211 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2212 /* clear V bit */
2213 tcg_gen_movi_tl(cpu_PSW_V, 0);
2214 /* calc SV bit */
2215 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2216 /* Calc AV bit */
2217 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2218 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2219 /* calc SAV bit */
2220 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2221 }
2222
2223 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2224 int32_t con)
2225 {
2226 TCGv temp = tcg_const_i32(con);
2227 gen_mul_i64u(ret_low, ret_high, r1, temp);
2228 }
2229
2230 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2231 {
2232 TCGv temp = tcg_const_i32(con);
2233 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2234 }
2235
2236 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2237 {
2238 TCGv temp = tcg_const_i32(con);
2239 gen_helper_mul_suov(ret, cpu_env, r1, temp);
2240 }
2241 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2242 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2243 {
2244 TCGv temp = tcg_const_i32(con);
2245 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2246 }
2247
2248 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2249 {
2250 TCGv temp = tcg_const_i32(con);
2251 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2252 }
2253
2254 static void
2255 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2256 {
2257 TCGv_i64 temp_64 = tcg_temp_new_i64();
2258 TCGv_i64 temp2_64 = tcg_temp_new_i64();
2259
2260 if (n == 0) {
2261 if (up_shift == 32) {
2262 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2263 } else if (up_shift == 16) {
2264 tcg_gen_ext_i32_i64(temp_64, arg1);
2265 tcg_gen_ext_i32_i64(temp2_64, arg2);
2266
2267 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2268 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2269 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2270 } else {
2271 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2272 }
2273 /* reset v bit */
2274 tcg_gen_movi_tl(cpu_PSW_V, 0);
2275 } else { /* n is expected to be 1 */
2276 tcg_gen_ext_i32_i64(temp_64, arg1);
2277 tcg_gen_ext_i32_i64(temp2_64, arg2);
2278
2279 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2280
2281 if (up_shift == 0) {
2282 tcg_gen_shli_i64(temp_64, temp_64, 1);
2283 } else {
2284 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2285 }
2286 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2287 /* overflow only occurs if r1 = r2 = 0x8000 */
2288 if (up_shift == 0) {/* result is 64 bit */
2289 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2290 0x80000000);
2291 } else { /* result is 32 bit */
2292 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2293 0x80000000);
2294 }
2295 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2296 /* calc sv overflow bit */
2297 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2298 }
2299 /* calc av overflow bit */
2300 if (up_shift == 0) {
2301 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2302 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2303 } else {
2304 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2305 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2306 }
2307 /* calc sav overflow bit */
2308 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2309 }
2310
2311 static void
2312 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2313 {
2314 TCGv temp = tcg_temp_new();
2315 if (n == 0) {
2316 tcg_gen_mul_tl(ret, arg1, arg2);
2317 } else { /* n is expected to be 1 */
2318 tcg_gen_mul_tl(ret, arg1, arg2);
2319 tcg_gen_shli_tl(ret, ret, 1);
2320 /* catch special case r1 = r2 = 0x8000 */
2321 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2322 tcg_gen_sub_tl(ret, ret, temp);
2323 }
2324 /* reset v bit */
2325 tcg_gen_movi_tl(cpu_PSW_V, 0);
2326 /* calc av overflow bit */
2327 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2328 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2329 /* calc sav overflow bit */
2330 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2331 }
2332
2333 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2334 {
2335 TCGv temp = tcg_temp_new();
2336 if (n == 0) {
2337 tcg_gen_mul_tl(ret, arg1, arg2);
2338 tcg_gen_addi_tl(ret, ret, 0x8000);
2339 } else {
2340 tcg_gen_mul_tl(ret, arg1, arg2);
2341 tcg_gen_shli_tl(ret, ret, 1);
2342 tcg_gen_addi_tl(ret, ret, 0x8000);
2343 /* catch special case r1 = r2 = 0x8000 */
2344 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2345 tcg_gen_muli_tl(temp, temp, 0x8001);
2346 tcg_gen_sub_tl(ret, ret, temp);
2347 }
2348 /* reset v bit */
2349 tcg_gen_movi_tl(cpu_PSW_V, 0);
2350 /* calc av overflow bit */
2351 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2352 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2353 /* calc sav overflow bit */
2354 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2355 /* cut halfword off */
2356 tcg_gen_andi_tl(ret, ret, 0xffff0000);
2357 }
2358
2359 static inline void
2360 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2361 TCGv r3)
2362 {
2363 TCGv_i64 temp64 = tcg_temp_new_i64();
2364 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2365 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2366 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2367 }
2368
2369 static inline void
2370 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2371 int32_t con)
2372 {
2373 TCGv temp = tcg_const_i32(con);
2374 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2375 }
2376
2377 static inline void
2378 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2379 TCGv r3)
2380 {
2381 TCGv_i64 temp64 = tcg_temp_new_i64();
2382 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2383 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2384 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2385 }
2386
2387 static inline void
2388 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2389 int32_t con)
2390 {
2391 TCGv temp = tcg_const_i32(con);
2392 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2393 }
2394
2395 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2396 {
2397 TCGv temp = tcg_const_i32(con);
2398 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2399 }
2400
2401 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2402 {
2403 TCGv temp = tcg_const_i32(con);
2404 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2405 }
2406
2407 static inline void
2408 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2409 TCGv r3)
2410 {
2411 TCGv_i64 temp64 = tcg_temp_new_i64();
2412 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2413 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2414 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2415 }
2416
2417 static inline void
2418 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2419 int32_t con)
2420 {
2421 TCGv temp = tcg_const_i32(con);
2422 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2423 }
2424
2425 static inline void
2426 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2427 TCGv r3)
2428 {
2429 TCGv_i64 temp64 = tcg_temp_new_i64();
2430 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2431 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2432 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2433 }
2434
2435 static inline void
2436 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2437 int32_t con)
2438 {
2439 TCGv temp = tcg_const_i32(con);
2440 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2441 }
2442
2443 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2444 {
2445 TCGv sat_neg = tcg_const_i32(low);
2446 TCGv temp = tcg_const_i32(up);
2447
2448 /* sat_neg = (arg < low ) ? low : arg; */
2449 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
2450
2451 /* ret = (sat_neg > up ) ? up : sat_neg; */
2452 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
2453 }
2454
2455 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2456 {
2457 TCGv temp = tcg_const_i32(up);
2458 /* sat_neg = (arg > up ) ? up : arg; */
2459 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
2460 }
2461
2462 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2463 {
2464 if (shift_count == -32) {
2465 tcg_gen_movi_tl(ret, 0);
2466 } else if (shift_count >= 0) {
2467 tcg_gen_shli_tl(ret, r1, shift_count);
2468 } else {
2469 tcg_gen_shri_tl(ret, r1, -shift_count);
2470 }
2471 }
2472
2473 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2474 {
2475 TCGv temp_low, temp_high;
2476
2477 if (shiftcount == -16) {
2478 tcg_gen_movi_tl(ret, 0);
2479 } else {
2480 temp_high = tcg_temp_new();
2481 temp_low = tcg_temp_new();
2482
2483 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2484 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2485 gen_shi(temp_low, temp_low, shiftcount);
2486 gen_shi(ret, temp_high, shiftcount);
2487 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2488 }
2489 }
2490
2491 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2492 {
2493 uint32_t msk, msk_start;
2494 TCGv temp = tcg_temp_new();
2495 TCGv temp2 = tcg_temp_new();
2496
2497 if (shift_count == 0) {
2498 /* Clear PSW.C and PSW.V */
2499 tcg_gen_movi_tl(cpu_PSW_C, 0);
2500 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2501 tcg_gen_mov_tl(ret, r1);
2502 } else if (shift_count == -32) {
2503 /* set PSW.C */
2504 tcg_gen_mov_tl(cpu_PSW_C, r1);
2505 /* fill ret completely with sign bit */
2506 tcg_gen_sari_tl(ret, r1, 31);
2507 /* clear PSW.V */
2508 tcg_gen_movi_tl(cpu_PSW_V, 0);
2509 } else if (shift_count > 0) {
2510 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
2511 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
2512
2513 /* calc carry */
2514 msk_start = 32 - shift_count;
2515 msk = ((1 << shift_count) - 1) << msk_start;
2516 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2517 /* calc v/sv bits */
2518 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2519 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2520 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2521 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2522 /* calc sv */
2523 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2524 /* do shift */
2525 tcg_gen_shli_tl(ret, r1, shift_count);
2526 } else {
2527 /* clear PSW.V */
2528 tcg_gen_movi_tl(cpu_PSW_V, 0);
2529 /* calc carry */
2530 msk = (1 << -shift_count) - 1;
2531 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2532 /* do shift */
2533 tcg_gen_sari_tl(ret, r1, -shift_count);
2534 }
2535 /* calc av overflow bit */
2536 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2537 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2538 /* calc sav overflow bit */
2539 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2540 }
2541
2542 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2543 {
2544 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2545 }
2546
2547 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2548 {
2549 TCGv temp = tcg_const_i32(con);
2550 gen_shas(ret, r1, temp);
2551 }
2552
2553 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2554 {
2555 TCGv low, high;
2556
2557 if (shift_count == 0) {
2558 tcg_gen_mov_tl(ret, r1);
2559 } else if (shift_count > 0) {
2560 low = tcg_temp_new();
2561 high = tcg_temp_new();
2562
2563 tcg_gen_andi_tl(high, r1, 0xffff0000);
2564 tcg_gen_shli_tl(low, r1, shift_count);
2565 tcg_gen_shli_tl(ret, high, shift_count);
2566 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2567 } else {
2568 low = tcg_temp_new();
2569 high = tcg_temp_new();
2570
2571 tcg_gen_ext16s_tl(low, r1);
2572 tcg_gen_sari_tl(low, low, -shift_count);
2573 tcg_gen_sari_tl(ret, r1, -shift_count);
2574 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2575 }
2576 }
2577
2578 /* ret = {ret[30:0], (r1 cond r2)}; */
2579 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2580 {
2581 TCGv temp = tcg_temp_new();
2582 TCGv temp2 = tcg_temp_new();
2583
2584 tcg_gen_shli_tl(temp, ret, 1);
2585 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2586 tcg_gen_or_tl(ret, temp, temp2);
2587 }
2588
2589 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2590 {
2591 TCGv temp = tcg_const_i32(con);
2592 gen_sh_cond(cond, ret, r1, temp);
2593 }
2594
2595 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2596 {
2597 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2598 }
2599
2600 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2601 {
2602 TCGv temp = tcg_const_i32(con);
2603 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2604 }
2605
2606 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2607 {
2608 TCGv temp = tcg_const_i32(con);
2609 gen_helper_add_suov(ret, cpu_env, r1, temp);
2610 }
2611
2612 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2613 {
2614 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2615 }
2616
2617 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2618 {
2619 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2620 }
2621
2622 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
2623 int pos1, int pos2,
2624 void(*op1)(TCGv, TCGv, TCGv),
2625 void(*op2)(TCGv, TCGv, TCGv))
2626 {
2627 TCGv temp1, temp2;
2628
2629 temp1 = tcg_temp_new();
2630 temp2 = tcg_temp_new();
2631
2632 tcg_gen_shri_tl(temp2, r2, pos2);
2633 tcg_gen_shri_tl(temp1, r1, pos1);
2634
2635 (*op1)(temp1, temp1, temp2);
2636 (*op2)(temp1 , ret, temp1);
2637
2638 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
2639 }
2640
2641 /* ret = r1[pos1] op1 r2[pos2]; */
2642 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
2643 int pos1, int pos2,
2644 void(*op1)(TCGv, TCGv, TCGv))
2645 {
2646 TCGv temp1, temp2;
2647
2648 temp1 = tcg_temp_new();
2649 temp2 = tcg_temp_new();
2650
2651 tcg_gen_shri_tl(temp2, r2, pos2);
2652 tcg_gen_shri_tl(temp1, r1, pos1);
2653
2654 (*op1)(ret, temp1, temp2);
2655
2656 tcg_gen_andi_tl(ret, ret, 0x1);
2657 }
2658
2659 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
2660 void(*op)(TCGv, TCGv, TCGv))
2661 {
2662 TCGv temp = tcg_temp_new();
2663 TCGv temp2 = tcg_temp_new();
2664 /* temp = (arg1 cond arg2 )*/
2665 tcg_gen_setcond_tl(cond, temp, r1, r2);
2666 /* temp2 = ret[0]*/
2667 tcg_gen_andi_tl(temp2, ret, 0x1);
2668 /* temp = temp insn temp2 */
2669 (*op)(temp, temp, temp2);
2670 /* ret = {ret[31:1], temp} */
2671 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
2672 }
2673
2674 static inline void
2675 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
2676 void(*op)(TCGv, TCGv, TCGv))
2677 {
2678 TCGv temp = tcg_const_i32(con);
2679 gen_accumulating_cond(cond, ret, r1, temp, op);
2680 }
2681
2682 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
2683 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
2684 {
2685 tcg_gen_setcond_tl(cond, ret, r1, r2);
2686 tcg_gen_neg_tl(ret, ret);
2687 }
2688
2689 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
2690 {
2691 TCGv b0 = tcg_temp_new();
2692 TCGv b1 = tcg_temp_new();
2693 TCGv b2 = tcg_temp_new();
2694 TCGv b3 = tcg_temp_new();
2695
2696 /* byte 0 */
2697 tcg_gen_andi_tl(b0, r1, 0xff);
2698 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
2699
2700 /* byte 1 */
2701 tcg_gen_andi_tl(b1, r1, 0xff00);
2702 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
2703
2704 /* byte 2 */
2705 tcg_gen_andi_tl(b2, r1, 0xff0000);
2706 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
2707
2708 /* byte 3 */
2709 tcg_gen_andi_tl(b3, r1, 0xff000000);
2710 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
2711
2712 /* combine them */
2713 tcg_gen_or_tl(ret, b0, b1);
2714 tcg_gen_or_tl(ret, ret, b2);
2715 tcg_gen_or_tl(ret, ret, b3);
2716 }
2717
2718 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
2719 {
2720 TCGv h0 = tcg_temp_new();
2721 TCGv h1 = tcg_temp_new();
2722
2723 /* halfword 0 */
2724 tcg_gen_andi_tl(h0, r1, 0xffff);
2725 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
2726
2727 /* halfword 1 */
2728 tcg_gen_andi_tl(h1, r1, 0xffff0000);
2729 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
2730
2731 /* combine them */
2732 tcg_gen_or_tl(ret, h0, h1);
2733 }
2734
2735 /* mask = ((1 << width) -1) << pos;
2736 ret = (r1 & ~mask) | (r2 << pos) & mask); */
2737 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
2738 {
2739 TCGv mask = tcg_temp_new();
2740 TCGv temp = tcg_temp_new();
2741 TCGv temp2 = tcg_temp_new();
2742
2743 tcg_gen_movi_tl(mask, 1);
2744 tcg_gen_shl_tl(mask, mask, width);
2745 tcg_gen_subi_tl(mask, mask, 1);
2746 tcg_gen_shl_tl(mask, mask, pos);
2747
2748 tcg_gen_shl_tl(temp, r2, pos);
2749 tcg_gen_and_tl(temp, temp, mask);
2750 tcg_gen_andc_tl(temp2, r1, mask);
2751 tcg_gen_or_tl(ret, temp, temp2);
2752 }
2753
2754 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
2755 {
2756 TCGv_i64 temp = tcg_temp_new_i64();
2757
2758 gen_helper_bsplit(temp, r1);
2759 tcg_gen_extr_i64_i32(rl, rh, temp);
2760 }
2761
2762 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
2763 {
2764 TCGv_i64 temp = tcg_temp_new_i64();
2765
2766 gen_helper_unpack(temp, r1);
2767 tcg_gen_extr_i64_i32(rl, rh, temp);
2768 }
2769
2770 static inline void
2771 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2772 {
2773 TCGv_i64 ret = tcg_temp_new_i64();
2774
2775 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
2776 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
2777 } else {
2778 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
2779 }
2780 tcg_gen_extr_i64_i32(rl, rh, ret);
2781 }
2782
2783 static inline void
2784 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2785 {
2786 TCGv_i64 ret = tcg_temp_new_i64();
2787
2788 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
2789 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
2790 } else {
2791 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
2792 }
2793 tcg_gen_extr_i64_i32(rl, rh, ret);
2794 }
2795
2796 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
2797 {
2798 TCGv temp = tcg_temp_new();
2799 /* calc AV bit */
2800 tcg_gen_add_tl(temp, arg_low, arg_low);
2801 tcg_gen_xor_tl(temp, temp, arg_low);
2802 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
2803 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
2804 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2805 /* calc SAV bit */
2806 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2807 tcg_gen_movi_tl(cpu_PSW_V, 0);
2808 }
2809
2810 static void gen_calc_usb_mulr_h(TCGv arg)
2811 {
2812 TCGv temp = tcg_temp_new();
2813 /* calc AV bit */
2814 tcg_gen_add_tl(temp, arg, arg);
2815 tcg_gen_xor_tl(temp, temp, arg);
2816 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
2817 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2818 /* calc SAV bit */
2819 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2820 /* clear V bit */
2821 tcg_gen_movi_tl(cpu_PSW_V, 0);
2822 }
2823
2824 /* helpers for generating program flow micro-ops */
2825
2826 static inline void gen_save_pc(target_ulong pc)
2827 {
2828 tcg_gen_movi_tl(cpu_PC, pc);
2829 }
2830
2831 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2832 {
2833 if (translator_use_goto_tb(&ctx->base, dest)) {
2834 tcg_gen_goto_tb(n);
2835 gen_save_pc(dest);
2836 tcg_gen_exit_tb(ctx->base.tb, n);
2837 } else {
2838 gen_save_pc(dest);
2839 tcg_gen_lookup_and_goto_ptr();
2840 }
2841 }
2842
2843 static void generate_trap(DisasContext *ctx, int class, int tin)
2844 {
2845 TCGv_i32 classtemp = tcg_const_i32(class);
2846 TCGv_i32 tintemp = tcg_const_i32(tin);
2847
2848 gen_save_pc(ctx->base.pc_next);
2849 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
2850 ctx->base.is_jmp = DISAS_NORETURN;
2851 }
2852
2853 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
2854 TCGv r2, int16_t address)
2855 {
2856 TCGLabel *jumpLabel = gen_new_label();
2857 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
2858
2859 gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
2860
2861 gen_set_label(jumpLabel);
2862 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2);
2863 }
2864
2865 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
2866 int r2, int16_t address)
2867 {
2868 TCGv temp = tcg_const_i32(r2);
2869 gen_branch_cond(ctx, cond, r1, temp, address);
2870 }
2871
2872 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
2873 {
2874 TCGLabel *l1 = gen_new_label();
2875
2876 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
2877 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
2878 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset);
2879 gen_set_label(l1);
2880 gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
2881 }
2882
2883 static void gen_fcall_save_ctx(DisasContext *ctx)
2884 {
2885 TCGv temp = tcg_temp_new();
2886
2887 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
2888 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
2889 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
2890 tcg_gen_mov_tl(cpu_gpr_a[10], temp);
2891 }
2892
2893 static void gen_fret(DisasContext *ctx)
2894 {
2895 TCGv temp = tcg_temp_new();
2896
2897 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
2898 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
2899 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
2900 tcg_gen_mov_tl(cpu_PC, temp);
2901 tcg_gen_exit_tb(NULL, 0);
2902 ctx->base.is_jmp = DISAS_NORETURN;
2903 }
2904
2905 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
2906 int r2 , int32_t constant , int32_t offset)
2907 {
2908 TCGv temp, temp2;
2909 int n;
2910
2911 switch (opc) {
2912 /* SB-format jumps */
2913 case OPC1_16_SB_J:
2914 case OPC1_32_B_J:
2915 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
2916 break;
2917 case OPC1_32_B_CALL:
2918 case OPC1_16_SB_CALL:
2919 gen_helper_1arg(call, ctx->pc_succ_insn);
2920 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
2921 break;
2922 case OPC1_16_SB_JZ:
2923 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
2924 break;
2925 case OPC1_16_SB_JNZ:
2926 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
2927 break;
2928 /* SBC-format jumps */
2929 case OPC1_16_SBC_JEQ:
2930 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
2931 break;
2932 case OPC1_16_SBC_JEQ2:
2933 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant,
2934 offset + 16);
2935 break;
2936 case OPC1_16_SBC_JNE:
2937 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
2938 break;
2939 case OPC1_16_SBC_JNE2:
2940 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15],
2941 constant, offset + 16);
2942 break;
2943 /* SBRN-format jumps */
2944 case OPC1_16_SBRN_JZ_T:
2945 temp = tcg_temp_new();
2946 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2947 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
2948 break;
2949 case OPC1_16_SBRN_JNZ_T:
2950 temp = tcg_temp_new();
2951 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2952 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
2953 break;
2954 /* SBR-format jumps */
2955 case OPC1_16_SBR_JEQ:
2956 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2957 offset);
2958 break;
2959 case OPC1_16_SBR_JEQ2:
2960 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2961 offset + 16);
2962 break;
2963 case OPC1_16_SBR_JNE:
2964 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2965 offset);
2966 break;
2967 case OPC1_16_SBR_JNE2:
2968 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2969 offset + 16);
2970 break;
2971 case OPC1_16_SBR_JNZ:
2972 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
2973 break;
2974 case OPC1_16_SBR_JNZ_A:
2975 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
2976 break;
2977 case OPC1_16_SBR_JGEZ:
2978 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
2979 break;
2980 case OPC1_16_SBR_JGTZ:
2981 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
2982 break;
2983 case OPC1_16_SBR_JLEZ:
2984 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
2985 break;
2986 case OPC1_16_SBR_JLTZ:
2987 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
2988 break;
2989 case OPC1_16_SBR_JZ:
2990 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
2991 break;
2992 case OPC1_16_SBR_JZ_A:
2993 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
2994 break;
2995 case OPC1_16_SBR_LOOP:
2996 gen_loop(ctx, r1, offset * 2 - 32);
2997 break;
2998 /* SR-format jumps */
2999 case OPC1_16_SR_JI:
3000 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
3001 tcg_gen_exit_tb(NULL, 0);
3002 break;
3003 case OPC2_32_SYS_RET:
3004 case OPC2_16_SR_RET:
3005 gen_helper_ret(cpu_env);
3006 tcg_gen_exit_tb(NULL, 0);
3007 break;
3008 /* B-format */
3009 case OPC1_32_B_CALLA:
3010 gen_helper_1arg(call, ctx->pc_succ_insn);
3011 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3012 break;
3013 case OPC1_32_B_FCALL:
3014 gen_fcall_save_ctx(ctx);
3015 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3016 break;
3017 case OPC1_32_B_FCALLA:
3018 gen_fcall_save_ctx(ctx);
3019 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3020 break;
3021 case OPC1_32_B_JLA:
3022 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
3023 /* fall through */
3024 case OPC1_32_B_JA:
3025 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3026 break;
3027 case OPC1_32_B_JL:
3028 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
3029 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3030 break;
3031 /* BOL format */
3032 case OPCM_32_BRC_EQ_NEQ:
3033 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3034 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3035 } else {
3036 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3037 }
3038 break;
3039 case OPCM_32_BRC_GE:
3040 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3041 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3042 } else {
3043 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3044 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3045 offset);
3046 }
3047 break;
3048 case OPCM_32_BRC_JLT:
3049 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3050 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3051 } else {
3052 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3053 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3054 offset);
3055 }
3056 break;
3057 case OPCM_32_BRC_JNE:
3058 temp = tcg_temp_new();
3059 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3060 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3061 /* subi is unconditional */
3062 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3063 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3064 } else {
3065 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3066 /* addi is unconditional */
3067 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3068 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3069 }
3070 break;
3071 /* BRN format */
3072 case OPCM_32_BRN_JTT:
3073 n = MASK_OP_BRN_N(ctx->opcode);
3074
3075 temp = tcg_temp_new();
3076 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3077
3078 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3079 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3080 } else {
3081 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3082 }
3083 break;
3084 /* BRR Format */
3085 case OPCM_32_BRR_EQ_NEQ:
3086 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3087 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3088 offset);
3089 } else {
3090 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3091 offset);
3092 }
3093 break;
3094 case OPCM_32_BRR_ADDR_EQ_NEQ:
3095 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3096 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3097 offset);
3098 } else {
3099 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3100 offset);
3101 }
3102 break;
3103 case OPCM_32_BRR_GE:
3104 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3105 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3106 offset);
3107 } else {
3108 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3109 offset);
3110 }
3111 break;
3112 case OPCM_32_BRR_JLT:
3113 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3114 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3115 offset);
3116 } else {
3117 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3118 offset);
3119 }
3120 break;
3121 case OPCM_32_BRR_LOOP:
3122 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3123 gen_loop(ctx, r2, offset * 2);
3124 } else {
3125 /* OPC2_32_BRR_LOOPU */
3126 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3127 }
3128 break;
3129 case OPCM_32_BRR_JNE:
3130 temp = tcg_temp_new();
3131 temp2 = tcg_temp_new();
3132 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3133 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3134 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3135 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3136 /* subi is unconditional */
3137 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3138 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3139 } else {
3140 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3141 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3142 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3143 /* addi is unconditional */
3144 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3145 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3146 }
3147 break;
3148 case OPCM_32_BRR_JNZ:
3149 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3150 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3151 } else {
3152 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3153 }
3154 break;
3155 default:
3156 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3157 }
3158 ctx->base.is_jmp = DISAS_NORETURN;
3159 }
3160
3161
3162 /*
3163 * Functions for decoding instructions
3164 */
3165
3166 static void decode_src_opc(DisasContext *ctx, int op1)
3167 {
3168 int r1;
3169 int32_t const4;
3170 TCGv temp, temp2;
3171
3172 r1 = MASK_OP_SRC_S1D(ctx->opcode);
3173 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3174
3175 switch (op1) {
3176 case OPC1_16_SRC_ADD:
3177 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3178 break;
3179 case OPC1_16_SRC_ADD_A15:
3180 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3181 break;
3182 case OPC1_16_SRC_ADD_15A:
3183 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3184 break;
3185 case OPC1_16_SRC_ADD_A:
3186 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3187 break;
3188 case OPC1_16_SRC_CADD:
3189 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3190 cpu_gpr_d[15]);
3191 break;
3192 case OPC1_16_SRC_CADDN:
3193 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3194 cpu_gpr_d[15]);
3195 break;
3196 case OPC1_16_SRC_CMOV:
3197 temp = tcg_const_tl(0);
3198 temp2 = tcg_const_tl(const4);
3199 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3200 temp2, cpu_gpr_d[r1]);
3201 break;
3202 case OPC1_16_SRC_CMOVN:
3203 temp = tcg_const_tl(0);
3204 temp2 = tcg_const_tl(const4);
3205 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3206 temp2, cpu_gpr_d[r1]);
3207 break;
3208 case OPC1_16_SRC_EQ:
3209 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3210 const4);
3211 break;
3212 case OPC1_16_SRC_LT:
3213 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3214 const4);
3215 break;
3216 case OPC1_16_SRC_MOV:
3217 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3218 break;
3219 case OPC1_16_SRC_MOV_A:
3220 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3221 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3222 break;
3223 case OPC1_16_SRC_MOV_E:
3224 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3225 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3226 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3227 } else {
3228 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3229 }
3230 break;
3231 case OPC1_16_SRC_SH:
3232 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3233 break;
3234 case OPC1_16_SRC_SHA:
3235 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3236 break;
3237 default:
3238 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3239 }
3240 }
3241
3242 static void decode_srr_opc(DisasContext *ctx, int op1)
3243 {
3244 int r1, r2;
3245 TCGv temp;
3246
3247 r1 = MASK_OP_SRR_S1D(ctx->opcode);
3248 r2 = MASK_OP_SRR_S2(ctx->opcode);
3249
3250 switch (op1) {
3251 case OPC1_16_SRR_ADD:
3252 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3253 break;
3254 case OPC1_16_SRR_ADD_A15:
3255 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3256 break;
3257 case OPC1_16_SRR_ADD_15A:
3258 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3259 break;
3260 case OPC1_16_SRR_ADD_A:
3261 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3262 break;
3263 case OPC1_16_SRR_ADDS:
3264 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3265 break;
3266 case OPC1_16_SRR_AND:
3267 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3268 break;
3269 case OPC1_16_SRR_CMOV:
3270 temp = tcg_const_tl(0);
3271 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3272 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3273 break;
3274 case OPC1_16_SRR_CMOVN:
3275 temp = tcg_const_tl(0);
3276 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3277 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3278 break;
3279 case OPC1_16_SRR_EQ:
3280 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3281 cpu_gpr_d[r2]);
3282 break;
3283 case OPC1_16_SRR_LT:
3284 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3285 cpu_gpr_d[r2]);
3286 break;
3287 case OPC1_16_SRR_MOV:
3288 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3289 break;
3290 case OPC1_16_SRR_MOV_A:
3291 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3292 break;
3293 case OPC1_16_SRR_MOV_AA:
3294 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3295 break;
3296 case OPC1_16_SRR_MOV_D:
3297 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3298 break;
3299 case OPC1_16_SRR_MUL:
3300 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3301 break;
3302 case OPC1_16_SRR_OR:
3303 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3304 break;
3305 case OPC1_16_SRR_SUB:
3306 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3307 break;
3308 case OPC1_16_SRR_SUB_A15B:
3309 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3310 break;
3311 case OPC1_16_SRR_SUB_15AB:
3312 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3313 break;
3314 case OPC1_16_SRR_SUBS:
3315 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3316 break;
3317 case OPC1_16_SRR_XOR:
3318 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3319 break;
3320 default:
3321 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3322 }
3323 }
3324
3325 static void decode_ssr_opc(DisasContext *ctx, int op1)
3326 {
3327 int r1, r2;
3328
3329 r1 = MASK_OP_SSR_S1(ctx->opcode);
3330 r2 = MASK_OP_SSR_S2(ctx->opcode);
3331
3332 switch (op1) {
3333 case OPC1_16_SSR_ST_A:
3334 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3335 break;
3336 case OPC1_16_SSR_ST_A_POSTINC:
3337 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3338 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3339 break;
3340 case OPC1_16_SSR_ST_B:
3341 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3342 break;
3343 case OPC1_16_SSR_ST_B_POSTINC:
3344 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3345 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3346 break;
3347 case OPC1_16_SSR_ST_H:
3348 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3349 break;
3350 case OPC1_16_SSR_ST_H_POSTINC:
3351 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3352 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3353 break;
3354 case OPC1_16_SSR_ST_W:
3355 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3356 break;
3357 case OPC1_16_SSR_ST_W_POSTINC:
3358 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3359 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3360 break;
3361 default:
3362 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3363 }
3364 }
3365
3366 static void decode_sc_opc(DisasContext *ctx, int op1)
3367 {
3368 int32_t const16;
3369
3370 const16 = MASK_OP_SC_CONST8(ctx->opcode);
3371
3372 switch (op1) {
3373 case OPC1_16_SC_AND:
3374 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3375 break;
3376 case OPC1_16_SC_BISR:
3377 gen_helper_1arg(bisr, const16 & 0xff);
3378 break;
3379 case OPC1_16_SC_LD_A:
3380 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3381 break;
3382 case OPC1_16_SC_LD_W:
3383 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3384 break;
3385 case OPC1_16_SC_MOV:
3386 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3387 break;
3388 case OPC1_16_SC_OR:
3389 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3390 break;
3391 case OPC1_16_SC_ST_A:
3392 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3393 break;
3394 case OPC1_16_SC_ST_W:
3395 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3396 break;
3397 case OPC1_16_SC_SUB_A:
3398 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3399 break;
3400 default:
3401 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3402 }
3403 }
3404
3405 static void decode_slr_opc(DisasContext *ctx, int op1)
3406 {
3407 int r1, r2;
3408
3409 r1 = MASK_OP_SLR_D(ctx->opcode);
3410 r2 = MASK_OP_SLR_S2(ctx->opcode);
3411
3412 switch (op1) {
3413 /* SLR-format */
3414 case OPC1_16_SLR_LD_A:
3415 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3416 break;
3417 case OPC1_16_SLR_LD_A_POSTINC:
3418 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3419 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3420 break;
3421 case OPC1_16_SLR_LD_BU:
3422 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3423 break;
3424 case OPC1_16_SLR_LD_BU_POSTINC:
3425 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3426 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3427 break;
3428 case OPC1_16_SLR_LD_H:
3429 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3430 break;
3431 case OPC1_16_SLR_LD_H_POSTINC:
3432 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3433 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3434 break;
3435 case OPC1_16_SLR_LD_W:
3436 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3437 break;
3438 case OPC1_16_SLR_LD_W_POSTINC:
3439 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3440 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3441 break;
3442 default:
3443 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3444 }
3445 }
3446
3447 static void decode_sro_opc(DisasContext *ctx, int op1)
3448 {
3449 int r2;
3450 int32_t address;
3451
3452 r2 = MASK_OP_SRO_S2(ctx->opcode);
3453 address = MASK_OP_SRO_OFF4(ctx->opcode);
3454
3455 /* SRO-format */
3456 switch (op1) {
3457 case OPC1_16_SRO_LD_A:
3458 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3459 break;
3460 case OPC1_16_SRO_LD_BU:
3461 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3462 break;
3463 case OPC1_16_SRO_LD_H:
3464 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3465 break;
3466 case OPC1_16_SRO_LD_W:
3467 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3468 break;
3469 case OPC1_16_SRO_ST_A:
3470 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3471 break;
3472 case OPC1_16_SRO_ST_B:
3473 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3474 break;
3475 case OPC1_16_SRO_ST_H:
3476 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3477 break;
3478 case OPC1_16_SRO_ST_W:
3479 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3480 break;
3481 default:
3482 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3483 }
3484 }
3485
3486 static void decode_sr_system(DisasContext *ctx)
3487 {
3488 uint32_t op2;
3489 op2 = MASK_OP_SR_OP2(ctx->opcode);
3490
3491 switch (op2) {
3492 case OPC2_16_SR_NOP:
3493 break;
3494 case OPC2_16_SR_RET:
3495 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3496 break;
3497 case OPC2_16_SR_RFE:
3498 gen_helper_rfe(cpu_env);
3499 tcg_gen_exit_tb(NULL, 0);
3500 ctx->base.is_jmp = DISAS_NORETURN;
3501 break;
3502 case OPC2_16_SR_DEBUG:
3503 /* raise EXCP_DEBUG */
3504 break;
3505 case OPC2_16_SR_FRET:
3506 gen_fret(ctx);
3507 break;
3508 default:
3509 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3510 }
3511 }
3512
3513 static void decode_sr_accu(DisasContext *ctx)
3514 {
3515 uint32_t op2;
3516 uint32_t r1;
3517
3518 r1 = MASK_OP_SR_S1D(ctx->opcode);
3519 op2 = MASK_OP_SR_OP2(ctx->opcode);
3520
3521 switch (op2) {
3522 case OPC2_16_SR_RSUB:
3523 /* calc V bit -- overflow only if r1 = -0x80000000 */
3524 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000);
3525 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3526 /* calc SV bit */
3527 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3528 /* sub */
3529 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3530 /* calc av */
3531 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3532 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3533 /* calc sav */
3534 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3535 break;
3536 case OPC2_16_SR_SAT_B:
3537 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3538 break;
3539 case OPC2_16_SR_SAT_BU:
3540 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3541 break;
3542 case OPC2_16_SR_SAT_H:
3543 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3544 break;
3545 case OPC2_16_SR_SAT_HU:
3546 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3547 break;
3548 default:
3549 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3550 }
3551 }
3552
3553 static void decode_16Bit_opc(DisasContext *ctx)
3554 {
3555 int op1;
3556 int r1, r2;
3557 int32_t const16;
3558 int32_t address;
3559 TCGv temp;
3560
3561 op1 = MASK_OP_MAJOR(ctx->opcode);
3562
3563 /* handle ADDSC.A opcode only being 6 bit long */
3564 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3565 op1 = OPC1_16_SRRS_ADDSC_A;
3566 }
3567
3568 switch (op1) {
3569 case OPC1_16_SRC_ADD:
3570 case OPC1_16_SRC_ADD_A15:
3571 case OPC1_16_SRC_ADD_15A:
3572 case OPC1_16_SRC_ADD_A:
3573 case OPC1_16_SRC_CADD:
3574 case OPC1_16_SRC_CADDN:
3575 case OPC1_16_SRC_CMOV:
3576 case OPC1_16_SRC_CMOVN:
3577 case OPC1_16_SRC_EQ:
3578 case OPC1_16_SRC_LT:
3579 case OPC1_16_SRC_MOV:
3580 case OPC1_16_SRC_MOV_A:
3581 case OPC1_16_SRC_MOV_E:
3582 case OPC1_16_SRC_SH:
3583 case OPC1_16_SRC_SHA:
3584 decode_src_opc(ctx, op1);
3585 break;
3586 /* SRR-format */
3587 case OPC1_16_SRR_ADD:
3588 case OPC1_16_SRR_ADD_A15:
3589 case OPC1_16_SRR_ADD_15A:
3590 case OPC1_16_SRR_ADD_A:
3591 case OPC1_16_SRR_ADDS:
3592 case OPC1_16_SRR_AND:
3593 case OPC1_16_SRR_CMOV:
3594 case OPC1_16_SRR_CMOVN:
3595 case OPC1_16_SRR_EQ:
3596 case OPC1_16_SRR_LT:
3597 case OPC1_16_SRR_MOV:
3598 case OPC1_16_SRR_MOV_A:
3599 case OPC1_16_SRR_MOV_AA:
3600 case OPC1_16_SRR_MOV_D:
3601 case OPC1_16_SRR_MUL:
3602 case OPC1_16_SRR_OR:
3603 case OPC1_16_SRR_SUB:
3604 case OPC1_16_SRR_SUB_A15B:
3605 case OPC1_16_SRR_SUB_15AB:
3606 case OPC1_16_SRR_SUBS:
3607 case OPC1_16_SRR_XOR:
3608 decode_srr_opc(ctx, op1);
3609 break;
3610 /* SSR-format */
3611 case OPC1_16_SSR_ST_A:
3612 case OPC1_16_SSR_ST_A_POSTINC:
3613 case OPC1_16_SSR_ST_B:
3614 case OPC1_16_SSR_ST_B_POSTINC:
3615 case OPC1_16_SSR_ST_H:
3616 case OPC1_16_SSR_ST_H_POSTINC:
3617 case OPC1_16_SSR_ST_W:
3618 case OPC1_16_SSR_ST_W_POSTINC:
3619 decode_ssr_opc(ctx, op1);
3620 break;
3621 /* SRRS-format */
3622 case OPC1_16_SRRS_ADDSC_A:
3623 r2 = MASK_OP_SRRS_S2(ctx->opcode);
3624 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
3625 const16 = MASK_OP_SRRS_N(ctx->opcode);
3626 temp = tcg_temp_new();
3627 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
3628 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
3629 break;
3630 /* SLRO-format */
3631 case OPC1_16_SLRO_LD_A:
3632 r1 = MASK_OP_SLRO_D(ctx->opcode);
3633 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3634 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3635 break;
3636 case OPC1_16_SLRO_LD_BU:
3637 r1 = MASK_OP_SLRO_D(ctx->opcode);
3638 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3639 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3640 break;
3641 case OPC1_16_SLRO_LD_H:
3642 r1 = MASK_OP_SLRO_D(ctx->opcode);
3643 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3644 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3645 break;
3646 case OPC1_16_SLRO_LD_W:
3647 r1 = MASK_OP_SLRO_D(ctx->opcode);
3648 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3649 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3650 break;
3651 /* SB-format */
3652 case OPC1_16_SB_CALL:
3653 case OPC1_16_SB_J:
3654 case OPC1_16_SB_JNZ:
3655 case OPC1_16_SB_JZ:
3656 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
3657 gen_compute_branch(ctx, op1, 0, 0, 0, address);
3658 break;
3659 /* SBC-format */
3660 case OPC1_16_SBC_JEQ:
3661 case OPC1_16_SBC_JNE:
3662 address = MASK_OP_SBC_DISP4(ctx->opcode);
3663 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3664 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3665 break;
3666 case OPC1_16_SBC_JEQ2:
3667 case OPC1_16_SBC_JNE2:
3668 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3669 address = MASK_OP_SBC_DISP4(ctx->opcode);
3670 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3671 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3672 } else {
3673 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3674 }
3675 break;
3676 /* SBRN-format */
3677 case OPC1_16_SBRN_JNZ_T:
3678 case OPC1_16_SBRN_JZ_T:
3679 address = MASK_OP_SBRN_DISP4(ctx->opcode);
3680 const16 = MASK_OP_SBRN_N(ctx->opcode);
3681 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3682 break;
3683 /* SBR-format */
3684 case OPC1_16_SBR_JEQ2:
3685 case OPC1_16_SBR_JNE2:
3686 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3687 r1 = MASK_OP_SBR_S2(ctx->opcode);
3688 address = MASK_OP_SBR_DISP4(ctx->opcode);
3689 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3690 } else {
3691 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3692 }
3693 break;
3694 case OPC1_16_SBR_JEQ:
3695 case OPC1_16_SBR_JGEZ:
3696 case OPC1_16_SBR_JGTZ:
3697 case OPC1_16_SBR_JLEZ:
3698 case OPC1_16_SBR_JLTZ:
3699 case OPC1_16_SBR_JNE:
3700 case OPC1_16_SBR_JNZ:
3701 case OPC1_16_SBR_JNZ_A:
3702 case OPC1_16_SBR_JZ:
3703 case OPC1_16_SBR_JZ_A:
3704 case OPC1_16_SBR_LOOP:
3705 r1 = MASK_OP_SBR_S2(ctx->opcode);
3706 address = MASK_OP_SBR_DISP4(ctx->opcode);
3707 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3708 break;
3709 /* SC-format */
3710 case OPC1_16_SC_AND:
3711 case OPC1_16_SC_BISR:
3712 case OPC1_16_SC_LD_A:
3713 case OPC1_16_SC_LD_W:
3714 case OPC1_16_SC_MOV:
3715 case OPC1_16_SC_OR:
3716 case OPC1_16_SC_ST_A:
3717 case OPC1_16_SC_ST_W:
3718 case OPC1_16_SC_SUB_A:
3719 decode_sc_opc(ctx, op1);
3720 break;
3721 /* SLR-format */
3722 case OPC1_16_SLR_LD_A:
3723 case OPC1_16_SLR_LD_A_POSTINC:
3724 case OPC1_16_SLR_LD_BU:
3725 case OPC1_16_SLR_LD_BU_POSTINC:
3726 case OPC1_16_SLR_LD_H:
3727 case OPC1_16_SLR_LD_H_POSTINC:
3728 case OPC1_16_SLR_LD_W:
3729 case OPC1_16_SLR_LD_W_POSTINC:
3730 decode_slr_opc(ctx, op1);
3731 break;
3732 /* SRO-format */
3733 case OPC1_16_SRO_LD_A:
3734 case OPC1_16_SRO_LD_BU:
3735 case OPC1_16_SRO_LD_H:
3736 case OPC1_16_SRO_LD_W:
3737 case OPC1_16_SRO_ST_A:
3738 case OPC1_16_SRO_ST_B:
3739 case OPC1_16_SRO_ST_H:
3740 case OPC1_16_SRO_ST_W:
3741 decode_sro_opc(ctx, op1);
3742 break;
3743 /* SSRO-format */
3744 case OPC1_16_SSRO_ST_A:
3745 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3746 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3747 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3748 break;
3749 case OPC1_16_SSRO_ST_B:
3750 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3751 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3752 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3753 break;
3754 case OPC1_16_SSRO_ST_H:
3755 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3756 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3757 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3758 break;
3759 case OPC1_16_SSRO_ST_W:
3760 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3761 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3762 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3763 break;
3764 /* SR-format */
3765 case OPCM_16_SR_SYSTEM:
3766 decode_sr_system(ctx);
3767 break;
3768 case OPCM_16_SR_ACCU:
3769 decode_sr_accu(ctx);
3770 break;
3771 case OPC1_16_SR_JI:
3772 r1 = MASK_OP_SR_S1D(ctx->opcode);
3773 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
3774 break;
3775 case OPC1_16_SR_NOT:
3776 r1 = MASK_OP_SR_S1D(ctx->opcode);
3777 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3778 break;
3779 default:
3780 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3781 }
3782 }
3783
3784 /*
3785 * 32 bit instructions
3786 */
3787
3788 /* ABS-format */
3789 static void decode_abs_ldw(DisasContext *ctx)
3790 {
3791 int32_t op2;
3792 int32_t r1;
3793 uint32_t address;
3794 TCGv temp;
3795
3796 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3797 address = MASK_OP_ABS_OFF18(ctx->opcode);
3798 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3799
3800 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3801
3802 switch (op2) {
3803 case OPC2_32_ABS_LD_A:
3804 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3805 break;
3806 case OPC2_32_ABS_LD_D:
3807 CHECK_REG_PAIR(r1);
3808 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3809 break;
3810 case OPC2_32_ABS_LD_DA:
3811 CHECK_REG_PAIR(r1);
3812 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3813 break;
3814 case OPC2_32_ABS_LD_W:
3815 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3816 break;
3817 default:
3818 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3819 }
3820 }
3821
3822 static void decode_abs_ldb(DisasContext *ctx)
3823 {
3824 int32_t op2;
3825 int32_t r1;
3826 uint32_t address;
3827 TCGv temp;
3828
3829 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3830 address = MASK_OP_ABS_OFF18(ctx->opcode);
3831 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3832
3833 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3834
3835 switch (op2) {
3836 case OPC2_32_ABS_LD_B:
3837 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
3838 break;
3839 case OPC2_32_ABS_LD_BU:
3840 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3841 break;
3842 case OPC2_32_ABS_LD_H:
3843 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
3844 break;
3845 case OPC2_32_ABS_LD_HU:
3846 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3847 break;
3848 default:
3849 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3850 }
3851 }
3852
3853 static void decode_abs_ldst_swap(DisasContext *ctx)
3854 {
3855 int32_t op2;
3856 int32_t r1;
3857 uint32_t address;
3858 TCGv temp;
3859
3860 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3861 address = MASK_OP_ABS_OFF18(ctx->opcode);
3862 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3863
3864 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3865
3866 switch (op2) {
3867 case OPC2_32_ABS_LDMST:
3868 gen_ldmst(ctx, r1, temp);
3869 break;
3870 case OPC2_32_ABS_SWAP_W:
3871 gen_swap(ctx, r1, temp);
3872 break;
3873 default:
3874 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3875 }
3876 }
3877
3878 static void decode_abs_ldst_context(DisasContext *ctx)
3879 {
3880 uint32_t op2;
3881 int32_t off18;
3882
3883 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
3884 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3885
3886 switch (op2) {
3887 case OPC2_32_ABS_LDLCX:
3888 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
3889 break;
3890 case OPC2_32_ABS_LDUCX:
3891 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
3892 break;
3893 case OPC2_32_ABS_STLCX:
3894 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
3895 break;
3896 case OPC2_32_ABS_STUCX:
3897 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
3898 break;
3899 default:
3900 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3901 }
3902 }
3903
3904 static void decode_abs_store(DisasContext *ctx)
3905 {
3906 int32_t op2;
3907 int32_t r1;
3908 uint32_t address;
3909 TCGv temp;
3910
3911 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3912 address = MASK_OP_ABS_OFF18(ctx->opcode);
3913 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3914
3915 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3916
3917 switch (op2) {
3918 case OPC2_32_ABS_ST_A:
3919 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3920 break;
3921 case OPC2_32_ABS_ST_D:
3922 CHECK_REG_PAIR(r1);
3923 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3924 break;
3925 case OPC2_32_ABS_ST_DA:
3926 CHECK_REG_PAIR(r1);
3927 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3928 break;
3929 case OPC2_32_ABS_ST_W:
3930 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3931 break;
3932 default:
3933 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3934 }
3935 }
3936
3937 static void decode_abs_storeb_h(DisasContext *ctx)
3938 {
3939 int32_t op2;
3940 int32_t r1;
3941 uint32_t address;
3942 TCGv temp;
3943
3944 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3945 address = MASK_OP_ABS_OFF18(ctx->opcode);
3946 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3947
3948 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3949
3950 switch (op2) {
3951 case OPC2_32_ABS_ST_B:
3952 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3953 break;
3954 case OPC2_32_ABS_ST_H:
3955 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3956 break;
3957 default:
3958 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3959 }
3960 }
3961
3962 /* Bit-format */
3963
3964 static void decode_bit_andacc(DisasContext *ctx)
3965 {
3966 uint32_t op2;
3967 int r1, r2, r3;
3968 int pos1, pos2;
3969
3970 r1 = MASK_OP_BIT_S1(ctx->opcode);
3971 r2 = MASK_OP_BIT_S2(ctx->opcode);
3972 r3 = MASK_OP_BIT_D(ctx->opcode);
3973 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3974 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3975 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3976
3977
3978 switch (op2) {
3979 case OPC2_32_BIT_AND_AND_T:
3980 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3981 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
3982 break;
3983 case OPC2_32_BIT_AND_ANDN_T:
3984 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3985 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
3986 break;
3987 case OPC2_32_BIT_AND_NOR_T:
3988 if (TCG_TARGET_HAS_andc_i32) {
3989 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3990 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
3991 } else {
3992 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3993 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
3994 }
3995 break;
3996 case OPC2_32_BIT_AND_OR_T:
3997 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3998 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
3999 break;
4000 default:
4001 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4002 }
4003 }
4004
4005 static void decode_bit_logical_t(DisasContext *ctx)
4006 {
4007 uint32_t op2;
4008 int r1, r2, r3;
4009 int pos1, pos2;
4010 r1 = MASK_OP_BIT_S1(ctx->opcode);
4011 r2 = MASK_OP_BIT_S2(ctx->opcode);
4012 r3 = MASK_OP_BIT_D(ctx->opcode);
4013 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4014 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4015 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4016
4017 switch (op2) {
4018 case OPC2_32_BIT_AND_T:
4019 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4020 pos1, pos2, &tcg_gen_and_tl);
4021 break;
4022 case OPC2_32_BIT_ANDN_T:
4023 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4024 pos1, pos2, &tcg_gen_andc_tl);
4025 break;
4026 case OPC2_32_BIT_NOR_T:
4027 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4028 pos1, pos2, &tcg_gen_nor_tl);
4029 break;
4030 case OPC2_32_BIT_OR_T:
4031 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4032 pos1, pos2, &tcg_gen_or_tl);
4033 break;
4034 default:
4035 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4036 }
4037 }
4038
4039 static void decode_bit_insert(DisasContext *ctx)
4040 {
4041 uint32_t op2;
4042 int r1, r2, r3;
4043 int pos1, pos2;
4044 TCGv temp;
4045 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4046 r1 = MASK_OP_BIT_S1(ctx->opcode);
4047 r2 = MASK_OP_BIT_S2(ctx->opcode);
4048 r3 = MASK_OP_BIT_D(ctx->opcode);
4049 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4050 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4051
4052 temp = tcg_temp_new();
4053
4054 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4055 if (op2 == OPC2_32_BIT_INSN_T) {
4056 tcg_gen_not_tl(temp, temp);
4057 }
4058 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4059 }
4060
4061 static void decode_bit_logical_t2(DisasContext *ctx)
4062 {
4063 uint32_t op2;
4064
4065 int r1, r2, r3;
4066 int pos1, pos2;
4067
4068 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4069 r1 = MASK_OP_BIT_S1(ctx->opcode);
4070 r2 = MASK_OP_BIT_S2(ctx->opcode);
4071 r3 = MASK_OP_BIT_D(ctx->opcode);
4072 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4073 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4074
4075 switch (op2) {
4076 case OPC2_32_BIT_NAND_T:
4077 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4078 pos1, pos2, &tcg_gen_nand_tl);
4079 break;
4080 case OPC2_32_BIT_ORN_T:
4081 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4082 pos1, pos2, &tcg_gen_orc_tl);
4083 break;
4084 case OPC2_32_BIT_XNOR_T:
4085 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4086 pos1, pos2, &tcg_gen_eqv_tl);
4087 break;
4088 case OPC2_32_BIT_XOR_T:
4089 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4090 pos1, pos2, &tcg_gen_xor_tl);
4091 break;
4092 default:
4093 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4094 }
4095 }
4096
4097 static void decode_bit_orand(DisasContext *ctx)
4098 {
4099 uint32_t op2;
4100
4101 int r1, r2, r3;
4102 int pos1, pos2;
4103
4104 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4105 r1 = MASK_OP_BIT_S1(ctx->opcode);
4106 r2 = MASK_OP_BIT_S2(ctx->opcode);
4107 r3 = MASK_OP_BIT_D(ctx->opcode);
4108 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4109 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4110
4111 switch (op2) {
4112 case OPC2_32_BIT_OR_AND_T:
4113 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4114 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4115 break;
4116 case OPC2_32_BIT_OR_ANDN_T:
4117 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4118 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4119 break;
4120 case OPC2_32_BIT_OR_NOR_T:
4121 if (TCG_TARGET_HAS_orc_i32) {
4122 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4123 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4124 } else {
4125 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4126 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4127 }
4128 break;
4129 case OPC2_32_BIT_OR_OR_T:
4130 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4131 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4132 break;
4133 default:
4134 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4135 }
4136 }
4137
4138 static void decode_bit_sh_logic1(DisasContext *ctx)
4139 {
4140 uint32_t op2;
4141 int r1, r2, r3;
4142 int pos1, pos2;
4143 TCGv temp;
4144
4145 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4146 r1 = MASK_OP_BIT_S1(ctx->opcode);
4147 r2 = MASK_OP_BIT_S2(ctx->opcode);
4148 r3 = MASK_OP_BIT_D(ctx->opcode);
4149 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4150 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4151
4152 temp = tcg_temp_new();
4153
4154 switch (op2) {
4155 case OPC2_32_BIT_SH_AND_T:
4156 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4157 pos1, pos2, &tcg_gen_and_tl);
4158 break;
4159 case OPC2_32_BIT_SH_ANDN_T:
4160 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4161 pos1, pos2, &tcg_gen_andc_tl);
4162 break;
4163 case OPC2_32_BIT_SH_NOR_T:
4164 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4165 pos1, pos2, &tcg_gen_nor_tl);
4166 break;
4167 case OPC2_32_BIT_SH_OR_T:
4168 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4169 pos1, pos2, &tcg_gen_or_tl);
4170 break;
4171 default:
4172 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4173 }
4174 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4175 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4176 }
4177
4178 static void decode_bit_sh_logic2(DisasContext *ctx)
4179 {
4180 uint32_t op2;
4181 int r1, r2, r3;
4182 int pos1, pos2;
4183 TCGv temp;
4184
4185 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4186 r1 = MASK_OP_BIT_S1(ctx->opcode);
4187 r2 = MASK_OP_BIT_S2(ctx->opcode);
4188 r3 = MASK_OP_BIT_D(ctx->opcode);
4189 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4190 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4191
4192 temp = tcg_temp_new();
4193
4194 switch (op2) {
4195 case OPC2_32_BIT_SH_NAND_T:
4196 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4197 pos1, pos2, &tcg_gen_nand_tl);
4198 break;
4199 case OPC2_32_BIT_SH_ORN_T:
4200 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4201 pos1, pos2, &tcg_gen_orc_tl);
4202 break;
4203 case OPC2_32_BIT_SH_XNOR_T:
4204 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4205 pos1, pos2, &tcg_gen_eqv_tl);
4206 break;
4207 case OPC2_32_BIT_SH_XOR_T:
4208 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4209 pos1, pos2, &tcg_gen_xor_tl);
4210 break;
4211 default:
4212 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4213 }
4214 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4215 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4216 }
4217
4218 /* BO-format */
4219
4220
4221 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
4222 {
4223 uint32_t op2;
4224 uint32_t off10;
4225 int32_t r1, r2;
4226 TCGv temp;
4227
4228 r1 = MASK_OP_BO_S1D(ctx->opcode);
4229 r2 = MASK_OP_BO_S2(ctx->opcode);
4230 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4231 op2 = MASK_OP_BO_OP2(ctx->opcode);
4232
4233 switch (op2) {
4234 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4235 case OPC2_32_BO_CACHEA_W_SHORTOFF:
4236 case OPC2_32_BO_CACHEA_I_SHORTOFF:
4237 /* instruction to access the cache */
4238 break;
4239 case OPC2_32_BO_CACHEA_WI_POSTINC:
4240 case OPC2_32_BO_CACHEA_W_POSTINC:
4241 case OPC2_32_BO_CACHEA_I_POSTINC:
4242 /* instruction to access the cache, but we still need to handle
4243 the addressing mode */
4244 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4245 break;
4246 case OPC2_32_BO_CACHEA_WI_PREINC:
4247 case OPC2_32_BO_CACHEA_W_PREINC:
4248 case OPC2_32_BO_CACHEA_I_PREINC:
4249 /* instruction to access the cache, but we still need to handle
4250 the addressing mode */
4251 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4252 break;
4253 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4254 case OPC2_32_BO_CACHEI_W_SHORTOFF:
4255 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
4256 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4257 }
4258 break;
4259 case OPC2_32_BO_CACHEI_W_POSTINC:
4260 case OPC2_32_BO_CACHEI_WI_POSTINC:
4261 if (has_feature(ctx, TRICORE_FEATURE_131)) {
4262 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4263 } else {
4264 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4265 }
4266 break;
4267 case OPC2_32_BO_CACHEI_W_PREINC:
4268 case OPC2_32_BO_CACHEI_WI_PREINC:
4269 if (has_feature(ctx, TRICORE_FEATURE_131)) {
4270 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4271 } else {
4272 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4273 }
4274 break;
4275 case OPC2_32_BO_ST_A_SHORTOFF:
4276 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4277 break;
4278 case OPC2_32_BO_ST_A_POSTINC:
4279 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4280 MO_LESL);
4281 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4282 break;
4283 case OPC2_32_BO_ST_A_PREINC:
4284 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4285 break;
4286 case OPC2_32_BO_ST_B_SHORTOFF:
4287 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4288 break;
4289 case OPC2_32_BO_ST_B_POSTINC:
4290 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4291 MO_UB);
4292 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4293 break;
4294 case OPC2_32_BO_ST_B_PREINC:
4295 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4296 break;
4297 case OPC2_32_BO_ST_D_SHORTOFF:
4298 CHECK_REG_PAIR(r1);
4299 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4300 off10, ctx);
4301 break;
4302 case OPC2_32_BO_ST_D_POSTINC:
4303 CHECK_REG_PAIR(r1);
4304 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4305 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4306 break;
4307 case OPC2_32_BO_ST_D_PREINC:
4308 CHECK_REG_PAIR(r1);
4309 temp = tcg_temp_new();
4310 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4311 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4312 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4313 break;
4314 case OPC2_32_BO_ST_DA_SHORTOFF:
4315 CHECK_REG_PAIR(r1);
4316 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4317 off10, ctx);
4318 break;
4319 case OPC2_32_BO_ST_DA_POSTINC:
4320 CHECK_REG_PAIR(r1);
4321 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4322 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4323 break;
4324 case OPC2_32_BO_ST_DA_PREINC:
4325 CHECK_REG_PAIR(r1);
4326 temp = tcg_temp_new();
4327 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4328 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4329 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4330 break;
4331 case OPC2_32_BO_ST_H_SHORTOFF:
4332 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4333 break;
4334 case OPC2_32_BO_ST_H_POSTINC:
4335 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4336 MO_LEUW);
4337 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4338 break;
4339 case OPC2_32_BO_ST_H_PREINC:
4340 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4341 break;
4342 case OPC2_32_BO_ST_Q_SHORTOFF:
4343 temp = tcg_temp_new();
4344 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4345 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4346 break;
4347 case OPC2_32_BO_ST_Q_POSTINC:
4348 temp = tcg_temp_new();
4349 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4350 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4351 MO_LEUW);
4352 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4353 break;
4354 case OPC2_32_BO_ST_Q_PREINC:
4355 temp = tcg_temp_new();
4356 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4357 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4358 break;
4359 case OPC2_32_BO_ST_W_SHORTOFF:
4360 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4361 break;
4362 case OPC2_32_BO_ST_W_POSTINC:
4363 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4364 MO_LEUL);
4365 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4366 break;
4367 case OPC2_32_BO_ST_W_PREINC:
4368 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4369 break;
4370 default:
4371 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4372 }
4373 }
4374
4375 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
4376 {
4377 uint32_t op2;
4378 uint32_t off10;
4379 int32_t r1, r2;
4380 TCGv temp, temp2, t_off10;
4381
4382 r1 = MASK_OP_BO_S1D(ctx->opcode);
4383 r2 = MASK_OP_BO_S2(ctx->opcode);
4384 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4385 op2 = MASK_OP_BO_OP2(ctx->opcode);
4386
4387 temp = tcg_temp_new();
4388 temp2 = tcg_temp_new();
4389 t_off10 = tcg_constant_i32(off10);
4390 CHECK_REG_PAIR(r2);
4391 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4392 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4393
4394 switch (op2) {
4395 case OPC2_32_BO_CACHEA_WI_BR:
4396 case OPC2_32_BO_CACHEA_W_BR:
4397 case OPC2_32_BO_CACHEA_I_BR:
4398 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4399 break;
4400 case OPC2_32_BO_CACHEA_WI_CIRC:
4401 case OPC2_32_BO_CACHEA_W_CIRC:
4402 case OPC2_32_BO_CACHEA_I_CIRC:
4403 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4404 break;
4405 case OPC2_32_BO_ST_A_BR:
4406 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4407 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4408 break;
4409 case OPC2_32_BO_ST_A_CIRC:
4410 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4411 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4412 break;
4413 case OPC2_32_BO_ST_B_BR:
4414 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4415 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4416 break;
4417 case OPC2_32_BO_ST_B_CIRC:
4418 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4419 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4420 break;
4421 case OPC2_32_BO_ST_D_BR:
4422 CHECK_REG_PAIR(r1);
4423 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4424 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4425 break;
4426 case OPC2_32_BO_ST_D_CIRC:
4427 CHECK_REG_PAIR(r1);
4428 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4429 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4430 tcg_gen_addi_tl(temp, temp, 4);
4431 tcg_gen_rem_tl(temp, temp, temp2);
4432 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4433 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4434 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4435 break;
4436 case OPC2_32_BO_ST_DA_BR:
4437 CHECK_REG_PAIR(r1);
4438 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4439 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4440 break;
4441 case OPC2_32_BO_ST_DA_CIRC:
4442 CHECK_REG_PAIR(r1);
4443 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4444 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4445 tcg_gen_addi_tl(temp, temp, 4);
4446 tcg_gen_rem_tl(temp, temp, temp2);
4447 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4448 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4449 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4450 break;
4451 case OPC2_32_BO_ST_H_BR:
4452 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4453 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4454 break;
4455 case OPC2_32_BO_ST_H_CIRC:
4456 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4457 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4458 break;
4459 case OPC2_32_BO_ST_Q_BR:
4460 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4461 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4462 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4463 break;
4464 case OPC2_32_BO_ST_Q_CIRC:
4465 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4466 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4467 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4468 break;
4469 case OPC2_32_BO_ST_W_BR:
4470 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4471 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4472 break;
4473 case OPC2_32_BO_ST_W_CIRC:
4474 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4475 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4476 break;
4477 default:
4478 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4479 }
4480 }
4481
4482 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
4483 {
4484 uint32_t op2;
4485 uint32_t off10;
4486 int32_t r1, r2;
4487 TCGv temp;
4488
4489 r1 = MASK_OP_BO_S1D(ctx->opcode);
4490 r2 = MASK_OP_BO_S2(ctx->opcode);
4491 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4492 op2 = MASK_OP_BO_OP2(ctx->opcode);
4493
4494 switch (op2) {
4495 case OPC2_32_BO_LD_A_SHORTOFF:
4496 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4497 break;
4498 case OPC2_32_BO_LD_A_POSTINC:
4499 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4500 MO_LEUL);
4501 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4502 break;
4503 case OPC2_32_BO_LD_A_PREINC:
4504 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4505 break;
4506 case OPC2_32_BO_LD_B_SHORTOFF:
4507 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4508 break;
4509 case OPC2_32_BO_LD_B_POSTINC:
4510 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4511 MO_SB);
4512 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4513 break;
4514 case OPC2_32_BO_LD_B_PREINC:
4515 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4516 break;
4517 case OPC2_32_BO_LD_BU_SHORTOFF:
4518 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4519 break;
4520 case OPC2_32_BO_LD_BU_POSTINC:
4521 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4522 MO_UB);
4523 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4524 break;
4525 case OPC2_32_BO_LD_BU_PREINC:
4526 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4527 break;
4528 case OPC2_32_BO_LD_D_SHORTOFF:
4529 CHECK_REG_PAIR(r1);
4530 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4531 off10, ctx);
4532 break;
4533 case OPC2_32_BO_LD_D_POSTINC:
4534 CHECK_REG_PAIR(r1);
4535 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4536 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4537 break;
4538 case OPC2_32_BO_LD_D_PREINC:
4539 CHECK_REG_PAIR(r1);
4540 temp = tcg_temp_new();
4541 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4542 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4543 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4544 break;
4545 case OPC2_32_BO_LD_DA_SHORTOFF:
4546 CHECK_REG_PAIR(r1);
4547 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4548 off10, ctx);
4549 break;
4550 case OPC2_32_BO_LD_DA_POSTINC:
4551 CHECK_REG_PAIR(r1);
4552 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4553 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4554 break;
4555 case OPC2_32_BO_LD_DA_PREINC:
4556 CHECK_REG_PAIR(r1);
4557 temp = tcg_temp_new();
4558 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4559 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4560 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4561 break;
4562 case OPC2_32_BO_LD_H_SHORTOFF:
4563 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4564 break;
4565 case OPC2_32_BO_LD_H_POSTINC:
4566 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4567 MO_LESW);
4568 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4569 break;
4570 case OPC2_32_BO_LD_H_PREINC:
4571 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4572 break;
4573 case OPC2_32_BO_LD_HU_SHORTOFF:
4574 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4575 break;
4576 case OPC2_32_BO_LD_HU_POSTINC:
4577 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4578 MO_LEUW);
4579 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4580 break;
4581 case OPC2_32_BO_LD_HU_PREINC:
4582 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4583 break;
4584 case OPC2_32_BO_LD_Q_SHORTOFF:
4585 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4586 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4587 break;
4588 case OPC2_32_BO_LD_Q_POSTINC:
4589 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4590 MO_LEUW);
4591 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4592 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4593 break;
4594 case OPC2_32_BO_LD_Q_PREINC:
4595 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4596 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4597 break;
4598 case OPC2_32_BO_LD_W_SHORTOFF:
4599 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4600 break;
4601 case OPC2_32_BO_LD_W_POSTINC:
4602 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4603 MO_LEUL);
4604 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4605 break;
4606 case OPC2_32_BO_LD_W_PREINC:
4607 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4608 break;
4609 default:
4610 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4611 }
4612 }
4613
4614 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
4615 {
4616 uint32_t op2;
4617 uint32_t off10;
4618 int r1, r2;
4619 TCGv temp, temp2, t_off10;
4620
4621 r1 = MASK_OP_BO_S1D(ctx->opcode);
4622 r2 = MASK_OP_BO_S2(ctx->opcode);
4623 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4624 op2 = MASK_OP_BO_OP2(ctx->opcode);
4625
4626 temp = tcg_temp_new();
4627 temp2 = tcg_temp_new();
4628 t_off10 = tcg_constant_i32(off10);
4629 CHECK_REG_PAIR(r2);
4630 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4631 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4632
4633
4634 switch (op2) {
4635 case OPC2_32_BO_LD_A_BR:
4636 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4637 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4638 break;
4639 case OPC2_32_BO_LD_A_CIRC:
4640 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4641 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4642 break;
4643 case OPC2_32_BO_LD_B_BR:
4644 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4645 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4646 break;
4647 case OPC2_32_BO_LD_B_CIRC:
4648 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4649 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4650 break;
4651 case OPC2_32_BO_LD_BU_BR:
4652 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4653 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4654 break;
4655 case OPC2_32_BO_LD_BU_CIRC:
4656 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4657 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4658 break;
4659 case OPC2_32_BO_LD_D_BR:
4660 CHECK_REG_PAIR(r1);
4661 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4662 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4663 break;
4664 case OPC2_32_BO_LD_D_CIRC:
4665 CHECK_REG_PAIR(r1);
4666 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4667 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4668 tcg_gen_addi_tl(temp, temp, 4);
4669 tcg_gen_rem_tl(temp, temp, temp2);
4670 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4671 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4672 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4673 break;
4674 case OPC2_32_BO_LD_DA_BR:
4675 CHECK_REG_PAIR(r1);
4676 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4677 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4678 break;
4679 case OPC2_32_BO_LD_DA_CIRC:
4680 CHECK_REG_PAIR(r1);
4681 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4682 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4683 tcg_gen_addi_tl(temp, temp, 4);
4684 tcg_gen_rem_tl(temp, temp, temp2);
4685 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4686 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4687 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4688 break;
4689 case OPC2_32_BO_LD_H_BR:
4690 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4691 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4692 break;
4693 case OPC2_32_BO_LD_H_CIRC:
4694 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4695 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4696 break;
4697 case OPC2_32_BO_LD_HU_BR:
4698 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4699 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4700 break;
4701 case OPC2_32_BO_LD_HU_CIRC:
4702 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4703 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4704 break;
4705 case OPC2_32_BO_LD_Q_BR:
4706 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4707 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4708 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4709 break;
4710 case OPC2_32_BO_LD_Q_CIRC:
4711 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4712 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4713 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4714 break;
4715 case OPC2_32_BO_LD_W_BR:
4716 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4717 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4718 break;
4719 case OPC2_32_BO_LD_W_CIRC:
4720 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4721 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4722 break;
4723 default:
4724 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4725 }
4726 }
4727
4728 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx)
4729 {
4730 uint32_t op2;
4731 uint32_t off10;
4732 int r1, r2;
4733
4734 TCGv temp;
4735
4736 r1 = MASK_OP_BO_S1D(ctx->opcode);
4737 r2 = MASK_OP_BO_S2(ctx->opcode);
4738 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4739 op2 = MASK_OP_BO_OP2(ctx->opcode);
4740
4741
4742 temp = tcg_temp_new();
4743
4744 switch (op2) {
4745 case OPC2_32_BO_LDLCX_SHORTOFF:
4746 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4747 gen_helper_ldlcx(cpu_env, temp);
4748 break;
4749 case OPC2_32_BO_LDMST_SHORTOFF:
4750 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4751 gen_ldmst(ctx, r1, temp);
4752 break;
4753 case OPC2_32_BO_LDMST_POSTINC:
4754 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4755 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4756 break;
4757 case OPC2_32_BO_LDMST_PREINC:
4758 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4759 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4760 break;
4761 case OPC2_32_BO_LDUCX_SHORTOFF:
4762 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4763 gen_helper_lducx(cpu_env, temp);
4764 break;
4765 case OPC2_32_BO_LEA_SHORTOFF:
4766 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
4767 break;
4768 case OPC2_32_BO_STLCX_SHORTOFF:
4769 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4770 gen_helper_stlcx(cpu_env, temp);
4771 break;
4772 case OPC2_32_BO_STUCX_SHORTOFF:
4773 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4774 gen_helper_stucx(cpu_env, temp);
4775 break;
4776 case OPC2_32_BO_SWAP_W_SHORTOFF:
4777 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4778 gen_swap(ctx, r1, temp);
4779 break;
4780 case OPC2_32_BO_SWAP_W_POSTINC:
4781 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4782 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4783 break;
4784 case OPC2_32_BO_SWAP_W_PREINC:
4785 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4786 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4787 break;
4788 case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
4789 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4790 gen_cmpswap(ctx, r1, temp);
4791 break;
4792 case OPC2_32_BO_CMPSWAP_W_POSTINC:
4793 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
4794 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4795 break;
4796 case OPC2_32_BO_CMPSWAP_W_PREINC:
4797 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4798 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
4799 break;
4800 case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
4801 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4802 gen_swapmsk(ctx, r1, temp);
4803 break;
4804 case OPC2_32_BO_SWAPMSK_W_POSTINC:
4805 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
4806 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4807 break;
4808 case OPC2_32_BO_SWAPMSK_W_PREINC:
4809 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4810 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
4811 break;
4812 default:
4813 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4814 }
4815 }
4816
4817 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
4818 {
4819 uint32_t op2;
4820 uint32_t off10;
4821 int r1, r2;
4822 TCGv temp, temp2, t_off10;
4823
4824 r1 = MASK_OP_BO_S1D(ctx->opcode);
4825 r2 = MASK_OP_BO_S2(ctx->opcode);
4826 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4827 op2 = MASK_OP_BO_OP2(ctx->opcode);
4828
4829 temp = tcg_temp_new();
4830 temp2 = tcg_temp_new();
4831 t_off10 = tcg_constant_i32(off10);
4832 CHECK_REG_PAIR(r2);
4833 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4834 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4835
4836 switch (op2) {
4837 case OPC2_32_BO_LDMST_BR:
4838 gen_ldmst(ctx, r1, temp2);
4839 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4840 break;
4841 case OPC2_32_BO_LDMST_CIRC:
4842 gen_ldmst(ctx, r1, temp2);
4843 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4844 break;
4845 case OPC2_32_BO_SWAP_W_BR:
4846 gen_swap(ctx, r1, temp2);
4847 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4848 break;
4849 case OPC2_32_BO_SWAP_W_CIRC:
4850 gen_swap(ctx, r1, temp2);
4851 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4852 break;
4853 case OPC2_32_BO_CMPSWAP_W_BR:
4854 gen_cmpswap(ctx, r1, temp2);
4855 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4856 break;
4857 case OPC2_32_BO_CMPSWAP_W_CIRC:
4858 gen_cmpswap(ctx, r1, temp2);
4859 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4860 break;
4861 case OPC2_32_BO_SWAPMSK_W_BR:
4862 gen_swapmsk(ctx, r1, temp2);
4863 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4864 break;
4865 case OPC2_32_BO_SWAPMSK_W_CIRC:
4866 gen_swapmsk(ctx, r1, temp2);
4867 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4868 break;
4869 default:
4870 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4871 }
4872 }
4873
4874 static void decode_bol_opc(DisasContext *ctx, int32_t op1)
4875 {
4876 int r1, r2;
4877 int32_t address;
4878 TCGv temp;
4879
4880 r1 = MASK_OP_BOL_S1D(ctx->opcode);
4881 r2 = MASK_OP_BOL_S2(ctx->opcode);
4882 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
4883
4884 switch (op1) {
4885 case OPC1_32_BOL_LD_A_LONGOFF:
4886 temp = tcg_temp_new();
4887 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4888 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
4889 break;
4890 case OPC1_32_BOL_LD_W_LONGOFF:
4891 temp = tcg_temp_new();
4892 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4893 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
4894 break;
4895 case OPC1_32_BOL_LEA_LONGOFF:
4896 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
4897 break;
4898 case OPC1_32_BOL_ST_A_LONGOFF:
4899 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4900 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
4901 } else {
4902 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4903 }
4904 break;
4905 case OPC1_32_BOL_ST_W_LONGOFF:
4906 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
4907 break;
4908 case OPC1_32_BOL_LD_B_LONGOFF:
4909 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4910 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4911 } else {
4912 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4913 }
4914 break;
4915 case OPC1_32_BOL_LD_BU_LONGOFF:
4916 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4917 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
4918 } else {
4919 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4920 }
4921 break;
4922 case OPC1_32_BOL_LD_H_LONGOFF:
4923 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4924 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4925 } else {
4926 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4927 }
4928 break;
4929 case OPC1_32_BOL_LD_HU_LONGOFF:
4930 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4931 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
4932 } else {
4933 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4934 }
4935 break;
4936 case OPC1_32_BOL_ST_B_LONGOFF:
4937 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4938 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4939 } else {
4940 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4941 }
4942 break;
4943 case OPC1_32_BOL_ST_H_LONGOFF:
4944 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4945 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4946 } else {
4947 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4948 }
4949 break;
4950 default:
4951 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4952 }
4953 }
4954
4955 /* RC format */
4956 static void decode_rc_logical_shift(DisasContext *ctx)
4957 {
4958 uint32_t op2;
4959 int r1, r2;
4960 int32_t const9;
4961 TCGv temp;
4962
4963 r2 = MASK_OP_RC_D(ctx->opcode);
4964 r1 = MASK_OP_RC_S1(ctx->opcode);
4965 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4966 op2 = MASK_OP_RC_OP2(ctx->opcode);
4967
4968 temp = tcg_temp_new();
4969
4970 switch (op2) {
4971 case OPC2_32_RC_AND:
4972 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4973 break;
4974 case OPC2_32_RC_ANDN:
4975 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4976 break;
4977 case OPC2_32_RC_NAND:
4978 tcg_gen_movi_tl(temp, const9);
4979 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4980 break;
4981 case OPC2_32_RC_NOR:
4982 tcg_gen_movi_tl(temp, const9);
4983 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4984 break;
4985 case OPC2_32_RC_OR:
4986 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4987 break;
4988 case OPC2_32_RC_ORN:
4989 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4990 break;
4991 case OPC2_32_RC_SH:
4992 const9 = sextract32(const9, 0, 6);
4993 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4994 break;
4995 case OPC2_32_RC_SH_H:
4996 const9 = sextract32(const9, 0, 5);
4997 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4998 break;
4999 case OPC2_32_RC_SHA:
5000 const9 = sextract32(const9, 0, 6);
5001 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5002 break;
5003 case OPC2_32_RC_SHA_H:
5004 const9 = sextract32(const9, 0, 5);
5005 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5006 break;
5007 case OPC2_32_RC_SHAS:
5008 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5009 break;
5010 case OPC2_32_RC_XNOR:
5011 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5012 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
5013 break;
5014 case OPC2_32_RC_XOR:
5015 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5016 break;
5017 default:
5018 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5019 }
5020 }
5021
5022 static void decode_rc_accumulator(DisasContext *ctx)
5023 {
5024 uint32_t op2;
5025 int r1, r2;
5026 int16_t const9;
5027
5028 TCGv temp;
5029
5030 r2 = MASK_OP_RC_D(ctx->opcode);
5031 r1 = MASK_OP_RC_S1(ctx->opcode);
5032 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5033
5034 op2 = MASK_OP_RC_OP2(ctx->opcode);
5035
5036 temp = tcg_temp_new();
5037
5038 switch (op2) {
5039 case OPC2_32_RC_ABSDIF:
5040 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5041 break;
5042 case OPC2_32_RC_ABSDIFS:
5043 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5044 break;
5045 case OPC2_32_RC_ADD:
5046 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5047 break;
5048 case OPC2_32_RC_ADDC:
5049 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5050 break;
5051 case OPC2_32_RC_ADDS:
5052 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5053 break;
5054 case OPC2_32_RC_ADDS_U:
5055 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5056 break;
5057 case OPC2_32_RC_ADDX:
5058 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5059 break;
5060 case OPC2_32_RC_AND_EQ:
5061 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5062 const9, &tcg_gen_and_tl);
5063 break;
5064 case OPC2_32_RC_AND_GE:
5065 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5066 const9, &tcg_gen_and_tl);
5067 break;
5068 case OPC2_32_RC_AND_GE_U:
5069 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5070 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5071 const9, &tcg_gen_and_tl);
5072 break;
5073 case OPC2_32_RC_AND_LT:
5074 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5075 const9, &tcg_gen_and_tl);
5076 break;
5077 case OPC2_32_RC_AND_LT_U:
5078 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5079 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5080 const9, &tcg_gen_and_tl);
5081 break;
5082 case OPC2_32_RC_AND_NE:
5083 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5084 const9, &tcg_gen_and_tl);
5085 break;
5086 case OPC2_32_RC_EQ:
5087 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5088 break;
5089 case OPC2_32_RC_EQANY_B:
5090 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5091 break;
5092 case OPC2_32_RC_EQANY_H:
5093 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5094 break;
5095 case OPC2_32_RC_GE:
5096 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5097 break;
5098 case OPC2_32_RC_GE_U:
5099 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5100 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5101 break;
5102 case OPC2_32_RC_LT:
5103 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5104 break;
5105 case OPC2_32_RC_LT_U:
5106 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5107 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5108 break;
5109 case OPC2_32_RC_MAX:
5110 tcg_gen_movi_tl(temp, const9);
5111 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5112 cpu_gpr_d[r1], temp);
5113 break;
5114 case OPC2_32_RC_MAX_U:
5115 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5116 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5117 cpu_gpr_d[r1], temp);
5118 break;
5119 case OPC2_32_RC_MIN:
5120 tcg_gen_movi_tl(temp, const9);
5121 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5122 cpu_gpr_d[r1], temp);
5123 break;
5124 case OPC2_32_RC_MIN_U:
5125 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5126 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5127 cpu_gpr_d[r1], temp);
5128 break;
5129 case OPC2_32_RC_NE:
5130 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5131 break;
5132 case OPC2_32_RC_OR_EQ:
5133 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5134 const9, &tcg_gen_or_tl);
5135 break;
5136 case OPC2_32_RC_OR_GE:
5137 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5138 const9, &tcg_gen_or_tl);
5139 break;
5140 case OPC2_32_RC_OR_GE_U:
5141 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5142 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5143 const9, &tcg_gen_or_tl);
5144 break;
5145 case OPC2_32_RC_OR_LT:
5146 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5147 const9, &tcg_gen_or_tl);
5148 break;
5149 case OPC2_32_RC_OR_LT_U:
5150 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5151 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5152 const9, &tcg_gen_or_tl);
5153 break;
5154 case OPC2_32_RC_OR_NE:
5155 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5156 const9, &tcg_gen_or_tl);
5157 break;
5158 case OPC2_32_RC_RSUB:
5159 tcg_gen_movi_tl(temp, const9);
5160 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5161 break;
5162 case OPC2_32_RC_RSUBS:
5163 tcg_gen_movi_tl(temp, const9);
5164 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5165 break;
5166 case OPC2_32_RC_RSUBS_U:
5167 tcg_gen_movi_tl(temp, const9);
5168 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5169 break;
5170 case OPC2_32_RC_SH_EQ:
5171 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5172 break;
5173 case OPC2_32_RC_SH_GE:
5174 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5175 break;
5176 case OPC2_32_RC_SH_GE_U:
5177 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5178 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5179 break;
5180 case OPC2_32_RC_SH_LT:
5181 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5182 break;
5183 case OPC2_32_RC_SH_LT_U:
5184 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5185 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5186 break;
5187 case OPC2_32_RC_SH_NE:
5188 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5189 break;
5190 case OPC2_32_RC_XOR_EQ:
5191 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5192 const9, &tcg_gen_xor_tl);
5193 break;
5194 case OPC2_32_RC_XOR_GE:
5195 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5196 const9, &tcg_gen_xor_tl);
5197 break;
5198 case OPC2_32_RC_XOR_GE_U:
5199 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5200 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5201 const9, &tcg_gen_xor_tl);
5202 break;
5203 case OPC2_32_RC_XOR_LT:
5204 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5205 const9, &tcg_gen_xor_tl);
5206 break;
5207 case OPC2_32_RC_XOR_LT_U:
5208 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5209 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5210 const9, &tcg_gen_xor_tl);
5211 break;
5212 case OPC2_32_RC_XOR_NE:
5213 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5214 const9, &tcg_gen_xor_tl);
5215 break;
5216 default:
5217 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5218 }
5219 }
5220
5221 static void decode_rc_serviceroutine(DisasContext *ctx)
5222 {
5223 uint32_t op2;
5224 uint32_t const9;
5225
5226 op2 = MASK_OP_RC_OP2(ctx->opcode);
5227 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5228
5229 switch (op2) {
5230 case OPC2_32_RC_BISR:
5231 gen_helper_1arg(bisr, const9);
5232 break;
5233 case OPC2_32_RC_SYSCALL:
5234 /* TODO: Add exception generation */
5235 break;
5236 default:
5237 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5238 }
5239 }
5240
5241 static void decode_rc_mul(DisasContext *ctx)
5242 {
5243 uint32_t op2;
5244 int r1, r2;
5245 int16_t const9;
5246
5247 r2 = MASK_OP_RC_D(ctx->opcode);
5248 r1 = MASK_OP_RC_S1(ctx->opcode);
5249 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5250
5251 op2 = MASK_OP_RC_OP2(ctx->opcode);
5252
5253 switch (op2) {
5254 case OPC2_32_RC_MUL_32:
5255 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5256 break;
5257 case OPC2_32_RC_MUL_64:
5258 CHECK_REG_PAIR(r2);
5259 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5260 break;
5261 case OPC2_32_RC_MULS_32:
5262 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5263 break;
5264 case OPC2_32_RC_MUL_U_64:
5265 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5266 CHECK_REG_PAIR(r2);
5267 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5268 break;
5269 case OPC2_32_RC_MULS_U_32:
5270 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5271 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5272 break;
5273 default:
5274 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5275 }
5276 }
5277
5278 /* RCPW format */
5279 static void decode_rcpw_insert(DisasContext *ctx)
5280 {
5281 uint32_t op2;
5282 int r1, r2;
5283 int32_t pos, width, const4;
5284
5285 TCGv temp;
5286
5287 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
5288 r1 = MASK_OP_RCPW_S1(ctx->opcode);
5289 r2 = MASK_OP_RCPW_D(ctx->opcode);
5290 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
5291 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
5292 pos = MASK_OP_RCPW_POS(ctx->opcode);
5293
5294 switch (op2) {
5295 case OPC2_32_RCPW_IMASK:
5296 CHECK_REG_PAIR(r2);
5297 /* if pos + width > 32 undefined result */
5298 if (pos + width <= 32) {
5299 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
5300 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
5301 }
5302 break;
5303 case OPC2_32_RCPW_INSERT:
5304 /* if pos + width > 32 undefined result */
5305 if (pos + width <= 32) {
5306 temp = tcg_const_i32(const4);
5307 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
5308 }
5309 break;
5310 default:
5311 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5312 }
5313 }
5314
5315 /* RCRW format */
5316
5317 static void decode_rcrw_insert(DisasContext *ctx)
5318 {
5319 uint32_t op2;
5320 int r1, r3, r4;
5321 int32_t width, const4;
5322
5323 TCGv temp, temp2, temp3;
5324
5325 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
5326 r1 = MASK_OP_RCRW_S1(ctx->opcode);
5327 r3 = MASK_OP_RCRW_S3(ctx->opcode);
5328 r4 = MASK_OP_RCRW_D(ctx->opcode);
5329 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
5330 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
5331
5332 temp = tcg_temp_new();
5333 temp2 = tcg_temp_new();
5334
5335 switch (op2) {
5336 case OPC2_32_RCRW_IMASK:
5337 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
5338 tcg_gen_movi_tl(temp2, (1 << width) - 1);
5339 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
5340 tcg_gen_movi_tl(temp2, const4);
5341 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
5342 break;
5343 case OPC2_32_RCRW_INSERT:
5344 temp3 = tcg_temp_new();
5345
5346 tcg_gen_movi_tl(temp, width);
5347 tcg_gen_movi_tl(temp2, const4);
5348 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
5349 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
5350 break;
5351 default:
5352 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5353 }
5354 }
5355
5356 /* RCR format */
5357
5358 static void decode_rcr_cond_select(DisasContext *ctx)
5359 {
5360 uint32_t op2;
5361 int r1, r3, r4;
5362 int32_t const9;
5363
5364 TCGv temp, temp2;
5365
5366 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5367 r1 = MASK_OP_RCR_S1(ctx->opcode);
5368 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5369 r3 = MASK_OP_RCR_S3(ctx->opcode);
5370 r4 = MASK_OP_RCR_D(ctx->opcode);
5371
5372 switch (op2) {
5373 case OPC2_32_RCR_CADD:
5374 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
5375 cpu_gpr_d[r3]);
5376 break;
5377 case OPC2_32_RCR_CADDN:
5378 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
5379 cpu_gpr_d[r3]);
5380 break;
5381 case OPC2_32_RCR_SEL:
5382 temp = tcg_const_i32(0);
5383 temp2 = tcg_const_i32(const9);
5384 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5385 cpu_gpr_d[r1], temp2);
5386 break;
5387 case OPC2_32_RCR_SELN:
5388 temp = tcg_const_i32(0);
5389 temp2 = tcg_const_i32(const9);
5390 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5391 cpu_gpr_d[r1], temp2);
5392 break;
5393 default:
5394 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5395 }
5396 }
5397
5398 static void decode_rcr_madd(DisasContext *ctx)
5399 {
5400 uint32_t op2;
5401 int r1, r3, r4;
5402 int32_t const9;
5403
5404
5405 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5406 r1 = MASK_OP_RCR_S1(ctx->opcode);
5407 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5408 r3 = MASK_OP_RCR_S3(ctx->opcode);
5409 r4 = MASK_OP_RCR_D(ctx->opcode);
5410
5411 switch (op2) {
5412 case OPC2_32_RCR_MADD_32:
5413 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5414 break;
5415 case OPC2_32_RCR_MADD_64:
5416 CHECK_REG_PAIR(r4);
5417 CHECK_REG_PAIR(r3);
5418 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5419 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5420 break;
5421 case OPC2_32_RCR_MADDS_32:
5422 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5423 break;
5424 case OPC2_32_RCR_MADDS_64:
5425 CHECK_REG_PAIR(r4);
5426 CHECK_REG_PAIR(r3);
5427 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5428 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5429 break;
5430 case OPC2_32_RCR_MADD_U_64:
5431 CHECK_REG_PAIR(r4);
5432 CHECK_REG_PAIR(r3);
5433 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5434 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5435 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5436 break;
5437 case OPC2_32_RCR_MADDS_U_32:
5438 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5439 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5440 break;
5441 case OPC2_32_RCR_MADDS_U_64:
5442 CHECK_REG_PAIR(r4);
5443 CHECK_REG_PAIR(r3);
5444 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5445 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5446 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5447 break;
5448 default:
5449 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5450 }
5451 }
5452
5453 static void decode_rcr_msub(DisasContext *ctx)
5454 {
5455 uint32_t op2;
5456 int r1, r3, r4;
5457 int32_t const9;
5458
5459
5460 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5461 r1 = MASK_OP_RCR_S1(ctx->opcode);
5462 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5463 r3 = MASK_OP_RCR_S3(ctx->opcode);
5464 r4 = MASK_OP_RCR_D(ctx->opcode);
5465
5466 switch (op2) {
5467 case OPC2_32_RCR_MSUB_32:
5468 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5469 break;
5470 case OPC2_32_RCR_MSUB_64:
5471 CHECK_REG_PAIR(r4);
5472 CHECK_REG_PAIR(r3);
5473 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5474 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5475 break;
5476 case OPC2_32_RCR_MSUBS_32:
5477 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5478 break;
5479 case OPC2_32_RCR_MSUBS_64:
5480 CHECK_REG_PAIR(r4);
5481 CHECK_REG_PAIR(r3);
5482 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5483 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5484 break;
5485 case OPC2_32_RCR_MSUB_U_64:
5486 CHECK_REG_PAIR(r4);
5487 CHECK_REG_PAIR(r3);
5488 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5489 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5490 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5491 break;
5492 case OPC2_32_RCR_MSUBS_U_32:
5493 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5494 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5495 break;
5496 case OPC2_32_RCR_MSUBS_U_64:
5497 CHECK_REG_PAIR(r4);
5498 CHECK_REG_PAIR(r3);
5499 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5500 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5501 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5502 break;
5503 default:
5504 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5505 }
5506 }
5507
5508 /* RLC format */
5509
5510 static void decode_rlc_opc(DisasContext *ctx,
5511 uint32_t op1)
5512 {
5513 int32_t const16;
5514 int r1, r2;
5515
5516 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
5517 r1 = MASK_OP_RLC_S1(ctx->opcode);
5518 r2 = MASK_OP_RLC_D(ctx->opcode);
5519
5520 switch (op1) {
5521 case OPC1_32_RLC_ADDI:
5522 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
5523 break;
5524 case OPC1_32_RLC_ADDIH:
5525 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
5526 break;
5527 case OPC1_32_RLC_ADDIH_A:
5528 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
5529 break;
5530 case OPC1_32_RLC_MFCR:
5531 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5532 gen_mfcr(ctx, cpu_gpr_d[r2], const16);
5533 break;
5534 case OPC1_32_RLC_MOV:
5535 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5536 break;
5537 case OPC1_32_RLC_MOV_64:
5538 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5539 CHECK_REG_PAIR(r2);
5540 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5541 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
5542 } else {
5543 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5544 }
5545 break;
5546 case OPC1_32_RLC_MOV_U:
5547 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5548 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5549 break;
5550 case OPC1_32_RLC_MOV_H:
5551 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
5552 break;
5553 case OPC1_32_RLC_MOVH_A:
5554 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
5555 break;
5556 case OPC1_32_RLC_MTCR:
5557 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5558 gen_mtcr(ctx, cpu_gpr_d[r1], const16);
5559 break;
5560 default:
5561 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5562 }
5563 }
5564
5565 /* RR format */
5566 static void decode_rr_accumulator(DisasContext *ctx)
5567 {
5568 uint32_t op2;
5569 int r3, r2, r1;
5570
5571 TCGv temp;
5572
5573 r3 = MASK_OP_RR_D(ctx->opcode);
5574 r2 = MASK_OP_RR_S2(ctx->opcode);
5575 r1 = MASK_OP_RR_S1(ctx->opcode);
5576 op2 = MASK_OP_RR_OP2(ctx->opcode);
5577
5578 switch (op2) {
5579 case OPC2_32_RR_ABS:
5580 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5581 break;
5582 case OPC2_32_RR_ABS_B:
5583 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5584 break;
5585 case OPC2_32_RR_ABS_H:
5586 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5587 break;
5588 case OPC2_32_RR_ABSDIF:
5589 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5590 break;
5591 case OPC2_32_RR_ABSDIF_B:
5592 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5593 cpu_gpr_d[r2]);
5594 break;
5595 case OPC2_32_RR_ABSDIF_H:
5596 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5597 cpu_gpr_d[r2]);
5598 break;
5599 case OPC2_32_RR_ABSDIFS:
5600 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5601 cpu_gpr_d[r2]);
5602 break;
5603 case OPC2_32_RR_ABSDIFS_H:
5604 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5605 cpu_gpr_d[r2]);
5606 break;
5607 case OPC2_32_RR_ABSS:
5608 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5609 break;
5610 case OPC2_32_RR_ABSS_H:
5611 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5612 break;
5613 case OPC2_32_RR_ADD:
5614 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5615 break;
5616 case OPC2_32_RR_ADD_B:
5617 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5618 break;
5619 case OPC2_32_RR_ADD_H:
5620 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5621 break;
5622 case OPC2_32_RR_ADDC:
5623 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5624 break;
5625 case OPC2_32_RR_ADDS:
5626 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5627 break;
5628 case OPC2_32_RR_ADDS_H:
5629 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5630 cpu_gpr_d[r2]);
5631 break;
5632 case OPC2_32_RR_ADDS_HU:
5633 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5634 cpu_gpr_d[r2]);
5635 break;
5636 case OPC2_32_RR_ADDS_U:
5637 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5638 cpu_gpr_d[r2]);
5639 break;
5640 case OPC2_32_RR_ADDX:
5641 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5642 break;
5643 case OPC2_32_RR_AND_EQ:
5644 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5645 cpu_gpr_d[r2], &tcg_gen_and_tl);
5646 break;
5647 case OPC2_32_RR_AND_GE:
5648 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5649 cpu_gpr_d[r2], &tcg_gen_and_tl);
5650 break;
5651 case OPC2_32_RR_AND_GE_U:
5652 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5653 cpu_gpr_d[r2], &tcg_gen_and_tl);
5654 break;
5655 case OPC2_32_RR_AND_LT:
5656 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5657 cpu_gpr_d[r2], &tcg_gen_and_tl);
5658 break;
5659 case OPC2_32_RR_AND_LT_U:
5660 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5661 cpu_gpr_d[r2], &tcg_gen_and_tl);
5662 break;
5663 case OPC2_32_RR_AND_NE:
5664 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5665 cpu_gpr_d[r2], &tcg_gen_and_tl);
5666 break;
5667 case OPC2_32_RR_EQ:
5668 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5669 cpu_gpr_d[r2]);
5670 break;
5671 case OPC2_32_RR_EQ_B:
5672 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5673 break;
5674 case OPC2_32_RR_EQ_H:
5675 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5676 break;
5677 case OPC2_32_RR_EQ_W:
5678 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5679 break;
5680 case OPC2_32_RR_EQANY_B:
5681 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5682 break;
5683 case OPC2_32_RR_EQANY_H:
5684 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5685 break;
5686 case OPC2_32_RR_GE:
5687 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5688 cpu_gpr_d[r2]);
5689 break;
5690 case OPC2_32_RR_GE_U:
5691 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5692 cpu_gpr_d[r2]);
5693 break;
5694 case OPC2_32_RR_LT:
5695 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5696 cpu_gpr_d[r2]);
5697 break;
5698 case OPC2_32_RR_LT_U:
5699 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5700 cpu_gpr_d[r2]);
5701 break;
5702 case OPC2_32_RR_LT_B:
5703 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5704 break;
5705 case OPC2_32_RR_LT_BU:
5706 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5707 break;
5708 case OPC2_32_RR_LT_H:
5709 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5710 break;
5711 case OPC2_32_RR_LT_HU:
5712 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5713 break;
5714 case OPC2_32_RR_LT_W:
5715 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5716 break;
5717 case OPC2_32_RR_LT_WU:
5718 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5719 break;
5720 case OPC2_32_RR_MAX:
5721 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5722 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5723 break;
5724 case OPC2_32_RR_MAX_U:
5725 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5726 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5727 break;
5728 case OPC2_32_RR_MAX_B:
5729 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5730 break;
5731 case OPC2_32_RR_MAX_BU:
5732 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5733 break;
5734 case OPC2_32_RR_MAX_H:
5735 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5736 break;
5737 case OPC2_32_RR_MAX_HU:
5738 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5739 break;
5740 case OPC2_32_RR_MIN:
5741 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5742 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5743 break;
5744 case OPC2_32_RR_MIN_U:
5745 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5746 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5747 break;
5748 case OPC2_32_RR_MIN_B:
5749 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5750 break;
5751 case OPC2_32_RR_MIN_BU:
5752 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5753 break;
5754 case OPC2_32_RR_MIN_H:
5755 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5756 break;
5757 case OPC2_32_RR_MIN_HU:
5758 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5759 break;
5760 case OPC2_32_RR_MOV:
5761 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5762 break;
5763 case OPC2_32_RR_MOV_64:
5764 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5765 temp = tcg_temp_new();
5766
5767 CHECK_REG_PAIR(r3);
5768 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
5769 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5770 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
5771 } else {
5772 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5773 }
5774 break;
5775 case OPC2_32_RR_MOVS_64:
5776 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5777 CHECK_REG_PAIR(r3);
5778 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5779 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
5780 } else {
5781 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5782 }
5783 break;
5784 case OPC2_32_RR_NE:
5785 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5786 cpu_gpr_d[r2]);
5787 break;
5788 case OPC2_32_RR_OR_EQ:
5789 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5790 cpu_gpr_d[r2], &tcg_gen_or_tl);
5791 break;
5792 case OPC2_32_RR_OR_GE:
5793 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5794 cpu_gpr_d[r2], &tcg_gen_or_tl);
5795 break;
5796 case OPC2_32_RR_OR_GE_U:
5797 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5798 cpu_gpr_d[r2], &tcg_gen_or_tl);
5799 break;
5800 case OPC2_32_RR_OR_LT:
5801 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5802 cpu_gpr_d[r2], &tcg_gen_or_tl);
5803 break;
5804 case OPC2_32_RR_OR_LT_U:
5805 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5806 cpu_gpr_d[r2], &tcg_gen_or_tl);
5807 break;
5808 case OPC2_32_RR_OR_NE:
5809 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5810 cpu_gpr_d[r2], &tcg_gen_or_tl);
5811 break;
5812 case OPC2_32_RR_SAT_B:
5813 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
5814 break;
5815 case OPC2_32_RR_SAT_BU:
5816 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
5817 break;
5818 case OPC2_32_RR_SAT_H:
5819 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
5820 break;
5821 case OPC2_32_RR_SAT_HU:
5822 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
5823 break;
5824 case OPC2_32_RR_SH_EQ:
5825 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5826 cpu_gpr_d[r2]);
5827 break;
5828 case OPC2_32_RR_SH_GE:
5829 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5830 cpu_gpr_d[r2]);
5831 break;
5832 case OPC2_32_RR_SH_GE_U:
5833 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5834 cpu_gpr_d[r2]);
5835 break;
5836 case OPC2_32_RR_SH_LT:
5837 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5838 cpu_gpr_d[r2]);
5839 break;
5840 case OPC2_32_RR_SH_LT_U:
5841 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5842 cpu_gpr_d[r2]);
5843 break;
5844 case OPC2_32_RR_SH_NE:
5845 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5846 cpu_gpr_d[r2]);
5847 break;
5848 case OPC2_32_RR_SUB:
5849 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5850 break;
5851 case OPC2_32_RR_SUB_B:
5852 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5853 break;
5854 case OPC2_32_RR_SUB_H:
5855 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5856 break;
5857 case OPC2_32_RR_SUBC:
5858 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5859 break;
5860 case OPC2_32_RR_SUBS:
5861 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5862 break;
5863 case OPC2_32_RR_SUBS_U:
5864 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5865 break;
5866 case OPC2_32_RR_SUBS_H:
5867 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5868 cpu_gpr_d[r2]);
5869 break;
5870 case OPC2_32_RR_SUBS_HU:
5871 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5872 cpu_gpr_d[r2]);
5873 break;
5874 case OPC2_32_RR_SUBX:
5875 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5876 break;
5877 case OPC2_32_RR_XOR_EQ:
5878 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5879 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5880 break;
5881 case OPC2_32_RR_XOR_GE:
5882 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5883 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5884 break;
5885 case OPC2_32_RR_XOR_GE_U:
5886 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5887 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5888 break;
5889 case OPC2_32_RR_XOR_LT:
5890 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5891 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5892 break;
5893 case OPC2_32_RR_XOR_LT_U:
5894 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5895 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5896 break;
5897 case OPC2_32_RR_XOR_NE:
5898 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5899 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5900 break;
5901 default:
5902 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5903 }
5904 }
5905
5906 static void decode_rr_logical_shift(DisasContext *ctx)
5907 {
5908 uint32_t op2;
5909 int r3, r2, r1;
5910
5911 r3 = MASK_OP_RR_D(ctx->opcode);
5912 r2 = MASK_OP_RR_S2(ctx->opcode);
5913 r1 = MASK_OP_RR_S1(ctx->opcode);
5914 op2 = MASK_OP_RR_OP2(ctx->opcode);
5915
5916 switch (op2) {
5917 case OPC2_32_RR_AND:
5918 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5919 break;
5920 case OPC2_32_RR_ANDN:
5921 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5922 break;
5923 case OPC2_32_RR_CLO:
5924 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5925 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
5926 break;
5927 case OPC2_32_RR_CLO_H:
5928 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5929 break;
5930 case OPC2_32_RR_CLS:
5931 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5932 break;
5933 case OPC2_32_RR_CLS_H:
5934 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5935 break;
5936 case OPC2_32_RR_CLZ:
5937 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
5938 break;
5939 case OPC2_32_RR_CLZ_H:
5940 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5941 break;
5942 case OPC2_32_RR_NAND:
5943 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5944 break;
5945 case OPC2_32_RR_NOR:
5946 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5947 break;
5948 case OPC2_32_RR_OR:
5949 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5950 break;
5951 case OPC2_32_RR_ORN:
5952 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5953 break;
5954 case OPC2_32_RR_SH:
5955 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5956 break;
5957 case OPC2_32_RR_SH_H:
5958 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5959 break;
5960 case OPC2_32_RR_SHA:
5961 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5962 break;
5963 case OPC2_32_RR_SHA_H:
5964 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5965 break;
5966 case OPC2_32_RR_SHAS:
5967 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5968 break;
5969 case OPC2_32_RR_XNOR:
5970 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5971 break;
5972 case OPC2_32_RR_XOR:
5973 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5974 break;
5975 default:
5976 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5977 }
5978 }
5979
5980 static void decode_rr_address(DisasContext *ctx)
5981 {
5982 uint32_t op2, n;
5983 int r1, r2, r3;
5984 TCGv temp;
5985
5986 op2 = MASK_OP_RR_OP2(ctx->opcode);
5987 r3 = MASK_OP_RR_D(ctx->opcode);
5988 r2 = MASK_OP_RR_S2(ctx->opcode);
5989 r1 = MASK_OP_RR_S1(ctx->opcode);
5990 n = MASK_OP_RR_N(ctx->opcode);
5991
5992 switch (op2) {
5993 case OPC2_32_RR_ADD_A:
5994 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
5995 break;
5996 case OPC2_32_RR_ADDSC_A:
5997 temp = tcg_temp_new();
5998 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
5999 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
6000 break;
6001 case OPC2_32_RR_ADDSC_AT:
6002 temp = tcg_temp_new();
6003 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
6004 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
6005 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
6006 break;
6007 case OPC2_32_RR_EQ_A:
6008 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
6009 cpu_gpr_a[r2]);
6010 break;
6011 case OPC2_32_RR_EQZ:
6012 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6013 break;
6014 case OPC2_32_RR_GE_A:
6015 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6016 cpu_gpr_a[r2]);
6017 break;
6018 case OPC2_32_RR_LT_A:
6019 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6020 cpu_gpr_a[r2]);
6021 break;
6022 case OPC2_32_RR_MOV_A:
6023 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
6024 break;
6025 case OPC2_32_RR_MOV_AA:
6026 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
6027 break;
6028 case OPC2_32_RR_MOV_D:
6029 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
6030 break;
6031 case OPC2_32_RR_NE_A:
6032 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
6033 cpu_gpr_a[r2]);
6034 break;
6035 case OPC2_32_RR_NEZ_A:
6036 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6037 break;
6038 case OPC2_32_RR_SUB_A:
6039 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6040 break;
6041 default:
6042 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6043 }
6044 }
6045
6046 static void decode_rr_idirect(DisasContext *ctx)
6047 {
6048 uint32_t op2;
6049 int r1;
6050
6051 op2 = MASK_OP_RR_OP2(ctx->opcode);
6052 r1 = MASK_OP_RR_S1(ctx->opcode);
6053
6054 switch (op2) {
6055 case OPC2_32_RR_JI:
6056 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6057 break;
6058 case OPC2_32_RR_JLI:
6059 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
6060 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6061 break;
6062 case OPC2_32_RR_CALLI:
6063 gen_helper_1arg(call, ctx->pc_succ_insn);
6064 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6065 break;
6066 case OPC2_32_RR_FCALLI:
6067 gen_fcall_save_ctx(ctx);
6068 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6069 break;
6070 default:
6071 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6072 }
6073 tcg_gen_exit_tb(NULL, 0);
6074 ctx->base.is_jmp = DISAS_NORETURN;
6075 }
6076
6077 static void decode_rr_divide(DisasContext *ctx)
6078 {
6079 uint32_t op2;
6080 int r1, r2, r3;
6081
6082 TCGv temp, temp2, temp3;
6083
6084 op2 = MASK_OP_RR_OP2(ctx->opcode);
6085 r3 = MASK_OP_RR_D(ctx->opcode);
6086 r2 = MASK_OP_RR_S2(ctx->opcode);
6087 r1 = MASK_OP_RR_S1(ctx->opcode);
6088
6089 switch (op2) {
6090 case OPC2_32_RR_BMERGE:
6091 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6092 break;
6093 case OPC2_32_RR_BSPLIT:
6094 CHECK_REG_PAIR(r3);
6095 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6096 break;
6097 case OPC2_32_RR_DVINIT_B:
6098 CHECK_REG_PAIR(r3);
6099 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6100 cpu_gpr_d[r2]);
6101 break;
6102 case OPC2_32_RR_DVINIT_BU:
6103 temp = tcg_temp_new();
6104 temp2 = tcg_temp_new();
6105 temp3 = tcg_temp_new();
6106 CHECK_REG_PAIR(r3);
6107 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
6108 /* reset av */
6109 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6110 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
6111 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6112 tcg_gen_abs_tl(temp, temp3);
6113 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
6114 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6115 } else {
6116 /* overflow = (D[b] == 0) */
6117 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6118 }
6119 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6120 /* sv */
6121 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6122 /* write result */
6123 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
6124 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6125 break;
6126 case OPC2_32_RR_DVINIT_H:
6127 CHECK_REG_PAIR(r3);
6128 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6129 cpu_gpr_d[r2]);
6130 break;
6131 case OPC2_32_RR_DVINIT_HU:
6132 temp = tcg_temp_new();
6133 temp2 = tcg_temp_new();
6134 temp3 = tcg_temp_new();
6135 CHECK_REG_PAIR(r3);
6136 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
6137 /* reset av */
6138 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6139 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
6140 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6141 tcg_gen_abs_tl(temp, temp3);
6142 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
6143 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6144 } else {
6145 /* overflow = (D[b] == 0) */
6146 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6147 }
6148 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6149 /* sv */
6150 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6151 /* write result */
6152 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
6153 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6154 break;
6155 case OPC2_32_RR_DVINIT:
6156 temp = tcg_temp_new();
6157 temp2 = tcg_temp_new();
6158 CHECK_REG_PAIR(r3);
6159 /* overflow = ((D[b] == 0) ||
6160 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6161 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
6162 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
6163 tcg_gen_and_tl(temp, temp, temp2);
6164 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
6165 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
6166 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6167 /* sv */
6168 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6169 /* reset av */
6170 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6171 /* write result */
6172 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6173 /* sign extend to high reg */
6174 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
6175 break;
6176 case OPC2_32_RR_DVINIT_U:
6177 /* overflow = (D[b] == 0) */
6178 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6179 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6180 /* sv */
6181 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6182 /* reset av */
6183 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6184 /* write result */
6185 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6186 /* zero extend to high reg*/
6187 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
6188 break;
6189 case OPC2_32_RR_PARITY:
6190 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6191 break;
6192 case OPC2_32_RR_UNPACK:
6193 CHECK_REG_PAIR(r3);
6194 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6195 break;
6196 case OPC2_32_RR_CRC32:
6197 if (has_feature(ctx, TRICORE_FEATURE_161)) {
6198 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6199 } else {
6200 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6201 }
6202 break;
6203 case OPC2_32_RR_DIV:
6204 if (has_feature(ctx, TRICORE_FEATURE_16)) {
6205 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6206 cpu_gpr_d[r2]);
6207 } else {
6208 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6209 }
6210 break;
6211 case OPC2_32_RR_DIV_U:
6212 if (has_feature(ctx, TRICORE_FEATURE_16)) {
6213 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6214 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6215 } else {
6216 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6217 }
6218 break;
6219 case OPC2_32_RR_MUL_F:
6220 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6221 break;
6222 case OPC2_32_RR_DIV_F:
6223 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6224 break;
6225 case OPC2_32_RR_CMP_F:
6226 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6227 break;
6228 case OPC2_32_RR_FTOI:
6229 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6230 break;
6231 case OPC2_32_RR_ITOF:
6232 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6233 break;
6234 case OPC2_32_RR_FTOUZ:
6235 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6236 break;
6237 case OPC2_32_RR_UPDFL:
6238 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
6239 break;
6240 case OPC2_32_RR_UTOF:
6241 gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6242 break;
6243 case OPC2_32_RR_FTOIZ:
6244 gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6245 break;
6246 case OPC2_32_RR_QSEED_F:
6247 gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6248 break;
6249 default:
6250 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6251 }
6252 }
6253
6254 /* RR1 Format */
6255 static void decode_rr1_mul(DisasContext *ctx)
6256 {
6257 uint32_t op2;
6258
6259 int r1, r2, r3;
6260 TCGv n;
6261 TCGv_i64 temp64;
6262
6263 r1 = MASK_OP_RR1_S1(ctx->opcode);
6264 r2 = MASK_OP_RR1_S2(ctx->opcode);
6265 r3 = MASK_OP_RR1_D(ctx->opcode);
6266 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
6267 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6268
6269 switch (op2) {
6270 case OPC2_32_RR1_MUL_H_32_LL:
6271 temp64 = tcg_temp_new_i64();
6272 CHECK_REG_PAIR(r3);
6273 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6274 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6275 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6276 break;
6277 case OPC2_32_RR1_MUL_H_32_LU:
6278 temp64 = tcg_temp_new_i64();
6279 CHECK_REG_PAIR(r3);
6280 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6281 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6282 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6283 break;
6284 case OPC2_32_RR1_MUL_H_32_UL:
6285 temp64 = tcg_temp_new_i64();
6286 CHECK_REG_PAIR(r3);
6287 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6288 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6289 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6290 break;
6291 case OPC2_32_RR1_MUL_H_32_UU:
6292 temp64 = tcg_temp_new_i64();
6293 CHECK_REG_PAIR(r3);
6294 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6295 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6296 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6297 break;
6298 case OPC2_32_RR1_MULM_H_64_LL:
6299 temp64 = tcg_temp_new_i64();
6300 CHECK_REG_PAIR(r3);
6301 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6302 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6303 /* reset V bit */
6304 tcg_gen_movi_tl(cpu_PSW_V, 0);
6305 /* reset AV bit */
6306 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6307 break;
6308 case OPC2_32_RR1_MULM_H_64_LU:
6309 temp64 = tcg_temp_new_i64();
6310 CHECK_REG_PAIR(r3);
6311 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6312 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6313 /* reset V bit */
6314 tcg_gen_movi_tl(cpu_PSW_V, 0);
6315 /* reset AV bit */
6316 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6317 break;
6318 case OPC2_32_RR1_MULM_H_64_UL:
6319 temp64 = tcg_temp_new_i64();
6320 CHECK_REG_PAIR(r3);
6321 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6322 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6323 /* reset V bit */
6324 tcg_gen_movi_tl(cpu_PSW_V, 0);
6325 /* reset AV bit */
6326 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6327 break;
6328 case OPC2_32_RR1_MULM_H_64_UU:
6329 temp64 = tcg_temp_new_i64();
6330 CHECK_REG_PAIR(r3);
6331 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6332 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6333 /* reset V bit */
6334 tcg_gen_movi_tl(cpu_PSW_V, 0);
6335 /* reset AV bit */
6336 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6337 break;
6338 case OPC2_32_RR1_MULR_H_16_LL:
6339 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6340 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6341 break;
6342 case OPC2_32_RR1_MULR_H_16_LU:
6343 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6344 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6345 break;
6346 case OPC2_32_RR1_MULR_H_16_UL:
6347 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6348 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6349 break;
6350 case OPC2_32_RR1_MULR_H_16_UU:
6351 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6352 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6353 break;
6354 default:
6355 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6356 }
6357 }
6358
6359 static void decode_rr1_mulq(DisasContext *ctx)
6360 {
6361 uint32_t op2;
6362 int r1, r2, r3;
6363 uint32_t n;
6364
6365 TCGv temp, temp2;
6366
6367 r1 = MASK_OP_RR1_S1(ctx->opcode);
6368 r2 = MASK_OP_RR1_S2(ctx->opcode);
6369 r3 = MASK_OP_RR1_D(ctx->opcode);
6370 n = MASK_OP_RR1_N(ctx->opcode);
6371 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6372
6373 temp = tcg_temp_new();
6374 temp2 = tcg_temp_new();
6375
6376 switch (op2) {
6377 case OPC2_32_RR1_MUL_Q_32:
6378 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
6379 break;
6380 case OPC2_32_RR1_MUL_Q_64:
6381 CHECK_REG_PAIR(r3);
6382 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6383 n, 0);
6384 break;
6385 case OPC2_32_RR1_MUL_Q_32_L:
6386 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6387 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6388 break;
6389 case OPC2_32_RR1_MUL_Q_64_L:
6390 CHECK_REG_PAIR(r3);
6391 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6392 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6393 break;
6394 case OPC2_32_RR1_MUL_Q_32_U:
6395 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6396 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6397 break;
6398 case OPC2_32_RR1_MUL_Q_64_U:
6399 CHECK_REG_PAIR(r3);
6400 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6401 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6402 break;
6403 case OPC2_32_RR1_MUL_Q_32_LL:
6404 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6405 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6406 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6407 break;
6408 case OPC2_32_RR1_MUL_Q_32_UU:
6409 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6410 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6411 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6412 break;
6413 case OPC2_32_RR1_MULR_Q_32_L:
6414 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6415 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6416 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6417 break;
6418 case OPC2_32_RR1_MULR_Q_32_U:
6419 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6420 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6421 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6422 break;
6423 default:
6424 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6425 }
6426 }
6427
6428 /* RR2 format */
6429 static void decode_rr2_mul(DisasContext *ctx)
6430 {
6431 uint32_t op2;
6432 int r1, r2, r3;
6433
6434 op2 = MASK_OP_RR2_OP2(ctx->opcode);
6435 r1 = MASK_OP_RR2_S1(ctx->opcode);
6436 r2 = MASK_OP_RR2_S2(ctx->opcode);
6437 r3 = MASK_OP_RR2_D(ctx->opcode);
6438 switch (op2) {
6439 case OPC2_32_RR2_MUL_32:
6440 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6441 break;
6442 case OPC2_32_RR2_MUL_64:
6443 CHECK_REG_PAIR(r3);
6444 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6445 cpu_gpr_d[r2]);
6446 break;
6447 case OPC2_32_RR2_MULS_32:
6448 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6449 cpu_gpr_d[r2]);
6450 break;
6451 case OPC2_32_RR2_MUL_U_64:
6452 CHECK_REG_PAIR(r3);
6453 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6454 cpu_gpr_d[r2]);
6455 break;
6456 case OPC2_32_RR2_MULS_U_32:
6457 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6458 cpu_gpr_d[r2]);
6459 break;
6460 default:
6461 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6462 }
6463 }
6464
6465 /* RRPW format */
6466 static void decode_rrpw_extract_insert(DisasContext *ctx)
6467 {
6468 uint32_t op2;
6469 int r1, r2, r3;
6470 int32_t pos, width;
6471 TCGv temp;
6472
6473 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
6474 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6475 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6476 r3 = MASK_OP_RRPW_D(ctx->opcode);
6477 pos = MASK_OP_RRPW_POS(ctx->opcode);
6478 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
6479
6480 switch (op2) {
6481 case OPC2_32_RRPW_EXTR:
6482 if (width == 0) {
6483 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6484 break;
6485 }
6486
6487 if (pos + width <= 32) {
6488 /* optimize special cases */
6489 if ((pos == 0) && (width == 8)) {
6490 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6491 } else if ((pos == 0) && (width == 16)) {
6492 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6493 } else {
6494 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
6495 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
6496 }
6497 }
6498 break;
6499 case OPC2_32_RRPW_EXTR_U:
6500 if (width == 0) {
6501 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6502 } else {
6503 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
6504 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
6505 }
6506 break;
6507 case OPC2_32_RRPW_IMASK:
6508 CHECK_REG_PAIR(r3);
6509
6510 if (pos + width <= 32) {
6511 temp = tcg_temp_new();
6512 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos);
6513 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
6514 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
6515 }
6516
6517 break;
6518 case OPC2_32_RRPW_INSERT:
6519 if (pos + width <= 32) {
6520 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
6521 pos, width);
6522 }
6523 break;
6524 default:
6525 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6526 }
6527 }
6528
6529 /* RRR format */
6530 static void decode_rrr_cond_select(DisasContext *ctx)
6531 {
6532 uint32_t op2;
6533 int r1, r2, r3, r4;
6534 TCGv temp;
6535
6536 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6537 r1 = MASK_OP_RRR_S1(ctx->opcode);
6538 r2 = MASK_OP_RRR_S2(ctx->opcode);
6539 r3 = MASK_OP_RRR_S3(ctx->opcode);
6540 r4 = MASK_OP_RRR_D(ctx->opcode);
6541
6542 switch (op2) {
6543 case OPC2_32_RRR_CADD:
6544 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
6545 cpu_gpr_d[r4], cpu_gpr_d[r3]);
6546 break;
6547 case OPC2_32_RRR_CADDN:
6548 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6549 cpu_gpr_d[r3]);
6550 break;
6551 case OPC2_32_RRR_CSUB:
6552 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6553 cpu_gpr_d[r3]);
6554 break;
6555 case OPC2_32_RRR_CSUBN:
6556 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6557 cpu_gpr_d[r3]);
6558 break;
6559 case OPC2_32_RRR_SEL:
6560 temp = tcg_const_i32(0);
6561 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6562 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6563 break;
6564 case OPC2_32_RRR_SELN:
6565 temp = tcg_const_i32(0);
6566 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6567 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6568 break;
6569 default:
6570 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6571 }
6572 }
6573
6574 static void decode_rrr_divide(DisasContext *ctx)
6575 {
6576 uint32_t op2;
6577
6578 int r1, r2, r3, r4;
6579
6580 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6581 r1 = MASK_OP_RRR_S1(ctx->opcode);
6582 r2 = MASK_OP_RRR_S2(ctx->opcode);
6583 r3 = MASK_OP_RRR_S3(ctx->opcode);
6584 r4 = MASK_OP_RRR_D(ctx->opcode);
6585
6586 switch (op2) {
6587 case OPC2_32_RRR_DVADJ:
6588 CHECK_REG_PAIR(r3);
6589 CHECK_REG_PAIR(r4);
6590 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6591 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6592 break;
6593 case OPC2_32_RRR_DVSTEP:
6594 CHECK_REG_PAIR(r3);
6595 CHECK_REG_PAIR(r4);
6596 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6597 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6598 break;
6599 case OPC2_32_RRR_DVSTEP_U:
6600 CHECK_REG_PAIR(r3);
6601 CHECK_REG_PAIR(r4);
6602 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6603 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6604 break;
6605 case OPC2_32_RRR_IXMAX:
6606 CHECK_REG_PAIR(r3);
6607 CHECK_REG_PAIR(r4);
6608 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6609 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6610 break;
6611 case OPC2_32_RRR_IXMAX_U:
6612 CHECK_REG_PAIR(r3);
6613 CHECK_REG_PAIR(r4);
6614 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6615 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6616 break;
6617 case OPC2_32_RRR_IXMIN:
6618 CHECK_REG_PAIR(r3);
6619 CHECK_REG_PAIR(r4);
6620 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6621 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6622 break;
6623 case OPC2_32_RRR_IXMIN_U:
6624 CHECK_REG_PAIR(r3);
6625 CHECK_REG_PAIR(r4);
6626 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6627 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6628 break;
6629 case OPC2_32_RRR_PACK:
6630 CHECK_REG_PAIR(r3);
6631 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
6632 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6633 break;
6634 case OPC2_32_RRR_ADD_F:
6635 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
6636 break;
6637 case OPC2_32_RRR_SUB_F:
6638 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
6639 break;
6640 case OPC2_32_RRR_MADD_F:
6641 gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6642 cpu_gpr_d[r2], cpu_gpr_d[r3]);
6643 break;
6644 case OPC2_32_RRR_MSUB_F:
6645 gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6646 cpu_gpr_d[r2], cpu_gpr_d[r3]);
6647 break;
6648 default:
6649 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6650 }
6651 }
6652
6653 /* RRR2 format */
6654 static void decode_rrr2_madd(DisasContext *ctx)
6655 {
6656 uint32_t op2;
6657 uint32_t r1, r2, r3, r4;
6658
6659 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6660 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6661 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6662 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6663 r4 = MASK_OP_RRR2_D(ctx->opcode);
6664 switch (op2) {
6665 case OPC2_32_RRR2_MADD_32:
6666 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6667 cpu_gpr_d[r2]);
6668 break;
6669 case OPC2_32_RRR2_MADD_64:
6670 CHECK_REG_PAIR(r4);
6671 CHECK_REG_PAIR(r3);
6672 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6673 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6674 break;
6675 case OPC2_32_RRR2_MADDS_32:
6676 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6677 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6678 break;
6679 case OPC2_32_RRR2_MADDS_64:
6680 CHECK_REG_PAIR(r4);
6681 CHECK_REG_PAIR(r3);
6682 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6683 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6684 break;
6685 case OPC2_32_RRR2_MADD_U_64:
6686 CHECK_REG_PAIR(r4);
6687 CHECK_REG_PAIR(r3);
6688 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6689 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6690 break;
6691 case OPC2_32_RRR2_MADDS_U_32:
6692 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6693 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6694 break;
6695 case OPC2_32_RRR2_MADDS_U_64:
6696 CHECK_REG_PAIR(r4);
6697 CHECK_REG_PAIR(r3);
6698 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6699 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6700 break;
6701 default:
6702 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6703 }
6704 }
6705
6706 static void decode_rrr2_msub(DisasContext *ctx)
6707 {
6708 uint32_t op2;
6709 uint32_t r1, r2, r3, r4;
6710
6711 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6712 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6713 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6714 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6715 r4 = MASK_OP_RRR2_D(ctx->opcode);
6716
6717 switch (op2) {
6718 case OPC2_32_RRR2_MSUB_32:
6719 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6720 cpu_gpr_d[r2]);
6721 break;
6722 case OPC2_32_RRR2_MSUB_64:
6723 CHECK_REG_PAIR(r4);
6724 CHECK_REG_PAIR(r3);
6725 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6726 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6727 break;
6728 case OPC2_32_RRR2_MSUBS_32:
6729 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6730 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6731 break;
6732 case OPC2_32_RRR2_MSUBS_64:
6733 CHECK_REG_PAIR(r4);
6734 CHECK_REG_PAIR(r3);
6735 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6736 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6737 break;
6738 case OPC2_32_RRR2_MSUB_U_64:
6739 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6740 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6741 break;
6742 case OPC2_32_RRR2_MSUBS_U_32:
6743 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6744 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6745 break;
6746 case OPC2_32_RRR2_MSUBS_U_64:
6747 CHECK_REG_PAIR(r4);
6748 CHECK_REG_PAIR(r3);
6749 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6750 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6751 break;
6752 default:
6753 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6754 }
6755 }
6756
6757 /* RRR1 format */
6758 static void decode_rrr1_madd(DisasContext *ctx)
6759 {
6760 uint32_t op2;
6761 uint32_t r1, r2, r3, r4, n;
6762
6763 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6764 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6765 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6766 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6767 r4 = MASK_OP_RRR1_D(ctx->opcode);
6768 n = MASK_OP_RRR1_N(ctx->opcode);
6769
6770 switch (op2) {
6771 case OPC2_32_RRR1_MADD_H_LL:
6772 CHECK_REG_PAIR(r4);
6773 CHECK_REG_PAIR(r3);
6774 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6775 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6776 break;
6777 case OPC2_32_RRR1_MADD_H_LU:
6778 CHECK_REG_PAIR(r4);
6779 CHECK_REG_PAIR(r3);
6780 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6781 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6782 break;
6783 case OPC2_32_RRR1_MADD_H_UL:
6784 CHECK_REG_PAIR(r4);
6785 CHECK_REG_PAIR(r3);
6786 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6787 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6788 break;
6789 case OPC2_32_RRR1_MADD_H_UU:
6790 CHECK_REG_PAIR(r4);
6791 CHECK_REG_PAIR(r3);
6792 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6793 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6794 break;
6795 case OPC2_32_RRR1_MADDS_H_LL:
6796 CHECK_REG_PAIR(r4);
6797 CHECK_REG_PAIR(r3);
6798 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6799 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6800 break;
6801 case OPC2_32_RRR1_MADDS_H_LU:
6802 CHECK_REG_PAIR(r4);
6803 CHECK_REG_PAIR(r3);
6804 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6805 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6806 break;
6807 case OPC2_32_RRR1_MADDS_H_UL:
6808 CHECK_REG_PAIR(r4);
6809 CHECK_REG_PAIR(r3);
6810 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6811 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6812 break;
6813 case OPC2_32_RRR1_MADDS_H_UU:
6814 CHECK_REG_PAIR(r4);
6815 CHECK_REG_PAIR(r3);
6816 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6817 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6818 break;
6819 case OPC2_32_RRR1_MADDM_H_LL:
6820 CHECK_REG_PAIR(r4);
6821 CHECK_REG_PAIR(r3);
6822 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6823 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6824 break;
6825 case OPC2_32_RRR1_MADDM_H_LU:
6826 CHECK_REG_PAIR(r4);
6827 CHECK_REG_PAIR(r3);
6828 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6829 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6830 break;
6831 case OPC2_32_RRR1_MADDM_H_UL:
6832 CHECK_REG_PAIR(r4);
6833 CHECK_REG_PAIR(r3);
6834 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6835 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6836 break;
6837 case OPC2_32_RRR1_MADDM_H_UU:
6838 CHECK_REG_PAIR(r4);
6839 CHECK_REG_PAIR(r3);
6840 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6841 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6842 break;
6843 case OPC2_32_RRR1_MADDMS_H_LL:
6844 CHECK_REG_PAIR(r4);
6845 CHECK_REG_PAIR(r3);
6846 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6847 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6848 break;
6849 case OPC2_32_RRR1_MADDMS_H_LU:
6850 CHECK_REG_PAIR(r4);
6851 CHECK_REG_PAIR(r3);
6852 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6853 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6854 break;
6855 case OPC2_32_RRR1_MADDMS_H_UL:
6856 CHECK_REG_PAIR(r4);
6857 CHECK_REG_PAIR(r3);
6858 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6859 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6860 break;
6861 case OPC2_32_RRR1_MADDMS_H_UU:
6862 CHECK_REG_PAIR(r4);
6863 CHECK_REG_PAIR(r3);
6864 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6865 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6866 break;
6867 case OPC2_32_RRR1_MADDR_H_LL:
6868 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6869 cpu_gpr_d[r2], n, MODE_LL);
6870 break;
6871 case OPC2_32_RRR1_MADDR_H_LU:
6872 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6873 cpu_gpr_d[r2], n, MODE_LU);
6874 break;
6875 case OPC2_32_RRR1_MADDR_H_UL:
6876 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6877 cpu_gpr_d[r2], n, MODE_UL);
6878 break;
6879 case OPC2_32_RRR1_MADDR_H_UU:
6880 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6881 cpu_gpr_d[r2], n, MODE_UU);
6882 break;
6883 case OPC2_32_RRR1_MADDRS_H_LL:
6884 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6885 cpu_gpr_d[r2], n, MODE_LL);
6886 break;
6887 case OPC2_32_RRR1_MADDRS_H_LU:
6888 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6889 cpu_gpr_d[r2], n, MODE_LU);
6890 break;
6891 case OPC2_32_RRR1_MADDRS_H_UL:
6892 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6893 cpu_gpr_d[r2], n, MODE_UL);
6894 break;
6895 case OPC2_32_RRR1_MADDRS_H_UU:
6896 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6897 cpu_gpr_d[r2], n, MODE_UU);
6898 break;
6899 default:
6900 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6901 }
6902 }
6903
6904 static void decode_rrr1_maddq_h(DisasContext *ctx)
6905 {
6906 uint32_t op2;
6907 uint32_t r1, r2, r3, r4, n;
6908 TCGv temp, temp2;
6909
6910 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6911 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6912 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6913 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6914 r4 = MASK_OP_RRR1_D(ctx->opcode);
6915 n = MASK_OP_RRR1_N(ctx->opcode);
6916
6917 temp = tcg_const_i32(n);
6918 temp2 = tcg_temp_new();
6919
6920 switch (op2) {
6921 case OPC2_32_RRR1_MADD_Q_32:
6922 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6923 cpu_gpr_d[r2], n, 32);
6924 break;
6925 case OPC2_32_RRR1_MADD_Q_64:
6926 CHECK_REG_PAIR(r4);
6927 CHECK_REG_PAIR(r3);
6928 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6929 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6930 n);
6931 break;
6932 case OPC2_32_RRR1_MADD_Q_32_L:
6933 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6934 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6935 temp, n, 16);
6936 break;
6937 case OPC2_32_RRR1_MADD_Q_64_L:
6938 CHECK_REG_PAIR(r4);
6939 CHECK_REG_PAIR(r3);
6940 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6941 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6942 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6943 n);
6944 break;
6945 case OPC2_32_RRR1_MADD_Q_32_U:
6946 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6947 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6948 temp, n, 16);
6949 break;
6950 case OPC2_32_RRR1_MADD_Q_64_U:
6951 CHECK_REG_PAIR(r4);
6952 CHECK_REG_PAIR(r3);
6953 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6954 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6955 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6956 n);
6957 break;
6958 case OPC2_32_RRR1_MADD_Q_32_LL:
6959 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6960 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6961 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6962 break;
6963 case OPC2_32_RRR1_MADD_Q_64_LL:
6964 CHECK_REG_PAIR(r4);
6965 CHECK_REG_PAIR(r3);
6966 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6967 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6968 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6969 cpu_gpr_d[r3+1], temp, temp2, n);
6970 break;
6971 case OPC2_32_RRR1_MADD_Q_32_UU:
6972 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6973 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6974 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6975 break;
6976 case OPC2_32_RRR1_MADD_Q_64_UU:
6977 CHECK_REG_PAIR(r4);
6978 CHECK_REG_PAIR(r3);
6979 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6980 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6981 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6982 cpu_gpr_d[r3+1], temp, temp2, n);
6983 break;
6984 case OPC2_32_RRR1_MADDS_Q_32:
6985 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6986 cpu_gpr_d[r2], n, 32);
6987 break;
6988 case OPC2_32_RRR1_MADDS_Q_64:
6989 CHECK_REG_PAIR(r4);
6990 CHECK_REG_PAIR(r3);
6991 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6992 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6993 n);
6994 break;
6995 case OPC2_32_RRR1_MADDS_Q_32_L:
6996 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6997 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6998 temp, n, 16);
6999 break;
7000 case OPC2_32_RRR1_MADDS_Q_64_L:
7001 CHECK_REG_PAIR(r4);
7002 CHECK_REG_PAIR(r3);
7003 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7004 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7005 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7006 n);
7007 break;
7008 case OPC2_32_RRR1_MADDS_Q_32_U:
7009 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7010 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7011 temp, n, 16);
7012 break;
7013 case OPC2_32_RRR1_MADDS_Q_64_U:
7014 CHECK_REG_PAIR(r4);
7015 CHECK_REG_PAIR(r3);
7016 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7017 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7018 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7019 n);
7020 break;
7021 case OPC2_32_RRR1_MADDS_Q_32_LL:
7022 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7023 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7024 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7025 break;
7026 case OPC2_32_RRR1_MADDS_Q_64_LL:
7027 CHECK_REG_PAIR(r4);
7028 CHECK_REG_PAIR(r3);
7029 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7030 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7031 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7032 cpu_gpr_d[r3+1], temp, temp2, n);
7033 break;
7034 case OPC2_32_RRR1_MADDS_Q_32_UU:
7035 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7036 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7037 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7038 break;
7039 case OPC2_32_RRR1_MADDS_Q_64_UU:
7040 CHECK_REG_PAIR(r4);
7041 CHECK_REG_PAIR(r3);
7042 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7043 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7044 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7045 cpu_gpr_d[r3+1], temp, temp2, n);
7046 break;
7047 case OPC2_32_RRR1_MADDR_H_64_UL:
7048 CHECK_REG_PAIR(r3);
7049 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7050 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7051 break;
7052 case OPC2_32_RRR1_MADDRS_H_64_UL:
7053 CHECK_REG_PAIR(r3);
7054 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7055 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7056 break;
7057 case OPC2_32_RRR1_MADDR_Q_32_LL:
7058 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7059 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7060 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7061 break;
7062 case OPC2_32_RRR1_MADDR_Q_32_UU:
7063 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7064 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7065 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7066 break;
7067 case OPC2_32_RRR1_MADDRS_Q_32_LL:
7068 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7069 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7070 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7071 break;
7072 case OPC2_32_RRR1_MADDRS_Q_32_UU:
7073 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7074 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7075 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7076 break;
7077 default:
7078 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7079 }
7080 }
7081
7082 static void decode_rrr1_maddsu_h(DisasContext *ctx)
7083 {
7084 uint32_t op2;
7085 uint32_t r1, r2, r3, r4, n;
7086
7087 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7088 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7089 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7090 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7091 r4 = MASK_OP_RRR1_D(ctx->opcode);
7092 n = MASK_OP_RRR1_N(ctx->opcode);
7093
7094 switch (op2) {
7095 case OPC2_32_RRR1_MADDSU_H_32_LL:
7096 CHECK_REG_PAIR(r4);
7097 CHECK_REG_PAIR(r3);
7098 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7099 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7100 break;
7101 case OPC2_32_RRR1_MADDSU_H_32_LU:
7102 CHECK_REG_PAIR(r4);
7103 CHECK_REG_PAIR(r3);
7104 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7105 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7106 break;
7107 case OPC2_32_RRR1_MADDSU_H_32_UL:
7108 CHECK_REG_PAIR(r4);
7109 CHECK_REG_PAIR(r3);
7110 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7111 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7112 break;
7113 case OPC2_32_RRR1_MADDSU_H_32_UU:
7114 CHECK_REG_PAIR(r4);
7115 CHECK_REG_PAIR(r3);
7116 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7117 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7118 break;
7119 case OPC2_32_RRR1_MADDSUS_H_32_LL:
7120 CHECK_REG_PAIR(r4);
7121 CHECK_REG_PAIR(r3);
7122 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7123 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7124 n, MODE_LL);
7125 break;
7126 case OPC2_32_RRR1_MADDSUS_H_32_LU:
7127 CHECK_REG_PAIR(r4);
7128 CHECK_REG_PAIR(r3);
7129 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7130 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7131 n, MODE_LU);
7132 break;
7133 case OPC2_32_RRR1_MADDSUS_H_32_UL:
7134 CHECK_REG_PAIR(r4);
7135 CHECK_REG_PAIR(r3);
7136 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7137 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7138 n, MODE_UL);
7139 break;
7140 case OPC2_32_RRR1_MADDSUS_H_32_UU:
7141 CHECK_REG_PAIR(r4);
7142 CHECK_REG_PAIR(r3);
7143 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7144 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7145 n, MODE_UU);
7146 break;
7147 case OPC2_32_RRR1_MADDSUM_H_64_LL:
7148 CHECK_REG_PAIR(r4);
7149 CHECK_REG_PAIR(r3);
7150 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7151 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7152 n, MODE_LL);
7153 break;
7154 case OPC2_32_RRR1_MADDSUM_H_64_LU:
7155 CHECK_REG_PAIR(r4);
7156 CHECK_REG_PAIR(r3);
7157 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7158 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7159 n, MODE_LU);
7160 break;
7161 case OPC2_32_RRR1_MADDSUM_H_64_UL:
7162 CHECK_REG_PAIR(r4);
7163 CHECK_REG_PAIR(r3);
7164 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7165 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7166 n, MODE_UL);
7167 break;
7168 case OPC2_32_RRR1_MADDSUM_H_64_UU:
7169 CHECK_REG_PAIR(r4);
7170 CHECK_REG_PAIR(r3);
7171 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7172 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7173 n, MODE_UU);
7174 break;
7175 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
7176 CHECK_REG_PAIR(r4);
7177 CHECK_REG_PAIR(r3);
7178 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7179 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7180 n, MODE_LL);
7181 break;
7182 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
7183 CHECK_REG_PAIR(r4);
7184 CHECK_REG_PAIR(r3);
7185 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7186 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7187 n, MODE_LU);
7188 break;
7189 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
7190 CHECK_REG_PAIR(r4);
7191 CHECK_REG_PAIR(r3);
7192 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7193 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7194 n, MODE_UL);
7195 break;
7196 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
7197 CHECK_REG_PAIR(r4);
7198 CHECK_REG_PAIR(r3);
7199 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7200 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7201 n, MODE_UU);
7202 break;
7203 case OPC2_32_RRR1_MADDSUR_H_16_LL:
7204 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7205 cpu_gpr_d[r2], n, MODE_LL);
7206 break;
7207 case OPC2_32_RRR1_MADDSUR_H_16_LU:
7208 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7209 cpu_gpr_d[r2], n, MODE_LU);
7210 break;
7211 case OPC2_32_RRR1_MADDSUR_H_16_UL:
7212 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7213 cpu_gpr_d[r2], n, MODE_UL);
7214 break;
7215 case OPC2_32_RRR1_MADDSUR_H_16_UU:
7216 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7217 cpu_gpr_d[r2], n, MODE_UU);
7218 break;
7219 case OPC2_32_RRR1_MADDSURS_H_16_LL:
7220 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7221 cpu_gpr_d[r2], n, MODE_LL);
7222 break;
7223 case OPC2_32_RRR1_MADDSURS_H_16_LU:
7224 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7225 cpu_gpr_d[r2], n, MODE_LU);
7226 break;
7227 case OPC2_32_RRR1_MADDSURS_H_16_UL:
7228 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7229 cpu_gpr_d[r2], n, MODE_UL);
7230 break;
7231 case OPC2_32_RRR1_MADDSURS_H_16_UU:
7232 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7233 cpu_gpr_d[r2], n, MODE_UU);
7234 break;
7235 default:
7236 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7237 }
7238 }
7239
7240 static void decode_rrr1_msub(DisasContext *ctx)
7241 {
7242 uint32_t op2;
7243 uint32_t r1, r2, r3, r4, n;
7244
7245 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7246 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7247 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7248 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7249 r4 = MASK_OP_RRR1_D(ctx->opcode);
7250 n = MASK_OP_RRR1_N(ctx->opcode);
7251
7252 switch (op2) {
7253 case OPC2_32_RRR1_MSUB_H_LL:
7254 CHECK_REG_PAIR(r4);
7255 CHECK_REG_PAIR(r3);
7256 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7257 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7258 break;
7259 case OPC2_32_RRR1_MSUB_H_LU:
7260 CHECK_REG_PAIR(r4);
7261 CHECK_REG_PAIR(r3);
7262 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7263 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7264 break;
7265 case OPC2_32_RRR1_MSUB_H_UL:
7266 CHECK_REG_PAIR(r4);
7267 CHECK_REG_PAIR(r3);
7268 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7269 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7270 break;
7271 case OPC2_32_RRR1_MSUB_H_UU:
7272 CHECK_REG_PAIR(r4);
7273 CHECK_REG_PAIR(r3);
7274 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7275 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7276 break;
7277 case OPC2_32_RRR1_MSUBS_H_LL:
7278 CHECK_REG_PAIR(r4);
7279 CHECK_REG_PAIR(r3);
7280 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7281 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7282 break;
7283 case OPC2_32_RRR1_MSUBS_H_LU:
7284 CHECK_REG_PAIR(r4);
7285 CHECK_REG_PAIR(r3);
7286 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7287 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7288 break;
7289 case OPC2_32_RRR1_MSUBS_H_UL:
7290 CHECK_REG_PAIR(r4);
7291 CHECK_REG_PAIR(r3);
7292 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7293 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7294 break;
7295 case OPC2_32_RRR1_MSUBS_H_UU:
7296 CHECK_REG_PAIR(r4);
7297 CHECK_REG_PAIR(r3);
7298 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7299 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7300 break;
7301 case OPC2_32_RRR1_MSUBM_H_LL:
7302 CHECK_REG_PAIR(r4);
7303 CHECK_REG_PAIR(r3);
7304 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7305 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7306 break;
7307 case OPC2_32_RRR1_MSUBM_H_LU:
7308 CHECK_REG_PAIR(r4);
7309 CHECK_REG_PAIR(r3);
7310 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7311 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7312 break;
7313 case OPC2_32_RRR1_MSUBM_H_UL:
7314 CHECK_REG_PAIR(r4);
7315 CHECK_REG_PAIR(r3);
7316 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7317 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7318 break;
7319 case OPC2_32_RRR1_MSUBM_H_UU:
7320 CHECK_REG_PAIR(r4);
7321 CHECK_REG_PAIR(r3);
7322 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7323 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7324 break;
7325 case OPC2_32_RRR1_MSUBMS_H_LL:
7326 CHECK_REG_PAIR(r4);
7327 CHECK_REG_PAIR(r3);
7328 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7329 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7330 break;
7331 case OPC2_32_RRR1_MSUBMS_H_LU:
7332 CHECK_REG_PAIR(r4);
7333 CHECK_REG_PAIR(r3);
7334 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7335 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7336 break;
7337 case OPC2_32_RRR1_MSUBMS_H_UL:
7338 CHECK_REG_PAIR(r4);
7339 CHECK_REG_PAIR(r3);
7340 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7341 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7342 break;
7343 case OPC2_32_RRR1_MSUBMS_H_UU:
7344 CHECK_REG_PAIR(r4);
7345 CHECK_REG_PAIR(r3);
7346 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7347 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7348 break;
7349 case OPC2_32_RRR1_MSUBR_H_LL:
7350 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7351 cpu_gpr_d[r2], n, MODE_LL);
7352 break;
7353 case OPC2_32_RRR1_MSUBR_H_LU:
7354 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7355 cpu_gpr_d[r2], n, MODE_LU);
7356 break;
7357 case OPC2_32_RRR1_MSUBR_H_UL:
7358 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7359 cpu_gpr_d[r2], n, MODE_UL);
7360 break;
7361 case OPC2_32_RRR1_MSUBR_H_UU:
7362 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7363 cpu_gpr_d[r2], n, MODE_UU);
7364 break;
7365 case OPC2_32_RRR1_MSUBRS_H_LL:
7366 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7367 cpu_gpr_d[r2], n, MODE_LL);
7368 break;
7369 case OPC2_32_RRR1_MSUBRS_H_LU:
7370 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7371 cpu_gpr_d[r2], n, MODE_LU);
7372 break;
7373 case OPC2_32_RRR1_MSUBRS_H_UL:
7374 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7375 cpu_gpr_d[r2], n, MODE_UL);
7376 break;
7377 case OPC2_32_RRR1_MSUBRS_H_UU:
7378 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7379 cpu_gpr_d[r2], n, MODE_UU);
7380 break;
7381 default:
7382 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7383 }
7384 }
7385
7386 static void decode_rrr1_msubq_h(DisasContext *ctx)
7387 {
7388 uint32_t op2;
7389 uint32_t r1, r2, r3, r4, n;
7390 TCGv temp, temp2;
7391
7392 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7393 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7394 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7395 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7396 r4 = MASK_OP_RRR1_D(ctx->opcode);
7397 n = MASK_OP_RRR1_N(ctx->opcode);
7398
7399 temp = tcg_const_i32(n);
7400 temp2 = tcg_temp_new();
7401
7402 switch (op2) {
7403 case OPC2_32_RRR1_MSUB_Q_32:
7404 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7405 cpu_gpr_d[r2], n, 32);
7406 break;
7407 case OPC2_32_RRR1_MSUB_Q_64:
7408 CHECK_REG_PAIR(r4);
7409 CHECK_REG_PAIR(r3);
7410 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7411 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7412 n);
7413 break;
7414 case OPC2_32_RRR1_MSUB_Q_32_L:
7415 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7416 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7417 temp, n, 16);
7418 break;
7419 case OPC2_32_RRR1_MSUB_Q_64_L:
7420 CHECK_REG_PAIR(r4);
7421 CHECK_REG_PAIR(r3);
7422 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7423 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7424 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7425 n);
7426 break;
7427 case OPC2_32_RRR1_MSUB_Q_32_U:
7428 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7429 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7430 temp, n, 16);
7431 break;
7432 case OPC2_32_RRR1_MSUB_Q_64_U:
7433 CHECK_REG_PAIR(r4);
7434 CHECK_REG_PAIR(r3);
7435 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7436 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7437 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7438 n);
7439 break;
7440 case OPC2_32_RRR1_MSUB_Q_32_LL:
7441 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7442 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7443 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7444 break;
7445 case OPC2_32_RRR1_MSUB_Q_64_LL:
7446 CHECK_REG_PAIR(r4);
7447 CHECK_REG_PAIR(r3);
7448 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7449 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7450 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7451 cpu_gpr_d[r3+1], temp, temp2, n);
7452 break;
7453 case OPC2_32_RRR1_MSUB_Q_32_UU:
7454 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7455 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7456 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7457 break;
7458 case OPC2_32_RRR1_MSUB_Q_64_UU:
7459 CHECK_REG_PAIR(r4);
7460 CHECK_REG_PAIR(r3);
7461 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7462 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7463 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7464 cpu_gpr_d[r3+1], temp, temp2, n);
7465 break;
7466 case OPC2_32_RRR1_MSUBS_Q_32:
7467 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7468 cpu_gpr_d[r2], n, 32);
7469 break;
7470 case OPC2_32_RRR1_MSUBS_Q_64:
7471 CHECK_REG_PAIR(r4);
7472 CHECK_REG_PAIR(r3);
7473 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7474 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7475 n);
7476 break;
7477 case OPC2_32_RRR1_MSUBS_Q_32_L:
7478 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7479 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7480 temp, n, 16);
7481 break;
7482 case OPC2_32_RRR1_MSUBS_Q_64_L:
7483 CHECK_REG_PAIR(r4);
7484 CHECK_REG_PAIR(r3);
7485 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7486 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7487 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7488 n);
7489 break;
7490 case OPC2_32_RRR1_MSUBS_Q_32_U:
7491 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7492 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7493 temp, n, 16);
7494 break;
7495 case OPC2_32_RRR1_MSUBS_Q_64_U:
7496 CHECK_REG_PAIR(r4);
7497 CHECK_REG_PAIR(r3);
7498 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7499 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7500 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7501 n);
7502 break;
7503 case OPC2_32_RRR1_MSUBS_Q_32_LL:
7504 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7505 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7506 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7507 break;
7508 case OPC2_32_RRR1_MSUBS_Q_64_LL:
7509 CHECK_REG_PAIR(r4);
7510 CHECK_REG_PAIR(r3);
7511 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7512 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7513 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7514 cpu_gpr_d[r3+1], temp, temp2, n);
7515 break;
7516 case OPC2_32_RRR1_MSUBS_Q_32_UU:
7517 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7518 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7519 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7520 break;
7521 case OPC2_32_RRR1_MSUBS_Q_64_UU:
7522 CHECK_REG_PAIR(r4);
7523 CHECK_REG_PAIR(r3);
7524 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7525 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7526 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7527 cpu_gpr_d[r3+1], temp, temp2, n);
7528 break;
7529 case OPC2_32_RRR1_MSUBR_H_64_UL:
7530 CHECK_REG_PAIR(r3);
7531 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7532 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7533 break;
7534 case OPC2_32_RRR1_MSUBRS_H_64_UL:
7535 CHECK_REG_PAIR(r3);
7536 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7537 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7538 break;
7539 case OPC2_32_RRR1_MSUBR_Q_32_LL:
7540 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7541 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7542 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7543 break;
7544 case OPC2_32_RRR1_MSUBR_Q_32_UU:
7545 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7546 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7547 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7548 break;
7549 case OPC2_32_RRR1_MSUBRS_Q_32_LL:
7550 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7551 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7552 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7553 break;
7554 case OPC2_32_RRR1_MSUBRS_Q_32_UU:
7555 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7556 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7557 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7558 break;
7559 default:
7560 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7561 }
7562 }
7563
7564 static void decode_rrr1_msubad_h(DisasContext *ctx)
7565 {
7566 uint32_t op2;
7567 uint32_t r1, r2, r3, r4, n;
7568
7569 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7570 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7571 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7572 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7573 r4 = MASK_OP_RRR1_D(ctx->opcode);
7574 n = MASK_OP_RRR1_N(ctx->opcode);
7575
7576 switch (op2) {
7577 case OPC2_32_RRR1_MSUBAD_H_32_LL:
7578 CHECK_REG_PAIR(r4);
7579 CHECK_REG_PAIR(r3);
7580 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7581 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7582 break;
7583 case OPC2_32_RRR1_MSUBAD_H_32_LU:
7584 CHECK_REG_PAIR(r4);
7585 CHECK_REG_PAIR(r3);
7586 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7587 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7588 break;
7589 case OPC2_32_RRR1_MSUBAD_H_32_UL:
7590 CHECK_REG_PAIR(r4);
7591 CHECK_REG_PAIR(r3);
7592 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7593 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7594 break;
7595 case OPC2_32_RRR1_MSUBAD_H_32_UU:
7596 CHECK_REG_PAIR(r4);
7597 CHECK_REG_PAIR(r3);
7598 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7599 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7600 break;
7601 case OPC2_32_RRR1_MSUBADS_H_32_LL:
7602 CHECK_REG_PAIR(r4);
7603 CHECK_REG_PAIR(r3);
7604 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7605 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7606 n, MODE_LL);
7607 break;
7608 case OPC2_32_RRR1_MSUBADS_H_32_LU:
7609 CHECK_REG_PAIR(r4);
7610 CHECK_REG_PAIR(r3);
7611 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7612 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7613 n, MODE_LU);
7614 break;
7615 case OPC2_32_RRR1_MSUBADS_H_32_UL:
7616 CHECK_REG_PAIR(r4);
7617 CHECK_REG_PAIR(r3);
7618 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7619 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7620 n, MODE_UL);
7621 break;
7622 case OPC2_32_RRR1_MSUBADS_H_32_UU:
7623 CHECK_REG_PAIR(r4);
7624 CHECK_REG_PAIR(r3);
7625 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7626 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7627 n, MODE_UU);
7628 break;
7629 case OPC2_32_RRR1_MSUBADM_H_64_LL:
7630 CHECK_REG_PAIR(r4);
7631 CHECK_REG_PAIR(r3);
7632 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7633 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7634 n, MODE_LL);
7635 break;
7636 case OPC2_32_RRR1_MSUBADM_H_64_LU:
7637 CHECK_REG_PAIR(r4);
7638 CHECK_REG_PAIR(r3);
7639 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7640 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7641 n, MODE_LU);
7642 break;
7643 case OPC2_32_RRR1_MSUBADM_H_64_UL:
7644 CHECK_REG_PAIR(r4);
7645 CHECK_REG_PAIR(r3);
7646 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7647 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7648 n, MODE_UL);
7649 break;
7650 case OPC2_32_RRR1_MSUBADM_H_64_UU:
7651 CHECK_REG_PAIR(r4);
7652 CHECK_REG_PAIR(r3);
7653 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7654 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7655 n, MODE_UU);
7656 break;
7657 case OPC2_32_RRR1_MSUBADMS_H_64_LL:
7658 CHECK_REG_PAIR(r4);
7659 CHECK_REG_PAIR(r3);
7660 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7661 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7662 n, MODE_LL);
7663 break;
7664 case OPC2_32_RRR1_MSUBADMS_H_64_LU:
7665 CHECK_REG_PAIR(r4);
7666 CHECK_REG_PAIR(r3);
7667 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7668 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7669 n, MODE_LU);
7670 break;
7671 case OPC2_32_RRR1_MSUBADMS_H_64_UL:
7672 CHECK_REG_PAIR(r4);
7673 CHECK_REG_PAIR(r3);
7674 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7675 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7676 n, MODE_UL);
7677 break;
7678 case OPC2_32_RRR1_MSUBADMS_H_64_UU:
7679 CHECK_REG_PAIR(r4);
7680 CHECK_REG_PAIR(r3);
7681 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7682 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7683 n, MODE_UU);
7684 break;
7685 case OPC2_32_RRR1_MSUBADR_H_16_LL:
7686 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7687 cpu_gpr_d[r2], n, MODE_LL);
7688 break;
7689 case OPC2_32_RRR1_MSUBADR_H_16_LU:
7690 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7691 cpu_gpr_d[r2], n, MODE_LU);
7692 break;
7693 case OPC2_32_RRR1_MSUBADR_H_16_UL:
7694 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7695 cpu_gpr_d[r2], n, MODE_UL);
7696 break;
7697 case OPC2_32_RRR1_MSUBADR_H_16_UU:
7698 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7699 cpu_gpr_d[r2], n, MODE_UU);
7700 break;
7701 case OPC2_32_RRR1_MSUBADRS_H_16_LL:
7702 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7703 cpu_gpr_d[r2], n, MODE_LL);
7704 break;
7705 case OPC2_32_RRR1_MSUBADRS_H_16_LU:
7706 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7707 cpu_gpr_d[r2], n, MODE_LU);
7708 break;
7709 case OPC2_32_RRR1_MSUBADRS_H_16_UL:
7710 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7711 cpu_gpr_d[r2], n, MODE_UL);
7712 break;
7713 case OPC2_32_RRR1_MSUBADRS_H_16_UU:
7714 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7715 cpu_gpr_d[r2], n, MODE_UU);
7716 break;
7717 default:
7718 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7719 }
7720 }
7721
7722 /* RRRR format */
7723 static void decode_rrrr_extract_insert(DisasContext *ctx)
7724 {
7725 uint32_t op2;
7726 int r1, r2, r3, r4;
7727 TCGv tmp_width, tmp_pos;
7728
7729 r1 = MASK_OP_RRRR_S1(ctx->opcode);
7730 r2 = MASK_OP_RRRR_S2(ctx->opcode);
7731 r3 = MASK_OP_RRRR_S3(ctx->opcode);
7732 r4 = MASK_OP_RRRR_D(ctx->opcode);
7733 op2 = MASK_OP_RRRR_OP2(ctx->opcode);
7734
7735 tmp_pos = tcg_temp_new();
7736 tmp_width = tcg_temp_new();
7737
7738 switch (op2) {
7739 case OPC2_32_RRRR_DEXTR:
7740 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7741 if (r1 == r2) {
7742 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7743 } else {
7744 TCGv msw = tcg_temp_new();
7745 TCGv zero = tcg_constant_tl(0);
7746 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
7747 tcg_gen_subfi_tl(msw, 32, tmp_pos);
7748 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw);
7749 /*
7750 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined
7751 * behaviour. So check that case here and set the low bits to zero
7752 * which effectivly returns cpu_gpr_d[r1]
7753 */
7754 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw);
7755 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw);
7756 }
7757 break;
7758 case OPC2_32_RRRR_EXTR:
7759 case OPC2_32_RRRR_EXTR_U:
7760 CHECK_REG_PAIR(r3);
7761 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7762 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7763 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
7764 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7765 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7766 tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
7767 if (op2 == OPC2_32_RRRR_EXTR) {
7768 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7769 } else {
7770 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7771 }
7772 break;
7773 case OPC2_32_RRRR_INSERT:
7774 CHECK_REG_PAIR(r3);
7775 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7776 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7777 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
7778 tmp_pos);
7779 break;
7780 default:
7781 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7782 }
7783 }
7784
7785 /* RRRW format */
7786 static void decode_rrrw_extract_insert(DisasContext *ctx)
7787 {
7788 uint32_t op2;
7789 int r1, r2, r3, r4;
7790 int32_t width;
7791
7792 TCGv temp, temp2;
7793
7794 op2 = MASK_OP_RRRW_OP2(ctx->opcode);
7795 r1 = MASK_OP_RRRW_S1(ctx->opcode);
7796 r2 = MASK_OP_RRRW_S2(ctx->opcode);
7797 r3 = MASK_OP_RRRW_S3(ctx->opcode);
7798 r4 = MASK_OP_RRRW_D(ctx->opcode);
7799 width = MASK_OP_RRRW_WIDTH(ctx->opcode);
7800
7801 temp = tcg_temp_new();
7802
7803 switch (op2) {
7804 case OPC2_32_RRRW_EXTR:
7805 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7806 tcg_gen_addi_tl(temp, temp, width);
7807 tcg_gen_subfi_tl(temp, 32, temp);
7808 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7809 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
7810 break;
7811 case OPC2_32_RRRW_EXTR_U:
7812 if (width == 0) {
7813 tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
7814 } else {
7815 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7816 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7817 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
7818 }
7819 break;
7820 case OPC2_32_RRRW_IMASK:
7821 temp2 = tcg_temp_new();
7822
7823 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7824 tcg_gen_movi_tl(temp2, (1 << width) - 1);
7825 tcg_gen_shl_tl(temp2, temp2, temp);
7826 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
7827 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
7828 break;
7829 case OPC2_32_RRRW_INSERT:
7830 temp2 = tcg_temp_new();
7831
7832 tcg_gen_movi_tl(temp, width);
7833 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
7834 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
7835 break;
7836 default:
7837 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7838 }
7839 }
7840
7841 /* SYS Format*/
7842 static void decode_sys_interrupts(DisasContext *ctx)
7843 {
7844 uint32_t op2;
7845 uint32_t r1;
7846 TCGLabel *l1;
7847 TCGv tmp;
7848
7849 op2 = MASK_OP_SYS_OP2(ctx->opcode);
7850 r1 = MASK_OP_SYS_S1D(ctx->opcode);
7851
7852 switch (op2) {
7853 case OPC2_32_SYS_DEBUG:
7854 /* raise EXCP_DEBUG */
7855 break;
7856 case OPC2_32_SYS_DISABLE:
7857 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3);
7858 break;
7859 case OPC2_32_SYS_DSYNC:
7860 break;
7861 case OPC2_32_SYS_ENABLE:
7862 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3);
7863 break;
7864 case OPC2_32_SYS_ISYNC:
7865 break;
7866 case OPC2_32_SYS_NOP:
7867 break;
7868 case OPC2_32_SYS_RET:
7869 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
7870 break;
7871 case OPC2_32_SYS_FRET:
7872 gen_fret(ctx);
7873 break;
7874 case OPC2_32_SYS_RFE:
7875 gen_helper_rfe(cpu_env);
7876 tcg_gen_exit_tb(NULL, 0);
7877 ctx->base.is_jmp = DISAS_NORETURN;
7878 break;
7879 case OPC2_32_SYS_RFM:
7880 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
7881 tmp = tcg_temp_new();
7882 l1 = gen_new_label();
7883
7884 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
7885 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
7886 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
7887 gen_helper_rfm(cpu_env);
7888 gen_set_label(l1);
7889 tcg_gen_exit_tb(NULL, 0);
7890 ctx->base.is_jmp = DISAS_NORETURN;
7891 } else {
7892 /* generate privilege trap */
7893 }
7894 break;
7895 case OPC2_32_SYS_RSLCX:
7896 gen_helper_rslcx(cpu_env);
7897 break;
7898 case OPC2_32_SYS_SVLCX:
7899 gen_helper_svlcx(cpu_env);
7900 break;
7901 case OPC2_32_SYS_RESTORE:
7902 if (has_feature(ctx, TRICORE_FEATURE_16)) {
7903 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
7904 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
7905 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
7906 } /* else raise privilege trap */
7907 } else {
7908 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7909 }
7910 break;
7911 case OPC2_32_SYS_TRAPSV:
7912 l1 = gen_new_label();
7913 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1);
7914 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF);
7915 gen_set_label(l1);
7916 break;
7917 case OPC2_32_SYS_TRAPV:
7918 l1 = gen_new_label();
7919 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1);
7920 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF);
7921 gen_set_label(l1);
7922 break;
7923 default:
7924 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7925 }
7926 }
7927
7928 static void decode_32Bit_opc(DisasContext *ctx)
7929 {
7930 int op1;
7931 int32_t r1, r2, r3;
7932 int32_t address, const16;
7933 int8_t b, const4;
7934 int32_t bpos;
7935 TCGv temp, temp2, temp3;
7936
7937 op1 = MASK_OP_MAJOR(ctx->opcode);
7938
7939 /* handle JNZ.T opcode only being 7 bit long */
7940 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
7941 op1 = OPCM_32_BRN_JTT;
7942 }
7943
7944 switch (op1) {
7945 /* ABS-format */
7946 case OPCM_32_ABS_LDW:
7947 decode_abs_ldw(ctx);
7948 break;
7949 case OPCM_32_ABS_LDB:
7950 decode_abs_ldb(ctx);
7951 break;
7952 case OPCM_32_ABS_LDMST_SWAP:
7953 decode_abs_ldst_swap(ctx);
7954 break;
7955 case OPCM_32_ABS_LDST_CONTEXT:
7956 decode_abs_ldst_context(ctx);
7957 break;
7958 case OPCM_32_ABS_STORE:
7959 decode_abs_store(ctx);
7960 break;
7961 case OPCM_32_ABS_STOREB_H:
7962 decode_abs_storeb_h(ctx);
7963 break;
7964 case OPC1_32_ABS_STOREQ:
7965 address = MASK_OP_ABS_OFF18(ctx->opcode);
7966 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7967 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7968 temp2 = tcg_temp_new();
7969
7970 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
7971 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
7972 break;
7973 case OPC1_32_ABS_LD_Q:
7974 address = MASK_OP_ABS_OFF18(ctx->opcode);
7975 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7976 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7977
7978 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
7979 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
7980 break;
7981 case OPC1_32_ABS_LEA:
7982 address = MASK_OP_ABS_OFF18(ctx->opcode);
7983 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7984 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
7985 break;
7986 /* ABSB-format */
7987 case OPC1_32_ABSB_ST_T:
7988 address = MASK_OP_ABS_OFF18(ctx->opcode);
7989 b = MASK_OP_ABSB_B(ctx->opcode);
7990 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
7991
7992 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7993 temp2 = tcg_temp_new();
7994
7995 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
7996 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
7997 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
7998 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
7999 break;
8000 /* B-format */
8001 case OPC1_32_B_CALL:
8002 case OPC1_32_B_CALLA:
8003 case OPC1_32_B_FCALL:
8004 case OPC1_32_B_FCALLA:
8005 case OPC1_32_B_J:
8006 case OPC1_32_B_JA:
8007 case OPC1_32_B_JL:
8008 case OPC1_32_B_JLA:
8009 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
8010 gen_compute_branch(ctx, op1, 0, 0, 0, address);
8011 break;
8012 /* Bit-format */
8013 case OPCM_32_BIT_ANDACC:
8014 decode_bit_andacc(ctx);
8015 break;
8016 case OPCM_32_BIT_LOGICAL_T1:
8017 decode_bit_logical_t(ctx);
8018 break;
8019 case OPCM_32_BIT_INSERT:
8020 decode_bit_insert(ctx);
8021 break;
8022 case OPCM_32_BIT_LOGICAL_T2:
8023 decode_bit_logical_t2(ctx);
8024 break;
8025 case OPCM_32_BIT_ORAND:
8026 decode_bit_orand(ctx);
8027 break;
8028 case OPCM_32_BIT_SH_LOGIC1:
8029 decode_bit_sh_logic1(ctx);
8030 break;
8031 case OPCM_32_BIT_SH_LOGIC2:
8032 decode_bit_sh_logic2(ctx);
8033 break;
8034 /* BO Format */
8035 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
8036 decode_bo_addrmode_post_pre_base(ctx);
8037 break;
8038 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
8039 decode_bo_addrmode_bitreverse_circular(ctx);
8040 break;
8041 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
8042 decode_bo_addrmode_ld_post_pre_base(ctx);
8043 break;
8044 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
8045 decode_bo_addrmode_ld_bitreverse_circular(ctx);
8046 break;
8047 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
8048 decode_bo_addrmode_stctx_post_pre_base(ctx);
8049 break;
8050 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
8051 decode_bo_addrmode_ldmst_bitreverse_circular(ctx);
8052 break;
8053 /* BOL-format */
8054 case OPC1_32_BOL_LD_A_LONGOFF:
8055 case OPC1_32_BOL_LD_W_LONGOFF:
8056 case OPC1_32_BOL_LEA_LONGOFF:
8057 case OPC1_32_BOL_ST_W_LONGOFF:
8058 case OPC1_32_BOL_ST_A_LONGOFF:
8059 case OPC1_32_BOL_LD_B_LONGOFF:
8060 case OPC1_32_BOL_LD_BU_LONGOFF:
8061 case OPC1_32_BOL_LD_H_LONGOFF:
8062 case OPC1_32_BOL_LD_HU_LONGOFF:
8063 case OPC1_32_BOL_ST_B_LONGOFF:
8064 case OPC1_32_BOL_ST_H_LONGOFF:
8065 decode_bol_opc(ctx, op1);
8066 break;
8067 /* BRC Format */
8068 case OPCM_32_BRC_EQ_NEQ:
8069 case OPCM_32_BRC_GE:
8070 case OPCM_32_BRC_JLT:
8071 case OPCM_32_BRC_JNE:
8072 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
8073 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
8074 r1 = MASK_OP_BRC_S1(ctx->opcode);
8075 gen_compute_branch(ctx, op1, r1, 0, const4, address);
8076 break;
8077 /* BRN Format */
8078 case OPCM_32_BRN_JTT:
8079 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
8080 r1 = MASK_OP_BRN_S1(ctx->opcode);
8081 gen_compute_branch(ctx, op1, r1, 0, 0, address);
8082 break;
8083 /* BRR Format */
8084 case OPCM_32_BRR_EQ_NEQ:
8085 case OPCM_32_BRR_ADDR_EQ_NEQ:
8086 case OPCM_32_BRR_GE:
8087 case OPCM_32_BRR_JLT:
8088 case OPCM_32_BRR_JNE:
8089 case OPCM_32_BRR_JNZ:
8090 case OPCM_32_BRR_LOOP:
8091 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
8092 r2 = MASK_OP_BRR_S2(ctx->opcode);
8093 r1 = MASK_OP_BRR_S1(ctx->opcode);
8094 gen_compute_branch(ctx, op1, r1, r2, 0, address);
8095 break;
8096 /* RC Format */
8097 case OPCM_32_RC_LOGICAL_SHIFT:
8098 decode_rc_logical_shift(ctx);
8099 break;
8100 case OPCM_32_RC_ACCUMULATOR:
8101 decode_rc_accumulator(ctx);
8102 break;
8103 case OPCM_32_RC_SERVICEROUTINE:
8104 decode_rc_serviceroutine(ctx);
8105 break;
8106 case OPCM_32_RC_MUL:
8107 decode_rc_mul(ctx);
8108 break;
8109 /* RCPW Format */
8110 case OPCM_32_RCPW_MASK_INSERT:
8111 decode_rcpw_insert(ctx);
8112 break;
8113 /* RCRR Format */
8114 case OPC1_32_RCRR_INSERT:
8115 r1 = MASK_OP_RCRR_S1(ctx->opcode);
8116 r2 = MASK_OP_RCRR_S3(ctx->opcode);
8117 r3 = MASK_OP_RCRR_D(ctx->opcode);
8118 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
8119 temp = tcg_const_i32(const16);
8120 temp2 = tcg_temp_new(); /* width*/
8121 temp3 = tcg_temp_new(); /* pos */
8122
8123 CHECK_REG_PAIR(r3);
8124
8125 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
8126 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
8127
8128 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
8129 break;
8130 /* RCRW Format */
8131 case OPCM_32_RCRW_MASK_INSERT:
8132 decode_rcrw_insert(ctx);
8133 break;
8134 /* RCR Format */
8135 case OPCM_32_RCR_COND_SELECT:
8136 decode_rcr_cond_select(ctx);
8137 break;
8138 case OPCM_32_RCR_MADD:
8139 decode_rcr_madd(ctx);
8140 break;
8141 case OPCM_32_RCR_MSUB:
8142 decode_rcr_msub(ctx);
8143 break;
8144 /* RLC Format */
8145 case OPC1_32_RLC_ADDI:
8146 case OPC1_32_RLC_ADDIH:
8147 case OPC1_32_RLC_ADDIH_A:
8148 case OPC1_32_RLC_MFCR:
8149 case OPC1_32_RLC_MOV:
8150 case OPC1_32_RLC_MOV_64:
8151 case OPC1_32_RLC_MOV_U:
8152 case OPC1_32_RLC_MOV_H:
8153 case OPC1_32_RLC_MOVH_A:
8154 case OPC1_32_RLC_MTCR:
8155 decode_rlc_opc(ctx, op1);
8156 break;
8157 /* RR Format */
8158 case OPCM_32_RR_ACCUMULATOR:
8159 decode_rr_accumulator(ctx);
8160 break;
8161 case OPCM_32_RR_LOGICAL_SHIFT:
8162 decode_rr_logical_shift(ctx);
8163 break;
8164 case OPCM_32_RR_ADDRESS:
8165 decode_rr_address(ctx);
8166 break;
8167 case OPCM_32_RR_IDIRECT:
8168 decode_rr_idirect(ctx);
8169 break;
8170 case OPCM_32_RR_DIVIDE:
8171 decode_rr_divide(ctx);
8172 break;
8173 /* RR1 Format */
8174 case OPCM_32_RR1_MUL:
8175 decode_rr1_mul(ctx);
8176 break;
8177 case OPCM_32_RR1_MULQ:
8178 decode_rr1_mulq(ctx);
8179 break;
8180 /* RR2 format */
8181 case OPCM_32_RR2_MUL:
8182 decode_rr2_mul(ctx);
8183 break;
8184 /* RRPW format */
8185 case OPCM_32_RRPW_EXTRACT_INSERT:
8186 decode_rrpw_extract_insert(ctx);
8187 break;
8188 case OPC1_32_RRPW_DEXTR:
8189 r1 = MASK_OP_RRPW_S1(ctx->opcode);
8190 r2 = MASK_OP_RRPW_S2(ctx->opcode);
8191 r3 = MASK_OP_RRPW_D(ctx->opcode);
8192 const16 = MASK_OP_RRPW_POS(ctx->opcode);
8193
8194 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1],
8195 32 - const16);
8196 break;
8197 /* RRR Format */
8198 case OPCM_32_RRR_COND_SELECT:
8199 decode_rrr_cond_select(ctx);
8200 break;
8201 case OPCM_32_RRR_DIVIDE:
8202 decode_rrr_divide(ctx);
8203 break;
8204 /* RRR2 Format */
8205 case OPCM_32_RRR2_MADD:
8206 decode_rrr2_madd(ctx);
8207 break;
8208 case OPCM_32_RRR2_MSUB:
8209 decode_rrr2_msub(ctx);
8210 break;
8211 /* RRR1 format */
8212 case OPCM_32_RRR1_MADD:
8213 decode_rrr1_madd(ctx);
8214 break;
8215 case OPCM_32_RRR1_MADDQ_H:
8216 decode_rrr1_maddq_h(ctx);
8217 break;
8218 case OPCM_32_RRR1_MADDSU_H:
8219 decode_rrr1_maddsu_h(ctx);
8220 break;
8221 case OPCM_32_RRR1_MSUB_H:
8222 decode_rrr1_msub(ctx);
8223 break;
8224 case OPCM_32_RRR1_MSUB_Q:
8225 decode_rrr1_msubq_h(ctx);
8226 break;
8227 case OPCM_32_RRR1_MSUBAD_H:
8228 decode_rrr1_msubad_h(ctx);
8229 break;
8230 /* RRRR format */
8231 case OPCM_32_RRRR_EXTRACT_INSERT:
8232 decode_rrrr_extract_insert(ctx);
8233 break;
8234 /* RRRW format */
8235 case OPCM_32_RRRW_EXTRACT_INSERT:
8236 decode_rrrw_extract_insert(ctx);
8237 break;
8238 /* SYS format */
8239 case OPCM_32_SYS_INTERRUPTS:
8240 decode_sys_interrupts(ctx);
8241 break;
8242 case OPC1_32_SYS_RSTV:
8243 tcg_gen_movi_tl(cpu_PSW_V, 0);
8244 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
8245 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
8246 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
8247 break;
8248 default:
8249 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8250 }
8251 }
8252
8253 static bool tricore_insn_is_16bit(uint32_t insn)
8254 {
8255 return (insn & 0x1) == 0;
8256 }
8257
8258 static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
8259 CPUState *cs)
8260 {
8261 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8262 CPUTriCoreState *env = cs->env_ptr;
8263 ctx->mem_idx = cpu_mmu_index(env, false);
8264 ctx->hflags = (uint32_t)ctx->base.tb->flags;
8265 ctx->features = env->features;
8266 }
8267
8268 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu)
8269 {
8270 }
8271
8272 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
8273 {
8274 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8275
8276 tcg_gen_insn_start(ctx->base.pc_next);
8277 }
8278
8279 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
8280 {
8281 /*
8282 * Return true if the insn at ctx->base.pc_next might cross a page boundary.
8283 * (False positives are OK, false negatives are not.)
8284 * Our caller ensures we are only called if dc->base.pc_next is less than
8285 * 4 bytes from the page boundary, so we cross the page if the first
8286 * 16 bits indicate that this is a 32 bit insn.
8287 */
8288 uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
8289
8290 return !tricore_insn_is_16bit(insn);
8291 }
8292
8293
8294 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
8295 {
8296 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8297 CPUTriCoreState *env = cpu->env_ptr;
8298 uint16_t insn_lo;
8299 bool is_16bit;
8300
8301 insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
8302 is_16bit = tricore_insn_is_16bit(insn_lo);
8303 if (is_16bit) {
8304 ctx->opcode = insn_lo;
8305 ctx->pc_succ_insn = ctx->base.pc_next + 2;
8306 decode_16Bit_opc(ctx);
8307 } else {
8308 uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
8309 ctx->opcode = insn_hi << 16 | insn_lo;
8310 ctx->pc_succ_insn = ctx->base.pc_next + 4;
8311 decode_32Bit_opc(ctx);
8312 }
8313 ctx->base.pc_next = ctx->pc_succ_insn;
8314
8315 if (ctx->base.is_jmp == DISAS_NEXT) {
8316 target_ulong page_start;
8317
8318 page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
8319 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE
8320 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3
8321 && insn_crosses_page(env, ctx))) {
8322 ctx->base.is_jmp = DISAS_TOO_MANY;
8323 }
8324 }
8325 }
8326
8327 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
8328 {
8329 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8330
8331 switch (ctx->base.is_jmp) {
8332 case DISAS_TOO_MANY:
8333 gen_goto_tb(ctx, 0, ctx->base.pc_next);
8334 break;
8335 case DISAS_NORETURN:
8336 break;
8337 default:
8338 g_assert_not_reached();
8339 }
8340 }
8341
8342 static void tricore_tr_disas_log(const DisasContextBase *dcbase,
8343 CPUState *cpu, FILE *logfile)
8344 {
8345 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
8346 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
8347 }
8348
8349 static const TranslatorOps tricore_tr_ops = {
8350 .init_disas_context = tricore_tr_init_disas_context,
8351 .tb_start = tricore_tr_tb_start,
8352 .insn_start = tricore_tr_insn_start,
8353 .translate_insn = tricore_tr_translate_insn,
8354 .tb_stop = tricore_tr_tb_stop,
8355 .disas_log = tricore_tr_disas_log,
8356 };
8357
8358
8359 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
8360 target_ulong pc, void *host_pc)
8361 {
8362 DisasContext ctx;
8363 translator_loop(cs, tb, max_insns, pc, host_pc,
8364 &tricore_tr_ops, &ctx.base);
8365 }
8366
8367 /*
8368 *
8369 * Initialization
8370 *
8371 */
8372
8373 void cpu_state_reset(CPUTriCoreState *env)
8374 {
8375 /* Reset Regs to Default Value */
8376 env->PSW = 0xb80;
8377 fpu_set_state(env);
8378 }
8379
8380 static void tricore_tcg_init_csfr(void)
8381 {
8382 cpu_PCXI = tcg_global_mem_new(cpu_env,
8383 offsetof(CPUTriCoreState, PCXI), "PCXI");
8384 cpu_PSW = tcg_global_mem_new(cpu_env,
8385 offsetof(CPUTriCoreState, PSW), "PSW");
8386 cpu_PC = tcg_global_mem_new(cpu_env,
8387 offsetof(CPUTriCoreState, PC), "PC");
8388 cpu_ICR = tcg_global_mem_new(cpu_env,
8389 offsetof(CPUTriCoreState, ICR), "ICR");
8390 }
8391
8392 void tricore_tcg_init(void)
8393 {
8394 int i;
8395
8396 /* reg init */
8397 for (i = 0 ; i < 16 ; i++) {
8398 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
8399 offsetof(CPUTriCoreState, gpr_a[i]),
8400 regnames_a[i]);
8401 }
8402 for (i = 0 ; i < 16 ; i++) {
8403 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
8404 offsetof(CPUTriCoreState, gpr_d[i]),
8405 regnames_d[i]);
8406 }
8407 tricore_tcg_init_csfr();
8408 /* init PSW flag cache */
8409 cpu_PSW_C = tcg_global_mem_new(cpu_env,
8410 offsetof(CPUTriCoreState, PSW_USB_C),
8411 "PSW_C");
8412 cpu_PSW_V = tcg_global_mem_new(cpu_env,
8413 offsetof(CPUTriCoreState, PSW_USB_V),
8414 "PSW_V");
8415 cpu_PSW_SV = tcg_global_mem_new(cpu_env,
8416 offsetof(CPUTriCoreState, PSW_USB_SV),
8417 "PSW_SV");
8418 cpu_PSW_AV = tcg_global_mem_new(cpu_env,
8419 offsetof(CPUTriCoreState, PSW_USB_AV),
8420 "PSW_AV");
8421 cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
8422 offsetof(CPUTriCoreState, PSW_USB_SAV),
8423 "PSW_SAV");
8424 }
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