]> git.proxmox.com Git - mirror_qemu.git/blob - target/tricore/translate.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target/tricore: Swap src and dst reg for RCRR_INSERT
[mirror_qemu.git] / target / tricore / translate.c
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "exec/cpu_ldst.h"
27 #include "qemu/qemu-print.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "tricore-opcodes.h"
33 #include "exec/translator.h"
34 #include "exec/log.h"
35
36 #define HELPER_H "helper.h"
37 #include "exec/helper-info.c.inc"
38 #undef HELPER_H
39
40 #define DISAS_EXIT DISAS_TARGET_0
41 #define DISAS_EXIT_UPDATE DISAS_TARGET_1
42 #define DISAS_JUMP DISAS_TARGET_2
43
44 /*
45 * TCG registers
46 */
47 static TCGv cpu_PC;
48 static TCGv cpu_PCXI;
49 static TCGv cpu_PSW;
50 static TCGv cpu_ICR;
51 /* GPR registers */
52 static TCGv cpu_gpr_a[16];
53 static TCGv cpu_gpr_d[16];
54 /* PSW Flag cache */
55 static TCGv cpu_PSW_C;
56 static TCGv cpu_PSW_V;
57 static TCGv cpu_PSW_SV;
58 static TCGv cpu_PSW_AV;
59 static TCGv cpu_PSW_SAV;
60
61 static const char *regnames_a[] = {
62 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
63 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
64 "a12" , "a13" , "a14" , "a15",
65 };
66
67 static const char *regnames_d[] = {
68 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
69 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
70 "d12" , "d13" , "d14" , "d15",
71 };
72
73 typedef struct DisasContext {
74 DisasContextBase base;
75 target_ulong pc_succ_insn;
76 uint32_t opcode;
77 /* Routine used to access memory */
78 int mem_idx;
79 int priv;
80 uint64_t features;
81 uint32_t icr_ie_mask, icr_ie_offset;
82 } DisasContext;
83
84 static int has_feature(DisasContext *ctx, int feature)
85 {
86 return (ctx->features & (1ULL << feature)) != 0;
87 }
88
89 enum {
90 MODE_LL = 0,
91 MODE_LU = 1,
92 MODE_UL = 2,
93 MODE_UU = 3,
94 };
95
96 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
97 {
98 TriCoreCPU *cpu = TRICORE_CPU(cs);
99 CPUTriCoreState *env = &cpu->env;
100 uint32_t psw;
101 int i;
102
103 psw = psw_read(env);
104
105 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
106 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
107 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
108 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
109 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
110 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
111
112 for (i = 0; i < 16; ++i) {
113 if ((i & 3) == 0) {
114 qemu_fprintf(f, "\nGPR A%02d:", i);
115 }
116 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
117 }
118 for (i = 0; i < 16; ++i) {
119 if ((i & 3) == 0) {
120 qemu_fprintf(f, "\nGPR D%02d:", i);
121 }
122 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
123 }
124 qemu_fprintf(f, "\n");
125 }
126
127 /*
128 * Functions to generate micro-ops
129 */
130
131 /* Macros for generating helpers */
132
133 #define gen_helper_1arg(name, arg) do { \
134 TCGv_i32 helper_tmp = tcg_constant_i32(arg); \
135 gen_helper_##name(cpu_env, helper_tmp); \
136 } while (0)
137
138 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
139 TCGv arg00 = tcg_temp_new(); \
140 TCGv arg01 = tcg_temp_new(); \
141 TCGv arg11 = tcg_temp_new(); \
142 tcg_gen_sari_tl(arg00, arg0, 16); \
143 tcg_gen_ext16s_tl(arg01, arg0); \
144 tcg_gen_ext16s_tl(arg11, arg1); \
145 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
146 } while (0)
147
148 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
149 TCGv arg00 = tcg_temp_new(); \
150 TCGv arg01 = tcg_temp_new(); \
151 TCGv arg10 = tcg_temp_new(); \
152 TCGv arg11 = tcg_temp_new(); \
153 tcg_gen_sari_tl(arg00, arg0, 16); \
154 tcg_gen_ext16s_tl(arg01, arg0); \
155 tcg_gen_sari_tl(arg11, arg1, 16); \
156 tcg_gen_ext16s_tl(arg10, arg1); \
157 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
158 } while (0)
159
160 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
161 TCGv arg00 = tcg_temp_new(); \
162 TCGv arg01 = tcg_temp_new(); \
163 TCGv arg10 = tcg_temp_new(); \
164 TCGv arg11 = tcg_temp_new(); \
165 tcg_gen_sari_tl(arg00, arg0, 16); \
166 tcg_gen_ext16s_tl(arg01, arg0); \
167 tcg_gen_sari_tl(arg10, arg1, 16); \
168 tcg_gen_ext16s_tl(arg11, arg1); \
169 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
170 } while (0)
171
172 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
173 TCGv arg00 = tcg_temp_new(); \
174 TCGv arg01 = tcg_temp_new(); \
175 TCGv arg11 = tcg_temp_new(); \
176 tcg_gen_sari_tl(arg01, arg0, 16); \
177 tcg_gen_ext16s_tl(arg00, arg0); \
178 tcg_gen_sari_tl(arg11, arg1, 16); \
179 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
180 } while (0)
181
182 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
183 TCGv_i64 ret = tcg_temp_new_i64(); \
184 TCGv_i64 arg1 = tcg_temp_new_i64(); \
185 \
186 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
187 gen_helper_##name(ret, arg1, arg2); \
188 tcg_gen_extr_i64_i32(rl, rh, ret); \
189 } while (0)
190
191 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
192 TCGv_i64 ret = tcg_temp_new_i64(); \
193 \
194 gen_helper_##name(ret, cpu_env, arg1, arg2); \
195 tcg_gen_extr_i64_i32(rl, rh, ret); \
196 } while (0)
197
198 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
199 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
200 ((offset & 0x0fffff) << 1))
201
202 /* For two 32-bit registers used a 64-bit register, the first
203 registernumber needs to be even. Otherwise we trap. */
204 static inline void generate_trap(DisasContext *ctx, int class, int tin);
205 #define CHECK_REG_PAIR(reg) do { \
206 if (reg & 0x1) { \
207 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
208 } \
209 } while (0)
210
211 /* Functions for load/save to/from memory */
212
213 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
214 int16_t con, MemOp mop)
215 {
216 TCGv temp = tcg_temp_new();
217 tcg_gen_addi_tl(temp, r2, con);
218 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
219 }
220
221 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
222 int16_t con, MemOp mop)
223 {
224 TCGv temp = tcg_temp_new();
225 tcg_gen_addi_tl(temp, r2, con);
226 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
227 }
228
229 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
230 {
231 TCGv_i64 temp = tcg_temp_new_i64();
232
233 tcg_gen_concat_i32_i64(temp, rl, rh);
234 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ);
235 }
236
237 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
238 DisasContext *ctx)
239 {
240 TCGv temp = tcg_temp_new();
241 tcg_gen_addi_tl(temp, base, con);
242 gen_st_2regs_64(rh, rl, temp, ctx);
243 }
244
245 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
246 {
247 TCGv_i64 temp = tcg_temp_new_i64();
248
249 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ);
250 /* write back to two 32 bit regs */
251 tcg_gen_extr_i64_i32(rl, rh, temp);
252 }
253
254 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
255 DisasContext *ctx)
256 {
257 TCGv temp = tcg_temp_new();
258 tcg_gen_addi_tl(temp, base, con);
259 gen_ld_2regs_64(rh, rl, temp, ctx);
260 }
261
262 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
263 MemOp mop)
264 {
265 TCGv temp = tcg_temp_new();
266 tcg_gen_addi_tl(temp, r2, off);
267 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
268 tcg_gen_mov_tl(r2, temp);
269 }
270
271 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
272 MemOp mop)
273 {
274 TCGv temp = tcg_temp_new();
275 tcg_gen_addi_tl(temp, r2, off);
276 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
277 tcg_gen_mov_tl(r2, temp);
278 }
279
280 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
281 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
282 {
283 TCGv temp = tcg_temp_new();
284 TCGv temp2 = tcg_temp_new();
285
286 CHECK_REG_PAIR(ereg);
287 /* temp = (M(EA, word) */
288 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
289 /* temp = temp & ~E[a][63:32]) */
290 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
291 /* temp2 = (E[a][31:0] & E[a][63:32]); */
292 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
293 /* temp = temp | temp2; */
294 tcg_gen_or_tl(temp, temp, temp2);
295 /* M(EA, word) = temp; */
296 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
297 }
298
299 /* tmp = M(EA, word);
300 M(EA, word) = D[a];
301 D[a] = tmp[31:0];*/
302 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
303 {
304 TCGv temp = tcg_temp_new();
305
306 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
307 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
308 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
309 }
310
311 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
312 {
313 TCGv temp = tcg_temp_new();
314 TCGv temp2 = tcg_temp_new();
315 CHECK_REG_PAIR(reg);
316 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
317 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
318 cpu_gpr_d[reg], temp);
319 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
320 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
321 }
322
323 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
324 {
325 TCGv temp = tcg_temp_new();
326 TCGv temp2 = tcg_temp_new();
327 TCGv temp3 = tcg_temp_new();
328 CHECK_REG_PAIR(reg);
329 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
330 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
331 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
332 tcg_gen_or_tl(temp2, temp2, temp3);
333 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
334 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
335 }
336
337 /* We generate loads and store to core special function register (csfr) through
338 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
339 macros R, A and E, which allow read-only, all and endinit protected access.
340 These macros also specify in which ISA version the csfr was introduced. */
341 #define R(ADDRESS, REG, FEATURE) \
342 case ADDRESS: \
343 if (has_feature(ctx, FEATURE)) { \
344 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
345 } \
346 break;
347 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
348 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
349 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
350 {
351 /* since we're caching PSW make this a special case */
352 if (offset == 0xfe04) {
353 gen_helper_psw_read(ret, cpu_env);
354 } else {
355 switch (offset) {
356 #include "csfr.h.inc"
357 }
358 }
359 }
360 #undef R
361 #undef A
362 #undef E
363
364 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
365 since no exception occurs */
366 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
367 case ADDRESS: \
368 if (has_feature(ctx, FEATURE)) { \
369 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
370 } \
371 break;
372 /* Endinit protected registers
373 TODO: Since the endinit bit is in a register of a not yet implemented
374 watchdog device, we handle endinit protected registers like
375 all-access registers for now. */
376 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
377 static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
378 int32_t offset)
379 {
380 if (ctx->priv == TRICORE_PRIV_SM) {
381 /* since we're caching PSW make this a special case */
382 if (offset == 0xfe04) {
383 gen_helper_psw_write(cpu_env, r1);
384 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
385 } else {
386 switch (offset) {
387 #include "csfr.h.inc"
388 }
389 }
390 } else {
391 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
392 }
393 }
394
395 /* Functions for arithmetic instructions */
396
397 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
398 {
399 TCGv t0 = tcg_temp_new_i32();
400 TCGv result = tcg_temp_new_i32();
401 /* Addition and set V/SV bits */
402 tcg_gen_add_tl(result, r1, r2);
403 /* calc V bit */
404 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
405 tcg_gen_xor_tl(t0, r1, r2);
406 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
407 /* Calc SV bit */
408 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
409 /* Calc AV/SAV bits */
410 tcg_gen_add_tl(cpu_PSW_AV, result, result);
411 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
412 /* calc SAV */
413 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
414 /* write back result */
415 tcg_gen_mov_tl(ret, result);
416 }
417
418 static inline void
419 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
420 {
421 TCGv temp = tcg_temp_new();
422 TCGv_i64 t0 = tcg_temp_new_i64();
423 TCGv_i64 t1 = tcg_temp_new_i64();
424 TCGv_i64 result = tcg_temp_new_i64();
425
426 tcg_gen_add_i64(result, r1, r2);
427 /* calc v bit */
428 tcg_gen_xor_i64(t1, result, r1);
429 tcg_gen_xor_i64(t0, r1, r2);
430 tcg_gen_andc_i64(t1, t1, t0);
431 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
432 /* calc SV bit */
433 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
434 /* calc AV/SAV bits */
435 tcg_gen_extrh_i64_i32(temp, result);
436 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
437 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
438 /* calc SAV */
439 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
440 /* write back result */
441 tcg_gen_mov_i64(ret, result);
442 }
443
444 static inline void
445 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
446 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
447 void(*op2)(TCGv, TCGv, TCGv))
448 {
449 TCGv temp = tcg_temp_new();
450 TCGv temp2 = tcg_temp_new();
451 TCGv temp3 = tcg_temp_new();
452 TCGv temp4 = tcg_temp_new();
453
454 (*op1)(temp, r1_low, r2);
455 /* calc V0 bit */
456 tcg_gen_xor_tl(temp2, temp, r1_low);
457 tcg_gen_xor_tl(temp3, r1_low, r2);
458 if (op1 == tcg_gen_add_tl) {
459 tcg_gen_andc_tl(temp2, temp2, temp3);
460 } else {
461 tcg_gen_and_tl(temp2, temp2, temp3);
462 }
463
464 (*op2)(temp3, r1_high, r3);
465 /* calc V1 bit */
466 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
467 tcg_gen_xor_tl(temp4, r1_high, r3);
468 if (op2 == tcg_gen_add_tl) {
469 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
470 } else {
471 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
472 }
473 /* combine V0/V1 bits */
474 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
475 /* calc sv bit */
476 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
477 /* write result */
478 tcg_gen_mov_tl(ret_low, temp);
479 tcg_gen_mov_tl(ret_high, temp3);
480 /* calc AV bit */
481 tcg_gen_add_tl(temp, ret_low, ret_low);
482 tcg_gen_xor_tl(temp, temp, ret_low);
483 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
484 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
485 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
486 /* calc SAV bit */
487 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
488 }
489
490 /* ret = r2 + (r1 * r3); */
491 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
492 {
493 TCGv_i64 t1 = tcg_temp_new_i64();
494 TCGv_i64 t2 = tcg_temp_new_i64();
495 TCGv_i64 t3 = tcg_temp_new_i64();
496
497 tcg_gen_ext_i32_i64(t1, r1);
498 tcg_gen_ext_i32_i64(t2, r2);
499 tcg_gen_ext_i32_i64(t3, r3);
500
501 tcg_gen_mul_i64(t1, t1, t3);
502 tcg_gen_add_i64(t1, t2, t1);
503
504 tcg_gen_extrl_i64_i32(ret, t1);
505 /* calc V
506 t1 > 0x7fffffff */
507 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
508 /* t1 < -0x80000000 */
509 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
510 tcg_gen_or_i64(t2, t2, t3);
511 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
512 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
513 /* Calc SV bit */
514 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
515 /* Calc AV/SAV bits */
516 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
517 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
518 /* calc SAV */
519 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
520 }
521
522 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
523 {
524 TCGv temp = tcg_constant_i32(con);
525 gen_madd32_d(ret, r1, r2, temp);
526 }
527
528 static inline void
529 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
530 TCGv r3)
531 {
532 TCGv t1 = tcg_temp_new();
533 TCGv t2 = tcg_temp_new();
534 TCGv t3 = tcg_temp_new();
535 TCGv t4 = tcg_temp_new();
536
537 tcg_gen_muls2_tl(t1, t2, r1, r3);
538 /* only the add can overflow */
539 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
540 /* calc V bit */
541 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
542 tcg_gen_xor_tl(t1, r2_high, t2);
543 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
544 /* Calc SV bit */
545 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
546 /* Calc AV/SAV bits */
547 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
548 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
549 /* calc SAV */
550 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
551 /* write back the result */
552 tcg_gen_mov_tl(ret_low, t3);
553 tcg_gen_mov_tl(ret_high, t4);
554 }
555
556 static inline void
557 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
558 TCGv r3)
559 {
560 TCGv_i64 t1 = tcg_temp_new_i64();
561 TCGv_i64 t2 = tcg_temp_new_i64();
562 TCGv_i64 t3 = tcg_temp_new_i64();
563
564 tcg_gen_extu_i32_i64(t1, r1);
565 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
566 tcg_gen_extu_i32_i64(t3, r3);
567
568 tcg_gen_mul_i64(t1, t1, t3);
569 tcg_gen_add_i64(t2, t2, t1);
570 /* write back result */
571 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
572 /* only the add overflows, if t2 < t1
573 calc V bit */
574 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
575 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
576 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
577 /* Calc SV bit */
578 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
579 /* Calc AV/SAV bits */
580 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
581 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
582 /* calc SAV */
583 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
584 }
585
586 static inline void
587 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
588 int32_t con)
589 {
590 TCGv temp = tcg_constant_i32(con);
591 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
592 }
593
594 static inline void
595 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
596 int32_t con)
597 {
598 TCGv temp = tcg_constant_i32(con);
599 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
600 }
601
602 static inline void
603 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
604 TCGv r3, uint32_t n, uint32_t mode)
605 {
606 TCGv t_n = tcg_constant_i32(n);
607 TCGv temp = tcg_temp_new();
608 TCGv temp2 = tcg_temp_new();
609 TCGv_i64 temp64 = tcg_temp_new_i64();
610 switch (mode) {
611 case MODE_LL:
612 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
613 break;
614 case MODE_LU:
615 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
616 break;
617 case MODE_UL:
618 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
619 break;
620 case MODE_UU:
621 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
622 break;
623 }
624 tcg_gen_extr_i64_i32(temp, temp2, temp64);
625 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
626 tcg_gen_add_tl, tcg_gen_add_tl);
627 }
628
629 static inline void
630 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
631 TCGv r3, uint32_t n, uint32_t mode)
632 {
633 TCGv t_n = tcg_constant_i32(n);
634 TCGv temp = tcg_temp_new();
635 TCGv temp2 = tcg_temp_new();
636 TCGv_i64 temp64 = tcg_temp_new_i64();
637 switch (mode) {
638 case MODE_LL:
639 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
640 break;
641 case MODE_LU:
642 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
643 break;
644 case MODE_UL:
645 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
646 break;
647 case MODE_UU:
648 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
649 break;
650 }
651 tcg_gen_extr_i64_i32(temp, temp2, temp64);
652 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
653 tcg_gen_sub_tl, tcg_gen_add_tl);
654 }
655
656 static inline void
657 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
658 TCGv r3, uint32_t n, uint32_t mode)
659 {
660 TCGv t_n = tcg_constant_i32(n);
661 TCGv_i64 temp64 = tcg_temp_new_i64();
662 TCGv_i64 temp64_2 = tcg_temp_new_i64();
663 TCGv_i64 temp64_3 = tcg_temp_new_i64();
664 switch (mode) {
665 case MODE_LL:
666 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
667 break;
668 case MODE_LU:
669 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
670 break;
671 case MODE_UL:
672 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
673 break;
674 case MODE_UU:
675 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
676 break;
677 }
678 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
679 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
680 tcg_gen_ext32s_i64(temp64, temp64); /* low */
681 tcg_gen_sub_i64(temp64, temp64_2, temp64);
682 tcg_gen_shli_i64(temp64, temp64, 16);
683
684 gen_add64_d(temp64_2, temp64_3, temp64);
685 /* write back result */
686 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
687 }
688
689 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
690
691 static inline void
692 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
693 TCGv r3, uint32_t n, uint32_t mode)
694 {
695 TCGv t_n = tcg_constant_i32(n);
696 TCGv temp = tcg_temp_new();
697 TCGv temp2 = tcg_temp_new();
698 TCGv temp3 = tcg_temp_new();
699 TCGv_i64 temp64 = tcg_temp_new_i64();
700
701 switch (mode) {
702 case MODE_LL:
703 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
704 break;
705 case MODE_LU:
706 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
707 break;
708 case MODE_UL:
709 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
710 break;
711 case MODE_UU:
712 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
713 break;
714 }
715 tcg_gen_extr_i64_i32(temp, temp2, temp64);
716 gen_adds(ret_low, r1_low, temp);
717 tcg_gen_mov_tl(temp, cpu_PSW_V);
718 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
719 gen_adds(ret_high, r1_high, temp2);
720 /* combine v bits */
721 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
722 /* combine av bits */
723 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
724 }
725
726 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
727
728 static inline void
729 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
730 TCGv r3, uint32_t n, uint32_t mode)
731 {
732 TCGv t_n = tcg_constant_i32(n);
733 TCGv temp = tcg_temp_new();
734 TCGv temp2 = tcg_temp_new();
735 TCGv temp3 = tcg_temp_new();
736 TCGv_i64 temp64 = tcg_temp_new_i64();
737
738 switch (mode) {
739 case MODE_LL:
740 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
741 break;
742 case MODE_LU:
743 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
744 break;
745 case MODE_UL:
746 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
747 break;
748 case MODE_UU:
749 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
750 break;
751 }
752 tcg_gen_extr_i64_i32(temp, temp2, temp64);
753 gen_subs(ret_low, r1_low, temp);
754 tcg_gen_mov_tl(temp, cpu_PSW_V);
755 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
756 gen_adds(ret_high, r1_high, temp2);
757 /* combine v bits */
758 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
759 /* combine av bits */
760 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
761 }
762
763 static inline void
764 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
765 TCGv r3, uint32_t n, uint32_t mode)
766 {
767 TCGv t_n = tcg_constant_i32(n);
768 TCGv_i64 temp64 = tcg_temp_new_i64();
769 TCGv_i64 temp64_2 = tcg_temp_new_i64();
770
771 switch (mode) {
772 case MODE_LL:
773 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
774 break;
775 case MODE_LU:
776 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
777 break;
778 case MODE_UL:
779 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
780 break;
781 case MODE_UU:
782 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
783 break;
784 }
785 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
786 tcg_gen_ext32s_i64(temp64, temp64); /* low */
787 tcg_gen_sub_i64(temp64, temp64_2, temp64);
788 tcg_gen_shli_i64(temp64, temp64, 16);
789 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
790
791 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
792 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
793 }
794
795
796 static inline void
797 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
798 TCGv r3, uint32_t n, uint32_t mode)
799 {
800 TCGv t_n = tcg_constant_i32(n);
801 TCGv_i64 temp64 = tcg_temp_new_i64();
802 TCGv_i64 temp64_2 = tcg_temp_new_i64();
803 TCGv_i64 temp64_3 = tcg_temp_new_i64();
804 switch (mode) {
805 case MODE_LL:
806 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
807 break;
808 case MODE_LU:
809 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
810 break;
811 case MODE_UL:
812 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
813 break;
814 case MODE_UU:
815 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
816 break;
817 }
818 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
819 gen_add64_d(temp64_3, temp64_2, temp64);
820 /* write back result */
821 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
822 }
823
824 static inline void
825 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
826 TCGv r3, uint32_t n, uint32_t mode)
827 {
828 TCGv t_n = tcg_constant_i32(n);
829 TCGv_i64 temp64 = tcg_temp_new_i64();
830 TCGv_i64 temp64_2 = tcg_temp_new_i64();
831 switch (mode) {
832 case MODE_LL:
833 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
834 break;
835 case MODE_LU:
836 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
837 break;
838 case MODE_UL:
839 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
840 break;
841 case MODE_UU:
842 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
843 break;
844 }
845 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
846 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
847 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
848 }
849
850 static inline void
851 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
852 uint32_t mode)
853 {
854 TCGv t_n = tcg_constant_i32(n);
855 TCGv_i64 temp64 = tcg_temp_new_i64();
856 switch (mode) {
857 case MODE_LL:
858 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
859 break;
860 case MODE_LU:
861 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
862 break;
863 case MODE_UL:
864 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
865 break;
866 case MODE_UU:
867 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
868 break;
869 }
870 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
871 }
872
873 static inline void
874 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
875 {
876 TCGv temp = tcg_temp_new();
877 TCGv temp2 = tcg_temp_new();
878
879 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
880 tcg_gen_shli_tl(temp, r1, 16);
881 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
882 }
883
884 static inline void
885 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
886 {
887 TCGv t_n = tcg_constant_i32(n);
888 TCGv temp = tcg_temp_new();
889 TCGv temp2 = tcg_temp_new();
890 TCGv_i64 temp64 = tcg_temp_new_i64();
891 switch (mode) {
892 case MODE_LL:
893 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
894 break;
895 case MODE_LU:
896 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
897 break;
898 case MODE_UL:
899 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
900 break;
901 case MODE_UU:
902 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
903 break;
904 }
905 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
906 tcg_gen_shli_tl(temp, r1, 16);
907 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
908 }
909
910
911 static inline void
912 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
913 uint32_t n, uint32_t mode)
914 {
915 TCGv t_n = tcg_constant_i32(n);
916 TCGv_i64 temp64 = tcg_temp_new_i64();
917 switch (mode) {
918 case MODE_LL:
919 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
920 break;
921 case MODE_LU:
922 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
923 break;
924 case MODE_UL:
925 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
926 break;
927 case MODE_UU:
928 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
929 break;
930 }
931 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
932 }
933
934 static inline void
935 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
936 {
937 TCGv temp = tcg_temp_new();
938 TCGv temp2 = tcg_temp_new();
939
940 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
941 tcg_gen_shli_tl(temp, r1, 16);
942 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
943 }
944
945 static inline void
946 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
947 {
948 TCGv t_n = tcg_constant_i32(n);
949 TCGv temp = tcg_temp_new();
950 TCGv temp2 = tcg_temp_new();
951 TCGv_i64 temp64 = tcg_temp_new_i64();
952 switch (mode) {
953 case MODE_LL:
954 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
955 break;
956 case MODE_LU:
957 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
958 break;
959 case MODE_UL:
960 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
961 break;
962 case MODE_UU:
963 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
964 break;
965 }
966 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
967 tcg_gen_shli_tl(temp, r1, 16);
968 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
969 }
970
971 static inline void
972 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
973 {
974 TCGv t_n = tcg_constant_i32(n);
975 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n);
976 }
977
978 static inline void
979 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
980 {
981 TCGv t_n = tcg_constant_i32(n);
982 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n);
983 }
984
985 static inline void
986 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
987 uint32_t up_shift)
988 {
989 TCGv temp = tcg_temp_new();
990 TCGv temp2 = tcg_temp_new();
991 TCGv temp3 = tcg_temp_new();
992 TCGv_i64 t1 = tcg_temp_new_i64();
993 TCGv_i64 t2 = tcg_temp_new_i64();
994 TCGv_i64 t3 = tcg_temp_new_i64();
995
996 tcg_gen_ext_i32_i64(t2, arg2);
997 tcg_gen_ext_i32_i64(t3, arg3);
998
999 tcg_gen_mul_i64(t2, t2, t3);
1000 tcg_gen_shli_i64(t2, t2, n);
1001
1002 tcg_gen_ext_i32_i64(t1, arg1);
1003 tcg_gen_sari_i64(t2, t2, up_shift);
1004
1005 tcg_gen_add_i64(t3, t1, t2);
1006 tcg_gen_extrl_i64_i32(temp3, t3);
1007 /* calc v bit */
1008 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1009 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1010 tcg_gen_or_i64(t1, t1, t2);
1011 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1012 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1013 /* We produce an overflow on the host if the mul before was
1014 (0x80000000 * 0x80000000) << 1). If this is the
1015 case, we negate the ovf. */
1016 if (n == 1) {
1017 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1018 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1019 tcg_gen_and_tl(temp, temp, temp2);
1020 tcg_gen_shli_tl(temp, temp, 31);
1021 /* negate v bit, if special condition */
1022 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1023 }
1024 /* Calc SV bit */
1025 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1026 /* Calc AV/SAV bits */
1027 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1028 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1029 /* calc SAV */
1030 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1031 /* write back result */
1032 tcg_gen_mov_tl(ret, temp3);
1033 }
1034
1035 static inline void
1036 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1037 {
1038 TCGv temp = tcg_temp_new();
1039 TCGv temp2 = tcg_temp_new();
1040 if (n == 0) {
1041 tcg_gen_mul_tl(temp, arg2, arg3);
1042 } else { /* n is expected to be 1 */
1043 tcg_gen_mul_tl(temp, arg2, arg3);
1044 tcg_gen_shli_tl(temp, temp, 1);
1045 /* catch special case r1 = r2 = 0x8000 */
1046 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1047 tcg_gen_sub_tl(temp, temp, temp2);
1048 }
1049 gen_add_d(ret, arg1, temp);
1050 }
1051
1052 static inline void
1053 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1054 {
1055 TCGv temp = tcg_temp_new();
1056 TCGv temp2 = tcg_temp_new();
1057 if (n == 0) {
1058 tcg_gen_mul_tl(temp, arg2, arg3);
1059 } else { /* n is expected to be 1 */
1060 tcg_gen_mul_tl(temp, arg2, arg3);
1061 tcg_gen_shli_tl(temp, temp, 1);
1062 /* catch special case r1 = r2 = 0x8000 */
1063 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1064 tcg_gen_sub_tl(temp, temp, temp2);
1065 }
1066 gen_adds(ret, arg1, temp);
1067 }
1068
1069 static inline void
1070 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1071 TCGv arg3, uint32_t n)
1072 {
1073 TCGv temp = tcg_temp_new();
1074 TCGv temp2 = tcg_temp_new();
1075 TCGv_i64 t1 = tcg_temp_new_i64();
1076 TCGv_i64 t2 = tcg_temp_new_i64();
1077 TCGv_i64 t3 = tcg_temp_new_i64();
1078
1079 if (n == 0) {
1080 tcg_gen_mul_tl(temp, arg2, arg3);
1081 } else { /* n is expected to be 1 */
1082 tcg_gen_mul_tl(temp, arg2, arg3);
1083 tcg_gen_shli_tl(temp, temp, 1);
1084 /* catch special case r1 = r2 = 0x8000 */
1085 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1086 tcg_gen_sub_tl(temp, temp, temp2);
1087 }
1088 tcg_gen_ext_i32_i64(t2, temp);
1089 tcg_gen_shli_i64(t2, t2, 16);
1090 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1091 gen_add64_d(t3, t1, t2);
1092 /* write back result */
1093 tcg_gen_extr_i64_i32(rl, rh, t3);
1094 }
1095
1096 static inline void
1097 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1098 TCGv arg3, uint32_t n)
1099 {
1100 TCGv temp = tcg_temp_new();
1101 TCGv temp2 = tcg_temp_new();
1102 TCGv_i64 t1 = tcg_temp_new_i64();
1103 TCGv_i64 t2 = tcg_temp_new_i64();
1104
1105 if (n == 0) {
1106 tcg_gen_mul_tl(temp, arg2, arg3);
1107 } else { /* n is expected to be 1 */
1108 tcg_gen_mul_tl(temp, arg2, arg3);
1109 tcg_gen_shli_tl(temp, temp, 1);
1110 /* catch special case r1 = r2 = 0x8000 */
1111 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1112 tcg_gen_sub_tl(temp, temp, temp2);
1113 }
1114 tcg_gen_ext_i32_i64(t2, temp);
1115 tcg_gen_shli_i64(t2, t2, 16);
1116 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1117
1118 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1119 tcg_gen_extr_i64_i32(rl, rh, t1);
1120 }
1121
1122 static inline void
1123 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1124 TCGv arg3, uint32_t n)
1125 {
1126 TCGv_i64 t1 = tcg_temp_new_i64();
1127 TCGv_i64 t2 = tcg_temp_new_i64();
1128 TCGv_i64 t3 = tcg_temp_new_i64();
1129 TCGv_i64 t4 = tcg_temp_new_i64();
1130 TCGv temp, temp2;
1131
1132 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1133 tcg_gen_ext_i32_i64(t2, arg2);
1134 tcg_gen_ext_i32_i64(t3, arg3);
1135
1136 tcg_gen_mul_i64(t2, t2, t3);
1137 if (n != 0) {
1138 tcg_gen_shli_i64(t2, t2, 1);
1139 }
1140 tcg_gen_add_i64(t4, t1, t2);
1141 /* calc v bit */
1142 tcg_gen_xor_i64(t3, t4, t1);
1143 tcg_gen_xor_i64(t2, t1, t2);
1144 tcg_gen_andc_i64(t3, t3, t2);
1145 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1146 /* We produce an overflow on the host if the mul before was
1147 (0x80000000 * 0x80000000) << 1). If this is the
1148 case, we negate the ovf. */
1149 if (n == 1) {
1150 temp = tcg_temp_new();
1151 temp2 = tcg_temp_new();
1152 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1153 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1154 tcg_gen_and_tl(temp, temp, temp2);
1155 tcg_gen_shli_tl(temp, temp, 31);
1156 /* negate v bit, if special condition */
1157 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1158 }
1159 /* write back result */
1160 tcg_gen_extr_i64_i32(rl, rh, t4);
1161 /* Calc SV bit */
1162 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1163 /* Calc AV/SAV bits */
1164 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1165 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1166 /* calc SAV */
1167 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1168 }
1169
1170 static inline void
1171 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1172 uint32_t up_shift)
1173 {
1174 TCGv_i64 t1 = tcg_temp_new_i64();
1175 TCGv_i64 t2 = tcg_temp_new_i64();
1176 TCGv_i64 t3 = tcg_temp_new_i64();
1177
1178 tcg_gen_ext_i32_i64(t1, arg1);
1179 tcg_gen_ext_i32_i64(t2, arg2);
1180 tcg_gen_ext_i32_i64(t3, arg3);
1181
1182 tcg_gen_mul_i64(t2, t2, t3);
1183 tcg_gen_sari_i64(t2, t2, up_shift - n);
1184
1185 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1186 }
1187
1188 static inline void
1189 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1190 TCGv arg3, uint32_t n)
1191 {
1192 TCGv_i64 r1 = tcg_temp_new_i64();
1193 TCGv t_n = tcg_constant_i32(n);
1194
1195 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1196 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
1197 tcg_gen_extr_i64_i32(rl, rh, r1);
1198 }
1199
1200 /* ret = r2 - (r1 * r3); */
1201 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1202 {
1203 TCGv_i64 t1 = tcg_temp_new_i64();
1204 TCGv_i64 t2 = tcg_temp_new_i64();
1205 TCGv_i64 t3 = tcg_temp_new_i64();
1206
1207 tcg_gen_ext_i32_i64(t1, r1);
1208 tcg_gen_ext_i32_i64(t2, r2);
1209 tcg_gen_ext_i32_i64(t3, r3);
1210
1211 tcg_gen_mul_i64(t1, t1, t3);
1212 tcg_gen_sub_i64(t1, t2, t1);
1213
1214 tcg_gen_extrl_i64_i32(ret, t1);
1215 /* calc V
1216 t2 > 0x7fffffff */
1217 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1218 /* result < -0x80000000 */
1219 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1220 tcg_gen_or_i64(t2, t2, t3);
1221 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
1222 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1223
1224 /* Calc SV bit */
1225 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1226 /* Calc AV/SAV bits */
1227 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1228 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1229 /* calc SAV */
1230 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1231 }
1232
1233 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1234 {
1235 TCGv temp = tcg_constant_i32(con);
1236 gen_msub32_d(ret, r1, r2, temp);
1237 }
1238
1239 static inline void
1240 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1241 TCGv r3)
1242 {
1243 TCGv t1 = tcg_temp_new();
1244 TCGv t2 = tcg_temp_new();
1245 TCGv t3 = tcg_temp_new();
1246 TCGv t4 = tcg_temp_new();
1247
1248 tcg_gen_muls2_tl(t1, t2, r1, r3);
1249 /* only the sub can overflow */
1250 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1251 /* calc V bit */
1252 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1253 tcg_gen_xor_tl(t1, r2_high, t2);
1254 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1255 /* Calc SV bit */
1256 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1257 /* Calc AV/SAV bits */
1258 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1259 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1260 /* calc SAV */
1261 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1262 /* write back the result */
1263 tcg_gen_mov_tl(ret_low, t3);
1264 tcg_gen_mov_tl(ret_high, t4);
1265 }
1266
1267 static inline void
1268 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1269 int32_t con)
1270 {
1271 TCGv temp = tcg_constant_i32(con);
1272 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1273 }
1274
1275 static inline void
1276 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1277 TCGv r3)
1278 {
1279 TCGv_i64 t1 = tcg_temp_new_i64();
1280 TCGv_i64 t2 = tcg_temp_new_i64();
1281 TCGv_i64 t3 = tcg_temp_new_i64();
1282
1283 tcg_gen_extu_i32_i64(t1, r1);
1284 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1285 tcg_gen_extu_i32_i64(t3, r3);
1286
1287 tcg_gen_mul_i64(t1, t1, t3);
1288 tcg_gen_sub_i64(t3, t2, t1);
1289 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1290 /* calc V bit, only the sub can overflow, if t1 > t2 */
1291 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1292 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1293 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1294 /* Calc SV bit */
1295 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1296 /* Calc AV/SAV bits */
1297 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1298 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1299 /* calc SAV */
1300 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1301 }
1302
1303 static inline void
1304 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1305 int32_t con)
1306 {
1307 TCGv temp = tcg_constant_i32(con);
1308 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1309 }
1310
1311 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1312 {
1313 TCGv temp = tcg_constant_i32(r2);
1314 gen_add_d(ret, r1, temp);
1315 }
1316
1317 /* calculate the carry bit too */
1318 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1319 {
1320 TCGv t0 = tcg_temp_new_i32();
1321 TCGv result = tcg_temp_new_i32();
1322
1323 tcg_gen_movi_tl(t0, 0);
1324 /* Addition and set C/V/SV bits */
1325 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1326 /* calc V bit */
1327 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1328 tcg_gen_xor_tl(t0, r1, r2);
1329 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1330 /* Calc SV bit */
1331 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1332 /* Calc AV/SAV bits */
1333 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1334 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1335 /* calc SAV */
1336 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1337 /* write back result */
1338 tcg_gen_mov_tl(ret, result);
1339 }
1340
1341 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1342 {
1343 TCGv temp = tcg_constant_i32(con);
1344 gen_add_CC(ret, r1, temp);
1345 }
1346
1347 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1348 {
1349 TCGv carry = tcg_temp_new_i32();
1350 TCGv t0 = tcg_temp_new_i32();
1351 TCGv result = tcg_temp_new_i32();
1352
1353 tcg_gen_movi_tl(t0, 0);
1354 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1355 /* Addition, carry and set C/V/SV bits */
1356 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1357 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1358 /* calc V bit */
1359 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1360 tcg_gen_xor_tl(t0, r1, r2);
1361 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1362 /* Calc SV bit */
1363 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1364 /* Calc AV/SAV bits */
1365 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1366 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1367 /* calc SAV */
1368 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1369 /* write back result */
1370 tcg_gen_mov_tl(ret, result);
1371 }
1372
1373 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1374 {
1375 TCGv temp = tcg_constant_i32(con);
1376 gen_addc_CC(ret, r1, temp);
1377 }
1378
1379 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1380 TCGv r4)
1381 {
1382 TCGv temp = tcg_temp_new();
1383 TCGv temp2 = tcg_temp_new();
1384 TCGv result = tcg_temp_new();
1385 TCGv mask = tcg_temp_new();
1386 TCGv t0 = tcg_constant_i32(0);
1387
1388 /* create mask for sticky bits */
1389 tcg_gen_setcond_tl(cond, mask, r4, t0);
1390 tcg_gen_shli_tl(mask, mask, 31);
1391
1392 tcg_gen_add_tl(result, r1, r2);
1393 /* Calc PSW_V */
1394 tcg_gen_xor_tl(temp, result, r1);
1395 tcg_gen_xor_tl(temp2, r1, r2);
1396 tcg_gen_andc_tl(temp, temp, temp2);
1397 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1398 /* Set PSW_SV */
1399 tcg_gen_and_tl(temp, temp, mask);
1400 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1401 /* calc AV bit */
1402 tcg_gen_add_tl(temp, result, result);
1403 tcg_gen_xor_tl(temp, temp, result);
1404 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1405 /* calc SAV bit */
1406 tcg_gen_and_tl(temp, temp, mask);
1407 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1408 /* write back result */
1409 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1410 }
1411
1412 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1413 TCGv r3, TCGv r4)
1414 {
1415 TCGv temp = tcg_constant_i32(r2);
1416 gen_cond_add(cond, r1, temp, r3, r4);
1417 }
1418
1419 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1420 {
1421 TCGv temp = tcg_temp_new_i32();
1422 TCGv result = tcg_temp_new_i32();
1423
1424 tcg_gen_sub_tl(result, r1, r2);
1425 /* calc V bit */
1426 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1427 tcg_gen_xor_tl(temp, r1, r2);
1428 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1429 /* calc SV bit */
1430 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1431 /* Calc AV bit */
1432 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1433 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1434 /* calc SAV bit */
1435 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1436 /* write back result */
1437 tcg_gen_mov_tl(ret, result);
1438 }
1439
1440 static inline void
1441 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1442 {
1443 TCGv temp = tcg_temp_new();
1444 TCGv_i64 t0 = tcg_temp_new_i64();
1445 TCGv_i64 t1 = tcg_temp_new_i64();
1446 TCGv_i64 result = tcg_temp_new_i64();
1447
1448 tcg_gen_sub_i64(result, r1, r2);
1449 /* calc v bit */
1450 tcg_gen_xor_i64(t1, result, r1);
1451 tcg_gen_xor_i64(t0, r1, r2);
1452 tcg_gen_and_i64(t1, t1, t0);
1453 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
1454 /* calc SV bit */
1455 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1456 /* calc AV/SAV bits */
1457 tcg_gen_extrh_i64_i32(temp, result);
1458 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1459 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1460 /* calc SAV */
1461 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1462 /* write back result */
1463 tcg_gen_mov_i64(ret, result);
1464 }
1465
1466 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1467 {
1468 TCGv result = tcg_temp_new();
1469 TCGv temp = tcg_temp_new();
1470
1471 tcg_gen_sub_tl(result, r1, r2);
1472 /* calc C bit */
1473 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1474 /* calc V bit */
1475 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1476 tcg_gen_xor_tl(temp, r1, r2);
1477 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1478 /* calc SV bit */
1479 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1480 /* Calc AV bit */
1481 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1482 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1483 /* calc SAV bit */
1484 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1485 /* write back result */
1486 tcg_gen_mov_tl(ret, result);
1487 }
1488
1489 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1490 {
1491 TCGv temp = tcg_temp_new();
1492 tcg_gen_not_tl(temp, r2);
1493 gen_addc_CC(ret, r1, temp);
1494 }
1495
1496 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1497 TCGv r4)
1498 {
1499 TCGv temp = tcg_temp_new();
1500 TCGv temp2 = tcg_temp_new();
1501 TCGv result = tcg_temp_new();
1502 TCGv mask = tcg_temp_new();
1503 TCGv t0 = tcg_constant_i32(0);
1504
1505 /* create mask for sticky bits */
1506 tcg_gen_setcond_tl(cond, mask, r4, t0);
1507 tcg_gen_shli_tl(mask, mask, 31);
1508
1509 tcg_gen_sub_tl(result, r1, r2);
1510 /* Calc PSW_V */
1511 tcg_gen_xor_tl(temp, result, r1);
1512 tcg_gen_xor_tl(temp2, r1, r2);
1513 tcg_gen_and_tl(temp, temp, temp2);
1514 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1515 /* Set PSW_SV */
1516 tcg_gen_and_tl(temp, temp, mask);
1517 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1518 /* calc AV bit */
1519 tcg_gen_add_tl(temp, result, result);
1520 tcg_gen_xor_tl(temp, temp, result);
1521 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1522 /* calc SAV bit */
1523 tcg_gen_and_tl(temp, temp, mask);
1524 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1525 /* write back result */
1526 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1527 }
1528
1529 static inline void
1530 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1531 TCGv r3, uint32_t n, uint32_t mode)
1532 {
1533 TCGv t_n = tcg_constant_i32(n);
1534 TCGv temp = tcg_temp_new();
1535 TCGv temp2 = tcg_temp_new();
1536 TCGv_i64 temp64 = tcg_temp_new_i64();
1537 switch (mode) {
1538 case MODE_LL:
1539 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1540 break;
1541 case MODE_LU:
1542 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1543 break;
1544 case MODE_UL:
1545 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1546 break;
1547 case MODE_UU:
1548 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1549 break;
1550 }
1551 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1552 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1553 tcg_gen_sub_tl, tcg_gen_sub_tl);
1554 }
1555
1556 static inline void
1557 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1558 TCGv r3, uint32_t n, uint32_t mode)
1559 {
1560 TCGv t_n = tcg_constant_i32(n);
1561 TCGv temp = tcg_temp_new();
1562 TCGv temp2 = tcg_temp_new();
1563 TCGv temp3 = tcg_temp_new();
1564 TCGv_i64 temp64 = tcg_temp_new_i64();
1565
1566 switch (mode) {
1567 case MODE_LL:
1568 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1569 break;
1570 case MODE_LU:
1571 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1572 break;
1573 case MODE_UL:
1574 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1575 break;
1576 case MODE_UU:
1577 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1578 break;
1579 }
1580 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1581 gen_subs(ret_low, r1_low, temp);
1582 tcg_gen_mov_tl(temp, cpu_PSW_V);
1583 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1584 gen_subs(ret_high, r1_high, temp2);
1585 /* combine v bits */
1586 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1587 /* combine av bits */
1588 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1589 }
1590
1591 static inline void
1592 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1593 TCGv r3, uint32_t n, uint32_t mode)
1594 {
1595 TCGv t_n = tcg_constant_i32(n);
1596 TCGv_i64 temp64 = tcg_temp_new_i64();
1597 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1598 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1599 switch (mode) {
1600 case MODE_LL:
1601 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
1602 break;
1603 case MODE_LU:
1604 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
1605 break;
1606 case MODE_UL:
1607 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
1608 break;
1609 case MODE_UU:
1610 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
1611 break;
1612 }
1613 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1614 gen_sub64_d(temp64_3, temp64_2, temp64);
1615 /* write back result */
1616 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1617 }
1618
1619 static inline void
1620 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1621 TCGv r3, uint32_t n, uint32_t mode)
1622 {
1623 TCGv t_n = tcg_constant_i32(n);
1624 TCGv_i64 temp64 = tcg_temp_new_i64();
1625 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1626 switch (mode) {
1627 case MODE_LL:
1628 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
1629 break;
1630 case MODE_LU:
1631 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
1632 break;
1633 case MODE_UL:
1634 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
1635 break;
1636 case MODE_UU:
1637 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
1638 break;
1639 }
1640 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1641 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1642 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1643 }
1644
1645 static inline void
1646 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1647 uint32_t mode)
1648 {
1649 TCGv t_n = tcg_constant_i32(n);
1650 TCGv_i64 temp64 = tcg_temp_new_i64();
1651 switch (mode) {
1652 case MODE_LL:
1653 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1654 break;
1655 case MODE_LU:
1656 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1657 break;
1658 case MODE_UL:
1659 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1660 break;
1661 case MODE_UU:
1662 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1663 break;
1664 }
1665 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1666 }
1667
1668 static inline void
1669 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1670 {
1671 TCGv temp = tcg_temp_new();
1672 TCGv temp2 = tcg_temp_new();
1673
1674 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1675 tcg_gen_shli_tl(temp, r1, 16);
1676 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1677 }
1678
1679 static inline void
1680 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1681 uint32_t n, uint32_t mode)
1682 {
1683 TCGv t_n = tcg_constant_i32(n);
1684 TCGv_i64 temp64 = tcg_temp_new_i64();
1685 switch (mode) {
1686 case MODE_LL:
1687 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1688 break;
1689 case MODE_LU:
1690 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1691 break;
1692 case MODE_UL:
1693 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1694 break;
1695 case MODE_UU:
1696 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1697 break;
1698 }
1699 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1700 }
1701
1702 static inline void
1703 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1704 {
1705 TCGv temp = tcg_temp_new();
1706 TCGv temp2 = tcg_temp_new();
1707
1708 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1709 tcg_gen_shli_tl(temp, r1, 16);
1710 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1711 }
1712
1713 static inline void
1714 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1715 {
1716 TCGv temp = tcg_constant_i32(n);
1717 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1718 }
1719
1720 static inline void
1721 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1722 {
1723 TCGv temp = tcg_constant_i32(n);
1724 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1725 }
1726
1727 static inline void
1728 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1729 uint32_t up_shift)
1730 {
1731 TCGv temp3 = tcg_temp_new();
1732 TCGv_i64 t1 = tcg_temp_new_i64();
1733 TCGv_i64 t2 = tcg_temp_new_i64();
1734 TCGv_i64 t3 = tcg_temp_new_i64();
1735 TCGv_i64 t4 = tcg_temp_new_i64();
1736
1737 tcg_gen_ext_i32_i64(t2, arg2);
1738 tcg_gen_ext_i32_i64(t3, arg3);
1739
1740 tcg_gen_mul_i64(t2, t2, t3);
1741
1742 tcg_gen_ext_i32_i64(t1, arg1);
1743 /* if we shift part of the fraction out, we need to round up */
1744 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1745 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1746 tcg_gen_sari_i64(t2, t2, up_shift - n);
1747 tcg_gen_add_i64(t2, t2, t4);
1748
1749 tcg_gen_sub_i64(t3, t1, t2);
1750 tcg_gen_extrl_i64_i32(temp3, t3);
1751 /* calc v bit */
1752 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1753 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1754 tcg_gen_or_i64(t1, t1, t2);
1755 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1756 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1757 /* Calc SV bit */
1758 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1759 /* Calc AV/SAV bits */
1760 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1761 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1762 /* calc SAV */
1763 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1764 /* write back result */
1765 tcg_gen_mov_tl(ret, temp3);
1766 }
1767
1768 static inline void
1769 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1770 {
1771 TCGv temp = tcg_temp_new();
1772 TCGv temp2 = tcg_temp_new();
1773 if (n == 0) {
1774 tcg_gen_mul_tl(temp, arg2, arg3);
1775 } else { /* n is expected to be 1 */
1776 tcg_gen_mul_tl(temp, arg2, arg3);
1777 tcg_gen_shli_tl(temp, temp, 1);
1778 /* catch special case r1 = r2 = 0x8000 */
1779 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1780 tcg_gen_sub_tl(temp, temp, temp2);
1781 }
1782 gen_sub_d(ret, arg1, temp);
1783 }
1784
1785 static inline void
1786 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1787 {
1788 TCGv temp = tcg_temp_new();
1789 TCGv temp2 = tcg_temp_new();
1790 if (n == 0) {
1791 tcg_gen_mul_tl(temp, arg2, arg3);
1792 } else { /* n is expected to be 1 */
1793 tcg_gen_mul_tl(temp, arg2, arg3);
1794 tcg_gen_shli_tl(temp, temp, 1);
1795 /* catch special case r1 = r2 = 0x8000 */
1796 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1797 tcg_gen_sub_tl(temp, temp, temp2);
1798 }
1799 gen_subs(ret, arg1, temp);
1800 }
1801
1802 static inline void
1803 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1804 TCGv arg3, uint32_t n)
1805 {
1806 TCGv temp = tcg_temp_new();
1807 TCGv temp2 = tcg_temp_new();
1808 TCGv_i64 t1 = tcg_temp_new_i64();
1809 TCGv_i64 t2 = tcg_temp_new_i64();
1810 TCGv_i64 t3 = tcg_temp_new_i64();
1811
1812 if (n == 0) {
1813 tcg_gen_mul_tl(temp, arg2, arg3);
1814 } else { /* n is expected to be 1 */
1815 tcg_gen_mul_tl(temp, arg2, arg3);
1816 tcg_gen_shli_tl(temp, temp, 1);
1817 /* catch special case r1 = r2 = 0x8000 */
1818 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1819 tcg_gen_sub_tl(temp, temp, temp2);
1820 }
1821 tcg_gen_ext_i32_i64(t2, temp);
1822 tcg_gen_shli_i64(t2, t2, 16);
1823 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1824 gen_sub64_d(t3, t1, t2);
1825 /* write back result */
1826 tcg_gen_extr_i64_i32(rl, rh, t3);
1827 }
1828
1829 static inline void
1830 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1831 TCGv arg3, uint32_t n)
1832 {
1833 TCGv temp = tcg_temp_new();
1834 TCGv temp2 = tcg_temp_new();
1835 TCGv_i64 t1 = tcg_temp_new_i64();
1836 TCGv_i64 t2 = tcg_temp_new_i64();
1837
1838 if (n == 0) {
1839 tcg_gen_mul_tl(temp, arg2, arg3);
1840 } else { /* n is expected to be 1 */
1841 tcg_gen_mul_tl(temp, arg2, arg3);
1842 tcg_gen_shli_tl(temp, temp, 1);
1843 /* catch special case r1 = r2 = 0x8000 */
1844 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1845 tcg_gen_sub_tl(temp, temp, temp2);
1846 }
1847 tcg_gen_ext_i32_i64(t2, temp);
1848 tcg_gen_shli_i64(t2, t2, 16);
1849 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1850
1851 gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
1852 tcg_gen_extr_i64_i32(rl, rh, t1);
1853 }
1854
1855 static inline void
1856 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1857 TCGv arg3, uint32_t n)
1858 {
1859 TCGv_i64 t1 = tcg_temp_new_i64();
1860 TCGv_i64 t2 = tcg_temp_new_i64();
1861 TCGv_i64 t3 = tcg_temp_new_i64();
1862 TCGv_i64 t4 = tcg_temp_new_i64();
1863 TCGv temp, temp2;
1864
1865 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1866 tcg_gen_ext_i32_i64(t2, arg2);
1867 tcg_gen_ext_i32_i64(t3, arg3);
1868
1869 tcg_gen_mul_i64(t2, t2, t3);
1870 if (n != 0) {
1871 tcg_gen_shli_i64(t2, t2, 1);
1872 }
1873 tcg_gen_sub_i64(t4, t1, t2);
1874 /* calc v bit */
1875 tcg_gen_xor_i64(t3, t4, t1);
1876 tcg_gen_xor_i64(t2, t1, t2);
1877 tcg_gen_and_i64(t3, t3, t2);
1878 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1879 /* We produce an overflow on the host if the mul before was
1880 (0x80000000 * 0x80000000) << 1). If this is the
1881 case, we negate the ovf. */
1882 if (n == 1) {
1883 temp = tcg_temp_new();
1884 temp2 = tcg_temp_new();
1885 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1886 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1887 tcg_gen_and_tl(temp, temp, temp2);
1888 tcg_gen_shli_tl(temp, temp, 31);
1889 /* negate v bit, if special condition */
1890 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1891 }
1892 /* write back result */
1893 tcg_gen_extr_i64_i32(rl, rh, t4);
1894 /* Calc SV bit */
1895 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1896 /* Calc AV/SAV bits */
1897 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1898 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1899 /* calc SAV */
1900 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1901 }
1902
1903 static inline void
1904 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1905 uint32_t up_shift)
1906 {
1907 TCGv_i64 t1 = tcg_temp_new_i64();
1908 TCGv_i64 t2 = tcg_temp_new_i64();
1909 TCGv_i64 t3 = tcg_temp_new_i64();
1910 TCGv_i64 t4 = tcg_temp_new_i64();
1911
1912 tcg_gen_ext_i32_i64(t1, arg1);
1913 tcg_gen_ext_i32_i64(t2, arg2);
1914 tcg_gen_ext_i32_i64(t3, arg3);
1915
1916 tcg_gen_mul_i64(t2, t2, t3);
1917 /* if we shift part of the fraction out, we need to round up */
1918 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1919 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1920 tcg_gen_sari_i64(t3, t2, up_shift - n);
1921 tcg_gen_add_i64(t3, t3, t4);
1922
1923 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
1924 }
1925
1926 static inline void
1927 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1928 TCGv arg3, uint32_t n)
1929 {
1930 TCGv_i64 r1 = tcg_temp_new_i64();
1931 TCGv t_n = tcg_constant_i32(n);
1932
1933 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1934 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
1935 tcg_gen_extr_i64_i32(rl, rh, r1);
1936 }
1937
1938 static inline void
1939 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1940 TCGv r3, uint32_t n, uint32_t mode)
1941 {
1942 TCGv t_n = tcg_constant_i32(n);
1943 TCGv temp = tcg_temp_new();
1944 TCGv temp2 = tcg_temp_new();
1945 TCGv_i64 temp64 = tcg_temp_new_i64();
1946 switch (mode) {
1947 case MODE_LL:
1948 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1949 break;
1950 case MODE_LU:
1951 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1952 break;
1953 case MODE_UL:
1954 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1955 break;
1956 case MODE_UU:
1957 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1958 break;
1959 }
1960 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1961 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1962 tcg_gen_add_tl, tcg_gen_sub_tl);
1963 }
1964
1965 static inline void
1966 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1967 TCGv r3, uint32_t n, uint32_t mode)
1968 {
1969 TCGv t_n = tcg_constant_i32(n);
1970 TCGv_i64 temp64 = tcg_temp_new_i64();
1971 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1972 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1973 switch (mode) {
1974 case MODE_LL:
1975 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1976 break;
1977 case MODE_LU:
1978 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1979 break;
1980 case MODE_UL:
1981 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1982 break;
1983 case MODE_UU:
1984 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1985 break;
1986 }
1987 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
1988 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
1989 tcg_gen_ext32s_i64(temp64, temp64); /* low */
1990 tcg_gen_sub_i64(temp64, temp64_2, temp64);
1991 tcg_gen_shli_i64(temp64, temp64, 16);
1992
1993 gen_sub64_d(temp64_2, temp64_3, temp64);
1994 /* write back result */
1995 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
1996 }
1997
1998 static inline void
1999 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2000 {
2001 TCGv t_n = tcg_constant_i32(n);
2002 TCGv temp = tcg_temp_new();
2003 TCGv temp2 = tcg_temp_new();
2004 TCGv_i64 temp64 = tcg_temp_new_i64();
2005 switch (mode) {
2006 case MODE_LL:
2007 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2008 break;
2009 case MODE_LU:
2010 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2011 break;
2012 case MODE_UL:
2013 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2014 break;
2015 case MODE_UU:
2016 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2017 break;
2018 }
2019 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2020 tcg_gen_shli_tl(temp, r1, 16);
2021 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2022 }
2023
2024 static inline void
2025 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2026 TCGv r3, uint32_t n, uint32_t mode)
2027 {
2028 TCGv t_n = tcg_constant_i32(n);
2029 TCGv temp = tcg_temp_new();
2030 TCGv temp2 = tcg_temp_new();
2031 TCGv temp3 = tcg_temp_new();
2032 TCGv_i64 temp64 = tcg_temp_new_i64();
2033
2034 switch (mode) {
2035 case MODE_LL:
2036 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2037 break;
2038 case MODE_LU:
2039 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2040 break;
2041 case MODE_UL:
2042 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2043 break;
2044 case MODE_UU:
2045 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2046 break;
2047 }
2048 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2049 gen_adds(ret_low, r1_low, temp);
2050 tcg_gen_mov_tl(temp, cpu_PSW_V);
2051 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2052 gen_subs(ret_high, r1_high, temp2);
2053 /* combine v bits */
2054 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2055 /* combine av bits */
2056 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2057 }
2058
2059 static inline void
2060 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2061 TCGv r3, uint32_t n, uint32_t mode)
2062 {
2063 TCGv t_n = tcg_constant_i32(n);
2064 TCGv_i64 temp64 = tcg_temp_new_i64();
2065 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2066
2067 switch (mode) {
2068 case MODE_LL:
2069 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2070 break;
2071 case MODE_LU:
2072 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2073 break;
2074 case MODE_UL:
2075 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2076 break;
2077 case MODE_UU:
2078 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2079 break;
2080 }
2081 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2082 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2083 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2084 tcg_gen_shli_i64(temp64, temp64, 16);
2085 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2086
2087 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2088 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2089 }
2090
2091 static inline void
2092 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2093 {
2094 TCGv t_n = tcg_constant_i32(n);
2095 TCGv temp = tcg_temp_new();
2096 TCGv temp2 = tcg_temp_new();
2097 TCGv_i64 temp64 = tcg_temp_new_i64();
2098 switch (mode) {
2099 case MODE_LL:
2100 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2101 break;
2102 case MODE_LU:
2103 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2104 break;
2105 case MODE_UL:
2106 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2107 break;
2108 case MODE_UU:
2109 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2110 break;
2111 }
2112 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2113 tcg_gen_shli_tl(temp, r1, 16);
2114 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2115 }
2116
2117 static inline void gen_abs(TCGv ret, TCGv r1)
2118 {
2119 tcg_gen_abs_tl(ret, r1);
2120 /* overflow can only happen, if r1 = 0x80000000 */
2121 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2122 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2123 /* calc SV bit */
2124 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2125 /* Calc AV bit */
2126 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2127 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2128 /* calc SAV bit */
2129 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2130 }
2131
2132 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2133 {
2134 TCGv temp = tcg_temp_new_i32();
2135 TCGv result = tcg_temp_new_i32();
2136
2137 tcg_gen_sub_tl(result, r1, r2);
2138 tcg_gen_sub_tl(temp, r2, r1);
2139 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2140
2141 /* calc V bit */
2142 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2143 tcg_gen_xor_tl(temp, result, r2);
2144 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2145 tcg_gen_xor_tl(temp, r1, r2);
2146 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2147 /* calc SV bit */
2148 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2149 /* Calc AV bit */
2150 tcg_gen_add_tl(cpu_PSW_AV, result, result);
2151 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2152 /* calc SAV bit */
2153 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2154 /* write back result */
2155 tcg_gen_mov_tl(ret, result);
2156 }
2157
2158 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2159 {
2160 TCGv temp = tcg_constant_i32(con);
2161 gen_absdif(ret, r1, temp);
2162 }
2163
2164 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2165 {
2166 TCGv temp = tcg_constant_i32(con);
2167 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2168 }
2169
2170 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2171 {
2172 TCGv high = tcg_temp_new();
2173 TCGv low = tcg_temp_new();
2174
2175 tcg_gen_muls2_tl(low, high, r1, r2);
2176 tcg_gen_mov_tl(ret, low);
2177 /* calc V bit */
2178 tcg_gen_sari_tl(low, low, 31);
2179 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2180 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2181 /* calc SV bit */
2182 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2183 /* Calc AV bit */
2184 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2185 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2186 /* calc SAV bit */
2187 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2188 }
2189
2190 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2191 {
2192 TCGv temp = tcg_constant_i32(con);
2193 gen_mul_i32s(ret, r1, temp);
2194 }
2195
2196 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2197 {
2198 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2199 /* clear V bit */
2200 tcg_gen_movi_tl(cpu_PSW_V, 0);
2201 /* calc SV bit */
2202 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2203 /* Calc AV bit */
2204 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2205 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2206 /* calc SAV bit */
2207 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2208 }
2209
2210 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2211 int32_t con)
2212 {
2213 TCGv temp = tcg_constant_i32(con);
2214 gen_mul_i64s(ret_low, ret_high, r1, temp);
2215 }
2216
2217 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2218 {
2219 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2220 /* clear V bit */
2221 tcg_gen_movi_tl(cpu_PSW_V, 0);
2222 /* calc SV bit */
2223 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2224 /* Calc AV bit */
2225 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2226 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2227 /* calc SAV bit */
2228 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2229 }
2230
2231 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2232 int32_t con)
2233 {
2234 TCGv temp = tcg_constant_i32(con);
2235 gen_mul_i64u(ret_low, ret_high, r1, temp);
2236 }
2237
2238 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2239 {
2240 TCGv temp = tcg_constant_i32(con);
2241 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2242 }
2243
2244 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2245 {
2246 TCGv temp = tcg_constant_i32(con);
2247 gen_helper_mul_suov(ret, cpu_env, r1, temp);
2248 }
2249
2250 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2251 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2252 {
2253 TCGv temp = tcg_constant_i32(con);
2254 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2255 }
2256
2257 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2258 {
2259 TCGv temp = tcg_constant_i32(con);
2260 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2261 }
2262
2263 static void
2264 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2265 {
2266 TCGv_i64 temp_64 = tcg_temp_new_i64();
2267 TCGv_i64 temp2_64 = tcg_temp_new_i64();
2268
2269 if (n == 0) {
2270 if (up_shift == 32) {
2271 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2272 } else if (up_shift == 16) {
2273 tcg_gen_ext_i32_i64(temp_64, arg1);
2274 tcg_gen_ext_i32_i64(temp2_64, arg2);
2275
2276 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2277 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2278 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2279 } else {
2280 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2281 }
2282 /* reset v bit */
2283 tcg_gen_movi_tl(cpu_PSW_V, 0);
2284 } else { /* n is expected to be 1 */
2285 tcg_gen_ext_i32_i64(temp_64, arg1);
2286 tcg_gen_ext_i32_i64(temp2_64, arg2);
2287
2288 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2289
2290 if (up_shift == 0) {
2291 tcg_gen_shli_i64(temp_64, temp_64, 1);
2292 } else {
2293 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2294 }
2295 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2296 /* overflow only occurs if r1 = r2 = 0x8000 */
2297 if (up_shift == 0) {/* result is 64 bit */
2298 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2299 0x80000000);
2300 } else { /* result is 32 bit */
2301 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2302 0x80000000);
2303 }
2304 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2305 /* calc sv overflow bit */
2306 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2307 }
2308 /* calc av overflow bit */
2309 if (up_shift == 0) {
2310 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2311 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2312 } else {
2313 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2314 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2315 }
2316 /* calc sav overflow bit */
2317 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2318 }
2319
2320 static void
2321 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2322 {
2323 TCGv temp = tcg_temp_new();
2324 if (n == 0) {
2325 tcg_gen_mul_tl(ret, arg1, arg2);
2326 } else { /* n is expected to be 1 */
2327 tcg_gen_mul_tl(ret, arg1, arg2);
2328 tcg_gen_shli_tl(ret, ret, 1);
2329 /* catch special case r1 = r2 = 0x8000 */
2330 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2331 tcg_gen_sub_tl(ret, ret, temp);
2332 }
2333 /* reset v bit */
2334 tcg_gen_movi_tl(cpu_PSW_V, 0);
2335 /* calc av overflow bit */
2336 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2337 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2338 /* calc sav overflow bit */
2339 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2340 }
2341
2342 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2343 {
2344 TCGv temp = tcg_temp_new();
2345 if (n == 0) {
2346 tcg_gen_mul_tl(ret, arg1, arg2);
2347 tcg_gen_addi_tl(ret, ret, 0x8000);
2348 } else {
2349 tcg_gen_mul_tl(ret, arg1, arg2);
2350 tcg_gen_shli_tl(ret, ret, 1);
2351 tcg_gen_addi_tl(ret, ret, 0x8000);
2352 /* catch special case r1 = r2 = 0x8000 */
2353 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2354 tcg_gen_muli_tl(temp, temp, 0x8001);
2355 tcg_gen_sub_tl(ret, ret, temp);
2356 }
2357 /* reset v bit */
2358 tcg_gen_movi_tl(cpu_PSW_V, 0);
2359 /* calc av overflow bit */
2360 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2361 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2362 /* calc sav overflow bit */
2363 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2364 /* cut halfword off */
2365 tcg_gen_andi_tl(ret, ret, 0xffff0000);
2366 }
2367
2368 static inline void
2369 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2370 TCGv r3)
2371 {
2372 TCGv_i64 temp64 = tcg_temp_new_i64();
2373 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2374 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2375 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2376 }
2377
2378 static inline void
2379 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2380 int32_t con)
2381 {
2382 TCGv temp = tcg_constant_i32(con);
2383 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2384 }
2385
2386 static inline void
2387 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2388 TCGv r3)
2389 {
2390 TCGv_i64 temp64 = tcg_temp_new_i64();
2391 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2392 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2393 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2394 }
2395
2396 static inline void
2397 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2398 int32_t con)
2399 {
2400 TCGv temp = tcg_constant_i32(con);
2401 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2402 }
2403
2404 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2405 {
2406 TCGv temp = tcg_constant_i32(con);
2407 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2408 }
2409
2410 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2411 {
2412 TCGv temp = tcg_constant_i32(con);
2413 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2414 }
2415
2416 static inline void
2417 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2418 TCGv r3)
2419 {
2420 TCGv_i64 temp64 = tcg_temp_new_i64();
2421 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2422 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2423 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2424 }
2425
2426 static inline void
2427 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2428 int32_t con)
2429 {
2430 TCGv temp = tcg_constant_i32(con);
2431 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2432 }
2433
2434 static inline void
2435 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2436 TCGv r3)
2437 {
2438 TCGv_i64 temp64 = tcg_temp_new_i64();
2439 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2440 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2441 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2442 }
2443
2444 static inline void
2445 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2446 int32_t con)
2447 {
2448 TCGv temp = tcg_constant_i32(con);
2449 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2450 }
2451
2452 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2453 {
2454 tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low));
2455 tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up));
2456 }
2457
2458 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2459 {
2460 tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up));
2461 }
2462
2463 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2464 {
2465 if (shift_count == -32) {
2466 tcg_gen_movi_tl(ret, 0);
2467 } else if (shift_count >= 0) {
2468 tcg_gen_shli_tl(ret, r1, shift_count);
2469 } else {
2470 tcg_gen_shri_tl(ret, r1, -shift_count);
2471 }
2472 }
2473
2474 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2475 {
2476 TCGv temp_low, temp_high;
2477
2478 if (shiftcount == -16) {
2479 tcg_gen_movi_tl(ret, 0);
2480 } else {
2481 temp_high = tcg_temp_new();
2482 temp_low = tcg_temp_new();
2483
2484 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2485 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2486 gen_shi(temp_low, temp_low, shiftcount);
2487 gen_shi(ret, temp_high, shiftcount);
2488 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2489 }
2490 }
2491
2492 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2493 {
2494 uint32_t msk, msk_start;
2495 TCGv temp = tcg_temp_new();
2496 TCGv temp2 = tcg_temp_new();
2497
2498 if (shift_count == 0) {
2499 /* Clear PSW.C and PSW.V */
2500 tcg_gen_movi_tl(cpu_PSW_C, 0);
2501 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2502 tcg_gen_mov_tl(ret, r1);
2503 } else if (shift_count == -32) {
2504 /* set PSW.C */
2505 tcg_gen_mov_tl(cpu_PSW_C, r1);
2506 /* fill ret completely with sign bit */
2507 tcg_gen_sari_tl(ret, r1, 31);
2508 /* clear PSW.V */
2509 tcg_gen_movi_tl(cpu_PSW_V, 0);
2510 } else if (shift_count > 0) {
2511 TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count);
2512 TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count);
2513
2514 /* calc carry */
2515 msk_start = 32 - shift_count;
2516 msk = ((1 << shift_count) - 1) << msk_start;
2517 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2518 /* calc v/sv bits */
2519 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2520 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2521 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2522 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2523 /* calc sv */
2524 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2525 /* do shift */
2526 tcg_gen_shli_tl(ret, r1, shift_count);
2527 } else {
2528 /* clear PSW.V */
2529 tcg_gen_movi_tl(cpu_PSW_V, 0);
2530 /* calc carry */
2531 msk = (1 << -shift_count) - 1;
2532 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2533 /* do shift */
2534 tcg_gen_sari_tl(ret, r1, -shift_count);
2535 }
2536 /* calc av overflow bit */
2537 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2538 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2539 /* calc sav overflow bit */
2540 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2541 }
2542
2543 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2544 {
2545 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2546 }
2547
2548 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2549 {
2550 TCGv temp = tcg_constant_i32(con);
2551 gen_shas(ret, r1, temp);
2552 }
2553
2554 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2555 {
2556 TCGv low, high;
2557
2558 if (shift_count == 0) {
2559 tcg_gen_mov_tl(ret, r1);
2560 } else if (shift_count > 0) {
2561 low = tcg_temp_new();
2562 high = tcg_temp_new();
2563
2564 tcg_gen_andi_tl(high, r1, 0xffff0000);
2565 tcg_gen_shli_tl(low, r1, shift_count);
2566 tcg_gen_shli_tl(ret, high, shift_count);
2567 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2568 } else {
2569 low = tcg_temp_new();
2570 high = tcg_temp_new();
2571
2572 tcg_gen_ext16s_tl(low, r1);
2573 tcg_gen_sari_tl(low, low, -shift_count);
2574 tcg_gen_sari_tl(ret, r1, -shift_count);
2575 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2576 }
2577 }
2578
2579 /* ret = {ret[30:0], (r1 cond r2)}; */
2580 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2581 {
2582 TCGv temp = tcg_temp_new();
2583 TCGv temp2 = tcg_temp_new();
2584
2585 tcg_gen_shli_tl(temp, ret, 1);
2586 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2587 tcg_gen_or_tl(ret, temp, temp2);
2588 }
2589
2590 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2591 {
2592 TCGv temp = tcg_constant_i32(con);
2593 gen_sh_cond(cond, ret, r1, temp);
2594 }
2595
2596 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2597 {
2598 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2599 }
2600
2601 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2602 {
2603 TCGv temp = tcg_constant_i32(con);
2604 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2605 }
2606
2607 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2608 {
2609 TCGv temp = tcg_constant_i32(con);
2610 gen_helper_add_suov(ret, cpu_env, r1, temp);
2611 }
2612
2613 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2614 {
2615 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2616 }
2617
2618 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2619 {
2620 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2621 }
2622
2623 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
2624 int pos1, int pos2,
2625 void(*op1)(TCGv, TCGv, TCGv),
2626 void(*op2)(TCGv, TCGv, TCGv))
2627 {
2628 TCGv temp1, temp2;
2629
2630 temp1 = tcg_temp_new();
2631 temp2 = tcg_temp_new();
2632
2633 tcg_gen_shri_tl(temp2, r2, pos2);
2634 tcg_gen_shri_tl(temp1, r1, pos1);
2635
2636 (*op1)(temp1, temp1, temp2);
2637 (*op2)(temp1 , ret, temp1);
2638
2639 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
2640 }
2641
2642 /* ret = r1[pos1] op1 r2[pos2]; */
2643 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
2644 int pos1, int pos2,
2645 void(*op1)(TCGv, TCGv, TCGv))
2646 {
2647 TCGv temp1, temp2;
2648
2649 temp1 = tcg_temp_new();
2650 temp2 = tcg_temp_new();
2651
2652 tcg_gen_shri_tl(temp2, r2, pos2);
2653 tcg_gen_shri_tl(temp1, r1, pos1);
2654
2655 (*op1)(ret, temp1, temp2);
2656
2657 tcg_gen_andi_tl(ret, ret, 0x1);
2658 }
2659
2660 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
2661 void(*op)(TCGv, TCGv, TCGv))
2662 {
2663 TCGv temp = tcg_temp_new();
2664 TCGv temp2 = tcg_temp_new();
2665 /* temp = (arg1 cond arg2 )*/
2666 tcg_gen_setcond_tl(cond, temp, r1, r2);
2667 /* temp2 = ret[0]*/
2668 tcg_gen_andi_tl(temp2, ret, 0x1);
2669 /* temp = temp insn temp2 */
2670 (*op)(temp, temp, temp2);
2671 /* ret = {ret[31:1], temp} */
2672 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
2673 }
2674
2675 static inline void
2676 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
2677 void(*op)(TCGv, TCGv, TCGv))
2678 {
2679 TCGv temp = tcg_constant_i32(con);
2680 gen_accumulating_cond(cond, ret, r1, temp, op);
2681 }
2682
2683 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
2684 {
2685 TCGv b0 = tcg_temp_new();
2686 TCGv b1 = tcg_temp_new();
2687 TCGv b2 = tcg_temp_new();
2688 TCGv b3 = tcg_temp_new();
2689
2690 /* byte 0 */
2691 tcg_gen_andi_tl(b0, r1, 0xff);
2692 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
2693
2694 /* byte 1 */
2695 tcg_gen_andi_tl(b1, r1, 0xff00);
2696 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
2697
2698 /* byte 2 */
2699 tcg_gen_andi_tl(b2, r1, 0xff0000);
2700 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
2701
2702 /* byte 3 */
2703 tcg_gen_andi_tl(b3, r1, 0xff000000);
2704 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
2705
2706 /* combine them */
2707 tcg_gen_or_tl(ret, b0, b1);
2708 tcg_gen_or_tl(ret, ret, b2);
2709 tcg_gen_or_tl(ret, ret, b3);
2710 }
2711
2712 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
2713 {
2714 TCGv h0 = tcg_temp_new();
2715 TCGv h1 = tcg_temp_new();
2716
2717 /* halfword 0 */
2718 tcg_gen_andi_tl(h0, r1, 0xffff);
2719 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
2720
2721 /* halfword 1 */
2722 tcg_gen_andi_tl(h1, r1, 0xffff0000);
2723 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
2724
2725 /* combine them */
2726 tcg_gen_or_tl(ret, h0, h1);
2727 }
2728
2729 /* mask = ((1 << width) -1) << pos;
2730 ret = (r1 & ~mask) | (r2 << pos) & mask); */
2731 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
2732 {
2733 TCGv mask = tcg_temp_new();
2734 TCGv temp = tcg_temp_new();
2735 TCGv temp2 = tcg_temp_new();
2736
2737 tcg_gen_movi_tl(mask, 1);
2738 tcg_gen_shl_tl(mask, mask, width);
2739 tcg_gen_subi_tl(mask, mask, 1);
2740 tcg_gen_shl_tl(mask, mask, pos);
2741
2742 tcg_gen_shl_tl(temp, r2, pos);
2743 tcg_gen_and_tl(temp, temp, mask);
2744 tcg_gen_andc_tl(temp2, r1, mask);
2745 tcg_gen_or_tl(ret, temp, temp2);
2746 }
2747
2748 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
2749 {
2750 TCGv_i64 temp = tcg_temp_new_i64();
2751
2752 gen_helper_bsplit(temp, r1);
2753 tcg_gen_extr_i64_i32(rl, rh, temp);
2754 }
2755
2756 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
2757 {
2758 TCGv_i64 temp = tcg_temp_new_i64();
2759
2760 gen_helper_unpack(temp, r1);
2761 tcg_gen_extr_i64_i32(rl, rh, temp);
2762 }
2763
2764 static inline void
2765 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2766 {
2767 TCGv_i64 ret = tcg_temp_new_i64();
2768
2769 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
2770 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
2771 } else {
2772 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
2773 }
2774 tcg_gen_extr_i64_i32(rl, rh, ret);
2775 }
2776
2777 static inline void
2778 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2779 {
2780 TCGv_i64 ret = tcg_temp_new_i64();
2781
2782 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
2783 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
2784 } else {
2785 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
2786 }
2787 tcg_gen_extr_i64_i32(rl, rh, ret);
2788 }
2789
2790 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
2791 {
2792 TCGv temp = tcg_temp_new();
2793 /* calc AV bit */
2794 tcg_gen_add_tl(temp, arg_low, arg_low);
2795 tcg_gen_xor_tl(temp, temp, arg_low);
2796 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
2797 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
2798 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2799 /* calc SAV bit */
2800 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2801 tcg_gen_movi_tl(cpu_PSW_V, 0);
2802 }
2803
2804 static void gen_calc_usb_mulr_h(TCGv arg)
2805 {
2806 TCGv temp = tcg_temp_new();
2807 /* calc AV bit */
2808 tcg_gen_add_tl(temp, arg, arg);
2809 tcg_gen_xor_tl(temp, temp, arg);
2810 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
2811 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2812 /* calc SAV bit */
2813 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2814 /* clear V bit */
2815 tcg_gen_movi_tl(cpu_PSW_V, 0);
2816 }
2817
2818 /* helpers for generating program flow micro-ops */
2819
2820 static inline void gen_save_pc(target_ulong pc)
2821 {
2822 tcg_gen_movi_tl(cpu_PC, pc);
2823 }
2824
2825 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2826 {
2827 if (translator_use_goto_tb(&ctx->base, dest)) {
2828 tcg_gen_goto_tb(n);
2829 gen_save_pc(dest);
2830 tcg_gen_exit_tb(ctx->base.tb, n);
2831 } else {
2832 gen_save_pc(dest);
2833 tcg_gen_lookup_and_goto_ptr();
2834 }
2835 ctx->base.is_jmp = DISAS_NORETURN;
2836 }
2837
2838 static void generate_trap(DisasContext *ctx, int class, int tin)
2839 {
2840 TCGv_i32 classtemp = tcg_constant_i32(class);
2841 TCGv_i32 tintemp = tcg_constant_i32(tin);
2842
2843 gen_save_pc(ctx->base.pc_next);
2844 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
2845 ctx->base.is_jmp = DISAS_NORETURN;
2846 }
2847
2848 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
2849 TCGv r2, int16_t address)
2850 {
2851 TCGLabel *jumpLabel = gen_new_label();
2852 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
2853
2854 gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
2855
2856 gen_set_label(jumpLabel);
2857 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2);
2858 }
2859
2860 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
2861 int r2, int16_t address)
2862 {
2863 TCGv temp = tcg_constant_i32(r2);
2864 gen_branch_cond(ctx, cond, r1, temp, address);
2865 }
2866
2867 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
2868 {
2869 TCGLabel *l1 = gen_new_label();
2870
2871 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
2872 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
2873 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset);
2874 gen_set_label(l1);
2875 gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
2876 }
2877
2878 static void gen_fcall_save_ctx(DisasContext *ctx)
2879 {
2880 TCGv temp = tcg_temp_new();
2881
2882 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
2883 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
2884 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
2885 tcg_gen_mov_tl(cpu_gpr_a[10], temp);
2886 }
2887
2888 static void gen_fret(DisasContext *ctx)
2889 {
2890 TCGv temp = tcg_temp_new();
2891
2892 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
2893 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
2894 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
2895 tcg_gen_mov_tl(cpu_PC, temp);
2896 ctx->base.is_jmp = DISAS_EXIT;
2897 }
2898
2899 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
2900 int r2 , int32_t constant , int32_t offset)
2901 {
2902 TCGv temp, temp2;
2903 int n;
2904
2905 switch (opc) {
2906 /* SB-format jumps */
2907 case OPC1_16_SB_J:
2908 case OPC1_32_B_J:
2909 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
2910 break;
2911 case OPC1_32_B_CALL:
2912 case OPC1_16_SB_CALL:
2913 gen_helper_1arg(call, ctx->pc_succ_insn);
2914 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
2915 break;
2916 case OPC1_16_SB_JZ:
2917 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
2918 break;
2919 case OPC1_16_SB_JNZ:
2920 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
2921 break;
2922 /* SBC-format jumps */
2923 case OPC1_16_SBC_JEQ:
2924 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
2925 break;
2926 case OPC1_16_SBC_JEQ2:
2927 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant,
2928 offset + 16);
2929 break;
2930 case OPC1_16_SBC_JNE:
2931 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
2932 break;
2933 case OPC1_16_SBC_JNE2:
2934 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15],
2935 constant, offset + 16);
2936 break;
2937 /* SBRN-format jumps */
2938 case OPC1_16_SBRN_JZ_T:
2939 temp = tcg_temp_new();
2940 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2941 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
2942 break;
2943 case OPC1_16_SBRN_JNZ_T:
2944 temp = tcg_temp_new();
2945 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2946 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
2947 break;
2948 /* SBR-format jumps */
2949 case OPC1_16_SBR_JEQ:
2950 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2951 offset);
2952 break;
2953 case OPC1_16_SBR_JEQ2:
2954 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2955 offset + 16);
2956 break;
2957 case OPC1_16_SBR_JNE:
2958 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2959 offset);
2960 break;
2961 case OPC1_16_SBR_JNE2:
2962 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2963 offset + 16);
2964 break;
2965 case OPC1_16_SBR_JNZ:
2966 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
2967 break;
2968 case OPC1_16_SBR_JNZ_A:
2969 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
2970 break;
2971 case OPC1_16_SBR_JGEZ:
2972 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
2973 break;
2974 case OPC1_16_SBR_JGTZ:
2975 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
2976 break;
2977 case OPC1_16_SBR_JLEZ:
2978 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
2979 break;
2980 case OPC1_16_SBR_JLTZ:
2981 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
2982 break;
2983 case OPC1_16_SBR_JZ:
2984 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
2985 break;
2986 case OPC1_16_SBR_JZ_A:
2987 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
2988 break;
2989 case OPC1_16_SBR_LOOP:
2990 gen_loop(ctx, r1, offset * 2 - 32);
2991 break;
2992 /* SR-format jumps */
2993 case OPC1_16_SR_JI:
2994 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
2995 ctx->base.is_jmp = DISAS_EXIT;
2996 break;
2997 case OPC2_32_SYS_RET:
2998 case OPC2_16_SR_RET:
2999 gen_helper_ret(cpu_env);
3000 ctx->base.is_jmp = DISAS_EXIT;
3001 break;
3002 /* B-format */
3003 case OPC1_32_B_CALLA:
3004 gen_helper_1arg(call, ctx->pc_succ_insn);
3005 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3006 break;
3007 case OPC1_32_B_FCALL:
3008 gen_fcall_save_ctx(ctx);
3009 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3010 break;
3011 case OPC1_32_B_FCALLA:
3012 gen_fcall_save_ctx(ctx);
3013 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3014 break;
3015 case OPC1_32_B_JLA:
3016 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
3017 /* fall through */
3018 case OPC1_32_B_JA:
3019 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3020 break;
3021 case OPC1_32_B_JL:
3022 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
3023 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3024 break;
3025 /* BOL format */
3026 case OPCM_32_BRC_EQ_NEQ:
3027 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3028 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3029 } else {
3030 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3031 }
3032 break;
3033 case OPCM_32_BRC_GE:
3034 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3035 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3036 } else {
3037 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3038 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3039 offset);
3040 }
3041 break;
3042 case OPCM_32_BRC_JLT:
3043 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3044 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3045 } else {
3046 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3047 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3048 offset);
3049 }
3050 break;
3051 case OPCM_32_BRC_JNE:
3052 temp = tcg_temp_new();
3053 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3054 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3055 /* subi is unconditional */
3056 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3057 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3058 } else {
3059 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3060 /* addi is unconditional */
3061 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3062 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3063 }
3064 break;
3065 /* BRN format */
3066 case OPCM_32_BRN_JTT:
3067 n = MASK_OP_BRN_N(ctx->opcode);
3068
3069 temp = tcg_temp_new();
3070 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3071
3072 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3073 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3074 } else {
3075 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3076 }
3077 break;
3078 /* BRR Format */
3079 case OPCM_32_BRR_EQ_NEQ:
3080 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3081 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3082 offset);
3083 } else {
3084 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3085 offset);
3086 }
3087 break;
3088 case OPCM_32_BRR_ADDR_EQ_NEQ:
3089 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3090 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3091 offset);
3092 } else {
3093 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3094 offset);
3095 }
3096 break;
3097 case OPCM_32_BRR_GE:
3098 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3099 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3100 offset);
3101 } else {
3102 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3103 offset);
3104 }
3105 break;
3106 case OPCM_32_BRR_JLT:
3107 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3108 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3109 offset);
3110 } else {
3111 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3112 offset);
3113 }
3114 break;
3115 case OPCM_32_BRR_LOOP:
3116 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3117 gen_loop(ctx, r2, offset * 2);
3118 } else {
3119 /* OPC2_32_BRR_LOOPU */
3120 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3121 }
3122 break;
3123 case OPCM_32_BRR_JNE:
3124 temp = tcg_temp_new();
3125 temp2 = tcg_temp_new();
3126 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3127 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3128 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3129 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3130 /* subi is unconditional */
3131 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3132 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3133 } else {
3134 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3135 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3136 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3137 /* addi is unconditional */
3138 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3139 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3140 }
3141 break;
3142 case OPCM_32_BRR_JNZ:
3143 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3144 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3145 } else {
3146 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3147 }
3148 break;
3149 default:
3150 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3151 }
3152 }
3153
3154
3155 /*
3156 * Functions for decoding instructions
3157 */
3158
3159 static void decode_src_opc(DisasContext *ctx, int op1)
3160 {
3161 int r1;
3162 int32_t const4;
3163 TCGv temp, temp2;
3164
3165 r1 = MASK_OP_SRC_S1D(ctx->opcode);
3166 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3167
3168 switch (op1) {
3169 case OPC1_16_SRC_ADD:
3170 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3171 break;
3172 case OPC1_16_SRC_ADD_A15:
3173 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3174 break;
3175 case OPC1_16_SRC_ADD_15A:
3176 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3177 break;
3178 case OPC1_16_SRC_ADD_A:
3179 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3180 break;
3181 case OPC1_16_SRC_CADD:
3182 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3183 cpu_gpr_d[15]);
3184 break;
3185 case OPC1_16_SRC_CADDN:
3186 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3187 cpu_gpr_d[15]);
3188 break;
3189 case OPC1_16_SRC_CMOV:
3190 temp = tcg_constant_tl(0);
3191 temp2 = tcg_constant_tl(const4);
3192 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3193 temp2, cpu_gpr_d[r1]);
3194 break;
3195 case OPC1_16_SRC_CMOVN:
3196 temp = tcg_constant_tl(0);
3197 temp2 = tcg_constant_tl(const4);
3198 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3199 temp2, cpu_gpr_d[r1]);
3200 break;
3201 case OPC1_16_SRC_EQ:
3202 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3203 const4);
3204 break;
3205 case OPC1_16_SRC_LT:
3206 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3207 const4);
3208 break;
3209 case OPC1_16_SRC_MOV:
3210 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3211 break;
3212 case OPC1_16_SRC_MOV_A:
3213 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3214 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3215 break;
3216 case OPC1_16_SRC_MOV_E:
3217 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3218 CHECK_REG_PAIR(r1);
3219 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3220 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3221 } else {
3222 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3223 }
3224 break;
3225 case OPC1_16_SRC_SH:
3226 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3227 break;
3228 case OPC1_16_SRC_SHA:
3229 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3230 break;
3231 default:
3232 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3233 }
3234 }
3235
3236 static void decode_srr_opc(DisasContext *ctx, int op1)
3237 {
3238 int r1, r2;
3239 TCGv temp;
3240
3241 r1 = MASK_OP_SRR_S1D(ctx->opcode);
3242 r2 = MASK_OP_SRR_S2(ctx->opcode);
3243
3244 switch (op1) {
3245 case OPC1_16_SRR_ADD:
3246 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3247 break;
3248 case OPC1_16_SRR_ADD_A15:
3249 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3250 break;
3251 case OPC1_16_SRR_ADD_15A:
3252 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3253 break;
3254 case OPC1_16_SRR_ADD_A:
3255 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3256 break;
3257 case OPC1_16_SRR_ADDS:
3258 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3259 break;
3260 case OPC1_16_SRR_AND:
3261 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3262 break;
3263 case OPC1_16_SRR_CMOV:
3264 temp = tcg_constant_tl(0);
3265 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3266 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3267 break;
3268 case OPC1_16_SRR_CMOVN:
3269 temp = tcg_constant_tl(0);
3270 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3271 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3272 break;
3273 case OPC1_16_SRR_EQ:
3274 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3275 cpu_gpr_d[r2]);
3276 break;
3277 case OPC1_16_SRR_LT:
3278 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3279 cpu_gpr_d[r2]);
3280 break;
3281 case OPC1_16_SRR_MOV:
3282 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3283 break;
3284 case OPC1_16_SRR_MOV_A:
3285 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3286 break;
3287 case OPC1_16_SRR_MOV_AA:
3288 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3289 break;
3290 case OPC1_16_SRR_MOV_D:
3291 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3292 break;
3293 case OPC1_16_SRR_MUL:
3294 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3295 break;
3296 case OPC1_16_SRR_OR:
3297 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3298 break;
3299 case OPC1_16_SRR_SUB:
3300 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3301 break;
3302 case OPC1_16_SRR_SUB_A15B:
3303 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3304 break;
3305 case OPC1_16_SRR_SUB_15AB:
3306 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3307 break;
3308 case OPC1_16_SRR_SUBS:
3309 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3310 break;
3311 case OPC1_16_SRR_XOR:
3312 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3313 break;
3314 default:
3315 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3316 }
3317 }
3318
3319 static void decode_ssr_opc(DisasContext *ctx, int op1)
3320 {
3321 int r1, r2;
3322
3323 r1 = MASK_OP_SSR_S1(ctx->opcode);
3324 r2 = MASK_OP_SSR_S2(ctx->opcode);
3325
3326 switch (op1) {
3327 case OPC1_16_SSR_ST_A:
3328 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3329 break;
3330 case OPC1_16_SSR_ST_A_POSTINC:
3331 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3332 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3333 break;
3334 case OPC1_16_SSR_ST_B:
3335 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3336 break;
3337 case OPC1_16_SSR_ST_B_POSTINC:
3338 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3339 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3340 break;
3341 case OPC1_16_SSR_ST_H:
3342 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3343 break;
3344 case OPC1_16_SSR_ST_H_POSTINC:
3345 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3346 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3347 break;
3348 case OPC1_16_SSR_ST_W:
3349 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3350 break;
3351 case OPC1_16_SSR_ST_W_POSTINC:
3352 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3353 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3354 break;
3355 default:
3356 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3357 }
3358 }
3359
3360 static void decode_sc_opc(DisasContext *ctx, int op1)
3361 {
3362 int32_t const16;
3363
3364 const16 = MASK_OP_SC_CONST8(ctx->opcode);
3365
3366 switch (op1) {
3367 case OPC1_16_SC_AND:
3368 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3369 break;
3370 case OPC1_16_SC_BISR:
3371 if (ctx->priv == TRICORE_PRIV_SM) {
3372 gen_helper_1arg(bisr, const16 & 0xff);
3373 } else {
3374 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
3375 }
3376 break;
3377 case OPC1_16_SC_LD_A:
3378 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3379 break;
3380 case OPC1_16_SC_LD_W:
3381 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3382 break;
3383 case OPC1_16_SC_MOV:
3384 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3385 break;
3386 case OPC1_16_SC_OR:
3387 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3388 break;
3389 case OPC1_16_SC_ST_A:
3390 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3391 break;
3392 case OPC1_16_SC_ST_W:
3393 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3394 break;
3395 case OPC1_16_SC_SUB_A:
3396 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3397 break;
3398 default:
3399 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3400 }
3401 }
3402
3403 static void decode_slr_opc(DisasContext *ctx, int op1)
3404 {
3405 int r1, r2;
3406
3407 r1 = MASK_OP_SLR_D(ctx->opcode);
3408 r2 = MASK_OP_SLR_S2(ctx->opcode);
3409
3410 switch (op1) {
3411 /* SLR-format */
3412 case OPC1_16_SLR_LD_A:
3413 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3414 break;
3415 case OPC1_16_SLR_LD_A_POSTINC:
3416 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3417 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3418 break;
3419 case OPC1_16_SLR_LD_BU:
3420 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3421 break;
3422 case OPC1_16_SLR_LD_BU_POSTINC:
3423 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3424 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3425 break;
3426 case OPC1_16_SLR_LD_H:
3427 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3428 break;
3429 case OPC1_16_SLR_LD_H_POSTINC:
3430 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3431 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3432 break;
3433 case OPC1_16_SLR_LD_W:
3434 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3435 break;
3436 case OPC1_16_SLR_LD_W_POSTINC:
3437 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3438 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3439 break;
3440 default:
3441 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3442 }
3443 }
3444
3445 static void decode_sro_opc(DisasContext *ctx, int op1)
3446 {
3447 int r2;
3448 int32_t address;
3449
3450 r2 = MASK_OP_SRO_S2(ctx->opcode);
3451 address = MASK_OP_SRO_OFF4(ctx->opcode);
3452
3453 /* SRO-format */
3454 switch (op1) {
3455 case OPC1_16_SRO_LD_A:
3456 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3457 break;
3458 case OPC1_16_SRO_LD_BU:
3459 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3460 break;
3461 case OPC1_16_SRO_LD_H:
3462 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3463 break;
3464 case OPC1_16_SRO_LD_W:
3465 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3466 break;
3467 case OPC1_16_SRO_ST_A:
3468 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3469 break;
3470 case OPC1_16_SRO_ST_B:
3471 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3472 break;
3473 case OPC1_16_SRO_ST_H:
3474 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3475 break;
3476 case OPC1_16_SRO_ST_W:
3477 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3478 break;
3479 default:
3480 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3481 }
3482 }
3483
3484 static void decode_sr_system(DisasContext *ctx)
3485 {
3486 uint32_t op2;
3487 op2 = MASK_OP_SR_OP2(ctx->opcode);
3488
3489 switch (op2) {
3490 case OPC2_16_SR_NOP:
3491 break;
3492 case OPC2_16_SR_RET:
3493 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3494 break;
3495 case OPC2_16_SR_RFE:
3496 gen_helper_rfe(cpu_env);
3497 ctx->base.is_jmp = DISAS_EXIT;
3498 break;
3499 case OPC2_16_SR_DEBUG:
3500 /* raise EXCP_DEBUG */
3501 break;
3502 case OPC2_16_SR_FRET:
3503 gen_fret(ctx);
3504 break;
3505 default:
3506 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3507 }
3508 }
3509
3510 static void decode_sr_accu(DisasContext *ctx)
3511 {
3512 uint32_t op2;
3513 uint32_t r1;
3514
3515 r1 = MASK_OP_SR_S1D(ctx->opcode);
3516 op2 = MASK_OP_SR_OP2(ctx->opcode);
3517
3518 switch (op2) {
3519 case OPC2_16_SR_RSUB:
3520 /* calc V bit -- overflow only if r1 = -0x80000000 */
3521 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000);
3522 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3523 /* calc SV bit */
3524 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3525 /* sub */
3526 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3527 /* calc av */
3528 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3529 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3530 /* calc sav */
3531 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3532 break;
3533 case OPC2_16_SR_SAT_B:
3534 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3535 break;
3536 case OPC2_16_SR_SAT_BU:
3537 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3538 break;
3539 case OPC2_16_SR_SAT_H:
3540 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3541 break;
3542 case OPC2_16_SR_SAT_HU:
3543 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3544 break;
3545 default:
3546 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3547 }
3548 }
3549
3550 static void decode_16Bit_opc(DisasContext *ctx)
3551 {
3552 int op1;
3553 int r1, r2;
3554 int32_t const16;
3555 int32_t address;
3556 TCGv temp;
3557
3558 op1 = MASK_OP_MAJOR(ctx->opcode);
3559
3560 /* handle ADDSC.A opcode only being 6 bit long */
3561 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3562 op1 = OPC1_16_SRRS_ADDSC_A;
3563 }
3564
3565 switch (op1) {
3566 case OPC1_16_SRC_ADD:
3567 case OPC1_16_SRC_ADD_A15:
3568 case OPC1_16_SRC_ADD_15A:
3569 case OPC1_16_SRC_ADD_A:
3570 case OPC1_16_SRC_CADD:
3571 case OPC1_16_SRC_CADDN:
3572 case OPC1_16_SRC_CMOV:
3573 case OPC1_16_SRC_CMOVN:
3574 case OPC1_16_SRC_EQ:
3575 case OPC1_16_SRC_LT:
3576 case OPC1_16_SRC_MOV:
3577 case OPC1_16_SRC_MOV_A:
3578 case OPC1_16_SRC_MOV_E:
3579 case OPC1_16_SRC_SH:
3580 case OPC1_16_SRC_SHA:
3581 decode_src_opc(ctx, op1);
3582 break;
3583 /* SRR-format */
3584 case OPC1_16_SRR_ADD:
3585 case OPC1_16_SRR_ADD_A15:
3586 case OPC1_16_SRR_ADD_15A:
3587 case OPC1_16_SRR_ADD_A:
3588 case OPC1_16_SRR_ADDS:
3589 case OPC1_16_SRR_AND:
3590 case OPC1_16_SRR_CMOV:
3591 case OPC1_16_SRR_CMOVN:
3592 case OPC1_16_SRR_EQ:
3593 case OPC1_16_SRR_LT:
3594 case OPC1_16_SRR_MOV:
3595 case OPC1_16_SRR_MOV_A:
3596 case OPC1_16_SRR_MOV_AA:
3597 case OPC1_16_SRR_MOV_D:
3598 case OPC1_16_SRR_MUL:
3599 case OPC1_16_SRR_OR:
3600 case OPC1_16_SRR_SUB:
3601 case OPC1_16_SRR_SUB_A15B:
3602 case OPC1_16_SRR_SUB_15AB:
3603 case OPC1_16_SRR_SUBS:
3604 case OPC1_16_SRR_XOR:
3605 decode_srr_opc(ctx, op1);
3606 break;
3607 /* SSR-format */
3608 case OPC1_16_SSR_ST_A:
3609 case OPC1_16_SSR_ST_A_POSTINC:
3610 case OPC1_16_SSR_ST_B:
3611 case OPC1_16_SSR_ST_B_POSTINC:
3612 case OPC1_16_SSR_ST_H:
3613 case OPC1_16_SSR_ST_H_POSTINC:
3614 case OPC1_16_SSR_ST_W:
3615 case OPC1_16_SSR_ST_W_POSTINC:
3616 decode_ssr_opc(ctx, op1);
3617 break;
3618 /* SRRS-format */
3619 case OPC1_16_SRRS_ADDSC_A:
3620 r2 = MASK_OP_SRRS_S2(ctx->opcode);
3621 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
3622 const16 = MASK_OP_SRRS_N(ctx->opcode);
3623 temp = tcg_temp_new();
3624 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
3625 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
3626 break;
3627 /* SLRO-format */
3628 case OPC1_16_SLRO_LD_A:
3629 r1 = MASK_OP_SLRO_D(ctx->opcode);
3630 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3631 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3632 break;
3633 case OPC1_16_SLRO_LD_BU:
3634 r1 = MASK_OP_SLRO_D(ctx->opcode);
3635 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3636 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3637 break;
3638 case OPC1_16_SLRO_LD_H:
3639 r1 = MASK_OP_SLRO_D(ctx->opcode);
3640 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3641 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3642 break;
3643 case OPC1_16_SLRO_LD_W:
3644 r1 = MASK_OP_SLRO_D(ctx->opcode);
3645 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3646 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3647 break;
3648 /* SB-format */
3649 case OPC1_16_SB_CALL:
3650 case OPC1_16_SB_J:
3651 case OPC1_16_SB_JNZ:
3652 case OPC1_16_SB_JZ:
3653 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
3654 gen_compute_branch(ctx, op1, 0, 0, 0, address);
3655 break;
3656 /* SBC-format */
3657 case OPC1_16_SBC_JEQ:
3658 case OPC1_16_SBC_JNE:
3659 address = MASK_OP_SBC_DISP4(ctx->opcode);
3660 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3661 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3662 break;
3663 case OPC1_16_SBC_JEQ2:
3664 case OPC1_16_SBC_JNE2:
3665 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3666 address = MASK_OP_SBC_DISP4(ctx->opcode);
3667 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3668 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3669 } else {
3670 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3671 }
3672 break;
3673 /* SBRN-format */
3674 case OPC1_16_SBRN_JNZ_T:
3675 case OPC1_16_SBRN_JZ_T:
3676 address = MASK_OP_SBRN_DISP4(ctx->opcode);
3677 const16 = MASK_OP_SBRN_N(ctx->opcode);
3678 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3679 break;
3680 /* SBR-format */
3681 case OPC1_16_SBR_JEQ2:
3682 case OPC1_16_SBR_JNE2:
3683 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3684 r1 = MASK_OP_SBR_S2(ctx->opcode);
3685 address = MASK_OP_SBR_DISP4(ctx->opcode);
3686 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3687 } else {
3688 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3689 }
3690 break;
3691 case OPC1_16_SBR_JEQ:
3692 case OPC1_16_SBR_JGEZ:
3693 case OPC1_16_SBR_JGTZ:
3694 case OPC1_16_SBR_JLEZ:
3695 case OPC1_16_SBR_JLTZ:
3696 case OPC1_16_SBR_JNE:
3697 case OPC1_16_SBR_JNZ:
3698 case OPC1_16_SBR_JNZ_A:
3699 case OPC1_16_SBR_JZ:
3700 case OPC1_16_SBR_JZ_A:
3701 case OPC1_16_SBR_LOOP:
3702 r1 = MASK_OP_SBR_S2(ctx->opcode);
3703 address = MASK_OP_SBR_DISP4(ctx->opcode);
3704 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3705 break;
3706 /* SC-format */
3707 case OPC1_16_SC_AND:
3708 case OPC1_16_SC_BISR:
3709 case OPC1_16_SC_LD_A:
3710 case OPC1_16_SC_LD_W:
3711 case OPC1_16_SC_MOV:
3712 case OPC1_16_SC_OR:
3713 case OPC1_16_SC_ST_A:
3714 case OPC1_16_SC_ST_W:
3715 case OPC1_16_SC_SUB_A:
3716 decode_sc_opc(ctx, op1);
3717 break;
3718 /* SLR-format */
3719 case OPC1_16_SLR_LD_A:
3720 case OPC1_16_SLR_LD_A_POSTINC:
3721 case OPC1_16_SLR_LD_BU:
3722 case OPC1_16_SLR_LD_BU_POSTINC:
3723 case OPC1_16_SLR_LD_H:
3724 case OPC1_16_SLR_LD_H_POSTINC:
3725 case OPC1_16_SLR_LD_W:
3726 case OPC1_16_SLR_LD_W_POSTINC:
3727 decode_slr_opc(ctx, op1);
3728 break;
3729 /* SRO-format */
3730 case OPC1_16_SRO_LD_A:
3731 case OPC1_16_SRO_LD_BU:
3732 case OPC1_16_SRO_LD_H:
3733 case OPC1_16_SRO_LD_W:
3734 case OPC1_16_SRO_ST_A:
3735 case OPC1_16_SRO_ST_B:
3736 case OPC1_16_SRO_ST_H:
3737 case OPC1_16_SRO_ST_W:
3738 decode_sro_opc(ctx, op1);
3739 break;
3740 /* SSRO-format */
3741 case OPC1_16_SSRO_ST_A:
3742 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3743 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3744 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3745 break;
3746 case OPC1_16_SSRO_ST_B:
3747 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3748 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3749 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3750 break;
3751 case OPC1_16_SSRO_ST_H:
3752 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3753 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3754 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3755 break;
3756 case OPC1_16_SSRO_ST_W:
3757 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3758 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3759 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3760 break;
3761 /* SR-format */
3762 case OPCM_16_SR_SYSTEM:
3763 decode_sr_system(ctx);
3764 break;
3765 case OPCM_16_SR_ACCU:
3766 decode_sr_accu(ctx);
3767 break;
3768 case OPC1_16_SR_JI:
3769 r1 = MASK_OP_SR_S1D(ctx->opcode);
3770 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
3771 break;
3772 case OPC1_16_SR_NOT:
3773 r1 = MASK_OP_SR_S1D(ctx->opcode);
3774 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3775 break;
3776 default:
3777 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3778 }
3779 }
3780
3781 /*
3782 * 32 bit instructions
3783 */
3784
3785 /* ABS-format */
3786 static void decode_abs_ldw(DisasContext *ctx)
3787 {
3788 int32_t op2;
3789 int32_t r1;
3790 uint32_t address;
3791 TCGv temp;
3792
3793 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3794 address = MASK_OP_ABS_OFF18(ctx->opcode);
3795 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3796
3797 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3798
3799 switch (op2) {
3800 case OPC2_32_ABS_LD_A:
3801 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3802 break;
3803 case OPC2_32_ABS_LD_D:
3804 CHECK_REG_PAIR(r1);
3805 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3806 break;
3807 case OPC2_32_ABS_LD_DA:
3808 CHECK_REG_PAIR(r1);
3809 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3810 break;
3811 case OPC2_32_ABS_LD_W:
3812 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3813 break;
3814 default:
3815 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3816 }
3817 }
3818
3819 static void decode_abs_ldb(DisasContext *ctx)
3820 {
3821 int32_t op2;
3822 int32_t r1;
3823 uint32_t address;
3824 TCGv temp;
3825
3826 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3827 address = MASK_OP_ABS_OFF18(ctx->opcode);
3828 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3829
3830 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3831
3832 switch (op2) {
3833 case OPC2_32_ABS_LD_B:
3834 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
3835 break;
3836 case OPC2_32_ABS_LD_BU:
3837 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3838 break;
3839 case OPC2_32_ABS_LD_H:
3840 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
3841 break;
3842 case OPC2_32_ABS_LD_HU:
3843 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3844 break;
3845 default:
3846 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3847 }
3848 }
3849
3850 static void decode_abs_ldst_swap(DisasContext *ctx)
3851 {
3852 int32_t op2;
3853 int32_t r1;
3854 uint32_t address;
3855 TCGv temp;
3856
3857 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3858 address = MASK_OP_ABS_OFF18(ctx->opcode);
3859 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3860
3861 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3862
3863 switch (op2) {
3864 case OPC2_32_ABS_LDMST:
3865 gen_ldmst(ctx, r1, temp);
3866 break;
3867 case OPC2_32_ABS_SWAP_W:
3868 gen_swap(ctx, r1, temp);
3869 break;
3870 default:
3871 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3872 }
3873 }
3874
3875 static void decode_abs_ldst_context(DisasContext *ctx)
3876 {
3877 uint32_t op2;
3878 int32_t off18;
3879
3880 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
3881 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3882
3883 switch (op2) {
3884 case OPC2_32_ABS_LDLCX:
3885 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
3886 break;
3887 case OPC2_32_ABS_LDUCX:
3888 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
3889 break;
3890 case OPC2_32_ABS_STLCX:
3891 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
3892 break;
3893 case OPC2_32_ABS_STUCX:
3894 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
3895 break;
3896 default:
3897 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3898 }
3899 }
3900
3901 static void decode_abs_store(DisasContext *ctx)
3902 {
3903 int32_t op2;
3904 int32_t r1;
3905 uint32_t address;
3906 TCGv temp;
3907
3908 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3909 address = MASK_OP_ABS_OFF18(ctx->opcode);
3910 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3911
3912 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3913
3914 switch (op2) {
3915 case OPC2_32_ABS_ST_A:
3916 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3917 break;
3918 case OPC2_32_ABS_ST_D:
3919 CHECK_REG_PAIR(r1);
3920 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3921 break;
3922 case OPC2_32_ABS_ST_DA:
3923 CHECK_REG_PAIR(r1);
3924 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3925 break;
3926 case OPC2_32_ABS_ST_W:
3927 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3928 break;
3929 default:
3930 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3931 }
3932 }
3933
3934 static void decode_abs_storeb_h(DisasContext *ctx)
3935 {
3936 int32_t op2;
3937 int32_t r1;
3938 uint32_t address;
3939 TCGv temp;
3940
3941 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3942 address = MASK_OP_ABS_OFF18(ctx->opcode);
3943 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3944
3945 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3946
3947 switch (op2) {
3948 case OPC2_32_ABS_ST_B:
3949 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3950 break;
3951 case OPC2_32_ABS_ST_H:
3952 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3953 break;
3954 default:
3955 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3956 }
3957 }
3958
3959 /* Bit-format */
3960
3961 static void decode_bit_andacc(DisasContext *ctx)
3962 {
3963 uint32_t op2;
3964 int r1, r2, r3;
3965 int pos1, pos2;
3966
3967 r1 = MASK_OP_BIT_S1(ctx->opcode);
3968 r2 = MASK_OP_BIT_S2(ctx->opcode);
3969 r3 = MASK_OP_BIT_D(ctx->opcode);
3970 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3971 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3972 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3973
3974
3975 switch (op2) {
3976 case OPC2_32_BIT_AND_AND_T:
3977 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3978 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
3979 break;
3980 case OPC2_32_BIT_AND_ANDN_T:
3981 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3982 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
3983 break;
3984 case OPC2_32_BIT_AND_NOR_T:
3985 if (TCG_TARGET_HAS_andc_i32) {
3986 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3987 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
3988 } else {
3989 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3990 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
3991 }
3992 break;
3993 case OPC2_32_BIT_AND_OR_T:
3994 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3995 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
3996 break;
3997 default:
3998 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3999 }
4000 }
4001
4002 static void decode_bit_logical_t(DisasContext *ctx)
4003 {
4004 uint32_t op2;
4005 int r1, r2, r3;
4006 int pos1, pos2;
4007 r1 = MASK_OP_BIT_S1(ctx->opcode);
4008 r2 = MASK_OP_BIT_S2(ctx->opcode);
4009 r3 = MASK_OP_BIT_D(ctx->opcode);
4010 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4011 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4012 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4013
4014 switch (op2) {
4015 case OPC2_32_BIT_AND_T:
4016 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4017 pos1, pos2, &tcg_gen_and_tl);
4018 break;
4019 case OPC2_32_BIT_ANDN_T:
4020 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4021 pos1, pos2, &tcg_gen_andc_tl);
4022 break;
4023 case OPC2_32_BIT_NOR_T:
4024 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4025 pos1, pos2, &tcg_gen_nor_tl);
4026 break;
4027 case OPC2_32_BIT_OR_T:
4028 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4029 pos1, pos2, &tcg_gen_or_tl);
4030 break;
4031 default:
4032 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4033 }
4034 }
4035
4036 static void decode_bit_insert(DisasContext *ctx)
4037 {
4038 uint32_t op2;
4039 int r1, r2, r3;
4040 int pos1, pos2;
4041 TCGv temp;
4042 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4043 r1 = MASK_OP_BIT_S1(ctx->opcode);
4044 r2 = MASK_OP_BIT_S2(ctx->opcode);
4045 r3 = MASK_OP_BIT_D(ctx->opcode);
4046 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4047 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4048
4049 temp = tcg_temp_new();
4050
4051 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4052 if (op2 == OPC2_32_BIT_INSN_T) {
4053 tcg_gen_not_tl(temp, temp);
4054 }
4055 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4056 }
4057
4058 static void decode_bit_logical_t2(DisasContext *ctx)
4059 {
4060 uint32_t op2;
4061
4062 int r1, r2, r3;
4063 int pos1, pos2;
4064
4065 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4066 r1 = MASK_OP_BIT_S1(ctx->opcode);
4067 r2 = MASK_OP_BIT_S2(ctx->opcode);
4068 r3 = MASK_OP_BIT_D(ctx->opcode);
4069 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4070 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4071
4072 switch (op2) {
4073 case OPC2_32_BIT_NAND_T:
4074 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4075 pos1, pos2, &tcg_gen_nand_tl);
4076 break;
4077 case OPC2_32_BIT_ORN_T:
4078 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4079 pos1, pos2, &tcg_gen_orc_tl);
4080 break;
4081 case OPC2_32_BIT_XNOR_T:
4082 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4083 pos1, pos2, &tcg_gen_eqv_tl);
4084 break;
4085 case OPC2_32_BIT_XOR_T:
4086 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4087 pos1, pos2, &tcg_gen_xor_tl);
4088 break;
4089 default:
4090 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4091 }
4092 }
4093
4094 static void decode_bit_orand(DisasContext *ctx)
4095 {
4096 uint32_t op2;
4097
4098 int r1, r2, r3;
4099 int pos1, pos2;
4100
4101 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4102 r1 = MASK_OP_BIT_S1(ctx->opcode);
4103 r2 = MASK_OP_BIT_S2(ctx->opcode);
4104 r3 = MASK_OP_BIT_D(ctx->opcode);
4105 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4106 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4107
4108 switch (op2) {
4109 case OPC2_32_BIT_OR_AND_T:
4110 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4111 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4112 break;
4113 case OPC2_32_BIT_OR_ANDN_T:
4114 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4115 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4116 break;
4117 case OPC2_32_BIT_OR_NOR_T:
4118 if (TCG_TARGET_HAS_orc_i32) {
4119 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4120 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4121 } else {
4122 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4123 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4124 }
4125 break;
4126 case OPC2_32_BIT_OR_OR_T:
4127 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4128 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4129 break;
4130 default:
4131 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4132 }
4133 }
4134
4135 static void decode_bit_sh_logic1(DisasContext *ctx)
4136 {
4137 uint32_t op2;
4138 int r1, r2, r3;
4139 int pos1, pos2;
4140 TCGv temp;
4141
4142 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4143 r1 = MASK_OP_BIT_S1(ctx->opcode);
4144 r2 = MASK_OP_BIT_S2(ctx->opcode);
4145 r3 = MASK_OP_BIT_D(ctx->opcode);
4146 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4147 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4148
4149 temp = tcg_temp_new();
4150
4151 switch (op2) {
4152 case OPC2_32_BIT_SH_AND_T:
4153 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4154 pos1, pos2, &tcg_gen_and_tl);
4155 break;
4156 case OPC2_32_BIT_SH_ANDN_T:
4157 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4158 pos1, pos2, &tcg_gen_andc_tl);
4159 break;
4160 case OPC2_32_BIT_SH_NOR_T:
4161 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4162 pos1, pos2, &tcg_gen_nor_tl);
4163 break;
4164 case OPC2_32_BIT_SH_OR_T:
4165 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4166 pos1, pos2, &tcg_gen_or_tl);
4167 break;
4168 default:
4169 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4170 }
4171 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4172 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4173 }
4174
4175 static void decode_bit_sh_logic2(DisasContext *ctx)
4176 {
4177 uint32_t op2;
4178 int r1, r2, r3;
4179 int pos1, pos2;
4180 TCGv temp;
4181
4182 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4183 r1 = MASK_OP_BIT_S1(ctx->opcode);
4184 r2 = MASK_OP_BIT_S2(ctx->opcode);
4185 r3 = MASK_OP_BIT_D(ctx->opcode);
4186 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4187 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4188
4189 temp = tcg_temp_new();
4190
4191 switch (op2) {
4192 case OPC2_32_BIT_SH_NAND_T:
4193 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4194 pos1, pos2, &tcg_gen_nand_tl);
4195 break;
4196 case OPC2_32_BIT_SH_ORN_T:
4197 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4198 pos1, pos2, &tcg_gen_orc_tl);
4199 break;
4200 case OPC2_32_BIT_SH_XNOR_T:
4201 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4202 pos1, pos2, &tcg_gen_eqv_tl);
4203 break;
4204 case OPC2_32_BIT_SH_XOR_T:
4205 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4206 pos1, pos2, &tcg_gen_xor_tl);
4207 break;
4208 default:
4209 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4210 }
4211 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4212 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4213 }
4214
4215 /* BO-format */
4216
4217
4218 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
4219 {
4220 uint32_t op2;
4221 uint32_t off10;
4222 int32_t r1, r2;
4223 TCGv temp;
4224
4225 r1 = MASK_OP_BO_S1D(ctx->opcode);
4226 r2 = MASK_OP_BO_S2(ctx->opcode);
4227 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4228 op2 = MASK_OP_BO_OP2(ctx->opcode);
4229
4230 switch (op2) {
4231 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4232 case OPC2_32_BO_CACHEA_W_SHORTOFF:
4233 case OPC2_32_BO_CACHEA_I_SHORTOFF:
4234 /* instruction to access the cache */
4235 break;
4236 case OPC2_32_BO_CACHEA_WI_POSTINC:
4237 case OPC2_32_BO_CACHEA_W_POSTINC:
4238 case OPC2_32_BO_CACHEA_I_POSTINC:
4239 /* instruction to access the cache, but we still need to handle
4240 the addressing mode */
4241 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4242 break;
4243 case OPC2_32_BO_CACHEA_WI_PREINC:
4244 case OPC2_32_BO_CACHEA_W_PREINC:
4245 case OPC2_32_BO_CACHEA_I_PREINC:
4246 /* instruction to access the cache, but we still need to handle
4247 the addressing mode */
4248 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4249 break;
4250 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4251 case OPC2_32_BO_CACHEI_W_SHORTOFF:
4252 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
4253 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4254 }
4255 break;
4256 case OPC2_32_BO_CACHEI_W_POSTINC:
4257 case OPC2_32_BO_CACHEI_WI_POSTINC:
4258 if (has_feature(ctx, TRICORE_FEATURE_131)) {
4259 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4260 } else {
4261 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4262 }
4263 break;
4264 case OPC2_32_BO_CACHEI_W_PREINC:
4265 case OPC2_32_BO_CACHEI_WI_PREINC:
4266 if (has_feature(ctx, TRICORE_FEATURE_131)) {
4267 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4268 } else {
4269 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4270 }
4271 break;
4272 case OPC2_32_BO_ST_A_SHORTOFF:
4273 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4274 break;
4275 case OPC2_32_BO_ST_A_POSTINC:
4276 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4277 MO_LESL);
4278 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4279 break;
4280 case OPC2_32_BO_ST_A_PREINC:
4281 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4282 break;
4283 case OPC2_32_BO_ST_B_SHORTOFF:
4284 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4285 break;
4286 case OPC2_32_BO_ST_B_POSTINC:
4287 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4288 MO_UB);
4289 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4290 break;
4291 case OPC2_32_BO_ST_B_PREINC:
4292 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4293 break;
4294 case OPC2_32_BO_ST_D_SHORTOFF:
4295 CHECK_REG_PAIR(r1);
4296 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4297 off10, ctx);
4298 break;
4299 case OPC2_32_BO_ST_D_POSTINC:
4300 CHECK_REG_PAIR(r1);
4301 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4302 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4303 break;
4304 case OPC2_32_BO_ST_D_PREINC:
4305 CHECK_REG_PAIR(r1);
4306 temp = tcg_temp_new();
4307 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4308 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4309 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4310 break;
4311 case OPC2_32_BO_ST_DA_SHORTOFF:
4312 CHECK_REG_PAIR(r1);
4313 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4314 off10, ctx);
4315 break;
4316 case OPC2_32_BO_ST_DA_POSTINC:
4317 CHECK_REG_PAIR(r1);
4318 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4319 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4320 break;
4321 case OPC2_32_BO_ST_DA_PREINC:
4322 CHECK_REG_PAIR(r1);
4323 temp = tcg_temp_new();
4324 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4325 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4326 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4327 break;
4328 case OPC2_32_BO_ST_H_SHORTOFF:
4329 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4330 break;
4331 case OPC2_32_BO_ST_H_POSTINC:
4332 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4333 MO_LEUW);
4334 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4335 break;
4336 case OPC2_32_BO_ST_H_PREINC:
4337 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4338 break;
4339 case OPC2_32_BO_ST_Q_SHORTOFF:
4340 temp = tcg_temp_new();
4341 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4342 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4343 break;
4344 case OPC2_32_BO_ST_Q_POSTINC:
4345 temp = tcg_temp_new();
4346 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4347 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4348 MO_LEUW);
4349 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4350 break;
4351 case OPC2_32_BO_ST_Q_PREINC:
4352 temp = tcg_temp_new();
4353 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4354 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4355 break;
4356 case OPC2_32_BO_ST_W_SHORTOFF:
4357 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4358 break;
4359 case OPC2_32_BO_ST_W_POSTINC:
4360 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4361 MO_LEUL);
4362 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4363 break;
4364 case OPC2_32_BO_ST_W_PREINC:
4365 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4366 break;
4367 default:
4368 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4369 }
4370 }
4371
4372 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
4373 {
4374 uint32_t op2;
4375 uint32_t off10;
4376 int32_t r1, r2;
4377 TCGv temp, temp2, t_off10;
4378
4379 r1 = MASK_OP_BO_S1D(ctx->opcode);
4380 r2 = MASK_OP_BO_S2(ctx->opcode);
4381 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4382 op2 = MASK_OP_BO_OP2(ctx->opcode);
4383
4384 temp = tcg_temp_new();
4385 temp2 = tcg_temp_new();
4386 t_off10 = tcg_constant_i32(off10);
4387 CHECK_REG_PAIR(r2);
4388 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4389 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4390
4391 switch (op2) {
4392 case OPC2_32_BO_CACHEA_WI_BR:
4393 case OPC2_32_BO_CACHEA_W_BR:
4394 case OPC2_32_BO_CACHEA_I_BR:
4395 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4396 break;
4397 case OPC2_32_BO_CACHEA_WI_CIRC:
4398 case OPC2_32_BO_CACHEA_W_CIRC:
4399 case OPC2_32_BO_CACHEA_I_CIRC:
4400 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4401 break;
4402 case OPC2_32_BO_ST_A_BR:
4403 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4404 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4405 break;
4406 case OPC2_32_BO_ST_A_CIRC:
4407 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4408 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4409 break;
4410 case OPC2_32_BO_ST_B_BR:
4411 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4412 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4413 break;
4414 case OPC2_32_BO_ST_B_CIRC:
4415 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4416 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4417 break;
4418 case OPC2_32_BO_ST_D_BR:
4419 CHECK_REG_PAIR(r1);
4420 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4421 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4422 break;
4423 case OPC2_32_BO_ST_D_CIRC:
4424 CHECK_REG_PAIR(r1);
4425 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4426 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4427 tcg_gen_addi_tl(temp, temp, 4);
4428 tcg_gen_rem_tl(temp, temp, temp2);
4429 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4430 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4431 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4432 break;
4433 case OPC2_32_BO_ST_DA_BR:
4434 CHECK_REG_PAIR(r1);
4435 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4436 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4437 break;
4438 case OPC2_32_BO_ST_DA_CIRC:
4439 CHECK_REG_PAIR(r1);
4440 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4441 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4442 tcg_gen_addi_tl(temp, temp, 4);
4443 tcg_gen_rem_tl(temp, temp, temp2);
4444 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4445 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4446 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4447 break;
4448 case OPC2_32_BO_ST_H_BR:
4449 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4450 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4451 break;
4452 case OPC2_32_BO_ST_H_CIRC:
4453 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4454 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4455 break;
4456 case OPC2_32_BO_ST_Q_BR:
4457 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4458 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4459 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4460 break;
4461 case OPC2_32_BO_ST_Q_CIRC:
4462 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4463 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4464 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4465 break;
4466 case OPC2_32_BO_ST_W_BR:
4467 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4468 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4469 break;
4470 case OPC2_32_BO_ST_W_CIRC:
4471 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4472 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4473 break;
4474 default:
4475 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4476 }
4477 }
4478
4479 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
4480 {
4481 uint32_t op2;
4482 uint32_t off10;
4483 int32_t r1, r2;
4484 TCGv temp;
4485
4486 r1 = MASK_OP_BO_S1D(ctx->opcode);
4487 r2 = MASK_OP_BO_S2(ctx->opcode);
4488 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4489 op2 = MASK_OP_BO_OP2(ctx->opcode);
4490
4491 switch (op2) {
4492 case OPC2_32_BO_LD_A_SHORTOFF:
4493 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4494 break;
4495 case OPC2_32_BO_LD_A_POSTINC:
4496 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4497 MO_LEUL);
4498 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4499 break;
4500 case OPC2_32_BO_LD_A_PREINC:
4501 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4502 break;
4503 case OPC2_32_BO_LD_B_SHORTOFF:
4504 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4505 break;
4506 case OPC2_32_BO_LD_B_POSTINC:
4507 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4508 MO_SB);
4509 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4510 break;
4511 case OPC2_32_BO_LD_B_PREINC:
4512 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4513 break;
4514 case OPC2_32_BO_LD_BU_SHORTOFF:
4515 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4516 break;
4517 case OPC2_32_BO_LD_BU_POSTINC:
4518 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4519 MO_UB);
4520 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4521 break;
4522 case OPC2_32_BO_LD_BU_PREINC:
4523 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4524 break;
4525 case OPC2_32_BO_LD_D_SHORTOFF:
4526 CHECK_REG_PAIR(r1);
4527 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4528 off10, ctx);
4529 break;
4530 case OPC2_32_BO_LD_D_POSTINC:
4531 CHECK_REG_PAIR(r1);
4532 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4533 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4534 break;
4535 case OPC2_32_BO_LD_D_PREINC:
4536 CHECK_REG_PAIR(r1);
4537 temp = tcg_temp_new();
4538 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4539 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4540 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4541 break;
4542 case OPC2_32_BO_LD_DA_SHORTOFF:
4543 CHECK_REG_PAIR(r1);
4544 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4545 off10, ctx);
4546 break;
4547 case OPC2_32_BO_LD_DA_POSTINC:
4548 CHECK_REG_PAIR(r1);
4549 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4550 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4551 break;
4552 case OPC2_32_BO_LD_DA_PREINC:
4553 CHECK_REG_PAIR(r1);
4554 temp = tcg_temp_new();
4555 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4556 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4557 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4558 break;
4559 case OPC2_32_BO_LD_H_SHORTOFF:
4560 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4561 break;
4562 case OPC2_32_BO_LD_H_POSTINC:
4563 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4564 MO_LESW);
4565 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4566 break;
4567 case OPC2_32_BO_LD_H_PREINC:
4568 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4569 break;
4570 case OPC2_32_BO_LD_HU_SHORTOFF:
4571 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4572 break;
4573 case OPC2_32_BO_LD_HU_POSTINC:
4574 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4575 MO_LEUW);
4576 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4577 break;
4578 case OPC2_32_BO_LD_HU_PREINC:
4579 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4580 break;
4581 case OPC2_32_BO_LD_Q_SHORTOFF:
4582 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4583 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4584 break;
4585 case OPC2_32_BO_LD_Q_POSTINC:
4586 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4587 MO_LEUW);
4588 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4589 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4590 break;
4591 case OPC2_32_BO_LD_Q_PREINC:
4592 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4593 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4594 break;
4595 case OPC2_32_BO_LD_W_SHORTOFF:
4596 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4597 break;
4598 case OPC2_32_BO_LD_W_POSTINC:
4599 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4600 MO_LEUL);
4601 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4602 break;
4603 case OPC2_32_BO_LD_W_PREINC:
4604 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4605 break;
4606 default:
4607 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4608 }
4609 }
4610
4611 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
4612 {
4613 uint32_t op2;
4614 uint32_t off10;
4615 int r1, r2;
4616 TCGv temp, temp2, t_off10;
4617
4618 r1 = MASK_OP_BO_S1D(ctx->opcode);
4619 r2 = MASK_OP_BO_S2(ctx->opcode);
4620 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4621 op2 = MASK_OP_BO_OP2(ctx->opcode);
4622
4623 temp = tcg_temp_new();
4624 temp2 = tcg_temp_new();
4625 t_off10 = tcg_constant_i32(off10);
4626 CHECK_REG_PAIR(r2);
4627 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4628 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4629
4630
4631 switch (op2) {
4632 case OPC2_32_BO_LD_A_BR:
4633 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4634 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4635 break;
4636 case OPC2_32_BO_LD_A_CIRC:
4637 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4638 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4639 break;
4640 case OPC2_32_BO_LD_B_BR:
4641 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4642 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4643 break;
4644 case OPC2_32_BO_LD_B_CIRC:
4645 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4646 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4647 break;
4648 case OPC2_32_BO_LD_BU_BR:
4649 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4650 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4651 break;
4652 case OPC2_32_BO_LD_BU_CIRC:
4653 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4654 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4655 break;
4656 case OPC2_32_BO_LD_D_BR:
4657 CHECK_REG_PAIR(r1);
4658 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4659 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4660 break;
4661 case OPC2_32_BO_LD_D_CIRC:
4662 CHECK_REG_PAIR(r1);
4663 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4664 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4665 tcg_gen_addi_tl(temp, temp, 4);
4666 tcg_gen_rem_tl(temp, temp, temp2);
4667 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4668 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4669 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4670 break;
4671 case OPC2_32_BO_LD_DA_BR:
4672 CHECK_REG_PAIR(r1);
4673 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4674 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4675 break;
4676 case OPC2_32_BO_LD_DA_CIRC:
4677 CHECK_REG_PAIR(r1);
4678 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4679 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4680 tcg_gen_addi_tl(temp, temp, 4);
4681 tcg_gen_rem_tl(temp, temp, temp2);
4682 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4683 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4684 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4685 break;
4686 case OPC2_32_BO_LD_H_BR:
4687 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4688 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4689 break;
4690 case OPC2_32_BO_LD_H_CIRC:
4691 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4692 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4693 break;
4694 case OPC2_32_BO_LD_HU_BR:
4695 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4696 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4697 break;
4698 case OPC2_32_BO_LD_HU_CIRC:
4699 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4700 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4701 break;
4702 case OPC2_32_BO_LD_Q_BR:
4703 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4704 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4705 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4706 break;
4707 case OPC2_32_BO_LD_Q_CIRC:
4708 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4709 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4710 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4711 break;
4712 case OPC2_32_BO_LD_W_BR:
4713 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4714 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4715 break;
4716 case OPC2_32_BO_LD_W_CIRC:
4717 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4718 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4719 break;
4720 default:
4721 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4722 }
4723 }
4724
4725 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx)
4726 {
4727 uint32_t op2;
4728 uint32_t off10;
4729 int r1, r2;
4730
4731 TCGv temp;
4732
4733 r1 = MASK_OP_BO_S1D(ctx->opcode);
4734 r2 = MASK_OP_BO_S2(ctx->opcode);
4735 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4736 op2 = MASK_OP_BO_OP2(ctx->opcode);
4737
4738
4739 temp = tcg_temp_new();
4740
4741 switch (op2) {
4742 case OPC2_32_BO_LDLCX_SHORTOFF:
4743 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4744 gen_helper_ldlcx(cpu_env, temp);
4745 break;
4746 case OPC2_32_BO_LDMST_SHORTOFF:
4747 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4748 gen_ldmst(ctx, r1, temp);
4749 break;
4750 case OPC2_32_BO_LDMST_POSTINC:
4751 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4752 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4753 break;
4754 case OPC2_32_BO_LDMST_PREINC:
4755 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4756 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4757 break;
4758 case OPC2_32_BO_LDUCX_SHORTOFF:
4759 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4760 gen_helper_lducx(cpu_env, temp);
4761 break;
4762 case OPC2_32_BO_LEA_SHORTOFF:
4763 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
4764 break;
4765 case OPC2_32_BO_STLCX_SHORTOFF:
4766 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4767 gen_helper_stlcx(cpu_env, temp);
4768 break;
4769 case OPC2_32_BO_STUCX_SHORTOFF:
4770 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4771 gen_helper_stucx(cpu_env, temp);
4772 break;
4773 case OPC2_32_BO_SWAP_W_SHORTOFF:
4774 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4775 gen_swap(ctx, r1, temp);
4776 break;
4777 case OPC2_32_BO_SWAP_W_POSTINC:
4778 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4779 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4780 break;
4781 case OPC2_32_BO_SWAP_W_PREINC:
4782 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4783 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4784 break;
4785 case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
4786 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4787 gen_cmpswap(ctx, r1, temp);
4788 break;
4789 case OPC2_32_BO_CMPSWAP_W_POSTINC:
4790 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
4791 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4792 break;
4793 case OPC2_32_BO_CMPSWAP_W_PREINC:
4794 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4795 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
4796 break;
4797 case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
4798 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4799 gen_swapmsk(ctx, r1, temp);
4800 break;
4801 case OPC2_32_BO_SWAPMSK_W_POSTINC:
4802 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
4803 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4804 break;
4805 case OPC2_32_BO_SWAPMSK_W_PREINC:
4806 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4807 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
4808 break;
4809 default:
4810 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4811 }
4812 }
4813
4814 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
4815 {
4816 uint32_t op2;
4817 uint32_t off10;
4818 int r1, r2;
4819 TCGv temp, temp2, t_off10;
4820
4821 r1 = MASK_OP_BO_S1D(ctx->opcode);
4822 r2 = MASK_OP_BO_S2(ctx->opcode);
4823 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4824 op2 = MASK_OP_BO_OP2(ctx->opcode);
4825
4826 temp = tcg_temp_new();
4827 temp2 = tcg_temp_new();
4828 t_off10 = tcg_constant_i32(off10);
4829 CHECK_REG_PAIR(r2);
4830 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4831 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4832
4833 switch (op2) {
4834 case OPC2_32_BO_LDMST_BR:
4835 gen_ldmst(ctx, r1, temp2);
4836 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4837 break;
4838 case OPC2_32_BO_LDMST_CIRC:
4839 gen_ldmst(ctx, r1, temp2);
4840 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4841 break;
4842 case OPC2_32_BO_SWAP_W_BR:
4843 gen_swap(ctx, r1, temp2);
4844 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4845 break;
4846 case OPC2_32_BO_SWAP_W_CIRC:
4847 gen_swap(ctx, r1, temp2);
4848 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4849 break;
4850 case OPC2_32_BO_CMPSWAP_W_BR:
4851 gen_cmpswap(ctx, r1, temp2);
4852 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4853 break;
4854 case OPC2_32_BO_CMPSWAP_W_CIRC:
4855 gen_cmpswap(ctx, r1, temp2);
4856 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4857 break;
4858 case OPC2_32_BO_SWAPMSK_W_BR:
4859 gen_swapmsk(ctx, r1, temp2);
4860 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4861 break;
4862 case OPC2_32_BO_SWAPMSK_W_CIRC:
4863 gen_swapmsk(ctx, r1, temp2);
4864 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4865 break;
4866 default:
4867 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4868 }
4869 }
4870
4871 static void decode_bol_opc(DisasContext *ctx, int32_t op1)
4872 {
4873 int r1, r2;
4874 int32_t address;
4875 TCGv temp;
4876
4877 r1 = MASK_OP_BOL_S1D(ctx->opcode);
4878 r2 = MASK_OP_BOL_S2(ctx->opcode);
4879 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
4880
4881 switch (op1) {
4882 case OPC1_32_BOL_LD_A_LONGOFF:
4883 temp = tcg_temp_new();
4884 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4885 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
4886 break;
4887 case OPC1_32_BOL_LD_W_LONGOFF:
4888 temp = tcg_temp_new();
4889 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4890 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
4891 break;
4892 case OPC1_32_BOL_LEA_LONGOFF:
4893 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
4894 break;
4895 case OPC1_32_BOL_ST_A_LONGOFF:
4896 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4897 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
4898 } else {
4899 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4900 }
4901 break;
4902 case OPC1_32_BOL_ST_W_LONGOFF:
4903 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
4904 break;
4905 case OPC1_32_BOL_LD_B_LONGOFF:
4906 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4907 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4908 } else {
4909 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4910 }
4911 break;
4912 case OPC1_32_BOL_LD_BU_LONGOFF:
4913 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4914 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
4915 } else {
4916 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4917 }
4918 break;
4919 case OPC1_32_BOL_LD_H_LONGOFF:
4920 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4921 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4922 } else {
4923 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4924 }
4925 break;
4926 case OPC1_32_BOL_LD_HU_LONGOFF:
4927 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4928 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
4929 } else {
4930 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4931 }
4932 break;
4933 case OPC1_32_BOL_ST_B_LONGOFF:
4934 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4935 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4936 } else {
4937 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4938 }
4939 break;
4940 case OPC1_32_BOL_ST_H_LONGOFF:
4941 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4942 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4943 } else {
4944 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4945 }
4946 break;
4947 default:
4948 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4949 }
4950 }
4951
4952 /* RC format */
4953 static void decode_rc_logical_shift(DisasContext *ctx)
4954 {
4955 uint32_t op2;
4956 int r1, r2;
4957 int32_t const9;
4958 TCGv temp;
4959
4960 r2 = MASK_OP_RC_D(ctx->opcode);
4961 r1 = MASK_OP_RC_S1(ctx->opcode);
4962 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4963 op2 = MASK_OP_RC_OP2(ctx->opcode);
4964
4965 temp = tcg_temp_new();
4966
4967 switch (op2) {
4968 case OPC2_32_RC_AND:
4969 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4970 break;
4971 case OPC2_32_RC_ANDN:
4972 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4973 break;
4974 case OPC2_32_RC_NAND:
4975 tcg_gen_movi_tl(temp, const9);
4976 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4977 break;
4978 case OPC2_32_RC_NOR:
4979 tcg_gen_movi_tl(temp, const9);
4980 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4981 break;
4982 case OPC2_32_RC_OR:
4983 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4984 break;
4985 case OPC2_32_RC_ORN:
4986 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4987 break;
4988 case OPC2_32_RC_SH:
4989 const9 = sextract32(const9, 0, 6);
4990 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4991 break;
4992 case OPC2_32_RC_SH_H:
4993 const9 = sextract32(const9, 0, 5);
4994 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4995 break;
4996 case OPC2_32_RC_SHA:
4997 const9 = sextract32(const9, 0, 6);
4998 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4999 break;
5000 case OPC2_32_RC_SHA_H:
5001 const9 = sextract32(const9, 0, 5);
5002 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5003 break;
5004 case OPC2_32_RC_SHAS:
5005 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5006 break;
5007 case OPC2_32_RC_XNOR:
5008 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5009 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
5010 break;
5011 case OPC2_32_RC_XOR:
5012 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5013 break;
5014 case OPC2_32_RC_SHUFFLE:
5015 if (has_feature(ctx, TRICORE_FEATURE_162)) {
5016 TCGv temp = tcg_constant_i32(const9);
5017 gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5018 } else {
5019 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5020 }
5021 break;
5022 default:
5023 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5024 }
5025 }
5026
5027 static void decode_rc_accumulator(DisasContext *ctx)
5028 {
5029 uint32_t op2;
5030 int r1, r2;
5031 int16_t const9;
5032
5033 TCGv temp;
5034
5035 r2 = MASK_OP_RC_D(ctx->opcode);
5036 r1 = MASK_OP_RC_S1(ctx->opcode);
5037 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5038
5039 op2 = MASK_OP_RC_OP2(ctx->opcode);
5040
5041 temp = tcg_temp_new();
5042
5043 switch (op2) {
5044 case OPC2_32_RC_ABSDIF:
5045 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5046 break;
5047 case OPC2_32_RC_ABSDIFS:
5048 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5049 break;
5050 case OPC2_32_RC_ADD:
5051 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5052 break;
5053 case OPC2_32_RC_ADDC:
5054 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5055 break;
5056 case OPC2_32_RC_ADDS:
5057 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5058 break;
5059 case OPC2_32_RC_ADDS_U:
5060 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5061 break;
5062 case OPC2_32_RC_ADDX:
5063 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5064 break;
5065 case OPC2_32_RC_AND_EQ:
5066 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5067 const9, &tcg_gen_and_tl);
5068 break;
5069 case OPC2_32_RC_AND_GE:
5070 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5071 const9, &tcg_gen_and_tl);
5072 break;
5073 case OPC2_32_RC_AND_GE_U:
5074 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5075 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5076 const9, &tcg_gen_and_tl);
5077 break;
5078 case OPC2_32_RC_AND_LT:
5079 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5080 const9, &tcg_gen_and_tl);
5081 break;
5082 case OPC2_32_RC_AND_LT_U:
5083 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5084 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5085 const9, &tcg_gen_and_tl);
5086 break;
5087 case OPC2_32_RC_AND_NE:
5088 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5089 const9, &tcg_gen_and_tl);
5090 break;
5091 case OPC2_32_RC_EQ:
5092 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5093 break;
5094 case OPC2_32_RC_EQANY_B:
5095 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5096 break;
5097 case OPC2_32_RC_EQANY_H:
5098 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5099 break;
5100 case OPC2_32_RC_GE:
5101 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5102 break;
5103 case OPC2_32_RC_GE_U:
5104 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5105 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5106 break;
5107 case OPC2_32_RC_LT:
5108 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5109 break;
5110 case OPC2_32_RC_LT_U:
5111 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5112 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5113 break;
5114 case OPC2_32_RC_MAX:
5115 tcg_gen_movi_tl(temp, const9);
5116 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5117 cpu_gpr_d[r1], temp);
5118 break;
5119 case OPC2_32_RC_MAX_U:
5120 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5121 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5122 cpu_gpr_d[r1], temp);
5123 break;
5124 case OPC2_32_RC_MIN:
5125 tcg_gen_movi_tl(temp, const9);
5126 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5127 cpu_gpr_d[r1], temp);
5128 break;
5129 case OPC2_32_RC_MIN_U:
5130 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5131 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5132 cpu_gpr_d[r1], temp);
5133 break;
5134 case OPC2_32_RC_NE:
5135 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5136 break;
5137 case OPC2_32_RC_OR_EQ:
5138 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5139 const9, &tcg_gen_or_tl);
5140 break;
5141 case OPC2_32_RC_OR_GE:
5142 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5143 const9, &tcg_gen_or_tl);
5144 break;
5145 case OPC2_32_RC_OR_GE_U:
5146 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5147 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5148 const9, &tcg_gen_or_tl);
5149 break;
5150 case OPC2_32_RC_OR_LT:
5151 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5152 const9, &tcg_gen_or_tl);
5153 break;
5154 case OPC2_32_RC_OR_LT_U:
5155 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5156 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5157 const9, &tcg_gen_or_tl);
5158 break;
5159 case OPC2_32_RC_OR_NE:
5160 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5161 const9, &tcg_gen_or_tl);
5162 break;
5163 case OPC2_32_RC_RSUB:
5164 tcg_gen_movi_tl(temp, const9);
5165 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5166 break;
5167 case OPC2_32_RC_RSUBS:
5168 tcg_gen_movi_tl(temp, const9);
5169 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5170 break;
5171 case OPC2_32_RC_RSUBS_U:
5172 tcg_gen_movi_tl(temp, const9);
5173 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5174 break;
5175 case OPC2_32_RC_SH_EQ:
5176 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5177 break;
5178 case OPC2_32_RC_SH_GE:
5179 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5180 break;
5181 case OPC2_32_RC_SH_GE_U:
5182 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5183 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5184 break;
5185 case OPC2_32_RC_SH_LT:
5186 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5187 break;
5188 case OPC2_32_RC_SH_LT_U:
5189 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5190 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5191 break;
5192 case OPC2_32_RC_SH_NE:
5193 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5194 break;
5195 case OPC2_32_RC_XOR_EQ:
5196 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5197 const9, &tcg_gen_xor_tl);
5198 break;
5199 case OPC2_32_RC_XOR_GE:
5200 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5201 const9, &tcg_gen_xor_tl);
5202 break;
5203 case OPC2_32_RC_XOR_GE_U:
5204 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5205 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5206 const9, &tcg_gen_xor_tl);
5207 break;
5208 case OPC2_32_RC_XOR_LT:
5209 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5210 const9, &tcg_gen_xor_tl);
5211 break;
5212 case OPC2_32_RC_XOR_LT_U:
5213 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5214 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5215 const9, &tcg_gen_xor_tl);
5216 break;
5217 case OPC2_32_RC_XOR_NE:
5218 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5219 const9, &tcg_gen_xor_tl);
5220 break;
5221 default:
5222 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5223 }
5224 }
5225
5226 static void decode_rc_serviceroutine(DisasContext *ctx)
5227 {
5228 uint32_t op2;
5229 uint32_t const9;
5230
5231 op2 = MASK_OP_RC_OP2(ctx->opcode);
5232 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5233
5234 switch (op2) {
5235 case OPC2_32_RC_BISR:
5236 if (ctx->priv == TRICORE_PRIV_SM) {
5237 gen_helper_1arg(bisr, const9);
5238 } else {
5239 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
5240 }
5241 break;
5242 case OPC2_32_RC_SYSCALL:
5243 generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff);
5244 break;
5245 default:
5246 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5247 }
5248 }
5249
5250 static void decode_rc_mul(DisasContext *ctx)
5251 {
5252 uint32_t op2;
5253 int r1, r2;
5254 int16_t const9;
5255
5256 r2 = MASK_OP_RC_D(ctx->opcode);
5257 r1 = MASK_OP_RC_S1(ctx->opcode);
5258 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5259
5260 op2 = MASK_OP_RC_OP2(ctx->opcode);
5261
5262 switch (op2) {
5263 case OPC2_32_RC_MUL_32:
5264 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5265 break;
5266 case OPC2_32_RC_MUL_64:
5267 CHECK_REG_PAIR(r2);
5268 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5269 break;
5270 case OPC2_32_RC_MULS_32:
5271 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5272 break;
5273 case OPC2_32_RC_MUL_U_64:
5274 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5275 CHECK_REG_PAIR(r2);
5276 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5277 break;
5278 case OPC2_32_RC_MULS_U_32:
5279 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5280 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5281 break;
5282 default:
5283 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5284 }
5285 }
5286
5287 /* RCPW format */
5288 static void decode_rcpw_insert(DisasContext *ctx)
5289 {
5290 uint32_t op2;
5291 int r1, r2;
5292 int32_t pos, width, const4;
5293
5294 TCGv temp;
5295
5296 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
5297 r1 = MASK_OP_RCPW_S1(ctx->opcode);
5298 r2 = MASK_OP_RCPW_D(ctx->opcode);
5299 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
5300 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
5301 pos = MASK_OP_RCPW_POS(ctx->opcode);
5302
5303 switch (op2) {
5304 case OPC2_32_RCPW_IMASK:
5305 CHECK_REG_PAIR(r2);
5306 /* if pos + width > 32 undefined result */
5307 if (pos + width <= 32) {
5308 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
5309 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
5310 }
5311 break;
5312 case OPC2_32_RCPW_INSERT:
5313 /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
5314 if (width == 0) {
5315 tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]);
5316 /* if pos + width > 32 undefined result */
5317 } else if (pos + width <= 32) {
5318 temp = tcg_constant_i32(const4);
5319 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
5320 }
5321 break;
5322 default:
5323 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5324 }
5325 }
5326
5327 /* RCRW format */
5328
5329 static void decode_rcrw_insert(DisasContext *ctx)
5330 {
5331 uint32_t op2;
5332 int r1, r3, r4;
5333 int32_t width, const4;
5334
5335 TCGv temp, temp2, temp3;
5336
5337 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
5338 r1 = MASK_OP_RCRW_S1(ctx->opcode);
5339 r3 = MASK_OP_RCRW_S3(ctx->opcode);
5340 r4 = MASK_OP_RCRW_D(ctx->opcode);
5341 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
5342 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
5343
5344 temp = tcg_temp_new();
5345 temp2 = tcg_temp_new();
5346
5347 switch (op2) {
5348 case OPC2_32_RCRW_IMASK:
5349 CHECK_REG_PAIR(r4);
5350 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
5351 tcg_gen_movi_tl(temp2, (1 << width) - 1);
5352 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
5353 tcg_gen_movi_tl(temp2, const4);
5354 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
5355 break;
5356 case OPC2_32_RCRW_INSERT:
5357 temp3 = tcg_temp_new();
5358
5359 tcg_gen_movi_tl(temp, width);
5360 tcg_gen_movi_tl(temp2, const4);
5361 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
5362 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
5363 break;
5364 default:
5365 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5366 }
5367 }
5368
5369 /* RCR format */
5370
5371 static void decode_rcr_cond_select(DisasContext *ctx)
5372 {
5373 uint32_t op2;
5374 int r1, r3, r4;
5375 int32_t const9;
5376
5377 TCGv temp, temp2;
5378
5379 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5380 r1 = MASK_OP_RCR_S1(ctx->opcode);
5381 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5382 r3 = MASK_OP_RCR_S3(ctx->opcode);
5383 r4 = MASK_OP_RCR_D(ctx->opcode);
5384
5385 switch (op2) {
5386 case OPC2_32_RCR_CADD:
5387 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
5388 cpu_gpr_d[r3]);
5389 break;
5390 case OPC2_32_RCR_CADDN:
5391 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
5392 cpu_gpr_d[r3]);
5393 break;
5394 case OPC2_32_RCR_SEL:
5395 temp = tcg_constant_i32(0);
5396 temp2 = tcg_constant_i32(const9);
5397 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5398 cpu_gpr_d[r1], temp2);
5399 break;
5400 case OPC2_32_RCR_SELN:
5401 temp = tcg_constant_i32(0);
5402 temp2 = tcg_constant_i32(const9);
5403 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5404 cpu_gpr_d[r1], temp2);
5405 break;
5406 default:
5407 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5408 }
5409 }
5410
5411 static void decode_rcr_madd(DisasContext *ctx)
5412 {
5413 uint32_t op2;
5414 int r1, r3, r4;
5415 int32_t const9;
5416
5417
5418 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5419 r1 = MASK_OP_RCR_S1(ctx->opcode);
5420 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5421 r3 = MASK_OP_RCR_S3(ctx->opcode);
5422 r4 = MASK_OP_RCR_D(ctx->opcode);
5423
5424 switch (op2) {
5425 case OPC2_32_RCR_MADD_32:
5426 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5427 break;
5428 case OPC2_32_RCR_MADD_64:
5429 CHECK_REG_PAIR(r4);
5430 CHECK_REG_PAIR(r3);
5431 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5432 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5433 break;
5434 case OPC2_32_RCR_MADDS_32:
5435 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5436 break;
5437 case OPC2_32_RCR_MADDS_64:
5438 CHECK_REG_PAIR(r4);
5439 CHECK_REG_PAIR(r3);
5440 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5441 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5442 break;
5443 case OPC2_32_RCR_MADD_U_64:
5444 CHECK_REG_PAIR(r4);
5445 CHECK_REG_PAIR(r3);
5446 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5447 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5448 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5449 break;
5450 case OPC2_32_RCR_MADDS_U_32:
5451 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5452 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5453 break;
5454 case OPC2_32_RCR_MADDS_U_64:
5455 CHECK_REG_PAIR(r4);
5456 CHECK_REG_PAIR(r3);
5457 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5458 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5459 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5460 break;
5461 default:
5462 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5463 }
5464 }
5465
5466 static void decode_rcr_msub(DisasContext *ctx)
5467 {
5468 uint32_t op2;
5469 int r1, r3, r4;
5470 int32_t const9;
5471
5472
5473 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5474 r1 = MASK_OP_RCR_S1(ctx->opcode);
5475 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5476 r3 = MASK_OP_RCR_S3(ctx->opcode);
5477 r4 = MASK_OP_RCR_D(ctx->opcode);
5478
5479 switch (op2) {
5480 case OPC2_32_RCR_MSUB_32:
5481 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5482 break;
5483 case OPC2_32_RCR_MSUB_64:
5484 CHECK_REG_PAIR(r4);
5485 CHECK_REG_PAIR(r3);
5486 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5487 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5488 break;
5489 case OPC2_32_RCR_MSUBS_32:
5490 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5491 break;
5492 case OPC2_32_RCR_MSUBS_64:
5493 CHECK_REG_PAIR(r4);
5494 CHECK_REG_PAIR(r3);
5495 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5496 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5497 break;
5498 case OPC2_32_RCR_MSUB_U_64:
5499 CHECK_REG_PAIR(r4);
5500 CHECK_REG_PAIR(r3);
5501 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5502 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5503 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5504 break;
5505 case OPC2_32_RCR_MSUBS_U_32:
5506 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5507 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5508 break;
5509 case OPC2_32_RCR_MSUBS_U_64:
5510 CHECK_REG_PAIR(r4);
5511 CHECK_REG_PAIR(r3);
5512 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5513 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5514 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5515 break;
5516 default:
5517 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5518 }
5519 }
5520
5521 /* RLC format */
5522
5523 static void decode_rlc_opc(DisasContext *ctx,
5524 uint32_t op1)
5525 {
5526 int32_t const16;
5527 int r1, r2;
5528
5529 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
5530 r1 = MASK_OP_RLC_S1(ctx->opcode);
5531 r2 = MASK_OP_RLC_D(ctx->opcode);
5532
5533 switch (op1) {
5534 case OPC1_32_RLC_ADDI:
5535 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
5536 break;
5537 case OPC1_32_RLC_ADDIH:
5538 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
5539 break;
5540 case OPC1_32_RLC_ADDIH_A:
5541 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
5542 break;
5543 case OPC1_32_RLC_MFCR:
5544 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5545 gen_mfcr(ctx, cpu_gpr_d[r2], const16);
5546 break;
5547 case OPC1_32_RLC_MOV:
5548 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5549 break;
5550 case OPC1_32_RLC_MOV_64:
5551 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5552 CHECK_REG_PAIR(r2);
5553 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5554 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
5555 } else {
5556 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5557 }
5558 break;
5559 case OPC1_32_RLC_MOV_U:
5560 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5561 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5562 break;
5563 case OPC1_32_RLC_MOV_H:
5564 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
5565 break;
5566 case OPC1_32_RLC_MOVH_A:
5567 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
5568 break;
5569 case OPC1_32_RLC_MTCR:
5570 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5571 gen_mtcr(ctx, cpu_gpr_d[r1], const16);
5572 break;
5573 default:
5574 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5575 }
5576 }
5577
5578 /* RR format */
5579 static void decode_rr_accumulator(DisasContext *ctx)
5580 {
5581 uint32_t op2;
5582 int r3, r2, r1;
5583
5584 TCGv temp;
5585
5586 r3 = MASK_OP_RR_D(ctx->opcode);
5587 r2 = MASK_OP_RR_S2(ctx->opcode);
5588 r1 = MASK_OP_RR_S1(ctx->opcode);
5589 op2 = MASK_OP_RR_OP2(ctx->opcode);
5590
5591 switch (op2) {
5592 case OPC2_32_RR_ABS:
5593 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5594 break;
5595 case OPC2_32_RR_ABS_B:
5596 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5597 break;
5598 case OPC2_32_RR_ABS_H:
5599 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5600 break;
5601 case OPC2_32_RR_ABSDIF:
5602 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5603 break;
5604 case OPC2_32_RR_ABSDIF_B:
5605 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5606 cpu_gpr_d[r2]);
5607 break;
5608 case OPC2_32_RR_ABSDIF_H:
5609 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5610 cpu_gpr_d[r2]);
5611 break;
5612 case OPC2_32_RR_ABSDIFS:
5613 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5614 cpu_gpr_d[r2]);
5615 break;
5616 case OPC2_32_RR_ABSDIFS_H:
5617 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5618 cpu_gpr_d[r2]);
5619 break;
5620 case OPC2_32_RR_ABSS:
5621 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5622 break;
5623 case OPC2_32_RR_ABSS_H:
5624 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5625 break;
5626 case OPC2_32_RR_ADD:
5627 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5628 break;
5629 case OPC2_32_RR_ADD_B:
5630 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5631 break;
5632 case OPC2_32_RR_ADD_H:
5633 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5634 break;
5635 case OPC2_32_RR_ADDC:
5636 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5637 break;
5638 case OPC2_32_RR_ADDS:
5639 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5640 break;
5641 case OPC2_32_RR_ADDS_H:
5642 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5643 cpu_gpr_d[r2]);
5644 break;
5645 case OPC2_32_RR_ADDS_HU:
5646 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5647 cpu_gpr_d[r2]);
5648 break;
5649 case OPC2_32_RR_ADDS_U:
5650 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5651 cpu_gpr_d[r2]);
5652 break;
5653 case OPC2_32_RR_ADDX:
5654 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5655 break;
5656 case OPC2_32_RR_AND_EQ:
5657 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5658 cpu_gpr_d[r2], &tcg_gen_and_tl);
5659 break;
5660 case OPC2_32_RR_AND_GE:
5661 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5662 cpu_gpr_d[r2], &tcg_gen_and_tl);
5663 break;
5664 case OPC2_32_RR_AND_GE_U:
5665 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5666 cpu_gpr_d[r2], &tcg_gen_and_tl);
5667 break;
5668 case OPC2_32_RR_AND_LT:
5669 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5670 cpu_gpr_d[r2], &tcg_gen_and_tl);
5671 break;
5672 case OPC2_32_RR_AND_LT_U:
5673 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5674 cpu_gpr_d[r2], &tcg_gen_and_tl);
5675 break;
5676 case OPC2_32_RR_AND_NE:
5677 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5678 cpu_gpr_d[r2], &tcg_gen_and_tl);
5679 break;
5680 case OPC2_32_RR_EQ:
5681 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5682 cpu_gpr_d[r2]);
5683 break;
5684 case OPC2_32_RR_EQ_B:
5685 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5686 break;
5687 case OPC2_32_RR_EQ_H:
5688 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5689 break;
5690 case OPC2_32_RR_EQ_W:
5691 tcg_gen_negsetcond_tl(TCG_COND_EQ, cpu_gpr_d[r3],
5692 cpu_gpr_d[r1], cpu_gpr_d[r2]);
5693 break;
5694 case OPC2_32_RR_EQANY_B:
5695 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5696 break;
5697 case OPC2_32_RR_EQANY_H:
5698 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5699 break;
5700 case OPC2_32_RR_GE:
5701 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5702 cpu_gpr_d[r2]);
5703 break;
5704 case OPC2_32_RR_GE_U:
5705 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5706 cpu_gpr_d[r2]);
5707 break;
5708 case OPC2_32_RR_LT:
5709 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5710 cpu_gpr_d[r2]);
5711 break;
5712 case OPC2_32_RR_LT_U:
5713 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5714 cpu_gpr_d[r2]);
5715 break;
5716 case OPC2_32_RR_LT_B:
5717 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5718 break;
5719 case OPC2_32_RR_LT_BU:
5720 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5721 break;
5722 case OPC2_32_RR_LT_H:
5723 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5724 break;
5725 case OPC2_32_RR_LT_HU:
5726 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5727 break;
5728 case OPC2_32_RR_LT_W:
5729 tcg_gen_negsetcond_tl(TCG_COND_LT, cpu_gpr_d[r3],
5730 cpu_gpr_d[r1], cpu_gpr_d[r2]);
5731 break;
5732 case OPC2_32_RR_LT_WU:
5733 tcg_gen_negsetcond_tl(TCG_COND_LTU, cpu_gpr_d[r3],
5734 cpu_gpr_d[r1], cpu_gpr_d[r2]);
5735 break;
5736 case OPC2_32_RR_MAX:
5737 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5738 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5739 break;
5740 case OPC2_32_RR_MAX_U:
5741 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5742 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5743 break;
5744 case OPC2_32_RR_MAX_B:
5745 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5746 break;
5747 case OPC2_32_RR_MAX_BU:
5748 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5749 break;
5750 case OPC2_32_RR_MAX_H:
5751 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5752 break;
5753 case OPC2_32_RR_MAX_HU:
5754 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5755 break;
5756 case OPC2_32_RR_MIN:
5757 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5758 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5759 break;
5760 case OPC2_32_RR_MIN_U:
5761 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5762 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5763 break;
5764 case OPC2_32_RR_MIN_B:
5765 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5766 break;
5767 case OPC2_32_RR_MIN_BU:
5768 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5769 break;
5770 case OPC2_32_RR_MIN_H:
5771 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5772 break;
5773 case OPC2_32_RR_MIN_HU:
5774 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5775 break;
5776 case OPC2_32_RR_MOV:
5777 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5778 break;
5779 case OPC2_32_RR_MOV_64:
5780 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5781 temp = tcg_temp_new();
5782
5783 CHECK_REG_PAIR(r3);
5784 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
5785 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5786 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
5787 } else {
5788 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5789 }
5790 break;
5791 case OPC2_32_RR_MOVS_64:
5792 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5793 CHECK_REG_PAIR(r3);
5794 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5795 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
5796 } else {
5797 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5798 }
5799 break;
5800 case OPC2_32_RR_NE:
5801 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5802 cpu_gpr_d[r2]);
5803 break;
5804 case OPC2_32_RR_OR_EQ:
5805 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5806 cpu_gpr_d[r2], &tcg_gen_or_tl);
5807 break;
5808 case OPC2_32_RR_OR_GE:
5809 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5810 cpu_gpr_d[r2], &tcg_gen_or_tl);
5811 break;
5812 case OPC2_32_RR_OR_GE_U:
5813 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5814 cpu_gpr_d[r2], &tcg_gen_or_tl);
5815 break;
5816 case OPC2_32_RR_OR_LT:
5817 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5818 cpu_gpr_d[r2], &tcg_gen_or_tl);
5819 break;
5820 case OPC2_32_RR_OR_LT_U:
5821 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5822 cpu_gpr_d[r2], &tcg_gen_or_tl);
5823 break;
5824 case OPC2_32_RR_OR_NE:
5825 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5826 cpu_gpr_d[r2], &tcg_gen_or_tl);
5827 break;
5828 case OPC2_32_RR_SAT_B:
5829 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
5830 break;
5831 case OPC2_32_RR_SAT_BU:
5832 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
5833 break;
5834 case OPC2_32_RR_SAT_H:
5835 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
5836 break;
5837 case OPC2_32_RR_SAT_HU:
5838 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
5839 break;
5840 case OPC2_32_RR_SH_EQ:
5841 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5842 cpu_gpr_d[r2]);
5843 break;
5844 case OPC2_32_RR_SH_GE:
5845 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5846 cpu_gpr_d[r2]);
5847 break;
5848 case OPC2_32_RR_SH_GE_U:
5849 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5850 cpu_gpr_d[r2]);
5851 break;
5852 case OPC2_32_RR_SH_LT:
5853 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5854 cpu_gpr_d[r2]);
5855 break;
5856 case OPC2_32_RR_SH_LT_U:
5857 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5858 cpu_gpr_d[r2]);
5859 break;
5860 case OPC2_32_RR_SH_NE:
5861 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5862 cpu_gpr_d[r2]);
5863 break;
5864 case OPC2_32_RR_SUB:
5865 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5866 break;
5867 case OPC2_32_RR_SUB_B:
5868 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5869 break;
5870 case OPC2_32_RR_SUB_H:
5871 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5872 break;
5873 case OPC2_32_RR_SUBC:
5874 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5875 break;
5876 case OPC2_32_RR_SUBS:
5877 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5878 break;
5879 case OPC2_32_RR_SUBS_U:
5880 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5881 break;
5882 case OPC2_32_RR_SUBS_H:
5883 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5884 cpu_gpr_d[r2]);
5885 break;
5886 case OPC2_32_RR_SUBS_HU:
5887 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5888 cpu_gpr_d[r2]);
5889 break;
5890 case OPC2_32_RR_SUBX:
5891 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5892 break;
5893 case OPC2_32_RR_XOR_EQ:
5894 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5895 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5896 break;
5897 case OPC2_32_RR_XOR_GE:
5898 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5899 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5900 break;
5901 case OPC2_32_RR_XOR_GE_U:
5902 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5903 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5904 break;
5905 case OPC2_32_RR_XOR_LT:
5906 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5907 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5908 break;
5909 case OPC2_32_RR_XOR_LT_U:
5910 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5911 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5912 break;
5913 case OPC2_32_RR_XOR_NE:
5914 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5915 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5916 break;
5917 default:
5918 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5919 }
5920 }
5921
5922 static void decode_rr_logical_shift(DisasContext *ctx)
5923 {
5924 uint32_t op2;
5925 int r3, r2, r1;
5926
5927 r3 = MASK_OP_RR_D(ctx->opcode);
5928 r2 = MASK_OP_RR_S2(ctx->opcode);
5929 r1 = MASK_OP_RR_S1(ctx->opcode);
5930 op2 = MASK_OP_RR_OP2(ctx->opcode);
5931
5932 switch (op2) {
5933 case OPC2_32_RR_AND:
5934 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5935 break;
5936 case OPC2_32_RR_ANDN:
5937 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5938 break;
5939 case OPC2_32_RR_CLO:
5940 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5941 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
5942 break;
5943 case OPC2_32_RR_CLO_H:
5944 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5945 break;
5946 case OPC2_32_RR_CLS:
5947 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5948 break;
5949 case OPC2_32_RR_CLS_H:
5950 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5951 break;
5952 case OPC2_32_RR_CLZ:
5953 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
5954 break;
5955 case OPC2_32_RR_CLZ_H:
5956 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5957 break;
5958 case OPC2_32_RR_NAND:
5959 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5960 break;
5961 case OPC2_32_RR_NOR:
5962 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5963 break;
5964 case OPC2_32_RR_OR:
5965 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5966 break;
5967 case OPC2_32_RR_ORN:
5968 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5969 break;
5970 case OPC2_32_RR_SH:
5971 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5972 break;
5973 case OPC2_32_RR_SH_H:
5974 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5975 break;
5976 case OPC2_32_RR_SHA:
5977 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5978 break;
5979 case OPC2_32_RR_SHA_H:
5980 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5981 break;
5982 case OPC2_32_RR_SHAS:
5983 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5984 break;
5985 case OPC2_32_RR_XNOR:
5986 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5987 break;
5988 case OPC2_32_RR_XOR:
5989 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5990 break;
5991 default:
5992 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5993 }
5994 }
5995
5996 static void decode_rr_address(DisasContext *ctx)
5997 {
5998 uint32_t op2, n;
5999 int r1, r2, r3;
6000 TCGv temp;
6001
6002 op2 = MASK_OP_RR_OP2(ctx->opcode);
6003 r3 = MASK_OP_RR_D(ctx->opcode);
6004 r2 = MASK_OP_RR_S2(ctx->opcode);
6005 r1 = MASK_OP_RR_S1(ctx->opcode);
6006 n = MASK_OP_RR_N(ctx->opcode);
6007
6008 switch (op2) {
6009 case OPC2_32_RR_ADD_A:
6010 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6011 break;
6012 case OPC2_32_RR_ADDSC_A:
6013 temp = tcg_temp_new();
6014 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
6015 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
6016 break;
6017 case OPC2_32_RR_ADDSC_AT:
6018 temp = tcg_temp_new();
6019 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
6020 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
6021 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
6022 break;
6023 case OPC2_32_RR_EQ_A:
6024 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
6025 cpu_gpr_a[r2]);
6026 break;
6027 case OPC2_32_RR_EQZ:
6028 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6029 break;
6030 case OPC2_32_RR_GE_A:
6031 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6032 cpu_gpr_a[r2]);
6033 break;
6034 case OPC2_32_RR_LT_A:
6035 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6036 cpu_gpr_a[r2]);
6037 break;
6038 case OPC2_32_RR_MOV_A:
6039 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
6040 break;
6041 case OPC2_32_RR_MOV_AA:
6042 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
6043 break;
6044 case OPC2_32_RR_MOV_D:
6045 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
6046 break;
6047 case OPC2_32_RR_NE_A:
6048 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
6049 cpu_gpr_a[r2]);
6050 break;
6051 case OPC2_32_RR_NEZ_A:
6052 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6053 break;
6054 case OPC2_32_RR_SUB_A:
6055 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6056 break;
6057 default:
6058 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6059 }
6060 }
6061
6062 static void decode_rr_idirect(DisasContext *ctx)
6063 {
6064 uint32_t op2;
6065 int r1;
6066
6067 op2 = MASK_OP_RR_OP2(ctx->opcode);
6068 r1 = MASK_OP_RR_S1(ctx->opcode);
6069
6070 switch (op2) {
6071 case OPC2_32_RR_JI:
6072 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6073 break;
6074 case OPC2_32_RR_JLI:
6075 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6076 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
6077 break;
6078 case OPC2_32_RR_CALLI:
6079 gen_helper_1arg(call, ctx->pc_succ_insn);
6080 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6081 break;
6082 case OPC2_32_RR_FCALLI:
6083 gen_fcall_save_ctx(ctx);
6084 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6085 break;
6086 default:
6087 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6088 return;
6089 }
6090 ctx->base.is_jmp = DISAS_JUMP;
6091 }
6092
6093 static void decode_rr_divide(DisasContext *ctx)
6094 {
6095 uint32_t op2;
6096 int r1, r2, r3;
6097
6098 TCGv temp, temp2, temp3;
6099
6100 op2 = MASK_OP_RR_OP2(ctx->opcode);
6101 r3 = MASK_OP_RR_D(ctx->opcode);
6102 r2 = MASK_OP_RR_S2(ctx->opcode);
6103 r1 = MASK_OP_RR_S1(ctx->opcode);
6104
6105 switch (op2) {
6106 case OPC2_32_RR_BMERGE:
6107 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6108 break;
6109 case OPC2_32_RR_BSPLIT:
6110 CHECK_REG_PAIR(r3);
6111 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6112 break;
6113 case OPC2_32_RR_DVINIT_B:
6114 CHECK_REG_PAIR(r3);
6115 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6116 cpu_gpr_d[r2]);
6117 break;
6118 case OPC2_32_RR_DVINIT_BU:
6119 temp = tcg_temp_new();
6120 temp2 = tcg_temp_new();
6121 temp3 = tcg_temp_new();
6122 CHECK_REG_PAIR(r3);
6123 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
6124 /* reset av */
6125 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6126 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
6127 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6128 tcg_gen_abs_tl(temp, temp3);
6129 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
6130 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6131 } else {
6132 /* overflow = (D[b] == 0) */
6133 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6134 }
6135 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6136 /* sv */
6137 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6138 /* write result */
6139 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
6140 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6141 break;
6142 case OPC2_32_RR_DVINIT_H:
6143 CHECK_REG_PAIR(r3);
6144 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6145 cpu_gpr_d[r2]);
6146 break;
6147 case OPC2_32_RR_DVINIT_HU:
6148 temp = tcg_temp_new();
6149 temp2 = tcg_temp_new();
6150 temp3 = tcg_temp_new();
6151 CHECK_REG_PAIR(r3);
6152 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
6153 /* reset av */
6154 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6155 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
6156 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6157 tcg_gen_abs_tl(temp, temp3);
6158 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
6159 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6160 } else {
6161 /* overflow = (D[b] == 0) */
6162 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6163 }
6164 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6165 /* sv */
6166 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6167 /* write result */
6168 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
6169 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6170 break;
6171 case OPC2_32_RR_DVINIT:
6172 temp = tcg_temp_new();
6173 temp2 = tcg_temp_new();
6174 CHECK_REG_PAIR(r3);
6175 /* overflow = ((D[b] == 0) ||
6176 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6177 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
6178 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
6179 tcg_gen_and_tl(temp, temp, temp2);
6180 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
6181 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
6182 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6183 /* sv */
6184 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6185 /* reset av */
6186 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6187 /* write result */
6188 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6189 /* sign extend to high reg */
6190 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
6191 break;
6192 case OPC2_32_RR_DVINIT_U:
6193 CHECK_REG_PAIR(r3);
6194 /* overflow = (D[b] == 0) */
6195 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6196 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6197 /* sv */
6198 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6199 /* reset av */
6200 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6201 /* write result */
6202 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6203 /* zero extend to high reg*/
6204 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
6205 break;
6206 case OPC2_32_RR_PARITY:
6207 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6208 break;
6209 case OPC2_32_RR_UNPACK:
6210 CHECK_REG_PAIR(r3);
6211 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6212 break;
6213 case OPC2_32_RR_CRC32_B:
6214 if (has_feature(ctx, TRICORE_FEATURE_162)) {
6215 gen_helper_crc32b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6216 } else {
6217 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6218 }
6219 break;
6220 case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */
6221 if (has_feature(ctx, TRICORE_FEATURE_161)) {
6222 gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6223 } else {
6224 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6225 }
6226 break;
6227 case OPC2_32_RR_CRC32L_W:
6228 if (has_feature(ctx, TRICORE_FEATURE_162)) {
6229 gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6230 } else {
6231 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6232 }
6233 break;
6234
6235 case OPC2_32_RR_POPCNT_W:
6236 if (has_feature(ctx, TRICORE_FEATURE_162)) {
6237 tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6238 } else {
6239 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6240 }
6241 break;
6242 case OPC2_32_RR_DIV:
6243 if (has_feature(ctx, TRICORE_FEATURE_16)) {
6244 CHECK_REG_PAIR(r3);
6245 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6246 cpu_gpr_d[r2]);
6247 } else {
6248 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6249 }
6250 break;
6251 case OPC2_32_RR_DIV_U:
6252 if (has_feature(ctx, TRICORE_FEATURE_16)) {
6253 CHECK_REG_PAIR(r3);
6254 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6255 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6256 } else {
6257 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6258 }
6259 break;
6260 case OPC2_32_RR_MUL_F:
6261 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6262 break;
6263 case OPC2_32_RR_DIV_F:
6264 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6265 break;
6266 case OPC2_32_RR_FTOHP:
6267 if (has_feature(ctx, TRICORE_FEATURE_162)) {
6268 gen_helper_ftohp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6269 } else {
6270 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6271 }
6272 break;
6273 case OPC2_32_RR_HPTOF:
6274 if (has_feature(ctx, TRICORE_FEATURE_162)) {
6275 gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6276 } else {
6277 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6278 }
6279 break;
6280 case OPC2_32_RR_CMP_F:
6281 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6282 break;
6283 case OPC2_32_RR_FTOI:
6284 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6285 break;
6286 case OPC2_32_RR_ITOF:
6287 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6288 break;
6289 case OPC2_32_RR_FTOU:
6290 gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6291 break;
6292 case OPC2_32_RR_FTOUZ:
6293 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6294 break;
6295 case OPC2_32_RR_UPDFL:
6296 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
6297 break;
6298 case OPC2_32_RR_UTOF:
6299 gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6300 break;
6301 case OPC2_32_RR_FTOIZ:
6302 gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6303 break;
6304 case OPC2_32_RR_QSEED_F:
6305 gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6306 break;
6307 default:
6308 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6309 }
6310 }
6311
6312 /* RR1 Format */
6313 static void decode_rr1_mul(DisasContext *ctx)
6314 {
6315 uint32_t op2;
6316
6317 int r1, r2, r3;
6318 TCGv n;
6319 TCGv_i64 temp64;
6320
6321 r1 = MASK_OP_RR1_S1(ctx->opcode);
6322 r2 = MASK_OP_RR1_S2(ctx->opcode);
6323 r3 = MASK_OP_RR1_D(ctx->opcode);
6324 n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode));
6325 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6326
6327 switch (op2) {
6328 case OPC2_32_RR1_MUL_H_32_LL:
6329 temp64 = tcg_temp_new_i64();
6330 CHECK_REG_PAIR(r3);
6331 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6332 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6333 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6334 break;
6335 case OPC2_32_RR1_MUL_H_32_LU:
6336 temp64 = tcg_temp_new_i64();
6337 CHECK_REG_PAIR(r3);
6338 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6339 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6340 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6341 break;
6342 case OPC2_32_RR1_MUL_H_32_UL:
6343 temp64 = tcg_temp_new_i64();
6344 CHECK_REG_PAIR(r3);
6345 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6346 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6347 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6348 break;
6349 case OPC2_32_RR1_MUL_H_32_UU:
6350 temp64 = tcg_temp_new_i64();
6351 CHECK_REG_PAIR(r3);
6352 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6353 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6354 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6355 break;
6356 case OPC2_32_RR1_MULM_H_64_LL:
6357 temp64 = tcg_temp_new_i64();
6358 CHECK_REG_PAIR(r3);
6359 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6360 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6361 /* reset V bit */
6362 tcg_gen_movi_tl(cpu_PSW_V, 0);
6363 /* reset AV bit */
6364 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6365 break;
6366 case OPC2_32_RR1_MULM_H_64_LU:
6367 temp64 = tcg_temp_new_i64();
6368 CHECK_REG_PAIR(r3);
6369 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6370 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6371 /* reset V bit */
6372 tcg_gen_movi_tl(cpu_PSW_V, 0);
6373 /* reset AV bit */
6374 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6375 break;
6376 case OPC2_32_RR1_MULM_H_64_UL:
6377 temp64 = tcg_temp_new_i64();
6378 CHECK_REG_PAIR(r3);
6379 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6380 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6381 /* reset V bit */
6382 tcg_gen_movi_tl(cpu_PSW_V, 0);
6383 /* reset AV bit */
6384 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6385 break;
6386 case OPC2_32_RR1_MULM_H_64_UU:
6387 temp64 = tcg_temp_new_i64();
6388 CHECK_REG_PAIR(r3);
6389 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6390 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6391 /* reset V bit */
6392 tcg_gen_movi_tl(cpu_PSW_V, 0);
6393 /* reset AV bit */
6394 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6395 break;
6396 case OPC2_32_RR1_MULR_H_16_LL:
6397 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6398 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6399 break;
6400 case OPC2_32_RR1_MULR_H_16_LU:
6401 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6402 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6403 break;
6404 case OPC2_32_RR1_MULR_H_16_UL:
6405 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6406 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6407 break;
6408 case OPC2_32_RR1_MULR_H_16_UU:
6409 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6410 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6411 break;
6412 default:
6413 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6414 }
6415 }
6416
6417 static void decode_rr1_mulq(DisasContext *ctx)
6418 {
6419 uint32_t op2;
6420 int r1, r2, r3;
6421 uint32_t n;
6422
6423 TCGv temp, temp2;
6424
6425 r1 = MASK_OP_RR1_S1(ctx->opcode);
6426 r2 = MASK_OP_RR1_S2(ctx->opcode);
6427 r3 = MASK_OP_RR1_D(ctx->opcode);
6428 n = MASK_OP_RR1_N(ctx->opcode);
6429 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6430
6431 temp = tcg_temp_new();
6432 temp2 = tcg_temp_new();
6433
6434 switch (op2) {
6435 case OPC2_32_RR1_MUL_Q_32:
6436 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
6437 break;
6438 case OPC2_32_RR1_MUL_Q_64:
6439 CHECK_REG_PAIR(r3);
6440 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6441 n, 0);
6442 break;
6443 case OPC2_32_RR1_MUL_Q_32_L:
6444 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6445 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6446 break;
6447 case OPC2_32_RR1_MUL_Q_64_L:
6448 CHECK_REG_PAIR(r3);
6449 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6450 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6451 break;
6452 case OPC2_32_RR1_MUL_Q_32_U:
6453 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6454 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6455 break;
6456 case OPC2_32_RR1_MUL_Q_64_U:
6457 CHECK_REG_PAIR(r3);
6458 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6459 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6460 break;
6461 case OPC2_32_RR1_MUL_Q_32_LL:
6462 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6463 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6464 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6465 break;
6466 case OPC2_32_RR1_MUL_Q_32_UU:
6467 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6468 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6469 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6470 break;
6471 case OPC2_32_RR1_MULR_Q_32_L:
6472 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6473 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6474 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6475 break;
6476 case OPC2_32_RR1_MULR_Q_32_U:
6477 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6478 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6479 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6480 break;
6481 default:
6482 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6483 }
6484 }
6485
6486 /* RR2 format */
6487 static void decode_rr2_mul(DisasContext *ctx)
6488 {
6489 uint32_t op2;
6490 int r1, r2, r3;
6491
6492 op2 = MASK_OP_RR2_OP2(ctx->opcode);
6493 r1 = MASK_OP_RR2_S1(ctx->opcode);
6494 r2 = MASK_OP_RR2_S2(ctx->opcode);
6495 r3 = MASK_OP_RR2_D(ctx->opcode);
6496 switch (op2) {
6497 case OPC2_32_RR2_MUL_32:
6498 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6499 break;
6500 case OPC2_32_RR2_MUL_64:
6501 CHECK_REG_PAIR(r3);
6502 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6503 cpu_gpr_d[r2]);
6504 break;
6505 case OPC2_32_RR2_MULS_32:
6506 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6507 cpu_gpr_d[r2]);
6508 break;
6509 case OPC2_32_RR2_MUL_U_64:
6510 CHECK_REG_PAIR(r3);
6511 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6512 cpu_gpr_d[r2]);
6513 break;
6514 case OPC2_32_RR2_MULS_U_32:
6515 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6516 cpu_gpr_d[r2]);
6517 break;
6518 default:
6519 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6520 }
6521 }
6522
6523 /* RRPW format */
6524 static void decode_rrpw_extract_insert(DisasContext *ctx)
6525 {
6526 uint32_t op2;
6527 int r1, r2, r3;
6528 int32_t pos, width;
6529 TCGv temp;
6530
6531 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
6532 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6533 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6534 r3 = MASK_OP_RRPW_D(ctx->opcode);
6535 pos = MASK_OP_RRPW_POS(ctx->opcode);
6536 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
6537
6538 switch (op2) {
6539 case OPC2_32_RRPW_EXTR:
6540 if (width == 0) {
6541 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6542 break;
6543 }
6544
6545 if (pos + width <= 32) {
6546 /* optimize special cases */
6547 if ((pos == 0) && (width == 8)) {
6548 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6549 } else if ((pos == 0) && (width == 16)) {
6550 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6551 } else {
6552 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
6553 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
6554 }
6555 }
6556 break;
6557 case OPC2_32_RRPW_EXTR_U:
6558 if (width == 0) {
6559 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6560 } else {
6561 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
6562 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
6563 }
6564 break;
6565 case OPC2_32_RRPW_IMASK:
6566 CHECK_REG_PAIR(r3);
6567
6568 if (pos + width <= 32) {
6569 temp = tcg_temp_new();
6570 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos);
6571 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
6572 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
6573 }
6574
6575 break;
6576 case OPC2_32_RRPW_INSERT:
6577 /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
6578 if (width == 0) {
6579 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6580 } else if (pos + width <= 32) {
6581 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
6582 pos, width);
6583 }
6584 break;
6585 default:
6586 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6587 }
6588 }
6589
6590 /* RRR format */
6591 static void decode_rrr_cond_select(DisasContext *ctx)
6592 {
6593 uint32_t op2;
6594 int r1, r2, r3, r4;
6595 TCGv temp;
6596
6597 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6598 r1 = MASK_OP_RRR_S1(ctx->opcode);
6599 r2 = MASK_OP_RRR_S2(ctx->opcode);
6600 r3 = MASK_OP_RRR_S3(ctx->opcode);
6601 r4 = MASK_OP_RRR_D(ctx->opcode);
6602
6603 switch (op2) {
6604 case OPC2_32_RRR_CADD:
6605 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
6606 cpu_gpr_d[r4], cpu_gpr_d[r3]);
6607 break;
6608 case OPC2_32_RRR_CADDN:
6609 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6610 cpu_gpr_d[r3]);
6611 break;
6612 case OPC2_32_RRR_CSUB:
6613 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6614 cpu_gpr_d[r3]);
6615 break;
6616 case OPC2_32_RRR_CSUBN:
6617 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6618 cpu_gpr_d[r3]);
6619 break;
6620 case OPC2_32_RRR_SEL:
6621 temp = tcg_constant_i32(0);
6622 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6623 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6624 break;
6625 case OPC2_32_RRR_SELN:
6626 temp = tcg_constant_i32(0);
6627 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6628 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6629 break;
6630 default:
6631 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6632 }
6633 }
6634
6635 static void decode_rrr_divide(DisasContext *ctx)
6636 {
6637 uint32_t op2;
6638
6639 int r1, r2, r3, r4;
6640
6641 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6642 r1 = MASK_OP_RRR_S1(ctx->opcode);
6643 r2 = MASK_OP_RRR_S2(ctx->opcode);
6644 r3 = MASK_OP_RRR_S3(ctx->opcode);
6645 r4 = MASK_OP_RRR_D(ctx->opcode);
6646
6647 switch (op2) {
6648 case OPC2_32_RRR_DVADJ:
6649 CHECK_REG_PAIR(r3);
6650 CHECK_REG_PAIR(r4);
6651 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6652 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6653 break;
6654 case OPC2_32_RRR_DVSTEP:
6655 CHECK_REG_PAIR(r3);
6656 CHECK_REG_PAIR(r4);
6657 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6658 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6659 break;
6660 case OPC2_32_RRR_DVSTEP_U:
6661 CHECK_REG_PAIR(r3);
6662 CHECK_REG_PAIR(r4);
6663 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6664 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6665 break;
6666 case OPC2_32_RRR_IXMAX:
6667 CHECK_REG_PAIR(r3);
6668 CHECK_REG_PAIR(r4);
6669 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6670 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6671 break;
6672 case OPC2_32_RRR_IXMAX_U:
6673 CHECK_REG_PAIR(r3);
6674 CHECK_REG_PAIR(r4);
6675 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6676 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6677 break;
6678 case OPC2_32_RRR_IXMIN:
6679 CHECK_REG_PAIR(r3);
6680 CHECK_REG_PAIR(r4);
6681 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6682 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6683 break;
6684 case OPC2_32_RRR_IXMIN_U:
6685 CHECK_REG_PAIR(r3);
6686 CHECK_REG_PAIR(r4);
6687 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6688 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6689 break;
6690 case OPC2_32_RRR_PACK:
6691 CHECK_REG_PAIR(r3);
6692 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
6693 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6694 break;
6695 case OPC2_32_RRR_CRCN:
6696 if (has_feature(ctx, TRICORE_FEATURE_162)) {
6697 gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2],
6698 cpu_gpr_d[r3]);
6699 } else {
6700 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6701 }
6702 break;
6703 case OPC2_32_RRR_ADD_F:
6704 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
6705 break;
6706 case OPC2_32_RRR_SUB_F:
6707 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
6708 break;
6709 case OPC2_32_RRR_MADD_F:
6710 gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6711 cpu_gpr_d[r2], cpu_gpr_d[r3]);
6712 break;
6713 case OPC2_32_RRR_MSUB_F:
6714 gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6715 cpu_gpr_d[r2], cpu_gpr_d[r3]);
6716 break;
6717 default:
6718 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6719 }
6720 }
6721
6722 /* RRR2 format */
6723 static void decode_rrr2_madd(DisasContext *ctx)
6724 {
6725 uint32_t op2;
6726 uint32_t r1, r2, r3, r4;
6727
6728 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6729 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6730 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6731 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6732 r4 = MASK_OP_RRR2_D(ctx->opcode);
6733 switch (op2) {
6734 case OPC2_32_RRR2_MADD_32:
6735 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6736 cpu_gpr_d[r2]);
6737 break;
6738 case OPC2_32_RRR2_MADD_64:
6739 CHECK_REG_PAIR(r4);
6740 CHECK_REG_PAIR(r3);
6741 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6742 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6743 break;
6744 case OPC2_32_RRR2_MADDS_32:
6745 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6746 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6747 break;
6748 case OPC2_32_RRR2_MADDS_64:
6749 CHECK_REG_PAIR(r4);
6750 CHECK_REG_PAIR(r3);
6751 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6752 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6753 break;
6754 case OPC2_32_RRR2_MADD_U_64:
6755 CHECK_REG_PAIR(r4);
6756 CHECK_REG_PAIR(r3);
6757 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6758 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6759 break;
6760 case OPC2_32_RRR2_MADDS_U_32:
6761 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6762 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6763 break;
6764 case OPC2_32_RRR2_MADDS_U_64:
6765 CHECK_REG_PAIR(r4);
6766 CHECK_REG_PAIR(r3);
6767 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6768 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6769 break;
6770 default:
6771 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6772 }
6773 }
6774
6775 static void decode_rrr2_msub(DisasContext *ctx)
6776 {
6777 uint32_t op2;
6778 uint32_t r1, r2, r3, r4;
6779
6780 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6781 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6782 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6783 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6784 r4 = MASK_OP_RRR2_D(ctx->opcode);
6785
6786 switch (op2) {
6787 case OPC2_32_RRR2_MSUB_32:
6788 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6789 cpu_gpr_d[r2]);
6790 break;
6791 case OPC2_32_RRR2_MSUB_64:
6792 CHECK_REG_PAIR(r4);
6793 CHECK_REG_PAIR(r3);
6794 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6795 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6796 break;
6797 case OPC2_32_RRR2_MSUBS_32:
6798 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6799 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6800 break;
6801 case OPC2_32_RRR2_MSUBS_64:
6802 CHECK_REG_PAIR(r4);
6803 CHECK_REG_PAIR(r3);
6804 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6805 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6806 break;
6807 case OPC2_32_RRR2_MSUB_U_64:
6808 CHECK_REG_PAIR(r4);
6809 CHECK_REG_PAIR(r3);
6810 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6811 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6812 break;
6813 case OPC2_32_RRR2_MSUBS_U_32:
6814 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6815 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6816 break;
6817 case OPC2_32_RRR2_MSUBS_U_64:
6818 CHECK_REG_PAIR(r4);
6819 CHECK_REG_PAIR(r3);
6820 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6821 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6822 break;
6823 default:
6824 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6825 }
6826 }
6827
6828 /* RRR1 format */
6829 static void decode_rrr1_madd(DisasContext *ctx)
6830 {
6831 uint32_t op2;
6832 uint32_t r1, r2, r3, r4, n;
6833
6834 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6835 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6836 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6837 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6838 r4 = MASK_OP_RRR1_D(ctx->opcode);
6839 n = MASK_OP_RRR1_N(ctx->opcode);
6840
6841 switch (op2) {
6842 case OPC2_32_RRR1_MADD_H_LL:
6843 CHECK_REG_PAIR(r4);
6844 CHECK_REG_PAIR(r3);
6845 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6846 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6847 break;
6848 case OPC2_32_RRR1_MADD_H_LU:
6849 CHECK_REG_PAIR(r4);
6850 CHECK_REG_PAIR(r3);
6851 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6852 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6853 break;
6854 case OPC2_32_RRR1_MADD_H_UL:
6855 CHECK_REG_PAIR(r4);
6856 CHECK_REG_PAIR(r3);
6857 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6858 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6859 break;
6860 case OPC2_32_RRR1_MADD_H_UU:
6861 CHECK_REG_PAIR(r4);
6862 CHECK_REG_PAIR(r3);
6863 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6864 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6865 break;
6866 case OPC2_32_RRR1_MADDS_H_LL:
6867 CHECK_REG_PAIR(r4);
6868 CHECK_REG_PAIR(r3);
6869 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6870 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6871 break;
6872 case OPC2_32_RRR1_MADDS_H_LU:
6873 CHECK_REG_PAIR(r4);
6874 CHECK_REG_PAIR(r3);
6875 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6876 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6877 break;
6878 case OPC2_32_RRR1_MADDS_H_UL:
6879 CHECK_REG_PAIR(r4);
6880 CHECK_REG_PAIR(r3);
6881 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6882 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6883 break;
6884 case OPC2_32_RRR1_MADDS_H_UU:
6885 CHECK_REG_PAIR(r4);
6886 CHECK_REG_PAIR(r3);
6887 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6888 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6889 break;
6890 case OPC2_32_RRR1_MADDM_H_LL:
6891 CHECK_REG_PAIR(r4);
6892 CHECK_REG_PAIR(r3);
6893 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6894 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6895 break;
6896 case OPC2_32_RRR1_MADDM_H_LU:
6897 CHECK_REG_PAIR(r4);
6898 CHECK_REG_PAIR(r3);
6899 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6900 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6901 break;
6902 case OPC2_32_RRR1_MADDM_H_UL:
6903 CHECK_REG_PAIR(r4);
6904 CHECK_REG_PAIR(r3);
6905 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6906 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6907 break;
6908 case OPC2_32_RRR1_MADDM_H_UU:
6909 CHECK_REG_PAIR(r4);
6910 CHECK_REG_PAIR(r3);
6911 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6912 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6913 break;
6914 case OPC2_32_RRR1_MADDMS_H_LL:
6915 CHECK_REG_PAIR(r4);
6916 CHECK_REG_PAIR(r3);
6917 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6918 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6919 break;
6920 case OPC2_32_RRR1_MADDMS_H_LU:
6921 CHECK_REG_PAIR(r4);
6922 CHECK_REG_PAIR(r3);
6923 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6924 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6925 break;
6926 case OPC2_32_RRR1_MADDMS_H_UL:
6927 CHECK_REG_PAIR(r4);
6928 CHECK_REG_PAIR(r3);
6929 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6930 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6931 break;
6932 case OPC2_32_RRR1_MADDMS_H_UU:
6933 CHECK_REG_PAIR(r4);
6934 CHECK_REG_PAIR(r3);
6935 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6936 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6937 break;
6938 case OPC2_32_RRR1_MADDR_H_LL:
6939 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6940 cpu_gpr_d[r2], n, MODE_LL);
6941 break;
6942 case OPC2_32_RRR1_MADDR_H_LU:
6943 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6944 cpu_gpr_d[r2], n, MODE_LU);
6945 break;
6946 case OPC2_32_RRR1_MADDR_H_UL:
6947 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6948 cpu_gpr_d[r2], n, MODE_UL);
6949 break;
6950 case OPC2_32_RRR1_MADDR_H_UU:
6951 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6952 cpu_gpr_d[r2], n, MODE_UU);
6953 break;
6954 case OPC2_32_RRR1_MADDRS_H_LL:
6955 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6956 cpu_gpr_d[r2], n, MODE_LL);
6957 break;
6958 case OPC2_32_RRR1_MADDRS_H_LU:
6959 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6960 cpu_gpr_d[r2], n, MODE_LU);
6961 break;
6962 case OPC2_32_RRR1_MADDRS_H_UL:
6963 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6964 cpu_gpr_d[r2], n, MODE_UL);
6965 break;
6966 case OPC2_32_RRR1_MADDRS_H_UU:
6967 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6968 cpu_gpr_d[r2], n, MODE_UU);
6969 break;
6970 default:
6971 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6972 }
6973 }
6974
6975 static void decode_rrr1_maddq_h(DisasContext *ctx)
6976 {
6977 uint32_t op2;
6978 uint32_t r1, r2, r3, r4, n;
6979 TCGv temp, temp2;
6980
6981 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6982 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6983 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6984 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6985 r4 = MASK_OP_RRR1_D(ctx->opcode);
6986 n = MASK_OP_RRR1_N(ctx->opcode);
6987
6988 temp = tcg_temp_new();
6989 temp2 = tcg_temp_new();
6990
6991 switch (op2) {
6992 case OPC2_32_RRR1_MADD_Q_32:
6993 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6994 cpu_gpr_d[r2], n, 32);
6995 break;
6996 case OPC2_32_RRR1_MADD_Q_64:
6997 CHECK_REG_PAIR(r4);
6998 CHECK_REG_PAIR(r3);
6999 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7000 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7001 n);
7002 break;
7003 case OPC2_32_RRR1_MADD_Q_32_L:
7004 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7005 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7006 temp, n, 16);
7007 break;
7008 case OPC2_32_RRR1_MADD_Q_64_L:
7009 CHECK_REG_PAIR(r4);
7010 CHECK_REG_PAIR(r3);
7011 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7012 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7013 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7014 n);
7015 break;
7016 case OPC2_32_RRR1_MADD_Q_32_U:
7017 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7018 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7019 temp, n, 16);
7020 break;
7021 case OPC2_32_RRR1_MADD_Q_64_U:
7022 CHECK_REG_PAIR(r4);
7023 CHECK_REG_PAIR(r3);
7024 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7025 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7026 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7027 n);
7028 break;
7029 case OPC2_32_RRR1_MADD_Q_32_LL:
7030 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7031 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7032 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7033 break;
7034 case OPC2_32_RRR1_MADD_Q_64_LL:
7035 CHECK_REG_PAIR(r4);
7036 CHECK_REG_PAIR(r3);
7037 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7038 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7039 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7040 cpu_gpr_d[r3+1], temp, temp2, n);
7041 break;
7042 case OPC2_32_RRR1_MADD_Q_32_UU:
7043 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7044 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7045 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7046 break;
7047 case OPC2_32_RRR1_MADD_Q_64_UU:
7048 CHECK_REG_PAIR(r4);
7049 CHECK_REG_PAIR(r3);
7050 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7051 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7052 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7053 cpu_gpr_d[r3+1], temp, temp2, n);
7054 break;
7055 case OPC2_32_RRR1_MADDS_Q_32:
7056 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7057 cpu_gpr_d[r2], n, 32);
7058 break;
7059 case OPC2_32_RRR1_MADDS_Q_64:
7060 CHECK_REG_PAIR(r4);
7061 CHECK_REG_PAIR(r3);
7062 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7063 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7064 n);
7065 break;
7066 case OPC2_32_RRR1_MADDS_Q_32_L:
7067 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7068 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7069 temp, n, 16);
7070 break;
7071 case OPC2_32_RRR1_MADDS_Q_64_L:
7072 CHECK_REG_PAIR(r4);
7073 CHECK_REG_PAIR(r3);
7074 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7075 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7076 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7077 n);
7078 break;
7079 case OPC2_32_RRR1_MADDS_Q_32_U:
7080 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7081 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7082 temp, n, 16);
7083 break;
7084 case OPC2_32_RRR1_MADDS_Q_64_U:
7085 CHECK_REG_PAIR(r4);
7086 CHECK_REG_PAIR(r3);
7087 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7088 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7089 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7090 n);
7091 break;
7092 case OPC2_32_RRR1_MADDS_Q_32_LL:
7093 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7094 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7095 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7096 break;
7097 case OPC2_32_RRR1_MADDS_Q_64_LL:
7098 CHECK_REG_PAIR(r4);
7099 CHECK_REG_PAIR(r3);
7100 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7101 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7102 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7103 cpu_gpr_d[r3+1], temp, temp2, n);
7104 break;
7105 case OPC2_32_RRR1_MADDS_Q_32_UU:
7106 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7107 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7108 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7109 break;
7110 case OPC2_32_RRR1_MADDS_Q_64_UU:
7111 CHECK_REG_PAIR(r4);
7112 CHECK_REG_PAIR(r3);
7113 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7114 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7115 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7116 cpu_gpr_d[r3+1], temp, temp2, n);
7117 break;
7118 case OPC2_32_RRR1_MADDR_H_64_UL:
7119 CHECK_REG_PAIR(r3);
7120 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7121 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7122 break;
7123 case OPC2_32_RRR1_MADDRS_H_64_UL:
7124 CHECK_REG_PAIR(r3);
7125 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7126 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7127 break;
7128 case OPC2_32_RRR1_MADDR_Q_32_LL:
7129 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7130 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7131 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7132 break;
7133 case OPC2_32_RRR1_MADDR_Q_32_UU:
7134 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7135 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7136 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7137 break;
7138 case OPC2_32_RRR1_MADDRS_Q_32_LL:
7139 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7140 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7141 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7142 break;
7143 case OPC2_32_RRR1_MADDRS_Q_32_UU:
7144 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7145 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7146 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7147 break;
7148 default:
7149 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7150 }
7151 }
7152
7153 static void decode_rrr1_maddsu_h(DisasContext *ctx)
7154 {
7155 uint32_t op2;
7156 uint32_t r1, r2, r3, r4, n;
7157
7158 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7159 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7160 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7161 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7162 r4 = MASK_OP_RRR1_D(ctx->opcode);
7163 n = MASK_OP_RRR1_N(ctx->opcode);
7164
7165 switch (op2) {
7166 case OPC2_32_RRR1_MADDSU_H_32_LL:
7167 CHECK_REG_PAIR(r4);
7168 CHECK_REG_PAIR(r3);
7169 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7170 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7171 break;
7172 case OPC2_32_RRR1_MADDSU_H_32_LU:
7173 CHECK_REG_PAIR(r4);
7174 CHECK_REG_PAIR(r3);
7175 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7176 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7177 break;
7178 case OPC2_32_RRR1_MADDSU_H_32_UL:
7179 CHECK_REG_PAIR(r4);
7180 CHECK_REG_PAIR(r3);
7181 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7182 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7183 break;
7184 case OPC2_32_RRR1_MADDSU_H_32_UU:
7185 CHECK_REG_PAIR(r4);
7186 CHECK_REG_PAIR(r3);
7187 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7188 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7189 break;
7190 case OPC2_32_RRR1_MADDSUS_H_32_LL:
7191 CHECK_REG_PAIR(r4);
7192 CHECK_REG_PAIR(r3);
7193 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7194 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7195 n, MODE_LL);
7196 break;
7197 case OPC2_32_RRR1_MADDSUS_H_32_LU:
7198 CHECK_REG_PAIR(r4);
7199 CHECK_REG_PAIR(r3);
7200 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7201 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7202 n, MODE_LU);
7203 break;
7204 case OPC2_32_RRR1_MADDSUS_H_32_UL:
7205 CHECK_REG_PAIR(r4);
7206 CHECK_REG_PAIR(r3);
7207 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7208 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7209 n, MODE_UL);
7210 break;
7211 case OPC2_32_RRR1_MADDSUS_H_32_UU:
7212 CHECK_REG_PAIR(r4);
7213 CHECK_REG_PAIR(r3);
7214 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7215 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7216 n, MODE_UU);
7217 break;
7218 case OPC2_32_RRR1_MADDSUM_H_64_LL:
7219 CHECK_REG_PAIR(r4);
7220 CHECK_REG_PAIR(r3);
7221 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7222 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7223 n, MODE_LL);
7224 break;
7225 case OPC2_32_RRR1_MADDSUM_H_64_LU:
7226 CHECK_REG_PAIR(r4);
7227 CHECK_REG_PAIR(r3);
7228 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7229 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7230 n, MODE_LU);
7231 break;
7232 case OPC2_32_RRR1_MADDSUM_H_64_UL:
7233 CHECK_REG_PAIR(r4);
7234 CHECK_REG_PAIR(r3);
7235 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7236 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7237 n, MODE_UL);
7238 break;
7239 case OPC2_32_RRR1_MADDSUM_H_64_UU:
7240 CHECK_REG_PAIR(r4);
7241 CHECK_REG_PAIR(r3);
7242 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7243 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7244 n, MODE_UU);
7245 break;
7246 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
7247 CHECK_REG_PAIR(r4);
7248 CHECK_REG_PAIR(r3);
7249 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7250 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7251 n, MODE_LL);
7252 break;
7253 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
7254 CHECK_REG_PAIR(r4);
7255 CHECK_REG_PAIR(r3);
7256 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7257 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7258 n, MODE_LU);
7259 break;
7260 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
7261 CHECK_REG_PAIR(r4);
7262 CHECK_REG_PAIR(r3);
7263 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7264 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7265 n, MODE_UL);
7266 break;
7267 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
7268 CHECK_REG_PAIR(r4);
7269 CHECK_REG_PAIR(r3);
7270 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7271 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7272 n, MODE_UU);
7273 break;
7274 case OPC2_32_RRR1_MADDSUR_H_16_LL:
7275 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7276 cpu_gpr_d[r2], n, MODE_LL);
7277 break;
7278 case OPC2_32_RRR1_MADDSUR_H_16_LU:
7279 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7280 cpu_gpr_d[r2], n, MODE_LU);
7281 break;
7282 case OPC2_32_RRR1_MADDSUR_H_16_UL:
7283 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7284 cpu_gpr_d[r2], n, MODE_UL);
7285 break;
7286 case OPC2_32_RRR1_MADDSUR_H_16_UU:
7287 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7288 cpu_gpr_d[r2], n, MODE_UU);
7289 break;
7290 case OPC2_32_RRR1_MADDSURS_H_16_LL:
7291 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7292 cpu_gpr_d[r2], n, MODE_LL);
7293 break;
7294 case OPC2_32_RRR1_MADDSURS_H_16_LU:
7295 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7296 cpu_gpr_d[r2], n, MODE_LU);
7297 break;
7298 case OPC2_32_RRR1_MADDSURS_H_16_UL:
7299 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7300 cpu_gpr_d[r2], n, MODE_UL);
7301 break;
7302 case OPC2_32_RRR1_MADDSURS_H_16_UU:
7303 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7304 cpu_gpr_d[r2], n, MODE_UU);
7305 break;
7306 default:
7307 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7308 }
7309 }
7310
7311 static void decode_rrr1_msub(DisasContext *ctx)
7312 {
7313 uint32_t op2;
7314 uint32_t r1, r2, r3, r4, n;
7315
7316 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7317 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7318 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7319 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7320 r4 = MASK_OP_RRR1_D(ctx->opcode);
7321 n = MASK_OP_RRR1_N(ctx->opcode);
7322
7323 switch (op2) {
7324 case OPC2_32_RRR1_MSUB_H_LL:
7325 CHECK_REG_PAIR(r4);
7326 CHECK_REG_PAIR(r3);
7327 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7328 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7329 break;
7330 case OPC2_32_RRR1_MSUB_H_LU:
7331 CHECK_REG_PAIR(r4);
7332 CHECK_REG_PAIR(r3);
7333 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7334 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7335 break;
7336 case OPC2_32_RRR1_MSUB_H_UL:
7337 CHECK_REG_PAIR(r4);
7338 CHECK_REG_PAIR(r3);
7339 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7340 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7341 break;
7342 case OPC2_32_RRR1_MSUB_H_UU:
7343 CHECK_REG_PAIR(r4);
7344 CHECK_REG_PAIR(r3);
7345 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7346 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7347 break;
7348 case OPC2_32_RRR1_MSUBS_H_LL:
7349 CHECK_REG_PAIR(r4);
7350 CHECK_REG_PAIR(r3);
7351 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7352 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7353 break;
7354 case OPC2_32_RRR1_MSUBS_H_LU:
7355 CHECK_REG_PAIR(r4);
7356 CHECK_REG_PAIR(r3);
7357 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7358 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7359 break;
7360 case OPC2_32_RRR1_MSUBS_H_UL:
7361 CHECK_REG_PAIR(r4);
7362 CHECK_REG_PAIR(r3);
7363 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7364 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7365 break;
7366 case OPC2_32_RRR1_MSUBS_H_UU:
7367 CHECK_REG_PAIR(r4);
7368 CHECK_REG_PAIR(r3);
7369 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7370 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7371 break;
7372 case OPC2_32_RRR1_MSUBM_H_LL:
7373 CHECK_REG_PAIR(r4);
7374 CHECK_REG_PAIR(r3);
7375 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7376 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7377 break;
7378 case OPC2_32_RRR1_MSUBM_H_LU:
7379 CHECK_REG_PAIR(r4);
7380 CHECK_REG_PAIR(r3);
7381 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7382 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7383 break;
7384 case OPC2_32_RRR1_MSUBM_H_UL:
7385 CHECK_REG_PAIR(r4);
7386 CHECK_REG_PAIR(r3);
7387 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7388 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7389 break;
7390 case OPC2_32_RRR1_MSUBM_H_UU:
7391 CHECK_REG_PAIR(r4);
7392 CHECK_REG_PAIR(r3);
7393 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7394 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7395 break;
7396 case OPC2_32_RRR1_MSUBMS_H_LL:
7397 CHECK_REG_PAIR(r4);
7398 CHECK_REG_PAIR(r3);
7399 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7400 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7401 break;
7402 case OPC2_32_RRR1_MSUBMS_H_LU:
7403 CHECK_REG_PAIR(r4);
7404 CHECK_REG_PAIR(r3);
7405 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7406 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7407 break;
7408 case OPC2_32_RRR1_MSUBMS_H_UL:
7409 CHECK_REG_PAIR(r4);
7410 CHECK_REG_PAIR(r3);
7411 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7412 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7413 break;
7414 case OPC2_32_RRR1_MSUBMS_H_UU:
7415 CHECK_REG_PAIR(r4);
7416 CHECK_REG_PAIR(r3);
7417 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7418 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7419 break;
7420 case OPC2_32_RRR1_MSUBR_H_LL:
7421 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7422 cpu_gpr_d[r2], n, MODE_LL);
7423 break;
7424 case OPC2_32_RRR1_MSUBR_H_LU:
7425 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7426 cpu_gpr_d[r2], n, MODE_LU);
7427 break;
7428 case OPC2_32_RRR1_MSUBR_H_UL:
7429 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7430 cpu_gpr_d[r2], n, MODE_UL);
7431 break;
7432 case OPC2_32_RRR1_MSUBR_H_UU:
7433 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7434 cpu_gpr_d[r2], n, MODE_UU);
7435 break;
7436 case OPC2_32_RRR1_MSUBRS_H_LL:
7437 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7438 cpu_gpr_d[r2], n, MODE_LL);
7439 break;
7440 case OPC2_32_RRR1_MSUBRS_H_LU:
7441 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7442 cpu_gpr_d[r2], n, MODE_LU);
7443 break;
7444 case OPC2_32_RRR1_MSUBRS_H_UL:
7445 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7446 cpu_gpr_d[r2], n, MODE_UL);
7447 break;
7448 case OPC2_32_RRR1_MSUBRS_H_UU:
7449 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7450 cpu_gpr_d[r2], n, MODE_UU);
7451 break;
7452 default:
7453 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7454 }
7455 }
7456
7457 static void decode_rrr1_msubq_h(DisasContext *ctx)
7458 {
7459 uint32_t op2;
7460 uint32_t r1, r2, r3, r4, n;
7461 TCGv temp, temp2;
7462
7463 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7464 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7465 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7466 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7467 r4 = MASK_OP_RRR1_D(ctx->opcode);
7468 n = MASK_OP_RRR1_N(ctx->opcode);
7469
7470 temp = tcg_temp_new();
7471 temp2 = tcg_temp_new();
7472
7473 switch (op2) {
7474 case OPC2_32_RRR1_MSUB_Q_32:
7475 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7476 cpu_gpr_d[r2], n, 32);
7477 break;
7478 case OPC2_32_RRR1_MSUB_Q_64:
7479 CHECK_REG_PAIR(r4);
7480 CHECK_REG_PAIR(r3);
7481 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7482 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7483 n);
7484 break;
7485 case OPC2_32_RRR1_MSUB_Q_32_L:
7486 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7487 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7488 temp, n, 16);
7489 break;
7490 case OPC2_32_RRR1_MSUB_Q_64_L:
7491 CHECK_REG_PAIR(r4);
7492 CHECK_REG_PAIR(r3);
7493 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7494 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7495 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7496 n);
7497 break;
7498 case OPC2_32_RRR1_MSUB_Q_32_U:
7499 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7500 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7501 temp, n, 16);
7502 break;
7503 case OPC2_32_RRR1_MSUB_Q_64_U:
7504 CHECK_REG_PAIR(r4);
7505 CHECK_REG_PAIR(r3);
7506 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7507 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7508 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7509 n);
7510 break;
7511 case OPC2_32_RRR1_MSUB_Q_32_LL:
7512 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7513 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7514 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7515 break;
7516 case OPC2_32_RRR1_MSUB_Q_64_LL:
7517 CHECK_REG_PAIR(r4);
7518 CHECK_REG_PAIR(r3);
7519 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7520 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7521 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7522 cpu_gpr_d[r3+1], temp, temp2, n);
7523 break;
7524 case OPC2_32_RRR1_MSUB_Q_32_UU:
7525 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7526 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7527 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7528 break;
7529 case OPC2_32_RRR1_MSUB_Q_64_UU:
7530 CHECK_REG_PAIR(r4);
7531 CHECK_REG_PAIR(r3);
7532 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7533 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7534 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7535 cpu_gpr_d[r3+1], temp, temp2, n);
7536 break;
7537 case OPC2_32_RRR1_MSUBS_Q_32:
7538 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7539 cpu_gpr_d[r2], n, 32);
7540 break;
7541 case OPC2_32_RRR1_MSUBS_Q_64:
7542 CHECK_REG_PAIR(r4);
7543 CHECK_REG_PAIR(r3);
7544 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7545 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7546 n);
7547 break;
7548 case OPC2_32_RRR1_MSUBS_Q_32_L:
7549 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7550 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7551 temp, n, 16);
7552 break;
7553 case OPC2_32_RRR1_MSUBS_Q_64_L:
7554 CHECK_REG_PAIR(r4);
7555 CHECK_REG_PAIR(r3);
7556 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7557 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7558 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7559 n);
7560 break;
7561 case OPC2_32_RRR1_MSUBS_Q_32_U:
7562 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7563 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7564 temp, n, 16);
7565 break;
7566 case OPC2_32_RRR1_MSUBS_Q_64_U:
7567 CHECK_REG_PAIR(r4);
7568 CHECK_REG_PAIR(r3);
7569 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7570 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7571 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7572 n);
7573 break;
7574 case OPC2_32_RRR1_MSUBS_Q_32_LL:
7575 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7576 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7577 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7578 break;
7579 case OPC2_32_RRR1_MSUBS_Q_64_LL:
7580 CHECK_REG_PAIR(r4);
7581 CHECK_REG_PAIR(r3);
7582 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7583 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7584 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7585 cpu_gpr_d[r3+1], temp, temp2, n);
7586 break;
7587 case OPC2_32_RRR1_MSUBS_Q_32_UU:
7588 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7589 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7590 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7591 break;
7592 case OPC2_32_RRR1_MSUBS_Q_64_UU:
7593 CHECK_REG_PAIR(r4);
7594 CHECK_REG_PAIR(r3);
7595 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7596 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7597 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7598 cpu_gpr_d[r3+1], temp, temp2, n);
7599 break;
7600 case OPC2_32_RRR1_MSUBR_H_64_UL:
7601 CHECK_REG_PAIR(r3);
7602 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7603 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7604 break;
7605 case OPC2_32_RRR1_MSUBRS_H_64_UL:
7606 CHECK_REG_PAIR(r3);
7607 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7608 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7609 break;
7610 case OPC2_32_RRR1_MSUBR_Q_32_LL:
7611 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7612 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7613 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7614 break;
7615 case OPC2_32_RRR1_MSUBR_Q_32_UU:
7616 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7617 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7618 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7619 break;
7620 case OPC2_32_RRR1_MSUBRS_Q_32_LL:
7621 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7622 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7623 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7624 break;
7625 case OPC2_32_RRR1_MSUBRS_Q_32_UU:
7626 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7627 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7628 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7629 break;
7630 default:
7631 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7632 }
7633 }
7634
7635 static void decode_rrr1_msubad_h(DisasContext *ctx)
7636 {
7637 uint32_t op2;
7638 uint32_t r1, r2, r3, r4, n;
7639
7640 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7641 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7642 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7643 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7644 r4 = MASK_OP_RRR1_D(ctx->opcode);
7645 n = MASK_OP_RRR1_N(ctx->opcode);
7646
7647 switch (op2) {
7648 case OPC2_32_RRR1_MSUBAD_H_32_LL:
7649 CHECK_REG_PAIR(r4);
7650 CHECK_REG_PAIR(r3);
7651 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7652 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7653 break;
7654 case OPC2_32_RRR1_MSUBAD_H_32_LU:
7655 CHECK_REG_PAIR(r4);
7656 CHECK_REG_PAIR(r3);
7657 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7658 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7659 break;
7660 case OPC2_32_RRR1_MSUBAD_H_32_UL:
7661 CHECK_REG_PAIR(r4);
7662 CHECK_REG_PAIR(r3);
7663 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7664 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7665 break;
7666 case OPC2_32_RRR1_MSUBAD_H_32_UU:
7667 CHECK_REG_PAIR(r4);
7668 CHECK_REG_PAIR(r3);
7669 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7670 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7671 break;
7672 case OPC2_32_RRR1_MSUBADS_H_32_LL:
7673 CHECK_REG_PAIR(r4);
7674 CHECK_REG_PAIR(r3);
7675 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7676 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7677 n, MODE_LL);
7678 break;
7679 case OPC2_32_RRR1_MSUBADS_H_32_LU:
7680 CHECK_REG_PAIR(r4);
7681 CHECK_REG_PAIR(r3);
7682 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7683 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7684 n, MODE_LU);
7685 break;
7686 case OPC2_32_RRR1_MSUBADS_H_32_UL:
7687 CHECK_REG_PAIR(r4);
7688 CHECK_REG_PAIR(r3);
7689 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7690 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7691 n, MODE_UL);
7692 break;
7693 case OPC2_32_RRR1_MSUBADS_H_32_UU:
7694 CHECK_REG_PAIR(r4);
7695 CHECK_REG_PAIR(r3);
7696 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7697 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7698 n, MODE_UU);
7699 break;
7700 case OPC2_32_RRR1_MSUBADM_H_64_LL:
7701 CHECK_REG_PAIR(r4);
7702 CHECK_REG_PAIR(r3);
7703 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7704 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7705 n, MODE_LL);
7706 break;
7707 case OPC2_32_RRR1_MSUBADM_H_64_LU:
7708 CHECK_REG_PAIR(r4);
7709 CHECK_REG_PAIR(r3);
7710 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7711 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7712 n, MODE_LU);
7713 break;
7714 case OPC2_32_RRR1_MSUBADM_H_64_UL:
7715 CHECK_REG_PAIR(r4);
7716 CHECK_REG_PAIR(r3);
7717 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7718 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7719 n, MODE_UL);
7720 break;
7721 case OPC2_32_RRR1_MSUBADM_H_64_UU:
7722 CHECK_REG_PAIR(r4);
7723 CHECK_REG_PAIR(r3);
7724 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7725 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7726 n, MODE_UU);
7727 break;
7728 case OPC2_32_RRR1_MSUBADMS_H_64_LL:
7729 CHECK_REG_PAIR(r4);
7730 CHECK_REG_PAIR(r3);
7731 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7732 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7733 n, MODE_LL);
7734 break;
7735 case OPC2_32_RRR1_MSUBADMS_H_64_LU:
7736 CHECK_REG_PAIR(r4);
7737 CHECK_REG_PAIR(r3);
7738 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7739 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7740 n, MODE_LU);
7741 break;
7742 case OPC2_32_RRR1_MSUBADMS_H_64_UL:
7743 CHECK_REG_PAIR(r4);
7744 CHECK_REG_PAIR(r3);
7745 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7746 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7747 n, MODE_UL);
7748 break;
7749 case OPC2_32_RRR1_MSUBADMS_H_64_UU:
7750 CHECK_REG_PAIR(r4);
7751 CHECK_REG_PAIR(r3);
7752 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7753 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7754 n, MODE_UU);
7755 break;
7756 case OPC2_32_RRR1_MSUBADR_H_16_LL:
7757 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7758 cpu_gpr_d[r2], n, MODE_LL);
7759 break;
7760 case OPC2_32_RRR1_MSUBADR_H_16_LU:
7761 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7762 cpu_gpr_d[r2], n, MODE_LU);
7763 break;
7764 case OPC2_32_RRR1_MSUBADR_H_16_UL:
7765 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7766 cpu_gpr_d[r2], n, MODE_UL);
7767 break;
7768 case OPC2_32_RRR1_MSUBADR_H_16_UU:
7769 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7770 cpu_gpr_d[r2], n, MODE_UU);
7771 break;
7772 case OPC2_32_RRR1_MSUBADRS_H_16_LL:
7773 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7774 cpu_gpr_d[r2], n, MODE_LL);
7775 break;
7776 case OPC2_32_RRR1_MSUBADRS_H_16_LU:
7777 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7778 cpu_gpr_d[r2], n, MODE_LU);
7779 break;
7780 case OPC2_32_RRR1_MSUBADRS_H_16_UL:
7781 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7782 cpu_gpr_d[r2], n, MODE_UL);
7783 break;
7784 case OPC2_32_RRR1_MSUBADRS_H_16_UU:
7785 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7786 cpu_gpr_d[r2], n, MODE_UU);
7787 break;
7788 default:
7789 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7790 }
7791 }
7792
7793 /* RRRR format */
7794 static void decode_rrrr_extract_insert(DisasContext *ctx)
7795 {
7796 uint32_t op2;
7797 int r1, r2, r3, r4;
7798 TCGv tmp_width, tmp_pos;
7799
7800 r1 = MASK_OP_RRRR_S1(ctx->opcode);
7801 r2 = MASK_OP_RRRR_S2(ctx->opcode);
7802 r3 = MASK_OP_RRRR_S3(ctx->opcode);
7803 r4 = MASK_OP_RRRR_D(ctx->opcode);
7804 op2 = MASK_OP_RRRR_OP2(ctx->opcode);
7805
7806 tmp_pos = tcg_temp_new();
7807 tmp_width = tcg_temp_new();
7808
7809 switch (op2) {
7810 case OPC2_32_RRRR_DEXTR:
7811 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7812 if (r1 == r2) {
7813 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7814 } else {
7815 TCGv msw = tcg_temp_new();
7816 TCGv zero = tcg_constant_tl(0);
7817 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
7818 tcg_gen_subfi_tl(msw, 32, tmp_pos);
7819 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw);
7820 /*
7821 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined
7822 * behaviour. So check that case here and set the low bits to zero
7823 * which effectivly returns cpu_gpr_d[r1]
7824 */
7825 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw);
7826 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw);
7827 }
7828 break;
7829 case OPC2_32_RRRR_EXTR:
7830 case OPC2_32_RRRR_EXTR_U:
7831 CHECK_REG_PAIR(r3);
7832 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7833 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7834 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
7835 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7836 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7837 tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
7838 if (op2 == OPC2_32_RRRR_EXTR) {
7839 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7840 } else {
7841 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7842 }
7843 break;
7844 case OPC2_32_RRRR_INSERT:
7845 CHECK_REG_PAIR(r3);
7846 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7847 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7848 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
7849 tmp_pos);
7850 break;
7851 default:
7852 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7853 }
7854 }
7855
7856 /* RRRW format */
7857 static void decode_rrrw_extract_insert(DisasContext *ctx)
7858 {
7859 uint32_t op2;
7860 int r1, r2, r3, r4;
7861 int32_t width;
7862
7863 TCGv temp, temp2;
7864
7865 op2 = MASK_OP_RRRW_OP2(ctx->opcode);
7866 r1 = MASK_OP_RRRW_S1(ctx->opcode);
7867 r2 = MASK_OP_RRRW_S2(ctx->opcode);
7868 r3 = MASK_OP_RRRW_S3(ctx->opcode);
7869 r4 = MASK_OP_RRRW_D(ctx->opcode);
7870 width = MASK_OP_RRRW_WIDTH(ctx->opcode);
7871
7872 temp = tcg_temp_new();
7873
7874 switch (op2) {
7875 case OPC2_32_RRRW_EXTR:
7876 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7877 tcg_gen_addi_tl(temp, temp, width);
7878 tcg_gen_subfi_tl(temp, 32, temp);
7879 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7880 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
7881 break;
7882 case OPC2_32_RRRW_EXTR_U:
7883 if (width == 0) {
7884 tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
7885 } else {
7886 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7887 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7888 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
7889 }
7890 break;
7891 case OPC2_32_RRRW_IMASK:
7892 temp2 = tcg_temp_new();
7893 CHECK_REG_PAIR(r4);
7894 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7895 tcg_gen_movi_tl(temp2, (1 << width) - 1);
7896 tcg_gen_shl_tl(temp2, temp2, temp);
7897 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
7898 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
7899 break;
7900 case OPC2_32_RRRW_INSERT:
7901 temp2 = tcg_temp_new();
7902
7903 tcg_gen_movi_tl(temp, width);
7904 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
7905 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
7906 break;
7907 default:
7908 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7909 }
7910 }
7911
7912 /* SYS Format*/
7913 static void decode_sys_interrupts(DisasContext *ctx)
7914 {
7915 uint32_t op2;
7916 uint32_t r1;
7917 TCGLabel *l1;
7918 TCGv tmp;
7919
7920 op2 = MASK_OP_SYS_OP2(ctx->opcode);
7921 r1 = MASK_OP_SYS_S1D(ctx->opcode);
7922
7923 switch (op2) {
7924 case OPC2_32_SYS_DEBUG:
7925 /* raise EXCP_DEBUG */
7926 break;
7927 case OPC2_32_SYS_DISABLE:
7928 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
7929 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
7930 } else {
7931 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
7932 }
7933 break;
7934 case OPC2_32_SYS_DISABLE_D:
7935 if (has_feature(ctx, TRICORE_FEATURE_16)) {
7936 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
7937 tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR,
7938 ctx->icr_ie_offset, 1);
7939 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
7940 } else {
7941 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
7942 }
7943 } else {
7944 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7945 }
7946 case OPC2_32_SYS_DSYNC:
7947 break;
7948 case OPC2_32_SYS_ENABLE:
7949 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
7950 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
7951 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
7952 } else {
7953 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
7954 }
7955 break;
7956 case OPC2_32_SYS_ISYNC:
7957 break;
7958 case OPC2_32_SYS_NOP:
7959 break;
7960 case OPC2_32_SYS_RET:
7961 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
7962 break;
7963 case OPC2_32_SYS_FRET:
7964 gen_fret(ctx);
7965 break;
7966 case OPC2_32_SYS_RFE:
7967 gen_helper_rfe(cpu_env);
7968 ctx->base.is_jmp = DISAS_EXIT;
7969 break;
7970 case OPC2_32_SYS_RFM:
7971 if (ctx->priv == TRICORE_PRIV_SM) {
7972 tmp = tcg_temp_new();
7973 l1 = gen_new_label();
7974
7975 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
7976 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
7977 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
7978 gen_helper_rfm(cpu_env);
7979 gen_set_label(l1);
7980 ctx->base.is_jmp = DISAS_EXIT;
7981 } else {
7982 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
7983 }
7984 break;
7985 case OPC2_32_SYS_RSLCX:
7986 gen_helper_rslcx(cpu_env);
7987 break;
7988 case OPC2_32_SYS_SVLCX:
7989 gen_helper_svlcx(cpu_env);
7990 break;
7991 case OPC2_32_SYS_RESTORE:
7992 if (has_feature(ctx, TRICORE_FEATURE_16)) {
7993 if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
7994 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1],
7995 ctx->icr_ie_offset, 1);
7996 ctx->base.is_jmp = DISAS_EXIT_UPDATE;
7997 } else {
7998 generate_trap(ctx, TRAPC_PROT, TIN1_PRIV);
7999 }
8000 } else {
8001 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8002 }
8003 break;
8004 case OPC2_32_SYS_TRAPSV:
8005 l1 = gen_new_label();
8006 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1);
8007 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF);
8008 gen_set_label(l1);
8009 break;
8010 case OPC2_32_SYS_TRAPV:
8011 l1 = gen_new_label();
8012 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1);
8013 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF);
8014 gen_set_label(l1);
8015 break;
8016 default:
8017 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8018 }
8019 }
8020
8021 static void decode_32Bit_opc(DisasContext *ctx)
8022 {
8023 int op1, op2;
8024 int32_t r1, r2, r3;
8025 int32_t address, const16;
8026 int8_t b, const4;
8027 int32_t bpos;
8028 TCGv temp, temp2, temp3;
8029
8030 op1 = MASK_OP_MAJOR(ctx->opcode);
8031
8032 /* handle JNZ.T opcode only being 7 bit long */
8033 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
8034 op1 = OPCM_32_BRN_JTT;
8035 }
8036
8037 switch (op1) {
8038 /* ABS-format */
8039 case OPCM_32_ABS_LDW:
8040 decode_abs_ldw(ctx);
8041 break;
8042 case OPCM_32_ABS_LDB:
8043 decode_abs_ldb(ctx);
8044 break;
8045 case OPCM_32_ABS_LDMST_SWAP:
8046 decode_abs_ldst_swap(ctx);
8047 break;
8048 case OPCM_32_ABS_LDST_CONTEXT:
8049 decode_abs_ldst_context(ctx);
8050 break;
8051 case OPCM_32_ABS_STORE:
8052 decode_abs_store(ctx);
8053 break;
8054 case OPCM_32_ABS_STOREB_H:
8055 decode_abs_storeb_h(ctx);
8056 break;
8057 case OPC1_32_ABS_STOREQ:
8058 address = MASK_OP_ABS_OFF18(ctx->opcode);
8059 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8060 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
8061 temp2 = tcg_temp_new();
8062
8063 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
8064 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
8065 break;
8066 case OPC1_32_ABS_LD_Q:
8067 address = MASK_OP_ABS_OFF18(ctx->opcode);
8068 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8069 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
8070
8071 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
8072 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
8073 break;
8074 case OPCM_32_ABS_LEA_LHA:
8075 address = MASK_OP_ABS_OFF18(ctx->opcode);
8076 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8077
8078 if (has_feature(ctx, TRICORE_FEATURE_162)) {
8079 op2 = MASK_OP_ABS_OP2(ctx->opcode);
8080 if (op2 == OPC2_32_ABS_LHA) {
8081 tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14);
8082 break;
8083 }
8084 /* otherwise translate regular LEA */
8085 }
8086
8087 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
8088 break;
8089 /* ABSB-format */
8090 case OPC1_32_ABSB_ST_T:
8091 address = MASK_OP_ABS_OFF18(ctx->opcode);
8092 b = MASK_OP_ABSB_B(ctx->opcode);
8093 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
8094
8095 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
8096 temp2 = tcg_temp_new();
8097
8098 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
8099 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
8100 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
8101 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
8102 break;
8103 /* B-format */
8104 case OPC1_32_B_CALL:
8105 case OPC1_32_B_CALLA:
8106 case OPC1_32_B_FCALL:
8107 case OPC1_32_B_FCALLA:
8108 case OPC1_32_B_J:
8109 case OPC1_32_B_JA:
8110 case OPC1_32_B_JL:
8111 case OPC1_32_B_JLA:
8112 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
8113 gen_compute_branch(ctx, op1, 0, 0, 0, address);
8114 break;
8115 /* Bit-format */
8116 case OPCM_32_BIT_ANDACC:
8117 decode_bit_andacc(ctx);
8118 break;
8119 case OPCM_32_BIT_LOGICAL_T1:
8120 decode_bit_logical_t(ctx);
8121 break;
8122 case OPCM_32_BIT_INSERT:
8123 decode_bit_insert(ctx);
8124 break;
8125 case OPCM_32_BIT_LOGICAL_T2:
8126 decode_bit_logical_t2(ctx);
8127 break;
8128 case OPCM_32_BIT_ORAND:
8129 decode_bit_orand(ctx);
8130 break;
8131 case OPCM_32_BIT_SH_LOGIC1:
8132 decode_bit_sh_logic1(ctx);
8133 break;
8134 case OPCM_32_BIT_SH_LOGIC2:
8135 decode_bit_sh_logic2(ctx);
8136 break;
8137 /* BO Format */
8138 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
8139 decode_bo_addrmode_post_pre_base(ctx);
8140 break;
8141 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
8142 decode_bo_addrmode_bitreverse_circular(ctx);
8143 break;
8144 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
8145 decode_bo_addrmode_ld_post_pre_base(ctx);
8146 break;
8147 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
8148 decode_bo_addrmode_ld_bitreverse_circular(ctx);
8149 break;
8150 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
8151 decode_bo_addrmode_stctx_post_pre_base(ctx);
8152 break;
8153 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
8154 decode_bo_addrmode_ldmst_bitreverse_circular(ctx);
8155 break;
8156 /* BOL-format */
8157 case OPC1_32_BOL_LD_A_LONGOFF:
8158 case OPC1_32_BOL_LD_W_LONGOFF:
8159 case OPC1_32_BOL_LEA_LONGOFF:
8160 case OPC1_32_BOL_ST_W_LONGOFF:
8161 case OPC1_32_BOL_ST_A_LONGOFF:
8162 case OPC1_32_BOL_LD_B_LONGOFF:
8163 case OPC1_32_BOL_LD_BU_LONGOFF:
8164 case OPC1_32_BOL_LD_H_LONGOFF:
8165 case OPC1_32_BOL_LD_HU_LONGOFF:
8166 case OPC1_32_BOL_ST_B_LONGOFF:
8167 case OPC1_32_BOL_ST_H_LONGOFF:
8168 decode_bol_opc(ctx, op1);
8169 break;
8170 /* BRC Format */
8171 case OPCM_32_BRC_EQ_NEQ:
8172 case OPCM_32_BRC_GE:
8173 case OPCM_32_BRC_JLT:
8174 case OPCM_32_BRC_JNE:
8175 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
8176 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
8177 r1 = MASK_OP_BRC_S1(ctx->opcode);
8178 gen_compute_branch(ctx, op1, r1, 0, const4, address);
8179 break;
8180 /* BRN Format */
8181 case OPCM_32_BRN_JTT:
8182 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
8183 r1 = MASK_OP_BRN_S1(ctx->opcode);
8184 gen_compute_branch(ctx, op1, r1, 0, 0, address);
8185 break;
8186 /* BRR Format */
8187 case OPCM_32_BRR_EQ_NEQ:
8188 case OPCM_32_BRR_ADDR_EQ_NEQ:
8189 case OPCM_32_BRR_GE:
8190 case OPCM_32_BRR_JLT:
8191 case OPCM_32_BRR_JNE:
8192 case OPCM_32_BRR_JNZ:
8193 case OPCM_32_BRR_LOOP:
8194 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
8195 r2 = MASK_OP_BRR_S2(ctx->opcode);
8196 r1 = MASK_OP_BRR_S1(ctx->opcode);
8197 gen_compute_branch(ctx, op1, r1, r2, 0, address);
8198 break;
8199 /* RC Format */
8200 case OPCM_32_RC_LOGICAL_SHIFT:
8201 decode_rc_logical_shift(ctx);
8202 break;
8203 case OPCM_32_RC_ACCUMULATOR:
8204 decode_rc_accumulator(ctx);
8205 break;
8206 case OPCM_32_RC_SERVICEROUTINE:
8207 decode_rc_serviceroutine(ctx);
8208 break;
8209 case OPCM_32_RC_MUL:
8210 decode_rc_mul(ctx);
8211 break;
8212 /* RCPW Format */
8213 case OPCM_32_RCPW_MASK_INSERT:
8214 decode_rcpw_insert(ctx);
8215 break;
8216 /* RCRR Format */
8217 case OPC1_32_RCRR_INSERT:
8218 r1 = MASK_OP_RCRR_S1(ctx->opcode);
8219 r2 = MASK_OP_RCRR_S3(ctx->opcode);
8220 r3 = MASK_OP_RCRR_D(ctx->opcode);
8221 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
8222 temp = tcg_constant_i32(const16);
8223 temp2 = tcg_temp_new(); /* width*/
8224 temp3 = tcg_temp_new(); /* pos */
8225
8226 CHECK_REG_PAIR(r2);
8227
8228 tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
8229 tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
8230
8231 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
8232 break;
8233 /* RCRW Format */
8234 case OPCM_32_RCRW_MASK_INSERT:
8235 decode_rcrw_insert(ctx);
8236 break;
8237 /* RCR Format */
8238 case OPCM_32_RCR_COND_SELECT:
8239 decode_rcr_cond_select(ctx);
8240 break;
8241 case OPCM_32_RCR_MADD:
8242 decode_rcr_madd(ctx);
8243 break;
8244 case OPCM_32_RCR_MSUB:
8245 decode_rcr_msub(ctx);
8246 break;
8247 /* RLC Format */
8248 case OPC1_32_RLC_ADDI:
8249 case OPC1_32_RLC_ADDIH:
8250 case OPC1_32_RLC_ADDIH_A:
8251 case OPC1_32_RLC_MFCR:
8252 case OPC1_32_RLC_MOV:
8253 case OPC1_32_RLC_MOV_64:
8254 case OPC1_32_RLC_MOV_U:
8255 case OPC1_32_RLC_MOV_H:
8256 case OPC1_32_RLC_MOVH_A:
8257 case OPC1_32_RLC_MTCR:
8258 decode_rlc_opc(ctx, op1);
8259 break;
8260 /* RR Format */
8261 case OPCM_32_RR_ACCUMULATOR:
8262 decode_rr_accumulator(ctx);
8263 break;
8264 case OPCM_32_RR_LOGICAL_SHIFT:
8265 decode_rr_logical_shift(ctx);
8266 break;
8267 case OPCM_32_RR_ADDRESS:
8268 decode_rr_address(ctx);
8269 break;
8270 case OPCM_32_RR_IDIRECT:
8271 decode_rr_idirect(ctx);
8272 break;
8273 case OPCM_32_RR_DIVIDE:
8274 decode_rr_divide(ctx);
8275 break;
8276 /* RR1 Format */
8277 case OPCM_32_RR1_MUL:
8278 decode_rr1_mul(ctx);
8279 break;
8280 case OPCM_32_RR1_MULQ:
8281 decode_rr1_mulq(ctx);
8282 break;
8283 /* RR2 format */
8284 case OPCM_32_RR2_MUL:
8285 decode_rr2_mul(ctx);
8286 break;
8287 /* RRPW format */
8288 case OPCM_32_RRPW_EXTRACT_INSERT:
8289 decode_rrpw_extract_insert(ctx);
8290 break;
8291 case OPC1_32_RRPW_DEXTR:
8292 r1 = MASK_OP_RRPW_S1(ctx->opcode);
8293 r2 = MASK_OP_RRPW_S2(ctx->opcode);
8294 r3 = MASK_OP_RRPW_D(ctx->opcode);
8295 const16 = MASK_OP_RRPW_POS(ctx->opcode);
8296
8297 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1],
8298 32 - const16);
8299 break;
8300 /* RRR Format */
8301 case OPCM_32_RRR_COND_SELECT:
8302 decode_rrr_cond_select(ctx);
8303 break;
8304 case OPCM_32_RRR_DIVIDE:
8305 decode_rrr_divide(ctx);
8306 break;
8307 /* RRR2 Format */
8308 case OPCM_32_RRR2_MADD:
8309 decode_rrr2_madd(ctx);
8310 break;
8311 case OPCM_32_RRR2_MSUB:
8312 decode_rrr2_msub(ctx);
8313 break;
8314 /* RRR1 format */
8315 case OPCM_32_RRR1_MADD:
8316 decode_rrr1_madd(ctx);
8317 break;
8318 case OPCM_32_RRR1_MADDQ_H:
8319 decode_rrr1_maddq_h(ctx);
8320 break;
8321 case OPCM_32_RRR1_MADDSU_H:
8322 decode_rrr1_maddsu_h(ctx);
8323 break;
8324 case OPCM_32_RRR1_MSUB_H:
8325 decode_rrr1_msub(ctx);
8326 break;
8327 case OPCM_32_RRR1_MSUB_Q:
8328 decode_rrr1_msubq_h(ctx);
8329 break;
8330 case OPCM_32_RRR1_MSUBAD_H:
8331 decode_rrr1_msubad_h(ctx);
8332 break;
8333 /* RRRR format */
8334 case OPCM_32_RRRR_EXTRACT_INSERT:
8335 decode_rrrr_extract_insert(ctx);
8336 break;
8337 /* RRRW format */
8338 case OPCM_32_RRRW_EXTRACT_INSERT:
8339 decode_rrrw_extract_insert(ctx);
8340 break;
8341 /* SYS format */
8342 case OPCM_32_SYS_INTERRUPTS:
8343 decode_sys_interrupts(ctx);
8344 break;
8345 case OPC1_32_SYS_RSTV:
8346 tcg_gen_movi_tl(cpu_PSW_V, 0);
8347 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
8348 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
8349 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
8350 break;
8351 default:
8352 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8353 }
8354 }
8355
8356 static bool tricore_insn_is_16bit(uint32_t insn)
8357 {
8358 return (insn & 0x1) == 0;
8359 }
8360
8361 static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
8362 CPUState *cs)
8363 {
8364 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8365 CPUTriCoreState *env = cs->env_ptr;
8366 ctx->mem_idx = cpu_mmu_index(env, false);
8367
8368 uint32_t tb_flags = (uint32_t)ctx->base.tb->flags;
8369 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
8370
8371 ctx->features = env->features;
8372 if (has_feature(ctx, TRICORE_FEATURE_161)) {
8373 ctx->icr_ie_mask = R_ICR_IE_161_MASK;
8374 ctx->icr_ie_offset = R_ICR_IE_161_SHIFT;
8375 } else {
8376 ctx->icr_ie_mask = R_ICR_IE_13_MASK;
8377 ctx->icr_ie_offset = R_ICR_IE_13_SHIFT;
8378 }
8379 }
8380
8381 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu)
8382 {
8383 }
8384
8385 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
8386 {
8387 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8388
8389 tcg_gen_insn_start(ctx->base.pc_next);
8390 }
8391
8392 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
8393 {
8394 /*
8395 * Return true if the insn at ctx->base.pc_next might cross a page boundary.
8396 * (False positives are OK, false negatives are not.)
8397 * Our caller ensures we are only called if dc->base.pc_next is less than
8398 * 4 bytes from the page boundary, so we cross the page if the first
8399 * 16 bits indicate that this is a 32 bit insn.
8400 */
8401 uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
8402
8403 return !tricore_insn_is_16bit(insn);
8404 }
8405
8406
8407 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
8408 {
8409 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8410 CPUTriCoreState *env = cpu->env_ptr;
8411 uint16_t insn_lo;
8412 bool is_16bit;
8413
8414 insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
8415 is_16bit = tricore_insn_is_16bit(insn_lo);
8416 if (is_16bit) {
8417 ctx->opcode = insn_lo;
8418 ctx->pc_succ_insn = ctx->base.pc_next + 2;
8419 decode_16Bit_opc(ctx);
8420 } else {
8421 uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
8422 ctx->opcode = insn_hi << 16 | insn_lo;
8423 ctx->pc_succ_insn = ctx->base.pc_next + 4;
8424 decode_32Bit_opc(ctx);
8425 }
8426 ctx->base.pc_next = ctx->pc_succ_insn;
8427
8428 if (ctx->base.is_jmp == DISAS_NEXT) {
8429 target_ulong page_start;
8430
8431 page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
8432 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE
8433 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3
8434 && insn_crosses_page(env, ctx))) {
8435 ctx->base.is_jmp = DISAS_TOO_MANY;
8436 }
8437 }
8438 }
8439
8440 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
8441 {
8442 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8443
8444 switch (ctx->base.is_jmp) {
8445 case DISAS_TOO_MANY:
8446 gen_goto_tb(ctx, 0, ctx->base.pc_next);
8447 break;
8448 case DISAS_EXIT_UPDATE:
8449 gen_save_pc(ctx->base.pc_next);
8450 /* fall through */
8451 case DISAS_EXIT:
8452 tcg_gen_exit_tb(NULL, 0);
8453 break;
8454 case DISAS_JUMP:
8455 tcg_gen_lookup_and_goto_ptr();
8456 break;
8457 case DISAS_NORETURN:
8458 break;
8459 default:
8460 g_assert_not_reached();
8461 }
8462 }
8463
8464 static void tricore_tr_disas_log(const DisasContextBase *dcbase,
8465 CPUState *cpu, FILE *logfile)
8466 {
8467 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
8468 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
8469 }
8470
8471 static const TranslatorOps tricore_tr_ops = {
8472 .init_disas_context = tricore_tr_init_disas_context,
8473 .tb_start = tricore_tr_tb_start,
8474 .insn_start = tricore_tr_insn_start,
8475 .translate_insn = tricore_tr_translate_insn,
8476 .tb_stop = tricore_tr_tb_stop,
8477 .disas_log = tricore_tr_disas_log,
8478 };
8479
8480
8481 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
8482 target_ulong pc, void *host_pc)
8483 {
8484 DisasContext ctx;
8485 translator_loop(cs, tb, max_insns, pc, host_pc,
8486 &tricore_tr_ops, &ctx.base);
8487 }
8488
8489 /*
8490 *
8491 * Initialization
8492 *
8493 */
8494
8495 void cpu_state_reset(CPUTriCoreState *env)
8496 {
8497 /* Reset Regs to Default Value */
8498 env->PSW = 0xb80;
8499 fpu_set_state(env);
8500 }
8501
8502 static void tricore_tcg_init_csfr(void)
8503 {
8504 cpu_PCXI = tcg_global_mem_new(cpu_env,
8505 offsetof(CPUTriCoreState, PCXI), "PCXI");
8506 cpu_PSW = tcg_global_mem_new(cpu_env,
8507 offsetof(CPUTriCoreState, PSW), "PSW");
8508 cpu_PC = tcg_global_mem_new(cpu_env,
8509 offsetof(CPUTriCoreState, PC), "PC");
8510 cpu_ICR = tcg_global_mem_new(cpu_env,
8511 offsetof(CPUTriCoreState, ICR), "ICR");
8512 }
8513
8514 void tricore_tcg_init(void)
8515 {
8516 int i;
8517
8518 /* reg init */
8519 for (i = 0 ; i < 16 ; i++) {
8520 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
8521 offsetof(CPUTriCoreState, gpr_a[i]),
8522 regnames_a[i]);
8523 }
8524 for (i = 0 ; i < 16 ; i++) {
8525 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
8526 offsetof(CPUTriCoreState, gpr_d[i]),
8527 regnames_d[i]);
8528 }
8529 tricore_tcg_init_csfr();
8530 /* init PSW flag cache */
8531 cpu_PSW_C = tcg_global_mem_new(cpu_env,
8532 offsetof(CPUTriCoreState, PSW_USB_C),
8533 "PSW_C");
8534 cpu_PSW_V = tcg_global_mem_new(cpu_env,
8535 offsetof(CPUTriCoreState, PSW_USB_V),
8536 "PSW_V");
8537 cpu_PSW_SV = tcg_global_mem_new(cpu_env,
8538 offsetof(CPUTriCoreState, PSW_USB_SV),
8539 "PSW_SV");
8540 cpu_PSW_AV = tcg_global_mem_new(cpu_env,
8541 offsetof(CPUTriCoreState, PSW_USB_AV),
8542 "PSW_AV");
8543 cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
8544 offsetof(CPUTriCoreState, PSW_USB_SAV),
8545 "PSW_SAV");
8546 }
QEMU mirror