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target/tricore: Fix RR_JLI clobbering reg A[11]
[mirror_qemu.git] / target / tricore / translate.c
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "exec/cpu_ldst.h"
27 #include "qemu/qemu-print.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "tricore-opcodes.h"
33 #include "exec/translator.h"
34 #include "exec/log.h"
35
36 #define HELPER_H "helper.h"
37 #include "exec/helper-info.c.inc"
38 #undef HELPER_H
39
40
41 /*
42 * TCG registers
43 */
44 static TCGv cpu_PC;
45 static TCGv cpu_PCXI;
46 static TCGv cpu_PSW;
47 static TCGv cpu_ICR;
48 /* GPR registers */
49 static TCGv cpu_gpr_a[16];
50 static TCGv cpu_gpr_d[16];
51 /* PSW Flag cache */
52 static TCGv cpu_PSW_C;
53 static TCGv cpu_PSW_V;
54 static TCGv cpu_PSW_SV;
55 static TCGv cpu_PSW_AV;
56 static TCGv cpu_PSW_SAV;
57
58 static const char *regnames_a[] = {
59 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
60 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
61 "a12" , "a13" , "a14" , "a15",
62 };
63
64 static const char *regnames_d[] = {
65 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
66 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
67 "d12" , "d13" , "d14" , "d15",
68 };
69
70 typedef struct DisasContext {
71 DisasContextBase base;
72 target_ulong pc_succ_insn;
73 uint32_t opcode;
74 /* Routine used to access memory */
75 int mem_idx;
76 uint32_t hflags, saved_hflags;
77 uint64_t features;
78 uint32_t icr_ie_mask, icr_ie_offset;
79 } DisasContext;
80
81 static int has_feature(DisasContext *ctx, int feature)
82 {
83 return (ctx->features & (1ULL << feature)) != 0;
84 }
85
86 enum {
87 MODE_LL = 0,
88 MODE_LU = 1,
89 MODE_UL = 2,
90 MODE_UU = 3,
91 };
92
93 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
94 {
95 TriCoreCPU *cpu = TRICORE_CPU(cs);
96 CPUTriCoreState *env = &cpu->env;
97 uint32_t psw;
98 int i;
99
100 psw = psw_read(env);
101
102 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
103 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
104 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
105 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
106 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
107 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
108
109 for (i = 0; i < 16; ++i) {
110 if ((i & 3) == 0) {
111 qemu_fprintf(f, "\nGPR A%02d:", i);
112 }
113 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
114 }
115 for (i = 0; i < 16; ++i) {
116 if ((i & 3) == 0) {
117 qemu_fprintf(f, "\nGPR D%02d:", i);
118 }
119 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
120 }
121 qemu_fprintf(f, "\n");
122 }
123
124 /*
125 * Functions to generate micro-ops
126 */
127
128 /* Makros for generating helpers */
129
130 #define gen_helper_1arg(name, arg) do { \
131 TCGv_i32 helper_tmp = tcg_constant_i32(arg); \
132 gen_helper_##name(cpu_env, helper_tmp); \
133 } while (0)
134
135 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
136 TCGv arg00 = tcg_temp_new(); \
137 TCGv arg01 = tcg_temp_new(); \
138 TCGv arg11 = tcg_temp_new(); \
139 tcg_gen_sari_tl(arg00, arg0, 16); \
140 tcg_gen_ext16s_tl(arg01, arg0); \
141 tcg_gen_ext16s_tl(arg11, arg1); \
142 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
143 } while (0)
144
145 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
146 TCGv arg00 = tcg_temp_new(); \
147 TCGv arg01 = tcg_temp_new(); \
148 TCGv arg10 = tcg_temp_new(); \
149 TCGv arg11 = tcg_temp_new(); \
150 tcg_gen_sari_tl(arg00, arg0, 16); \
151 tcg_gen_ext16s_tl(arg01, arg0); \
152 tcg_gen_sari_tl(arg11, arg1, 16); \
153 tcg_gen_ext16s_tl(arg10, arg1); \
154 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
155 } while (0)
156
157 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
158 TCGv arg00 = tcg_temp_new(); \
159 TCGv arg01 = tcg_temp_new(); \
160 TCGv arg10 = tcg_temp_new(); \
161 TCGv arg11 = tcg_temp_new(); \
162 tcg_gen_sari_tl(arg00, arg0, 16); \
163 tcg_gen_ext16s_tl(arg01, arg0); \
164 tcg_gen_sari_tl(arg10, arg1, 16); \
165 tcg_gen_ext16s_tl(arg11, arg1); \
166 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
167 } while (0)
168
169 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
170 TCGv arg00 = tcg_temp_new(); \
171 TCGv arg01 = tcg_temp_new(); \
172 TCGv arg11 = tcg_temp_new(); \
173 tcg_gen_sari_tl(arg01, arg0, 16); \
174 tcg_gen_ext16s_tl(arg00, arg0); \
175 tcg_gen_sari_tl(arg11, arg1, 16); \
176 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
177 } while (0)
178
179 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
180 TCGv_i64 ret = tcg_temp_new_i64(); \
181 TCGv_i64 arg1 = tcg_temp_new_i64(); \
182 \
183 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
184 gen_helper_##name(ret, arg1, arg2); \
185 tcg_gen_extr_i64_i32(rl, rh, ret); \
186 } while (0)
187
188 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
189 TCGv_i64 ret = tcg_temp_new_i64(); \
190 \
191 gen_helper_##name(ret, cpu_env, arg1, arg2); \
192 tcg_gen_extr_i64_i32(rl, rh, ret); \
193 } while (0)
194
195 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
196 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
197 ((offset & 0x0fffff) << 1))
198
199 /* For two 32-bit registers used a 64-bit register, the first
200 registernumber needs to be even. Otherwise we trap. */
201 static inline void generate_trap(DisasContext *ctx, int class, int tin);
202 #define CHECK_REG_PAIR(reg) do { \
203 if (reg & 0x1) { \
204 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
205 } \
206 } while (0)
207
208 /* Functions for load/save to/from memory */
209
210 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
211 int16_t con, MemOp mop)
212 {
213 TCGv temp = tcg_temp_new();
214 tcg_gen_addi_tl(temp, r2, con);
215 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
216 }
217
218 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
219 int16_t con, MemOp mop)
220 {
221 TCGv temp = tcg_temp_new();
222 tcg_gen_addi_tl(temp, r2, con);
223 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
224 }
225
226 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
227 {
228 TCGv_i64 temp = tcg_temp_new_i64();
229
230 tcg_gen_concat_i32_i64(temp, rl, rh);
231 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ);
232 }
233
234 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
235 DisasContext *ctx)
236 {
237 TCGv temp = tcg_temp_new();
238 tcg_gen_addi_tl(temp, base, con);
239 gen_st_2regs_64(rh, rl, temp, ctx);
240 }
241
242 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
243 {
244 TCGv_i64 temp = tcg_temp_new_i64();
245
246 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ);
247 /* write back to two 32 bit regs */
248 tcg_gen_extr_i64_i32(rl, rh, temp);
249 }
250
251 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
252 DisasContext *ctx)
253 {
254 TCGv temp = tcg_temp_new();
255 tcg_gen_addi_tl(temp, base, con);
256 gen_ld_2regs_64(rh, rl, temp, ctx);
257 }
258
259 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
260 MemOp mop)
261 {
262 TCGv temp = tcg_temp_new();
263 tcg_gen_addi_tl(temp, r2, off);
264 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
265 tcg_gen_mov_tl(r2, temp);
266 }
267
268 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
269 MemOp mop)
270 {
271 TCGv temp = tcg_temp_new();
272 tcg_gen_addi_tl(temp, r2, off);
273 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
274 tcg_gen_mov_tl(r2, temp);
275 }
276
277 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
278 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
279 {
280 TCGv temp = tcg_temp_new();
281 TCGv temp2 = tcg_temp_new();
282
283 CHECK_REG_PAIR(ereg);
284 /* temp = (M(EA, word) */
285 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
286 /* temp = temp & ~E[a][63:32]) */
287 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
288 /* temp2 = (E[a][31:0] & E[a][63:32]); */
289 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
290 /* temp = temp | temp2; */
291 tcg_gen_or_tl(temp, temp, temp2);
292 /* M(EA, word) = temp; */
293 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
294 }
295
296 /* tmp = M(EA, word);
297 M(EA, word) = D[a];
298 D[a] = tmp[31:0];*/
299 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
300 {
301 TCGv temp = tcg_temp_new();
302
303 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
304 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
305 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
306 }
307
308 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
309 {
310 TCGv temp = tcg_temp_new();
311 TCGv temp2 = tcg_temp_new();
312 CHECK_REG_PAIR(reg);
313 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
314 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
315 cpu_gpr_d[reg], temp);
316 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
317 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
318 }
319
320 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
321 {
322 TCGv temp = tcg_temp_new();
323 TCGv temp2 = tcg_temp_new();
324 TCGv temp3 = tcg_temp_new();
325 CHECK_REG_PAIR(reg);
326 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
327 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
328 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
329 tcg_gen_or_tl(temp2, temp2, temp3);
330 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
331 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
332 }
333
334
335 /* We generate loads and store to core special function register (csfr) through
336 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
337 makros R, A and E, which allow read-only, all and endinit protected access.
338 These makros also specify in which ISA version the csfr was introduced. */
339 #define R(ADDRESS, REG, FEATURE) \
340 case ADDRESS: \
341 if (has_feature(ctx, FEATURE)) { \
342 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
343 } \
344 break;
345 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
346 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
347 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
348 {
349 /* since we're caching PSW make this a special case */
350 if (offset == 0xfe04) {
351 gen_helper_psw_read(ret, cpu_env);
352 } else {
353 switch (offset) {
354 #include "csfr.h.inc"
355 }
356 }
357 }
358 #undef R
359 #undef A
360 #undef E
361
362 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
363 since no execption occurs */
364 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
365 case ADDRESS: \
366 if (has_feature(ctx, FEATURE)) { \
367 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
368 } \
369 break;
370 /* Endinit protected registers
371 TODO: Since the endinit bit is in a register of a not yet implemented
372 watchdog device, we handle endinit protected registers like
373 all-access registers for now. */
374 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
375 static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
376 int32_t offset)
377 {
378 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
379 /* since we're caching PSW make this a special case */
380 if (offset == 0xfe04) {
381 gen_helper_psw_write(cpu_env, r1);
382 } else {
383 switch (offset) {
384 #include "csfr.h.inc"
385 }
386 }
387 } else {
388 /* generate privilege trap */
389 }
390 }
391
392 /* Functions for arithmetic instructions */
393
394 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
395 {
396 TCGv t0 = tcg_temp_new_i32();
397 TCGv result = tcg_temp_new_i32();
398 /* Addition and set V/SV bits */
399 tcg_gen_add_tl(result, r1, r2);
400 /* calc V bit */
401 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
402 tcg_gen_xor_tl(t0, r1, r2);
403 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
404 /* Calc SV bit */
405 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
406 /* Calc AV/SAV bits */
407 tcg_gen_add_tl(cpu_PSW_AV, result, result);
408 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
409 /* calc SAV */
410 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
411 /* write back result */
412 tcg_gen_mov_tl(ret, result);
413 }
414
415 static inline void
416 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
417 {
418 TCGv temp = tcg_temp_new();
419 TCGv_i64 t0 = tcg_temp_new_i64();
420 TCGv_i64 t1 = tcg_temp_new_i64();
421 TCGv_i64 result = tcg_temp_new_i64();
422
423 tcg_gen_add_i64(result, r1, r2);
424 /* calc v bit */
425 tcg_gen_xor_i64(t1, result, r1);
426 tcg_gen_xor_i64(t0, r1, r2);
427 tcg_gen_andc_i64(t1, t1, t0);
428 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
429 /* calc SV bit */
430 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
431 /* calc AV/SAV bits */
432 tcg_gen_extrh_i64_i32(temp, result);
433 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
434 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
435 /* calc SAV */
436 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
437 /* write back result */
438 tcg_gen_mov_i64(ret, result);
439 }
440
441 static inline void
442 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
443 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
444 void(*op2)(TCGv, TCGv, TCGv))
445 {
446 TCGv temp = tcg_temp_new();
447 TCGv temp2 = tcg_temp_new();
448 TCGv temp3 = tcg_temp_new();
449 TCGv temp4 = tcg_temp_new();
450
451 (*op1)(temp, r1_low, r2);
452 /* calc V0 bit */
453 tcg_gen_xor_tl(temp2, temp, r1_low);
454 tcg_gen_xor_tl(temp3, r1_low, r2);
455 if (op1 == tcg_gen_add_tl) {
456 tcg_gen_andc_tl(temp2, temp2, temp3);
457 } else {
458 tcg_gen_and_tl(temp2, temp2, temp3);
459 }
460
461 (*op2)(temp3, r1_high, r3);
462 /* calc V1 bit */
463 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
464 tcg_gen_xor_tl(temp4, r1_high, r3);
465 if (op2 == tcg_gen_add_tl) {
466 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
467 } else {
468 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
469 }
470 /* combine V0/V1 bits */
471 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
472 /* calc sv bit */
473 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
474 /* write result */
475 tcg_gen_mov_tl(ret_low, temp);
476 tcg_gen_mov_tl(ret_high, temp3);
477 /* calc AV bit */
478 tcg_gen_add_tl(temp, ret_low, ret_low);
479 tcg_gen_xor_tl(temp, temp, ret_low);
480 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
481 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
482 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
483 /* calc SAV bit */
484 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
485 }
486
487 /* ret = r2 + (r1 * r3); */
488 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
489 {
490 TCGv_i64 t1 = tcg_temp_new_i64();
491 TCGv_i64 t2 = tcg_temp_new_i64();
492 TCGv_i64 t3 = tcg_temp_new_i64();
493
494 tcg_gen_ext_i32_i64(t1, r1);
495 tcg_gen_ext_i32_i64(t2, r2);
496 tcg_gen_ext_i32_i64(t3, r3);
497
498 tcg_gen_mul_i64(t1, t1, t3);
499 tcg_gen_add_i64(t1, t2, t1);
500
501 tcg_gen_extrl_i64_i32(ret, t1);
502 /* calc V
503 t1 > 0x7fffffff */
504 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
505 /* t1 < -0x80000000 */
506 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
507 tcg_gen_or_i64(t2, t2, t3);
508 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
509 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
510 /* Calc SV bit */
511 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
512 /* Calc AV/SAV bits */
513 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
514 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
515 /* calc SAV */
516 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
517 }
518
519 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
520 {
521 TCGv temp = tcg_constant_i32(con);
522 gen_madd32_d(ret, r1, r2, temp);
523 }
524
525 static inline void
526 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
527 TCGv r3)
528 {
529 TCGv t1 = tcg_temp_new();
530 TCGv t2 = tcg_temp_new();
531 TCGv t3 = tcg_temp_new();
532 TCGv t4 = tcg_temp_new();
533
534 tcg_gen_muls2_tl(t1, t2, r1, r3);
535 /* only the add can overflow */
536 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
537 /* calc V bit */
538 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
539 tcg_gen_xor_tl(t1, r2_high, t2);
540 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
541 /* Calc SV bit */
542 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
543 /* Calc AV/SAV bits */
544 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
545 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
546 /* calc SAV */
547 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
548 /* write back the result */
549 tcg_gen_mov_tl(ret_low, t3);
550 tcg_gen_mov_tl(ret_high, t4);
551 }
552
553 static inline void
554 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
555 TCGv r3)
556 {
557 TCGv_i64 t1 = tcg_temp_new_i64();
558 TCGv_i64 t2 = tcg_temp_new_i64();
559 TCGv_i64 t3 = tcg_temp_new_i64();
560
561 tcg_gen_extu_i32_i64(t1, r1);
562 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
563 tcg_gen_extu_i32_i64(t3, r3);
564
565 tcg_gen_mul_i64(t1, t1, t3);
566 tcg_gen_add_i64(t2, t2, t1);
567 /* write back result */
568 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
569 /* only the add overflows, if t2 < t1
570 calc V bit */
571 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
572 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
573 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
574 /* Calc SV bit */
575 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
576 /* Calc AV/SAV bits */
577 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
578 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
579 /* calc SAV */
580 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
581 }
582
583 static inline void
584 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
585 int32_t con)
586 {
587 TCGv temp = tcg_constant_i32(con);
588 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
589 }
590
591 static inline void
592 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
593 int32_t con)
594 {
595 TCGv temp = tcg_constant_i32(con);
596 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
597 }
598
599 static inline void
600 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
601 TCGv r3, uint32_t n, uint32_t mode)
602 {
603 TCGv t_n = tcg_constant_i32(n);
604 TCGv temp = tcg_temp_new();
605 TCGv temp2 = tcg_temp_new();
606 TCGv_i64 temp64 = tcg_temp_new_i64();
607 switch (mode) {
608 case MODE_LL:
609 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
610 break;
611 case MODE_LU:
612 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
613 break;
614 case MODE_UL:
615 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
616 break;
617 case MODE_UU:
618 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
619 break;
620 }
621 tcg_gen_extr_i64_i32(temp, temp2, temp64);
622 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
623 tcg_gen_add_tl, tcg_gen_add_tl);
624 }
625
626 static inline void
627 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
628 TCGv r3, uint32_t n, uint32_t mode)
629 {
630 TCGv t_n = tcg_constant_i32(n);
631 TCGv temp = tcg_temp_new();
632 TCGv temp2 = tcg_temp_new();
633 TCGv_i64 temp64 = tcg_temp_new_i64();
634 switch (mode) {
635 case MODE_LL:
636 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
637 break;
638 case MODE_LU:
639 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
640 break;
641 case MODE_UL:
642 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
643 break;
644 case MODE_UU:
645 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
646 break;
647 }
648 tcg_gen_extr_i64_i32(temp, temp2, temp64);
649 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
650 tcg_gen_sub_tl, tcg_gen_add_tl);
651 }
652
653 static inline void
654 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
655 TCGv r3, uint32_t n, uint32_t mode)
656 {
657 TCGv t_n = tcg_constant_i32(n);
658 TCGv_i64 temp64 = tcg_temp_new_i64();
659 TCGv_i64 temp64_2 = tcg_temp_new_i64();
660 TCGv_i64 temp64_3 = tcg_temp_new_i64();
661 switch (mode) {
662 case MODE_LL:
663 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
664 break;
665 case MODE_LU:
666 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
667 break;
668 case MODE_UL:
669 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
670 break;
671 case MODE_UU:
672 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
673 break;
674 }
675 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
676 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
677 tcg_gen_ext32s_i64(temp64, temp64); /* low */
678 tcg_gen_sub_i64(temp64, temp64_2, temp64);
679 tcg_gen_shli_i64(temp64, temp64, 16);
680
681 gen_add64_d(temp64_2, temp64_3, temp64);
682 /* write back result */
683 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
684 }
685
686 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
687
688 static inline void
689 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
690 TCGv r3, uint32_t n, uint32_t mode)
691 {
692 TCGv t_n = tcg_constant_i32(n);
693 TCGv temp = tcg_temp_new();
694 TCGv temp2 = tcg_temp_new();
695 TCGv temp3 = tcg_temp_new();
696 TCGv_i64 temp64 = tcg_temp_new_i64();
697
698 switch (mode) {
699 case MODE_LL:
700 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
701 break;
702 case MODE_LU:
703 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
704 break;
705 case MODE_UL:
706 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
707 break;
708 case MODE_UU:
709 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
710 break;
711 }
712 tcg_gen_extr_i64_i32(temp, temp2, temp64);
713 gen_adds(ret_low, r1_low, temp);
714 tcg_gen_mov_tl(temp, cpu_PSW_V);
715 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
716 gen_adds(ret_high, r1_high, temp2);
717 /* combine v bits */
718 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
719 /* combine av bits */
720 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
721 }
722
723 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
724
725 static inline void
726 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
727 TCGv r3, uint32_t n, uint32_t mode)
728 {
729 TCGv t_n = tcg_constant_i32(n);
730 TCGv temp = tcg_temp_new();
731 TCGv temp2 = tcg_temp_new();
732 TCGv temp3 = tcg_temp_new();
733 TCGv_i64 temp64 = tcg_temp_new_i64();
734
735 switch (mode) {
736 case MODE_LL:
737 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
738 break;
739 case MODE_LU:
740 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
741 break;
742 case MODE_UL:
743 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
744 break;
745 case MODE_UU:
746 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
747 break;
748 }
749 tcg_gen_extr_i64_i32(temp, temp2, temp64);
750 gen_subs(ret_low, r1_low, temp);
751 tcg_gen_mov_tl(temp, cpu_PSW_V);
752 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
753 gen_adds(ret_high, r1_high, temp2);
754 /* combine v bits */
755 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
756 /* combine av bits */
757 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
758 }
759
760 static inline void
761 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
762 TCGv r3, uint32_t n, uint32_t mode)
763 {
764 TCGv t_n = tcg_constant_i32(n);
765 TCGv_i64 temp64 = tcg_temp_new_i64();
766 TCGv_i64 temp64_2 = tcg_temp_new_i64();
767
768 switch (mode) {
769 case MODE_LL:
770 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
771 break;
772 case MODE_LU:
773 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
774 break;
775 case MODE_UL:
776 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
777 break;
778 case MODE_UU:
779 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
780 break;
781 }
782 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
783 tcg_gen_ext32s_i64(temp64, temp64); /* low */
784 tcg_gen_sub_i64(temp64, temp64_2, temp64);
785 tcg_gen_shli_i64(temp64, temp64, 16);
786 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
787
788 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
789 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
790 }
791
792
793 static inline void
794 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
795 TCGv r3, uint32_t n, uint32_t mode)
796 {
797 TCGv t_n = tcg_constant_i32(n);
798 TCGv_i64 temp64 = tcg_temp_new_i64();
799 TCGv_i64 temp64_2 = tcg_temp_new_i64();
800 TCGv_i64 temp64_3 = tcg_temp_new_i64();
801 switch (mode) {
802 case MODE_LL:
803 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
804 break;
805 case MODE_LU:
806 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
807 break;
808 case MODE_UL:
809 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
810 break;
811 case MODE_UU:
812 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
813 break;
814 }
815 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
816 gen_add64_d(temp64_3, temp64_2, temp64);
817 /* write back result */
818 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
819 }
820
821 static inline void
822 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
823 TCGv r3, uint32_t n, uint32_t mode)
824 {
825 TCGv t_n = tcg_constant_i32(n);
826 TCGv_i64 temp64 = tcg_temp_new_i64();
827 TCGv_i64 temp64_2 = tcg_temp_new_i64();
828 switch (mode) {
829 case MODE_LL:
830 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
831 break;
832 case MODE_LU:
833 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
834 break;
835 case MODE_UL:
836 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
837 break;
838 case MODE_UU:
839 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
840 break;
841 }
842 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
843 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
844 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
845 }
846
847 static inline void
848 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
849 uint32_t mode)
850 {
851 TCGv t_n = tcg_constant_i32(n);
852 TCGv_i64 temp64 = tcg_temp_new_i64();
853 switch (mode) {
854 case MODE_LL:
855 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
856 break;
857 case MODE_LU:
858 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
859 break;
860 case MODE_UL:
861 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
862 break;
863 case MODE_UU:
864 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
865 break;
866 }
867 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
868 }
869
870 static inline void
871 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
872 {
873 TCGv temp = tcg_temp_new();
874 TCGv temp2 = tcg_temp_new();
875
876 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
877 tcg_gen_shli_tl(temp, r1, 16);
878 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
879 }
880
881 static inline void
882 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
883 {
884 TCGv t_n = tcg_constant_i32(n);
885 TCGv temp = tcg_temp_new();
886 TCGv temp2 = tcg_temp_new();
887 TCGv_i64 temp64 = tcg_temp_new_i64();
888 switch (mode) {
889 case MODE_LL:
890 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
891 break;
892 case MODE_LU:
893 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
894 break;
895 case MODE_UL:
896 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
897 break;
898 case MODE_UU:
899 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
900 break;
901 }
902 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
903 tcg_gen_shli_tl(temp, r1, 16);
904 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
905 }
906
907
908 static inline void
909 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
910 uint32_t n, uint32_t mode)
911 {
912 TCGv t_n = tcg_constant_i32(n);
913 TCGv_i64 temp64 = tcg_temp_new_i64();
914 switch (mode) {
915 case MODE_LL:
916 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
917 break;
918 case MODE_LU:
919 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
920 break;
921 case MODE_UL:
922 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
923 break;
924 case MODE_UU:
925 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
926 break;
927 }
928 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
929 }
930
931 static inline void
932 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
933 {
934 TCGv temp = tcg_temp_new();
935 TCGv temp2 = tcg_temp_new();
936
937 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
938 tcg_gen_shli_tl(temp, r1, 16);
939 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
940 }
941
942 static inline void
943 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
944 {
945 TCGv t_n = tcg_constant_i32(n);
946 TCGv temp = tcg_temp_new();
947 TCGv temp2 = tcg_temp_new();
948 TCGv_i64 temp64 = tcg_temp_new_i64();
949 switch (mode) {
950 case MODE_LL:
951 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
952 break;
953 case MODE_LU:
954 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
955 break;
956 case MODE_UL:
957 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
958 break;
959 case MODE_UU:
960 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
961 break;
962 }
963 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
964 tcg_gen_shli_tl(temp, r1, 16);
965 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
966 }
967
968 static inline void
969 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
970 {
971 TCGv t_n = tcg_constant_i32(n);
972 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n);
973 }
974
975 static inline void
976 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
977 {
978 TCGv t_n = tcg_constant_i32(n);
979 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n);
980 }
981
982 static inline void
983 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
984 uint32_t up_shift)
985 {
986 TCGv temp = tcg_temp_new();
987 TCGv temp2 = tcg_temp_new();
988 TCGv temp3 = tcg_temp_new();
989 TCGv_i64 t1 = tcg_temp_new_i64();
990 TCGv_i64 t2 = tcg_temp_new_i64();
991 TCGv_i64 t3 = tcg_temp_new_i64();
992
993 tcg_gen_ext_i32_i64(t2, arg2);
994 tcg_gen_ext_i32_i64(t3, arg3);
995
996 tcg_gen_mul_i64(t2, t2, t3);
997 tcg_gen_shli_i64(t2, t2, n);
998
999 tcg_gen_ext_i32_i64(t1, arg1);
1000 tcg_gen_sari_i64(t2, t2, up_shift);
1001
1002 tcg_gen_add_i64(t3, t1, t2);
1003 tcg_gen_extrl_i64_i32(temp3, t3);
1004 /* calc v bit */
1005 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1006 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1007 tcg_gen_or_i64(t1, t1, t2);
1008 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1009 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1010 /* We produce an overflow on the host if the mul before was
1011 (0x80000000 * 0x80000000) << 1). If this is the
1012 case, we negate the ovf. */
1013 if (n == 1) {
1014 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1015 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1016 tcg_gen_and_tl(temp, temp, temp2);
1017 tcg_gen_shli_tl(temp, temp, 31);
1018 /* negate v bit, if special condition */
1019 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1020 }
1021 /* Calc SV bit */
1022 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1023 /* Calc AV/SAV bits */
1024 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1025 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1026 /* calc SAV */
1027 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1028 /* write back result */
1029 tcg_gen_mov_tl(ret, temp3);
1030 }
1031
1032 static inline void
1033 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1034 {
1035 TCGv temp = tcg_temp_new();
1036 TCGv temp2 = tcg_temp_new();
1037 if (n == 0) {
1038 tcg_gen_mul_tl(temp, arg2, arg3);
1039 } else { /* n is expected to be 1 */
1040 tcg_gen_mul_tl(temp, arg2, arg3);
1041 tcg_gen_shli_tl(temp, temp, 1);
1042 /* catch special case r1 = r2 = 0x8000 */
1043 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1044 tcg_gen_sub_tl(temp, temp, temp2);
1045 }
1046 gen_add_d(ret, arg1, temp);
1047 }
1048
1049 static inline void
1050 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1051 {
1052 TCGv temp = tcg_temp_new();
1053 TCGv temp2 = tcg_temp_new();
1054 if (n == 0) {
1055 tcg_gen_mul_tl(temp, arg2, arg3);
1056 } else { /* n is expected to be 1 */
1057 tcg_gen_mul_tl(temp, arg2, arg3);
1058 tcg_gen_shli_tl(temp, temp, 1);
1059 /* catch special case r1 = r2 = 0x8000 */
1060 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1061 tcg_gen_sub_tl(temp, temp, temp2);
1062 }
1063 gen_adds(ret, arg1, temp);
1064 }
1065
1066 static inline void
1067 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1068 TCGv arg3, uint32_t n)
1069 {
1070 TCGv temp = tcg_temp_new();
1071 TCGv temp2 = tcg_temp_new();
1072 TCGv_i64 t1 = tcg_temp_new_i64();
1073 TCGv_i64 t2 = tcg_temp_new_i64();
1074 TCGv_i64 t3 = tcg_temp_new_i64();
1075
1076 if (n == 0) {
1077 tcg_gen_mul_tl(temp, arg2, arg3);
1078 } else { /* n is expected to be 1 */
1079 tcg_gen_mul_tl(temp, arg2, arg3);
1080 tcg_gen_shli_tl(temp, temp, 1);
1081 /* catch special case r1 = r2 = 0x8000 */
1082 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1083 tcg_gen_sub_tl(temp, temp, temp2);
1084 }
1085 tcg_gen_ext_i32_i64(t2, temp);
1086 tcg_gen_shli_i64(t2, t2, 16);
1087 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1088 gen_add64_d(t3, t1, t2);
1089 /* write back result */
1090 tcg_gen_extr_i64_i32(rl, rh, t3);
1091 }
1092
1093 static inline void
1094 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1095 TCGv arg3, uint32_t n)
1096 {
1097 TCGv temp = tcg_temp_new();
1098 TCGv temp2 = tcg_temp_new();
1099 TCGv_i64 t1 = tcg_temp_new_i64();
1100 TCGv_i64 t2 = tcg_temp_new_i64();
1101
1102 if (n == 0) {
1103 tcg_gen_mul_tl(temp, arg2, arg3);
1104 } else { /* n is expected to be 1 */
1105 tcg_gen_mul_tl(temp, arg2, arg3);
1106 tcg_gen_shli_tl(temp, temp, 1);
1107 /* catch special case r1 = r2 = 0x8000 */
1108 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1109 tcg_gen_sub_tl(temp, temp, temp2);
1110 }
1111 tcg_gen_ext_i32_i64(t2, temp);
1112 tcg_gen_shli_i64(t2, t2, 16);
1113 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1114
1115 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1116 tcg_gen_extr_i64_i32(rl, rh, t1);
1117 }
1118
1119 static inline void
1120 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1121 TCGv arg3, uint32_t n)
1122 {
1123 TCGv_i64 t1 = tcg_temp_new_i64();
1124 TCGv_i64 t2 = tcg_temp_new_i64();
1125 TCGv_i64 t3 = tcg_temp_new_i64();
1126 TCGv_i64 t4 = tcg_temp_new_i64();
1127 TCGv temp, temp2;
1128
1129 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1130 tcg_gen_ext_i32_i64(t2, arg2);
1131 tcg_gen_ext_i32_i64(t3, arg3);
1132
1133 tcg_gen_mul_i64(t2, t2, t3);
1134 if (n != 0) {
1135 tcg_gen_shli_i64(t2, t2, 1);
1136 }
1137 tcg_gen_add_i64(t4, t1, t2);
1138 /* calc v bit */
1139 tcg_gen_xor_i64(t3, t4, t1);
1140 tcg_gen_xor_i64(t2, t1, t2);
1141 tcg_gen_andc_i64(t3, t3, t2);
1142 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1143 /* We produce an overflow on the host if the mul before was
1144 (0x80000000 * 0x80000000) << 1). If this is the
1145 case, we negate the ovf. */
1146 if (n == 1) {
1147 temp = tcg_temp_new();
1148 temp2 = tcg_temp_new();
1149 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1150 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1151 tcg_gen_and_tl(temp, temp, temp2);
1152 tcg_gen_shli_tl(temp, temp, 31);
1153 /* negate v bit, if special condition */
1154 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1155 }
1156 /* write back result */
1157 tcg_gen_extr_i64_i32(rl, rh, t4);
1158 /* Calc SV bit */
1159 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1160 /* Calc AV/SAV bits */
1161 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1162 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1163 /* calc SAV */
1164 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1165 }
1166
1167 static inline void
1168 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1169 uint32_t up_shift)
1170 {
1171 TCGv_i64 t1 = tcg_temp_new_i64();
1172 TCGv_i64 t2 = tcg_temp_new_i64();
1173 TCGv_i64 t3 = tcg_temp_new_i64();
1174
1175 tcg_gen_ext_i32_i64(t1, arg1);
1176 tcg_gen_ext_i32_i64(t2, arg2);
1177 tcg_gen_ext_i32_i64(t3, arg3);
1178
1179 tcg_gen_mul_i64(t2, t2, t3);
1180 tcg_gen_sari_i64(t2, t2, up_shift - n);
1181
1182 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1183 }
1184
1185 static inline void
1186 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1187 TCGv arg3, uint32_t n)
1188 {
1189 TCGv_i64 r1 = tcg_temp_new_i64();
1190 TCGv t_n = tcg_constant_i32(n);
1191
1192 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1193 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
1194 tcg_gen_extr_i64_i32(rl, rh, r1);
1195 }
1196
1197 /* ret = r2 - (r1 * r3); */
1198 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1199 {
1200 TCGv_i64 t1 = tcg_temp_new_i64();
1201 TCGv_i64 t2 = tcg_temp_new_i64();
1202 TCGv_i64 t3 = tcg_temp_new_i64();
1203
1204 tcg_gen_ext_i32_i64(t1, r1);
1205 tcg_gen_ext_i32_i64(t2, r2);
1206 tcg_gen_ext_i32_i64(t3, r3);
1207
1208 tcg_gen_mul_i64(t1, t1, t3);
1209 tcg_gen_sub_i64(t1, t2, t1);
1210
1211 tcg_gen_extrl_i64_i32(ret, t1);
1212 /* calc V
1213 t2 > 0x7fffffff */
1214 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1215 /* result < -0x80000000 */
1216 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1217 tcg_gen_or_i64(t2, t2, t3);
1218 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
1219 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1220
1221 /* Calc SV bit */
1222 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1223 /* Calc AV/SAV bits */
1224 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1225 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1226 /* calc SAV */
1227 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1228 }
1229
1230 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1231 {
1232 TCGv temp = tcg_constant_i32(con);
1233 gen_msub32_d(ret, r1, r2, temp);
1234 }
1235
1236 static inline void
1237 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1238 TCGv r3)
1239 {
1240 TCGv t1 = tcg_temp_new();
1241 TCGv t2 = tcg_temp_new();
1242 TCGv t3 = tcg_temp_new();
1243 TCGv t4 = tcg_temp_new();
1244
1245 tcg_gen_muls2_tl(t1, t2, r1, r3);
1246 /* only the sub can overflow */
1247 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1248 /* calc V bit */
1249 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1250 tcg_gen_xor_tl(t1, r2_high, t2);
1251 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1252 /* Calc SV bit */
1253 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1254 /* Calc AV/SAV bits */
1255 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1256 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1257 /* calc SAV */
1258 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1259 /* write back the result */
1260 tcg_gen_mov_tl(ret_low, t3);
1261 tcg_gen_mov_tl(ret_high, t4);
1262 }
1263
1264 static inline void
1265 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1266 int32_t con)
1267 {
1268 TCGv temp = tcg_constant_i32(con);
1269 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1270 }
1271
1272 static inline void
1273 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1274 TCGv r3)
1275 {
1276 TCGv_i64 t1 = tcg_temp_new_i64();
1277 TCGv_i64 t2 = tcg_temp_new_i64();
1278 TCGv_i64 t3 = tcg_temp_new_i64();
1279
1280 tcg_gen_extu_i32_i64(t1, r1);
1281 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1282 tcg_gen_extu_i32_i64(t3, r3);
1283
1284 tcg_gen_mul_i64(t1, t1, t3);
1285 tcg_gen_sub_i64(t3, t2, t1);
1286 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1287 /* calc V bit, only the sub can overflow, if t1 > t2 */
1288 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1289 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1290 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1291 /* Calc SV bit */
1292 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1293 /* Calc AV/SAV bits */
1294 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1295 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1296 /* calc SAV */
1297 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1298 }
1299
1300 static inline void
1301 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1302 int32_t con)
1303 {
1304 TCGv temp = tcg_constant_i32(con);
1305 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1306 }
1307
1308 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1309 {
1310 TCGv temp = tcg_constant_i32(r2);
1311 gen_add_d(ret, r1, temp);
1312 }
1313
1314 /* calculate the carry bit too */
1315 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1316 {
1317 TCGv t0 = tcg_temp_new_i32();
1318 TCGv result = tcg_temp_new_i32();
1319
1320 tcg_gen_movi_tl(t0, 0);
1321 /* Addition and set C/V/SV bits */
1322 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1323 /* calc V bit */
1324 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1325 tcg_gen_xor_tl(t0, r1, r2);
1326 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1327 /* Calc SV bit */
1328 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1329 /* Calc AV/SAV bits */
1330 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1331 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1332 /* calc SAV */
1333 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1334 /* write back result */
1335 tcg_gen_mov_tl(ret, result);
1336 }
1337
1338 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1339 {
1340 TCGv temp = tcg_constant_i32(con);
1341 gen_add_CC(ret, r1, temp);
1342 }
1343
1344 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1345 {
1346 TCGv carry = tcg_temp_new_i32();
1347 TCGv t0 = tcg_temp_new_i32();
1348 TCGv result = tcg_temp_new_i32();
1349
1350 tcg_gen_movi_tl(t0, 0);
1351 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1352 /* Addition, carry and set C/V/SV bits */
1353 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1354 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1355 /* calc V bit */
1356 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1357 tcg_gen_xor_tl(t0, r1, r2);
1358 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1359 /* Calc SV bit */
1360 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1361 /* Calc AV/SAV bits */
1362 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1363 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1364 /* calc SAV */
1365 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1366 /* write back result */
1367 tcg_gen_mov_tl(ret, result);
1368 }
1369
1370 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1371 {
1372 TCGv temp = tcg_constant_i32(con);
1373 gen_addc_CC(ret, r1, temp);
1374 }
1375
1376 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1377 TCGv r4)
1378 {
1379 TCGv temp = tcg_temp_new();
1380 TCGv temp2 = tcg_temp_new();
1381 TCGv result = tcg_temp_new();
1382 TCGv mask = tcg_temp_new();
1383 TCGv t0 = tcg_constant_i32(0);
1384
1385 /* create mask for sticky bits */
1386 tcg_gen_setcond_tl(cond, mask, r4, t0);
1387 tcg_gen_shli_tl(mask, mask, 31);
1388
1389 tcg_gen_add_tl(result, r1, r2);
1390 /* Calc PSW_V */
1391 tcg_gen_xor_tl(temp, result, r1);
1392 tcg_gen_xor_tl(temp2, r1, r2);
1393 tcg_gen_andc_tl(temp, temp, temp2);
1394 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1395 /* Set PSW_SV */
1396 tcg_gen_and_tl(temp, temp, mask);
1397 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1398 /* calc AV bit */
1399 tcg_gen_add_tl(temp, result, result);
1400 tcg_gen_xor_tl(temp, temp, result);
1401 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1402 /* calc SAV bit */
1403 tcg_gen_and_tl(temp, temp, mask);
1404 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1405 /* write back result */
1406 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1407 }
1408
1409 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1410 TCGv r3, TCGv r4)
1411 {
1412 TCGv temp = tcg_constant_i32(r2);
1413 gen_cond_add(cond, r1, temp, r3, r4);
1414 }
1415
1416 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1417 {
1418 TCGv temp = tcg_temp_new_i32();
1419 TCGv result = tcg_temp_new_i32();
1420
1421 tcg_gen_sub_tl(result, r1, r2);
1422 /* calc V bit */
1423 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1424 tcg_gen_xor_tl(temp, r1, r2);
1425 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1426 /* calc SV bit */
1427 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1428 /* Calc AV bit */
1429 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1430 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1431 /* calc SAV bit */
1432 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1433 /* write back result */
1434 tcg_gen_mov_tl(ret, result);
1435 }
1436
1437 static inline void
1438 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1439 {
1440 TCGv temp = tcg_temp_new();
1441 TCGv_i64 t0 = tcg_temp_new_i64();
1442 TCGv_i64 t1 = tcg_temp_new_i64();
1443 TCGv_i64 result = tcg_temp_new_i64();
1444
1445 tcg_gen_sub_i64(result, r1, r2);
1446 /* calc v bit */
1447 tcg_gen_xor_i64(t1, result, r1);
1448 tcg_gen_xor_i64(t0, r1, r2);
1449 tcg_gen_and_i64(t1, t1, t0);
1450 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
1451 /* calc SV bit */
1452 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1453 /* calc AV/SAV bits */
1454 tcg_gen_extrh_i64_i32(temp, result);
1455 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1456 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1457 /* calc SAV */
1458 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1459 /* write back result */
1460 tcg_gen_mov_i64(ret, result);
1461 }
1462
1463 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1464 {
1465 TCGv result = tcg_temp_new();
1466 TCGv temp = tcg_temp_new();
1467
1468 tcg_gen_sub_tl(result, r1, r2);
1469 /* calc C bit */
1470 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1471 /* calc V bit */
1472 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1473 tcg_gen_xor_tl(temp, r1, r2);
1474 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1475 /* calc SV bit */
1476 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1477 /* Calc AV bit */
1478 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1479 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1480 /* calc SAV bit */
1481 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1482 /* write back result */
1483 tcg_gen_mov_tl(ret, result);
1484 }
1485
1486 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1487 {
1488 TCGv temp = tcg_temp_new();
1489 tcg_gen_not_tl(temp, r2);
1490 gen_addc_CC(ret, r1, temp);
1491 }
1492
1493 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1494 TCGv r4)
1495 {
1496 TCGv temp = tcg_temp_new();
1497 TCGv temp2 = tcg_temp_new();
1498 TCGv result = tcg_temp_new();
1499 TCGv mask = tcg_temp_new();
1500 TCGv t0 = tcg_constant_i32(0);
1501
1502 /* create mask for sticky bits */
1503 tcg_gen_setcond_tl(cond, mask, r4, t0);
1504 tcg_gen_shli_tl(mask, mask, 31);
1505
1506 tcg_gen_sub_tl(result, r1, r2);
1507 /* Calc PSW_V */
1508 tcg_gen_xor_tl(temp, result, r1);
1509 tcg_gen_xor_tl(temp2, r1, r2);
1510 tcg_gen_and_tl(temp, temp, temp2);
1511 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1512 /* Set PSW_SV */
1513 tcg_gen_and_tl(temp, temp, mask);
1514 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1515 /* calc AV bit */
1516 tcg_gen_add_tl(temp, result, result);
1517 tcg_gen_xor_tl(temp, temp, result);
1518 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1519 /* calc SAV bit */
1520 tcg_gen_and_tl(temp, temp, mask);
1521 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1522 /* write back result */
1523 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1524 }
1525
1526 static inline void
1527 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1528 TCGv r3, uint32_t n, uint32_t mode)
1529 {
1530 TCGv t_n = tcg_constant_i32(n);
1531 TCGv temp = tcg_temp_new();
1532 TCGv temp2 = tcg_temp_new();
1533 TCGv_i64 temp64 = tcg_temp_new_i64();
1534 switch (mode) {
1535 case MODE_LL:
1536 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1537 break;
1538 case MODE_LU:
1539 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1540 break;
1541 case MODE_UL:
1542 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1543 break;
1544 case MODE_UU:
1545 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1546 break;
1547 }
1548 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1549 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1550 tcg_gen_sub_tl, tcg_gen_sub_tl);
1551 }
1552
1553 static inline void
1554 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1555 TCGv r3, uint32_t n, uint32_t mode)
1556 {
1557 TCGv t_n = tcg_constant_i32(n);
1558 TCGv temp = tcg_temp_new();
1559 TCGv temp2 = tcg_temp_new();
1560 TCGv temp3 = tcg_temp_new();
1561 TCGv_i64 temp64 = tcg_temp_new_i64();
1562
1563 switch (mode) {
1564 case MODE_LL:
1565 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1566 break;
1567 case MODE_LU:
1568 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1569 break;
1570 case MODE_UL:
1571 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1572 break;
1573 case MODE_UU:
1574 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1575 break;
1576 }
1577 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1578 gen_subs(ret_low, r1_low, temp);
1579 tcg_gen_mov_tl(temp, cpu_PSW_V);
1580 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1581 gen_subs(ret_high, r1_high, temp2);
1582 /* combine v bits */
1583 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1584 /* combine av bits */
1585 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1586 }
1587
1588 static inline void
1589 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1590 TCGv r3, uint32_t n, uint32_t mode)
1591 {
1592 TCGv t_n = tcg_constant_i32(n);
1593 TCGv_i64 temp64 = tcg_temp_new_i64();
1594 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1595 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1596 switch (mode) {
1597 case MODE_LL:
1598 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
1599 break;
1600 case MODE_LU:
1601 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
1602 break;
1603 case MODE_UL:
1604 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
1605 break;
1606 case MODE_UU:
1607 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
1608 break;
1609 }
1610 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1611 gen_sub64_d(temp64_3, temp64_2, temp64);
1612 /* write back result */
1613 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1614 }
1615
1616 static inline void
1617 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1618 TCGv r3, uint32_t n, uint32_t mode)
1619 {
1620 TCGv t_n = tcg_constant_i32(n);
1621 TCGv_i64 temp64 = tcg_temp_new_i64();
1622 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1623 switch (mode) {
1624 case MODE_LL:
1625 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
1626 break;
1627 case MODE_LU:
1628 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
1629 break;
1630 case MODE_UL:
1631 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
1632 break;
1633 case MODE_UU:
1634 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
1635 break;
1636 }
1637 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1638 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1639 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1640 }
1641
1642 static inline void
1643 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1644 uint32_t mode)
1645 {
1646 TCGv t_n = tcg_constant_i32(n);
1647 TCGv_i64 temp64 = tcg_temp_new_i64();
1648 switch (mode) {
1649 case MODE_LL:
1650 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1651 break;
1652 case MODE_LU:
1653 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1654 break;
1655 case MODE_UL:
1656 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1657 break;
1658 case MODE_UU:
1659 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1660 break;
1661 }
1662 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1663 }
1664
1665 static inline void
1666 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1667 {
1668 TCGv temp = tcg_temp_new();
1669 TCGv temp2 = tcg_temp_new();
1670
1671 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1672 tcg_gen_shli_tl(temp, r1, 16);
1673 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1674 }
1675
1676 static inline void
1677 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1678 uint32_t n, uint32_t mode)
1679 {
1680 TCGv t_n = tcg_constant_i32(n);
1681 TCGv_i64 temp64 = tcg_temp_new_i64();
1682 switch (mode) {
1683 case MODE_LL:
1684 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1685 break;
1686 case MODE_LU:
1687 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1688 break;
1689 case MODE_UL:
1690 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1691 break;
1692 case MODE_UU:
1693 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1694 break;
1695 }
1696 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1697 }
1698
1699 static inline void
1700 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1701 {
1702 TCGv temp = tcg_temp_new();
1703 TCGv temp2 = tcg_temp_new();
1704
1705 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1706 tcg_gen_shli_tl(temp, r1, 16);
1707 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1708 }
1709
1710 static inline void
1711 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1712 {
1713 TCGv temp = tcg_constant_i32(n);
1714 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1715 }
1716
1717 static inline void
1718 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1719 {
1720 TCGv temp = tcg_constant_i32(n);
1721 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1722 }
1723
1724 static inline void
1725 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1726 uint32_t up_shift)
1727 {
1728 TCGv temp3 = tcg_temp_new();
1729 TCGv_i64 t1 = tcg_temp_new_i64();
1730 TCGv_i64 t2 = tcg_temp_new_i64();
1731 TCGv_i64 t3 = tcg_temp_new_i64();
1732 TCGv_i64 t4 = tcg_temp_new_i64();
1733
1734 tcg_gen_ext_i32_i64(t2, arg2);
1735 tcg_gen_ext_i32_i64(t3, arg3);
1736
1737 tcg_gen_mul_i64(t2, t2, t3);
1738
1739 tcg_gen_ext_i32_i64(t1, arg1);
1740 /* if we shift part of the fraction out, we need to round up */
1741 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1742 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1743 tcg_gen_sari_i64(t2, t2, up_shift - n);
1744 tcg_gen_add_i64(t2, t2, t4);
1745
1746 tcg_gen_sub_i64(t3, t1, t2);
1747 tcg_gen_extrl_i64_i32(temp3, t3);
1748 /* calc v bit */
1749 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1750 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1751 tcg_gen_or_i64(t1, t1, t2);
1752 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1753 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1754 /* Calc SV bit */
1755 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1756 /* Calc AV/SAV bits */
1757 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1758 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1759 /* calc SAV */
1760 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1761 /* write back result */
1762 tcg_gen_mov_tl(ret, temp3);
1763 }
1764
1765 static inline void
1766 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1767 {
1768 TCGv temp = tcg_temp_new();
1769 TCGv temp2 = tcg_temp_new();
1770 if (n == 0) {
1771 tcg_gen_mul_tl(temp, arg2, arg3);
1772 } else { /* n is expected to be 1 */
1773 tcg_gen_mul_tl(temp, arg2, arg3);
1774 tcg_gen_shli_tl(temp, temp, 1);
1775 /* catch special case r1 = r2 = 0x8000 */
1776 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1777 tcg_gen_sub_tl(temp, temp, temp2);
1778 }
1779 gen_sub_d(ret, arg1, temp);
1780 }
1781
1782 static inline void
1783 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1784 {
1785 TCGv temp = tcg_temp_new();
1786 TCGv temp2 = tcg_temp_new();
1787 if (n == 0) {
1788 tcg_gen_mul_tl(temp, arg2, arg3);
1789 } else { /* n is expected to be 1 */
1790 tcg_gen_mul_tl(temp, arg2, arg3);
1791 tcg_gen_shli_tl(temp, temp, 1);
1792 /* catch special case r1 = r2 = 0x8000 */
1793 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1794 tcg_gen_sub_tl(temp, temp, temp2);
1795 }
1796 gen_subs(ret, arg1, temp);
1797 }
1798
1799 static inline void
1800 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1801 TCGv arg3, uint32_t n)
1802 {
1803 TCGv temp = tcg_temp_new();
1804 TCGv temp2 = tcg_temp_new();
1805 TCGv_i64 t1 = tcg_temp_new_i64();
1806 TCGv_i64 t2 = tcg_temp_new_i64();
1807 TCGv_i64 t3 = tcg_temp_new_i64();
1808
1809 if (n == 0) {
1810 tcg_gen_mul_tl(temp, arg2, arg3);
1811 } else { /* n is expected to be 1 */
1812 tcg_gen_mul_tl(temp, arg2, arg3);
1813 tcg_gen_shli_tl(temp, temp, 1);
1814 /* catch special case r1 = r2 = 0x8000 */
1815 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1816 tcg_gen_sub_tl(temp, temp, temp2);
1817 }
1818 tcg_gen_ext_i32_i64(t2, temp);
1819 tcg_gen_shli_i64(t2, t2, 16);
1820 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1821 gen_sub64_d(t3, t1, t2);
1822 /* write back result */
1823 tcg_gen_extr_i64_i32(rl, rh, t3);
1824 }
1825
1826 static inline void
1827 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1828 TCGv arg3, uint32_t n)
1829 {
1830 TCGv temp = tcg_temp_new();
1831 TCGv temp2 = tcg_temp_new();
1832 TCGv_i64 t1 = tcg_temp_new_i64();
1833 TCGv_i64 t2 = tcg_temp_new_i64();
1834
1835 if (n == 0) {
1836 tcg_gen_mul_tl(temp, arg2, arg3);
1837 } else { /* n is expected to be 1 */
1838 tcg_gen_mul_tl(temp, arg2, arg3);
1839 tcg_gen_shli_tl(temp, temp, 1);
1840 /* catch special case r1 = r2 = 0x8000 */
1841 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1842 tcg_gen_sub_tl(temp, temp, temp2);
1843 }
1844 tcg_gen_ext_i32_i64(t2, temp);
1845 tcg_gen_shli_i64(t2, t2, 16);
1846 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1847
1848 gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
1849 tcg_gen_extr_i64_i32(rl, rh, t1);
1850 }
1851
1852 static inline void
1853 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1854 TCGv arg3, uint32_t n)
1855 {
1856 TCGv_i64 t1 = tcg_temp_new_i64();
1857 TCGv_i64 t2 = tcg_temp_new_i64();
1858 TCGv_i64 t3 = tcg_temp_new_i64();
1859 TCGv_i64 t4 = tcg_temp_new_i64();
1860 TCGv temp, temp2;
1861
1862 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1863 tcg_gen_ext_i32_i64(t2, arg2);
1864 tcg_gen_ext_i32_i64(t3, arg3);
1865
1866 tcg_gen_mul_i64(t2, t2, t3);
1867 if (n != 0) {
1868 tcg_gen_shli_i64(t2, t2, 1);
1869 }
1870 tcg_gen_sub_i64(t4, t1, t2);
1871 /* calc v bit */
1872 tcg_gen_xor_i64(t3, t4, t1);
1873 tcg_gen_xor_i64(t2, t1, t2);
1874 tcg_gen_and_i64(t3, t3, t2);
1875 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1876 /* We produce an overflow on the host if the mul before was
1877 (0x80000000 * 0x80000000) << 1). If this is the
1878 case, we negate the ovf. */
1879 if (n == 1) {
1880 temp = tcg_temp_new();
1881 temp2 = tcg_temp_new();
1882 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1883 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1884 tcg_gen_and_tl(temp, temp, temp2);
1885 tcg_gen_shli_tl(temp, temp, 31);
1886 /* negate v bit, if special condition */
1887 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1888 }
1889 /* write back result */
1890 tcg_gen_extr_i64_i32(rl, rh, t4);
1891 /* Calc SV bit */
1892 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1893 /* Calc AV/SAV bits */
1894 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1895 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1896 /* calc SAV */
1897 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1898 }
1899
1900 static inline void
1901 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1902 uint32_t up_shift)
1903 {
1904 TCGv_i64 t1 = tcg_temp_new_i64();
1905 TCGv_i64 t2 = tcg_temp_new_i64();
1906 TCGv_i64 t3 = tcg_temp_new_i64();
1907 TCGv_i64 t4 = tcg_temp_new_i64();
1908
1909 tcg_gen_ext_i32_i64(t1, arg1);
1910 tcg_gen_ext_i32_i64(t2, arg2);
1911 tcg_gen_ext_i32_i64(t3, arg3);
1912
1913 tcg_gen_mul_i64(t2, t2, t3);
1914 /* if we shift part of the fraction out, we need to round up */
1915 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1916 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1917 tcg_gen_sari_i64(t3, t2, up_shift - n);
1918 tcg_gen_add_i64(t3, t3, t4);
1919
1920 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
1921 }
1922
1923 static inline void
1924 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1925 TCGv arg3, uint32_t n)
1926 {
1927 TCGv_i64 r1 = tcg_temp_new_i64();
1928 TCGv t_n = tcg_constant_i32(n);
1929
1930 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1931 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
1932 tcg_gen_extr_i64_i32(rl, rh, r1);
1933 }
1934
1935 static inline void
1936 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1937 TCGv r3, uint32_t n, uint32_t mode)
1938 {
1939 TCGv t_n = tcg_constant_i32(n);
1940 TCGv temp = tcg_temp_new();
1941 TCGv temp2 = tcg_temp_new();
1942 TCGv_i64 temp64 = tcg_temp_new_i64();
1943 switch (mode) {
1944 case MODE_LL:
1945 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1946 break;
1947 case MODE_LU:
1948 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1949 break;
1950 case MODE_UL:
1951 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1952 break;
1953 case MODE_UU:
1954 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1955 break;
1956 }
1957 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1958 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1959 tcg_gen_add_tl, tcg_gen_sub_tl);
1960 }
1961
1962 static inline void
1963 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1964 TCGv r3, uint32_t n, uint32_t mode)
1965 {
1966 TCGv t_n = tcg_constant_i32(n);
1967 TCGv_i64 temp64 = tcg_temp_new_i64();
1968 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1969 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1970 switch (mode) {
1971 case MODE_LL:
1972 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1973 break;
1974 case MODE_LU:
1975 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1976 break;
1977 case MODE_UL:
1978 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1979 break;
1980 case MODE_UU:
1981 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1982 break;
1983 }
1984 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
1985 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
1986 tcg_gen_ext32s_i64(temp64, temp64); /* low */
1987 tcg_gen_sub_i64(temp64, temp64_2, temp64);
1988 tcg_gen_shli_i64(temp64, temp64, 16);
1989
1990 gen_sub64_d(temp64_2, temp64_3, temp64);
1991 /* write back result */
1992 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
1993 }
1994
1995 static inline void
1996 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1997 {
1998 TCGv t_n = tcg_constant_i32(n);
1999 TCGv temp = tcg_temp_new();
2000 TCGv temp2 = tcg_temp_new();
2001 TCGv_i64 temp64 = tcg_temp_new_i64();
2002 switch (mode) {
2003 case MODE_LL:
2004 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2005 break;
2006 case MODE_LU:
2007 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2008 break;
2009 case MODE_UL:
2010 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2011 break;
2012 case MODE_UU:
2013 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2014 break;
2015 }
2016 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2017 tcg_gen_shli_tl(temp, r1, 16);
2018 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2019 }
2020
2021 static inline void
2022 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2023 TCGv r3, uint32_t n, uint32_t mode)
2024 {
2025 TCGv t_n = tcg_constant_i32(n);
2026 TCGv temp = tcg_temp_new();
2027 TCGv temp2 = tcg_temp_new();
2028 TCGv temp3 = tcg_temp_new();
2029 TCGv_i64 temp64 = tcg_temp_new_i64();
2030
2031 switch (mode) {
2032 case MODE_LL:
2033 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2034 break;
2035 case MODE_LU:
2036 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2037 break;
2038 case MODE_UL:
2039 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2040 break;
2041 case MODE_UU:
2042 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2043 break;
2044 }
2045 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2046 gen_adds(ret_low, r1_low, temp);
2047 tcg_gen_mov_tl(temp, cpu_PSW_V);
2048 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2049 gen_subs(ret_high, r1_high, temp2);
2050 /* combine v bits */
2051 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2052 /* combine av bits */
2053 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2054 }
2055
2056 static inline void
2057 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2058 TCGv r3, uint32_t n, uint32_t mode)
2059 {
2060 TCGv t_n = tcg_constant_i32(n);
2061 TCGv_i64 temp64 = tcg_temp_new_i64();
2062 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2063
2064 switch (mode) {
2065 case MODE_LL:
2066 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2067 break;
2068 case MODE_LU:
2069 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2070 break;
2071 case MODE_UL:
2072 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2073 break;
2074 case MODE_UU:
2075 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2076 break;
2077 }
2078 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2079 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2080 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2081 tcg_gen_shli_i64(temp64, temp64, 16);
2082 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2083
2084 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2085 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2086 }
2087
2088 static inline void
2089 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2090 {
2091 TCGv t_n = tcg_constant_i32(n);
2092 TCGv temp = tcg_temp_new();
2093 TCGv temp2 = tcg_temp_new();
2094 TCGv_i64 temp64 = tcg_temp_new_i64();
2095 switch (mode) {
2096 case MODE_LL:
2097 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2098 break;
2099 case MODE_LU:
2100 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2101 break;
2102 case MODE_UL:
2103 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2104 break;
2105 case MODE_UU:
2106 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2107 break;
2108 }
2109 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2110 tcg_gen_shli_tl(temp, r1, 16);
2111 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2112 }
2113
2114 static inline void gen_abs(TCGv ret, TCGv r1)
2115 {
2116 tcg_gen_abs_tl(ret, r1);
2117 /* overflow can only happen, if r1 = 0x80000000 */
2118 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2119 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2120 /* calc SV bit */
2121 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2122 /* Calc AV bit */
2123 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2124 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2125 /* calc SAV bit */
2126 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2127 }
2128
2129 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2130 {
2131 TCGv temp = tcg_temp_new_i32();
2132 TCGv result = tcg_temp_new_i32();
2133
2134 tcg_gen_sub_tl(result, r1, r2);
2135 tcg_gen_sub_tl(temp, r2, r1);
2136 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2137
2138 /* calc V bit */
2139 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2140 tcg_gen_xor_tl(temp, result, r2);
2141 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2142 tcg_gen_xor_tl(temp, r1, r2);
2143 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2144 /* calc SV bit */
2145 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2146 /* Calc AV bit */
2147 tcg_gen_add_tl(cpu_PSW_AV, result, result);
2148 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2149 /* calc SAV bit */
2150 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2151 /* write back result */
2152 tcg_gen_mov_tl(ret, result);
2153 }
2154
2155 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2156 {
2157 TCGv temp = tcg_constant_i32(con);
2158 gen_absdif(ret, r1, temp);
2159 }
2160
2161 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2162 {
2163 TCGv temp = tcg_constant_i32(con);
2164 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2165 }
2166
2167 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2168 {
2169 TCGv high = tcg_temp_new();
2170 TCGv low = tcg_temp_new();
2171
2172 tcg_gen_muls2_tl(low, high, r1, r2);
2173 tcg_gen_mov_tl(ret, low);
2174 /* calc V bit */
2175 tcg_gen_sari_tl(low, low, 31);
2176 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2177 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2178 /* calc SV bit */
2179 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2180 /* Calc AV bit */
2181 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2182 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2183 /* calc SAV bit */
2184 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2185 }
2186
2187 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2188 {
2189 TCGv temp = tcg_constant_i32(con);
2190 gen_mul_i32s(ret, r1, temp);
2191 }
2192
2193 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2194 {
2195 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2196 /* clear V bit */
2197 tcg_gen_movi_tl(cpu_PSW_V, 0);
2198 /* calc SV bit */
2199 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2200 /* Calc AV bit */
2201 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2202 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2203 /* calc SAV bit */
2204 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2205 }
2206
2207 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2208 int32_t con)
2209 {
2210 TCGv temp = tcg_constant_i32(con);
2211 gen_mul_i64s(ret_low, ret_high, r1, temp);
2212 }
2213
2214 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2215 {
2216 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2217 /* clear V bit */
2218 tcg_gen_movi_tl(cpu_PSW_V, 0);
2219 /* calc SV bit */
2220 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2221 /* Calc AV bit */
2222 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2223 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2224 /* calc SAV bit */
2225 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2226 }
2227
2228 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2229 int32_t con)
2230 {
2231 TCGv temp = tcg_constant_i32(con);
2232 gen_mul_i64u(ret_low, ret_high, r1, temp);
2233 }
2234
2235 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2236 {
2237 TCGv temp = tcg_constant_i32(con);
2238 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2239 }
2240
2241 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2242 {
2243 TCGv temp = tcg_constant_i32(con);
2244 gen_helper_mul_suov(ret, cpu_env, r1, temp);
2245 }
2246
2247 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2248 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2249 {
2250 TCGv temp = tcg_constant_i32(con);
2251 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2252 }
2253
2254 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2255 {
2256 TCGv temp = tcg_constant_i32(con);
2257 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2258 }
2259
2260 static void
2261 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2262 {
2263 TCGv_i64 temp_64 = tcg_temp_new_i64();
2264 TCGv_i64 temp2_64 = tcg_temp_new_i64();
2265
2266 if (n == 0) {
2267 if (up_shift == 32) {
2268 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2269 } else if (up_shift == 16) {
2270 tcg_gen_ext_i32_i64(temp_64, arg1);
2271 tcg_gen_ext_i32_i64(temp2_64, arg2);
2272
2273 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2274 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2275 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2276 } else {
2277 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2278 }
2279 /* reset v bit */
2280 tcg_gen_movi_tl(cpu_PSW_V, 0);
2281 } else { /* n is expected to be 1 */
2282 tcg_gen_ext_i32_i64(temp_64, arg1);
2283 tcg_gen_ext_i32_i64(temp2_64, arg2);
2284
2285 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2286
2287 if (up_shift == 0) {
2288 tcg_gen_shli_i64(temp_64, temp_64, 1);
2289 } else {
2290 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2291 }
2292 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2293 /* overflow only occurs if r1 = r2 = 0x8000 */
2294 if (up_shift == 0) {/* result is 64 bit */
2295 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2296 0x80000000);
2297 } else { /* result is 32 bit */
2298 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2299 0x80000000);
2300 }
2301 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2302 /* calc sv overflow bit */
2303 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2304 }
2305 /* calc av overflow bit */
2306 if (up_shift == 0) {
2307 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2308 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2309 } else {
2310 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2311 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2312 }
2313 /* calc sav overflow bit */
2314 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2315 }
2316
2317 static void
2318 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2319 {
2320 TCGv temp = tcg_temp_new();
2321 if (n == 0) {
2322 tcg_gen_mul_tl(ret, arg1, arg2);
2323 } else { /* n is expected to be 1 */
2324 tcg_gen_mul_tl(ret, arg1, arg2);
2325 tcg_gen_shli_tl(ret, ret, 1);
2326 /* catch special case r1 = r2 = 0x8000 */
2327 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2328 tcg_gen_sub_tl(ret, ret, temp);
2329 }
2330 /* reset v bit */
2331 tcg_gen_movi_tl(cpu_PSW_V, 0);
2332 /* calc av overflow bit */
2333 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2334 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2335 /* calc sav overflow bit */
2336 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2337 }
2338
2339 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2340 {
2341 TCGv temp = tcg_temp_new();
2342 if (n == 0) {
2343 tcg_gen_mul_tl(ret, arg1, arg2);
2344 tcg_gen_addi_tl(ret, ret, 0x8000);
2345 } else {
2346 tcg_gen_mul_tl(ret, arg1, arg2);
2347 tcg_gen_shli_tl(ret, ret, 1);
2348 tcg_gen_addi_tl(ret, ret, 0x8000);
2349 /* catch special case r1 = r2 = 0x8000 */
2350 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2351 tcg_gen_muli_tl(temp, temp, 0x8001);
2352 tcg_gen_sub_tl(ret, ret, temp);
2353 }
2354 /* reset v bit */
2355 tcg_gen_movi_tl(cpu_PSW_V, 0);
2356 /* calc av overflow bit */
2357 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2358 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2359 /* calc sav overflow bit */
2360 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2361 /* cut halfword off */
2362 tcg_gen_andi_tl(ret, ret, 0xffff0000);
2363 }
2364
2365 static inline void
2366 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2367 TCGv r3)
2368 {
2369 TCGv_i64 temp64 = tcg_temp_new_i64();
2370 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2371 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2372 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2373 }
2374
2375 static inline void
2376 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2377 int32_t con)
2378 {
2379 TCGv temp = tcg_constant_i32(con);
2380 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2381 }
2382
2383 static inline void
2384 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2385 TCGv r3)
2386 {
2387 TCGv_i64 temp64 = tcg_temp_new_i64();
2388 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2389 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2390 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2391 }
2392
2393 static inline void
2394 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2395 int32_t con)
2396 {
2397 TCGv temp = tcg_constant_i32(con);
2398 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2399 }
2400
2401 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2402 {
2403 TCGv temp = tcg_constant_i32(con);
2404 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2405 }
2406
2407 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2408 {
2409 TCGv temp = tcg_constant_i32(con);
2410 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2411 }
2412
2413 static inline void
2414 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2415 TCGv r3)
2416 {
2417 TCGv_i64 temp64 = tcg_temp_new_i64();
2418 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2419 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2420 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2421 }
2422
2423 static inline void
2424 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2425 int32_t con)
2426 {
2427 TCGv temp = tcg_constant_i32(con);
2428 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2429 }
2430
2431 static inline void
2432 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2433 TCGv r3)
2434 {
2435 TCGv_i64 temp64 = tcg_temp_new_i64();
2436 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2437 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2438 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2439 }
2440
2441 static inline void
2442 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2443 int32_t con)
2444 {
2445 TCGv temp = tcg_constant_i32(con);
2446 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2447 }
2448
2449 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2450 {
2451 tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low));
2452 tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up));
2453 }
2454
2455 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2456 {
2457 tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up));
2458 }
2459
2460 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2461 {
2462 if (shift_count == -32) {
2463 tcg_gen_movi_tl(ret, 0);
2464 } else if (shift_count >= 0) {
2465 tcg_gen_shli_tl(ret, r1, shift_count);
2466 } else {
2467 tcg_gen_shri_tl(ret, r1, -shift_count);
2468 }
2469 }
2470
2471 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2472 {
2473 TCGv temp_low, temp_high;
2474
2475 if (shiftcount == -16) {
2476 tcg_gen_movi_tl(ret, 0);
2477 } else {
2478 temp_high = tcg_temp_new();
2479 temp_low = tcg_temp_new();
2480
2481 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2482 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2483 gen_shi(temp_low, temp_low, shiftcount);
2484 gen_shi(ret, temp_high, shiftcount);
2485 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2486 }
2487 }
2488
2489 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2490 {
2491 uint32_t msk, msk_start;
2492 TCGv temp = tcg_temp_new();
2493 TCGv temp2 = tcg_temp_new();
2494
2495 if (shift_count == 0) {
2496 /* Clear PSW.C and PSW.V */
2497 tcg_gen_movi_tl(cpu_PSW_C, 0);
2498 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2499 tcg_gen_mov_tl(ret, r1);
2500 } else if (shift_count == -32) {
2501 /* set PSW.C */
2502 tcg_gen_mov_tl(cpu_PSW_C, r1);
2503 /* fill ret completely with sign bit */
2504 tcg_gen_sari_tl(ret, r1, 31);
2505 /* clear PSW.V */
2506 tcg_gen_movi_tl(cpu_PSW_V, 0);
2507 } else if (shift_count > 0) {
2508 TCGv t_max = tcg_constant_i32(0x7FFFFFFF >> shift_count);
2509 TCGv t_min = tcg_constant_i32(((int32_t) -0x80000000) >> shift_count);
2510
2511 /* calc carry */
2512 msk_start = 32 - shift_count;
2513 msk = ((1 << shift_count) - 1) << msk_start;
2514 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2515 /* calc v/sv bits */
2516 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2517 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2518 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2519 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2520 /* calc sv */
2521 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2522 /* do shift */
2523 tcg_gen_shli_tl(ret, r1, shift_count);
2524 } else {
2525 /* clear PSW.V */
2526 tcg_gen_movi_tl(cpu_PSW_V, 0);
2527 /* calc carry */
2528 msk = (1 << -shift_count) - 1;
2529 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2530 /* do shift */
2531 tcg_gen_sari_tl(ret, r1, -shift_count);
2532 }
2533 /* calc av overflow bit */
2534 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2535 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2536 /* calc sav overflow bit */
2537 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2538 }
2539
2540 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2541 {
2542 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2543 }
2544
2545 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2546 {
2547 TCGv temp = tcg_constant_i32(con);
2548 gen_shas(ret, r1, temp);
2549 }
2550
2551 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2552 {
2553 TCGv low, high;
2554
2555 if (shift_count == 0) {
2556 tcg_gen_mov_tl(ret, r1);
2557 } else if (shift_count > 0) {
2558 low = tcg_temp_new();
2559 high = tcg_temp_new();
2560
2561 tcg_gen_andi_tl(high, r1, 0xffff0000);
2562 tcg_gen_shli_tl(low, r1, shift_count);
2563 tcg_gen_shli_tl(ret, high, shift_count);
2564 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2565 } else {
2566 low = tcg_temp_new();
2567 high = tcg_temp_new();
2568
2569 tcg_gen_ext16s_tl(low, r1);
2570 tcg_gen_sari_tl(low, low, -shift_count);
2571 tcg_gen_sari_tl(ret, r1, -shift_count);
2572 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2573 }
2574 }
2575
2576 /* ret = {ret[30:0], (r1 cond r2)}; */
2577 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2578 {
2579 TCGv temp = tcg_temp_new();
2580 TCGv temp2 = tcg_temp_new();
2581
2582 tcg_gen_shli_tl(temp, ret, 1);
2583 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2584 tcg_gen_or_tl(ret, temp, temp2);
2585 }
2586
2587 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2588 {
2589 TCGv temp = tcg_constant_i32(con);
2590 gen_sh_cond(cond, ret, r1, temp);
2591 }
2592
2593 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2594 {
2595 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2596 }
2597
2598 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2599 {
2600 TCGv temp = tcg_constant_i32(con);
2601 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2602 }
2603
2604 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2605 {
2606 TCGv temp = tcg_constant_i32(con);
2607 gen_helper_add_suov(ret, cpu_env, r1, temp);
2608 }
2609
2610 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2611 {
2612 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2613 }
2614
2615 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2616 {
2617 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2618 }
2619
2620 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
2621 int pos1, int pos2,
2622 void(*op1)(TCGv, TCGv, TCGv),
2623 void(*op2)(TCGv, TCGv, TCGv))
2624 {
2625 TCGv temp1, temp2;
2626
2627 temp1 = tcg_temp_new();
2628 temp2 = tcg_temp_new();
2629
2630 tcg_gen_shri_tl(temp2, r2, pos2);
2631 tcg_gen_shri_tl(temp1, r1, pos1);
2632
2633 (*op1)(temp1, temp1, temp2);
2634 (*op2)(temp1 , ret, temp1);
2635
2636 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
2637 }
2638
2639 /* ret = r1[pos1] op1 r2[pos2]; */
2640 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
2641 int pos1, int pos2,
2642 void(*op1)(TCGv, TCGv, TCGv))
2643 {
2644 TCGv temp1, temp2;
2645
2646 temp1 = tcg_temp_new();
2647 temp2 = tcg_temp_new();
2648
2649 tcg_gen_shri_tl(temp2, r2, pos2);
2650 tcg_gen_shri_tl(temp1, r1, pos1);
2651
2652 (*op1)(ret, temp1, temp2);
2653
2654 tcg_gen_andi_tl(ret, ret, 0x1);
2655 }
2656
2657 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
2658 void(*op)(TCGv, TCGv, TCGv))
2659 {
2660 TCGv temp = tcg_temp_new();
2661 TCGv temp2 = tcg_temp_new();
2662 /* temp = (arg1 cond arg2 )*/
2663 tcg_gen_setcond_tl(cond, temp, r1, r2);
2664 /* temp2 = ret[0]*/
2665 tcg_gen_andi_tl(temp2, ret, 0x1);
2666 /* temp = temp insn temp2 */
2667 (*op)(temp, temp, temp2);
2668 /* ret = {ret[31:1], temp} */
2669 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
2670 }
2671
2672 static inline void
2673 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
2674 void(*op)(TCGv, TCGv, TCGv))
2675 {
2676 TCGv temp = tcg_constant_i32(con);
2677 gen_accumulating_cond(cond, ret, r1, temp, op);
2678 }
2679
2680 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
2681 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
2682 {
2683 tcg_gen_setcond_tl(cond, ret, r1, r2);
2684 tcg_gen_neg_tl(ret, ret);
2685 }
2686
2687 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
2688 {
2689 TCGv b0 = tcg_temp_new();
2690 TCGv b1 = tcg_temp_new();
2691 TCGv b2 = tcg_temp_new();
2692 TCGv b3 = tcg_temp_new();
2693
2694 /* byte 0 */
2695 tcg_gen_andi_tl(b0, r1, 0xff);
2696 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
2697
2698 /* byte 1 */
2699 tcg_gen_andi_tl(b1, r1, 0xff00);
2700 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
2701
2702 /* byte 2 */
2703 tcg_gen_andi_tl(b2, r1, 0xff0000);
2704 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
2705
2706 /* byte 3 */
2707 tcg_gen_andi_tl(b3, r1, 0xff000000);
2708 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
2709
2710 /* combine them */
2711 tcg_gen_or_tl(ret, b0, b1);
2712 tcg_gen_or_tl(ret, ret, b2);
2713 tcg_gen_or_tl(ret, ret, b3);
2714 }
2715
2716 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
2717 {
2718 TCGv h0 = tcg_temp_new();
2719 TCGv h1 = tcg_temp_new();
2720
2721 /* halfword 0 */
2722 tcg_gen_andi_tl(h0, r1, 0xffff);
2723 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
2724
2725 /* halfword 1 */
2726 tcg_gen_andi_tl(h1, r1, 0xffff0000);
2727 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
2728
2729 /* combine them */
2730 tcg_gen_or_tl(ret, h0, h1);
2731 }
2732
2733 /* mask = ((1 << width) -1) << pos;
2734 ret = (r1 & ~mask) | (r2 << pos) & mask); */
2735 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
2736 {
2737 TCGv mask = tcg_temp_new();
2738 TCGv temp = tcg_temp_new();
2739 TCGv temp2 = tcg_temp_new();
2740
2741 tcg_gen_movi_tl(mask, 1);
2742 tcg_gen_shl_tl(mask, mask, width);
2743 tcg_gen_subi_tl(mask, mask, 1);
2744 tcg_gen_shl_tl(mask, mask, pos);
2745
2746 tcg_gen_shl_tl(temp, r2, pos);
2747 tcg_gen_and_tl(temp, temp, mask);
2748 tcg_gen_andc_tl(temp2, r1, mask);
2749 tcg_gen_or_tl(ret, temp, temp2);
2750 }
2751
2752 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
2753 {
2754 TCGv_i64 temp = tcg_temp_new_i64();
2755
2756 gen_helper_bsplit(temp, r1);
2757 tcg_gen_extr_i64_i32(rl, rh, temp);
2758 }
2759
2760 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
2761 {
2762 TCGv_i64 temp = tcg_temp_new_i64();
2763
2764 gen_helper_unpack(temp, r1);
2765 tcg_gen_extr_i64_i32(rl, rh, temp);
2766 }
2767
2768 static inline void
2769 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2770 {
2771 TCGv_i64 ret = tcg_temp_new_i64();
2772
2773 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
2774 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
2775 } else {
2776 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
2777 }
2778 tcg_gen_extr_i64_i32(rl, rh, ret);
2779 }
2780
2781 static inline void
2782 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2783 {
2784 TCGv_i64 ret = tcg_temp_new_i64();
2785
2786 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
2787 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
2788 } else {
2789 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
2790 }
2791 tcg_gen_extr_i64_i32(rl, rh, ret);
2792 }
2793
2794 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
2795 {
2796 TCGv temp = tcg_temp_new();
2797 /* calc AV bit */
2798 tcg_gen_add_tl(temp, arg_low, arg_low);
2799 tcg_gen_xor_tl(temp, temp, arg_low);
2800 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
2801 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
2802 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2803 /* calc SAV bit */
2804 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2805 tcg_gen_movi_tl(cpu_PSW_V, 0);
2806 }
2807
2808 static void gen_calc_usb_mulr_h(TCGv arg)
2809 {
2810 TCGv temp = tcg_temp_new();
2811 /* calc AV bit */
2812 tcg_gen_add_tl(temp, arg, arg);
2813 tcg_gen_xor_tl(temp, temp, arg);
2814 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
2815 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2816 /* calc SAV bit */
2817 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2818 /* clear V bit */
2819 tcg_gen_movi_tl(cpu_PSW_V, 0);
2820 }
2821
2822 /* helpers for generating program flow micro-ops */
2823
2824 static inline void gen_save_pc(target_ulong pc)
2825 {
2826 tcg_gen_movi_tl(cpu_PC, pc);
2827 }
2828
2829 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2830 {
2831 if (translator_use_goto_tb(&ctx->base, dest)) {
2832 tcg_gen_goto_tb(n);
2833 gen_save_pc(dest);
2834 tcg_gen_exit_tb(ctx->base.tb, n);
2835 } else {
2836 gen_save_pc(dest);
2837 tcg_gen_lookup_and_goto_ptr();
2838 }
2839 }
2840
2841 static void generate_trap(DisasContext *ctx, int class, int tin)
2842 {
2843 TCGv_i32 classtemp = tcg_constant_i32(class);
2844 TCGv_i32 tintemp = tcg_constant_i32(tin);
2845
2846 gen_save_pc(ctx->base.pc_next);
2847 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
2848 ctx->base.is_jmp = DISAS_NORETURN;
2849 }
2850
2851 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
2852 TCGv r2, int16_t address)
2853 {
2854 TCGLabel *jumpLabel = gen_new_label();
2855 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
2856
2857 gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
2858
2859 gen_set_label(jumpLabel);
2860 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2);
2861 }
2862
2863 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
2864 int r2, int16_t address)
2865 {
2866 TCGv temp = tcg_constant_i32(r2);
2867 gen_branch_cond(ctx, cond, r1, temp, address);
2868 }
2869
2870 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
2871 {
2872 TCGLabel *l1 = gen_new_label();
2873
2874 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
2875 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
2876 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset);
2877 gen_set_label(l1);
2878 gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
2879 }
2880
2881 static void gen_fcall_save_ctx(DisasContext *ctx)
2882 {
2883 TCGv temp = tcg_temp_new();
2884
2885 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
2886 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
2887 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
2888 tcg_gen_mov_tl(cpu_gpr_a[10], temp);
2889 }
2890
2891 static void gen_fret(DisasContext *ctx)
2892 {
2893 TCGv temp = tcg_temp_new();
2894
2895 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
2896 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
2897 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
2898 tcg_gen_mov_tl(cpu_PC, temp);
2899 tcg_gen_exit_tb(NULL, 0);
2900 ctx->base.is_jmp = DISAS_NORETURN;
2901 }
2902
2903 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
2904 int r2 , int32_t constant , int32_t offset)
2905 {
2906 TCGv temp, temp2;
2907 int n;
2908
2909 switch (opc) {
2910 /* SB-format jumps */
2911 case OPC1_16_SB_J:
2912 case OPC1_32_B_J:
2913 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
2914 break;
2915 case OPC1_32_B_CALL:
2916 case OPC1_16_SB_CALL:
2917 gen_helper_1arg(call, ctx->pc_succ_insn);
2918 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
2919 break;
2920 case OPC1_16_SB_JZ:
2921 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
2922 break;
2923 case OPC1_16_SB_JNZ:
2924 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
2925 break;
2926 /* SBC-format jumps */
2927 case OPC1_16_SBC_JEQ:
2928 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
2929 break;
2930 case OPC1_16_SBC_JEQ2:
2931 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant,
2932 offset + 16);
2933 break;
2934 case OPC1_16_SBC_JNE:
2935 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
2936 break;
2937 case OPC1_16_SBC_JNE2:
2938 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15],
2939 constant, offset + 16);
2940 break;
2941 /* SBRN-format jumps */
2942 case OPC1_16_SBRN_JZ_T:
2943 temp = tcg_temp_new();
2944 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2945 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
2946 break;
2947 case OPC1_16_SBRN_JNZ_T:
2948 temp = tcg_temp_new();
2949 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2950 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
2951 break;
2952 /* SBR-format jumps */
2953 case OPC1_16_SBR_JEQ:
2954 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2955 offset);
2956 break;
2957 case OPC1_16_SBR_JEQ2:
2958 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2959 offset + 16);
2960 break;
2961 case OPC1_16_SBR_JNE:
2962 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2963 offset);
2964 break;
2965 case OPC1_16_SBR_JNE2:
2966 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2967 offset + 16);
2968 break;
2969 case OPC1_16_SBR_JNZ:
2970 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
2971 break;
2972 case OPC1_16_SBR_JNZ_A:
2973 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
2974 break;
2975 case OPC1_16_SBR_JGEZ:
2976 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
2977 break;
2978 case OPC1_16_SBR_JGTZ:
2979 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
2980 break;
2981 case OPC1_16_SBR_JLEZ:
2982 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
2983 break;
2984 case OPC1_16_SBR_JLTZ:
2985 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
2986 break;
2987 case OPC1_16_SBR_JZ:
2988 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
2989 break;
2990 case OPC1_16_SBR_JZ_A:
2991 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
2992 break;
2993 case OPC1_16_SBR_LOOP:
2994 gen_loop(ctx, r1, offset * 2 - 32);
2995 break;
2996 /* SR-format jumps */
2997 case OPC1_16_SR_JI:
2998 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
2999 tcg_gen_exit_tb(NULL, 0);
3000 break;
3001 case OPC2_32_SYS_RET:
3002 case OPC2_16_SR_RET:
3003 gen_helper_ret(cpu_env);
3004 tcg_gen_exit_tb(NULL, 0);
3005 break;
3006 /* B-format */
3007 case OPC1_32_B_CALLA:
3008 gen_helper_1arg(call, ctx->pc_succ_insn);
3009 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3010 break;
3011 case OPC1_32_B_FCALL:
3012 gen_fcall_save_ctx(ctx);
3013 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3014 break;
3015 case OPC1_32_B_FCALLA:
3016 gen_fcall_save_ctx(ctx);
3017 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3018 break;
3019 case OPC1_32_B_JLA:
3020 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
3021 /* fall through */
3022 case OPC1_32_B_JA:
3023 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3024 break;
3025 case OPC1_32_B_JL:
3026 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
3027 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3028 break;
3029 /* BOL format */
3030 case OPCM_32_BRC_EQ_NEQ:
3031 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3032 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3033 } else {
3034 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3035 }
3036 break;
3037 case OPCM_32_BRC_GE:
3038 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3039 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3040 } else {
3041 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3042 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3043 offset);
3044 }
3045 break;
3046 case OPCM_32_BRC_JLT:
3047 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3048 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3049 } else {
3050 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3051 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3052 offset);
3053 }
3054 break;
3055 case OPCM_32_BRC_JNE:
3056 temp = tcg_temp_new();
3057 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3058 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3059 /* subi is unconditional */
3060 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3061 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3062 } else {
3063 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3064 /* addi is unconditional */
3065 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3066 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3067 }
3068 break;
3069 /* BRN format */
3070 case OPCM_32_BRN_JTT:
3071 n = MASK_OP_BRN_N(ctx->opcode);
3072
3073 temp = tcg_temp_new();
3074 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3075
3076 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3077 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3078 } else {
3079 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3080 }
3081 break;
3082 /* BRR Format */
3083 case OPCM_32_BRR_EQ_NEQ:
3084 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3085 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3086 offset);
3087 } else {
3088 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3089 offset);
3090 }
3091 break;
3092 case OPCM_32_BRR_ADDR_EQ_NEQ:
3093 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3094 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3095 offset);
3096 } else {
3097 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3098 offset);
3099 }
3100 break;
3101 case OPCM_32_BRR_GE:
3102 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3103 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3104 offset);
3105 } else {
3106 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3107 offset);
3108 }
3109 break;
3110 case OPCM_32_BRR_JLT:
3111 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3112 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3113 offset);
3114 } else {
3115 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3116 offset);
3117 }
3118 break;
3119 case OPCM_32_BRR_LOOP:
3120 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3121 gen_loop(ctx, r2, offset * 2);
3122 } else {
3123 /* OPC2_32_BRR_LOOPU */
3124 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3125 }
3126 break;
3127 case OPCM_32_BRR_JNE:
3128 temp = tcg_temp_new();
3129 temp2 = tcg_temp_new();
3130 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3131 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3132 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3133 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3134 /* subi is unconditional */
3135 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3136 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3137 } else {
3138 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3139 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3140 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3141 /* addi is unconditional */
3142 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3143 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3144 }
3145 break;
3146 case OPCM_32_BRR_JNZ:
3147 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3148 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3149 } else {
3150 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3151 }
3152 break;
3153 default:
3154 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3155 }
3156 ctx->base.is_jmp = DISAS_NORETURN;
3157 }
3158
3159
3160 /*
3161 * Functions for decoding instructions
3162 */
3163
3164 static void decode_src_opc(DisasContext *ctx, int op1)
3165 {
3166 int r1;
3167 int32_t const4;
3168 TCGv temp, temp2;
3169
3170 r1 = MASK_OP_SRC_S1D(ctx->opcode);
3171 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3172
3173 switch (op1) {
3174 case OPC1_16_SRC_ADD:
3175 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3176 break;
3177 case OPC1_16_SRC_ADD_A15:
3178 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3179 break;
3180 case OPC1_16_SRC_ADD_15A:
3181 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3182 break;
3183 case OPC1_16_SRC_ADD_A:
3184 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3185 break;
3186 case OPC1_16_SRC_CADD:
3187 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3188 cpu_gpr_d[15]);
3189 break;
3190 case OPC1_16_SRC_CADDN:
3191 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3192 cpu_gpr_d[15]);
3193 break;
3194 case OPC1_16_SRC_CMOV:
3195 temp = tcg_constant_tl(0);
3196 temp2 = tcg_constant_tl(const4);
3197 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3198 temp2, cpu_gpr_d[r1]);
3199 break;
3200 case OPC1_16_SRC_CMOVN:
3201 temp = tcg_constant_tl(0);
3202 temp2 = tcg_constant_tl(const4);
3203 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3204 temp2, cpu_gpr_d[r1]);
3205 break;
3206 case OPC1_16_SRC_EQ:
3207 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3208 const4);
3209 break;
3210 case OPC1_16_SRC_LT:
3211 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3212 const4);
3213 break;
3214 case OPC1_16_SRC_MOV:
3215 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3216 break;
3217 case OPC1_16_SRC_MOV_A:
3218 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3219 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3220 break;
3221 case OPC1_16_SRC_MOV_E:
3222 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3223 CHECK_REG_PAIR(r1);
3224 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3225 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3226 } else {
3227 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3228 }
3229 break;
3230 case OPC1_16_SRC_SH:
3231 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3232 break;
3233 case OPC1_16_SRC_SHA:
3234 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3235 break;
3236 default:
3237 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3238 }
3239 }
3240
3241 static void decode_srr_opc(DisasContext *ctx, int op1)
3242 {
3243 int r1, r2;
3244 TCGv temp;
3245
3246 r1 = MASK_OP_SRR_S1D(ctx->opcode);
3247 r2 = MASK_OP_SRR_S2(ctx->opcode);
3248
3249 switch (op1) {
3250 case OPC1_16_SRR_ADD:
3251 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3252 break;
3253 case OPC1_16_SRR_ADD_A15:
3254 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3255 break;
3256 case OPC1_16_SRR_ADD_15A:
3257 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3258 break;
3259 case OPC1_16_SRR_ADD_A:
3260 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3261 break;
3262 case OPC1_16_SRR_ADDS:
3263 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3264 break;
3265 case OPC1_16_SRR_AND:
3266 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3267 break;
3268 case OPC1_16_SRR_CMOV:
3269 temp = tcg_constant_tl(0);
3270 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3271 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3272 break;
3273 case OPC1_16_SRR_CMOVN:
3274 temp = tcg_constant_tl(0);
3275 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3276 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3277 break;
3278 case OPC1_16_SRR_EQ:
3279 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3280 cpu_gpr_d[r2]);
3281 break;
3282 case OPC1_16_SRR_LT:
3283 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3284 cpu_gpr_d[r2]);
3285 break;
3286 case OPC1_16_SRR_MOV:
3287 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3288 break;
3289 case OPC1_16_SRR_MOV_A:
3290 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3291 break;
3292 case OPC1_16_SRR_MOV_AA:
3293 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3294 break;
3295 case OPC1_16_SRR_MOV_D:
3296 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3297 break;
3298 case OPC1_16_SRR_MUL:
3299 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3300 break;
3301 case OPC1_16_SRR_OR:
3302 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3303 break;
3304 case OPC1_16_SRR_SUB:
3305 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3306 break;
3307 case OPC1_16_SRR_SUB_A15B:
3308 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3309 break;
3310 case OPC1_16_SRR_SUB_15AB:
3311 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3312 break;
3313 case OPC1_16_SRR_SUBS:
3314 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3315 break;
3316 case OPC1_16_SRR_XOR:
3317 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3318 break;
3319 default:
3320 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3321 }
3322 }
3323
3324 static void decode_ssr_opc(DisasContext *ctx, int op1)
3325 {
3326 int r1, r2;
3327
3328 r1 = MASK_OP_SSR_S1(ctx->opcode);
3329 r2 = MASK_OP_SSR_S2(ctx->opcode);
3330
3331 switch (op1) {
3332 case OPC1_16_SSR_ST_A:
3333 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3334 break;
3335 case OPC1_16_SSR_ST_A_POSTINC:
3336 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3337 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3338 break;
3339 case OPC1_16_SSR_ST_B:
3340 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3341 break;
3342 case OPC1_16_SSR_ST_B_POSTINC:
3343 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3344 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3345 break;
3346 case OPC1_16_SSR_ST_H:
3347 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3348 break;
3349 case OPC1_16_SSR_ST_H_POSTINC:
3350 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3351 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3352 break;
3353 case OPC1_16_SSR_ST_W:
3354 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3355 break;
3356 case OPC1_16_SSR_ST_W_POSTINC:
3357 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3358 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3359 break;
3360 default:
3361 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3362 }
3363 }
3364
3365 static void decode_sc_opc(DisasContext *ctx, int op1)
3366 {
3367 int32_t const16;
3368
3369 const16 = MASK_OP_SC_CONST8(ctx->opcode);
3370
3371 switch (op1) {
3372 case OPC1_16_SC_AND:
3373 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3374 break;
3375 case OPC1_16_SC_BISR:
3376 gen_helper_1arg(bisr, const16 & 0xff);
3377 break;
3378 case OPC1_16_SC_LD_A:
3379 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3380 break;
3381 case OPC1_16_SC_LD_W:
3382 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3383 break;
3384 case OPC1_16_SC_MOV:
3385 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3386 break;
3387 case OPC1_16_SC_OR:
3388 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3389 break;
3390 case OPC1_16_SC_ST_A:
3391 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3392 break;
3393 case OPC1_16_SC_ST_W:
3394 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3395 break;
3396 case OPC1_16_SC_SUB_A:
3397 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3398 break;
3399 default:
3400 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3401 }
3402 }
3403
3404 static void decode_slr_opc(DisasContext *ctx, int op1)
3405 {
3406 int r1, r2;
3407
3408 r1 = MASK_OP_SLR_D(ctx->opcode);
3409 r2 = MASK_OP_SLR_S2(ctx->opcode);
3410
3411 switch (op1) {
3412 /* SLR-format */
3413 case OPC1_16_SLR_LD_A:
3414 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3415 break;
3416 case OPC1_16_SLR_LD_A_POSTINC:
3417 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3418 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3419 break;
3420 case OPC1_16_SLR_LD_BU:
3421 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3422 break;
3423 case OPC1_16_SLR_LD_BU_POSTINC:
3424 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3425 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3426 break;
3427 case OPC1_16_SLR_LD_H:
3428 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3429 break;
3430 case OPC1_16_SLR_LD_H_POSTINC:
3431 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3432 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3433 break;
3434 case OPC1_16_SLR_LD_W:
3435 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3436 break;
3437 case OPC1_16_SLR_LD_W_POSTINC:
3438 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3439 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3440 break;
3441 default:
3442 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3443 }
3444 }
3445
3446 static void decode_sro_opc(DisasContext *ctx, int op1)
3447 {
3448 int r2;
3449 int32_t address;
3450
3451 r2 = MASK_OP_SRO_S2(ctx->opcode);
3452 address = MASK_OP_SRO_OFF4(ctx->opcode);
3453
3454 /* SRO-format */
3455 switch (op1) {
3456 case OPC1_16_SRO_LD_A:
3457 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3458 break;
3459 case OPC1_16_SRO_LD_BU:
3460 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3461 break;
3462 case OPC1_16_SRO_LD_H:
3463 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3464 break;
3465 case OPC1_16_SRO_LD_W:
3466 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3467 break;
3468 case OPC1_16_SRO_ST_A:
3469 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3470 break;
3471 case OPC1_16_SRO_ST_B:
3472 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3473 break;
3474 case OPC1_16_SRO_ST_H:
3475 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3476 break;
3477 case OPC1_16_SRO_ST_W:
3478 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3479 break;
3480 default:
3481 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3482 }
3483 }
3484
3485 static void decode_sr_system(DisasContext *ctx)
3486 {
3487 uint32_t op2;
3488 op2 = MASK_OP_SR_OP2(ctx->opcode);
3489
3490 switch (op2) {
3491 case OPC2_16_SR_NOP:
3492 break;
3493 case OPC2_16_SR_RET:
3494 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3495 break;
3496 case OPC2_16_SR_RFE:
3497 gen_helper_rfe(cpu_env);
3498 tcg_gen_exit_tb(NULL, 0);
3499 ctx->base.is_jmp = DISAS_NORETURN;
3500 break;
3501 case OPC2_16_SR_DEBUG:
3502 /* raise EXCP_DEBUG */
3503 break;
3504 case OPC2_16_SR_FRET:
3505 gen_fret(ctx);
3506 break;
3507 default:
3508 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3509 }
3510 }
3511
3512 static void decode_sr_accu(DisasContext *ctx)
3513 {
3514 uint32_t op2;
3515 uint32_t r1;
3516
3517 r1 = MASK_OP_SR_S1D(ctx->opcode);
3518 op2 = MASK_OP_SR_OP2(ctx->opcode);
3519
3520 switch (op2) {
3521 case OPC2_16_SR_RSUB:
3522 /* calc V bit -- overflow only if r1 = -0x80000000 */
3523 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], -0x80000000);
3524 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3525 /* calc SV bit */
3526 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3527 /* sub */
3528 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3529 /* calc av */
3530 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3531 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3532 /* calc sav */
3533 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3534 break;
3535 case OPC2_16_SR_SAT_B:
3536 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3537 break;
3538 case OPC2_16_SR_SAT_BU:
3539 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3540 break;
3541 case OPC2_16_SR_SAT_H:
3542 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3543 break;
3544 case OPC2_16_SR_SAT_HU:
3545 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3546 break;
3547 default:
3548 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3549 }
3550 }
3551
3552 static void decode_16Bit_opc(DisasContext *ctx)
3553 {
3554 int op1;
3555 int r1, r2;
3556 int32_t const16;
3557 int32_t address;
3558 TCGv temp;
3559
3560 op1 = MASK_OP_MAJOR(ctx->opcode);
3561
3562 /* handle ADDSC.A opcode only being 6 bit long */
3563 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3564 op1 = OPC1_16_SRRS_ADDSC_A;
3565 }
3566
3567 switch (op1) {
3568 case OPC1_16_SRC_ADD:
3569 case OPC1_16_SRC_ADD_A15:
3570 case OPC1_16_SRC_ADD_15A:
3571 case OPC1_16_SRC_ADD_A:
3572 case OPC1_16_SRC_CADD:
3573 case OPC1_16_SRC_CADDN:
3574 case OPC1_16_SRC_CMOV:
3575 case OPC1_16_SRC_CMOVN:
3576 case OPC1_16_SRC_EQ:
3577 case OPC1_16_SRC_LT:
3578 case OPC1_16_SRC_MOV:
3579 case OPC1_16_SRC_MOV_A:
3580 case OPC1_16_SRC_MOV_E:
3581 case OPC1_16_SRC_SH:
3582 case OPC1_16_SRC_SHA:
3583 decode_src_opc(ctx, op1);
3584 break;
3585 /* SRR-format */
3586 case OPC1_16_SRR_ADD:
3587 case OPC1_16_SRR_ADD_A15:
3588 case OPC1_16_SRR_ADD_15A:
3589 case OPC1_16_SRR_ADD_A:
3590 case OPC1_16_SRR_ADDS:
3591 case OPC1_16_SRR_AND:
3592 case OPC1_16_SRR_CMOV:
3593 case OPC1_16_SRR_CMOVN:
3594 case OPC1_16_SRR_EQ:
3595 case OPC1_16_SRR_LT:
3596 case OPC1_16_SRR_MOV:
3597 case OPC1_16_SRR_MOV_A:
3598 case OPC1_16_SRR_MOV_AA:
3599 case OPC1_16_SRR_MOV_D:
3600 case OPC1_16_SRR_MUL:
3601 case OPC1_16_SRR_OR:
3602 case OPC1_16_SRR_SUB:
3603 case OPC1_16_SRR_SUB_A15B:
3604 case OPC1_16_SRR_SUB_15AB:
3605 case OPC1_16_SRR_SUBS:
3606 case OPC1_16_SRR_XOR:
3607 decode_srr_opc(ctx, op1);
3608 break;
3609 /* SSR-format */
3610 case OPC1_16_SSR_ST_A:
3611 case OPC1_16_SSR_ST_A_POSTINC:
3612 case OPC1_16_SSR_ST_B:
3613 case OPC1_16_SSR_ST_B_POSTINC:
3614 case OPC1_16_SSR_ST_H:
3615 case OPC1_16_SSR_ST_H_POSTINC:
3616 case OPC1_16_SSR_ST_W:
3617 case OPC1_16_SSR_ST_W_POSTINC:
3618 decode_ssr_opc(ctx, op1);
3619 break;
3620 /* SRRS-format */
3621 case OPC1_16_SRRS_ADDSC_A:
3622 r2 = MASK_OP_SRRS_S2(ctx->opcode);
3623 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
3624 const16 = MASK_OP_SRRS_N(ctx->opcode);
3625 temp = tcg_temp_new();
3626 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
3627 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
3628 break;
3629 /* SLRO-format */
3630 case OPC1_16_SLRO_LD_A:
3631 r1 = MASK_OP_SLRO_D(ctx->opcode);
3632 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3633 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3634 break;
3635 case OPC1_16_SLRO_LD_BU:
3636 r1 = MASK_OP_SLRO_D(ctx->opcode);
3637 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3638 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3639 break;
3640 case OPC1_16_SLRO_LD_H:
3641 r1 = MASK_OP_SLRO_D(ctx->opcode);
3642 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3643 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3644 break;
3645 case OPC1_16_SLRO_LD_W:
3646 r1 = MASK_OP_SLRO_D(ctx->opcode);
3647 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3648 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3649 break;
3650 /* SB-format */
3651 case OPC1_16_SB_CALL:
3652 case OPC1_16_SB_J:
3653 case OPC1_16_SB_JNZ:
3654 case OPC1_16_SB_JZ:
3655 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
3656 gen_compute_branch(ctx, op1, 0, 0, 0, address);
3657 break;
3658 /* SBC-format */
3659 case OPC1_16_SBC_JEQ:
3660 case OPC1_16_SBC_JNE:
3661 address = MASK_OP_SBC_DISP4(ctx->opcode);
3662 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3663 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3664 break;
3665 case OPC1_16_SBC_JEQ2:
3666 case OPC1_16_SBC_JNE2:
3667 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3668 address = MASK_OP_SBC_DISP4(ctx->opcode);
3669 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3670 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3671 } else {
3672 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3673 }
3674 break;
3675 /* SBRN-format */
3676 case OPC1_16_SBRN_JNZ_T:
3677 case OPC1_16_SBRN_JZ_T:
3678 address = MASK_OP_SBRN_DISP4(ctx->opcode);
3679 const16 = MASK_OP_SBRN_N(ctx->opcode);
3680 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3681 break;
3682 /* SBR-format */
3683 case OPC1_16_SBR_JEQ2:
3684 case OPC1_16_SBR_JNE2:
3685 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3686 r1 = MASK_OP_SBR_S2(ctx->opcode);
3687 address = MASK_OP_SBR_DISP4(ctx->opcode);
3688 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3689 } else {
3690 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3691 }
3692 break;
3693 case OPC1_16_SBR_JEQ:
3694 case OPC1_16_SBR_JGEZ:
3695 case OPC1_16_SBR_JGTZ:
3696 case OPC1_16_SBR_JLEZ:
3697 case OPC1_16_SBR_JLTZ:
3698 case OPC1_16_SBR_JNE:
3699 case OPC1_16_SBR_JNZ:
3700 case OPC1_16_SBR_JNZ_A:
3701 case OPC1_16_SBR_JZ:
3702 case OPC1_16_SBR_JZ_A:
3703 case OPC1_16_SBR_LOOP:
3704 r1 = MASK_OP_SBR_S2(ctx->opcode);
3705 address = MASK_OP_SBR_DISP4(ctx->opcode);
3706 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3707 break;
3708 /* SC-format */
3709 case OPC1_16_SC_AND:
3710 case OPC1_16_SC_BISR:
3711 case OPC1_16_SC_LD_A:
3712 case OPC1_16_SC_LD_W:
3713 case OPC1_16_SC_MOV:
3714 case OPC1_16_SC_OR:
3715 case OPC1_16_SC_ST_A:
3716 case OPC1_16_SC_ST_W:
3717 case OPC1_16_SC_SUB_A:
3718 decode_sc_opc(ctx, op1);
3719 break;
3720 /* SLR-format */
3721 case OPC1_16_SLR_LD_A:
3722 case OPC1_16_SLR_LD_A_POSTINC:
3723 case OPC1_16_SLR_LD_BU:
3724 case OPC1_16_SLR_LD_BU_POSTINC:
3725 case OPC1_16_SLR_LD_H:
3726 case OPC1_16_SLR_LD_H_POSTINC:
3727 case OPC1_16_SLR_LD_W:
3728 case OPC1_16_SLR_LD_W_POSTINC:
3729 decode_slr_opc(ctx, op1);
3730 break;
3731 /* SRO-format */
3732 case OPC1_16_SRO_LD_A:
3733 case OPC1_16_SRO_LD_BU:
3734 case OPC1_16_SRO_LD_H:
3735 case OPC1_16_SRO_LD_W:
3736 case OPC1_16_SRO_ST_A:
3737 case OPC1_16_SRO_ST_B:
3738 case OPC1_16_SRO_ST_H:
3739 case OPC1_16_SRO_ST_W:
3740 decode_sro_opc(ctx, op1);
3741 break;
3742 /* SSRO-format */
3743 case OPC1_16_SSRO_ST_A:
3744 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3745 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3746 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3747 break;
3748 case OPC1_16_SSRO_ST_B:
3749 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3750 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3751 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3752 break;
3753 case OPC1_16_SSRO_ST_H:
3754 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3755 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3756 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3757 break;
3758 case OPC1_16_SSRO_ST_W:
3759 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3760 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3761 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3762 break;
3763 /* SR-format */
3764 case OPCM_16_SR_SYSTEM:
3765 decode_sr_system(ctx);
3766 break;
3767 case OPCM_16_SR_ACCU:
3768 decode_sr_accu(ctx);
3769 break;
3770 case OPC1_16_SR_JI:
3771 r1 = MASK_OP_SR_S1D(ctx->opcode);
3772 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
3773 break;
3774 case OPC1_16_SR_NOT:
3775 r1 = MASK_OP_SR_S1D(ctx->opcode);
3776 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3777 break;
3778 default:
3779 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3780 }
3781 }
3782
3783 /*
3784 * 32 bit instructions
3785 */
3786
3787 /* ABS-format */
3788 static void decode_abs_ldw(DisasContext *ctx)
3789 {
3790 int32_t op2;
3791 int32_t r1;
3792 uint32_t address;
3793 TCGv temp;
3794
3795 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3796 address = MASK_OP_ABS_OFF18(ctx->opcode);
3797 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3798
3799 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3800
3801 switch (op2) {
3802 case OPC2_32_ABS_LD_A:
3803 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3804 break;
3805 case OPC2_32_ABS_LD_D:
3806 CHECK_REG_PAIR(r1);
3807 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3808 break;
3809 case OPC2_32_ABS_LD_DA:
3810 CHECK_REG_PAIR(r1);
3811 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3812 break;
3813 case OPC2_32_ABS_LD_W:
3814 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3815 break;
3816 default:
3817 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3818 }
3819 }
3820
3821 static void decode_abs_ldb(DisasContext *ctx)
3822 {
3823 int32_t op2;
3824 int32_t r1;
3825 uint32_t address;
3826 TCGv temp;
3827
3828 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3829 address = MASK_OP_ABS_OFF18(ctx->opcode);
3830 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3831
3832 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3833
3834 switch (op2) {
3835 case OPC2_32_ABS_LD_B:
3836 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
3837 break;
3838 case OPC2_32_ABS_LD_BU:
3839 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3840 break;
3841 case OPC2_32_ABS_LD_H:
3842 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
3843 break;
3844 case OPC2_32_ABS_LD_HU:
3845 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3846 break;
3847 default:
3848 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3849 }
3850 }
3851
3852 static void decode_abs_ldst_swap(DisasContext *ctx)
3853 {
3854 int32_t op2;
3855 int32_t r1;
3856 uint32_t address;
3857 TCGv temp;
3858
3859 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3860 address = MASK_OP_ABS_OFF18(ctx->opcode);
3861 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3862
3863 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3864
3865 switch (op2) {
3866 case OPC2_32_ABS_LDMST:
3867 gen_ldmst(ctx, r1, temp);
3868 break;
3869 case OPC2_32_ABS_SWAP_W:
3870 gen_swap(ctx, r1, temp);
3871 break;
3872 default:
3873 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3874 }
3875 }
3876
3877 static void decode_abs_ldst_context(DisasContext *ctx)
3878 {
3879 uint32_t op2;
3880 int32_t off18;
3881
3882 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
3883 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3884
3885 switch (op2) {
3886 case OPC2_32_ABS_LDLCX:
3887 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
3888 break;
3889 case OPC2_32_ABS_LDUCX:
3890 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
3891 break;
3892 case OPC2_32_ABS_STLCX:
3893 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
3894 break;
3895 case OPC2_32_ABS_STUCX:
3896 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
3897 break;
3898 default:
3899 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3900 }
3901 }
3902
3903 static void decode_abs_store(DisasContext *ctx)
3904 {
3905 int32_t op2;
3906 int32_t r1;
3907 uint32_t address;
3908 TCGv temp;
3909
3910 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3911 address = MASK_OP_ABS_OFF18(ctx->opcode);
3912 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3913
3914 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3915
3916 switch (op2) {
3917 case OPC2_32_ABS_ST_A:
3918 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3919 break;
3920 case OPC2_32_ABS_ST_D:
3921 CHECK_REG_PAIR(r1);
3922 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3923 break;
3924 case OPC2_32_ABS_ST_DA:
3925 CHECK_REG_PAIR(r1);
3926 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3927 break;
3928 case OPC2_32_ABS_ST_W:
3929 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3930 break;
3931 default:
3932 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3933 }
3934 }
3935
3936 static void decode_abs_storeb_h(DisasContext *ctx)
3937 {
3938 int32_t op2;
3939 int32_t r1;
3940 uint32_t address;
3941 TCGv temp;
3942
3943 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3944 address = MASK_OP_ABS_OFF18(ctx->opcode);
3945 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3946
3947 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
3948
3949 switch (op2) {
3950 case OPC2_32_ABS_ST_B:
3951 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3952 break;
3953 case OPC2_32_ABS_ST_H:
3954 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3955 break;
3956 default:
3957 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3958 }
3959 }
3960
3961 /* Bit-format */
3962
3963 static void decode_bit_andacc(DisasContext *ctx)
3964 {
3965 uint32_t op2;
3966 int r1, r2, r3;
3967 int pos1, pos2;
3968
3969 r1 = MASK_OP_BIT_S1(ctx->opcode);
3970 r2 = MASK_OP_BIT_S2(ctx->opcode);
3971 r3 = MASK_OP_BIT_D(ctx->opcode);
3972 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3973 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3974 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3975
3976
3977 switch (op2) {
3978 case OPC2_32_BIT_AND_AND_T:
3979 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3980 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
3981 break;
3982 case OPC2_32_BIT_AND_ANDN_T:
3983 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3984 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
3985 break;
3986 case OPC2_32_BIT_AND_NOR_T:
3987 if (TCG_TARGET_HAS_andc_i32) {
3988 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3989 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
3990 } else {
3991 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3992 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
3993 }
3994 break;
3995 case OPC2_32_BIT_AND_OR_T:
3996 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3997 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
3998 break;
3999 default:
4000 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4001 }
4002 }
4003
4004 static void decode_bit_logical_t(DisasContext *ctx)
4005 {
4006 uint32_t op2;
4007 int r1, r2, r3;
4008 int pos1, pos2;
4009 r1 = MASK_OP_BIT_S1(ctx->opcode);
4010 r2 = MASK_OP_BIT_S2(ctx->opcode);
4011 r3 = MASK_OP_BIT_D(ctx->opcode);
4012 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4013 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4014 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4015
4016 switch (op2) {
4017 case OPC2_32_BIT_AND_T:
4018 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4019 pos1, pos2, &tcg_gen_and_tl);
4020 break;
4021 case OPC2_32_BIT_ANDN_T:
4022 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4023 pos1, pos2, &tcg_gen_andc_tl);
4024 break;
4025 case OPC2_32_BIT_NOR_T:
4026 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4027 pos1, pos2, &tcg_gen_nor_tl);
4028 break;
4029 case OPC2_32_BIT_OR_T:
4030 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4031 pos1, pos2, &tcg_gen_or_tl);
4032 break;
4033 default:
4034 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4035 }
4036 }
4037
4038 static void decode_bit_insert(DisasContext *ctx)
4039 {
4040 uint32_t op2;
4041 int r1, r2, r3;
4042 int pos1, pos2;
4043 TCGv temp;
4044 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4045 r1 = MASK_OP_BIT_S1(ctx->opcode);
4046 r2 = MASK_OP_BIT_S2(ctx->opcode);
4047 r3 = MASK_OP_BIT_D(ctx->opcode);
4048 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4049 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4050
4051 temp = tcg_temp_new();
4052
4053 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4054 if (op2 == OPC2_32_BIT_INSN_T) {
4055 tcg_gen_not_tl(temp, temp);
4056 }
4057 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4058 }
4059
4060 static void decode_bit_logical_t2(DisasContext *ctx)
4061 {
4062 uint32_t op2;
4063
4064 int r1, r2, r3;
4065 int pos1, pos2;
4066
4067 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4068 r1 = MASK_OP_BIT_S1(ctx->opcode);
4069 r2 = MASK_OP_BIT_S2(ctx->opcode);
4070 r3 = MASK_OP_BIT_D(ctx->opcode);
4071 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4072 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4073
4074 switch (op2) {
4075 case OPC2_32_BIT_NAND_T:
4076 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4077 pos1, pos2, &tcg_gen_nand_tl);
4078 break;
4079 case OPC2_32_BIT_ORN_T:
4080 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4081 pos1, pos2, &tcg_gen_orc_tl);
4082 break;
4083 case OPC2_32_BIT_XNOR_T:
4084 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4085 pos1, pos2, &tcg_gen_eqv_tl);
4086 break;
4087 case OPC2_32_BIT_XOR_T:
4088 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4089 pos1, pos2, &tcg_gen_xor_tl);
4090 break;
4091 default:
4092 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4093 }
4094 }
4095
4096 static void decode_bit_orand(DisasContext *ctx)
4097 {
4098 uint32_t op2;
4099
4100 int r1, r2, r3;
4101 int pos1, pos2;
4102
4103 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4104 r1 = MASK_OP_BIT_S1(ctx->opcode);
4105 r2 = MASK_OP_BIT_S2(ctx->opcode);
4106 r3 = MASK_OP_BIT_D(ctx->opcode);
4107 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4108 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4109
4110 switch (op2) {
4111 case OPC2_32_BIT_OR_AND_T:
4112 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4113 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4114 break;
4115 case OPC2_32_BIT_OR_ANDN_T:
4116 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4117 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4118 break;
4119 case OPC2_32_BIT_OR_NOR_T:
4120 if (TCG_TARGET_HAS_orc_i32) {
4121 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4122 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4123 } else {
4124 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4125 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4126 }
4127 break;
4128 case OPC2_32_BIT_OR_OR_T:
4129 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4130 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4131 break;
4132 default:
4133 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4134 }
4135 }
4136
4137 static void decode_bit_sh_logic1(DisasContext *ctx)
4138 {
4139 uint32_t op2;
4140 int r1, r2, r3;
4141 int pos1, pos2;
4142 TCGv temp;
4143
4144 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4145 r1 = MASK_OP_BIT_S1(ctx->opcode);
4146 r2 = MASK_OP_BIT_S2(ctx->opcode);
4147 r3 = MASK_OP_BIT_D(ctx->opcode);
4148 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4149 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4150
4151 temp = tcg_temp_new();
4152
4153 switch (op2) {
4154 case OPC2_32_BIT_SH_AND_T:
4155 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4156 pos1, pos2, &tcg_gen_and_tl);
4157 break;
4158 case OPC2_32_BIT_SH_ANDN_T:
4159 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4160 pos1, pos2, &tcg_gen_andc_tl);
4161 break;
4162 case OPC2_32_BIT_SH_NOR_T:
4163 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4164 pos1, pos2, &tcg_gen_nor_tl);
4165 break;
4166 case OPC2_32_BIT_SH_OR_T:
4167 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4168 pos1, pos2, &tcg_gen_or_tl);
4169 break;
4170 default:
4171 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4172 }
4173 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4174 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4175 }
4176
4177 static void decode_bit_sh_logic2(DisasContext *ctx)
4178 {
4179 uint32_t op2;
4180 int r1, r2, r3;
4181 int pos1, pos2;
4182 TCGv temp;
4183
4184 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4185 r1 = MASK_OP_BIT_S1(ctx->opcode);
4186 r2 = MASK_OP_BIT_S2(ctx->opcode);
4187 r3 = MASK_OP_BIT_D(ctx->opcode);
4188 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4189 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4190
4191 temp = tcg_temp_new();
4192
4193 switch (op2) {
4194 case OPC2_32_BIT_SH_NAND_T:
4195 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4196 pos1, pos2, &tcg_gen_nand_tl);
4197 break;
4198 case OPC2_32_BIT_SH_ORN_T:
4199 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4200 pos1, pos2, &tcg_gen_orc_tl);
4201 break;
4202 case OPC2_32_BIT_SH_XNOR_T:
4203 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4204 pos1, pos2, &tcg_gen_eqv_tl);
4205 break;
4206 case OPC2_32_BIT_SH_XOR_T:
4207 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4208 pos1, pos2, &tcg_gen_xor_tl);
4209 break;
4210 default:
4211 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4212 }
4213 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4214 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4215 }
4216
4217 /* BO-format */
4218
4219
4220 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
4221 {
4222 uint32_t op2;
4223 uint32_t off10;
4224 int32_t r1, r2;
4225 TCGv temp;
4226
4227 r1 = MASK_OP_BO_S1D(ctx->opcode);
4228 r2 = MASK_OP_BO_S2(ctx->opcode);
4229 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4230 op2 = MASK_OP_BO_OP2(ctx->opcode);
4231
4232 switch (op2) {
4233 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4234 case OPC2_32_BO_CACHEA_W_SHORTOFF:
4235 case OPC2_32_BO_CACHEA_I_SHORTOFF:
4236 /* instruction to access the cache */
4237 break;
4238 case OPC2_32_BO_CACHEA_WI_POSTINC:
4239 case OPC2_32_BO_CACHEA_W_POSTINC:
4240 case OPC2_32_BO_CACHEA_I_POSTINC:
4241 /* instruction to access the cache, but we still need to handle
4242 the addressing mode */
4243 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4244 break;
4245 case OPC2_32_BO_CACHEA_WI_PREINC:
4246 case OPC2_32_BO_CACHEA_W_PREINC:
4247 case OPC2_32_BO_CACHEA_I_PREINC:
4248 /* instruction to access the cache, but we still need to handle
4249 the addressing mode */
4250 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4251 break;
4252 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4253 case OPC2_32_BO_CACHEI_W_SHORTOFF:
4254 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
4255 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4256 }
4257 break;
4258 case OPC2_32_BO_CACHEI_W_POSTINC:
4259 case OPC2_32_BO_CACHEI_WI_POSTINC:
4260 if (has_feature(ctx, TRICORE_FEATURE_131)) {
4261 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4262 } else {
4263 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4264 }
4265 break;
4266 case OPC2_32_BO_CACHEI_W_PREINC:
4267 case OPC2_32_BO_CACHEI_WI_PREINC:
4268 if (has_feature(ctx, TRICORE_FEATURE_131)) {
4269 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4270 } else {
4271 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4272 }
4273 break;
4274 case OPC2_32_BO_ST_A_SHORTOFF:
4275 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4276 break;
4277 case OPC2_32_BO_ST_A_POSTINC:
4278 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4279 MO_LESL);
4280 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4281 break;
4282 case OPC2_32_BO_ST_A_PREINC:
4283 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4284 break;
4285 case OPC2_32_BO_ST_B_SHORTOFF:
4286 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4287 break;
4288 case OPC2_32_BO_ST_B_POSTINC:
4289 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4290 MO_UB);
4291 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4292 break;
4293 case OPC2_32_BO_ST_B_PREINC:
4294 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4295 break;
4296 case OPC2_32_BO_ST_D_SHORTOFF:
4297 CHECK_REG_PAIR(r1);
4298 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4299 off10, ctx);
4300 break;
4301 case OPC2_32_BO_ST_D_POSTINC:
4302 CHECK_REG_PAIR(r1);
4303 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4304 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4305 break;
4306 case OPC2_32_BO_ST_D_PREINC:
4307 CHECK_REG_PAIR(r1);
4308 temp = tcg_temp_new();
4309 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4310 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4311 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4312 break;
4313 case OPC2_32_BO_ST_DA_SHORTOFF:
4314 CHECK_REG_PAIR(r1);
4315 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4316 off10, ctx);
4317 break;
4318 case OPC2_32_BO_ST_DA_POSTINC:
4319 CHECK_REG_PAIR(r1);
4320 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4321 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4322 break;
4323 case OPC2_32_BO_ST_DA_PREINC:
4324 CHECK_REG_PAIR(r1);
4325 temp = tcg_temp_new();
4326 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4327 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4328 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4329 break;
4330 case OPC2_32_BO_ST_H_SHORTOFF:
4331 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4332 break;
4333 case OPC2_32_BO_ST_H_POSTINC:
4334 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4335 MO_LEUW);
4336 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4337 break;
4338 case OPC2_32_BO_ST_H_PREINC:
4339 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4340 break;
4341 case OPC2_32_BO_ST_Q_SHORTOFF:
4342 temp = tcg_temp_new();
4343 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4344 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4345 break;
4346 case OPC2_32_BO_ST_Q_POSTINC:
4347 temp = tcg_temp_new();
4348 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4349 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4350 MO_LEUW);
4351 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4352 break;
4353 case OPC2_32_BO_ST_Q_PREINC:
4354 temp = tcg_temp_new();
4355 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4356 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4357 break;
4358 case OPC2_32_BO_ST_W_SHORTOFF:
4359 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4360 break;
4361 case OPC2_32_BO_ST_W_POSTINC:
4362 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4363 MO_LEUL);
4364 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4365 break;
4366 case OPC2_32_BO_ST_W_PREINC:
4367 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4368 break;
4369 default:
4370 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4371 }
4372 }
4373
4374 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
4375 {
4376 uint32_t op2;
4377 uint32_t off10;
4378 int32_t r1, r2;
4379 TCGv temp, temp2, t_off10;
4380
4381 r1 = MASK_OP_BO_S1D(ctx->opcode);
4382 r2 = MASK_OP_BO_S2(ctx->opcode);
4383 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4384 op2 = MASK_OP_BO_OP2(ctx->opcode);
4385
4386 temp = tcg_temp_new();
4387 temp2 = tcg_temp_new();
4388 t_off10 = tcg_constant_i32(off10);
4389 CHECK_REG_PAIR(r2);
4390 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4391 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4392
4393 switch (op2) {
4394 case OPC2_32_BO_CACHEA_WI_BR:
4395 case OPC2_32_BO_CACHEA_W_BR:
4396 case OPC2_32_BO_CACHEA_I_BR:
4397 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4398 break;
4399 case OPC2_32_BO_CACHEA_WI_CIRC:
4400 case OPC2_32_BO_CACHEA_W_CIRC:
4401 case OPC2_32_BO_CACHEA_I_CIRC:
4402 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4403 break;
4404 case OPC2_32_BO_ST_A_BR:
4405 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4406 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4407 break;
4408 case OPC2_32_BO_ST_A_CIRC:
4409 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4410 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4411 break;
4412 case OPC2_32_BO_ST_B_BR:
4413 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4414 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4415 break;
4416 case OPC2_32_BO_ST_B_CIRC:
4417 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4418 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4419 break;
4420 case OPC2_32_BO_ST_D_BR:
4421 CHECK_REG_PAIR(r1);
4422 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4423 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4424 break;
4425 case OPC2_32_BO_ST_D_CIRC:
4426 CHECK_REG_PAIR(r1);
4427 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4428 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4429 tcg_gen_addi_tl(temp, temp, 4);
4430 tcg_gen_rem_tl(temp, temp, temp2);
4431 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4432 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4433 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4434 break;
4435 case OPC2_32_BO_ST_DA_BR:
4436 CHECK_REG_PAIR(r1);
4437 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4438 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4439 break;
4440 case OPC2_32_BO_ST_DA_CIRC:
4441 CHECK_REG_PAIR(r1);
4442 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4443 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4444 tcg_gen_addi_tl(temp, temp, 4);
4445 tcg_gen_rem_tl(temp, temp, temp2);
4446 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4447 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4448 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4449 break;
4450 case OPC2_32_BO_ST_H_BR:
4451 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4452 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4453 break;
4454 case OPC2_32_BO_ST_H_CIRC:
4455 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4456 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4457 break;
4458 case OPC2_32_BO_ST_Q_BR:
4459 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4460 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4461 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4462 break;
4463 case OPC2_32_BO_ST_Q_CIRC:
4464 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4465 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4466 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4467 break;
4468 case OPC2_32_BO_ST_W_BR:
4469 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4470 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4471 break;
4472 case OPC2_32_BO_ST_W_CIRC:
4473 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4474 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4475 break;
4476 default:
4477 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4478 }
4479 }
4480
4481 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
4482 {
4483 uint32_t op2;
4484 uint32_t off10;
4485 int32_t r1, r2;
4486 TCGv temp;
4487
4488 r1 = MASK_OP_BO_S1D(ctx->opcode);
4489 r2 = MASK_OP_BO_S2(ctx->opcode);
4490 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4491 op2 = MASK_OP_BO_OP2(ctx->opcode);
4492
4493 switch (op2) {
4494 case OPC2_32_BO_LD_A_SHORTOFF:
4495 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4496 break;
4497 case OPC2_32_BO_LD_A_POSTINC:
4498 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4499 MO_LEUL);
4500 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4501 break;
4502 case OPC2_32_BO_LD_A_PREINC:
4503 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4504 break;
4505 case OPC2_32_BO_LD_B_SHORTOFF:
4506 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4507 break;
4508 case OPC2_32_BO_LD_B_POSTINC:
4509 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4510 MO_SB);
4511 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4512 break;
4513 case OPC2_32_BO_LD_B_PREINC:
4514 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4515 break;
4516 case OPC2_32_BO_LD_BU_SHORTOFF:
4517 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4518 break;
4519 case OPC2_32_BO_LD_BU_POSTINC:
4520 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4521 MO_UB);
4522 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4523 break;
4524 case OPC2_32_BO_LD_BU_PREINC:
4525 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4526 break;
4527 case OPC2_32_BO_LD_D_SHORTOFF:
4528 CHECK_REG_PAIR(r1);
4529 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4530 off10, ctx);
4531 break;
4532 case OPC2_32_BO_LD_D_POSTINC:
4533 CHECK_REG_PAIR(r1);
4534 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4535 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4536 break;
4537 case OPC2_32_BO_LD_D_PREINC:
4538 CHECK_REG_PAIR(r1);
4539 temp = tcg_temp_new();
4540 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4541 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4542 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4543 break;
4544 case OPC2_32_BO_LD_DA_SHORTOFF:
4545 CHECK_REG_PAIR(r1);
4546 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4547 off10, ctx);
4548 break;
4549 case OPC2_32_BO_LD_DA_POSTINC:
4550 CHECK_REG_PAIR(r1);
4551 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4552 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4553 break;
4554 case OPC2_32_BO_LD_DA_PREINC:
4555 CHECK_REG_PAIR(r1);
4556 temp = tcg_temp_new();
4557 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4558 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4559 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4560 break;
4561 case OPC2_32_BO_LD_H_SHORTOFF:
4562 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4563 break;
4564 case OPC2_32_BO_LD_H_POSTINC:
4565 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4566 MO_LESW);
4567 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4568 break;
4569 case OPC2_32_BO_LD_H_PREINC:
4570 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4571 break;
4572 case OPC2_32_BO_LD_HU_SHORTOFF:
4573 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4574 break;
4575 case OPC2_32_BO_LD_HU_POSTINC:
4576 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4577 MO_LEUW);
4578 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4579 break;
4580 case OPC2_32_BO_LD_HU_PREINC:
4581 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4582 break;
4583 case OPC2_32_BO_LD_Q_SHORTOFF:
4584 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4585 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4586 break;
4587 case OPC2_32_BO_LD_Q_POSTINC:
4588 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4589 MO_LEUW);
4590 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4591 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4592 break;
4593 case OPC2_32_BO_LD_Q_PREINC:
4594 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4595 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4596 break;
4597 case OPC2_32_BO_LD_W_SHORTOFF:
4598 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4599 break;
4600 case OPC2_32_BO_LD_W_POSTINC:
4601 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4602 MO_LEUL);
4603 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4604 break;
4605 case OPC2_32_BO_LD_W_PREINC:
4606 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4607 break;
4608 default:
4609 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4610 }
4611 }
4612
4613 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
4614 {
4615 uint32_t op2;
4616 uint32_t off10;
4617 int r1, r2;
4618 TCGv temp, temp2, t_off10;
4619
4620 r1 = MASK_OP_BO_S1D(ctx->opcode);
4621 r2 = MASK_OP_BO_S2(ctx->opcode);
4622 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4623 op2 = MASK_OP_BO_OP2(ctx->opcode);
4624
4625 temp = tcg_temp_new();
4626 temp2 = tcg_temp_new();
4627 t_off10 = tcg_constant_i32(off10);
4628 CHECK_REG_PAIR(r2);
4629 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4630 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4631
4632
4633 switch (op2) {
4634 case OPC2_32_BO_LD_A_BR:
4635 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4636 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4637 break;
4638 case OPC2_32_BO_LD_A_CIRC:
4639 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4640 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4641 break;
4642 case OPC2_32_BO_LD_B_BR:
4643 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4644 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4645 break;
4646 case OPC2_32_BO_LD_B_CIRC:
4647 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4648 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4649 break;
4650 case OPC2_32_BO_LD_BU_BR:
4651 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4652 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4653 break;
4654 case OPC2_32_BO_LD_BU_CIRC:
4655 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4656 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4657 break;
4658 case OPC2_32_BO_LD_D_BR:
4659 CHECK_REG_PAIR(r1);
4660 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4661 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4662 break;
4663 case OPC2_32_BO_LD_D_CIRC:
4664 CHECK_REG_PAIR(r1);
4665 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4666 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4667 tcg_gen_addi_tl(temp, temp, 4);
4668 tcg_gen_rem_tl(temp, temp, temp2);
4669 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4670 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4671 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4672 break;
4673 case OPC2_32_BO_LD_DA_BR:
4674 CHECK_REG_PAIR(r1);
4675 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4676 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4677 break;
4678 case OPC2_32_BO_LD_DA_CIRC:
4679 CHECK_REG_PAIR(r1);
4680 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4681 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4682 tcg_gen_addi_tl(temp, temp, 4);
4683 tcg_gen_rem_tl(temp, temp, temp2);
4684 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4685 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4686 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4687 break;
4688 case OPC2_32_BO_LD_H_BR:
4689 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4690 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4691 break;
4692 case OPC2_32_BO_LD_H_CIRC:
4693 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4694 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4695 break;
4696 case OPC2_32_BO_LD_HU_BR:
4697 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4698 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4699 break;
4700 case OPC2_32_BO_LD_HU_CIRC:
4701 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4702 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4703 break;
4704 case OPC2_32_BO_LD_Q_BR:
4705 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4706 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4707 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4708 break;
4709 case OPC2_32_BO_LD_Q_CIRC:
4710 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4711 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4712 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4713 break;
4714 case OPC2_32_BO_LD_W_BR:
4715 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4716 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4717 break;
4718 case OPC2_32_BO_LD_W_CIRC:
4719 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4720 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4721 break;
4722 default:
4723 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4724 }
4725 }
4726
4727 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx)
4728 {
4729 uint32_t op2;
4730 uint32_t off10;
4731 int r1, r2;
4732
4733 TCGv temp;
4734
4735 r1 = MASK_OP_BO_S1D(ctx->opcode);
4736 r2 = MASK_OP_BO_S2(ctx->opcode);
4737 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4738 op2 = MASK_OP_BO_OP2(ctx->opcode);
4739
4740
4741 temp = tcg_temp_new();
4742
4743 switch (op2) {
4744 case OPC2_32_BO_LDLCX_SHORTOFF:
4745 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4746 gen_helper_ldlcx(cpu_env, temp);
4747 break;
4748 case OPC2_32_BO_LDMST_SHORTOFF:
4749 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4750 gen_ldmst(ctx, r1, temp);
4751 break;
4752 case OPC2_32_BO_LDMST_POSTINC:
4753 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4754 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4755 break;
4756 case OPC2_32_BO_LDMST_PREINC:
4757 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4758 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4759 break;
4760 case OPC2_32_BO_LDUCX_SHORTOFF:
4761 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4762 gen_helper_lducx(cpu_env, temp);
4763 break;
4764 case OPC2_32_BO_LEA_SHORTOFF:
4765 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
4766 break;
4767 case OPC2_32_BO_STLCX_SHORTOFF:
4768 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4769 gen_helper_stlcx(cpu_env, temp);
4770 break;
4771 case OPC2_32_BO_STUCX_SHORTOFF:
4772 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4773 gen_helper_stucx(cpu_env, temp);
4774 break;
4775 case OPC2_32_BO_SWAP_W_SHORTOFF:
4776 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4777 gen_swap(ctx, r1, temp);
4778 break;
4779 case OPC2_32_BO_SWAP_W_POSTINC:
4780 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4781 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4782 break;
4783 case OPC2_32_BO_SWAP_W_PREINC:
4784 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4785 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4786 break;
4787 case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
4788 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4789 gen_cmpswap(ctx, r1, temp);
4790 break;
4791 case OPC2_32_BO_CMPSWAP_W_POSTINC:
4792 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
4793 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4794 break;
4795 case OPC2_32_BO_CMPSWAP_W_PREINC:
4796 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4797 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
4798 break;
4799 case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
4800 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4801 gen_swapmsk(ctx, r1, temp);
4802 break;
4803 case OPC2_32_BO_SWAPMSK_W_POSTINC:
4804 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
4805 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4806 break;
4807 case OPC2_32_BO_SWAPMSK_W_PREINC:
4808 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4809 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
4810 break;
4811 default:
4812 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4813 }
4814 }
4815
4816 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
4817 {
4818 uint32_t op2;
4819 uint32_t off10;
4820 int r1, r2;
4821 TCGv temp, temp2, t_off10;
4822
4823 r1 = MASK_OP_BO_S1D(ctx->opcode);
4824 r2 = MASK_OP_BO_S2(ctx->opcode);
4825 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4826 op2 = MASK_OP_BO_OP2(ctx->opcode);
4827
4828 temp = tcg_temp_new();
4829 temp2 = tcg_temp_new();
4830 t_off10 = tcg_constant_i32(off10);
4831 CHECK_REG_PAIR(r2);
4832 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4833 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4834
4835 switch (op2) {
4836 case OPC2_32_BO_LDMST_BR:
4837 gen_ldmst(ctx, r1, temp2);
4838 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4839 break;
4840 case OPC2_32_BO_LDMST_CIRC:
4841 gen_ldmst(ctx, r1, temp2);
4842 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4843 break;
4844 case OPC2_32_BO_SWAP_W_BR:
4845 gen_swap(ctx, r1, temp2);
4846 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4847 break;
4848 case OPC2_32_BO_SWAP_W_CIRC:
4849 gen_swap(ctx, r1, temp2);
4850 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4851 break;
4852 case OPC2_32_BO_CMPSWAP_W_BR:
4853 gen_cmpswap(ctx, r1, temp2);
4854 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4855 break;
4856 case OPC2_32_BO_CMPSWAP_W_CIRC:
4857 gen_cmpswap(ctx, r1, temp2);
4858 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4859 break;
4860 case OPC2_32_BO_SWAPMSK_W_BR:
4861 gen_swapmsk(ctx, r1, temp2);
4862 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4863 break;
4864 case OPC2_32_BO_SWAPMSK_W_CIRC:
4865 gen_swapmsk(ctx, r1, temp2);
4866 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], t_off10);
4867 break;
4868 default:
4869 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4870 }
4871 }
4872
4873 static void decode_bol_opc(DisasContext *ctx, int32_t op1)
4874 {
4875 int r1, r2;
4876 int32_t address;
4877 TCGv temp;
4878
4879 r1 = MASK_OP_BOL_S1D(ctx->opcode);
4880 r2 = MASK_OP_BOL_S2(ctx->opcode);
4881 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
4882
4883 switch (op1) {
4884 case OPC1_32_BOL_LD_A_LONGOFF:
4885 temp = tcg_temp_new();
4886 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4887 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
4888 break;
4889 case OPC1_32_BOL_LD_W_LONGOFF:
4890 temp = tcg_temp_new();
4891 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4892 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
4893 break;
4894 case OPC1_32_BOL_LEA_LONGOFF:
4895 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
4896 break;
4897 case OPC1_32_BOL_ST_A_LONGOFF:
4898 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4899 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
4900 } else {
4901 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4902 }
4903 break;
4904 case OPC1_32_BOL_ST_W_LONGOFF:
4905 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
4906 break;
4907 case OPC1_32_BOL_LD_B_LONGOFF:
4908 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4909 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4910 } else {
4911 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4912 }
4913 break;
4914 case OPC1_32_BOL_LD_BU_LONGOFF:
4915 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4916 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
4917 } else {
4918 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4919 }
4920 break;
4921 case OPC1_32_BOL_LD_H_LONGOFF:
4922 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4923 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4924 } else {
4925 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4926 }
4927 break;
4928 case OPC1_32_BOL_LD_HU_LONGOFF:
4929 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4930 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
4931 } else {
4932 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4933 }
4934 break;
4935 case OPC1_32_BOL_ST_B_LONGOFF:
4936 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4937 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4938 } else {
4939 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4940 }
4941 break;
4942 case OPC1_32_BOL_ST_H_LONGOFF:
4943 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4944 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4945 } else {
4946 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4947 }
4948 break;
4949 default:
4950 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4951 }
4952 }
4953
4954 /* RC format */
4955 static void decode_rc_logical_shift(DisasContext *ctx)
4956 {
4957 uint32_t op2;
4958 int r1, r2;
4959 int32_t const9;
4960 TCGv temp;
4961
4962 r2 = MASK_OP_RC_D(ctx->opcode);
4963 r1 = MASK_OP_RC_S1(ctx->opcode);
4964 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4965 op2 = MASK_OP_RC_OP2(ctx->opcode);
4966
4967 temp = tcg_temp_new();
4968
4969 switch (op2) {
4970 case OPC2_32_RC_AND:
4971 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4972 break;
4973 case OPC2_32_RC_ANDN:
4974 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4975 break;
4976 case OPC2_32_RC_NAND:
4977 tcg_gen_movi_tl(temp, const9);
4978 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4979 break;
4980 case OPC2_32_RC_NOR:
4981 tcg_gen_movi_tl(temp, const9);
4982 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4983 break;
4984 case OPC2_32_RC_OR:
4985 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4986 break;
4987 case OPC2_32_RC_ORN:
4988 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4989 break;
4990 case OPC2_32_RC_SH:
4991 const9 = sextract32(const9, 0, 6);
4992 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4993 break;
4994 case OPC2_32_RC_SH_H:
4995 const9 = sextract32(const9, 0, 5);
4996 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4997 break;
4998 case OPC2_32_RC_SHA:
4999 const9 = sextract32(const9, 0, 6);
5000 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5001 break;
5002 case OPC2_32_RC_SHA_H:
5003 const9 = sextract32(const9, 0, 5);
5004 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5005 break;
5006 case OPC2_32_RC_SHAS:
5007 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5008 break;
5009 case OPC2_32_RC_XNOR:
5010 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5011 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
5012 break;
5013 case OPC2_32_RC_XOR:
5014 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5015 break;
5016 case OPC2_32_RC_SHUFFLE:
5017 if (has_feature(ctx, TRICORE_FEATURE_162)) {
5018 TCGv temp = tcg_constant_i32(const9);
5019 gen_helper_shuffle(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5020 } else {
5021 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5022 }
5023 break;
5024 default:
5025 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5026 }
5027 }
5028
5029 static void decode_rc_accumulator(DisasContext *ctx)
5030 {
5031 uint32_t op2;
5032 int r1, r2;
5033 int16_t const9;
5034
5035 TCGv temp;
5036
5037 r2 = MASK_OP_RC_D(ctx->opcode);
5038 r1 = MASK_OP_RC_S1(ctx->opcode);
5039 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5040
5041 op2 = MASK_OP_RC_OP2(ctx->opcode);
5042
5043 temp = tcg_temp_new();
5044
5045 switch (op2) {
5046 case OPC2_32_RC_ABSDIF:
5047 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5048 break;
5049 case OPC2_32_RC_ABSDIFS:
5050 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5051 break;
5052 case OPC2_32_RC_ADD:
5053 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5054 break;
5055 case OPC2_32_RC_ADDC:
5056 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5057 break;
5058 case OPC2_32_RC_ADDS:
5059 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5060 break;
5061 case OPC2_32_RC_ADDS_U:
5062 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5063 break;
5064 case OPC2_32_RC_ADDX:
5065 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5066 break;
5067 case OPC2_32_RC_AND_EQ:
5068 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5069 const9, &tcg_gen_and_tl);
5070 break;
5071 case OPC2_32_RC_AND_GE:
5072 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5073 const9, &tcg_gen_and_tl);
5074 break;
5075 case OPC2_32_RC_AND_GE_U:
5076 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5077 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5078 const9, &tcg_gen_and_tl);
5079 break;
5080 case OPC2_32_RC_AND_LT:
5081 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5082 const9, &tcg_gen_and_tl);
5083 break;
5084 case OPC2_32_RC_AND_LT_U:
5085 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5086 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5087 const9, &tcg_gen_and_tl);
5088 break;
5089 case OPC2_32_RC_AND_NE:
5090 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5091 const9, &tcg_gen_and_tl);
5092 break;
5093 case OPC2_32_RC_EQ:
5094 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5095 break;
5096 case OPC2_32_RC_EQANY_B:
5097 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5098 break;
5099 case OPC2_32_RC_EQANY_H:
5100 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5101 break;
5102 case OPC2_32_RC_GE:
5103 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5104 break;
5105 case OPC2_32_RC_GE_U:
5106 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5107 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5108 break;
5109 case OPC2_32_RC_LT:
5110 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5111 break;
5112 case OPC2_32_RC_LT_U:
5113 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5114 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5115 break;
5116 case OPC2_32_RC_MAX:
5117 tcg_gen_movi_tl(temp, const9);
5118 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5119 cpu_gpr_d[r1], temp);
5120 break;
5121 case OPC2_32_RC_MAX_U:
5122 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5123 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5124 cpu_gpr_d[r1], temp);
5125 break;
5126 case OPC2_32_RC_MIN:
5127 tcg_gen_movi_tl(temp, const9);
5128 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5129 cpu_gpr_d[r1], temp);
5130 break;
5131 case OPC2_32_RC_MIN_U:
5132 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5133 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5134 cpu_gpr_d[r1], temp);
5135 break;
5136 case OPC2_32_RC_NE:
5137 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5138 break;
5139 case OPC2_32_RC_OR_EQ:
5140 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5141 const9, &tcg_gen_or_tl);
5142 break;
5143 case OPC2_32_RC_OR_GE:
5144 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5145 const9, &tcg_gen_or_tl);
5146 break;
5147 case OPC2_32_RC_OR_GE_U:
5148 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5149 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5150 const9, &tcg_gen_or_tl);
5151 break;
5152 case OPC2_32_RC_OR_LT:
5153 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5154 const9, &tcg_gen_or_tl);
5155 break;
5156 case OPC2_32_RC_OR_LT_U:
5157 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5158 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5159 const9, &tcg_gen_or_tl);
5160 break;
5161 case OPC2_32_RC_OR_NE:
5162 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5163 const9, &tcg_gen_or_tl);
5164 break;
5165 case OPC2_32_RC_RSUB:
5166 tcg_gen_movi_tl(temp, const9);
5167 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5168 break;
5169 case OPC2_32_RC_RSUBS:
5170 tcg_gen_movi_tl(temp, const9);
5171 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5172 break;
5173 case OPC2_32_RC_RSUBS_U:
5174 tcg_gen_movi_tl(temp, const9);
5175 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5176 break;
5177 case OPC2_32_RC_SH_EQ:
5178 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5179 break;
5180 case OPC2_32_RC_SH_GE:
5181 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5182 break;
5183 case OPC2_32_RC_SH_GE_U:
5184 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5185 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5186 break;
5187 case OPC2_32_RC_SH_LT:
5188 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5189 break;
5190 case OPC2_32_RC_SH_LT_U:
5191 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5192 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5193 break;
5194 case OPC2_32_RC_SH_NE:
5195 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5196 break;
5197 case OPC2_32_RC_XOR_EQ:
5198 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5199 const9, &tcg_gen_xor_tl);
5200 break;
5201 case OPC2_32_RC_XOR_GE:
5202 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5203 const9, &tcg_gen_xor_tl);
5204 break;
5205 case OPC2_32_RC_XOR_GE_U:
5206 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5207 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5208 const9, &tcg_gen_xor_tl);
5209 break;
5210 case OPC2_32_RC_XOR_LT:
5211 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5212 const9, &tcg_gen_xor_tl);
5213 break;
5214 case OPC2_32_RC_XOR_LT_U:
5215 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5216 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5217 const9, &tcg_gen_xor_tl);
5218 break;
5219 case OPC2_32_RC_XOR_NE:
5220 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5221 const9, &tcg_gen_xor_tl);
5222 break;
5223 default:
5224 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5225 }
5226 }
5227
5228 static void decode_rc_serviceroutine(DisasContext *ctx)
5229 {
5230 uint32_t op2;
5231 uint32_t const9;
5232
5233 op2 = MASK_OP_RC_OP2(ctx->opcode);
5234 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5235
5236 switch (op2) {
5237 case OPC2_32_RC_BISR:
5238 gen_helper_1arg(bisr, const9);
5239 break;
5240 case OPC2_32_RC_SYSCALL:
5241 generate_trap(ctx, TRAPC_SYSCALL, const9 & 0xff);
5242 break;
5243 default:
5244 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5245 }
5246 }
5247
5248 static void decode_rc_mul(DisasContext *ctx)
5249 {
5250 uint32_t op2;
5251 int r1, r2;
5252 int16_t const9;
5253
5254 r2 = MASK_OP_RC_D(ctx->opcode);
5255 r1 = MASK_OP_RC_S1(ctx->opcode);
5256 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5257
5258 op2 = MASK_OP_RC_OP2(ctx->opcode);
5259
5260 switch (op2) {
5261 case OPC2_32_RC_MUL_32:
5262 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5263 break;
5264 case OPC2_32_RC_MUL_64:
5265 CHECK_REG_PAIR(r2);
5266 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5267 break;
5268 case OPC2_32_RC_MULS_32:
5269 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5270 break;
5271 case OPC2_32_RC_MUL_U_64:
5272 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5273 CHECK_REG_PAIR(r2);
5274 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5275 break;
5276 case OPC2_32_RC_MULS_U_32:
5277 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5278 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5279 break;
5280 default:
5281 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5282 }
5283 }
5284
5285 /* RCPW format */
5286 static void decode_rcpw_insert(DisasContext *ctx)
5287 {
5288 uint32_t op2;
5289 int r1, r2;
5290 int32_t pos, width, const4;
5291
5292 TCGv temp;
5293
5294 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
5295 r1 = MASK_OP_RCPW_S1(ctx->opcode);
5296 r2 = MASK_OP_RCPW_D(ctx->opcode);
5297 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
5298 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
5299 pos = MASK_OP_RCPW_POS(ctx->opcode);
5300
5301 switch (op2) {
5302 case OPC2_32_RCPW_IMASK:
5303 CHECK_REG_PAIR(r2);
5304 /* if pos + width > 32 undefined result */
5305 if (pos + width <= 32) {
5306 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
5307 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
5308 }
5309 break;
5310 case OPC2_32_RCPW_INSERT:
5311 /* if pos + width > 32 undefined result */
5312 if (pos + width <= 32) {
5313 temp = tcg_constant_i32(const4);
5314 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
5315 }
5316 break;
5317 default:
5318 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5319 }
5320 }
5321
5322 /* RCRW format */
5323
5324 static void decode_rcrw_insert(DisasContext *ctx)
5325 {
5326 uint32_t op2;
5327 int r1, r3, r4;
5328 int32_t width, const4;
5329
5330 TCGv temp, temp2, temp3;
5331
5332 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
5333 r1 = MASK_OP_RCRW_S1(ctx->opcode);
5334 r3 = MASK_OP_RCRW_S3(ctx->opcode);
5335 r4 = MASK_OP_RCRW_D(ctx->opcode);
5336 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
5337 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
5338
5339 temp = tcg_temp_new();
5340 temp2 = tcg_temp_new();
5341
5342 switch (op2) {
5343 case OPC2_32_RCRW_IMASK:
5344 CHECK_REG_PAIR(r4);
5345 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
5346 tcg_gen_movi_tl(temp2, (1 << width) - 1);
5347 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
5348 tcg_gen_movi_tl(temp2, const4);
5349 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
5350 break;
5351 case OPC2_32_RCRW_INSERT:
5352 temp3 = tcg_temp_new();
5353
5354 tcg_gen_movi_tl(temp, width);
5355 tcg_gen_movi_tl(temp2, const4);
5356 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
5357 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
5358 break;
5359 default:
5360 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5361 }
5362 }
5363
5364 /* RCR format */
5365
5366 static void decode_rcr_cond_select(DisasContext *ctx)
5367 {
5368 uint32_t op2;
5369 int r1, r3, r4;
5370 int32_t const9;
5371
5372 TCGv temp, temp2;
5373
5374 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5375 r1 = MASK_OP_RCR_S1(ctx->opcode);
5376 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5377 r3 = MASK_OP_RCR_S3(ctx->opcode);
5378 r4 = MASK_OP_RCR_D(ctx->opcode);
5379
5380 switch (op2) {
5381 case OPC2_32_RCR_CADD:
5382 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
5383 cpu_gpr_d[r3]);
5384 break;
5385 case OPC2_32_RCR_CADDN:
5386 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
5387 cpu_gpr_d[r3]);
5388 break;
5389 case OPC2_32_RCR_SEL:
5390 temp = tcg_constant_i32(0);
5391 temp2 = tcg_constant_i32(const9);
5392 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5393 cpu_gpr_d[r1], temp2);
5394 break;
5395 case OPC2_32_RCR_SELN:
5396 temp = tcg_constant_i32(0);
5397 temp2 = tcg_constant_i32(const9);
5398 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5399 cpu_gpr_d[r1], temp2);
5400 break;
5401 default:
5402 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5403 }
5404 }
5405
5406 static void decode_rcr_madd(DisasContext *ctx)
5407 {
5408 uint32_t op2;
5409 int r1, r3, r4;
5410 int32_t const9;
5411
5412
5413 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5414 r1 = MASK_OP_RCR_S1(ctx->opcode);
5415 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5416 r3 = MASK_OP_RCR_S3(ctx->opcode);
5417 r4 = MASK_OP_RCR_D(ctx->opcode);
5418
5419 switch (op2) {
5420 case OPC2_32_RCR_MADD_32:
5421 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5422 break;
5423 case OPC2_32_RCR_MADD_64:
5424 CHECK_REG_PAIR(r4);
5425 CHECK_REG_PAIR(r3);
5426 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5427 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5428 break;
5429 case OPC2_32_RCR_MADDS_32:
5430 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5431 break;
5432 case OPC2_32_RCR_MADDS_64:
5433 CHECK_REG_PAIR(r4);
5434 CHECK_REG_PAIR(r3);
5435 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5436 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5437 break;
5438 case OPC2_32_RCR_MADD_U_64:
5439 CHECK_REG_PAIR(r4);
5440 CHECK_REG_PAIR(r3);
5441 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5442 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5443 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5444 break;
5445 case OPC2_32_RCR_MADDS_U_32:
5446 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5447 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5448 break;
5449 case OPC2_32_RCR_MADDS_U_64:
5450 CHECK_REG_PAIR(r4);
5451 CHECK_REG_PAIR(r3);
5452 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5453 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5454 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5455 break;
5456 default:
5457 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5458 }
5459 }
5460
5461 static void decode_rcr_msub(DisasContext *ctx)
5462 {
5463 uint32_t op2;
5464 int r1, r3, r4;
5465 int32_t const9;
5466
5467
5468 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5469 r1 = MASK_OP_RCR_S1(ctx->opcode);
5470 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5471 r3 = MASK_OP_RCR_S3(ctx->opcode);
5472 r4 = MASK_OP_RCR_D(ctx->opcode);
5473
5474 switch (op2) {
5475 case OPC2_32_RCR_MSUB_32:
5476 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5477 break;
5478 case OPC2_32_RCR_MSUB_64:
5479 CHECK_REG_PAIR(r4);
5480 CHECK_REG_PAIR(r3);
5481 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5482 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5483 break;
5484 case OPC2_32_RCR_MSUBS_32:
5485 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5486 break;
5487 case OPC2_32_RCR_MSUBS_64:
5488 CHECK_REG_PAIR(r4);
5489 CHECK_REG_PAIR(r3);
5490 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5491 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5492 break;
5493 case OPC2_32_RCR_MSUB_U_64:
5494 CHECK_REG_PAIR(r4);
5495 CHECK_REG_PAIR(r3);
5496 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5497 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5498 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5499 break;
5500 case OPC2_32_RCR_MSUBS_U_32:
5501 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5502 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5503 break;
5504 case OPC2_32_RCR_MSUBS_U_64:
5505 CHECK_REG_PAIR(r4);
5506 CHECK_REG_PAIR(r3);
5507 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5508 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5509 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5510 break;
5511 default:
5512 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5513 }
5514 }
5515
5516 /* RLC format */
5517
5518 static void decode_rlc_opc(DisasContext *ctx,
5519 uint32_t op1)
5520 {
5521 int32_t const16;
5522 int r1, r2;
5523
5524 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
5525 r1 = MASK_OP_RLC_S1(ctx->opcode);
5526 r2 = MASK_OP_RLC_D(ctx->opcode);
5527
5528 switch (op1) {
5529 case OPC1_32_RLC_ADDI:
5530 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
5531 break;
5532 case OPC1_32_RLC_ADDIH:
5533 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
5534 break;
5535 case OPC1_32_RLC_ADDIH_A:
5536 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
5537 break;
5538 case OPC1_32_RLC_MFCR:
5539 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5540 gen_mfcr(ctx, cpu_gpr_d[r2], const16);
5541 break;
5542 case OPC1_32_RLC_MOV:
5543 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5544 break;
5545 case OPC1_32_RLC_MOV_64:
5546 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5547 CHECK_REG_PAIR(r2);
5548 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5549 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
5550 } else {
5551 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5552 }
5553 break;
5554 case OPC1_32_RLC_MOV_U:
5555 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5556 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5557 break;
5558 case OPC1_32_RLC_MOV_H:
5559 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
5560 break;
5561 case OPC1_32_RLC_MOVH_A:
5562 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
5563 break;
5564 case OPC1_32_RLC_MTCR:
5565 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5566 gen_mtcr(ctx, cpu_gpr_d[r1], const16);
5567 break;
5568 default:
5569 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5570 }
5571 }
5572
5573 /* RR format */
5574 static void decode_rr_accumulator(DisasContext *ctx)
5575 {
5576 uint32_t op2;
5577 int r3, r2, r1;
5578
5579 TCGv temp;
5580
5581 r3 = MASK_OP_RR_D(ctx->opcode);
5582 r2 = MASK_OP_RR_S2(ctx->opcode);
5583 r1 = MASK_OP_RR_S1(ctx->opcode);
5584 op2 = MASK_OP_RR_OP2(ctx->opcode);
5585
5586 switch (op2) {
5587 case OPC2_32_RR_ABS:
5588 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5589 break;
5590 case OPC2_32_RR_ABS_B:
5591 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5592 break;
5593 case OPC2_32_RR_ABS_H:
5594 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5595 break;
5596 case OPC2_32_RR_ABSDIF:
5597 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5598 break;
5599 case OPC2_32_RR_ABSDIF_B:
5600 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5601 cpu_gpr_d[r2]);
5602 break;
5603 case OPC2_32_RR_ABSDIF_H:
5604 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5605 cpu_gpr_d[r2]);
5606 break;
5607 case OPC2_32_RR_ABSDIFS:
5608 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5609 cpu_gpr_d[r2]);
5610 break;
5611 case OPC2_32_RR_ABSDIFS_H:
5612 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5613 cpu_gpr_d[r2]);
5614 break;
5615 case OPC2_32_RR_ABSS:
5616 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5617 break;
5618 case OPC2_32_RR_ABSS_H:
5619 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5620 break;
5621 case OPC2_32_RR_ADD:
5622 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5623 break;
5624 case OPC2_32_RR_ADD_B:
5625 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5626 break;
5627 case OPC2_32_RR_ADD_H:
5628 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5629 break;
5630 case OPC2_32_RR_ADDC:
5631 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5632 break;
5633 case OPC2_32_RR_ADDS:
5634 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5635 break;
5636 case OPC2_32_RR_ADDS_H:
5637 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5638 cpu_gpr_d[r2]);
5639 break;
5640 case OPC2_32_RR_ADDS_HU:
5641 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5642 cpu_gpr_d[r2]);
5643 break;
5644 case OPC2_32_RR_ADDS_U:
5645 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5646 cpu_gpr_d[r2]);
5647 break;
5648 case OPC2_32_RR_ADDX:
5649 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5650 break;
5651 case OPC2_32_RR_AND_EQ:
5652 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5653 cpu_gpr_d[r2], &tcg_gen_and_tl);
5654 break;
5655 case OPC2_32_RR_AND_GE:
5656 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5657 cpu_gpr_d[r2], &tcg_gen_and_tl);
5658 break;
5659 case OPC2_32_RR_AND_GE_U:
5660 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5661 cpu_gpr_d[r2], &tcg_gen_and_tl);
5662 break;
5663 case OPC2_32_RR_AND_LT:
5664 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5665 cpu_gpr_d[r2], &tcg_gen_and_tl);
5666 break;
5667 case OPC2_32_RR_AND_LT_U:
5668 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5669 cpu_gpr_d[r2], &tcg_gen_and_tl);
5670 break;
5671 case OPC2_32_RR_AND_NE:
5672 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5673 cpu_gpr_d[r2], &tcg_gen_and_tl);
5674 break;
5675 case OPC2_32_RR_EQ:
5676 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5677 cpu_gpr_d[r2]);
5678 break;
5679 case OPC2_32_RR_EQ_B:
5680 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5681 break;
5682 case OPC2_32_RR_EQ_H:
5683 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5684 break;
5685 case OPC2_32_RR_EQ_W:
5686 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5687 break;
5688 case OPC2_32_RR_EQANY_B:
5689 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5690 break;
5691 case OPC2_32_RR_EQANY_H:
5692 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5693 break;
5694 case OPC2_32_RR_GE:
5695 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5696 cpu_gpr_d[r2]);
5697 break;
5698 case OPC2_32_RR_GE_U:
5699 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5700 cpu_gpr_d[r2]);
5701 break;
5702 case OPC2_32_RR_LT:
5703 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5704 cpu_gpr_d[r2]);
5705 break;
5706 case OPC2_32_RR_LT_U:
5707 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5708 cpu_gpr_d[r2]);
5709 break;
5710 case OPC2_32_RR_LT_B:
5711 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5712 break;
5713 case OPC2_32_RR_LT_BU:
5714 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5715 break;
5716 case OPC2_32_RR_LT_H:
5717 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5718 break;
5719 case OPC2_32_RR_LT_HU:
5720 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5721 break;
5722 case OPC2_32_RR_LT_W:
5723 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5724 break;
5725 case OPC2_32_RR_LT_WU:
5726 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5727 break;
5728 case OPC2_32_RR_MAX:
5729 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5730 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5731 break;
5732 case OPC2_32_RR_MAX_U:
5733 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5734 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5735 break;
5736 case OPC2_32_RR_MAX_B:
5737 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5738 break;
5739 case OPC2_32_RR_MAX_BU:
5740 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5741 break;
5742 case OPC2_32_RR_MAX_H:
5743 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5744 break;
5745 case OPC2_32_RR_MAX_HU:
5746 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5747 break;
5748 case OPC2_32_RR_MIN:
5749 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5750 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5751 break;
5752 case OPC2_32_RR_MIN_U:
5753 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5754 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5755 break;
5756 case OPC2_32_RR_MIN_B:
5757 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5758 break;
5759 case OPC2_32_RR_MIN_BU:
5760 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5761 break;
5762 case OPC2_32_RR_MIN_H:
5763 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5764 break;
5765 case OPC2_32_RR_MIN_HU:
5766 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5767 break;
5768 case OPC2_32_RR_MOV:
5769 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5770 break;
5771 case OPC2_32_RR_MOV_64:
5772 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5773 temp = tcg_temp_new();
5774
5775 CHECK_REG_PAIR(r3);
5776 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
5777 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5778 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
5779 } else {
5780 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5781 }
5782 break;
5783 case OPC2_32_RR_MOVS_64:
5784 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5785 CHECK_REG_PAIR(r3);
5786 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5787 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
5788 } else {
5789 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5790 }
5791 break;
5792 case OPC2_32_RR_NE:
5793 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5794 cpu_gpr_d[r2]);
5795 break;
5796 case OPC2_32_RR_OR_EQ:
5797 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5798 cpu_gpr_d[r2], &tcg_gen_or_tl);
5799 break;
5800 case OPC2_32_RR_OR_GE:
5801 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5802 cpu_gpr_d[r2], &tcg_gen_or_tl);
5803 break;
5804 case OPC2_32_RR_OR_GE_U:
5805 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5806 cpu_gpr_d[r2], &tcg_gen_or_tl);
5807 break;
5808 case OPC2_32_RR_OR_LT:
5809 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5810 cpu_gpr_d[r2], &tcg_gen_or_tl);
5811 break;
5812 case OPC2_32_RR_OR_LT_U:
5813 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5814 cpu_gpr_d[r2], &tcg_gen_or_tl);
5815 break;
5816 case OPC2_32_RR_OR_NE:
5817 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5818 cpu_gpr_d[r2], &tcg_gen_or_tl);
5819 break;
5820 case OPC2_32_RR_SAT_B:
5821 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
5822 break;
5823 case OPC2_32_RR_SAT_BU:
5824 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
5825 break;
5826 case OPC2_32_RR_SAT_H:
5827 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
5828 break;
5829 case OPC2_32_RR_SAT_HU:
5830 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
5831 break;
5832 case OPC2_32_RR_SH_EQ:
5833 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5834 cpu_gpr_d[r2]);
5835 break;
5836 case OPC2_32_RR_SH_GE:
5837 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5838 cpu_gpr_d[r2]);
5839 break;
5840 case OPC2_32_RR_SH_GE_U:
5841 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5842 cpu_gpr_d[r2]);
5843 break;
5844 case OPC2_32_RR_SH_LT:
5845 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5846 cpu_gpr_d[r2]);
5847 break;
5848 case OPC2_32_RR_SH_LT_U:
5849 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5850 cpu_gpr_d[r2]);
5851 break;
5852 case OPC2_32_RR_SH_NE:
5853 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5854 cpu_gpr_d[r2]);
5855 break;
5856 case OPC2_32_RR_SUB:
5857 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5858 break;
5859 case OPC2_32_RR_SUB_B:
5860 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5861 break;
5862 case OPC2_32_RR_SUB_H:
5863 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5864 break;
5865 case OPC2_32_RR_SUBC:
5866 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5867 break;
5868 case OPC2_32_RR_SUBS:
5869 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5870 break;
5871 case OPC2_32_RR_SUBS_U:
5872 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5873 break;
5874 case OPC2_32_RR_SUBS_H:
5875 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5876 cpu_gpr_d[r2]);
5877 break;
5878 case OPC2_32_RR_SUBS_HU:
5879 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5880 cpu_gpr_d[r2]);
5881 break;
5882 case OPC2_32_RR_SUBX:
5883 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5884 break;
5885 case OPC2_32_RR_XOR_EQ:
5886 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5887 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5888 break;
5889 case OPC2_32_RR_XOR_GE:
5890 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5891 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5892 break;
5893 case OPC2_32_RR_XOR_GE_U:
5894 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5895 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5896 break;
5897 case OPC2_32_RR_XOR_LT:
5898 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5899 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5900 break;
5901 case OPC2_32_RR_XOR_LT_U:
5902 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5903 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5904 break;
5905 case OPC2_32_RR_XOR_NE:
5906 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5907 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5908 break;
5909 default:
5910 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5911 }
5912 }
5913
5914 static void decode_rr_logical_shift(DisasContext *ctx)
5915 {
5916 uint32_t op2;
5917 int r3, r2, r1;
5918
5919 r3 = MASK_OP_RR_D(ctx->opcode);
5920 r2 = MASK_OP_RR_S2(ctx->opcode);
5921 r1 = MASK_OP_RR_S1(ctx->opcode);
5922 op2 = MASK_OP_RR_OP2(ctx->opcode);
5923
5924 switch (op2) {
5925 case OPC2_32_RR_AND:
5926 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5927 break;
5928 case OPC2_32_RR_ANDN:
5929 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5930 break;
5931 case OPC2_32_RR_CLO:
5932 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5933 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
5934 break;
5935 case OPC2_32_RR_CLO_H:
5936 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5937 break;
5938 case OPC2_32_RR_CLS:
5939 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5940 break;
5941 case OPC2_32_RR_CLS_H:
5942 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5943 break;
5944 case OPC2_32_RR_CLZ:
5945 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
5946 break;
5947 case OPC2_32_RR_CLZ_H:
5948 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5949 break;
5950 case OPC2_32_RR_NAND:
5951 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5952 break;
5953 case OPC2_32_RR_NOR:
5954 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5955 break;
5956 case OPC2_32_RR_OR:
5957 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5958 break;
5959 case OPC2_32_RR_ORN:
5960 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5961 break;
5962 case OPC2_32_RR_SH:
5963 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5964 break;
5965 case OPC2_32_RR_SH_H:
5966 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5967 break;
5968 case OPC2_32_RR_SHA:
5969 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5970 break;
5971 case OPC2_32_RR_SHA_H:
5972 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5973 break;
5974 case OPC2_32_RR_SHAS:
5975 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5976 break;
5977 case OPC2_32_RR_XNOR:
5978 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5979 break;
5980 case OPC2_32_RR_XOR:
5981 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5982 break;
5983 default:
5984 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5985 }
5986 }
5987
5988 static void decode_rr_address(DisasContext *ctx)
5989 {
5990 uint32_t op2, n;
5991 int r1, r2, r3;
5992 TCGv temp;
5993
5994 op2 = MASK_OP_RR_OP2(ctx->opcode);
5995 r3 = MASK_OP_RR_D(ctx->opcode);
5996 r2 = MASK_OP_RR_S2(ctx->opcode);
5997 r1 = MASK_OP_RR_S1(ctx->opcode);
5998 n = MASK_OP_RR_N(ctx->opcode);
5999
6000 switch (op2) {
6001 case OPC2_32_RR_ADD_A:
6002 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6003 break;
6004 case OPC2_32_RR_ADDSC_A:
6005 temp = tcg_temp_new();
6006 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
6007 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
6008 break;
6009 case OPC2_32_RR_ADDSC_AT:
6010 temp = tcg_temp_new();
6011 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
6012 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
6013 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
6014 break;
6015 case OPC2_32_RR_EQ_A:
6016 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
6017 cpu_gpr_a[r2]);
6018 break;
6019 case OPC2_32_RR_EQZ:
6020 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6021 break;
6022 case OPC2_32_RR_GE_A:
6023 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6024 cpu_gpr_a[r2]);
6025 break;
6026 case OPC2_32_RR_LT_A:
6027 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6028 cpu_gpr_a[r2]);
6029 break;
6030 case OPC2_32_RR_MOV_A:
6031 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
6032 break;
6033 case OPC2_32_RR_MOV_AA:
6034 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
6035 break;
6036 case OPC2_32_RR_MOV_D:
6037 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
6038 break;
6039 case OPC2_32_RR_NE_A:
6040 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
6041 cpu_gpr_a[r2]);
6042 break;
6043 case OPC2_32_RR_NEZ_A:
6044 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6045 break;
6046 case OPC2_32_RR_SUB_A:
6047 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6048 break;
6049 default:
6050 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6051 }
6052 }
6053
6054 static void decode_rr_idirect(DisasContext *ctx)
6055 {
6056 uint32_t op2;
6057 int r1;
6058
6059 op2 = MASK_OP_RR_OP2(ctx->opcode);
6060 r1 = MASK_OP_RR_S1(ctx->opcode);
6061
6062 switch (op2) {
6063 case OPC2_32_RR_JI:
6064 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6065 break;
6066 case OPC2_32_RR_JLI:
6067 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6068 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
6069 break;
6070 case OPC2_32_RR_CALLI:
6071 gen_helper_1arg(call, ctx->pc_succ_insn);
6072 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6073 break;
6074 case OPC2_32_RR_FCALLI:
6075 gen_fcall_save_ctx(ctx);
6076 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6077 break;
6078 default:
6079 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6080 }
6081 tcg_gen_exit_tb(NULL, 0);
6082 ctx->base.is_jmp = DISAS_NORETURN;
6083 }
6084
6085 static void decode_rr_divide(DisasContext *ctx)
6086 {
6087 uint32_t op2;
6088 int r1, r2, r3;
6089
6090 TCGv temp, temp2, temp3;
6091
6092 op2 = MASK_OP_RR_OP2(ctx->opcode);
6093 r3 = MASK_OP_RR_D(ctx->opcode);
6094 r2 = MASK_OP_RR_S2(ctx->opcode);
6095 r1 = MASK_OP_RR_S1(ctx->opcode);
6096
6097 switch (op2) {
6098 case OPC2_32_RR_BMERGE:
6099 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6100 break;
6101 case OPC2_32_RR_BSPLIT:
6102 CHECK_REG_PAIR(r3);
6103 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6104 break;
6105 case OPC2_32_RR_DVINIT_B:
6106 CHECK_REG_PAIR(r3);
6107 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6108 cpu_gpr_d[r2]);
6109 break;
6110 case OPC2_32_RR_DVINIT_BU:
6111 temp = tcg_temp_new();
6112 temp2 = tcg_temp_new();
6113 temp3 = tcg_temp_new();
6114 CHECK_REG_PAIR(r3);
6115 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
6116 /* reset av */
6117 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6118 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
6119 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6120 tcg_gen_abs_tl(temp, temp3);
6121 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
6122 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6123 } else {
6124 /* overflow = (D[b] == 0) */
6125 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6126 }
6127 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6128 /* sv */
6129 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6130 /* write result */
6131 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
6132 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6133 break;
6134 case OPC2_32_RR_DVINIT_H:
6135 CHECK_REG_PAIR(r3);
6136 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6137 cpu_gpr_d[r2]);
6138 break;
6139 case OPC2_32_RR_DVINIT_HU:
6140 temp = tcg_temp_new();
6141 temp2 = tcg_temp_new();
6142 temp3 = tcg_temp_new();
6143 CHECK_REG_PAIR(r3);
6144 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
6145 /* reset av */
6146 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6147 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
6148 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6149 tcg_gen_abs_tl(temp, temp3);
6150 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
6151 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6152 } else {
6153 /* overflow = (D[b] == 0) */
6154 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6155 }
6156 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6157 /* sv */
6158 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6159 /* write result */
6160 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
6161 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6162 break;
6163 case OPC2_32_RR_DVINIT:
6164 temp = tcg_temp_new();
6165 temp2 = tcg_temp_new();
6166 CHECK_REG_PAIR(r3);
6167 /* overflow = ((D[b] == 0) ||
6168 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6169 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
6170 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
6171 tcg_gen_and_tl(temp, temp, temp2);
6172 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
6173 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
6174 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6175 /* sv */
6176 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6177 /* reset av */
6178 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6179 /* write result */
6180 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6181 /* sign extend to high reg */
6182 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
6183 break;
6184 case OPC2_32_RR_DVINIT_U:
6185 CHECK_REG_PAIR(r3);
6186 /* overflow = (D[b] == 0) */
6187 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6188 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6189 /* sv */
6190 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6191 /* reset av */
6192 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6193 /* write result */
6194 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6195 /* zero extend to high reg*/
6196 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
6197 break;
6198 case OPC2_32_RR_PARITY:
6199 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6200 break;
6201 case OPC2_32_RR_UNPACK:
6202 CHECK_REG_PAIR(r3);
6203 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6204 break;
6205 case OPC2_32_RR_CRC32_B:
6206 if (has_feature(ctx, TRICORE_FEATURE_162)) {
6207 gen_helper_crc32b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6208 } else {
6209 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6210 }
6211 break;
6212 case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */
6213 if (has_feature(ctx, TRICORE_FEATURE_161)) {
6214 gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6215 } else {
6216 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6217 }
6218 break;
6219 case OPC2_32_RR_CRC32L_W:
6220 if (has_feature(ctx, TRICORE_FEATURE_162)) {
6221 gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6222 } else {
6223 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6224 }
6225 break;
6226
6227 case OPC2_32_RR_POPCNT_W:
6228 if (has_feature(ctx, TRICORE_FEATURE_162)) {
6229 tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6230 } else {
6231 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6232 }
6233 break;
6234 case OPC2_32_RR_DIV:
6235 if (has_feature(ctx, TRICORE_FEATURE_16)) {
6236 CHECK_REG_PAIR(r3);
6237 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6238 cpu_gpr_d[r2]);
6239 } else {
6240 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6241 }
6242 break;
6243 case OPC2_32_RR_DIV_U:
6244 if (has_feature(ctx, TRICORE_FEATURE_16)) {
6245 CHECK_REG_PAIR(r3);
6246 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6247 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6248 } else {
6249 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6250 }
6251 break;
6252 case OPC2_32_RR_MUL_F:
6253 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6254 break;
6255 case OPC2_32_RR_DIV_F:
6256 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6257 break;
6258 case OPC2_32_RR_CMP_F:
6259 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6260 break;
6261 case OPC2_32_RR_FTOI:
6262 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6263 break;
6264 case OPC2_32_RR_ITOF:
6265 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6266 break;
6267 case OPC2_32_RR_FTOUZ:
6268 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6269 break;
6270 case OPC2_32_RR_UPDFL:
6271 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
6272 break;
6273 case OPC2_32_RR_UTOF:
6274 gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6275 break;
6276 case OPC2_32_RR_FTOIZ:
6277 gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6278 break;
6279 case OPC2_32_RR_QSEED_F:
6280 gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6281 break;
6282 default:
6283 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6284 }
6285 }
6286
6287 /* RR1 Format */
6288 static void decode_rr1_mul(DisasContext *ctx)
6289 {
6290 uint32_t op2;
6291
6292 int r1, r2, r3;
6293 TCGv n;
6294 TCGv_i64 temp64;
6295
6296 r1 = MASK_OP_RR1_S1(ctx->opcode);
6297 r2 = MASK_OP_RR1_S2(ctx->opcode);
6298 r3 = MASK_OP_RR1_D(ctx->opcode);
6299 n = tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode));
6300 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6301
6302 switch (op2) {
6303 case OPC2_32_RR1_MUL_H_32_LL:
6304 temp64 = tcg_temp_new_i64();
6305 CHECK_REG_PAIR(r3);
6306 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6307 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6308 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6309 break;
6310 case OPC2_32_RR1_MUL_H_32_LU:
6311 temp64 = tcg_temp_new_i64();
6312 CHECK_REG_PAIR(r3);
6313 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6314 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6315 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6316 break;
6317 case OPC2_32_RR1_MUL_H_32_UL:
6318 temp64 = tcg_temp_new_i64();
6319 CHECK_REG_PAIR(r3);
6320 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6321 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6322 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6323 break;
6324 case OPC2_32_RR1_MUL_H_32_UU:
6325 temp64 = tcg_temp_new_i64();
6326 CHECK_REG_PAIR(r3);
6327 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6328 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6329 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6330 break;
6331 case OPC2_32_RR1_MULM_H_64_LL:
6332 temp64 = tcg_temp_new_i64();
6333 CHECK_REG_PAIR(r3);
6334 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6335 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6336 /* reset V bit */
6337 tcg_gen_movi_tl(cpu_PSW_V, 0);
6338 /* reset AV bit */
6339 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6340 break;
6341 case OPC2_32_RR1_MULM_H_64_LU:
6342 temp64 = tcg_temp_new_i64();
6343 CHECK_REG_PAIR(r3);
6344 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6345 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6346 /* reset V bit */
6347 tcg_gen_movi_tl(cpu_PSW_V, 0);
6348 /* reset AV bit */
6349 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6350 break;
6351 case OPC2_32_RR1_MULM_H_64_UL:
6352 temp64 = tcg_temp_new_i64();
6353 CHECK_REG_PAIR(r3);
6354 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6355 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6356 /* reset V bit */
6357 tcg_gen_movi_tl(cpu_PSW_V, 0);
6358 /* reset AV bit */
6359 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6360 break;
6361 case OPC2_32_RR1_MULM_H_64_UU:
6362 temp64 = tcg_temp_new_i64();
6363 CHECK_REG_PAIR(r3);
6364 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6365 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6366 /* reset V bit */
6367 tcg_gen_movi_tl(cpu_PSW_V, 0);
6368 /* reset AV bit */
6369 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6370 break;
6371 case OPC2_32_RR1_MULR_H_16_LL:
6372 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6373 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6374 break;
6375 case OPC2_32_RR1_MULR_H_16_LU:
6376 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6377 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6378 break;
6379 case OPC2_32_RR1_MULR_H_16_UL:
6380 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6381 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6382 break;
6383 case OPC2_32_RR1_MULR_H_16_UU:
6384 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6385 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6386 break;
6387 default:
6388 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6389 }
6390 }
6391
6392 static void decode_rr1_mulq(DisasContext *ctx)
6393 {
6394 uint32_t op2;
6395 int r1, r2, r3;
6396 uint32_t n;
6397
6398 TCGv temp, temp2;
6399
6400 r1 = MASK_OP_RR1_S1(ctx->opcode);
6401 r2 = MASK_OP_RR1_S2(ctx->opcode);
6402 r3 = MASK_OP_RR1_D(ctx->opcode);
6403 n = MASK_OP_RR1_N(ctx->opcode);
6404 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6405
6406 temp = tcg_temp_new();
6407 temp2 = tcg_temp_new();
6408
6409 switch (op2) {
6410 case OPC2_32_RR1_MUL_Q_32:
6411 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
6412 break;
6413 case OPC2_32_RR1_MUL_Q_64:
6414 CHECK_REG_PAIR(r3);
6415 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6416 n, 0);
6417 break;
6418 case OPC2_32_RR1_MUL_Q_32_L:
6419 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6420 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6421 break;
6422 case OPC2_32_RR1_MUL_Q_64_L:
6423 CHECK_REG_PAIR(r3);
6424 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6425 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6426 break;
6427 case OPC2_32_RR1_MUL_Q_32_U:
6428 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6429 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6430 break;
6431 case OPC2_32_RR1_MUL_Q_64_U:
6432 CHECK_REG_PAIR(r3);
6433 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6434 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6435 break;
6436 case OPC2_32_RR1_MUL_Q_32_LL:
6437 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6438 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6439 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6440 break;
6441 case OPC2_32_RR1_MUL_Q_32_UU:
6442 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6443 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6444 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6445 break;
6446 case OPC2_32_RR1_MULR_Q_32_L:
6447 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6448 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6449 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6450 break;
6451 case OPC2_32_RR1_MULR_Q_32_U:
6452 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6453 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6454 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6455 break;
6456 default:
6457 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6458 }
6459 }
6460
6461 /* RR2 format */
6462 static void decode_rr2_mul(DisasContext *ctx)
6463 {
6464 uint32_t op2;
6465 int r1, r2, r3;
6466
6467 op2 = MASK_OP_RR2_OP2(ctx->opcode);
6468 r1 = MASK_OP_RR2_S1(ctx->opcode);
6469 r2 = MASK_OP_RR2_S2(ctx->opcode);
6470 r3 = MASK_OP_RR2_D(ctx->opcode);
6471 switch (op2) {
6472 case OPC2_32_RR2_MUL_32:
6473 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6474 break;
6475 case OPC2_32_RR2_MUL_64:
6476 CHECK_REG_PAIR(r3);
6477 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6478 cpu_gpr_d[r2]);
6479 break;
6480 case OPC2_32_RR2_MULS_32:
6481 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6482 cpu_gpr_d[r2]);
6483 break;
6484 case OPC2_32_RR2_MUL_U_64:
6485 CHECK_REG_PAIR(r3);
6486 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6487 cpu_gpr_d[r2]);
6488 break;
6489 case OPC2_32_RR2_MULS_U_32:
6490 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6491 cpu_gpr_d[r2]);
6492 break;
6493 default:
6494 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6495 }
6496 }
6497
6498 /* RRPW format */
6499 static void decode_rrpw_extract_insert(DisasContext *ctx)
6500 {
6501 uint32_t op2;
6502 int r1, r2, r3;
6503 int32_t pos, width;
6504 TCGv temp;
6505
6506 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
6507 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6508 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6509 r3 = MASK_OP_RRPW_D(ctx->opcode);
6510 pos = MASK_OP_RRPW_POS(ctx->opcode);
6511 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
6512
6513 switch (op2) {
6514 case OPC2_32_RRPW_EXTR:
6515 if (width == 0) {
6516 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6517 break;
6518 }
6519
6520 if (pos + width <= 32) {
6521 /* optimize special cases */
6522 if ((pos == 0) && (width == 8)) {
6523 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6524 } else if ((pos == 0) && (width == 16)) {
6525 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6526 } else {
6527 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
6528 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
6529 }
6530 }
6531 break;
6532 case OPC2_32_RRPW_EXTR_U:
6533 if (width == 0) {
6534 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6535 } else {
6536 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
6537 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
6538 }
6539 break;
6540 case OPC2_32_RRPW_IMASK:
6541 CHECK_REG_PAIR(r3);
6542
6543 if (pos + width <= 32) {
6544 temp = tcg_temp_new();
6545 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos);
6546 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
6547 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
6548 }
6549
6550 break;
6551 case OPC2_32_RRPW_INSERT:
6552 if (pos + width <= 32) {
6553 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
6554 pos, width);
6555 }
6556 break;
6557 default:
6558 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6559 }
6560 }
6561
6562 /* RRR format */
6563 static void decode_rrr_cond_select(DisasContext *ctx)
6564 {
6565 uint32_t op2;
6566 int r1, r2, r3, r4;
6567 TCGv temp;
6568
6569 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6570 r1 = MASK_OP_RRR_S1(ctx->opcode);
6571 r2 = MASK_OP_RRR_S2(ctx->opcode);
6572 r3 = MASK_OP_RRR_S3(ctx->opcode);
6573 r4 = MASK_OP_RRR_D(ctx->opcode);
6574
6575 switch (op2) {
6576 case OPC2_32_RRR_CADD:
6577 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
6578 cpu_gpr_d[r4], cpu_gpr_d[r3]);
6579 break;
6580 case OPC2_32_RRR_CADDN:
6581 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6582 cpu_gpr_d[r3]);
6583 break;
6584 case OPC2_32_RRR_CSUB:
6585 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6586 cpu_gpr_d[r3]);
6587 break;
6588 case OPC2_32_RRR_CSUBN:
6589 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6590 cpu_gpr_d[r3]);
6591 break;
6592 case OPC2_32_RRR_SEL:
6593 temp = tcg_constant_i32(0);
6594 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6595 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6596 break;
6597 case OPC2_32_RRR_SELN:
6598 temp = tcg_constant_i32(0);
6599 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6600 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6601 break;
6602 default:
6603 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6604 }
6605 }
6606
6607 static void decode_rrr_divide(DisasContext *ctx)
6608 {
6609 uint32_t op2;
6610
6611 int r1, r2, r3, r4;
6612
6613 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6614 r1 = MASK_OP_RRR_S1(ctx->opcode);
6615 r2 = MASK_OP_RRR_S2(ctx->opcode);
6616 r3 = MASK_OP_RRR_S3(ctx->opcode);
6617 r4 = MASK_OP_RRR_D(ctx->opcode);
6618
6619 switch (op2) {
6620 case OPC2_32_RRR_DVADJ:
6621 CHECK_REG_PAIR(r3);
6622 CHECK_REG_PAIR(r4);
6623 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6624 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6625 break;
6626 case OPC2_32_RRR_DVSTEP:
6627 CHECK_REG_PAIR(r3);
6628 CHECK_REG_PAIR(r4);
6629 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6630 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6631 break;
6632 case OPC2_32_RRR_DVSTEP_U:
6633 CHECK_REG_PAIR(r3);
6634 CHECK_REG_PAIR(r4);
6635 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6636 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6637 break;
6638 case OPC2_32_RRR_IXMAX:
6639 CHECK_REG_PAIR(r3);
6640 CHECK_REG_PAIR(r4);
6641 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6642 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6643 break;
6644 case OPC2_32_RRR_IXMAX_U:
6645 CHECK_REG_PAIR(r3);
6646 CHECK_REG_PAIR(r4);
6647 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6648 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6649 break;
6650 case OPC2_32_RRR_IXMIN:
6651 CHECK_REG_PAIR(r3);
6652 CHECK_REG_PAIR(r4);
6653 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6654 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6655 break;
6656 case OPC2_32_RRR_IXMIN_U:
6657 CHECK_REG_PAIR(r3);
6658 CHECK_REG_PAIR(r4);
6659 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6660 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6661 break;
6662 case OPC2_32_RRR_PACK:
6663 CHECK_REG_PAIR(r3);
6664 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
6665 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6666 break;
6667 case OPC2_32_RRR_ADD_F:
6668 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
6669 break;
6670 case OPC2_32_RRR_SUB_F:
6671 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
6672 break;
6673 case OPC2_32_RRR_MADD_F:
6674 gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6675 cpu_gpr_d[r2], cpu_gpr_d[r3]);
6676 break;
6677 case OPC2_32_RRR_MSUB_F:
6678 gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6679 cpu_gpr_d[r2], cpu_gpr_d[r3]);
6680 break;
6681 default:
6682 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6683 }
6684 }
6685
6686 /* RRR2 format */
6687 static void decode_rrr2_madd(DisasContext *ctx)
6688 {
6689 uint32_t op2;
6690 uint32_t r1, r2, r3, r4;
6691
6692 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6693 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6694 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6695 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6696 r4 = MASK_OP_RRR2_D(ctx->opcode);
6697 switch (op2) {
6698 case OPC2_32_RRR2_MADD_32:
6699 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6700 cpu_gpr_d[r2]);
6701 break;
6702 case OPC2_32_RRR2_MADD_64:
6703 CHECK_REG_PAIR(r4);
6704 CHECK_REG_PAIR(r3);
6705 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6706 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6707 break;
6708 case OPC2_32_RRR2_MADDS_32:
6709 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6710 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6711 break;
6712 case OPC2_32_RRR2_MADDS_64:
6713 CHECK_REG_PAIR(r4);
6714 CHECK_REG_PAIR(r3);
6715 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6716 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6717 break;
6718 case OPC2_32_RRR2_MADD_U_64:
6719 CHECK_REG_PAIR(r4);
6720 CHECK_REG_PAIR(r3);
6721 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6722 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6723 break;
6724 case OPC2_32_RRR2_MADDS_U_32:
6725 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6726 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6727 break;
6728 case OPC2_32_RRR2_MADDS_U_64:
6729 CHECK_REG_PAIR(r4);
6730 CHECK_REG_PAIR(r3);
6731 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6732 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6733 break;
6734 default:
6735 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6736 }
6737 }
6738
6739 static void decode_rrr2_msub(DisasContext *ctx)
6740 {
6741 uint32_t op2;
6742 uint32_t r1, r2, r3, r4;
6743
6744 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6745 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6746 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6747 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6748 r4 = MASK_OP_RRR2_D(ctx->opcode);
6749
6750 switch (op2) {
6751 case OPC2_32_RRR2_MSUB_32:
6752 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6753 cpu_gpr_d[r2]);
6754 break;
6755 case OPC2_32_RRR2_MSUB_64:
6756 CHECK_REG_PAIR(r4);
6757 CHECK_REG_PAIR(r3);
6758 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6759 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6760 break;
6761 case OPC2_32_RRR2_MSUBS_32:
6762 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6763 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6764 break;
6765 case OPC2_32_RRR2_MSUBS_64:
6766 CHECK_REG_PAIR(r4);
6767 CHECK_REG_PAIR(r3);
6768 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6769 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6770 break;
6771 case OPC2_32_RRR2_MSUB_U_64:
6772 CHECK_REG_PAIR(r4);
6773 CHECK_REG_PAIR(r3);
6774 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6775 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6776 break;
6777 case OPC2_32_RRR2_MSUBS_U_32:
6778 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6779 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6780 break;
6781 case OPC2_32_RRR2_MSUBS_U_64:
6782 CHECK_REG_PAIR(r4);
6783 CHECK_REG_PAIR(r3);
6784 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6785 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6786 break;
6787 default:
6788 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6789 }
6790 }
6791
6792 /* RRR1 format */
6793 static void decode_rrr1_madd(DisasContext *ctx)
6794 {
6795 uint32_t op2;
6796 uint32_t r1, r2, r3, r4, n;
6797
6798 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6799 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6800 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6801 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6802 r4 = MASK_OP_RRR1_D(ctx->opcode);
6803 n = MASK_OP_RRR1_N(ctx->opcode);
6804
6805 switch (op2) {
6806 case OPC2_32_RRR1_MADD_H_LL:
6807 CHECK_REG_PAIR(r4);
6808 CHECK_REG_PAIR(r3);
6809 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6810 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6811 break;
6812 case OPC2_32_RRR1_MADD_H_LU:
6813 CHECK_REG_PAIR(r4);
6814 CHECK_REG_PAIR(r3);
6815 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6816 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6817 break;
6818 case OPC2_32_RRR1_MADD_H_UL:
6819 CHECK_REG_PAIR(r4);
6820 CHECK_REG_PAIR(r3);
6821 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6822 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6823 break;
6824 case OPC2_32_RRR1_MADD_H_UU:
6825 CHECK_REG_PAIR(r4);
6826 CHECK_REG_PAIR(r3);
6827 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6828 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6829 break;
6830 case OPC2_32_RRR1_MADDS_H_LL:
6831 CHECK_REG_PAIR(r4);
6832 CHECK_REG_PAIR(r3);
6833 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6834 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6835 break;
6836 case OPC2_32_RRR1_MADDS_H_LU:
6837 CHECK_REG_PAIR(r4);
6838 CHECK_REG_PAIR(r3);
6839 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6840 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6841 break;
6842 case OPC2_32_RRR1_MADDS_H_UL:
6843 CHECK_REG_PAIR(r4);
6844 CHECK_REG_PAIR(r3);
6845 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6846 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6847 break;
6848 case OPC2_32_RRR1_MADDS_H_UU:
6849 CHECK_REG_PAIR(r4);
6850 CHECK_REG_PAIR(r3);
6851 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6852 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6853 break;
6854 case OPC2_32_RRR1_MADDM_H_LL:
6855 CHECK_REG_PAIR(r4);
6856 CHECK_REG_PAIR(r3);
6857 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6858 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6859 break;
6860 case OPC2_32_RRR1_MADDM_H_LU:
6861 CHECK_REG_PAIR(r4);
6862 CHECK_REG_PAIR(r3);
6863 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6864 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6865 break;
6866 case OPC2_32_RRR1_MADDM_H_UL:
6867 CHECK_REG_PAIR(r4);
6868 CHECK_REG_PAIR(r3);
6869 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6870 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6871 break;
6872 case OPC2_32_RRR1_MADDM_H_UU:
6873 CHECK_REG_PAIR(r4);
6874 CHECK_REG_PAIR(r3);
6875 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6876 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6877 break;
6878 case OPC2_32_RRR1_MADDMS_H_LL:
6879 CHECK_REG_PAIR(r4);
6880 CHECK_REG_PAIR(r3);
6881 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6882 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6883 break;
6884 case OPC2_32_RRR1_MADDMS_H_LU:
6885 CHECK_REG_PAIR(r4);
6886 CHECK_REG_PAIR(r3);
6887 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6888 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6889 break;
6890 case OPC2_32_RRR1_MADDMS_H_UL:
6891 CHECK_REG_PAIR(r4);
6892 CHECK_REG_PAIR(r3);
6893 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6894 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6895 break;
6896 case OPC2_32_RRR1_MADDMS_H_UU:
6897 CHECK_REG_PAIR(r4);
6898 CHECK_REG_PAIR(r3);
6899 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6900 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6901 break;
6902 case OPC2_32_RRR1_MADDR_H_LL:
6903 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6904 cpu_gpr_d[r2], n, MODE_LL);
6905 break;
6906 case OPC2_32_RRR1_MADDR_H_LU:
6907 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6908 cpu_gpr_d[r2], n, MODE_LU);
6909 break;
6910 case OPC2_32_RRR1_MADDR_H_UL:
6911 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6912 cpu_gpr_d[r2], n, MODE_UL);
6913 break;
6914 case OPC2_32_RRR1_MADDR_H_UU:
6915 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6916 cpu_gpr_d[r2], n, MODE_UU);
6917 break;
6918 case OPC2_32_RRR1_MADDRS_H_LL:
6919 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6920 cpu_gpr_d[r2], n, MODE_LL);
6921 break;
6922 case OPC2_32_RRR1_MADDRS_H_LU:
6923 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6924 cpu_gpr_d[r2], n, MODE_LU);
6925 break;
6926 case OPC2_32_RRR1_MADDRS_H_UL:
6927 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6928 cpu_gpr_d[r2], n, MODE_UL);
6929 break;
6930 case OPC2_32_RRR1_MADDRS_H_UU:
6931 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6932 cpu_gpr_d[r2], n, MODE_UU);
6933 break;
6934 default:
6935 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6936 }
6937 }
6938
6939 static void decode_rrr1_maddq_h(DisasContext *ctx)
6940 {
6941 uint32_t op2;
6942 uint32_t r1, r2, r3, r4, n;
6943 TCGv temp, temp2;
6944
6945 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6946 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6947 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6948 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6949 r4 = MASK_OP_RRR1_D(ctx->opcode);
6950 n = MASK_OP_RRR1_N(ctx->opcode);
6951
6952 temp = tcg_temp_new();
6953 temp2 = tcg_temp_new();
6954
6955 switch (op2) {
6956 case OPC2_32_RRR1_MADD_Q_32:
6957 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6958 cpu_gpr_d[r2], n, 32);
6959 break;
6960 case OPC2_32_RRR1_MADD_Q_64:
6961 CHECK_REG_PAIR(r4);
6962 CHECK_REG_PAIR(r3);
6963 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6964 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6965 n);
6966 break;
6967 case OPC2_32_RRR1_MADD_Q_32_L:
6968 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6969 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6970 temp, n, 16);
6971 break;
6972 case OPC2_32_RRR1_MADD_Q_64_L:
6973 CHECK_REG_PAIR(r4);
6974 CHECK_REG_PAIR(r3);
6975 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6976 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6977 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6978 n);
6979 break;
6980 case OPC2_32_RRR1_MADD_Q_32_U:
6981 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6982 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6983 temp, n, 16);
6984 break;
6985 case OPC2_32_RRR1_MADD_Q_64_U:
6986 CHECK_REG_PAIR(r4);
6987 CHECK_REG_PAIR(r3);
6988 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6989 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6990 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6991 n);
6992 break;
6993 case OPC2_32_RRR1_MADD_Q_32_LL:
6994 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6995 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6996 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6997 break;
6998 case OPC2_32_RRR1_MADD_Q_64_LL:
6999 CHECK_REG_PAIR(r4);
7000 CHECK_REG_PAIR(r3);
7001 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7002 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7003 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7004 cpu_gpr_d[r3+1], temp, temp2, n);
7005 break;
7006 case OPC2_32_RRR1_MADD_Q_32_UU:
7007 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7008 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7009 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7010 break;
7011 case OPC2_32_RRR1_MADD_Q_64_UU:
7012 CHECK_REG_PAIR(r4);
7013 CHECK_REG_PAIR(r3);
7014 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7015 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7016 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7017 cpu_gpr_d[r3+1], temp, temp2, n);
7018 break;
7019 case OPC2_32_RRR1_MADDS_Q_32:
7020 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7021 cpu_gpr_d[r2], n, 32);
7022 break;
7023 case OPC2_32_RRR1_MADDS_Q_64:
7024 CHECK_REG_PAIR(r4);
7025 CHECK_REG_PAIR(r3);
7026 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7027 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7028 n);
7029 break;
7030 case OPC2_32_RRR1_MADDS_Q_32_L:
7031 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7032 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7033 temp, n, 16);
7034 break;
7035 case OPC2_32_RRR1_MADDS_Q_64_L:
7036 CHECK_REG_PAIR(r4);
7037 CHECK_REG_PAIR(r3);
7038 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7039 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7040 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7041 n);
7042 break;
7043 case OPC2_32_RRR1_MADDS_Q_32_U:
7044 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7045 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7046 temp, n, 16);
7047 break;
7048 case OPC2_32_RRR1_MADDS_Q_64_U:
7049 CHECK_REG_PAIR(r4);
7050 CHECK_REG_PAIR(r3);
7051 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7052 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7053 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7054 n);
7055 break;
7056 case OPC2_32_RRR1_MADDS_Q_32_LL:
7057 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7058 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7059 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7060 break;
7061 case OPC2_32_RRR1_MADDS_Q_64_LL:
7062 CHECK_REG_PAIR(r4);
7063 CHECK_REG_PAIR(r3);
7064 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7065 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7066 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7067 cpu_gpr_d[r3+1], temp, temp2, n);
7068 break;
7069 case OPC2_32_RRR1_MADDS_Q_32_UU:
7070 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7071 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7072 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7073 break;
7074 case OPC2_32_RRR1_MADDS_Q_64_UU:
7075 CHECK_REG_PAIR(r4);
7076 CHECK_REG_PAIR(r3);
7077 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7078 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7079 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7080 cpu_gpr_d[r3+1], temp, temp2, n);
7081 break;
7082 case OPC2_32_RRR1_MADDR_H_64_UL:
7083 CHECK_REG_PAIR(r3);
7084 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7085 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7086 break;
7087 case OPC2_32_RRR1_MADDRS_H_64_UL:
7088 CHECK_REG_PAIR(r3);
7089 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7090 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7091 break;
7092 case OPC2_32_RRR1_MADDR_Q_32_LL:
7093 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7094 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7095 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7096 break;
7097 case OPC2_32_RRR1_MADDR_Q_32_UU:
7098 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7099 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7100 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7101 break;
7102 case OPC2_32_RRR1_MADDRS_Q_32_LL:
7103 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7104 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7105 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7106 break;
7107 case OPC2_32_RRR1_MADDRS_Q_32_UU:
7108 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7109 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7110 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7111 break;
7112 default:
7113 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7114 }
7115 }
7116
7117 static void decode_rrr1_maddsu_h(DisasContext *ctx)
7118 {
7119 uint32_t op2;
7120 uint32_t r1, r2, r3, r4, n;
7121
7122 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7123 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7124 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7125 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7126 r4 = MASK_OP_RRR1_D(ctx->opcode);
7127 n = MASK_OP_RRR1_N(ctx->opcode);
7128
7129 switch (op2) {
7130 case OPC2_32_RRR1_MADDSU_H_32_LL:
7131 CHECK_REG_PAIR(r4);
7132 CHECK_REG_PAIR(r3);
7133 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7134 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7135 break;
7136 case OPC2_32_RRR1_MADDSU_H_32_LU:
7137 CHECK_REG_PAIR(r4);
7138 CHECK_REG_PAIR(r3);
7139 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7140 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7141 break;
7142 case OPC2_32_RRR1_MADDSU_H_32_UL:
7143 CHECK_REG_PAIR(r4);
7144 CHECK_REG_PAIR(r3);
7145 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7146 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7147 break;
7148 case OPC2_32_RRR1_MADDSU_H_32_UU:
7149 CHECK_REG_PAIR(r4);
7150 CHECK_REG_PAIR(r3);
7151 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7152 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7153 break;
7154 case OPC2_32_RRR1_MADDSUS_H_32_LL:
7155 CHECK_REG_PAIR(r4);
7156 CHECK_REG_PAIR(r3);
7157 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7158 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7159 n, MODE_LL);
7160 break;
7161 case OPC2_32_RRR1_MADDSUS_H_32_LU:
7162 CHECK_REG_PAIR(r4);
7163 CHECK_REG_PAIR(r3);
7164 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7165 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7166 n, MODE_LU);
7167 break;
7168 case OPC2_32_RRR1_MADDSUS_H_32_UL:
7169 CHECK_REG_PAIR(r4);
7170 CHECK_REG_PAIR(r3);
7171 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7172 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7173 n, MODE_UL);
7174 break;
7175 case OPC2_32_RRR1_MADDSUS_H_32_UU:
7176 CHECK_REG_PAIR(r4);
7177 CHECK_REG_PAIR(r3);
7178 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7179 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7180 n, MODE_UU);
7181 break;
7182 case OPC2_32_RRR1_MADDSUM_H_64_LL:
7183 CHECK_REG_PAIR(r4);
7184 CHECK_REG_PAIR(r3);
7185 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7186 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7187 n, MODE_LL);
7188 break;
7189 case OPC2_32_RRR1_MADDSUM_H_64_LU:
7190 CHECK_REG_PAIR(r4);
7191 CHECK_REG_PAIR(r3);
7192 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7193 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7194 n, MODE_LU);
7195 break;
7196 case OPC2_32_RRR1_MADDSUM_H_64_UL:
7197 CHECK_REG_PAIR(r4);
7198 CHECK_REG_PAIR(r3);
7199 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7200 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7201 n, MODE_UL);
7202 break;
7203 case OPC2_32_RRR1_MADDSUM_H_64_UU:
7204 CHECK_REG_PAIR(r4);
7205 CHECK_REG_PAIR(r3);
7206 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7207 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7208 n, MODE_UU);
7209 break;
7210 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
7211 CHECK_REG_PAIR(r4);
7212 CHECK_REG_PAIR(r3);
7213 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7214 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7215 n, MODE_LL);
7216 break;
7217 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
7218 CHECK_REG_PAIR(r4);
7219 CHECK_REG_PAIR(r3);
7220 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7221 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7222 n, MODE_LU);
7223 break;
7224 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
7225 CHECK_REG_PAIR(r4);
7226 CHECK_REG_PAIR(r3);
7227 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7228 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7229 n, MODE_UL);
7230 break;
7231 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
7232 CHECK_REG_PAIR(r4);
7233 CHECK_REG_PAIR(r3);
7234 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7235 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7236 n, MODE_UU);
7237 break;
7238 case OPC2_32_RRR1_MADDSUR_H_16_LL:
7239 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7240 cpu_gpr_d[r2], n, MODE_LL);
7241 break;
7242 case OPC2_32_RRR1_MADDSUR_H_16_LU:
7243 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7244 cpu_gpr_d[r2], n, MODE_LU);
7245 break;
7246 case OPC2_32_RRR1_MADDSUR_H_16_UL:
7247 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7248 cpu_gpr_d[r2], n, MODE_UL);
7249 break;
7250 case OPC2_32_RRR1_MADDSUR_H_16_UU:
7251 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7252 cpu_gpr_d[r2], n, MODE_UU);
7253 break;
7254 case OPC2_32_RRR1_MADDSURS_H_16_LL:
7255 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7256 cpu_gpr_d[r2], n, MODE_LL);
7257 break;
7258 case OPC2_32_RRR1_MADDSURS_H_16_LU:
7259 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7260 cpu_gpr_d[r2], n, MODE_LU);
7261 break;
7262 case OPC2_32_RRR1_MADDSURS_H_16_UL:
7263 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7264 cpu_gpr_d[r2], n, MODE_UL);
7265 break;
7266 case OPC2_32_RRR1_MADDSURS_H_16_UU:
7267 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7268 cpu_gpr_d[r2], n, MODE_UU);
7269 break;
7270 default:
7271 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7272 }
7273 }
7274
7275 static void decode_rrr1_msub(DisasContext *ctx)
7276 {
7277 uint32_t op2;
7278 uint32_t r1, r2, r3, r4, n;
7279
7280 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7281 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7282 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7283 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7284 r4 = MASK_OP_RRR1_D(ctx->opcode);
7285 n = MASK_OP_RRR1_N(ctx->opcode);
7286
7287 switch (op2) {
7288 case OPC2_32_RRR1_MSUB_H_LL:
7289 CHECK_REG_PAIR(r4);
7290 CHECK_REG_PAIR(r3);
7291 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7292 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7293 break;
7294 case OPC2_32_RRR1_MSUB_H_LU:
7295 CHECK_REG_PAIR(r4);
7296 CHECK_REG_PAIR(r3);
7297 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7298 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7299 break;
7300 case OPC2_32_RRR1_MSUB_H_UL:
7301 CHECK_REG_PAIR(r4);
7302 CHECK_REG_PAIR(r3);
7303 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7304 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7305 break;
7306 case OPC2_32_RRR1_MSUB_H_UU:
7307 CHECK_REG_PAIR(r4);
7308 CHECK_REG_PAIR(r3);
7309 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7310 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7311 break;
7312 case OPC2_32_RRR1_MSUBS_H_LL:
7313 CHECK_REG_PAIR(r4);
7314 CHECK_REG_PAIR(r3);
7315 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7316 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7317 break;
7318 case OPC2_32_RRR1_MSUBS_H_LU:
7319 CHECK_REG_PAIR(r4);
7320 CHECK_REG_PAIR(r3);
7321 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7322 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7323 break;
7324 case OPC2_32_RRR1_MSUBS_H_UL:
7325 CHECK_REG_PAIR(r4);
7326 CHECK_REG_PAIR(r3);
7327 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7328 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7329 break;
7330 case OPC2_32_RRR1_MSUBS_H_UU:
7331 CHECK_REG_PAIR(r4);
7332 CHECK_REG_PAIR(r3);
7333 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7334 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7335 break;
7336 case OPC2_32_RRR1_MSUBM_H_LL:
7337 CHECK_REG_PAIR(r4);
7338 CHECK_REG_PAIR(r3);
7339 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7340 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7341 break;
7342 case OPC2_32_RRR1_MSUBM_H_LU:
7343 CHECK_REG_PAIR(r4);
7344 CHECK_REG_PAIR(r3);
7345 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7346 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7347 break;
7348 case OPC2_32_RRR1_MSUBM_H_UL:
7349 CHECK_REG_PAIR(r4);
7350 CHECK_REG_PAIR(r3);
7351 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7352 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7353 break;
7354 case OPC2_32_RRR1_MSUBM_H_UU:
7355 CHECK_REG_PAIR(r4);
7356 CHECK_REG_PAIR(r3);
7357 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7358 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7359 break;
7360 case OPC2_32_RRR1_MSUBMS_H_LL:
7361 CHECK_REG_PAIR(r4);
7362 CHECK_REG_PAIR(r3);
7363 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7364 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7365 break;
7366 case OPC2_32_RRR1_MSUBMS_H_LU:
7367 CHECK_REG_PAIR(r4);
7368 CHECK_REG_PAIR(r3);
7369 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7370 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7371 break;
7372 case OPC2_32_RRR1_MSUBMS_H_UL:
7373 CHECK_REG_PAIR(r4);
7374 CHECK_REG_PAIR(r3);
7375 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7376 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7377 break;
7378 case OPC2_32_RRR1_MSUBMS_H_UU:
7379 CHECK_REG_PAIR(r4);
7380 CHECK_REG_PAIR(r3);
7381 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7382 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7383 break;
7384 case OPC2_32_RRR1_MSUBR_H_LL:
7385 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7386 cpu_gpr_d[r2], n, MODE_LL);
7387 break;
7388 case OPC2_32_RRR1_MSUBR_H_LU:
7389 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7390 cpu_gpr_d[r2], n, MODE_LU);
7391 break;
7392 case OPC2_32_RRR1_MSUBR_H_UL:
7393 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7394 cpu_gpr_d[r2], n, MODE_UL);
7395 break;
7396 case OPC2_32_RRR1_MSUBR_H_UU:
7397 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7398 cpu_gpr_d[r2], n, MODE_UU);
7399 break;
7400 case OPC2_32_RRR1_MSUBRS_H_LL:
7401 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7402 cpu_gpr_d[r2], n, MODE_LL);
7403 break;
7404 case OPC2_32_RRR1_MSUBRS_H_LU:
7405 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7406 cpu_gpr_d[r2], n, MODE_LU);
7407 break;
7408 case OPC2_32_RRR1_MSUBRS_H_UL:
7409 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7410 cpu_gpr_d[r2], n, MODE_UL);
7411 break;
7412 case OPC2_32_RRR1_MSUBRS_H_UU:
7413 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7414 cpu_gpr_d[r2], n, MODE_UU);
7415 break;
7416 default:
7417 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7418 }
7419 }
7420
7421 static void decode_rrr1_msubq_h(DisasContext *ctx)
7422 {
7423 uint32_t op2;
7424 uint32_t r1, r2, r3, r4, n;
7425 TCGv temp, temp2;
7426
7427 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7428 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7429 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7430 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7431 r4 = MASK_OP_RRR1_D(ctx->opcode);
7432 n = MASK_OP_RRR1_N(ctx->opcode);
7433
7434 temp = tcg_temp_new();
7435 temp2 = tcg_temp_new();
7436
7437 switch (op2) {
7438 case OPC2_32_RRR1_MSUB_Q_32:
7439 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7440 cpu_gpr_d[r2], n, 32);
7441 break;
7442 case OPC2_32_RRR1_MSUB_Q_64:
7443 CHECK_REG_PAIR(r4);
7444 CHECK_REG_PAIR(r3);
7445 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7446 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7447 n);
7448 break;
7449 case OPC2_32_RRR1_MSUB_Q_32_L:
7450 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7451 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7452 temp, n, 16);
7453 break;
7454 case OPC2_32_RRR1_MSUB_Q_64_L:
7455 CHECK_REG_PAIR(r4);
7456 CHECK_REG_PAIR(r3);
7457 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7458 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7459 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7460 n);
7461 break;
7462 case OPC2_32_RRR1_MSUB_Q_32_U:
7463 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7464 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7465 temp, n, 16);
7466 break;
7467 case OPC2_32_RRR1_MSUB_Q_64_U:
7468 CHECK_REG_PAIR(r4);
7469 CHECK_REG_PAIR(r3);
7470 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7471 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7472 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7473 n);
7474 break;
7475 case OPC2_32_RRR1_MSUB_Q_32_LL:
7476 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7477 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7478 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7479 break;
7480 case OPC2_32_RRR1_MSUB_Q_64_LL:
7481 CHECK_REG_PAIR(r4);
7482 CHECK_REG_PAIR(r3);
7483 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7484 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7485 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7486 cpu_gpr_d[r3+1], temp, temp2, n);
7487 break;
7488 case OPC2_32_RRR1_MSUB_Q_32_UU:
7489 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7490 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7491 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7492 break;
7493 case OPC2_32_RRR1_MSUB_Q_64_UU:
7494 CHECK_REG_PAIR(r4);
7495 CHECK_REG_PAIR(r3);
7496 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7497 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7498 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7499 cpu_gpr_d[r3+1], temp, temp2, n);
7500 break;
7501 case OPC2_32_RRR1_MSUBS_Q_32:
7502 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7503 cpu_gpr_d[r2], n, 32);
7504 break;
7505 case OPC2_32_RRR1_MSUBS_Q_64:
7506 CHECK_REG_PAIR(r4);
7507 CHECK_REG_PAIR(r3);
7508 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7509 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7510 n);
7511 break;
7512 case OPC2_32_RRR1_MSUBS_Q_32_L:
7513 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7514 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7515 temp, n, 16);
7516 break;
7517 case OPC2_32_RRR1_MSUBS_Q_64_L:
7518 CHECK_REG_PAIR(r4);
7519 CHECK_REG_PAIR(r3);
7520 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7521 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7522 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7523 n);
7524 break;
7525 case OPC2_32_RRR1_MSUBS_Q_32_U:
7526 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7527 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7528 temp, n, 16);
7529 break;
7530 case OPC2_32_RRR1_MSUBS_Q_64_U:
7531 CHECK_REG_PAIR(r4);
7532 CHECK_REG_PAIR(r3);
7533 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7534 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7535 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7536 n);
7537 break;
7538 case OPC2_32_RRR1_MSUBS_Q_32_LL:
7539 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7540 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7541 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7542 break;
7543 case OPC2_32_RRR1_MSUBS_Q_64_LL:
7544 CHECK_REG_PAIR(r4);
7545 CHECK_REG_PAIR(r3);
7546 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7547 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7548 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7549 cpu_gpr_d[r3+1], temp, temp2, n);
7550 break;
7551 case OPC2_32_RRR1_MSUBS_Q_32_UU:
7552 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7553 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7554 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7555 break;
7556 case OPC2_32_RRR1_MSUBS_Q_64_UU:
7557 CHECK_REG_PAIR(r4);
7558 CHECK_REG_PAIR(r3);
7559 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7560 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7561 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7562 cpu_gpr_d[r3+1], temp, temp2, n);
7563 break;
7564 case OPC2_32_RRR1_MSUBR_H_64_UL:
7565 CHECK_REG_PAIR(r3);
7566 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7567 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7568 break;
7569 case OPC2_32_RRR1_MSUBRS_H_64_UL:
7570 CHECK_REG_PAIR(r3);
7571 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7572 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7573 break;
7574 case OPC2_32_RRR1_MSUBR_Q_32_LL:
7575 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7576 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7577 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7578 break;
7579 case OPC2_32_RRR1_MSUBR_Q_32_UU:
7580 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7581 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7582 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7583 break;
7584 case OPC2_32_RRR1_MSUBRS_Q_32_LL:
7585 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7586 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7587 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7588 break;
7589 case OPC2_32_RRR1_MSUBRS_Q_32_UU:
7590 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7591 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7592 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7593 break;
7594 default:
7595 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7596 }
7597 }
7598
7599 static void decode_rrr1_msubad_h(DisasContext *ctx)
7600 {
7601 uint32_t op2;
7602 uint32_t r1, r2, r3, r4, n;
7603
7604 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7605 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7606 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7607 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7608 r4 = MASK_OP_RRR1_D(ctx->opcode);
7609 n = MASK_OP_RRR1_N(ctx->opcode);
7610
7611 switch (op2) {
7612 case OPC2_32_RRR1_MSUBAD_H_32_LL:
7613 CHECK_REG_PAIR(r4);
7614 CHECK_REG_PAIR(r3);
7615 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7616 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7617 break;
7618 case OPC2_32_RRR1_MSUBAD_H_32_LU:
7619 CHECK_REG_PAIR(r4);
7620 CHECK_REG_PAIR(r3);
7621 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7622 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7623 break;
7624 case OPC2_32_RRR1_MSUBAD_H_32_UL:
7625 CHECK_REG_PAIR(r4);
7626 CHECK_REG_PAIR(r3);
7627 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7628 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7629 break;
7630 case OPC2_32_RRR1_MSUBAD_H_32_UU:
7631 CHECK_REG_PAIR(r4);
7632 CHECK_REG_PAIR(r3);
7633 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7634 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7635 break;
7636 case OPC2_32_RRR1_MSUBADS_H_32_LL:
7637 CHECK_REG_PAIR(r4);
7638 CHECK_REG_PAIR(r3);
7639 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7640 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7641 n, MODE_LL);
7642 break;
7643 case OPC2_32_RRR1_MSUBADS_H_32_LU:
7644 CHECK_REG_PAIR(r4);
7645 CHECK_REG_PAIR(r3);
7646 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7647 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7648 n, MODE_LU);
7649 break;
7650 case OPC2_32_RRR1_MSUBADS_H_32_UL:
7651 CHECK_REG_PAIR(r4);
7652 CHECK_REG_PAIR(r3);
7653 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7654 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7655 n, MODE_UL);
7656 break;
7657 case OPC2_32_RRR1_MSUBADS_H_32_UU:
7658 CHECK_REG_PAIR(r4);
7659 CHECK_REG_PAIR(r3);
7660 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7661 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7662 n, MODE_UU);
7663 break;
7664 case OPC2_32_RRR1_MSUBADM_H_64_LL:
7665 CHECK_REG_PAIR(r4);
7666 CHECK_REG_PAIR(r3);
7667 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7668 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7669 n, MODE_LL);
7670 break;
7671 case OPC2_32_RRR1_MSUBADM_H_64_LU:
7672 CHECK_REG_PAIR(r4);
7673 CHECK_REG_PAIR(r3);
7674 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7675 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7676 n, MODE_LU);
7677 break;
7678 case OPC2_32_RRR1_MSUBADM_H_64_UL:
7679 CHECK_REG_PAIR(r4);
7680 CHECK_REG_PAIR(r3);
7681 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7682 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7683 n, MODE_UL);
7684 break;
7685 case OPC2_32_RRR1_MSUBADM_H_64_UU:
7686 CHECK_REG_PAIR(r4);
7687 CHECK_REG_PAIR(r3);
7688 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7689 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7690 n, MODE_UU);
7691 break;
7692 case OPC2_32_RRR1_MSUBADMS_H_64_LL:
7693 CHECK_REG_PAIR(r4);
7694 CHECK_REG_PAIR(r3);
7695 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7696 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7697 n, MODE_LL);
7698 break;
7699 case OPC2_32_RRR1_MSUBADMS_H_64_LU:
7700 CHECK_REG_PAIR(r4);
7701 CHECK_REG_PAIR(r3);
7702 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7703 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7704 n, MODE_LU);
7705 break;
7706 case OPC2_32_RRR1_MSUBADMS_H_64_UL:
7707 CHECK_REG_PAIR(r4);
7708 CHECK_REG_PAIR(r3);
7709 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7710 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7711 n, MODE_UL);
7712 break;
7713 case OPC2_32_RRR1_MSUBADMS_H_64_UU:
7714 CHECK_REG_PAIR(r4);
7715 CHECK_REG_PAIR(r3);
7716 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7717 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7718 n, MODE_UU);
7719 break;
7720 case OPC2_32_RRR1_MSUBADR_H_16_LL:
7721 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7722 cpu_gpr_d[r2], n, MODE_LL);
7723 break;
7724 case OPC2_32_RRR1_MSUBADR_H_16_LU:
7725 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7726 cpu_gpr_d[r2], n, MODE_LU);
7727 break;
7728 case OPC2_32_RRR1_MSUBADR_H_16_UL:
7729 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7730 cpu_gpr_d[r2], n, MODE_UL);
7731 break;
7732 case OPC2_32_RRR1_MSUBADR_H_16_UU:
7733 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7734 cpu_gpr_d[r2], n, MODE_UU);
7735 break;
7736 case OPC2_32_RRR1_MSUBADRS_H_16_LL:
7737 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7738 cpu_gpr_d[r2], n, MODE_LL);
7739 break;
7740 case OPC2_32_RRR1_MSUBADRS_H_16_LU:
7741 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7742 cpu_gpr_d[r2], n, MODE_LU);
7743 break;
7744 case OPC2_32_RRR1_MSUBADRS_H_16_UL:
7745 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7746 cpu_gpr_d[r2], n, MODE_UL);
7747 break;
7748 case OPC2_32_RRR1_MSUBADRS_H_16_UU:
7749 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7750 cpu_gpr_d[r2], n, MODE_UU);
7751 break;
7752 default:
7753 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7754 }
7755 }
7756
7757 /* RRRR format */
7758 static void decode_rrrr_extract_insert(DisasContext *ctx)
7759 {
7760 uint32_t op2;
7761 int r1, r2, r3, r4;
7762 TCGv tmp_width, tmp_pos;
7763
7764 r1 = MASK_OP_RRRR_S1(ctx->opcode);
7765 r2 = MASK_OP_RRRR_S2(ctx->opcode);
7766 r3 = MASK_OP_RRRR_S3(ctx->opcode);
7767 r4 = MASK_OP_RRRR_D(ctx->opcode);
7768 op2 = MASK_OP_RRRR_OP2(ctx->opcode);
7769
7770 tmp_pos = tcg_temp_new();
7771 tmp_width = tcg_temp_new();
7772
7773 switch (op2) {
7774 case OPC2_32_RRRR_DEXTR:
7775 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7776 if (r1 == r2) {
7777 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7778 } else {
7779 TCGv msw = tcg_temp_new();
7780 TCGv zero = tcg_constant_tl(0);
7781 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
7782 tcg_gen_subfi_tl(msw, 32, tmp_pos);
7783 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw);
7784 /*
7785 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined
7786 * behaviour. So check that case here and set the low bits to zero
7787 * which effectivly returns cpu_gpr_d[r1]
7788 */
7789 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw);
7790 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw);
7791 }
7792 break;
7793 case OPC2_32_RRRR_EXTR:
7794 case OPC2_32_RRRR_EXTR_U:
7795 CHECK_REG_PAIR(r3);
7796 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7797 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7798 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
7799 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7800 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7801 tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
7802 if (op2 == OPC2_32_RRRR_EXTR) {
7803 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7804 } else {
7805 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7806 }
7807 break;
7808 case OPC2_32_RRRR_INSERT:
7809 CHECK_REG_PAIR(r3);
7810 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7811 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7812 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
7813 tmp_pos);
7814 break;
7815 default:
7816 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7817 }
7818 }
7819
7820 /* RRRW format */
7821 static void decode_rrrw_extract_insert(DisasContext *ctx)
7822 {
7823 uint32_t op2;
7824 int r1, r2, r3, r4;
7825 int32_t width;
7826
7827 TCGv temp, temp2;
7828
7829 op2 = MASK_OP_RRRW_OP2(ctx->opcode);
7830 r1 = MASK_OP_RRRW_S1(ctx->opcode);
7831 r2 = MASK_OP_RRRW_S2(ctx->opcode);
7832 r3 = MASK_OP_RRRW_S3(ctx->opcode);
7833 r4 = MASK_OP_RRRW_D(ctx->opcode);
7834 width = MASK_OP_RRRW_WIDTH(ctx->opcode);
7835
7836 temp = tcg_temp_new();
7837
7838 switch (op2) {
7839 case OPC2_32_RRRW_EXTR:
7840 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7841 tcg_gen_addi_tl(temp, temp, width);
7842 tcg_gen_subfi_tl(temp, 32, temp);
7843 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7844 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
7845 break;
7846 case OPC2_32_RRRW_EXTR_U:
7847 if (width == 0) {
7848 tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
7849 } else {
7850 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7851 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7852 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
7853 }
7854 break;
7855 case OPC2_32_RRRW_IMASK:
7856 temp2 = tcg_temp_new();
7857 CHECK_REG_PAIR(r4);
7858 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7859 tcg_gen_movi_tl(temp2, (1 << width) - 1);
7860 tcg_gen_shl_tl(temp2, temp2, temp);
7861 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
7862 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
7863 break;
7864 case OPC2_32_RRRW_INSERT:
7865 temp2 = tcg_temp_new();
7866
7867 tcg_gen_movi_tl(temp, width);
7868 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
7869 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
7870 break;
7871 default:
7872 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7873 }
7874 }
7875
7876 /* SYS Format*/
7877 static void decode_sys_interrupts(DisasContext *ctx)
7878 {
7879 uint32_t op2;
7880 uint32_t r1;
7881 TCGLabel *l1;
7882 TCGv tmp;
7883
7884 op2 = MASK_OP_SYS_OP2(ctx->opcode);
7885 r1 = MASK_OP_SYS_S1D(ctx->opcode);
7886
7887 switch (op2) {
7888 case OPC2_32_SYS_DEBUG:
7889 /* raise EXCP_DEBUG */
7890 break;
7891 case OPC2_32_SYS_DISABLE:
7892 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
7893 break;
7894 case OPC2_32_SYS_DISABLE_D:
7895 if (has_feature(ctx, TRICORE_FEATURE_16)) {
7896 tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, ctx->icr_ie_offset, 1);
7897 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
7898 } else {
7899 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7900 }
7901 case OPC2_32_SYS_DSYNC:
7902 break;
7903 case OPC2_32_SYS_ENABLE:
7904 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
7905 break;
7906 case OPC2_32_SYS_ISYNC:
7907 break;
7908 case OPC2_32_SYS_NOP:
7909 break;
7910 case OPC2_32_SYS_RET:
7911 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
7912 break;
7913 case OPC2_32_SYS_FRET:
7914 gen_fret(ctx);
7915 break;
7916 case OPC2_32_SYS_RFE:
7917 gen_helper_rfe(cpu_env);
7918 tcg_gen_exit_tb(NULL, 0);
7919 ctx->base.is_jmp = DISAS_NORETURN;
7920 break;
7921 case OPC2_32_SYS_RFM:
7922 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
7923 tmp = tcg_temp_new();
7924 l1 = gen_new_label();
7925
7926 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
7927 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
7928 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
7929 gen_helper_rfm(cpu_env);
7930 gen_set_label(l1);
7931 tcg_gen_exit_tb(NULL, 0);
7932 ctx->base.is_jmp = DISAS_NORETURN;
7933 } else {
7934 /* generate privilege trap */
7935 }
7936 break;
7937 case OPC2_32_SYS_RSLCX:
7938 gen_helper_rslcx(cpu_env);
7939 break;
7940 case OPC2_32_SYS_SVLCX:
7941 gen_helper_svlcx(cpu_env);
7942 break;
7943 case OPC2_32_SYS_RESTORE:
7944 if (has_feature(ctx, TRICORE_FEATURE_16)) {
7945 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
7946 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
7947 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
7948 } /* else raise privilege trap */
7949 } else {
7950 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7951 }
7952 break;
7953 case OPC2_32_SYS_TRAPSV:
7954 l1 = gen_new_label();
7955 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1);
7956 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF);
7957 gen_set_label(l1);
7958 break;
7959 case OPC2_32_SYS_TRAPV:
7960 l1 = gen_new_label();
7961 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1);
7962 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF);
7963 gen_set_label(l1);
7964 break;
7965 default:
7966 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7967 }
7968 }
7969
7970 static void decode_32Bit_opc(DisasContext *ctx)
7971 {
7972 int op1, op2;
7973 int32_t r1, r2, r3;
7974 int32_t address, const16;
7975 int8_t b, const4;
7976 int32_t bpos;
7977 TCGv temp, temp2, temp3;
7978
7979 op1 = MASK_OP_MAJOR(ctx->opcode);
7980
7981 /* handle JNZ.T opcode only being 7 bit long */
7982 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
7983 op1 = OPCM_32_BRN_JTT;
7984 }
7985
7986 switch (op1) {
7987 /* ABS-format */
7988 case OPCM_32_ABS_LDW:
7989 decode_abs_ldw(ctx);
7990 break;
7991 case OPCM_32_ABS_LDB:
7992 decode_abs_ldb(ctx);
7993 break;
7994 case OPCM_32_ABS_LDMST_SWAP:
7995 decode_abs_ldst_swap(ctx);
7996 break;
7997 case OPCM_32_ABS_LDST_CONTEXT:
7998 decode_abs_ldst_context(ctx);
7999 break;
8000 case OPCM_32_ABS_STORE:
8001 decode_abs_store(ctx);
8002 break;
8003 case OPCM_32_ABS_STOREB_H:
8004 decode_abs_storeb_h(ctx);
8005 break;
8006 case OPC1_32_ABS_STOREQ:
8007 address = MASK_OP_ABS_OFF18(ctx->opcode);
8008 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8009 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
8010 temp2 = tcg_temp_new();
8011
8012 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
8013 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
8014 break;
8015 case OPC1_32_ABS_LD_Q:
8016 address = MASK_OP_ABS_OFF18(ctx->opcode);
8017 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8018 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
8019
8020 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
8021 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
8022 break;
8023 case OPCM_32_ABS_LEA_LHA:
8024 address = MASK_OP_ABS_OFF18(ctx->opcode);
8025 r1 = MASK_OP_ABS_S1D(ctx->opcode);
8026
8027 if (has_feature(ctx, TRICORE_FEATURE_162)) {
8028 op2 = MASK_OP_ABS_OP2(ctx->opcode);
8029 if (op2 == OPC2_32_ABS_LHA) {
8030 tcg_gen_movi_tl(cpu_gpr_a[r1], address << 14);
8031 break;
8032 }
8033 /* otherwise translate regular LEA */
8034 }
8035
8036 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
8037 break;
8038 /* ABSB-format */
8039 case OPC1_32_ABSB_ST_T:
8040 address = MASK_OP_ABS_OFF18(ctx->opcode);
8041 b = MASK_OP_ABSB_B(ctx->opcode);
8042 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
8043
8044 temp = tcg_constant_i32(EA_ABS_FORMAT(address));
8045 temp2 = tcg_temp_new();
8046
8047 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
8048 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
8049 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
8050 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
8051 break;
8052 /* B-format */
8053 case OPC1_32_B_CALL:
8054 case OPC1_32_B_CALLA:
8055 case OPC1_32_B_FCALL:
8056 case OPC1_32_B_FCALLA:
8057 case OPC1_32_B_J:
8058 case OPC1_32_B_JA:
8059 case OPC1_32_B_JL:
8060 case OPC1_32_B_JLA:
8061 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
8062 gen_compute_branch(ctx, op1, 0, 0, 0, address);
8063 break;
8064 /* Bit-format */
8065 case OPCM_32_BIT_ANDACC:
8066 decode_bit_andacc(ctx);
8067 break;
8068 case OPCM_32_BIT_LOGICAL_T1:
8069 decode_bit_logical_t(ctx);
8070 break;
8071 case OPCM_32_BIT_INSERT:
8072 decode_bit_insert(ctx);
8073 break;
8074 case OPCM_32_BIT_LOGICAL_T2:
8075 decode_bit_logical_t2(ctx);
8076 break;
8077 case OPCM_32_BIT_ORAND:
8078 decode_bit_orand(ctx);
8079 break;
8080 case OPCM_32_BIT_SH_LOGIC1:
8081 decode_bit_sh_logic1(ctx);
8082 break;
8083 case OPCM_32_BIT_SH_LOGIC2:
8084 decode_bit_sh_logic2(ctx);
8085 break;
8086 /* BO Format */
8087 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
8088 decode_bo_addrmode_post_pre_base(ctx);
8089 break;
8090 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
8091 decode_bo_addrmode_bitreverse_circular(ctx);
8092 break;
8093 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
8094 decode_bo_addrmode_ld_post_pre_base(ctx);
8095 break;
8096 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
8097 decode_bo_addrmode_ld_bitreverse_circular(ctx);
8098 break;
8099 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
8100 decode_bo_addrmode_stctx_post_pre_base(ctx);
8101 break;
8102 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
8103 decode_bo_addrmode_ldmst_bitreverse_circular(ctx);
8104 break;
8105 /* BOL-format */
8106 case OPC1_32_BOL_LD_A_LONGOFF:
8107 case OPC1_32_BOL_LD_W_LONGOFF:
8108 case OPC1_32_BOL_LEA_LONGOFF:
8109 case OPC1_32_BOL_ST_W_LONGOFF:
8110 case OPC1_32_BOL_ST_A_LONGOFF:
8111 case OPC1_32_BOL_LD_B_LONGOFF:
8112 case OPC1_32_BOL_LD_BU_LONGOFF:
8113 case OPC1_32_BOL_LD_H_LONGOFF:
8114 case OPC1_32_BOL_LD_HU_LONGOFF:
8115 case OPC1_32_BOL_ST_B_LONGOFF:
8116 case OPC1_32_BOL_ST_H_LONGOFF:
8117 decode_bol_opc(ctx, op1);
8118 break;
8119 /* BRC Format */
8120 case OPCM_32_BRC_EQ_NEQ:
8121 case OPCM_32_BRC_GE:
8122 case OPCM_32_BRC_JLT:
8123 case OPCM_32_BRC_JNE:
8124 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
8125 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
8126 r1 = MASK_OP_BRC_S1(ctx->opcode);
8127 gen_compute_branch(ctx, op1, r1, 0, const4, address);
8128 break;
8129 /* BRN Format */
8130 case OPCM_32_BRN_JTT:
8131 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
8132 r1 = MASK_OP_BRN_S1(ctx->opcode);
8133 gen_compute_branch(ctx, op1, r1, 0, 0, address);
8134 break;
8135 /* BRR Format */
8136 case OPCM_32_BRR_EQ_NEQ:
8137 case OPCM_32_BRR_ADDR_EQ_NEQ:
8138 case OPCM_32_BRR_GE:
8139 case OPCM_32_BRR_JLT:
8140 case OPCM_32_BRR_JNE:
8141 case OPCM_32_BRR_JNZ:
8142 case OPCM_32_BRR_LOOP:
8143 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
8144 r2 = MASK_OP_BRR_S2(ctx->opcode);
8145 r1 = MASK_OP_BRR_S1(ctx->opcode);
8146 gen_compute_branch(ctx, op1, r1, r2, 0, address);
8147 break;
8148 /* RC Format */
8149 case OPCM_32_RC_LOGICAL_SHIFT:
8150 decode_rc_logical_shift(ctx);
8151 break;
8152 case OPCM_32_RC_ACCUMULATOR:
8153 decode_rc_accumulator(ctx);
8154 break;
8155 case OPCM_32_RC_SERVICEROUTINE:
8156 decode_rc_serviceroutine(ctx);
8157 break;
8158 case OPCM_32_RC_MUL:
8159 decode_rc_mul(ctx);
8160 break;
8161 /* RCPW Format */
8162 case OPCM_32_RCPW_MASK_INSERT:
8163 decode_rcpw_insert(ctx);
8164 break;
8165 /* RCRR Format */
8166 case OPC1_32_RCRR_INSERT:
8167 r1 = MASK_OP_RCRR_S1(ctx->opcode);
8168 r2 = MASK_OP_RCRR_S3(ctx->opcode);
8169 r3 = MASK_OP_RCRR_D(ctx->opcode);
8170 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
8171 temp = tcg_constant_i32(const16);
8172 temp2 = tcg_temp_new(); /* width*/
8173 temp3 = tcg_temp_new(); /* pos */
8174
8175 CHECK_REG_PAIR(r3);
8176
8177 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
8178 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
8179
8180 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
8181 break;
8182 /* RCRW Format */
8183 case OPCM_32_RCRW_MASK_INSERT:
8184 decode_rcrw_insert(ctx);
8185 break;
8186 /* RCR Format */
8187 case OPCM_32_RCR_COND_SELECT:
8188 decode_rcr_cond_select(ctx);
8189 break;
8190 case OPCM_32_RCR_MADD:
8191 decode_rcr_madd(ctx);
8192 break;
8193 case OPCM_32_RCR_MSUB:
8194 decode_rcr_msub(ctx);
8195 break;
8196 /* RLC Format */
8197 case OPC1_32_RLC_ADDI:
8198 case OPC1_32_RLC_ADDIH:
8199 case OPC1_32_RLC_ADDIH_A:
8200 case OPC1_32_RLC_MFCR:
8201 case OPC1_32_RLC_MOV:
8202 case OPC1_32_RLC_MOV_64:
8203 case OPC1_32_RLC_MOV_U:
8204 case OPC1_32_RLC_MOV_H:
8205 case OPC1_32_RLC_MOVH_A:
8206 case OPC1_32_RLC_MTCR:
8207 decode_rlc_opc(ctx, op1);
8208 break;
8209 /* RR Format */
8210 case OPCM_32_RR_ACCUMULATOR:
8211 decode_rr_accumulator(ctx);
8212 break;
8213 case OPCM_32_RR_LOGICAL_SHIFT:
8214 decode_rr_logical_shift(ctx);
8215 break;
8216 case OPCM_32_RR_ADDRESS:
8217 decode_rr_address(ctx);
8218 break;
8219 case OPCM_32_RR_IDIRECT:
8220 decode_rr_idirect(ctx);
8221 break;
8222 case OPCM_32_RR_DIVIDE:
8223 decode_rr_divide(ctx);
8224 break;
8225 /* RR1 Format */
8226 case OPCM_32_RR1_MUL:
8227 decode_rr1_mul(ctx);
8228 break;
8229 case OPCM_32_RR1_MULQ:
8230 decode_rr1_mulq(ctx);
8231 break;
8232 /* RR2 format */
8233 case OPCM_32_RR2_MUL:
8234 decode_rr2_mul(ctx);
8235 break;
8236 /* RRPW format */
8237 case OPCM_32_RRPW_EXTRACT_INSERT:
8238 decode_rrpw_extract_insert(ctx);
8239 break;
8240 case OPC1_32_RRPW_DEXTR:
8241 r1 = MASK_OP_RRPW_S1(ctx->opcode);
8242 r2 = MASK_OP_RRPW_S2(ctx->opcode);
8243 r3 = MASK_OP_RRPW_D(ctx->opcode);
8244 const16 = MASK_OP_RRPW_POS(ctx->opcode);
8245
8246 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1],
8247 32 - const16);
8248 break;
8249 /* RRR Format */
8250 case OPCM_32_RRR_COND_SELECT:
8251 decode_rrr_cond_select(ctx);
8252 break;
8253 case OPCM_32_RRR_DIVIDE:
8254 decode_rrr_divide(ctx);
8255 break;
8256 /* RRR2 Format */
8257 case OPCM_32_RRR2_MADD:
8258 decode_rrr2_madd(ctx);
8259 break;
8260 case OPCM_32_RRR2_MSUB:
8261 decode_rrr2_msub(ctx);
8262 break;
8263 /* RRR1 format */
8264 case OPCM_32_RRR1_MADD:
8265 decode_rrr1_madd(ctx);
8266 break;
8267 case OPCM_32_RRR1_MADDQ_H:
8268 decode_rrr1_maddq_h(ctx);
8269 break;
8270 case OPCM_32_RRR1_MADDSU_H:
8271 decode_rrr1_maddsu_h(ctx);
8272 break;
8273 case OPCM_32_RRR1_MSUB_H:
8274 decode_rrr1_msub(ctx);
8275 break;
8276 case OPCM_32_RRR1_MSUB_Q:
8277 decode_rrr1_msubq_h(ctx);
8278 break;
8279 case OPCM_32_RRR1_MSUBAD_H:
8280 decode_rrr1_msubad_h(ctx);
8281 break;
8282 /* RRRR format */
8283 case OPCM_32_RRRR_EXTRACT_INSERT:
8284 decode_rrrr_extract_insert(ctx);
8285 break;
8286 /* RRRW format */
8287 case OPCM_32_RRRW_EXTRACT_INSERT:
8288 decode_rrrw_extract_insert(ctx);
8289 break;
8290 /* SYS format */
8291 case OPCM_32_SYS_INTERRUPTS:
8292 decode_sys_interrupts(ctx);
8293 break;
8294 case OPC1_32_SYS_RSTV:
8295 tcg_gen_movi_tl(cpu_PSW_V, 0);
8296 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
8297 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
8298 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
8299 break;
8300 default:
8301 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8302 }
8303 }
8304
8305 static bool tricore_insn_is_16bit(uint32_t insn)
8306 {
8307 return (insn & 0x1) == 0;
8308 }
8309
8310 static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
8311 CPUState *cs)
8312 {
8313 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8314 CPUTriCoreState *env = cs->env_ptr;
8315 ctx->mem_idx = cpu_mmu_index(env, false);
8316 ctx->hflags = (uint32_t)ctx->base.tb->flags;
8317 ctx->features = env->features;
8318 if (has_feature(ctx, TRICORE_FEATURE_161)) {
8319 ctx->icr_ie_mask = R_ICR_IE_161_MASK;
8320 ctx->icr_ie_offset = R_ICR_IE_161_SHIFT;
8321 } else {
8322 ctx->icr_ie_mask = R_ICR_IE_13_MASK;
8323 ctx->icr_ie_offset = R_ICR_IE_13_SHIFT;
8324 }
8325 }
8326
8327 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu)
8328 {
8329 }
8330
8331 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
8332 {
8333 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8334
8335 tcg_gen_insn_start(ctx->base.pc_next);
8336 }
8337
8338 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
8339 {
8340 /*
8341 * Return true if the insn at ctx->base.pc_next might cross a page boundary.
8342 * (False positives are OK, false negatives are not.)
8343 * Our caller ensures we are only called if dc->base.pc_next is less than
8344 * 4 bytes from the page boundary, so we cross the page if the first
8345 * 16 bits indicate that this is a 32 bit insn.
8346 */
8347 uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
8348
8349 return !tricore_insn_is_16bit(insn);
8350 }
8351
8352
8353 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
8354 {
8355 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8356 CPUTriCoreState *env = cpu->env_ptr;
8357 uint16_t insn_lo;
8358 bool is_16bit;
8359
8360 insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
8361 is_16bit = tricore_insn_is_16bit(insn_lo);
8362 if (is_16bit) {
8363 ctx->opcode = insn_lo;
8364 ctx->pc_succ_insn = ctx->base.pc_next + 2;
8365 decode_16Bit_opc(ctx);
8366 } else {
8367 uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
8368 ctx->opcode = insn_hi << 16 | insn_lo;
8369 ctx->pc_succ_insn = ctx->base.pc_next + 4;
8370 decode_32Bit_opc(ctx);
8371 }
8372 ctx->base.pc_next = ctx->pc_succ_insn;
8373
8374 if (ctx->base.is_jmp == DISAS_NEXT) {
8375 target_ulong page_start;
8376
8377 page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
8378 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE
8379 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3
8380 && insn_crosses_page(env, ctx))) {
8381 ctx->base.is_jmp = DISAS_TOO_MANY;
8382 }
8383 }
8384 }
8385
8386 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
8387 {
8388 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8389
8390 switch (ctx->base.is_jmp) {
8391 case DISAS_TOO_MANY:
8392 gen_goto_tb(ctx, 0, ctx->base.pc_next);
8393 break;
8394 case DISAS_NORETURN:
8395 break;
8396 default:
8397 g_assert_not_reached();
8398 }
8399 }
8400
8401 static void tricore_tr_disas_log(const DisasContextBase *dcbase,
8402 CPUState *cpu, FILE *logfile)
8403 {
8404 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
8405 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
8406 }
8407
8408 static const TranslatorOps tricore_tr_ops = {
8409 .init_disas_context = tricore_tr_init_disas_context,
8410 .tb_start = tricore_tr_tb_start,
8411 .insn_start = tricore_tr_insn_start,
8412 .translate_insn = tricore_tr_translate_insn,
8413 .tb_stop = tricore_tr_tb_stop,
8414 .disas_log = tricore_tr_disas_log,
8415 };
8416
8417
8418 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
8419 target_ulong pc, void *host_pc)
8420 {
8421 DisasContext ctx;
8422 translator_loop(cs, tb, max_insns, pc, host_pc,
8423 &tricore_tr_ops, &ctx.base);
8424 }
8425
8426 /*
8427 *
8428 * Initialization
8429 *
8430 */
8431
8432 void cpu_state_reset(CPUTriCoreState *env)
8433 {
8434 /* Reset Regs to Default Value */
8435 env->PSW = 0xb80;
8436 fpu_set_state(env);
8437 }
8438
8439 static void tricore_tcg_init_csfr(void)
8440 {
8441 cpu_PCXI = tcg_global_mem_new(cpu_env,
8442 offsetof(CPUTriCoreState, PCXI), "PCXI");
8443 cpu_PSW = tcg_global_mem_new(cpu_env,
8444 offsetof(CPUTriCoreState, PSW), "PSW");
8445 cpu_PC = tcg_global_mem_new(cpu_env,
8446 offsetof(CPUTriCoreState, PC), "PC");
8447 cpu_ICR = tcg_global_mem_new(cpu_env,
8448 offsetof(CPUTriCoreState, ICR), "ICR");
8449 }
8450
8451 void tricore_tcg_init(void)
8452 {
8453 int i;
8454
8455 /* reg init */
8456 for (i = 0 ; i < 16 ; i++) {
8457 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
8458 offsetof(CPUTriCoreState, gpr_a[i]),
8459 regnames_a[i]);
8460 }
8461 for (i = 0 ; i < 16 ; i++) {
8462 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
8463 offsetof(CPUTriCoreState, gpr_d[i]),
8464 regnames_d[i]);
8465 }
8466 tricore_tcg_init_csfr();
8467 /* init PSW flag cache */
8468 cpu_PSW_C = tcg_global_mem_new(cpu_env,
8469 offsetof(CPUTriCoreState, PSW_USB_C),
8470 "PSW_C");
8471 cpu_PSW_V = tcg_global_mem_new(cpu_env,
8472 offsetof(CPUTriCoreState, PSW_USB_V),
8473 "PSW_V");
8474 cpu_PSW_SV = tcg_global_mem_new(cpu_env,
8475 offsetof(CPUTriCoreState, PSW_USB_SV),
8476 "PSW_SV");
8477 cpu_PSW_AV = tcg_global_mem_new(cpu_env,
8478 offsetof(CPUTriCoreState, PSW_USB_AV),
8479 "PSW_AV");
8480 cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
8481 offsetof(CPUTriCoreState, PSW_USB_SAV),
8482 "PSW_SAV");
8483 }
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