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target/tricore: Split t_n as constant from temp as variable
[mirror_qemu.git] / target / tricore / translate.c
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "exec/cpu_ldst.h"
27 #include "qemu/qemu-print.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "tricore-opcodes.h"
33 #include "exec/translator.h"
34 #include "exec/log.h"
35
36 /*
37 * TCG registers
38 */
39 static TCGv cpu_PC;
40 static TCGv cpu_PCXI;
41 static TCGv cpu_PSW;
42 static TCGv cpu_ICR;
43 /* GPR registers */
44 static TCGv cpu_gpr_a[16];
45 static TCGv cpu_gpr_d[16];
46 /* PSW Flag cache */
47 static TCGv cpu_PSW_C;
48 static TCGv cpu_PSW_V;
49 static TCGv cpu_PSW_SV;
50 static TCGv cpu_PSW_AV;
51 static TCGv cpu_PSW_SAV;
52
53 #include "exec/gen-icount.h"
54
55 static const char *regnames_a[] = {
56 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
57 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
58 "a12" , "a13" , "a14" , "a15",
59 };
60
61 static const char *regnames_d[] = {
62 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
63 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
64 "d12" , "d13" , "d14" , "d15",
65 };
66
67 typedef struct DisasContext {
68 DisasContextBase base;
69 target_ulong pc_succ_insn;
70 uint32_t opcode;
71 /* Routine used to access memory */
72 int mem_idx;
73 uint32_t hflags, saved_hflags;
74 uint64_t features;
75 } DisasContext;
76
77 static int has_feature(DisasContext *ctx, int feature)
78 {
79 return (ctx->features & (1ULL << feature)) != 0;
80 }
81
82 enum {
83 MODE_LL = 0,
84 MODE_LU = 1,
85 MODE_UL = 2,
86 MODE_UU = 3,
87 };
88
89 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags)
90 {
91 TriCoreCPU *cpu = TRICORE_CPU(cs);
92 CPUTriCoreState *env = &cpu->env;
93 uint32_t psw;
94 int i;
95
96 psw = psw_read(env);
97
98 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
99 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
100 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
101 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
102 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
103 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
104
105 for (i = 0; i < 16; ++i) {
106 if ((i & 3) == 0) {
107 qemu_fprintf(f, "\nGPR A%02d:", i);
108 }
109 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
110 }
111 for (i = 0; i < 16; ++i) {
112 if ((i & 3) == 0) {
113 qemu_fprintf(f, "\nGPR D%02d:", i);
114 }
115 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
116 }
117 qemu_fprintf(f, "\n");
118 }
119
120 /*
121 * Functions to generate micro-ops
122 */
123
124 /* Makros for generating helpers */
125
126 #define gen_helper_1arg(name, arg) do { \
127 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
128 gen_helper_##name(cpu_env, helper_tmp); \
129 } while (0)
130
131 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
132 TCGv arg00 = tcg_temp_new(); \
133 TCGv arg01 = tcg_temp_new(); \
134 TCGv arg11 = tcg_temp_new(); \
135 tcg_gen_sari_tl(arg00, arg0, 16); \
136 tcg_gen_ext16s_tl(arg01, arg0); \
137 tcg_gen_ext16s_tl(arg11, arg1); \
138 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
139 } while (0)
140
141 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
142 TCGv arg00 = tcg_temp_new(); \
143 TCGv arg01 = tcg_temp_new(); \
144 TCGv arg10 = tcg_temp_new(); \
145 TCGv arg11 = tcg_temp_new(); \
146 tcg_gen_sari_tl(arg00, arg0, 16); \
147 tcg_gen_ext16s_tl(arg01, arg0); \
148 tcg_gen_sari_tl(arg11, arg1, 16); \
149 tcg_gen_ext16s_tl(arg10, arg1); \
150 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
151 } while (0)
152
153 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
154 TCGv arg00 = tcg_temp_new(); \
155 TCGv arg01 = tcg_temp_new(); \
156 TCGv arg10 = tcg_temp_new(); \
157 TCGv arg11 = tcg_temp_new(); \
158 tcg_gen_sari_tl(arg00, arg0, 16); \
159 tcg_gen_ext16s_tl(arg01, arg0); \
160 tcg_gen_sari_tl(arg10, arg1, 16); \
161 tcg_gen_ext16s_tl(arg11, arg1); \
162 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
163 } while (0)
164
165 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
166 TCGv arg00 = tcg_temp_new(); \
167 TCGv arg01 = tcg_temp_new(); \
168 TCGv arg11 = tcg_temp_new(); \
169 tcg_gen_sari_tl(arg01, arg0, 16); \
170 tcg_gen_ext16s_tl(arg00, arg0); \
171 tcg_gen_sari_tl(arg11, arg1, 16); \
172 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
173 } while (0)
174
175 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
176 TCGv_i64 ret = tcg_temp_new_i64(); \
177 TCGv_i64 arg1 = tcg_temp_new_i64(); \
178 \
179 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
180 gen_helper_##name(ret, arg1, arg2); \
181 tcg_gen_extr_i64_i32(rl, rh, ret); \
182 } while (0)
183
184 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
185 TCGv_i64 ret = tcg_temp_new_i64(); \
186 \
187 gen_helper_##name(ret, cpu_env, arg1, arg2); \
188 tcg_gen_extr_i64_i32(rl, rh, ret); \
189 } while (0)
190
191 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
192 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
193 ((offset & 0x0fffff) << 1))
194
195 /* For two 32-bit registers used a 64-bit register, the first
196 registernumber needs to be even. Otherwise we trap. */
197 static inline void generate_trap(DisasContext *ctx, int class, int tin);
198 #define CHECK_REG_PAIR(reg) do { \
199 if (reg & 0x1) { \
200 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
201 } \
202 } while (0)
203
204 /* Functions for load/save to/from memory */
205
206 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
207 int16_t con, MemOp mop)
208 {
209 TCGv temp = tcg_temp_new();
210 tcg_gen_addi_tl(temp, r2, con);
211 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
212 }
213
214 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
215 int16_t con, MemOp mop)
216 {
217 TCGv temp = tcg_temp_new();
218 tcg_gen_addi_tl(temp, r2, con);
219 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
220 }
221
222 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
223 {
224 TCGv_i64 temp = tcg_temp_new_i64();
225
226 tcg_gen_concat_i32_i64(temp, rl, rh);
227 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ);
228 }
229
230 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
231 DisasContext *ctx)
232 {
233 TCGv temp = tcg_temp_new();
234 tcg_gen_addi_tl(temp, base, con);
235 gen_st_2regs_64(rh, rl, temp, ctx);
236 }
237
238 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
239 {
240 TCGv_i64 temp = tcg_temp_new_i64();
241
242 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ);
243 /* write back to two 32 bit regs */
244 tcg_gen_extr_i64_i32(rl, rh, temp);
245 }
246
247 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
248 DisasContext *ctx)
249 {
250 TCGv temp = tcg_temp_new();
251 tcg_gen_addi_tl(temp, base, con);
252 gen_ld_2regs_64(rh, rl, temp, ctx);
253 }
254
255 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
256 MemOp mop)
257 {
258 TCGv temp = tcg_temp_new();
259 tcg_gen_addi_tl(temp, r2, off);
260 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
261 tcg_gen_mov_tl(r2, temp);
262 }
263
264 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
265 MemOp mop)
266 {
267 TCGv temp = tcg_temp_new();
268 tcg_gen_addi_tl(temp, r2, off);
269 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
270 tcg_gen_mov_tl(r2, temp);
271 }
272
273 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
274 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
275 {
276 TCGv temp = tcg_temp_new();
277 TCGv temp2 = tcg_temp_new();
278
279 CHECK_REG_PAIR(ereg);
280 /* temp = (M(EA, word) */
281 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
282 /* temp = temp & ~E[a][63:32]) */
283 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
284 /* temp2 = (E[a][31:0] & E[a][63:32]); */
285 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
286 /* temp = temp | temp2; */
287 tcg_gen_or_tl(temp, temp, temp2);
288 /* M(EA, word) = temp; */
289 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
290 }
291
292 /* tmp = M(EA, word);
293 M(EA, word) = D[a];
294 D[a] = tmp[31:0];*/
295 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
296 {
297 TCGv temp = tcg_temp_new();
298
299 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
300 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
301 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
302 }
303
304 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
305 {
306 TCGv temp = tcg_temp_new();
307 TCGv temp2 = tcg_temp_new();
308 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
309 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
310 cpu_gpr_d[reg], temp);
311 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
312 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
313 }
314
315 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
316 {
317 TCGv temp = tcg_temp_new();
318 TCGv temp2 = tcg_temp_new();
319 TCGv temp3 = tcg_temp_new();
320
321 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
322 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
323 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
324 tcg_gen_or_tl(temp2, temp2, temp3);
325 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
326 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
327 }
328
329
330 /* We generate loads and store to core special function register (csfr) through
331 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
332 makros R, A and E, which allow read-only, all and endinit protected access.
333 These makros also specify in which ISA version the csfr was introduced. */
334 #define R(ADDRESS, REG, FEATURE) \
335 case ADDRESS: \
336 if (has_feature(ctx, FEATURE)) { \
337 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
338 } \
339 break;
340 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
341 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
342 static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
343 {
344 /* since we're caching PSW make this a special case */
345 if (offset == 0xfe04) {
346 gen_helper_psw_read(ret, cpu_env);
347 } else {
348 switch (offset) {
349 #include "csfr.h.inc"
350 }
351 }
352 }
353 #undef R
354 #undef A
355 #undef E
356
357 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
358 since no execption occurs */
359 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
360 case ADDRESS: \
361 if (has_feature(ctx, FEATURE)) { \
362 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
363 } \
364 break;
365 /* Endinit protected registers
366 TODO: Since the endinit bit is in a register of a not yet implemented
367 watchdog device, we handle endinit protected registers like
368 all-access registers for now. */
369 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
370 static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
371 int32_t offset)
372 {
373 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
374 /* since we're caching PSW make this a special case */
375 if (offset == 0xfe04) {
376 gen_helper_psw_write(cpu_env, r1);
377 } else {
378 switch (offset) {
379 #include "csfr.h.inc"
380 }
381 }
382 } else {
383 /* generate privilege trap */
384 }
385 }
386
387 /* Functions for arithmetic instructions */
388
389 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
390 {
391 TCGv t0 = tcg_temp_new_i32();
392 TCGv result = tcg_temp_new_i32();
393 /* Addition and set V/SV bits */
394 tcg_gen_add_tl(result, r1, r2);
395 /* calc V bit */
396 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
397 tcg_gen_xor_tl(t0, r1, r2);
398 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
399 /* Calc SV bit */
400 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
401 /* Calc AV/SAV bits */
402 tcg_gen_add_tl(cpu_PSW_AV, result, result);
403 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
404 /* calc SAV */
405 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
406 /* write back result */
407 tcg_gen_mov_tl(ret, result);
408 }
409
410 static inline void
411 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
412 {
413 TCGv temp = tcg_temp_new();
414 TCGv_i64 t0 = tcg_temp_new_i64();
415 TCGv_i64 t1 = tcg_temp_new_i64();
416 TCGv_i64 result = tcg_temp_new_i64();
417
418 tcg_gen_add_i64(result, r1, r2);
419 /* calc v bit */
420 tcg_gen_xor_i64(t1, result, r1);
421 tcg_gen_xor_i64(t0, r1, r2);
422 tcg_gen_andc_i64(t1, t1, t0);
423 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
424 /* calc SV bit */
425 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
426 /* calc AV/SAV bits */
427 tcg_gen_extrh_i64_i32(temp, result);
428 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
429 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
430 /* calc SAV */
431 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
432 /* write back result */
433 tcg_gen_mov_i64(ret, result);
434 }
435
436 static inline void
437 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
438 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
439 void(*op2)(TCGv, TCGv, TCGv))
440 {
441 TCGv temp = tcg_temp_new();
442 TCGv temp2 = tcg_temp_new();
443 TCGv temp3 = tcg_temp_new();
444 TCGv temp4 = tcg_temp_new();
445
446 (*op1)(temp, r1_low, r2);
447 /* calc V0 bit */
448 tcg_gen_xor_tl(temp2, temp, r1_low);
449 tcg_gen_xor_tl(temp3, r1_low, r2);
450 if (op1 == tcg_gen_add_tl) {
451 tcg_gen_andc_tl(temp2, temp2, temp3);
452 } else {
453 tcg_gen_and_tl(temp2, temp2, temp3);
454 }
455
456 (*op2)(temp3, r1_high, r3);
457 /* calc V1 bit */
458 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
459 tcg_gen_xor_tl(temp4, r1_high, r3);
460 if (op2 == tcg_gen_add_tl) {
461 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
462 } else {
463 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
464 }
465 /* combine V0/V1 bits */
466 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
467 /* calc sv bit */
468 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
469 /* write result */
470 tcg_gen_mov_tl(ret_low, temp);
471 tcg_gen_mov_tl(ret_high, temp3);
472 /* calc AV bit */
473 tcg_gen_add_tl(temp, ret_low, ret_low);
474 tcg_gen_xor_tl(temp, temp, ret_low);
475 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
476 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
477 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
478 /* calc SAV bit */
479 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
480 }
481
482 /* ret = r2 + (r1 * r3); */
483 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
484 {
485 TCGv_i64 t1 = tcg_temp_new_i64();
486 TCGv_i64 t2 = tcg_temp_new_i64();
487 TCGv_i64 t3 = tcg_temp_new_i64();
488
489 tcg_gen_ext_i32_i64(t1, r1);
490 tcg_gen_ext_i32_i64(t2, r2);
491 tcg_gen_ext_i32_i64(t3, r3);
492
493 tcg_gen_mul_i64(t1, t1, t3);
494 tcg_gen_add_i64(t1, t2, t1);
495
496 tcg_gen_extrl_i64_i32(ret, t1);
497 /* calc V
498 t1 > 0x7fffffff */
499 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
500 /* t1 < -0x80000000 */
501 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
502 tcg_gen_or_i64(t2, t2, t3);
503 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
504 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
505 /* Calc SV bit */
506 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
507 /* Calc AV/SAV bits */
508 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
509 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
510 /* calc SAV */
511 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
512 }
513
514 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
515 {
516 TCGv temp = tcg_const_i32(con);
517 gen_madd32_d(ret, r1, r2, temp);
518 }
519
520 static inline void
521 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
522 TCGv r3)
523 {
524 TCGv t1 = tcg_temp_new();
525 TCGv t2 = tcg_temp_new();
526 TCGv t3 = tcg_temp_new();
527 TCGv t4 = tcg_temp_new();
528
529 tcg_gen_muls2_tl(t1, t2, r1, r3);
530 /* only the add can overflow */
531 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
532 /* calc V bit */
533 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
534 tcg_gen_xor_tl(t1, r2_high, t2);
535 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
536 /* Calc SV bit */
537 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
538 /* Calc AV/SAV bits */
539 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
540 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
541 /* calc SAV */
542 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
543 /* write back the result */
544 tcg_gen_mov_tl(ret_low, t3);
545 tcg_gen_mov_tl(ret_high, t4);
546 }
547
548 static inline void
549 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
550 TCGv r3)
551 {
552 TCGv_i64 t1 = tcg_temp_new_i64();
553 TCGv_i64 t2 = tcg_temp_new_i64();
554 TCGv_i64 t3 = tcg_temp_new_i64();
555
556 tcg_gen_extu_i32_i64(t1, r1);
557 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
558 tcg_gen_extu_i32_i64(t3, r3);
559
560 tcg_gen_mul_i64(t1, t1, t3);
561 tcg_gen_add_i64(t2, t2, t1);
562 /* write back result */
563 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
564 /* only the add overflows, if t2 < t1
565 calc V bit */
566 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
567 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
568 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
569 /* Calc SV bit */
570 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
571 /* Calc AV/SAV bits */
572 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
573 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
574 /* calc SAV */
575 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
576 }
577
578 static inline void
579 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
580 int32_t con)
581 {
582 TCGv temp = tcg_const_i32(con);
583 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
584 }
585
586 static inline void
587 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
588 int32_t con)
589 {
590 TCGv temp = tcg_const_i32(con);
591 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
592 }
593
594 static inline void
595 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
596 TCGv r3, uint32_t n, uint32_t mode)
597 {
598 TCGv t_n = tcg_constant_i32(n);
599 TCGv temp = tcg_temp_new();
600 TCGv temp2 = tcg_temp_new();
601 TCGv_i64 temp64 = tcg_temp_new_i64();
602 switch (mode) {
603 case MODE_LL:
604 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
605 break;
606 case MODE_LU:
607 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
608 break;
609 case MODE_UL:
610 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
611 break;
612 case MODE_UU:
613 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
614 break;
615 }
616 tcg_gen_extr_i64_i32(temp, temp2, temp64);
617 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
618 tcg_gen_add_tl, tcg_gen_add_tl);
619 }
620
621 static inline void
622 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
623 TCGv r3, uint32_t n, uint32_t mode)
624 {
625 TCGv t_n = tcg_constant_i32(n);
626 TCGv temp = tcg_temp_new();
627 TCGv temp2 = tcg_temp_new();
628 TCGv_i64 temp64 = tcg_temp_new_i64();
629 switch (mode) {
630 case MODE_LL:
631 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
632 break;
633 case MODE_LU:
634 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
635 break;
636 case MODE_UL:
637 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
638 break;
639 case MODE_UU:
640 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
641 break;
642 }
643 tcg_gen_extr_i64_i32(temp, temp2, temp64);
644 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
645 tcg_gen_sub_tl, tcg_gen_add_tl);
646 }
647
648 static inline void
649 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
650 TCGv r3, uint32_t n, uint32_t mode)
651 {
652 TCGv t_n = tcg_constant_i32(n);
653 TCGv_i64 temp64 = tcg_temp_new_i64();
654 TCGv_i64 temp64_2 = tcg_temp_new_i64();
655 TCGv_i64 temp64_3 = tcg_temp_new_i64();
656 switch (mode) {
657 case MODE_LL:
658 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
659 break;
660 case MODE_LU:
661 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
662 break;
663 case MODE_UL:
664 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
665 break;
666 case MODE_UU:
667 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
668 break;
669 }
670 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
671 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
672 tcg_gen_ext32s_i64(temp64, temp64); /* low */
673 tcg_gen_sub_i64(temp64, temp64_2, temp64);
674 tcg_gen_shli_i64(temp64, temp64, 16);
675
676 gen_add64_d(temp64_2, temp64_3, temp64);
677 /* write back result */
678 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
679 }
680
681 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
682
683 static inline void
684 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
685 TCGv r3, uint32_t n, uint32_t mode)
686 {
687 TCGv t_n = tcg_constant_i32(n);
688 TCGv temp = tcg_temp_new();
689 TCGv temp2 = tcg_temp_new();
690 TCGv temp3 = tcg_temp_new();
691 TCGv_i64 temp64 = tcg_temp_new_i64();
692
693 switch (mode) {
694 case MODE_LL:
695 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
696 break;
697 case MODE_LU:
698 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
699 break;
700 case MODE_UL:
701 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
702 break;
703 case MODE_UU:
704 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
705 break;
706 }
707 tcg_gen_extr_i64_i32(temp, temp2, temp64);
708 gen_adds(ret_low, r1_low, temp);
709 tcg_gen_mov_tl(temp, cpu_PSW_V);
710 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
711 gen_adds(ret_high, r1_high, temp2);
712 /* combine v bits */
713 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
714 /* combine av bits */
715 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
716 }
717
718 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
719
720 static inline void
721 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
722 TCGv r3, uint32_t n, uint32_t mode)
723 {
724 TCGv t_n = tcg_constant_i32(n);
725 TCGv temp = tcg_temp_new();
726 TCGv temp2 = tcg_temp_new();
727 TCGv temp3 = tcg_temp_new();
728 TCGv_i64 temp64 = tcg_temp_new_i64();
729
730 switch (mode) {
731 case MODE_LL:
732 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
733 break;
734 case MODE_LU:
735 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
736 break;
737 case MODE_UL:
738 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
739 break;
740 case MODE_UU:
741 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
742 break;
743 }
744 tcg_gen_extr_i64_i32(temp, temp2, temp64);
745 gen_subs(ret_low, r1_low, temp);
746 tcg_gen_mov_tl(temp, cpu_PSW_V);
747 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
748 gen_adds(ret_high, r1_high, temp2);
749 /* combine v bits */
750 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
751 /* combine av bits */
752 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
753 }
754
755 static inline void
756 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
757 TCGv r3, uint32_t n, uint32_t mode)
758 {
759 TCGv t_n = tcg_constant_i32(n);
760 TCGv_i64 temp64 = tcg_temp_new_i64();
761 TCGv_i64 temp64_2 = tcg_temp_new_i64();
762
763 switch (mode) {
764 case MODE_LL:
765 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
766 break;
767 case MODE_LU:
768 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
769 break;
770 case MODE_UL:
771 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
772 break;
773 case MODE_UU:
774 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
775 break;
776 }
777 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
778 tcg_gen_ext32s_i64(temp64, temp64); /* low */
779 tcg_gen_sub_i64(temp64, temp64_2, temp64);
780 tcg_gen_shli_i64(temp64, temp64, 16);
781 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
782
783 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
784 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
785 }
786
787
788 static inline void
789 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
790 TCGv r3, uint32_t n, uint32_t mode)
791 {
792 TCGv t_n = tcg_constant_i32(n);
793 TCGv_i64 temp64 = tcg_temp_new_i64();
794 TCGv_i64 temp64_2 = tcg_temp_new_i64();
795 TCGv_i64 temp64_3 = tcg_temp_new_i64();
796 switch (mode) {
797 case MODE_LL:
798 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
799 break;
800 case MODE_LU:
801 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
802 break;
803 case MODE_UL:
804 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
805 break;
806 case MODE_UU:
807 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
808 break;
809 }
810 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
811 gen_add64_d(temp64_3, temp64_2, temp64);
812 /* write back result */
813 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
814 }
815
816 static inline void
817 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
818 TCGv r3, uint32_t n, uint32_t mode)
819 {
820 TCGv t_n = tcg_constant_i32(n);
821 TCGv_i64 temp64 = tcg_temp_new_i64();
822 TCGv_i64 temp64_2 = tcg_temp_new_i64();
823 switch (mode) {
824 case MODE_LL:
825 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
826 break;
827 case MODE_LU:
828 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
829 break;
830 case MODE_UL:
831 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
832 break;
833 case MODE_UU:
834 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
835 break;
836 }
837 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
838 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
839 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
840 }
841
842 static inline void
843 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
844 uint32_t mode)
845 {
846 TCGv t_n = tcg_constant_i32(n);
847 TCGv_i64 temp64 = tcg_temp_new_i64();
848 switch (mode) {
849 case MODE_LL:
850 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
851 break;
852 case MODE_LU:
853 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
854 break;
855 case MODE_UL:
856 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
857 break;
858 case MODE_UU:
859 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
860 break;
861 }
862 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
863 }
864
865 static inline void
866 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
867 {
868 TCGv temp = tcg_temp_new();
869 TCGv temp2 = tcg_temp_new();
870
871 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
872 tcg_gen_shli_tl(temp, r1, 16);
873 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
874 }
875
876 static inline void
877 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
878 {
879 TCGv t_n = tcg_constant_i32(n);
880 TCGv temp = tcg_temp_new();
881 TCGv temp2 = tcg_temp_new();
882 TCGv_i64 temp64 = tcg_temp_new_i64();
883 switch (mode) {
884 case MODE_LL:
885 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
886 break;
887 case MODE_LU:
888 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
889 break;
890 case MODE_UL:
891 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
892 break;
893 case MODE_UU:
894 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
895 break;
896 }
897 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
898 tcg_gen_shli_tl(temp, r1, 16);
899 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
900 }
901
902
903 static inline void
904 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
905 uint32_t n, uint32_t mode)
906 {
907 TCGv t_n = tcg_constant_i32(n);
908 TCGv_i64 temp64 = tcg_temp_new_i64();
909 switch (mode) {
910 case MODE_LL:
911 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
912 break;
913 case MODE_LU:
914 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
915 break;
916 case MODE_UL:
917 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
918 break;
919 case MODE_UU:
920 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
921 break;
922 }
923 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
924 }
925
926 static inline void
927 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
928 {
929 TCGv temp = tcg_temp_new();
930 TCGv temp2 = tcg_temp_new();
931
932 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
933 tcg_gen_shli_tl(temp, r1, 16);
934 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
935 }
936
937 static inline void
938 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
939 {
940 TCGv t_n = tcg_constant_i32(n);
941 TCGv temp = tcg_temp_new();
942 TCGv temp2 = tcg_temp_new();
943 TCGv_i64 temp64 = tcg_temp_new_i64();
944 switch (mode) {
945 case MODE_LL:
946 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
947 break;
948 case MODE_LU:
949 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
950 break;
951 case MODE_UL:
952 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
953 break;
954 case MODE_UU:
955 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
956 break;
957 }
958 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
959 tcg_gen_shli_tl(temp, r1, 16);
960 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
961 }
962
963 static inline void
964 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
965 {
966 TCGv t_n = tcg_constant_i32(n);
967 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n);
968 }
969
970 static inline void
971 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
972 {
973 TCGv t_n = tcg_constant_i32(n);
974 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n);
975 }
976
977 static inline void
978 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
979 uint32_t up_shift)
980 {
981 TCGv temp = tcg_temp_new();
982 TCGv temp2 = tcg_temp_new();
983 TCGv temp3 = tcg_temp_new();
984 TCGv_i64 t1 = tcg_temp_new_i64();
985 TCGv_i64 t2 = tcg_temp_new_i64();
986 TCGv_i64 t3 = tcg_temp_new_i64();
987
988 tcg_gen_ext_i32_i64(t2, arg2);
989 tcg_gen_ext_i32_i64(t3, arg3);
990
991 tcg_gen_mul_i64(t2, t2, t3);
992 tcg_gen_shli_i64(t2, t2, n);
993
994 tcg_gen_ext_i32_i64(t1, arg1);
995 tcg_gen_sari_i64(t2, t2, up_shift);
996
997 tcg_gen_add_i64(t3, t1, t2);
998 tcg_gen_extrl_i64_i32(temp3, t3);
999 /* calc v bit */
1000 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1001 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1002 tcg_gen_or_i64(t1, t1, t2);
1003 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1004 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1005 /* We produce an overflow on the host if the mul before was
1006 (0x80000000 * 0x80000000) << 1). If this is the
1007 case, we negate the ovf. */
1008 if (n == 1) {
1009 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1010 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1011 tcg_gen_and_tl(temp, temp, temp2);
1012 tcg_gen_shli_tl(temp, temp, 31);
1013 /* negate v bit, if special condition */
1014 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1015 }
1016 /* Calc SV bit */
1017 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1018 /* Calc AV/SAV bits */
1019 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1020 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1021 /* calc SAV */
1022 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1023 /* write back result */
1024 tcg_gen_mov_tl(ret, temp3);
1025 }
1026
1027 static inline void
1028 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1029 {
1030 TCGv temp = tcg_temp_new();
1031 TCGv temp2 = tcg_temp_new();
1032 if (n == 0) {
1033 tcg_gen_mul_tl(temp, arg2, arg3);
1034 } else { /* n is expected to be 1 */
1035 tcg_gen_mul_tl(temp, arg2, arg3);
1036 tcg_gen_shli_tl(temp, temp, 1);
1037 /* catch special case r1 = r2 = 0x8000 */
1038 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1039 tcg_gen_sub_tl(temp, temp, temp2);
1040 }
1041 gen_add_d(ret, arg1, temp);
1042 }
1043
1044 static inline void
1045 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1046 {
1047 TCGv temp = tcg_temp_new();
1048 TCGv temp2 = tcg_temp_new();
1049 if (n == 0) {
1050 tcg_gen_mul_tl(temp, arg2, arg3);
1051 } else { /* n is expected to be 1 */
1052 tcg_gen_mul_tl(temp, arg2, arg3);
1053 tcg_gen_shli_tl(temp, temp, 1);
1054 /* catch special case r1 = r2 = 0x8000 */
1055 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1056 tcg_gen_sub_tl(temp, temp, temp2);
1057 }
1058 gen_adds(ret, arg1, temp);
1059 }
1060
1061 static inline void
1062 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1063 TCGv arg3, uint32_t n)
1064 {
1065 TCGv temp = tcg_temp_new();
1066 TCGv temp2 = tcg_temp_new();
1067 TCGv_i64 t1 = tcg_temp_new_i64();
1068 TCGv_i64 t2 = tcg_temp_new_i64();
1069 TCGv_i64 t3 = tcg_temp_new_i64();
1070
1071 if (n == 0) {
1072 tcg_gen_mul_tl(temp, arg2, arg3);
1073 } else { /* n is expected to be 1 */
1074 tcg_gen_mul_tl(temp, arg2, arg3);
1075 tcg_gen_shli_tl(temp, temp, 1);
1076 /* catch special case r1 = r2 = 0x8000 */
1077 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1078 tcg_gen_sub_tl(temp, temp, temp2);
1079 }
1080 tcg_gen_ext_i32_i64(t2, temp);
1081 tcg_gen_shli_i64(t2, t2, 16);
1082 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1083 gen_add64_d(t3, t1, t2);
1084 /* write back result */
1085 tcg_gen_extr_i64_i32(rl, rh, t3);
1086 }
1087
1088 static inline void
1089 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1090 TCGv arg3, uint32_t n)
1091 {
1092 TCGv temp = tcg_temp_new();
1093 TCGv temp2 = tcg_temp_new();
1094 TCGv_i64 t1 = tcg_temp_new_i64();
1095 TCGv_i64 t2 = tcg_temp_new_i64();
1096
1097 if (n == 0) {
1098 tcg_gen_mul_tl(temp, arg2, arg3);
1099 } else { /* n is expected to be 1 */
1100 tcg_gen_mul_tl(temp, arg2, arg3);
1101 tcg_gen_shli_tl(temp, temp, 1);
1102 /* catch special case r1 = r2 = 0x8000 */
1103 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1104 tcg_gen_sub_tl(temp, temp, temp2);
1105 }
1106 tcg_gen_ext_i32_i64(t2, temp);
1107 tcg_gen_shli_i64(t2, t2, 16);
1108 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1109
1110 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1111 tcg_gen_extr_i64_i32(rl, rh, t1);
1112 }
1113
1114 static inline void
1115 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1116 TCGv arg3, uint32_t n)
1117 {
1118 TCGv_i64 t1 = tcg_temp_new_i64();
1119 TCGv_i64 t2 = tcg_temp_new_i64();
1120 TCGv_i64 t3 = tcg_temp_new_i64();
1121 TCGv_i64 t4 = tcg_temp_new_i64();
1122 TCGv temp, temp2;
1123
1124 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1125 tcg_gen_ext_i32_i64(t2, arg2);
1126 tcg_gen_ext_i32_i64(t3, arg3);
1127
1128 tcg_gen_mul_i64(t2, t2, t3);
1129 if (n != 0) {
1130 tcg_gen_shli_i64(t2, t2, 1);
1131 }
1132 tcg_gen_add_i64(t4, t1, t2);
1133 /* calc v bit */
1134 tcg_gen_xor_i64(t3, t4, t1);
1135 tcg_gen_xor_i64(t2, t1, t2);
1136 tcg_gen_andc_i64(t3, t3, t2);
1137 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1138 /* We produce an overflow on the host if the mul before was
1139 (0x80000000 * 0x80000000) << 1). If this is the
1140 case, we negate the ovf. */
1141 if (n == 1) {
1142 temp = tcg_temp_new();
1143 temp2 = tcg_temp_new();
1144 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1145 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1146 tcg_gen_and_tl(temp, temp, temp2);
1147 tcg_gen_shli_tl(temp, temp, 31);
1148 /* negate v bit, if special condition */
1149 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1150 }
1151 /* write back result */
1152 tcg_gen_extr_i64_i32(rl, rh, t4);
1153 /* Calc SV bit */
1154 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1155 /* Calc AV/SAV bits */
1156 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1157 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1158 /* calc SAV */
1159 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1160 }
1161
1162 static inline void
1163 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1164 uint32_t up_shift)
1165 {
1166 TCGv_i64 t1 = tcg_temp_new_i64();
1167 TCGv_i64 t2 = tcg_temp_new_i64();
1168 TCGv_i64 t3 = tcg_temp_new_i64();
1169
1170 tcg_gen_ext_i32_i64(t1, arg1);
1171 tcg_gen_ext_i32_i64(t2, arg2);
1172 tcg_gen_ext_i32_i64(t3, arg3);
1173
1174 tcg_gen_mul_i64(t2, t2, t3);
1175 tcg_gen_sari_i64(t2, t2, up_shift - n);
1176
1177 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1178 }
1179
1180 static inline void
1181 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1182 TCGv arg3, uint32_t n)
1183 {
1184 TCGv_i64 r1 = tcg_temp_new_i64();
1185 TCGv t_n = tcg_constant_i32(n);
1186
1187 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1188 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
1189 tcg_gen_extr_i64_i32(rl, rh, r1);
1190 }
1191
1192 /* ret = r2 - (r1 * r3); */
1193 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1194 {
1195 TCGv_i64 t1 = tcg_temp_new_i64();
1196 TCGv_i64 t2 = tcg_temp_new_i64();
1197 TCGv_i64 t3 = tcg_temp_new_i64();
1198
1199 tcg_gen_ext_i32_i64(t1, r1);
1200 tcg_gen_ext_i32_i64(t2, r2);
1201 tcg_gen_ext_i32_i64(t3, r3);
1202
1203 tcg_gen_mul_i64(t1, t1, t3);
1204 tcg_gen_sub_i64(t1, t2, t1);
1205
1206 tcg_gen_extrl_i64_i32(ret, t1);
1207 /* calc V
1208 t2 > 0x7fffffff */
1209 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1210 /* result < -0x80000000 */
1211 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1212 tcg_gen_or_i64(t2, t2, t3);
1213 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
1214 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1215
1216 /* Calc SV bit */
1217 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1218 /* Calc AV/SAV bits */
1219 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1220 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1221 /* calc SAV */
1222 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1223 }
1224
1225 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1226 {
1227 TCGv temp = tcg_const_i32(con);
1228 gen_msub32_d(ret, r1, r2, temp);
1229 }
1230
1231 static inline void
1232 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1233 TCGv r3)
1234 {
1235 TCGv t1 = tcg_temp_new();
1236 TCGv t2 = tcg_temp_new();
1237 TCGv t3 = tcg_temp_new();
1238 TCGv t4 = tcg_temp_new();
1239
1240 tcg_gen_muls2_tl(t1, t2, r1, r3);
1241 /* only the sub can overflow */
1242 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1243 /* calc V bit */
1244 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1245 tcg_gen_xor_tl(t1, r2_high, t2);
1246 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1247 /* Calc SV bit */
1248 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1249 /* Calc AV/SAV bits */
1250 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1251 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1252 /* calc SAV */
1253 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1254 /* write back the result */
1255 tcg_gen_mov_tl(ret_low, t3);
1256 tcg_gen_mov_tl(ret_high, t4);
1257 }
1258
1259 static inline void
1260 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1261 int32_t con)
1262 {
1263 TCGv temp = tcg_const_i32(con);
1264 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1265 }
1266
1267 static inline void
1268 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1269 TCGv r3)
1270 {
1271 TCGv_i64 t1 = tcg_temp_new_i64();
1272 TCGv_i64 t2 = tcg_temp_new_i64();
1273 TCGv_i64 t3 = tcg_temp_new_i64();
1274
1275 tcg_gen_extu_i32_i64(t1, r1);
1276 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1277 tcg_gen_extu_i32_i64(t3, r3);
1278
1279 tcg_gen_mul_i64(t1, t1, t3);
1280 tcg_gen_sub_i64(t3, t2, t1);
1281 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1282 /* calc V bit, only the sub can overflow, if t1 > t2 */
1283 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1284 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1285 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1286 /* Calc SV bit */
1287 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1288 /* Calc AV/SAV bits */
1289 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1290 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1291 /* calc SAV */
1292 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1293 }
1294
1295 static inline void
1296 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1297 int32_t con)
1298 {
1299 TCGv temp = tcg_const_i32(con);
1300 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1301 }
1302
1303 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1304 {
1305 TCGv temp = tcg_const_i32(r2);
1306 gen_add_d(ret, r1, temp);
1307 }
1308
1309 /* calculate the carry bit too */
1310 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1311 {
1312 TCGv t0 = tcg_temp_new_i32();
1313 TCGv result = tcg_temp_new_i32();
1314
1315 tcg_gen_movi_tl(t0, 0);
1316 /* Addition and set C/V/SV bits */
1317 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1318 /* calc V bit */
1319 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1320 tcg_gen_xor_tl(t0, r1, r2);
1321 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1322 /* Calc SV bit */
1323 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1324 /* Calc AV/SAV bits */
1325 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1326 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1327 /* calc SAV */
1328 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1329 /* write back result */
1330 tcg_gen_mov_tl(ret, result);
1331 }
1332
1333 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1334 {
1335 TCGv temp = tcg_const_i32(con);
1336 gen_add_CC(ret, r1, temp);
1337 }
1338
1339 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1340 {
1341 TCGv carry = tcg_temp_new_i32();
1342 TCGv t0 = tcg_temp_new_i32();
1343 TCGv result = tcg_temp_new_i32();
1344
1345 tcg_gen_movi_tl(t0, 0);
1346 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1347 /* Addition, carry and set C/V/SV bits */
1348 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1349 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1350 /* calc V bit */
1351 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1352 tcg_gen_xor_tl(t0, r1, r2);
1353 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1354 /* Calc SV bit */
1355 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1356 /* Calc AV/SAV bits */
1357 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1358 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1359 /* calc SAV */
1360 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1361 /* write back result */
1362 tcg_gen_mov_tl(ret, result);
1363 }
1364
1365 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1366 {
1367 TCGv temp = tcg_const_i32(con);
1368 gen_addc_CC(ret, r1, temp);
1369 }
1370
1371 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1372 TCGv r4)
1373 {
1374 TCGv temp = tcg_temp_new();
1375 TCGv temp2 = tcg_temp_new();
1376 TCGv result = tcg_temp_new();
1377 TCGv mask = tcg_temp_new();
1378 TCGv t0 = tcg_const_i32(0);
1379
1380 /* create mask for sticky bits */
1381 tcg_gen_setcond_tl(cond, mask, r4, t0);
1382 tcg_gen_shli_tl(mask, mask, 31);
1383
1384 tcg_gen_add_tl(result, r1, r2);
1385 /* Calc PSW_V */
1386 tcg_gen_xor_tl(temp, result, r1);
1387 tcg_gen_xor_tl(temp2, r1, r2);
1388 tcg_gen_andc_tl(temp, temp, temp2);
1389 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1390 /* Set PSW_SV */
1391 tcg_gen_and_tl(temp, temp, mask);
1392 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1393 /* calc AV bit */
1394 tcg_gen_add_tl(temp, result, result);
1395 tcg_gen_xor_tl(temp, temp, result);
1396 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1397 /* calc SAV bit */
1398 tcg_gen_and_tl(temp, temp, mask);
1399 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1400 /* write back result */
1401 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1402 }
1403
1404 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1405 TCGv r3, TCGv r4)
1406 {
1407 TCGv temp = tcg_const_i32(r2);
1408 gen_cond_add(cond, r1, temp, r3, r4);
1409 }
1410
1411 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1412 {
1413 TCGv temp = tcg_temp_new_i32();
1414 TCGv result = tcg_temp_new_i32();
1415
1416 tcg_gen_sub_tl(result, r1, r2);
1417 /* calc V bit */
1418 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1419 tcg_gen_xor_tl(temp, r1, r2);
1420 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1421 /* calc SV bit */
1422 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1423 /* Calc AV bit */
1424 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1425 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1426 /* calc SAV bit */
1427 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1428 /* write back result */
1429 tcg_gen_mov_tl(ret, result);
1430 }
1431
1432 static inline void
1433 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1434 {
1435 TCGv temp = tcg_temp_new();
1436 TCGv_i64 t0 = tcg_temp_new_i64();
1437 TCGv_i64 t1 = tcg_temp_new_i64();
1438 TCGv_i64 result = tcg_temp_new_i64();
1439
1440 tcg_gen_sub_i64(result, r1, r2);
1441 /* calc v bit */
1442 tcg_gen_xor_i64(t1, result, r1);
1443 tcg_gen_xor_i64(t0, r1, r2);
1444 tcg_gen_and_i64(t1, t1, t0);
1445 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
1446 /* calc SV bit */
1447 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1448 /* calc AV/SAV bits */
1449 tcg_gen_extrh_i64_i32(temp, result);
1450 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1451 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1452 /* calc SAV */
1453 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1454 /* write back result */
1455 tcg_gen_mov_i64(ret, result);
1456 }
1457
1458 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1459 {
1460 TCGv result = tcg_temp_new();
1461 TCGv temp = tcg_temp_new();
1462
1463 tcg_gen_sub_tl(result, r1, r2);
1464 /* calc C bit */
1465 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1466 /* calc V bit */
1467 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1468 tcg_gen_xor_tl(temp, r1, r2);
1469 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1470 /* calc SV bit */
1471 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1472 /* Calc AV bit */
1473 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1474 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1475 /* calc SAV bit */
1476 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1477 /* write back result */
1478 tcg_gen_mov_tl(ret, result);
1479 }
1480
1481 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1482 {
1483 TCGv temp = tcg_temp_new();
1484 tcg_gen_not_tl(temp, r2);
1485 gen_addc_CC(ret, r1, temp);
1486 }
1487
1488 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1489 TCGv r4)
1490 {
1491 TCGv temp = tcg_temp_new();
1492 TCGv temp2 = tcg_temp_new();
1493 TCGv result = tcg_temp_new();
1494 TCGv mask = tcg_temp_new();
1495 TCGv t0 = tcg_const_i32(0);
1496
1497 /* create mask for sticky bits */
1498 tcg_gen_setcond_tl(cond, mask, r4, t0);
1499 tcg_gen_shli_tl(mask, mask, 31);
1500
1501 tcg_gen_sub_tl(result, r1, r2);
1502 /* Calc PSW_V */
1503 tcg_gen_xor_tl(temp, result, r1);
1504 tcg_gen_xor_tl(temp2, r1, r2);
1505 tcg_gen_and_tl(temp, temp, temp2);
1506 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1507 /* Set PSW_SV */
1508 tcg_gen_and_tl(temp, temp, mask);
1509 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1510 /* calc AV bit */
1511 tcg_gen_add_tl(temp, result, result);
1512 tcg_gen_xor_tl(temp, temp, result);
1513 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1514 /* calc SAV bit */
1515 tcg_gen_and_tl(temp, temp, mask);
1516 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1517 /* write back result */
1518 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1519 }
1520
1521 static inline void
1522 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1523 TCGv r3, uint32_t n, uint32_t mode)
1524 {
1525 TCGv t_n = tcg_constant_i32(n);
1526 TCGv temp = tcg_temp_new();
1527 TCGv temp2 = tcg_temp_new();
1528 TCGv_i64 temp64 = tcg_temp_new_i64();
1529 switch (mode) {
1530 case MODE_LL:
1531 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1532 break;
1533 case MODE_LU:
1534 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1535 break;
1536 case MODE_UL:
1537 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1538 break;
1539 case MODE_UU:
1540 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1541 break;
1542 }
1543 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1544 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1545 tcg_gen_sub_tl, tcg_gen_sub_tl);
1546 }
1547
1548 static inline void
1549 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1550 TCGv r3, uint32_t n, uint32_t mode)
1551 {
1552 TCGv t_n = tcg_constant_i32(n);
1553 TCGv temp = tcg_temp_new();
1554 TCGv temp2 = tcg_temp_new();
1555 TCGv temp3 = tcg_temp_new();
1556 TCGv_i64 temp64 = tcg_temp_new_i64();
1557
1558 switch (mode) {
1559 case MODE_LL:
1560 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1561 break;
1562 case MODE_LU:
1563 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1564 break;
1565 case MODE_UL:
1566 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1567 break;
1568 case MODE_UU:
1569 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1570 break;
1571 }
1572 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1573 gen_subs(ret_low, r1_low, temp);
1574 tcg_gen_mov_tl(temp, cpu_PSW_V);
1575 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1576 gen_subs(ret_high, r1_high, temp2);
1577 /* combine v bits */
1578 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1579 /* combine av bits */
1580 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1581 }
1582
1583 static inline void
1584 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1585 TCGv r3, uint32_t n, uint32_t mode)
1586 {
1587 TCGv t_n = tcg_constant_i32(n);
1588 TCGv_i64 temp64 = tcg_temp_new_i64();
1589 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1590 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1591 switch (mode) {
1592 case MODE_LL:
1593 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
1594 break;
1595 case MODE_LU:
1596 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
1597 break;
1598 case MODE_UL:
1599 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
1600 break;
1601 case MODE_UU:
1602 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
1603 break;
1604 }
1605 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1606 gen_sub64_d(temp64_3, temp64_2, temp64);
1607 /* write back result */
1608 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1609 }
1610
1611 static inline void
1612 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1613 TCGv r3, uint32_t n, uint32_t mode)
1614 {
1615 TCGv t_n = tcg_constant_i32(n);
1616 TCGv_i64 temp64 = tcg_temp_new_i64();
1617 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1618 switch (mode) {
1619 case MODE_LL:
1620 GEN_HELPER_LL(mulm_h, temp64, r2, r3, t_n);
1621 break;
1622 case MODE_LU:
1623 GEN_HELPER_LU(mulm_h, temp64, r2, r3, t_n);
1624 break;
1625 case MODE_UL:
1626 GEN_HELPER_UL(mulm_h, temp64, r2, r3, t_n);
1627 break;
1628 case MODE_UU:
1629 GEN_HELPER_UU(mulm_h, temp64, r2, r3, t_n);
1630 break;
1631 }
1632 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1633 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1634 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1635 }
1636
1637 static inline void
1638 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1639 uint32_t mode)
1640 {
1641 TCGv t_n = tcg_constant_i32(n);
1642 TCGv_i64 temp64 = tcg_temp_new_i64();
1643 switch (mode) {
1644 case MODE_LL:
1645 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1646 break;
1647 case MODE_LU:
1648 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1649 break;
1650 case MODE_UL:
1651 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1652 break;
1653 case MODE_UU:
1654 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1655 break;
1656 }
1657 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1658 }
1659
1660 static inline void
1661 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1662 {
1663 TCGv temp = tcg_temp_new();
1664 TCGv temp2 = tcg_temp_new();
1665
1666 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1667 tcg_gen_shli_tl(temp, r1, 16);
1668 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1669 }
1670
1671 static inline void
1672 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1673 uint32_t n, uint32_t mode)
1674 {
1675 TCGv t_n = tcg_constant_i32(n);
1676 TCGv_i64 temp64 = tcg_temp_new_i64();
1677 switch (mode) {
1678 case MODE_LL:
1679 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1680 break;
1681 case MODE_LU:
1682 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1683 break;
1684 case MODE_UL:
1685 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1686 break;
1687 case MODE_UU:
1688 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1689 break;
1690 }
1691 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1692 }
1693
1694 static inline void
1695 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1696 {
1697 TCGv temp = tcg_temp_new();
1698 TCGv temp2 = tcg_temp_new();
1699
1700 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1701 tcg_gen_shli_tl(temp, r1, 16);
1702 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1703 }
1704
1705 static inline void
1706 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1707 {
1708 TCGv temp = tcg_const_i32(n);
1709 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1710 }
1711
1712 static inline void
1713 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1714 {
1715 TCGv temp = tcg_const_i32(n);
1716 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1717 }
1718
1719 static inline void
1720 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1721 uint32_t up_shift)
1722 {
1723 TCGv temp3 = tcg_temp_new();
1724 TCGv_i64 t1 = tcg_temp_new_i64();
1725 TCGv_i64 t2 = tcg_temp_new_i64();
1726 TCGv_i64 t3 = tcg_temp_new_i64();
1727 TCGv_i64 t4 = tcg_temp_new_i64();
1728
1729 tcg_gen_ext_i32_i64(t2, arg2);
1730 tcg_gen_ext_i32_i64(t3, arg3);
1731
1732 tcg_gen_mul_i64(t2, t2, t3);
1733
1734 tcg_gen_ext_i32_i64(t1, arg1);
1735 /* if we shift part of the fraction out, we need to round up */
1736 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1737 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1738 tcg_gen_sari_i64(t2, t2, up_shift - n);
1739 tcg_gen_add_i64(t2, t2, t4);
1740
1741 tcg_gen_sub_i64(t3, t1, t2);
1742 tcg_gen_extrl_i64_i32(temp3, t3);
1743 /* calc v bit */
1744 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1745 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1746 tcg_gen_or_i64(t1, t1, t2);
1747 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1748 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1749 /* Calc SV bit */
1750 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1751 /* Calc AV/SAV bits */
1752 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1753 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1754 /* calc SAV */
1755 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1756 /* write back result */
1757 tcg_gen_mov_tl(ret, temp3);
1758 }
1759
1760 static inline void
1761 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1762 {
1763 TCGv temp = tcg_temp_new();
1764 TCGv temp2 = tcg_temp_new();
1765 if (n == 0) {
1766 tcg_gen_mul_tl(temp, arg2, arg3);
1767 } else { /* n is expected to be 1 */
1768 tcg_gen_mul_tl(temp, arg2, arg3);
1769 tcg_gen_shli_tl(temp, temp, 1);
1770 /* catch special case r1 = r2 = 0x8000 */
1771 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1772 tcg_gen_sub_tl(temp, temp, temp2);
1773 }
1774 gen_sub_d(ret, arg1, temp);
1775 }
1776
1777 static inline void
1778 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1779 {
1780 TCGv temp = tcg_temp_new();
1781 TCGv temp2 = tcg_temp_new();
1782 if (n == 0) {
1783 tcg_gen_mul_tl(temp, arg2, arg3);
1784 } else { /* n is expected to be 1 */
1785 tcg_gen_mul_tl(temp, arg2, arg3);
1786 tcg_gen_shli_tl(temp, temp, 1);
1787 /* catch special case r1 = r2 = 0x8000 */
1788 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1789 tcg_gen_sub_tl(temp, temp, temp2);
1790 }
1791 gen_subs(ret, arg1, temp);
1792 }
1793
1794 static inline void
1795 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1796 TCGv arg3, uint32_t n)
1797 {
1798 TCGv temp = tcg_temp_new();
1799 TCGv temp2 = tcg_temp_new();
1800 TCGv_i64 t1 = tcg_temp_new_i64();
1801 TCGv_i64 t2 = tcg_temp_new_i64();
1802 TCGv_i64 t3 = tcg_temp_new_i64();
1803
1804 if (n == 0) {
1805 tcg_gen_mul_tl(temp, arg2, arg3);
1806 } else { /* n is expected to be 1 */
1807 tcg_gen_mul_tl(temp, arg2, arg3);
1808 tcg_gen_shli_tl(temp, temp, 1);
1809 /* catch special case r1 = r2 = 0x8000 */
1810 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1811 tcg_gen_sub_tl(temp, temp, temp2);
1812 }
1813 tcg_gen_ext_i32_i64(t2, temp);
1814 tcg_gen_shli_i64(t2, t2, 16);
1815 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1816 gen_sub64_d(t3, t1, t2);
1817 /* write back result */
1818 tcg_gen_extr_i64_i32(rl, rh, t3);
1819 }
1820
1821 static inline void
1822 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1823 TCGv arg3, uint32_t n)
1824 {
1825 TCGv temp = tcg_temp_new();
1826 TCGv temp2 = tcg_temp_new();
1827 TCGv_i64 t1 = tcg_temp_new_i64();
1828 TCGv_i64 t2 = tcg_temp_new_i64();
1829
1830 if (n == 0) {
1831 tcg_gen_mul_tl(temp, arg2, arg3);
1832 } else { /* n is expected to be 1 */
1833 tcg_gen_mul_tl(temp, arg2, arg3);
1834 tcg_gen_shli_tl(temp, temp, 1);
1835 /* catch special case r1 = r2 = 0x8000 */
1836 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1837 tcg_gen_sub_tl(temp, temp, temp2);
1838 }
1839 tcg_gen_ext_i32_i64(t2, temp);
1840 tcg_gen_shli_i64(t2, t2, 16);
1841 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1842
1843 gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
1844 tcg_gen_extr_i64_i32(rl, rh, t1);
1845 }
1846
1847 static inline void
1848 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1849 TCGv arg3, uint32_t n)
1850 {
1851 TCGv_i64 t1 = tcg_temp_new_i64();
1852 TCGv_i64 t2 = tcg_temp_new_i64();
1853 TCGv_i64 t3 = tcg_temp_new_i64();
1854 TCGv_i64 t4 = tcg_temp_new_i64();
1855 TCGv temp, temp2;
1856
1857 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1858 tcg_gen_ext_i32_i64(t2, arg2);
1859 tcg_gen_ext_i32_i64(t3, arg3);
1860
1861 tcg_gen_mul_i64(t2, t2, t3);
1862 if (n != 0) {
1863 tcg_gen_shli_i64(t2, t2, 1);
1864 }
1865 tcg_gen_sub_i64(t4, t1, t2);
1866 /* calc v bit */
1867 tcg_gen_xor_i64(t3, t4, t1);
1868 tcg_gen_xor_i64(t2, t1, t2);
1869 tcg_gen_and_i64(t3, t3, t2);
1870 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1871 /* We produce an overflow on the host if the mul before was
1872 (0x80000000 * 0x80000000) << 1). If this is the
1873 case, we negate the ovf. */
1874 if (n == 1) {
1875 temp = tcg_temp_new();
1876 temp2 = tcg_temp_new();
1877 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1878 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1879 tcg_gen_and_tl(temp, temp, temp2);
1880 tcg_gen_shli_tl(temp, temp, 31);
1881 /* negate v bit, if special condition */
1882 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1883 }
1884 /* write back result */
1885 tcg_gen_extr_i64_i32(rl, rh, t4);
1886 /* Calc SV bit */
1887 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1888 /* Calc AV/SAV bits */
1889 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1890 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1891 /* calc SAV */
1892 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1893 }
1894
1895 static inline void
1896 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1897 uint32_t up_shift)
1898 {
1899 TCGv_i64 t1 = tcg_temp_new_i64();
1900 TCGv_i64 t2 = tcg_temp_new_i64();
1901 TCGv_i64 t3 = tcg_temp_new_i64();
1902 TCGv_i64 t4 = tcg_temp_new_i64();
1903
1904 tcg_gen_ext_i32_i64(t1, arg1);
1905 tcg_gen_ext_i32_i64(t2, arg2);
1906 tcg_gen_ext_i32_i64(t3, arg3);
1907
1908 tcg_gen_mul_i64(t2, t2, t3);
1909 /* if we shift part of the fraction out, we need to round up */
1910 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1911 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1912 tcg_gen_sari_i64(t3, t2, up_shift - n);
1913 tcg_gen_add_i64(t3, t3, t4);
1914
1915 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
1916 }
1917
1918 static inline void
1919 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1920 TCGv arg3, uint32_t n)
1921 {
1922 TCGv_i64 r1 = tcg_temp_new_i64();
1923 TCGv t_n = tcg_constant_i32(n);
1924
1925 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1926 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n);
1927 tcg_gen_extr_i64_i32(rl, rh, r1);
1928 }
1929
1930 static inline void
1931 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1932 TCGv r3, uint32_t n, uint32_t mode)
1933 {
1934 TCGv t_n = tcg_constant_i32(n);
1935 TCGv temp = tcg_temp_new();
1936 TCGv temp2 = tcg_temp_new();
1937 TCGv_i64 temp64 = tcg_temp_new_i64();
1938 switch (mode) {
1939 case MODE_LL:
1940 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1941 break;
1942 case MODE_LU:
1943 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1944 break;
1945 case MODE_UL:
1946 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1947 break;
1948 case MODE_UU:
1949 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1950 break;
1951 }
1952 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1953 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1954 tcg_gen_add_tl, tcg_gen_sub_tl);
1955 }
1956
1957 static inline void
1958 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1959 TCGv r3, uint32_t n, uint32_t mode)
1960 {
1961 TCGv t_n = tcg_constant_i32(n);
1962 TCGv_i64 temp64 = tcg_temp_new_i64();
1963 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1964 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1965 switch (mode) {
1966 case MODE_LL:
1967 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
1968 break;
1969 case MODE_LU:
1970 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
1971 break;
1972 case MODE_UL:
1973 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
1974 break;
1975 case MODE_UU:
1976 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
1977 break;
1978 }
1979 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
1980 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
1981 tcg_gen_ext32s_i64(temp64, temp64); /* low */
1982 tcg_gen_sub_i64(temp64, temp64_2, temp64);
1983 tcg_gen_shli_i64(temp64, temp64, 16);
1984
1985 gen_sub64_d(temp64_2, temp64_3, temp64);
1986 /* write back result */
1987 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
1988 }
1989
1990 static inline void
1991 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1992 {
1993 TCGv t_n = tcg_constant_i32(n);
1994 TCGv temp = tcg_temp_new();
1995 TCGv temp2 = tcg_temp_new();
1996 TCGv_i64 temp64 = tcg_temp_new_i64();
1997 switch (mode) {
1998 case MODE_LL:
1999 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2000 break;
2001 case MODE_LU:
2002 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2003 break;
2004 case MODE_UL:
2005 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2006 break;
2007 case MODE_UU:
2008 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2009 break;
2010 }
2011 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2012 tcg_gen_shli_tl(temp, r1, 16);
2013 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2014 }
2015
2016 static inline void
2017 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2018 TCGv r3, uint32_t n, uint32_t mode)
2019 {
2020 TCGv t_n = tcg_constant_i32(n);
2021 TCGv temp = tcg_temp_new();
2022 TCGv temp2 = tcg_temp_new();
2023 TCGv temp3 = tcg_temp_new();
2024 TCGv_i64 temp64 = tcg_temp_new_i64();
2025
2026 switch (mode) {
2027 case MODE_LL:
2028 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2029 break;
2030 case MODE_LU:
2031 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2032 break;
2033 case MODE_UL:
2034 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2035 break;
2036 case MODE_UU:
2037 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2038 break;
2039 }
2040 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2041 gen_adds(ret_low, r1_low, temp);
2042 tcg_gen_mov_tl(temp, cpu_PSW_V);
2043 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2044 gen_subs(ret_high, r1_high, temp2);
2045 /* combine v bits */
2046 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2047 /* combine av bits */
2048 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2049 }
2050
2051 static inline void
2052 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2053 TCGv r3, uint32_t n, uint32_t mode)
2054 {
2055 TCGv t_n = tcg_constant_i32(n);
2056 TCGv_i64 temp64 = tcg_temp_new_i64();
2057 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2058
2059 switch (mode) {
2060 case MODE_LL:
2061 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2062 break;
2063 case MODE_LU:
2064 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2065 break;
2066 case MODE_UL:
2067 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2068 break;
2069 case MODE_UU:
2070 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2071 break;
2072 }
2073 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2074 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2075 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2076 tcg_gen_shli_i64(temp64, temp64, 16);
2077 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2078
2079 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2080 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2081 }
2082
2083 static inline void
2084 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2085 {
2086 TCGv t_n = tcg_constant_i32(n);
2087 TCGv temp = tcg_temp_new();
2088 TCGv temp2 = tcg_temp_new();
2089 TCGv_i64 temp64 = tcg_temp_new_i64();
2090 switch (mode) {
2091 case MODE_LL:
2092 GEN_HELPER_LL(mul_h, temp64, r2, r3, t_n);
2093 break;
2094 case MODE_LU:
2095 GEN_HELPER_LU(mul_h, temp64, r2, r3, t_n);
2096 break;
2097 case MODE_UL:
2098 GEN_HELPER_UL(mul_h, temp64, r2, r3, t_n);
2099 break;
2100 case MODE_UU:
2101 GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n);
2102 break;
2103 }
2104 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2105 tcg_gen_shli_tl(temp, r1, 16);
2106 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2107 }
2108
2109 static inline void gen_abs(TCGv ret, TCGv r1)
2110 {
2111 tcg_gen_abs_tl(ret, r1);
2112 /* overflow can only happen, if r1 = 0x80000000 */
2113 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2114 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2115 /* calc SV bit */
2116 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2117 /* Calc AV bit */
2118 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2119 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2120 /* calc SAV bit */
2121 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2122 }
2123
2124 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2125 {
2126 TCGv temp = tcg_temp_new_i32();
2127 TCGv result = tcg_temp_new_i32();
2128
2129 tcg_gen_sub_tl(result, r1, r2);
2130 tcg_gen_sub_tl(temp, r2, r1);
2131 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2132
2133 /* calc V bit */
2134 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2135 tcg_gen_xor_tl(temp, result, r2);
2136 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2137 tcg_gen_xor_tl(temp, r1, r2);
2138 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2139 /* calc SV bit */
2140 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2141 /* Calc AV bit */
2142 tcg_gen_add_tl(cpu_PSW_AV, result, result);
2143 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2144 /* calc SAV bit */
2145 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2146 /* write back result */
2147 tcg_gen_mov_tl(ret, result);
2148 }
2149
2150 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2151 {
2152 TCGv temp = tcg_const_i32(con);
2153 gen_absdif(ret, r1, temp);
2154 }
2155
2156 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2157 {
2158 TCGv temp = tcg_const_i32(con);
2159 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2160 }
2161
2162 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2163 {
2164 TCGv high = tcg_temp_new();
2165 TCGv low = tcg_temp_new();
2166
2167 tcg_gen_muls2_tl(low, high, r1, r2);
2168 tcg_gen_mov_tl(ret, low);
2169 /* calc V bit */
2170 tcg_gen_sari_tl(low, low, 31);
2171 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2172 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2173 /* calc SV bit */
2174 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2175 /* Calc AV bit */
2176 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2177 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2178 /* calc SAV bit */
2179 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2180 }
2181
2182 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2183 {
2184 TCGv temp = tcg_const_i32(con);
2185 gen_mul_i32s(ret, r1, temp);
2186 }
2187
2188 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2189 {
2190 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2191 /* clear V bit */
2192 tcg_gen_movi_tl(cpu_PSW_V, 0);
2193 /* calc SV bit */
2194 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2195 /* Calc AV bit */
2196 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2197 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2198 /* calc SAV bit */
2199 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2200 }
2201
2202 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2203 int32_t con)
2204 {
2205 TCGv temp = tcg_const_i32(con);
2206 gen_mul_i64s(ret_low, ret_high, r1, temp);
2207 }
2208
2209 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2210 {
2211 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2212 /* clear V bit */
2213 tcg_gen_movi_tl(cpu_PSW_V, 0);
2214 /* calc SV bit */
2215 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2216 /* Calc AV bit */
2217 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2218 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2219 /* calc SAV bit */
2220 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2221 }
2222
2223 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2224 int32_t con)
2225 {
2226 TCGv temp = tcg_const_i32(con);
2227 gen_mul_i64u(ret_low, ret_high, r1, temp);
2228 }
2229
2230 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2231 {
2232 TCGv temp = tcg_const_i32(con);
2233 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2234 }
2235
2236 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2237 {
2238 TCGv temp = tcg_const_i32(con);
2239 gen_helper_mul_suov(ret, cpu_env, r1, temp);
2240 }
2241 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2242 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2243 {
2244 TCGv temp = tcg_const_i32(con);
2245 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2246 }
2247
2248 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2249 {
2250 TCGv temp = tcg_const_i32(con);
2251 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2252 }
2253
2254 static void
2255 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2256 {
2257 TCGv_i64 temp_64 = tcg_temp_new_i64();
2258 TCGv_i64 temp2_64 = tcg_temp_new_i64();
2259
2260 if (n == 0) {
2261 if (up_shift == 32) {
2262 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2263 } else if (up_shift == 16) {
2264 tcg_gen_ext_i32_i64(temp_64, arg1);
2265 tcg_gen_ext_i32_i64(temp2_64, arg2);
2266
2267 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2268 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2269 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2270 } else {
2271 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2272 }
2273 /* reset v bit */
2274 tcg_gen_movi_tl(cpu_PSW_V, 0);
2275 } else { /* n is expected to be 1 */
2276 tcg_gen_ext_i32_i64(temp_64, arg1);
2277 tcg_gen_ext_i32_i64(temp2_64, arg2);
2278
2279 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2280
2281 if (up_shift == 0) {
2282 tcg_gen_shli_i64(temp_64, temp_64, 1);
2283 } else {
2284 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2285 }
2286 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2287 /* overflow only occurs if r1 = r2 = 0x8000 */
2288 if (up_shift == 0) {/* result is 64 bit */
2289 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2290 0x80000000);
2291 } else { /* result is 32 bit */
2292 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2293 0x80000000);
2294 }
2295 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2296 /* calc sv overflow bit */
2297 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2298 }
2299 /* calc av overflow bit */
2300 if (up_shift == 0) {
2301 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2302 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2303 } else {
2304 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2305 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2306 }
2307 /* calc sav overflow bit */
2308 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2309 }
2310
2311 static void
2312 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2313 {
2314 TCGv temp = tcg_temp_new();
2315 if (n == 0) {
2316 tcg_gen_mul_tl(ret, arg1, arg2);
2317 } else { /* n is expected to be 1 */
2318 tcg_gen_mul_tl(ret, arg1, arg2);
2319 tcg_gen_shli_tl(ret, ret, 1);
2320 /* catch special case r1 = r2 = 0x8000 */
2321 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2322 tcg_gen_sub_tl(ret, ret, temp);
2323 }
2324 /* reset v bit */
2325 tcg_gen_movi_tl(cpu_PSW_V, 0);
2326 /* calc av overflow bit */
2327 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2328 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2329 /* calc sav overflow bit */
2330 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2331 }
2332
2333 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2334 {
2335 TCGv temp = tcg_temp_new();
2336 if (n == 0) {
2337 tcg_gen_mul_tl(ret, arg1, arg2);
2338 tcg_gen_addi_tl(ret, ret, 0x8000);
2339 } else {
2340 tcg_gen_mul_tl(ret, arg1, arg2);
2341 tcg_gen_shli_tl(ret, ret, 1);
2342 tcg_gen_addi_tl(ret, ret, 0x8000);
2343 /* catch special case r1 = r2 = 0x8000 */
2344 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2345 tcg_gen_muli_tl(temp, temp, 0x8001);
2346 tcg_gen_sub_tl(ret, ret, temp);
2347 }
2348 /* reset v bit */
2349 tcg_gen_movi_tl(cpu_PSW_V, 0);
2350 /* calc av overflow bit */
2351 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2352 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2353 /* calc sav overflow bit */
2354 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2355 /* cut halfword off */
2356 tcg_gen_andi_tl(ret, ret, 0xffff0000);
2357 }
2358
2359 static inline void
2360 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2361 TCGv r3)
2362 {
2363 TCGv_i64 temp64 = tcg_temp_new_i64();
2364 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2365 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2366 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2367 }
2368
2369 static inline void
2370 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2371 int32_t con)
2372 {
2373 TCGv temp = tcg_const_i32(con);
2374 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2375 }
2376
2377 static inline void
2378 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2379 TCGv r3)
2380 {
2381 TCGv_i64 temp64 = tcg_temp_new_i64();
2382 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2383 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2384 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2385 }
2386
2387 static inline void
2388 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2389 int32_t con)
2390 {
2391 TCGv temp = tcg_const_i32(con);
2392 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2393 }
2394
2395 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2396 {
2397 TCGv temp = tcg_const_i32(con);
2398 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2399 }
2400
2401 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2402 {
2403 TCGv temp = tcg_const_i32(con);
2404 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2405 }
2406
2407 static inline void
2408 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2409 TCGv r3)
2410 {
2411 TCGv_i64 temp64 = tcg_temp_new_i64();
2412 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2413 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2414 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2415 }
2416
2417 static inline void
2418 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2419 int32_t con)
2420 {
2421 TCGv temp = tcg_const_i32(con);
2422 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2423 }
2424
2425 static inline void
2426 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2427 TCGv r3)
2428 {
2429 TCGv_i64 temp64 = tcg_temp_new_i64();
2430 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2431 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2432 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2433 }
2434
2435 static inline void
2436 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2437 int32_t con)
2438 {
2439 TCGv temp = tcg_const_i32(con);
2440 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2441 }
2442
2443 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2444 {
2445 TCGv sat_neg = tcg_const_i32(low);
2446 TCGv temp = tcg_const_i32(up);
2447
2448 /* sat_neg = (arg < low ) ? low : arg; */
2449 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
2450
2451 /* ret = (sat_neg > up ) ? up : sat_neg; */
2452 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
2453 }
2454
2455 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2456 {
2457 TCGv temp = tcg_const_i32(up);
2458 /* sat_neg = (arg > up ) ? up : arg; */
2459 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
2460 }
2461
2462 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2463 {
2464 if (shift_count == -32) {
2465 tcg_gen_movi_tl(ret, 0);
2466 } else if (shift_count >= 0) {
2467 tcg_gen_shli_tl(ret, r1, shift_count);
2468 } else {
2469 tcg_gen_shri_tl(ret, r1, -shift_count);
2470 }
2471 }
2472
2473 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2474 {
2475 TCGv temp_low, temp_high;
2476
2477 if (shiftcount == -16) {
2478 tcg_gen_movi_tl(ret, 0);
2479 } else {
2480 temp_high = tcg_temp_new();
2481 temp_low = tcg_temp_new();
2482
2483 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2484 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2485 gen_shi(temp_low, temp_low, shiftcount);
2486 gen_shi(ret, temp_high, shiftcount);
2487 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2488 }
2489 }
2490
2491 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2492 {
2493 uint32_t msk, msk_start;
2494 TCGv temp = tcg_temp_new();
2495 TCGv temp2 = tcg_temp_new();
2496
2497 if (shift_count == 0) {
2498 /* Clear PSW.C and PSW.V */
2499 tcg_gen_movi_tl(cpu_PSW_C, 0);
2500 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2501 tcg_gen_mov_tl(ret, r1);
2502 } else if (shift_count == -32) {
2503 /* set PSW.C */
2504 tcg_gen_mov_tl(cpu_PSW_C, r1);
2505 /* fill ret completely with sign bit */
2506 tcg_gen_sari_tl(ret, r1, 31);
2507 /* clear PSW.V */
2508 tcg_gen_movi_tl(cpu_PSW_V, 0);
2509 } else if (shift_count > 0) {
2510 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
2511 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
2512
2513 /* calc carry */
2514 msk_start = 32 - shift_count;
2515 msk = ((1 << shift_count) - 1) << msk_start;
2516 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2517 /* calc v/sv bits */
2518 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2519 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2520 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2521 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2522 /* calc sv */
2523 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2524 /* do shift */
2525 tcg_gen_shli_tl(ret, r1, shift_count);
2526 } else {
2527 /* clear PSW.V */
2528 tcg_gen_movi_tl(cpu_PSW_V, 0);
2529 /* calc carry */
2530 msk = (1 << -shift_count) - 1;
2531 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2532 /* do shift */
2533 tcg_gen_sari_tl(ret, r1, -shift_count);
2534 }
2535 /* calc av overflow bit */
2536 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2537 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2538 /* calc sav overflow bit */
2539 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2540 }
2541
2542 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2543 {
2544 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2545 }
2546
2547 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2548 {
2549 TCGv temp = tcg_const_i32(con);
2550 gen_shas(ret, r1, temp);
2551 }
2552
2553 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2554 {
2555 TCGv low, high;
2556
2557 if (shift_count == 0) {
2558 tcg_gen_mov_tl(ret, r1);
2559 } else if (shift_count > 0) {
2560 low = tcg_temp_new();
2561 high = tcg_temp_new();
2562
2563 tcg_gen_andi_tl(high, r1, 0xffff0000);
2564 tcg_gen_shli_tl(low, r1, shift_count);
2565 tcg_gen_shli_tl(ret, high, shift_count);
2566 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2567 } else {
2568 low = tcg_temp_new();
2569 high = tcg_temp_new();
2570
2571 tcg_gen_ext16s_tl(low, r1);
2572 tcg_gen_sari_tl(low, low, -shift_count);
2573 tcg_gen_sari_tl(ret, r1, -shift_count);
2574 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2575 }
2576 }
2577
2578 /* ret = {ret[30:0], (r1 cond r2)}; */
2579 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2580 {
2581 TCGv temp = tcg_temp_new();
2582 TCGv temp2 = tcg_temp_new();
2583
2584 tcg_gen_shli_tl(temp, ret, 1);
2585 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2586 tcg_gen_or_tl(ret, temp, temp2);
2587 }
2588
2589 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2590 {
2591 TCGv temp = tcg_const_i32(con);
2592 gen_sh_cond(cond, ret, r1, temp);
2593 }
2594
2595 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2596 {
2597 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2598 }
2599
2600 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2601 {
2602 TCGv temp = tcg_const_i32(con);
2603 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2604 }
2605
2606 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2607 {
2608 TCGv temp = tcg_const_i32(con);
2609 gen_helper_add_suov(ret, cpu_env, r1, temp);
2610 }
2611
2612 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2613 {
2614 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2615 }
2616
2617 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2618 {
2619 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2620 }
2621
2622 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
2623 int pos1, int pos2,
2624 void(*op1)(TCGv, TCGv, TCGv),
2625 void(*op2)(TCGv, TCGv, TCGv))
2626 {
2627 TCGv temp1, temp2;
2628
2629 temp1 = tcg_temp_new();
2630 temp2 = tcg_temp_new();
2631
2632 tcg_gen_shri_tl(temp2, r2, pos2);
2633 tcg_gen_shri_tl(temp1, r1, pos1);
2634
2635 (*op1)(temp1, temp1, temp2);
2636 (*op2)(temp1 , ret, temp1);
2637
2638 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
2639 }
2640
2641 /* ret = r1[pos1] op1 r2[pos2]; */
2642 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
2643 int pos1, int pos2,
2644 void(*op1)(TCGv, TCGv, TCGv))
2645 {
2646 TCGv temp1, temp2;
2647
2648 temp1 = tcg_temp_new();
2649 temp2 = tcg_temp_new();
2650
2651 tcg_gen_shri_tl(temp2, r2, pos2);
2652 tcg_gen_shri_tl(temp1, r1, pos1);
2653
2654 (*op1)(ret, temp1, temp2);
2655
2656 tcg_gen_andi_tl(ret, ret, 0x1);
2657 }
2658
2659 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
2660 void(*op)(TCGv, TCGv, TCGv))
2661 {
2662 TCGv temp = tcg_temp_new();
2663 TCGv temp2 = tcg_temp_new();
2664 /* temp = (arg1 cond arg2 )*/
2665 tcg_gen_setcond_tl(cond, temp, r1, r2);
2666 /* temp2 = ret[0]*/
2667 tcg_gen_andi_tl(temp2, ret, 0x1);
2668 /* temp = temp insn temp2 */
2669 (*op)(temp, temp, temp2);
2670 /* ret = {ret[31:1], temp} */
2671 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
2672 }
2673
2674 static inline void
2675 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
2676 void(*op)(TCGv, TCGv, TCGv))
2677 {
2678 TCGv temp = tcg_const_i32(con);
2679 gen_accumulating_cond(cond, ret, r1, temp, op);
2680 }
2681
2682 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
2683 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
2684 {
2685 tcg_gen_setcond_tl(cond, ret, r1, r2);
2686 tcg_gen_neg_tl(ret, ret);
2687 }
2688
2689 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
2690 {
2691 TCGv b0 = tcg_temp_new();
2692 TCGv b1 = tcg_temp_new();
2693 TCGv b2 = tcg_temp_new();
2694 TCGv b3 = tcg_temp_new();
2695
2696 /* byte 0 */
2697 tcg_gen_andi_tl(b0, r1, 0xff);
2698 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
2699
2700 /* byte 1 */
2701 tcg_gen_andi_tl(b1, r1, 0xff00);
2702 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
2703
2704 /* byte 2 */
2705 tcg_gen_andi_tl(b2, r1, 0xff0000);
2706 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
2707
2708 /* byte 3 */
2709 tcg_gen_andi_tl(b3, r1, 0xff000000);
2710 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
2711
2712 /* combine them */
2713 tcg_gen_or_tl(ret, b0, b1);
2714 tcg_gen_or_tl(ret, ret, b2);
2715 tcg_gen_or_tl(ret, ret, b3);
2716 }
2717
2718 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
2719 {
2720 TCGv h0 = tcg_temp_new();
2721 TCGv h1 = tcg_temp_new();
2722
2723 /* halfword 0 */
2724 tcg_gen_andi_tl(h0, r1, 0xffff);
2725 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
2726
2727 /* halfword 1 */
2728 tcg_gen_andi_tl(h1, r1, 0xffff0000);
2729 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
2730
2731 /* combine them */
2732 tcg_gen_or_tl(ret, h0, h1);
2733 }
2734
2735 /* mask = ((1 << width) -1) << pos;
2736 ret = (r1 & ~mask) | (r2 << pos) & mask); */
2737 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
2738 {
2739 TCGv mask = tcg_temp_new();
2740 TCGv temp = tcg_temp_new();
2741 TCGv temp2 = tcg_temp_new();
2742
2743 tcg_gen_movi_tl(mask, 1);
2744 tcg_gen_shl_tl(mask, mask, width);
2745 tcg_gen_subi_tl(mask, mask, 1);
2746 tcg_gen_shl_tl(mask, mask, pos);
2747
2748 tcg_gen_shl_tl(temp, r2, pos);
2749 tcg_gen_and_tl(temp, temp, mask);
2750 tcg_gen_andc_tl(temp2, r1, mask);
2751 tcg_gen_or_tl(ret, temp, temp2);
2752 }
2753
2754 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
2755 {
2756 TCGv_i64 temp = tcg_temp_new_i64();
2757
2758 gen_helper_bsplit(temp, r1);
2759 tcg_gen_extr_i64_i32(rl, rh, temp);
2760 }
2761
2762 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
2763 {
2764 TCGv_i64 temp = tcg_temp_new_i64();
2765
2766 gen_helper_unpack(temp, r1);
2767 tcg_gen_extr_i64_i32(rl, rh, temp);
2768 }
2769
2770 static inline void
2771 gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2772 {
2773 TCGv_i64 ret = tcg_temp_new_i64();
2774
2775 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
2776 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
2777 } else {
2778 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
2779 }
2780 tcg_gen_extr_i64_i32(rl, rh, ret);
2781 }
2782
2783 static inline void
2784 gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
2785 {
2786 TCGv_i64 ret = tcg_temp_new_i64();
2787
2788 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
2789 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
2790 } else {
2791 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
2792 }
2793 tcg_gen_extr_i64_i32(rl, rh, ret);
2794 }
2795
2796 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
2797 {
2798 TCGv temp = tcg_temp_new();
2799 /* calc AV bit */
2800 tcg_gen_add_tl(temp, arg_low, arg_low);
2801 tcg_gen_xor_tl(temp, temp, arg_low);
2802 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
2803 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
2804 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2805 /* calc SAV bit */
2806 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2807 tcg_gen_movi_tl(cpu_PSW_V, 0);
2808 }
2809
2810 static void gen_calc_usb_mulr_h(TCGv arg)
2811 {
2812 TCGv temp = tcg_temp_new();
2813 /* calc AV bit */
2814 tcg_gen_add_tl(temp, arg, arg);
2815 tcg_gen_xor_tl(temp, temp, arg);
2816 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
2817 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
2818 /* calc SAV bit */
2819 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2820 /* clear V bit */
2821 tcg_gen_movi_tl(cpu_PSW_V, 0);
2822 }
2823
2824 /* helpers for generating program flow micro-ops */
2825
2826 static inline void gen_save_pc(target_ulong pc)
2827 {
2828 tcg_gen_movi_tl(cpu_PC, pc);
2829 }
2830
2831 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2832 {
2833 if (translator_use_goto_tb(&ctx->base, dest)) {
2834 tcg_gen_goto_tb(n);
2835 gen_save_pc(dest);
2836 tcg_gen_exit_tb(ctx->base.tb, n);
2837 } else {
2838 gen_save_pc(dest);
2839 tcg_gen_lookup_and_goto_ptr();
2840 }
2841 }
2842
2843 static void generate_trap(DisasContext *ctx, int class, int tin)
2844 {
2845 TCGv_i32 classtemp = tcg_const_i32(class);
2846 TCGv_i32 tintemp = tcg_const_i32(tin);
2847
2848 gen_save_pc(ctx->base.pc_next);
2849 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
2850 ctx->base.is_jmp = DISAS_NORETURN;
2851 }
2852
2853 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
2854 TCGv r2, int16_t address)
2855 {
2856 TCGLabel *jumpLabel = gen_new_label();
2857 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
2858
2859 gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
2860
2861 gen_set_label(jumpLabel);
2862 gen_goto_tb(ctx, 0, ctx->base.pc_next + address * 2);
2863 }
2864
2865 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
2866 int r2, int16_t address)
2867 {
2868 TCGv temp = tcg_const_i32(r2);
2869 gen_branch_cond(ctx, cond, r1, temp, address);
2870 }
2871
2872 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
2873 {
2874 TCGLabel *l1 = gen_new_label();
2875
2876 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
2877 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
2878 gen_goto_tb(ctx, 1, ctx->base.pc_next + offset);
2879 gen_set_label(l1);
2880 gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
2881 }
2882
2883 static void gen_fcall_save_ctx(DisasContext *ctx)
2884 {
2885 TCGv temp = tcg_temp_new();
2886
2887 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
2888 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
2889 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
2890 tcg_gen_mov_tl(cpu_gpr_a[10], temp);
2891 }
2892
2893 static void gen_fret(DisasContext *ctx)
2894 {
2895 TCGv temp = tcg_temp_new();
2896
2897 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
2898 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
2899 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
2900 tcg_gen_mov_tl(cpu_PC, temp);
2901 tcg_gen_exit_tb(NULL, 0);
2902 ctx->base.is_jmp = DISAS_NORETURN;
2903 }
2904
2905 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
2906 int r2 , int32_t constant , int32_t offset)
2907 {
2908 TCGv temp, temp2;
2909 int n;
2910
2911 switch (opc) {
2912 /* SB-format jumps */
2913 case OPC1_16_SB_J:
2914 case OPC1_32_B_J:
2915 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
2916 break;
2917 case OPC1_32_B_CALL:
2918 case OPC1_16_SB_CALL:
2919 gen_helper_1arg(call, ctx->pc_succ_insn);
2920 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
2921 break;
2922 case OPC1_16_SB_JZ:
2923 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
2924 break;
2925 case OPC1_16_SB_JNZ:
2926 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
2927 break;
2928 /* SBC-format jumps */
2929 case OPC1_16_SBC_JEQ:
2930 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
2931 break;
2932 case OPC1_16_SBC_JEQ2:
2933 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant,
2934 offset + 16);
2935 break;
2936 case OPC1_16_SBC_JNE:
2937 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
2938 break;
2939 case OPC1_16_SBC_JNE2:
2940 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15],
2941 constant, offset + 16);
2942 break;
2943 /* SBRN-format jumps */
2944 case OPC1_16_SBRN_JZ_T:
2945 temp = tcg_temp_new();
2946 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2947 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
2948 break;
2949 case OPC1_16_SBRN_JNZ_T:
2950 temp = tcg_temp_new();
2951 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
2952 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
2953 break;
2954 /* SBR-format jumps */
2955 case OPC1_16_SBR_JEQ:
2956 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2957 offset);
2958 break;
2959 case OPC1_16_SBR_JEQ2:
2960 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
2961 offset + 16);
2962 break;
2963 case OPC1_16_SBR_JNE:
2964 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2965 offset);
2966 break;
2967 case OPC1_16_SBR_JNE2:
2968 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
2969 offset + 16);
2970 break;
2971 case OPC1_16_SBR_JNZ:
2972 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
2973 break;
2974 case OPC1_16_SBR_JNZ_A:
2975 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
2976 break;
2977 case OPC1_16_SBR_JGEZ:
2978 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
2979 break;
2980 case OPC1_16_SBR_JGTZ:
2981 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
2982 break;
2983 case OPC1_16_SBR_JLEZ:
2984 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
2985 break;
2986 case OPC1_16_SBR_JLTZ:
2987 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
2988 break;
2989 case OPC1_16_SBR_JZ:
2990 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
2991 break;
2992 case OPC1_16_SBR_JZ_A:
2993 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
2994 break;
2995 case OPC1_16_SBR_LOOP:
2996 gen_loop(ctx, r1, offset * 2 - 32);
2997 break;
2998 /* SR-format jumps */
2999 case OPC1_16_SR_JI:
3000 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
3001 tcg_gen_exit_tb(NULL, 0);
3002 break;
3003 case OPC2_32_SYS_RET:
3004 case OPC2_16_SR_RET:
3005 gen_helper_ret(cpu_env);
3006 tcg_gen_exit_tb(NULL, 0);
3007 break;
3008 /* B-format */
3009 case OPC1_32_B_CALLA:
3010 gen_helper_1arg(call, ctx->pc_succ_insn);
3011 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3012 break;
3013 case OPC1_32_B_FCALL:
3014 gen_fcall_save_ctx(ctx);
3015 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3016 break;
3017 case OPC1_32_B_FCALLA:
3018 gen_fcall_save_ctx(ctx);
3019 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3020 break;
3021 case OPC1_32_B_JLA:
3022 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
3023 /* fall through */
3024 case OPC1_32_B_JA:
3025 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3026 break;
3027 case OPC1_32_B_JL:
3028 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
3029 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3030 break;
3031 /* BOL format */
3032 case OPCM_32_BRC_EQ_NEQ:
3033 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3034 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3035 } else {
3036 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3037 }
3038 break;
3039 case OPCM_32_BRC_GE:
3040 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3041 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3042 } else {
3043 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3044 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3045 offset);
3046 }
3047 break;
3048 case OPCM_32_BRC_JLT:
3049 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3050 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3051 } else {
3052 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3053 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3054 offset);
3055 }
3056 break;
3057 case OPCM_32_BRC_JNE:
3058 temp = tcg_temp_new();
3059 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3060 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3061 /* subi is unconditional */
3062 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3063 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3064 } else {
3065 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3066 /* addi is unconditional */
3067 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3068 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3069 }
3070 break;
3071 /* BRN format */
3072 case OPCM_32_BRN_JTT:
3073 n = MASK_OP_BRN_N(ctx->opcode);
3074
3075 temp = tcg_temp_new();
3076 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3077
3078 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3079 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3080 } else {
3081 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3082 }
3083 break;
3084 /* BRR Format */
3085 case OPCM_32_BRR_EQ_NEQ:
3086 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3087 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3088 offset);
3089 } else {
3090 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3091 offset);
3092 }
3093 break;
3094 case OPCM_32_BRR_ADDR_EQ_NEQ:
3095 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3096 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3097 offset);
3098 } else {
3099 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3100 offset);
3101 }
3102 break;
3103 case OPCM_32_BRR_GE:
3104 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3105 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3106 offset);
3107 } else {
3108 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3109 offset);
3110 }
3111 break;
3112 case OPCM_32_BRR_JLT:
3113 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3114 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3115 offset);
3116 } else {
3117 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3118 offset);
3119 }
3120 break;
3121 case OPCM_32_BRR_LOOP:
3122 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3123 gen_loop(ctx, r2, offset * 2);
3124 } else {
3125 /* OPC2_32_BRR_LOOPU */
3126 gen_goto_tb(ctx, 0, ctx->base.pc_next + offset * 2);
3127 }
3128 break;
3129 case OPCM_32_BRR_JNE:
3130 temp = tcg_temp_new();
3131 temp2 = tcg_temp_new();
3132 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3133 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3134 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3135 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3136 /* subi is unconditional */
3137 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3138 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3139 } else {
3140 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3141 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3142 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3143 /* addi is unconditional */
3144 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3145 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3146 }
3147 break;
3148 case OPCM_32_BRR_JNZ:
3149 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3150 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3151 } else {
3152 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3153 }
3154 break;
3155 default:
3156 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3157 }
3158 ctx->base.is_jmp = DISAS_NORETURN;
3159 }
3160
3161
3162 /*
3163 * Functions for decoding instructions
3164 */
3165
3166 static void decode_src_opc(DisasContext *ctx, int op1)
3167 {
3168 int r1;
3169 int32_t const4;
3170 TCGv temp, temp2;
3171
3172 r1 = MASK_OP_SRC_S1D(ctx->opcode);
3173 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3174
3175 switch (op1) {
3176 case OPC1_16_SRC_ADD:
3177 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3178 break;
3179 case OPC1_16_SRC_ADD_A15:
3180 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3181 break;
3182 case OPC1_16_SRC_ADD_15A:
3183 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3184 break;
3185 case OPC1_16_SRC_ADD_A:
3186 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3187 break;
3188 case OPC1_16_SRC_CADD:
3189 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3190 cpu_gpr_d[15]);
3191 break;
3192 case OPC1_16_SRC_CADDN:
3193 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3194 cpu_gpr_d[15]);
3195 break;
3196 case OPC1_16_SRC_CMOV:
3197 temp = tcg_const_tl(0);
3198 temp2 = tcg_const_tl(const4);
3199 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3200 temp2, cpu_gpr_d[r1]);
3201 break;
3202 case OPC1_16_SRC_CMOVN:
3203 temp = tcg_const_tl(0);
3204 temp2 = tcg_const_tl(const4);
3205 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3206 temp2, cpu_gpr_d[r1]);
3207 break;
3208 case OPC1_16_SRC_EQ:
3209 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3210 const4);
3211 break;
3212 case OPC1_16_SRC_LT:
3213 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3214 const4);
3215 break;
3216 case OPC1_16_SRC_MOV:
3217 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3218 break;
3219 case OPC1_16_SRC_MOV_A:
3220 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3221 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3222 break;
3223 case OPC1_16_SRC_MOV_E:
3224 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3225 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3226 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3227 } else {
3228 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3229 }
3230 break;
3231 case OPC1_16_SRC_SH:
3232 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3233 break;
3234 case OPC1_16_SRC_SHA:
3235 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3236 break;
3237 default:
3238 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3239 }
3240 }
3241
3242 static void decode_srr_opc(DisasContext *ctx, int op1)
3243 {
3244 int r1, r2;
3245 TCGv temp;
3246
3247 r1 = MASK_OP_SRR_S1D(ctx->opcode);
3248 r2 = MASK_OP_SRR_S2(ctx->opcode);
3249
3250 switch (op1) {
3251 case OPC1_16_SRR_ADD:
3252 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3253 break;
3254 case OPC1_16_SRR_ADD_A15:
3255 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3256 break;
3257 case OPC1_16_SRR_ADD_15A:
3258 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3259 break;
3260 case OPC1_16_SRR_ADD_A:
3261 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3262 break;
3263 case OPC1_16_SRR_ADDS:
3264 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3265 break;
3266 case OPC1_16_SRR_AND:
3267 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3268 break;
3269 case OPC1_16_SRR_CMOV:
3270 temp = tcg_const_tl(0);
3271 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3272 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3273 break;
3274 case OPC1_16_SRR_CMOVN:
3275 temp = tcg_const_tl(0);
3276 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3277 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3278 break;
3279 case OPC1_16_SRR_EQ:
3280 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3281 cpu_gpr_d[r2]);
3282 break;
3283 case OPC1_16_SRR_LT:
3284 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3285 cpu_gpr_d[r2]);
3286 break;
3287 case OPC1_16_SRR_MOV:
3288 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3289 break;
3290 case OPC1_16_SRR_MOV_A:
3291 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3292 break;
3293 case OPC1_16_SRR_MOV_AA:
3294 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3295 break;
3296 case OPC1_16_SRR_MOV_D:
3297 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3298 break;
3299 case OPC1_16_SRR_MUL:
3300 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3301 break;
3302 case OPC1_16_SRR_OR:
3303 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3304 break;
3305 case OPC1_16_SRR_SUB:
3306 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3307 break;
3308 case OPC1_16_SRR_SUB_A15B:
3309 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3310 break;
3311 case OPC1_16_SRR_SUB_15AB:
3312 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3313 break;
3314 case OPC1_16_SRR_SUBS:
3315 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3316 break;
3317 case OPC1_16_SRR_XOR:
3318 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3319 break;
3320 default:
3321 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3322 }
3323 }
3324
3325 static void decode_ssr_opc(DisasContext *ctx, int op1)
3326 {
3327 int r1, r2;
3328
3329 r1 = MASK_OP_SSR_S1(ctx->opcode);
3330 r2 = MASK_OP_SSR_S2(ctx->opcode);
3331
3332 switch (op1) {
3333 case OPC1_16_SSR_ST_A:
3334 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3335 break;
3336 case OPC1_16_SSR_ST_A_POSTINC:
3337 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3338 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3339 break;
3340 case OPC1_16_SSR_ST_B:
3341 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3342 break;
3343 case OPC1_16_SSR_ST_B_POSTINC:
3344 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3345 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3346 break;
3347 case OPC1_16_SSR_ST_H:
3348 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3349 break;
3350 case OPC1_16_SSR_ST_H_POSTINC:
3351 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3352 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3353 break;
3354 case OPC1_16_SSR_ST_W:
3355 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3356 break;
3357 case OPC1_16_SSR_ST_W_POSTINC:
3358 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3359 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3360 break;
3361 default:
3362 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3363 }
3364 }
3365
3366 static void decode_sc_opc(DisasContext *ctx, int op1)
3367 {
3368 int32_t const16;
3369
3370 const16 = MASK_OP_SC_CONST8(ctx->opcode);
3371
3372 switch (op1) {
3373 case OPC1_16_SC_AND:
3374 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3375 break;
3376 case OPC1_16_SC_BISR:
3377 gen_helper_1arg(bisr, const16 & 0xff);
3378 break;
3379 case OPC1_16_SC_LD_A:
3380 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3381 break;
3382 case OPC1_16_SC_LD_W:
3383 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3384 break;
3385 case OPC1_16_SC_MOV:
3386 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3387 break;
3388 case OPC1_16_SC_OR:
3389 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3390 break;
3391 case OPC1_16_SC_ST_A:
3392 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3393 break;
3394 case OPC1_16_SC_ST_W:
3395 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3396 break;
3397 case OPC1_16_SC_SUB_A:
3398 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3399 break;
3400 default:
3401 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3402 }
3403 }
3404
3405 static void decode_slr_opc(DisasContext *ctx, int op1)
3406 {
3407 int r1, r2;
3408
3409 r1 = MASK_OP_SLR_D(ctx->opcode);
3410 r2 = MASK_OP_SLR_S2(ctx->opcode);
3411
3412 switch (op1) {
3413 /* SLR-format */
3414 case OPC1_16_SLR_LD_A:
3415 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3416 break;
3417 case OPC1_16_SLR_LD_A_POSTINC:
3418 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3419 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3420 break;
3421 case OPC1_16_SLR_LD_BU:
3422 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3423 break;
3424 case OPC1_16_SLR_LD_BU_POSTINC:
3425 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3426 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3427 break;
3428 case OPC1_16_SLR_LD_H:
3429 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3430 break;
3431 case OPC1_16_SLR_LD_H_POSTINC:
3432 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3433 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3434 break;
3435 case OPC1_16_SLR_LD_W:
3436 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3437 break;
3438 case OPC1_16_SLR_LD_W_POSTINC:
3439 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3440 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3441 break;
3442 default:
3443 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3444 }
3445 }
3446
3447 static void decode_sro_opc(DisasContext *ctx, int op1)
3448 {
3449 int r2;
3450 int32_t address;
3451
3452 r2 = MASK_OP_SRO_S2(ctx->opcode);
3453 address = MASK_OP_SRO_OFF4(ctx->opcode);
3454
3455 /* SRO-format */
3456 switch (op1) {
3457 case OPC1_16_SRO_LD_A:
3458 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3459 break;
3460 case OPC1_16_SRO_LD_BU:
3461 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3462 break;
3463 case OPC1_16_SRO_LD_H:
3464 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3465 break;
3466 case OPC1_16_SRO_LD_W:
3467 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3468 break;
3469 case OPC1_16_SRO_ST_A:
3470 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3471 break;
3472 case OPC1_16_SRO_ST_B:
3473 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3474 break;
3475 case OPC1_16_SRO_ST_H:
3476 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3477 break;
3478 case OPC1_16_SRO_ST_W:
3479 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3480 break;
3481 default:
3482 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3483 }
3484 }
3485
3486 static void decode_sr_system(DisasContext *ctx)
3487 {
3488 uint32_t op2;
3489 op2 = MASK_OP_SR_OP2(ctx->opcode);
3490
3491 switch (op2) {
3492 case OPC2_16_SR_NOP:
3493 break;
3494 case OPC2_16_SR_RET:
3495 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3496 break;
3497 case OPC2_16_SR_RFE:
3498 gen_helper_rfe(cpu_env);
3499 tcg_gen_exit_tb(NULL, 0);
3500 ctx->base.is_jmp = DISAS_NORETURN;
3501 break;
3502 case OPC2_16_SR_DEBUG:
3503 /* raise EXCP_DEBUG */
3504 break;
3505 case OPC2_16_SR_FRET:
3506 gen_fret(ctx);
3507 break;
3508 default:
3509 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3510 }
3511 }
3512
3513 static void decode_sr_accu(DisasContext *ctx)
3514 {
3515 uint32_t op2;
3516 uint32_t r1;
3517 TCGv temp;
3518
3519 r1 = MASK_OP_SR_S1D(ctx->opcode);
3520 op2 = MASK_OP_SR_OP2(ctx->opcode);
3521
3522 switch (op2) {
3523 case OPC2_16_SR_RSUB:
3524 /* overflow only if r1 = -0x80000000 */
3525 temp = tcg_const_i32(-0x80000000);
3526 /* calc V bit */
3527 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
3528 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3529 /* calc SV bit */
3530 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3531 /* sub */
3532 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3533 /* calc av */
3534 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3535 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3536 /* calc sav */
3537 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3538 break;
3539 case OPC2_16_SR_SAT_B:
3540 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3541 break;
3542 case OPC2_16_SR_SAT_BU:
3543 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3544 break;
3545 case OPC2_16_SR_SAT_H:
3546 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3547 break;
3548 case OPC2_16_SR_SAT_HU:
3549 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3550 break;
3551 default:
3552 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3553 }
3554 }
3555
3556 static void decode_16Bit_opc(DisasContext *ctx)
3557 {
3558 int op1;
3559 int r1, r2;
3560 int32_t const16;
3561 int32_t address;
3562 TCGv temp;
3563
3564 op1 = MASK_OP_MAJOR(ctx->opcode);
3565
3566 /* handle ADDSC.A opcode only being 6 bit long */
3567 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3568 op1 = OPC1_16_SRRS_ADDSC_A;
3569 }
3570
3571 switch (op1) {
3572 case OPC1_16_SRC_ADD:
3573 case OPC1_16_SRC_ADD_A15:
3574 case OPC1_16_SRC_ADD_15A:
3575 case OPC1_16_SRC_ADD_A:
3576 case OPC1_16_SRC_CADD:
3577 case OPC1_16_SRC_CADDN:
3578 case OPC1_16_SRC_CMOV:
3579 case OPC1_16_SRC_CMOVN:
3580 case OPC1_16_SRC_EQ:
3581 case OPC1_16_SRC_LT:
3582 case OPC1_16_SRC_MOV:
3583 case OPC1_16_SRC_MOV_A:
3584 case OPC1_16_SRC_MOV_E:
3585 case OPC1_16_SRC_SH:
3586 case OPC1_16_SRC_SHA:
3587 decode_src_opc(ctx, op1);
3588 break;
3589 /* SRR-format */
3590 case OPC1_16_SRR_ADD:
3591 case OPC1_16_SRR_ADD_A15:
3592 case OPC1_16_SRR_ADD_15A:
3593 case OPC1_16_SRR_ADD_A:
3594 case OPC1_16_SRR_ADDS:
3595 case OPC1_16_SRR_AND:
3596 case OPC1_16_SRR_CMOV:
3597 case OPC1_16_SRR_CMOVN:
3598 case OPC1_16_SRR_EQ:
3599 case OPC1_16_SRR_LT:
3600 case OPC1_16_SRR_MOV:
3601 case OPC1_16_SRR_MOV_A:
3602 case OPC1_16_SRR_MOV_AA:
3603 case OPC1_16_SRR_MOV_D:
3604 case OPC1_16_SRR_MUL:
3605 case OPC1_16_SRR_OR:
3606 case OPC1_16_SRR_SUB:
3607 case OPC1_16_SRR_SUB_A15B:
3608 case OPC1_16_SRR_SUB_15AB:
3609 case OPC1_16_SRR_SUBS:
3610 case OPC1_16_SRR_XOR:
3611 decode_srr_opc(ctx, op1);
3612 break;
3613 /* SSR-format */
3614 case OPC1_16_SSR_ST_A:
3615 case OPC1_16_SSR_ST_A_POSTINC:
3616 case OPC1_16_SSR_ST_B:
3617 case OPC1_16_SSR_ST_B_POSTINC:
3618 case OPC1_16_SSR_ST_H:
3619 case OPC1_16_SSR_ST_H_POSTINC:
3620 case OPC1_16_SSR_ST_W:
3621 case OPC1_16_SSR_ST_W_POSTINC:
3622 decode_ssr_opc(ctx, op1);
3623 break;
3624 /* SRRS-format */
3625 case OPC1_16_SRRS_ADDSC_A:
3626 r2 = MASK_OP_SRRS_S2(ctx->opcode);
3627 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
3628 const16 = MASK_OP_SRRS_N(ctx->opcode);
3629 temp = tcg_temp_new();
3630 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
3631 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
3632 break;
3633 /* SLRO-format */
3634 case OPC1_16_SLRO_LD_A:
3635 r1 = MASK_OP_SLRO_D(ctx->opcode);
3636 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3637 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3638 break;
3639 case OPC1_16_SLRO_LD_BU:
3640 r1 = MASK_OP_SLRO_D(ctx->opcode);
3641 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3642 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3643 break;
3644 case OPC1_16_SLRO_LD_H:
3645 r1 = MASK_OP_SLRO_D(ctx->opcode);
3646 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3647 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3648 break;
3649 case OPC1_16_SLRO_LD_W:
3650 r1 = MASK_OP_SLRO_D(ctx->opcode);
3651 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3652 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3653 break;
3654 /* SB-format */
3655 case OPC1_16_SB_CALL:
3656 case OPC1_16_SB_J:
3657 case OPC1_16_SB_JNZ:
3658 case OPC1_16_SB_JZ:
3659 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
3660 gen_compute_branch(ctx, op1, 0, 0, 0, address);
3661 break;
3662 /* SBC-format */
3663 case OPC1_16_SBC_JEQ:
3664 case OPC1_16_SBC_JNE:
3665 address = MASK_OP_SBC_DISP4(ctx->opcode);
3666 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3667 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3668 break;
3669 case OPC1_16_SBC_JEQ2:
3670 case OPC1_16_SBC_JNE2:
3671 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3672 address = MASK_OP_SBC_DISP4(ctx->opcode);
3673 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
3674 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3675 } else {
3676 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3677 }
3678 break;
3679 /* SBRN-format */
3680 case OPC1_16_SBRN_JNZ_T:
3681 case OPC1_16_SBRN_JZ_T:
3682 address = MASK_OP_SBRN_DISP4(ctx->opcode);
3683 const16 = MASK_OP_SBRN_N(ctx->opcode);
3684 gen_compute_branch(ctx, op1, 0, 0, const16, address);
3685 break;
3686 /* SBR-format */
3687 case OPC1_16_SBR_JEQ2:
3688 case OPC1_16_SBR_JNE2:
3689 if (has_feature(ctx, TRICORE_FEATURE_16)) {
3690 r1 = MASK_OP_SBR_S2(ctx->opcode);
3691 address = MASK_OP_SBR_DISP4(ctx->opcode);
3692 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3693 } else {
3694 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3695 }
3696 break;
3697 case OPC1_16_SBR_JEQ:
3698 case OPC1_16_SBR_JGEZ:
3699 case OPC1_16_SBR_JGTZ:
3700 case OPC1_16_SBR_JLEZ:
3701 case OPC1_16_SBR_JLTZ:
3702 case OPC1_16_SBR_JNE:
3703 case OPC1_16_SBR_JNZ:
3704 case OPC1_16_SBR_JNZ_A:
3705 case OPC1_16_SBR_JZ:
3706 case OPC1_16_SBR_JZ_A:
3707 case OPC1_16_SBR_LOOP:
3708 r1 = MASK_OP_SBR_S2(ctx->opcode);
3709 address = MASK_OP_SBR_DISP4(ctx->opcode);
3710 gen_compute_branch(ctx, op1, r1, 0, 0, address);
3711 break;
3712 /* SC-format */
3713 case OPC1_16_SC_AND:
3714 case OPC1_16_SC_BISR:
3715 case OPC1_16_SC_LD_A:
3716 case OPC1_16_SC_LD_W:
3717 case OPC1_16_SC_MOV:
3718 case OPC1_16_SC_OR:
3719 case OPC1_16_SC_ST_A:
3720 case OPC1_16_SC_ST_W:
3721 case OPC1_16_SC_SUB_A:
3722 decode_sc_opc(ctx, op1);
3723 break;
3724 /* SLR-format */
3725 case OPC1_16_SLR_LD_A:
3726 case OPC1_16_SLR_LD_A_POSTINC:
3727 case OPC1_16_SLR_LD_BU:
3728 case OPC1_16_SLR_LD_BU_POSTINC:
3729 case OPC1_16_SLR_LD_H:
3730 case OPC1_16_SLR_LD_H_POSTINC:
3731 case OPC1_16_SLR_LD_W:
3732 case OPC1_16_SLR_LD_W_POSTINC:
3733 decode_slr_opc(ctx, op1);
3734 break;
3735 /* SRO-format */
3736 case OPC1_16_SRO_LD_A:
3737 case OPC1_16_SRO_LD_BU:
3738 case OPC1_16_SRO_LD_H:
3739 case OPC1_16_SRO_LD_W:
3740 case OPC1_16_SRO_ST_A:
3741 case OPC1_16_SRO_ST_B:
3742 case OPC1_16_SRO_ST_H:
3743 case OPC1_16_SRO_ST_W:
3744 decode_sro_opc(ctx, op1);
3745 break;
3746 /* SSRO-format */
3747 case OPC1_16_SSRO_ST_A:
3748 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3749 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3750 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3751 break;
3752 case OPC1_16_SSRO_ST_B:
3753 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3754 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3755 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3756 break;
3757 case OPC1_16_SSRO_ST_H:
3758 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3759 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3760 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3761 break;
3762 case OPC1_16_SSRO_ST_W:
3763 r1 = MASK_OP_SSRO_S1(ctx->opcode);
3764 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
3765 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3766 break;
3767 /* SR-format */
3768 case OPCM_16_SR_SYSTEM:
3769 decode_sr_system(ctx);
3770 break;
3771 case OPCM_16_SR_ACCU:
3772 decode_sr_accu(ctx);
3773 break;
3774 case OPC1_16_SR_JI:
3775 r1 = MASK_OP_SR_S1D(ctx->opcode);
3776 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
3777 break;
3778 case OPC1_16_SR_NOT:
3779 r1 = MASK_OP_SR_S1D(ctx->opcode);
3780 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3781 break;
3782 default:
3783 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3784 }
3785 }
3786
3787 /*
3788 * 32 bit instructions
3789 */
3790
3791 /* ABS-format */
3792 static void decode_abs_ldw(DisasContext *ctx)
3793 {
3794 int32_t op2;
3795 int32_t r1;
3796 uint32_t address;
3797 TCGv temp;
3798
3799 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3800 address = MASK_OP_ABS_OFF18(ctx->opcode);
3801 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3802
3803 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3804
3805 switch (op2) {
3806 case OPC2_32_ABS_LD_A:
3807 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3808 break;
3809 case OPC2_32_ABS_LD_D:
3810 CHECK_REG_PAIR(r1);
3811 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3812 break;
3813 case OPC2_32_ABS_LD_DA:
3814 CHECK_REG_PAIR(r1);
3815 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3816 break;
3817 case OPC2_32_ABS_LD_W:
3818 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3819 break;
3820 default:
3821 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3822 }
3823 }
3824
3825 static void decode_abs_ldb(DisasContext *ctx)
3826 {
3827 int32_t op2;
3828 int32_t r1;
3829 uint32_t address;
3830 TCGv temp;
3831
3832 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3833 address = MASK_OP_ABS_OFF18(ctx->opcode);
3834 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3835
3836 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3837
3838 switch (op2) {
3839 case OPC2_32_ABS_LD_B:
3840 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
3841 break;
3842 case OPC2_32_ABS_LD_BU:
3843 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3844 break;
3845 case OPC2_32_ABS_LD_H:
3846 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
3847 break;
3848 case OPC2_32_ABS_LD_HU:
3849 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3850 break;
3851 default:
3852 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3853 }
3854 }
3855
3856 static void decode_abs_ldst_swap(DisasContext *ctx)
3857 {
3858 int32_t op2;
3859 int32_t r1;
3860 uint32_t address;
3861 TCGv temp;
3862
3863 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3864 address = MASK_OP_ABS_OFF18(ctx->opcode);
3865 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3866
3867 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3868
3869 switch (op2) {
3870 case OPC2_32_ABS_LDMST:
3871 gen_ldmst(ctx, r1, temp);
3872 break;
3873 case OPC2_32_ABS_SWAP_W:
3874 gen_swap(ctx, r1, temp);
3875 break;
3876 default:
3877 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3878 }
3879 }
3880
3881 static void decode_abs_ldst_context(DisasContext *ctx)
3882 {
3883 uint32_t op2;
3884 int32_t off18;
3885
3886 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
3887 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3888
3889 switch (op2) {
3890 case OPC2_32_ABS_LDLCX:
3891 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
3892 break;
3893 case OPC2_32_ABS_LDUCX:
3894 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
3895 break;
3896 case OPC2_32_ABS_STLCX:
3897 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
3898 break;
3899 case OPC2_32_ABS_STUCX:
3900 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
3901 break;
3902 default:
3903 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3904 }
3905 }
3906
3907 static void decode_abs_store(DisasContext *ctx)
3908 {
3909 int32_t op2;
3910 int32_t r1;
3911 uint32_t address;
3912 TCGv temp;
3913
3914 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3915 address = MASK_OP_ABS_OFF18(ctx->opcode);
3916 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3917
3918 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3919
3920 switch (op2) {
3921 case OPC2_32_ABS_ST_A:
3922 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
3923 break;
3924 case OPC2_32_ABS_ST_D:
3925 CHECK_REG_PAIR(r1);
3926 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
3927 break;
3928 case OPC2_32_ABS_ST_DA:
3929 CHECK_REG_PAIR(r1);
3930 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
3931 break;
3932 case OPC2_32_ABS_ST_W:
3933 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
3934 break;
3935 default:
3936 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3937 }
3938 }
3939
3940 static void decode_abs_storeb_h(DisasContext *ctx)
3941 {
3942 int32_t op2;
3943 int32_t r1;
3944 uint32_t address;
3945 TCGv temp;
3946
3947 r1 = MASK_OP_ABS_S1D(ctx->opcode);
3948 address = MASK_OP_ABS_OFF18(ctx->opcode);
3949 op2 = MASK_OP_ABS_OP2(ctx->opcode);
3950
3951 temp = tcg_const_i32(EA_ABS_FORMAT(address));
3952
3953 switch (op2) {
3954 case OPC2_32_ABS_ST_B:
3955 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
3956 break;
3957 case OPC2_32_ABS_ST_H:
3958 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
3959 break;
3960 default:
3961 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3962 }
3963 }
3964
3965 /* Bit-format */
3966
3967 static void decode_bit_andacc(DisasContext *ctx)
3968 {
3969 uint32_t op2;
3970 int r1, r2, r3;
3971 int pos1, pos2;
3972
3973 r1 = MASK_OP_BIT_S1(ctx->opcode);
3974 r2 = MASK_OP_BIT_S2(ctx->opcode);
3975 r3 = MASK_OP_BIT_D(ctx->opcode);
3976 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
3977 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
3978 op2 = MASK_OP_BIT_OP2(ctx->opcode);
3979
3980
3981 switch (op2) {
3982 case OPC2_32_BIT_AND_AND_T:
3983 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3984 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
3985 break;
3986 case OPC2_32_BIT_AND_ANDN_T:
3987 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3988 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
3989 break;
3990 case OPC2_32_BIT_AND_NOR_T:
3991 if (TCG_TARGET_HAS_andc_i32) {
3992 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3993 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
3994 } else {
3995 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
3996 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
3997 }
3998 break;
3999 case OPC2_32_BIT_AND_OR_T:
4000 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4001 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
4002 break;
4003 default:
4004 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4005 }
4006 }
4007
4008 static void decode_bit_logical_t(DisasContext *ctx)
4009 {
4010 uint32_t op2;
4011 int r1, r2, r3;
4012 int pos1, pos2;
4013 r1 = MASK_OP_BIT_S1(ctx->opcode);
4014 r2 = MASK_OP_BIT_S2(ctx->opcode);
4015 r3 = MASK_OP_BIT_D(ctx->opcode);
4016 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4017 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4018 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4019
4020 switch (op2) {
4021 case OPC2_32_BIT_AND_T:
4022 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4023 pos1, pos2, &tcg_gen_and_tl);
4024 break;
4025 case OPC2_32_BIT_ANDN_T:
4026 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4027 pos1, pos2, &tcg_gen_andc_tl);
4028 break;
4029 case OPC2_32_BIT_NOR_T:
4030 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4031 pos1, pos2, &tcg_gen_nor_tl);
4032 break;
4033 case OPC2_32_BIT_OR_T:
4034 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4035 pos1, pos2, &tcg_gen_or_tl);
4036 break;
4037 default:
4038 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4039 }
4040 }
4041
4042 static void decode_bit_insert(DisasContext *ctx)
4043 {
4044 uint32_t op2;
4045 int r1, r2, r3;
4046 int pos1, pos2;
4047 TCGv temp;
4048 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4049 r1 = MASK_OP_BIT_S1(ctx->opcode);
4050 r2 = MASK_OP_BIT_S2(ctx->opcode);
4051 r3 = MASK_OP_BIT_D(ctx->opcode);
4052 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4053 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4054
4055 temp = tcg_temp_new();
4056
4057 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4058 if (op2 == OPC2_32_BIT_INSN_T) {
4059 tcg_gen_not_tl(temp, temp);
4060 }
4061 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4062 }
4063
4064 static void decode_bit_logical_t2(DisasContext *ctx)
4065 {
4066 uint32_t op2;
4067
4068 int r1, r2, r3;
4069 int pos1, pos2;
4070
4071 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4072 r1 = MASK_OP_BIT_S1(ctx->opcode);
4073 r2 = MASK_OP_BIT_S2(ctx->opcode);
4074 r3 = MASK_OP_BIT_D(ctx->opcode);
4075 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4076 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4077
4078 switch (op2) {
4079 case OPC2_32_BIT_NAND_T:
4080 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4081 pos1, pos2, &tcg_gen_nand_tl);
4082 break;
4083 case OPC2_32_BIT_ORN_T:
4084 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4085 pos1, pos2, &tcg_gen_orc_tl);
4086 break;
4087 case OPC2_32_BIT_XNOR_T:
4088 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4089 pos1, pos2, &tcg_gen_eqv_tl);
4090 break;
4091 case OPC2_32_BIT_XOR_T:
4092 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4093 pos1, pos2, &tcg_gen_xor_tl);
4094 break;
4095 default:
4096 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4097 }
4098 }
4099
4100 static void decode_bit_orand(DisasContext *ctx)
4101 {
4102 uint32_t op2;
4103
4104 int r1, r2, r3;
4105 int pos1, pos2;
4106
4107 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4108 r1 = MASK_OP_BIT_S1(ctx->opcode);
4109 r2 = MASK_OP_BIT_S2(ctx->opcode);
4110 r3 = MASK_OP_BIT_D(ctx->opcode);
4111 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4112 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4113
4114 switch (op2) {
4115 case OPC2_32_BIT_OR_AND_T:
4116 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4117 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4118 break;
4119 case OPC2_32_BIT_OR_ANDN_T:
4120 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4121 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4122 break;
4123 case OPC2_32_BIT_OR_NOR_T:
4124 if (TCG_TARGET_HAS_orc_i32) {
4125 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4126 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4127 } else {
4128 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4129 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4130 }
4131 break;
4132 case OPC2_32_BIT_OR_OR_T:
4133 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4134 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4135 break;
4136 default:
4137 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4138 }
4139 }
4140
4141 static void decode_bit_sh_logic1(DisasContext *ctx)
4142 {
4143 uint32_t op2;
4144 int r1, r2, r3;
4145 int pos1, pos2;
4146 TCGv temp;
4147
4148 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4149 r1 = MASK_OP_BIT_S1(ctx->opcode);
4150 r2 = MASK_OP_BIT_S2(ctx->opcode);
4151 r3 = MASK_OP_BIT_D(ctx->opcode);
4152 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4153 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4154
4155 temp = tcg_temp_new();
4156
4157 switch (op2) {
4158 case OPC2_32_BIT_SH_AND_T:
4159 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4160 pos1, pos2, &tcg_gen_and_tl);
4161 break;
4162 case OPC2_32_BIT_SH_ANDN_T:
4163 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4164 pos1, pos2, &tcg_gen_andc_tl);
4165 break;
4166 case OPC2_32_BIT_SH_NOR_T:
4167 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4168 pos1, pos2, &tcg_gen_nor_tl);
4169 break;
4170 case OPC2_32_BIT_SH_OR_T:
4171 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4172 pos1, pos2, &tcg_gen_or_tl);
4173 break;
4174 default:
4175 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4176 }
4177 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4178 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4179 }
4180
4181 static void decode_bit_sh_logic2(DisasContext *ctx)
4182 {
4183 uint32_t op2;
4184 int r1, r2, r3;
4185 int pos1, pos2;
4186 TCGv temp;
4187
4188 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4189 r1 = MASK_OP_BIT_S1(ctx->opcode);
4190 r2 = MASK_OP_BIT_S2(ctx->opcode);
4191 r3 = MASK_OP_BIT_D(ctx->opcode);
4192 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4193 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4194
4195 temp = tcg_temp_new();
4196
4197 switch (op2) {
4198 case OPC2_32_BIT_SH_NAND_T:
4199 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4200 pos1, pos2, &tcg_gen_nand_tl);
4201 break;
4202 case OPC2_32_BIT_SH_ORN_T:
4203 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4204 pos1, pos2, &tcg_gen_orc_tl);
4205 break;
4206 case OPC2_32_BIT_SH_XNOR_T:
4207 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4208 pos1, pos2, &tcg_gen_eqv_tl);
4209 break;
4210 case OPC2_32_BIT_SH_XOR_T:
4211 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4212 pos1, pos2, &tcg_gen_xor_tl);
4213 break;
4214 default:
4215 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4216 }
4217 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4218 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4219 }
4220
4221 /* BO-format */
4222
4223
4224 static void decode_bo_addrmode_post_pre_base(DisasContext *ctx)
4225 {
4226 uint32_t op2;
4227 uint32_t off10;
4228 int32_t r1, r2;
4229 TCGv temp;
4230
4231 r1 = MASK_OP_BO_S1D(ctx->opcode);
4232 r2 = MASK_OP_BO_S2(ctx->opcode);
4233 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4234 op2 = MASK_OP_BO_OP2(ctx->opcode);
4235
4236 switch (op2) {
4237 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4238 case OPC2_32_BO_CACHEA_W_SHORTOFF:
4239 case OPC2_32_BO_CACHEA_I_SHORTOFF:
4240 /* instruction to access the cache */
4241 break;
4242 case OPC2_32_BO_CACHEA_WI_POSTINC:
4243 case OPC2_32_BO_CACHEA_W_POSTINC:
4244 case OPC2_32_BO_CACHEA_I_POSTINC:
4245 /* instruction to access the cache, but we still need to handle
4246 the addressing mode */
4247 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4248 break;
4249 case OPC2_32_BO_CACHEA_WI_PREINC:
4250 case OPC2_32_BO_CACHEA_W_PREINC:
4251 case OPC2_32_BO_CACHEA_I_PREINC:
4252 /* instruction to access the cache, but we still need to handle
4253 the addressing mode */
4254 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4255 break;
4256 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4257 case OPC2_32_BO_CACHEI_W_SHORTOFF:
4258 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
4259 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4260 }
4261 break;
4262 case OPC2_32_BO_CACHEI_W_POSTINC:
4263 case OPC2_32_BO_CACHEI_WI_POSTINC:
4264 if (has_feature(ctx, TRICORE_FEATURE_131)) {
4265 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4266 } else {
4267 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4268 }
4269 break;
4270 case OPC2_32_BO_CACHEI_W_PREINC:
4271 case OPC2_32_BO_CACHEI_WI_PREINC:
4272 if (has_feature(ctx, TRICORE_FEATURE_131)) {
4273 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4274 } else {
4275 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4276 }
4277 break;
4278 case OPC2_32_BO_ST_A_SHORTOFF:
4279 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4280 break;
4281 case OPC2_32_BO_ST_A_POSTINC:
4282 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4283 MO_LESL);
4284 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4285 break;
4286 case OPC2_32_BO_ST_A_PREINC:
4287 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4288 break;
4289 case OPC2_32_BO_ST_B_SHORTOFF:
4290 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4291 break;
4292 case OPC2_32_BO_ST_B_POSTINC:
4293 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4294 MO_UB);
4295 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4296 break;
4297 case OPC2_32_BO_ST_B_PREINC:
4298 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4299 break;
4300 case OPC2_32_BO_ST_D_SHORTOFF:
4301 CHECK_REG_PAIR(r1);
4302 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4303 off10, ctx);
4304 break;
4305 case OPC2_32_BO_ST_D_POSTINC:
4306 CHECK_REG_PAIR(r1);
4307 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4308 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4309 break;
4310 case OPC2_32_BO_ST_D_PREINC:
4311 CHECK_REG_PAIR(r1);
4312 temp = tcg_temp_new();
4313 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4314 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4315 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4316 break;
4317 case OPC2_32_BO_ST_DA_SHORTOFF:
4318 CHECK_REG_PAIR(r1);
4319 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4320 off10, ctx);
4321 break;
4322 case OPC2_32_BO_ST_DA_POSTINC:
4323 CHECK_REG_PAIR(r1);
4324 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4325 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4326 break;
4327 case OPC2_32_BO_ST_DA_PREINC:
4328 CHECK_REG_PAIR(r1);
4329 temp = tcg_temp_new();
4330 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4331 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4332 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4333 break;
4334 case OPC2_32_BO_ST_H_SHORTOFF:
4335 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4336 break;
4337 case OPC2_32_BO_ST_H_POSTINC:
4338 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4339 MO_LEUW);
4340 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4341 break;
4342 case OPC2_32_BO_ST_H_PREINC:
4343 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4344 break;
4345 case OPC2_32_BO_ST_Q_SHORTOFF:
4346 temp = tcg_temp_new();
4347 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4348 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4349 break;
4350 case OPC2_32_BO_ST_Q_POSTINC:
4351 temp = tcg_temp_new();
4352 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4353 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4354 MO_LEUW);
4355 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4356 break;
4357 case OPC2_32_BO_ST_Q_PREINC:
4358 temp = tcg_temp_new();
4359 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4360 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4361 break;
4362 case OPC2_32_BO_ST_W_SHORTOFF:
4363 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4364 break;
4365 case OPC2_32_BO_ST_W_POSTINC:
4366 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4367 MO_LEUL);
4368 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4369 break;
4370 case OPC2_32_BO_ST_W_PREINC:
4371 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4372 break;
4373 default:
4374 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4375 }
4376 }
4377
4378 static void decode_bo_addrmode_bitreverse_circular(DisasContext *ctx)
4379 {
4380 uint32_t op2;
4381 uint32_t off10;
4382 int32_t r1, r2;
4383 TCGv temp, temp2, temp3;
4384
4385 r1 = MASK_OP_BO_S1D(ctx->opcode);
4386 r2 = MASK_OP_BO_S2(ctx->opcode);
4387 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4388 op2 = MASK_OP_BO_OP2(ctx->opcode);
4389
4390 temp = tcg_temp_new();
4391 temp2 = tcg_temp_new();
4392 temp3 = tcg_const_i32(off10);
4393 CHECK_REG_PAIR(r2);
4394 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4395 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4396
4397 switch (op2) {
4398 case OPC2_32_BO_CACHEA_WI_BR:
4399 case OPC2_32_BO_CACHEA_W_BR:
4400 case OPC2_32_BO_CACHEA_I_BR:
4401 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4402 break;
4403 case OPC2_32_BO_CACHEA_WI_CIRC:
4404 case OPC2_32_BO_CACHEA_W_CIRC:
4405 case OPC2_32_BO_CACHEA_I_CIRC:
4406 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4407 break;
4408 case OPC2_32_BO_ST_A_BR:
4409 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4410 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4411 break;
4412 case OPC2_32_BO_ST_A_CIRC:
4413 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4414 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4415 break;
4416 case OPC2_32_BO_ST_B_BR:
4417 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4418 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4419 break;
4420 case OPC2_32_BO_ST_B_CIRC:
4421 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4422 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4423 break;
4424 case OPC2_32_BO_ST_D_BR:
4425 CHECK_REG_PAIR(r1);
4426 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4427 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4428 break;
4429 case OPC2_32_BO_ST_D_CIRC:
4430 CHECK_REG_PAIR(r1);
4431 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4432 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4433 tcg_gen_addi_tl(temp, temp, 4);
4434 tcg_gen_rem_tl(temp, temp, temp2);
4435 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4436 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4437 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4438 break;
4439 case OPC2_32_BO_ST_DA_BR:
4440 CHECK_REG_PAIR(r1);
4441 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4442 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4443 break;
4444 case OPC2_32_BO_ST_DA_CIRC:
4445 CHECK_REG_PAIR(r1);
4446 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4447 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4448 tcg_gen_addi_tl(temp, temp, 4);
4449 tcg_gen_rem_tl(temp, temp, temp2);
4450 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4451 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4452 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4453 break;
4454 case OPC2_32_BO_ST_H_BR:
4455 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4456 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4457 break;
4458 case OPC2_32_BO_ST_H_CIRC:
4459 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4460 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4461 break;
4462 case OPC2_32_BO_ST_Q_BR:
4463 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4464 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4465 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4466 break;
4467 case OPC2_32_BO_ST_Q_CIRC:
4468 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4469 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4470 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4471 break;
4472 case OPC2_32_BO_ST_W_BR:
4473 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4474 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4475 break;
4476 case OPC2_32_BO_ST_W_CIRC:
4477 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4478 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4479 break;
4480 default:
4481 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4482 }
4483 }
4484
4485 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
4486 {
4487 uint32_t op2;
4488 uint32_t off10;
4489 int32_t r1, r2;
4490 TCGv temp;
4491
4492 r1 = MASK_OP_BO_S1D(ctx->opcode);
4493 r2 = MASK_OP_BO_S2(ctx->opcode);
4494 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4495 op2 = MASK_OP_BO_OP2(ctx->opcode);
4496
4497 switch (op2) {
4498 case OPC2_32_BO_LD_A_SHORTOFF:
4499 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4500 break;
4501 case OPC2_32_BO_LD_A_POSTINC:
4502 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4503 MO_LEUL);
4504 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4505 break;
4506 case OPC2_32_BO_LD_A_PREINC:
4507 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4508 break;
4509 case OPC2_32_BO_LD_B_SHORTOFF:
4510 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4511 break;
4512 case OPC2_32_BO_LD_B_POSTINC:
4513 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4514 MO_SB);
4515 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4516 break;
4517 case OPC2_32_BO_LD_B_PREINC:
4518 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4519 break;
4520 case OPC2_32_BO_LD_BU_SHORTOFF:
4521 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4522 break;
4523 case OPC2_32_BO_LD_BU_POSTINC:
4524 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4525 MO_UB);
4526 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4527 break;
4528 case OPC2_32_BO_LD_BU_PREINC:
4529 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4530 break;
4531 case OPC2_32_BO_LD_D_SHORTOFF:
4532 CHECK_REG_PAIR(r1);
4533 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4534 off10, ctx);
4535 break;
4536 case OPC2_32_BO_LD_D_POSTINC:
4537 CHECK_REG_PAIR(r1);
4538 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4539 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4540 break;
4541 case OPC2_32_BO_LD_D_PREINC:
4542 CHECK_REG_PAIR(r1);
4543 temp = tcg_temp_new();
4544 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4545 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4546 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4547 break;
4548 case OPC2_32_BO_LD_DA_SHORTOFF:
4549 CHECK_REG_PAIR(r1);
4550 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4551 off10, ctx);
4552 break;
4553 case OPC2_32_BO_LD_DA_POSTINC:
4554 CHECK_REG_PAIR(r1);
4555 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4556 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4557 break;
4558 case OPC2_32_BO_LD_DA_PREINC:
4559 CHECK_REG_PAIR(r1);
4560 temp = tcg_temp_new();
4561 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4562 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4563 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4564 break;
4565 case OPC2_32_BO_LD_H_SHORTOFF:
4566 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4567 break;
4568 case OPC2_32_BO_LD_H_POSTINC:
4569 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4570 MO_LESW);
4571 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4572 break;
4573 case OPC2_32_BO_LD_H_PREINC:
4574 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4575 break;
4576 case OPC2_32_BO_LD_HU_SHORTOFF:
4577 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4578 break;
4579 case OPC2_32_BO_LD_HU_POSTINC:
4580 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4581 MO_LEUW);
4582 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4583 break;
4584 case OPC2_32_BO_LD_HU_PREINC:
4585 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4586 break;
4587 case OPC2_32_BO_LD_Q_SHORTOFF:
4588 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4589 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4590 break;
4591 case OPC2_32_BO_LD_Q_POSTINC:
4592 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4593 MO_LEUW);
4594 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4595 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4596 break;
4597 case OPC2_32_BO_LD_Q_PREINC:
4598 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4599 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4600 break;
4601 case OPC2_32_BO_LD_W_SHORTOFF:
4602 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4603 break;
4604 case OPC2_32_BO_LD_W_POSTINC:
4605 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4606 MO_LEUL);
4607 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4608 break;
4609 case OPC2_32_BO_LD_W_PREINC:
4610 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4611 break;
4612 default:
4613 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4614 }
4615 }
4616
4617 static void decode_bo_addrmode_ld_bitreverse_circular(DisasContext *ctx)
4618 {
4619 uint32_t op2;
4620 uint32_t off10;
4621 int r1, r2;
4622
4623 TCGv temp, temp2, temp3;
4624
4625 r1 = MASK_OP_BO_S1D(ctx->opcode);
4626 r2 = MASK_OP_BO_S2(ctx->opcode);
4627 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4628 op2 = MASK_OP_BO_OP2(ctx->opcode);
4629
4630 temp = tcg_temp_new();
4631 temp2 = tcg_temp_new();
4632 temp3 = tcg_const_i32(off10);
4633 CHECK_REG_PAIR(r2);
4634 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4635 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4636
4637
4638 switch (op2) {
4639 case OPC2_32_BO_LD_A_BR:
4640 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4641 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4642 break;
4643 case OPC2_32_BO_LD_A_CIRC:
4644 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4645 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4646 break;
4647 case OPC2_32_BO_LD_B_BR:
4648 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4649 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4650 break;
4651 case OPC2_32_BO_LD_B_CIRC:
4652 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4653 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4654 break;
4655 case OPC2_32_BO_LD_BU_BR:
4656 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4657 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4658 break;
4659 case OPC2_32_BO_LD_BU_CIRC:
4660 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4661 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4662 break;
4663 case OPC2_32_BO_LD_D_BR:
4664 CHECK_REG_PAIR(r1);
4665 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4666 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4667 break;
4668 case OPC2_32_BO_LD_D_CIRC:
4669 CHECK_REG_PAIR(r1);
4670 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4671 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4672 tcg_gen_addi_tl(temp, temp, 4);
4673 tcg_gen_rem_tl(temp, temp, temp2);
4674 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4675 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4676 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4677 break;
4678 case OPC2_32_BO_LD_DA_BR:
4679 CHECK_REG_PAIR(r1);
4680 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4681 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4682 break;
4683 case OPC2_32_BO_LD_DA_CIRC:
4684 CHECK_REG_PAIR(r1);
4685 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4686 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4687 tcg_gen_addi_tl(temp, temp, 4);
4688 tcg_gen_rem_tl(temp, temp, temp2);
4689 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4690 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4691 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4692 break;
4693 case OPC2_32_BO_LD_H_BR:
4694 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4695 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4696 break;
4697 case OPC2_32_BO_LD_H_CIRC:
4698 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4699 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4700 break;
4701 case OPC2_32_BO_LD_HU_BR:
4702 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4703 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4704 break;
4705 case OPC2_32_BO_LD_HU_CIRC:
4706 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4707 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4708 break;
4709 case OPC2_32_BO_LD_Q_BR:
4710 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4711 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4712 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4713 break;
4714 case OPC2_32_BO_LD_Q_CIRC:
4715 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4716 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4717 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4718 break;
4719 case OPC2_32_BO_LD_W_BR:
4720 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4721 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4722 break;
4723 case OPC2_32_BO_LD_W_CIRC:
4724 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4725 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4726 break;
4727 default:
4728 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4729 }
4730 }
4731
4732 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx)
4733 {
4734 uint32_t op2;
4735 uint32_t off10;
4736 int r1, r2;
4737
4738 TCGv temp;
4739
4740 r1 = MASK_OP_BO_S1D(ctx->opcode);
4741 r2 = MASK_OP_BO_S2(ctx->opcode);
4742 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4743 op2 = MASK_OP_BO_OP2(ctx->opcode);
4744
4745
4746 temp = tcg_temp_new();
4747
4748 switch (op2) {
4749 case OPC2_32_BO_LDLCX_SHORTOFF:
4750 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4751 gen_helper_ldlcx(cpu_env, temp);
4752 break;
4753 case OPC2_32_BO_LDMST_SHORTOFF:
4754 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4755 gen_ldmst(ctx, r1, temp);
4756 break;
4757 case OPC2_32_BO_LDMST_POSTINC:
4758 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4759 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4760 break;
4761 case OPC2_32_BO_LDMST_PREINC:
4762 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4763 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
4764 break;
4765 case OPC2_32_BO_LDUCX_SHORTOFF:
4766 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4767 gen_helper_lducx(cpu_env, temp);
4768 break;
4769 case OPC2_32_BO_LEA_SHORTOFF:
4770 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
4771 break;
4772 case OPC2_32_BO_STLCX_SHORTOFF:
4773 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4774 gen_helper_stlcx(cpu_env, temp);
4775 break;
4776 case OPC2_32_BO_STUCX_SHORTOFF:
4777 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4778 gen_helper_stucx(cpu_env, temp);
4779 break;
4780 case OPC2_32_BO_SWAP_W_SHORTOFF:
4781 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4782 gen_swap(ctx, r1, temp);
4783 break;
4784 case OPC2_32_BO_SWAP_W_POSTINC:
4785 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4786 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4787 break;
4788 case OPC2_32_BO_SWAP_W_PREINC:
4789 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4790 gen_swap(ctx, r1, cpu_gpr_a[r2]);
4791 break;
4792 case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
4793 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4794 gen_cmpswap(ctx, r1, temp);
4795 break;
4796 case OPC2_32_BO_CMPSWAP_W_POSTINC:
4797 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
4798 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4799 break;
4800 case OPC2_32_BO_CMPSWAP_W_PREINC:
4801 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4802 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
4803 break;
4804 case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
4805 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4806 gen_swapmsk(ctx, r1, temp);
4807 break;
4808 case OPC2_32_BO_SWAPMSK_W_POSTINC:
4809 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
4810 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4811 break;
4812 case OPC2_32_BO_SWAPMSK_W_PREINC:
4813 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4814 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
4815 break;
4816 default:
4817 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4818 }
4819 }
4820
4821 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx)
4822 {
4823 uint32_t op2;
4824 uint32_t off10;
4825 int r1, r2;
4826
4827 TCGv temp, temp2, temp3;
4828
4829 r1 = MASK_OP_BO_S1D(ctx->opcode);
4830 r2 = MASK_OP_BO_S2(ctx->opcode);
4831 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4832 op2 = MASK_OP_BO_OP2(ctx->opcode);
4833
4834 temp = tcg_temp_new();
4835 temp2 = tcg_temp_new();
4836 temp3 = tcg_const_i32(off10);
4837 CHECK_REG_PAIR(r2);
4838 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4839 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4840
4841 switch (op2) {
4842 case OPC2_32_BO_LDMST_BR:
4843 gen_ldmst(ctx, r1, temp2);
4844 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4845 break;
4846 case OPC2_32_BO_LDMST_CIRC:
4847 gen_ldmst(ctx, r1, temp2);
4848 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4849 break;
4850 case OPC2_32_BO_SWAP_W_BR:
4851 gen_swap(ctx, r1, temp2);
4852 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4853 break;
4854 case OPC2_32_BO_SWAP_W_CIRC:
4855 gen_swap(ctx, r1, temp2);
4856 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4857 break;
4858 case OPC2_32_BO_CMPSWAP_W_BR:
4859 gen_cmpswap(ctx, r1, temp2);
4860 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4861 break;
4862 case OPC2_32_BO_CMPSWAP_W_CIRC:
4863 gen_cmpswap(ctx, r1, temp2);
4864 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4865 break;
4866 case OPC2_32_BO_SWAPMSK_W_BR:
4867 gen_swapmsk(ctx, r1, temp2);
4868 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4869 break;
4870 case OPC2_32_BO_SWAPMSK_W_CIRC:
4871 gen_swapmsk(ctx, r1, temp2);
4872 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4873 break;
4874 default:
4875 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4876 }
4877 }
4878
4879 static void decode_bol_opc(DisasContext *ctx, int32_t op1)
4880 {
4881 int r1, r2;
4882 int32_t address;
4883 TCGv temp;
4884
4885 r1 = MASK_OP_BOL_S1D(ctx->opcode);
4886 r2 = MASK_OP_BOL_S2(ctx->opcode);
4887 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
4888
4889 switch (op1) {
4890 case OPC1_32_BOL_LD_A_LONGOFF:
4891 temp = tcg_temp_new();
4892 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4893 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
4894 break;
4895 case OPC1_32_BOL_LD_W_LONGOFF:
4896 temp = tcg_temp_new();
4897 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
4898 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
4899 break;
4900 case OPC1_32_BOL_LEA_LONGOFF:
4901 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
4902 break;
4903 case OPC1_32_BOL_ST_A_LONGOFF:
4904 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4905 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
4906 } else {
4907 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4908 }
4909 break;
4910 case OPC1_32_BOL_ST_W_LONGOFF:
4911 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
4912 break;
4913 case OPC1_32_BOL_LD_B_LONGOFF:
4914 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4915 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4916 } else {
4917 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4918 }
4919 break;
4920 case OPC1_32_BOL_LD_BU_LONGOFF:
4921 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4922 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
4923 } else {
4924 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4925 }
4926 break;
4927 case OPC1_32_BOL_LD_H_LONGOFF:
4928 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4929 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4930 } else {
4931 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4932 }
4933 break;
4934 case OPC1_32_BOL_LD_HU_LONGOFF:
4935 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4936 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
4937 } else {
4938 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4939 }
4940 break;
4941 case OPC1_32_BOL_ST_B_LONGOFF:
4942 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4943 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
4944 } else {
4945 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4946 }
4947 break;
4948 case OPC1_32_BOL_ST_H_LONGOFF:
4949 if (has_feature(ctx, TRICORE_FEATURE_16)) {
4950 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
4951 } else {
4952 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4953 }
4954 break;
4955 default:
4956 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4957 }
4958 }
4959
4960 /* RC format */
4961 static void decode_rc_logical_shift(DisasContext *ctx)
4962 {
4963 uint32_t op2;
4964 int r1, r2;
4965 int32_t const9;
4966 TCGv temp;
4967
4968 r2 = MASK_OP_RC_D(ctx->opcode);
4969 r1 = MASK_OP_RC_S1(ctx->opcode);
4970 const9 = MASK_OP_RC_CONST9(ctx->opcode);
4971 op2 = MASK_OP_RC_OP2(ctx->opcode);
4972
4973 temp = tcg_temp_new();
4974
4975 switch (op2) {
4976 case OPC2_32_RC_AND:
4977 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4978 break;
4979 case OPC2_32_RC_ANDN:
4980 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4981 break;
4982 case OPC2_32_RC_NAND:
4983 tcg_gen_movi_tl(temp, const9);
4984 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4985 break;
4986 case OPC2_32_RC_NOR:
4987 tcg_gen_movi_tl(temp, const9);
4988 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
4989 break;
4990 case OPC2_32_RC_OR:
4991 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4992 break;
4993 case OPC2_32_RC_ORN:
4994 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
4995 break;
4996 case OPC2_32_RC_SH:
4997 const9 = sextract32(const9, 0, 6);
4998 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
4999 break;
5000 case OPC2_32_RC_SH_H:
5001 const9 = sextract32(const9, 0, 5);
5002 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5003 break;
5004 case OPC2_32_RC_SHA:
5005 const9 = sextract32(const9, 0, 6);
5006 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5007 break;
5008 case OPC2_32_RC_SHA_H:
5009 const9 = sextract32(const9, 0, 5);
5010 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5011 break;
5012 case OPC2_32_RC_SHAS:
5013 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5014 break;
5015 case OPC2_32_RC_XNOR:
5016 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5017 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
5018 break;
5019 case OPC2_32_RC_XOR:
5020 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5021 break;
5022 default:
5023 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5024 }
5025 }
5026
5027 static void decode_rc_accumulator(DisasContext *ctx)
5028 {
5029 uint32_t op2;
5030 int r1, r2;
5031 int16_t const9;
5032
5033 TCGv temp;
5034
5035 r2 = MASK_OP_RC_D(ctx->opcode);
5036 r1 = MASK_OP_RC_S1(ctx->opcode);
5037 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5038
5039 op2 = MASK_OP_RC_OP2(ctx->opcode);
5040
5041 temp = tcg_temp_new();
5042
5043 switch (op2) {
5044 case OPC2_32_RC_ABSDIF:
5045 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5046 break;
5047 case OPC2_32_RC_ABSDIFS:
5048 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5049 break;
5050 case OPC2_32_RC_ADD:
5051 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5052 break;
5053 case OPC2_32_RC_ADDC:
5054 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5055 break;
5056 case OPC2_32_RC_ADDS:
5057 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5058 break;
5059 case OPC2_32_RC_ADDS_U:
5060 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5061 break;
5062 case OPC2_32_RC_ADDX:
5063 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5064 break;
5065 case OPC2_32_RC_AND_EQ:
5066 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5067 const9, &tcg_gen_and_tl);
5068 break;
5069 case OPC2_32_RC_AND_GE:
5070 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5071 const9, &tcg_gen_and_tl);
5072 break;
5073 case OPC2_32_RC_AND_GE_U:
5074 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5075 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5076 const9, &tcg_gen_and_tl);
5077 break;
5078 case OPC2_32_RC_AND_LT:
5079 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5080 const9, &tcg_gen_and_tl);
5081 break;
5082 case OPC2_32_RC_AND_LT_U:
5083 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5084 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5085 const9, &tcg_gen_and_tl);
5086 break;
5087 case OPC2_32_RC_AND_NE:
5088 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5089 const9, &tcg_gen_and_tl);
5090 break;
5091 case OPC2_32_RC_EQ:
5092 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5093 break;
5094 case OPC2_32_RC_EQANY_B:
5095 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5096 break;
5097 case OPC2_32_RC_EQANY_H:
5098 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5099 break;
5100 case OPC2_32_RC_GE:
5101 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5102 break;
5103 case OPC2_32_RC_GE_U:
5104 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5105 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5106 break;
5107 case OPC2_32_RC_LT:
5108 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5109 break;
5110 case OPC2_32_RC_LT_U:
5111 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5112 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5113 break;
5114 case OPC2_32_RC_MAX:
5115 tcg_gen_movi_tl(temp, const9);
5116 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5117 cpu_gpr_d[r1], temp);
5118 break;
5119 case OPC2_32_RC_MAX_U:
5120 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5121 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5122 cpu_gpr_d[r1], temp);
5123 break;
5124 case OPC2_32_RC_MIN:
5125 tcg_gen_movi_tl(temp, const9);
5126 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5127 cpu_gpr_d[r1], temp);
5128 break;
5129 case OPC2_32_RC_MIN_U:
5130 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5131 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5132 cpu_gpr_d[r1], temp);
5133 break;
5134 case OPC2_32_RC_NE:
5135 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5136 break;
5137 case OPC2_32_RC_OR_EQ:
5138 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5139 const9, &tcg_gen_or_tl);
5140 break;
5141 case OPC2_32_RC_OR_GE:
5142 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5143 const9, &tcg_gen_or_tl);
5144 break;
5145 case OPC2_32_RC_OR_GE_U:
5146 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5147 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5148 const9, &tcg_gen_or_tl);
5149 break;
5150 case OPC2_32_RC_OR_LT:
5151 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5152 const9, &tcg_gen_or_tl);
5153 break;
5154 case OPC2_32_RC_OR_LT_U:
5155 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5156 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5157 const9, &tcg_gen_or_tl);
5158 break;
5159 case OPC2_32_RC_OR_NE:
5160 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5161 const9, &tcg_gen_or_tl);
5162 break;
5163 case OPC2_32_RC_RSUB:
5164 tcg_gen_movi_tl(temp, const9);
5165 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5166 break;
5167 case OPC2_32_RC_RSUBS:
5168 tcg_gen_movi_tl(temp, const9);
5169 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5170 break;
5171 case OPC2_32_RC_RSUBS_U:
5172 tcg_gen_movi_tl(temp, const9);
5173 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5174 break;
5175 case OPC2_32_RC_SH_EQ:
5176 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5177 break;
5178 case OPC2_32_RC_SH_GE:
5179 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5180 break;
5181 case OPC2_32_RC_SH_GE_U:
5182 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5183 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5184 break;
5185 case OPC2_32_RC_SH_LT:
5186 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5187 break;
5188 case OPC2_32_RC_SH_LT_U:
5189 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5190 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5191 break;
5192 case OPC2_32_RC_SH_NE:
5193 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5194 break;
5195 case OPC2_32_RC_XOR_EQ:
5196 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5197 const9, &tcg_gen_xor_tl);
5198 break;
5199 case OPC2_32_RC_XOR_GE:
5200 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5201 const9, &tcg_gen_xor_tl);
5202 break;
5203 case OPC2_32_RC_XOR_GE_U:
5204 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5205 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5206 const9, &tcg_gen_xor_tl);
5207 break;
5208 case OPC2_32_RC_XOR_LT:
5209 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5210 const9, &tcg_gen_xor_tl);
5211 break;
5212 case OPC2_32_RC_XOR_LT_U:
5213 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5214 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5215 const9, &tcg_gen_xor_tl);
5216 break;
5217 case OPC2_32_RC_XOR_NE:
5218 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5219 const9, &tcg_gen_xor_tl);
5220 break;
5221 default:
5222 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5223 }
5224 }
5225
5226 static void decode_rc_serviceroutine(DisasContext *ctx)
5227 {
5228 uint32_t op2;
5229 uint32_t const9;
5230
5231 op2 = MASK_OP_RC_OP2(ctx->opcode);
5232 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5233
5234 switch (op2) {
5235 case OPC2_32_RC_BISR:
5236 gen_helper_1arg(bisr, const9);
5237 break;
5238 case OPC2_32_RC_SYSCALL:
5239 /* TODO: Add exception generation */
5240 break;
5241 default:
5242 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5243 }
5244 }
5245
5246 static void decode_rc_mul(DisasContext *ctx)
5247 {
5248 uint32_t op2;
5249 int r1, r2;
5250 int16_t const9;
5251
5252 r2 = MASK_OP_RC_D(ctx->opcode);
5253 r1 = MASK_OP_RC_S1(ctx->opcode);
5254 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5255
5256 op2 = MASK_OP_RC_OP2(ctx->opcode);
5257
5258 switch (op2) {
5259 case OPC2_32_RC_MUL_32:
5260 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5261 break;
5262 case OPC2_32_RC_MUL_64:
5263 CHECK_REG_PAIR(r2);
5264 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5265 break;
5266 case OPC2_32_RC_MULS_32:
5267 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5268 break;
5269 case OPC2_32_RC_MUL_U_64:
5270 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5271 CHECK_REG_PAIR(r2);
5272 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5273 break;
5274 case OPC2_32_RC_MULS_U_32:
5275 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5276 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5277 break;
5278 default:
5279 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5280 }
5281 }
5282
5283 /* RCPW format */
5284 static void decode_rcpw_insert(DisasContext *ctx)
5285 {
5286 uint32_t op2;
5287 int r1, r2;
5288 int32_t pos, width, const4;
5289
5290 TCGv temp;
5291
5292 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
5293 r1 = MASK_OP_RCPW_S1(ctx->opcode);
5294 r2 = MASK_OP_RCPW_D(ctx->opcode);
5295 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
5296 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
5297 pos = MASK_OP_RCPW_POS(ctx->opcode);
5298
5299 switch (op2) {
5300 case OPC2_32_RCPW_IMASK:
5301 CHECK_REG_PAIR(r2);
5302 /* if pos + width > 32 undefined result */
5303 if (pos + width <= 32) {
5304 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
5305 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
5306 }
5307 break;
5308 case OPC2_32_RCPW_INSERT:
5309 /* if pos + width > 32 undefined result */
5310 if (pos + width <= 32) {
5311 temp = tcg_const_i32(const4);
5312 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
5313 }
5314 break;
5315 default:
5316 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5317 }
5318 }
5319
5320 /* RCRW format */
5321
5322 static void decode_rcrw_insert(DisasContext *ctx)
5323 {
5324 uint32_t op2;
5325 int r1, r3, r4;
5326 int32_t width, const4;
5327
5328 TCGv temp, temp2, temp3;
5329
5330 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
5331 r1 = MASK_OP_RCRW_S1(ctx->opcode);
5332 r3 = MASK_OP_RCRW_S3(ctx->opcode);
5333 r4 = MASK_OP_RCRW_D(ctx->opcode);
5334 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
5335 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
5336
5337 temp = tcg_temp_new();
5338 temp2 = tcg_temp_new();
5339
5340 switch (op2) {
5341 case OPC2_32_RCRW_IMASK:
5342 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
5343 tcg_gen_movi_tl(temp2, (1 << width) - 1);
5344 tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
5345 tcg_gen_movi_tl(temp2, const4);
5346 tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
5347 break;
5348 case OPC2_32_RCRW_INSERT:
5349 temp3 = tcg_temp_new();
5350
5351 tcg_gen_movi_tl(temp, width);
5352 tcg_gen_movi_tl(temp2, const4);
5353 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
5354 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
5355 break;
5356 default:
5357 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5358 }
5359 }
5360
5361 /* RCR format */
5362
5363 static void decode_rcr_cond_select(DisasContext *ctx)
5364 {
5365 uint32_t op2;
5366 int r1, r3, r4;
5367 int32_t const9;
5368
5369 TCGv temp, temp2;
5370
5371 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5372 r1 = MASK_OP_RCR_S1(ctx->opcode);
5373 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5374 r3 = MASK_OP_RCR_S3(ctx->opcode);
5375 r4 = MASK_OP_RCR_D(ctx->opcode);
5376
5377 switch (op2) {
5378 case OPC2_32_RCR_CADD:
5379 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
5380 cpu_gpr_d[r3]);
5381 break;
5382 case OPC2_32_RCR_CADDN:
5383 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4],
5384 cpu_gpr_d[r3]);
5385 break;
5386 case OPC2_32_RCR_SEL:
5387 temp = tcg_const_i32(0);
5388 temp2 = tcg_const_i32(const9);
5389 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5390 cpu_gpr_d[r1], temp2);
5391 break;
5392 case OPC2_32_RCR_SELN:
5393 temp = tcg_const_i32(0);
5394 temp2 = tcg_const_i32(const9);
5395 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5396 cpu_gpr_d[r1], temp2);
5397 break;
5398 default:
5399 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5400 }
5401 }
5402
5403 static void decode_rcr_madd(DisasContext *ctx)
5404 {
5405 uint32_t op2;
5406 int r1, r3, r4;
5407 int32_t const9;
5408
5409
5410 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5411 r1 = MASK_OP_RCR_S1(ctx->opcode);
5412 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5413 r3 = MASK_OP_RCR_S3(ctx->opcode);
5414 r4 = MASK_OP_RCR_D(ctx->opcode);
5415
5416 switch (op2) {
5417 case OPC2_32_RCR_MADD_32:
5418 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5419 break;
5420 case OPC2_32_RCR_MADD_64:
5421 CHECK_REG_PAIR(r4);
5422 CHECK_REG_PAIR(r3);
5423 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5424 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5425 break;
5426 case OPC2_32_RCR_MADDS_32:
5427 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5428 break;
5429 case OPC2_32_RCR_MADDS_64:
5430 CHECK_REG_PAIR(r4);
5431 CHECK_REG_PAIR(r3);
5432 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5433 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5434 break;
5435 case OPC2_32_RCR_MADD_U_64:
5436 CHECK_REG_PAIR(r4);
5437 CHECK_REG_PAIR(r3);
5438 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5439 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5440 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5441 break;
5442 case OPC2_32_RCR_MADDS_U_32:
5443 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5444 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5445 break;
5446 case OPC2_32_RCR_MADDS_U_64:
5447 CHECK_REG_PAIR(r4);
5448 CHECK_REG_PAIR(r3);
5449 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5450 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5451 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5452 break;
5453 default:
5454 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5455 }
5456 }
5457
5458 static void decode_rcr_msub(DisasContext *ctx)
5459 {
5460 uint32_t op2;
5461 int r1, r3, r4;
5462 int32_t const9;
5463
5464
5465 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5466 r1 = MASK_OP_RCR_S1(ctx->opcode);
5467 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5468 r3 = MASK_OP_RCR_S3(ctx->opcode);
5469 r4 = MASK_OP_RCR_D(ctx->opcode);
5470
5471 switch (op2) {
5472 case OPC2_32_RCR_MSUB_32:
5473 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5474 break;
5475 case OPC2_32_RCR_MSUB_64:
5476 CHECK_REG_PAIR(r4);
5477 CHECK_REG_PAIR(r3);
5478 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5479 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5480 break;
5481 case OPC2_32_RCR_MSUBS_32:
5482 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5483 break;
5484 case OPC2_32_RCR_MSUBS_64:
5485 CHECK_REG_PAIR(r4);
5486 CHECK_REG_PAIR(r3);
5487 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5488 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5489 break;
5490 case OPC2_32_RCR_MSUB_U_64:
5491 CHECK_REG_PAIR(r4);
5492 CHECK_REG_PAIR(r3);
5493 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5494 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5495 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5496 break;
5497 case OPC2_32_RCR_MSUBS_U_32:
5498 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5499 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5500 break;
5501 case OPC2_32_RCR_MSUBS_U_64:
5502 CHECK_REG_PAIR(r4);
5503 CHECK_REG_PAIR(r3);
5504 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5505 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5506 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5507 break;
5508 default:
5509 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5510 }
5511 }
5512
5513 /* RLC format */
5514
5515 static void decode_rlc_opc(DisasContext *ctx,
5516 uint32_t op1)
5517 {
5518 int32_t const16;
5519 int r1, r2;
5520
5521 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
5522 r1 = MASK_OP_RLC_S1(ctx->opcode);
5523 r2 = MASK_OP_RLC_D(ctx->opcode);
5524
5525 switch (op1) {
5526 case OPC1_32_RLC_ADDI:
5527 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
5528 break;
5529 case OPC1_32_RLC_ADDIH:
5530 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
5531 break;
5532 case OPC1_32_RLC_ADDIH_A:
5533 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
5534 break;
5535 case OPC1_32_RLC_MFCR:
5536 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5537 gen_mfcr(ctx, cpu_gpr_d[r2], const16);
5538 break;
5539 case OPC1_32_RLC_MOV:
5540 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5541 break;
5542 case OPC1_32_RLC_MOV_64:
5543 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5544 CHECK_REG_PAIR(r2);
5545 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5546 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
5547 } else {
5548 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5549 }
5550 break;
5551 case OPC1_32_RLC_MOV_U:
5552 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5553 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5554 break;
5555 case OPC1_32_RLC_MOV_H:
5556 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
5557 break;
5558 case OPC1_32_RLC_MOVH_A:
5559 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
5560 break;
5561 case OPC1_32_RLC_MTCR:
5562 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5563 gen_mtcr(ctx, cpu_gpr_d[r1], const16);
5564 break;
5565 default:
5566 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5567 }
5568 }
5569
5570 /* RR format */
5571 static void decode_rr_accumulator(DisasContext *ctx)
5572 {
5573 uint32_t op2;
5574 int r3, r2, r1;
5575
5576 TCGv temp;
5577
5578 r3 = MASK_OP_RR_D(ctx->opcode);
5579 r2 = MASK_OP_RR_S2(ctx->opcode);
5580 r1 = MASK_OP_RR_S1(ctx->opcode);
5581 op2 = MASK_OP_RR_OP2(ctx->opcode);
5582
5583 switch (op2) {
5584 case OPC2_32_RR_ABS:
5585 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5586 break;
5587 case OPC2_32_RR_ABS_B:
5588 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5589 break;
5590 case OPC2_32_RR_ABS_H:
5591 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5592 break;
5593 case OPC2_32_RR_ABSDIF:
5594 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5595 break;
5596 case OPC2_32_RR_ABSDIF_B:
5597 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5598 cpu_gpr_d[r2]);
5599 break;
5600 case OPC2_32_RR_ABSDIF_H:
5601 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5602 cpu_gpr_d[r2]);
5603 break;
5604 case OPC2_32_RR_ABSDIFS:
5605 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5606 cpu_gpr_d[r2]);
5607 break;
5608 case OPC2_32_RR_ABSDIFS_H:
5609 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5610 cpu_gpr_d[r2]);
5611 break;
5612 case OPC2_32_RR_ABSS:
5613 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5614 break;
5615 case OPC2_32_RR_ABSS_H:
5616 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5617 break;
5618 case OPC2_32_RR_ADD:
5619 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5620 break;
5621 case OPC2_32_RR_ADD_B:
5622 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5623 break;
5624 case OPC2_32_RR_ADD_H:
5625 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5626 break;
5627 case OPC2_32_RR_ADDC:
5628 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5629 break;
5630 case OPC2_32_RR_ADDS:
5631 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5632 break;
5633 case OPC2_32_RR_ADDS_H:
5634 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5635 cpu_gpr_d[r2]);
5636 break;
5637 case OPC2_32_RR_ADDS_HU:
5638 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5639 cpu_gpr_d[r2]);
5640 break;
5641 case OPC2_32_RR_ADDS_U:
5642 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5643 cpu_gpr_d[r2]);
5644 break;
5645 case OPC2_32_RR_ADDX:
5646 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5647 break;
5648 case OPC2_32_RR_AND_EQ:
5649 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5650 cpu_gpr_d[r2], &tcg_gen_and_tl);
5651 break;
5652 case OPC2_32_RR_AND_GE:
5653 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5654 cpu_gpr_d[r2], &tcg_gen_and_tl);
5655 break;
5656 case OPC2_32_RR_AND_GE_U:
5657 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5658 cpu_gpr_d[r2], &tcg_gen_and_tl);
5659 break;
5660 case OPC2_32_RR_AND_LT:
5661 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5662 cpu_gpr_d[r2], &tcg_gen_and_tl);
5663 break;
5664 case OPC2_32_RR_AND_LT_U:
5665 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5666 cpu_gpr_d[r2], &tcg_gen_and_tl);
5667 break;
5668 case OPC2_32_RR_AND_NE:
5669 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5670 cpu_gpr_d[r2], &tcg_gen_and_tl);
5671 break;
5672 case OPC2_32_RR_EQ:
5673 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5674 cpu_gpr_d[r2]);
5675 break;
5676 case OPC2_32_RR_EQ_B:
5677 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5678 break;
5679 case OPC2_32_RR_EQ_H:
5680 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5681 break;
5682 case OPC2_32_RR_EQ_W:
5683 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5684 break;
5685 case OPC2_32_RR_EQANY_B:
5686 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5687 break;
5688 case OPC2_32_RR_EQANY_H:
5689 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5690 break;
5691 case OPC2_32_RR_GE:
5692 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5693 cpu_gpr_d[r2]);
5694 break;
5695 case OPC2_32_RR_GE_U:
5696 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5697 cpu_gpr_d[r2]);
5698 break;
5699 case OPC2_32_RR_LT:
5700 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5701 cpu_gpr_d[r2]);
5702 break;
5703 case OPC2_32_RR_LT_U:
5704 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5705 cpu_gpr_d[r2]);
5706 break;
5707 case OPC2_32_RR_LT_B:
5708 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5709 break;
5710 case OPC2_32_RR_LT_BU:
5711 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5712 break;
5713 case OPC2_32_RR_LT_H:
5714 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5715 break;
5716 case OPC2_32_RR_LT_HU:
5717 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5718 break;
5719 case OPC2_32_RR_LT_W:
5720 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5721 break;
5722 case OPC2_32_RR_LT_WU:
5723 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5724 break;
5725 case OPC2_32_RR_MAX:
5726 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5727 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5728 break;
5729 case OPC2_32_RR_MAX_U:
5730 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5731 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5732 break;
5733 case OPC2_32_RR_MAX_B:
5734 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5735 break;
5736 case OPC2_32_RR_MAX_BU:
5737 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5738 break;
5739 case OPC2_32_RR_MAX_H:
5740 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5741 break;
5742 case OPC2_32_RR_MAX_HU:
5743 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5744 break;
5745 case OPC2_32_RR_MIN:
5746 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5747 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5748 break;
5749 case OPC2_32_RR_MIN_U:
5750 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5751 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5752 break;
5753 case OPC2_32_RR_MIN_B:
5754 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5755 break;
5756 case OPC2_32_RR_MIN_BU:
5757 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5758 break;
5759 case OPC2_32_RR_MIN_H:
5760 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5761 break;
5762 case OPC2_32_RR_MIN_HU:
5763 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5764 break;
5765 case OPC2_32_RR_MOV:
5766 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5767 break;
5768 case OPC2_32_RR_MOV_64:
5769 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5770 temp = tcg_temp_new();
5771
5772 CHECK_REG_PAIR(r3);
5773 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
5774 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5775 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
5776 } else {
5777 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5778 }
5779 break;
5780 case OPC2_32_RR_MOVS_64:
5781 if (has_feature(ctx, TRICORE_FEATURE_16)) {
5782 CHECK_REG_PAIR(r3);
5783 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5784 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31);
5785 } else {
5786 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5787 }
5788 break;
5789 case OPC2_32_RR_NE:
5790 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5791 cpu_gpr_d[r2]);
5792 break;
5793 case OPC2_32_RR_OR_EQ:
5794 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5795 cpu_gpr_d[r2], &tcg_gen_or_tl);
5796 break;
5797 case OPC2_32_RR_OR_GE:
5798 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5799 cpu_gpr_d[r2], &tcg_gen_or_tl);
5800 break;
5801 case OPC2_32_RR_OR_GE_U:
5802 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5803 cpu_gpr_d[r2], &tcg_gen_or_tl);
5804 break;
5805 case OPC2_32_RR_OR_LT:
5806 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5807 cpu_gpr_d[r2], &tcg_gen_or_tl);
5808 break;
5809 case OPC2_32_RR_OR_LT_U:
5810 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5811 cpu_gpr_d[r2], &tcg_gen_or_tl);
5812 break;
5813 case OPC2_32_RR_OR_NE:
5814 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5815 cpu_gpr_d[r2], &tcg_gen_or_tl);
5816 break;
5817 case OPC2_32_RR_SAT_B:
5818 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
5819 break;
5820 case OPC2_32_RR_SAT_BU:
5821 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
5822 break;
5823 case OPC2_32_RR_SAT_H:
5824 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
5825 break;
5826 case OPC2_32_RR_SAT_HU:
5827 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
5828 break;
5829 case OPC2_32_RR_SH_EQ:
5830 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5831 cpu_gpr_d[r2]);
5832 break;
5833 case OPC2_32_RR_SH_GE:
5834 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5835 cpu_gpr_d[r2]);
5836 break;
5837 case OPC2_32_RR_SH_GE_U:
5838 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5839 cpu_gpr_d[r2]);
5840 break;
5841 case OPC2_32_RR_SH_LT:
5842 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5843 cpu_gpr_d[r2]);
5844 break;
5845 case OPC2_32_RR_SH_LT_U:
5846 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5847 cpu_gpr_d[r2]);
5848 break;
5849 case OPC2_32_RR_SH_NE:
5850 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5851 cpu_gpr_d[r2]);
5852 break;
5853 case OPC2_32_RR_SUB:
5854 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5855 break;
5856 case OPC2_32_RR_SUB_B:
5857 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5858 break;
5859 case OPC2_32_RR_SUB_H:
5860 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5861 break;
5862 case OPC2_32_RR_SUBC:
5863 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5864 break;
5865 case OPC2_32_RR_SUBS:
5866 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5867 break;
5868 case OPC2_32_RR_SUBS_U:
5869 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5870 break;
5871 case OPC2_32_RR_SUBS_H:
5872 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5873 cpu_gpr_d[r2]);
5874 break;
5875 case OPC2_32_RR_SUBS_HU:
5876 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5877 cpu_gpr_d[r2]);
5878 break;
5879 case OPC2_32_RR_SUBX:
5880 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5881 break;
5882 case OPC2_32_RR_XOR_EQ:
5883 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5884 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5885 break;
5886 case OPC2_32_RR_XOR_GE:
5887 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5888 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5889 break;
5890 case OPC2_32_RR_XOR_GE_U:
5891 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5892 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5893 break;
5894 case OPC2_32_RR_XOR_LT:
5895 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5896 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5897 break;
5898 case OPC2_32_RR_XOR_LT_U:
5899 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5900 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5901 break;
5902 case OPC2_32_RR_XOR_NE:
5903 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5904 cpu_gpr_d[r2], &tcg_gen_xor_tl);
5905 break;
5906 default:
5907 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5908 }
5909 }
5910
5911 static void decode_rr_logical_shift(DisasContext *ctx)
5912 {
5913 uint32_t op2;
5914 int r3, r2, r1;
5915
5916 r3 = MASK_OP_RR_D(ctx->opcode);
5917 r2 = MASK_OP_RR_S2(ctx->opcode);
5918 r1 = MASK_OP_RR_S1(ctx->opcode);
5919 op2 = MASK_OP_RR_OP2(ctx->opcode);
5920
5921 switch (op2) {
5922 case OPC2_32_RR_AND:
5923 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5924 break;
5925 case OPC2_32_RR_ANDN:
5926 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5927 break;
5928 case OPC2_32_RR_CLO:
5929 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5930 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
5931 break;
5932 case OPC2_32_RR_CLO_H:
5933 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5934 break;
5935 case OPC2_32_RR_CLS:
5936 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5937 break;
5938 case OPC2_32_RR_CLS_H:
5939 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5940 break;
5941 case OPC2_32_RR_CLZ:
5942 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
5943 break;
5944 case OPC2_32_RR_CLZ_H:
5945 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
5946 break;
5947 case OPC2_32_RR_NAND:
5948 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5949 break;
5950 case OPC2_32_RR_NOR:
5951 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5952 break;
5953 case OPC2_32_RR_OR:
5954 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5955 break;
5956 case OPC2_32_RR_ORN:
5957 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5958 break;
5959 case OPC2_32_RR_SH:
5960 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5961 break;
5962 case OPC2_32_RR_SH_H:
5963 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5964 break;
5965 case OPC2_32_RR_SHA:
5966 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5967 break;
5968 case OPC2_32_RR_SHA_H:
5969 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5970 break;
5971 case OPC2_32_RR_SHAS:
5972 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5973 break;
5974 case OPC2_32_RR_XNOR:
5975 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5976 break;
5977 case OPC2_32_RR_XOR:
5978 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5979 break;
5980 default:
5981 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
5982 }
5983 }
5984
5985 static void decode_rr_address(DisasContext *ctx)
5986 {
5987 uint32_t op2, n;
5988 int r1, r2, r3;
5989 TCGv temp;
5990
5991 op2 = MASK_OP_RR_OP2(ctx->opcode);
5992 r3 = MASK_OP_RR_D(ctx->opcode);
5993 r2 = MASK_OP_RR_S2(ctx->opcode);
5994 r1 = MASK_OP_RR_S1(ctx->opcode);
5995 n = MASK_OP_RR_N(ctx->opcode);
5996
5997 switch (op2) {
5998 case OPC2_32_RR_ADD_A:
5999 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6000 break;
6001 case OPC2_32_RR_ADDSC_A:
6002 temp = tcg_temp_new();
6003 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
6004 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
6005 break;
6006 case OPC2_32_RR_ADDSC_AT:
6007 temp = tcg_temp_new();
6008 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
6009 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
6010 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
6011 break;
6012 case OPC2_32_RR_EQ_A:
6013 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
6014 cpu_gpr_a[r2]);
6015 break;
6016 case OPC2_32_RR_EQZ:
6017 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6018 break;
6019 case OPC2_32_RR_GE_A:
6020 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6021 cpu_gpr_a[r2]);
6022 break;
6023 case OPC2_32_RR_LT_A:
6024 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6025 cpu_gpr_a[r2]);
6026 break;
6027 case OPC2_32_RR_MOV_A:
6028 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
6029 break;
6030 case OPC2_32_RR_MOV_AA:
6031 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
6032 break;
6033 case OPC2_32_RR_MOV_D:
6034 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
6035 break;
6036 case OPC2_32_RR_NE_A:
6037 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
6038 cpu_gpr_a[r2]);
6039 break;
6040 case OPC2_32_RR_NEZ_A:
6041 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6042 break;
6043 case OPC2_32_RR_SUB_A:
6044 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6045 break;
6046 default:
6047 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6048 }
6049 }
6050
6051 static void decode_rr_idirect(DisasContext *ctx)
6052 {
6053 uint32_t op2;
6054 int r1;
6055
6056 op2 = MASK_OP_RR_OP2(ctx->opcode);
6057 r1 = MASK_OP_RR_S1(ctx->opcode);
6058
6059 switch (op2) {
6060 case OPC2_32_RR_JI:
6061 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6062 break;
6063 case OPC2_32_RR_JLI:
6064 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn);
6065 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6066 break;
6067 case OPC2_32_RR_CALLI:
6068 gen_helper_1arg(call, ctx->pc_succ_insn);
6069 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6070 break;
6071 case OPC2_32_RR_FCALLI:
6072 gen_fcall_save_ctx(ctx);
6073 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6074 break;
6075 default:
6076 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6077 }
6078 tcg_gen_exit_tb(NULL, 0);
6079 ctx->base.is_jmp = DISAS_NORETURN;
6080 }
6081
6082 static void decode_rr_divide(DisasContext *ctx)
6083 {
6084 uint32_t op2;
6085 int r1, r2, r3;
6086
6087 TCGv temp, temp2, temp3;
6088
6089 op2 = MASK_OP_RR_OP2(ctx->opcode);
6090 r3 = MASK_OP_RR_D(ctx->opcode);
6091 r2 = MASK_OP_RR_S2(ctx->opcode);
6092 r1 = MASK_OP_RR_S1(ctx->opcode);
6093
6094 switch (op2) {
6095 case OPC2_32_RR_BMERGE:
6096 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6097 break;
6098 case OPC2_32_RR_BSPLIT:
6099 CHECK_REG_PAIR(r3);
6100 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6101 break;
6102 case OPC2_32_RR_DVINIT_B:
6103 CHECK_REG_PAIR(r3);
6104 gen_dvinit_b(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6105 cpu_gpr_d[r2]);
6106 break;
6107 case OPC2_32_RR_DVINIT_BU:
6108 temp = tcg_temp_new();
6109 temp2 = tcg_temp_new();
6110 temp3 = tcg_temp_new();
6111 CHECK_REG_PAIR(r3);
6112 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
6113 /* reset av */
6114 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6115 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
6116 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6117 tcg_gen_abs_tl(temp, temp3);
6118 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
6119 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6120 } else {
6121 /* overflow = (D[b] == 0) */
6122 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6123 }
6124 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6125 /* sv */
6126 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6127 /* write result */
6128 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
6129 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6130 break;
6131 case OPC2_32_RR_DVINIT_H:
6132 CHECK_REG_PAIR(r3);
6133 gen_dvinit_h(ctx, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6134 cpu_gpr_d[r2]);
6135 break;
6136 case OPC2_32_RR_DVINIT_HU:
6137 temp = tcg_temp_new();
6138 temp2 = tcg_temp_new();
6139 temp3 = tcg_temp_new();
6140 CHECK_REG_PAIR(r3);
6141 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
6142 /* reset av */
6143 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6144 if (!has_feature(ctx, TRICORE_FEATURE_131)) {
6145 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6146 tcg_gen_abs_tl(temp, temp3);
6147 tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
6148 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6149 } else {
6150 /* overflow = (D[b] == 0) */
6151 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6152 }
6153 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6154 /* sv */
6155 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6156 /* write result */
6157 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
6158 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6159 break;
6160 case OPC2_32_RR_DVINIT:
6161 temp = tcg_temp_new();
6162 temp2 = tcg_temp_new();
6163 CHECK_REG_PAIR(r3);
6164 /* overflow = ((D[b] == 0) ||
6165 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6166 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
6167 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
6168 tcg_gen_and_tl(temp, temp, temp2);
6169 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
6170 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
6171 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6172 /* sv */
6173 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6174 /* reset av */
6175 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6176 /* write result */
6177 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6178 /* sign extend to high reg */
6179 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
6180 break;
6181 case OPC2_32_RR_DVINIT_U:
6182 /* overflow = (D[b] == 0) */
6183 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6184 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6185 /* sv */
6186 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6187 /* reset av */
6188 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6189 /* write result */
6190 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6191 /* zero extend to high reg*/
6192 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
6193 break;
6194 case OPC2_32_RR_PARITY:
6195 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6196 break;
6197 case OPC2_32_RR_UNPACK:
6198 CHECK_REG_PAIR(r3);
6199 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6200 break;
6201 case OPC2_32_RR_CRC32:
6202 if (has_feature(ctx, TRICORE_FEATURE_161)) {
6203 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6204 } else {
6205 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6206 }
6207 break;
6208 case OPC2_32_RR_DIV:
6209 if (has_feature(ctx, TRICORE_FEATURE_16)) {
6210 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6211 cpu_gpr_d[r2]);
6212 } else {
6213 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6214 }
6215 break;
6216 case OPC2_32_RR_DIV_U:
6217 if (has_feature(ctx, TRICORE_FEATURE_16)) {
6218 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1],
6219 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6220 } else {
6221 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6222 }
6223 break;
6224 case OPC2_32_RR_MUL_F:
6225 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6226 break;
6227 case OPC2_32_RR_DIV_F:
6228 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6229 break;
6230 case OPC2_32_RR_CMP_F:
6231 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6232 break;
6233 case OPC2_32_RR_FTOI:
6234 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6235 break;
6236 case OPC2_32_RR_ITOF:
6237 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6238 break;
6239 case OPC2_32_RR_FTOUZ:
6240 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6241 break;
6242 case OPC2_32_RR_UPDFL:
6243 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
6244 break;
6245 case OPC2_32_RR_UTOF:
6246 gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6247 break;
6248 case OPC2_32_RR_FTOIZ:
6249 gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6250 break;
6251 case OPC2_32_RR_QSEED_F:
6252 gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
6253 break;
6254 default:
6255 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6256 }
6257 }
6258
6259 /* RR1 Format */
6260 static void decode_rr1_mul(DisasContext *ctx)
6261 {
6262 uint32_t op2;
6263
6264 int r1, r2, r3;
6265 TCGv n;
6266 TCGv_i64 temp64;
6267
6268 r1 = MASK_OP_RR1_S1(ctx->opcode);
6269 r2 = MASK_OP_RR1_S2(ctx->opcode);
6270 r3 = MASK_OP_RR1_D(ctx->opcode);
6271 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
6272 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6273
6274 switch (op2) {
6275 case OPC2_32_RR1_MUL_H_32_LL:
6276 temp64 = tcg_temp_new_i64();
6277 CHECK_REG_PAIR(r3);
6278 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6279 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6280 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6281 break;
6282 case OPC2_32_RR1_MUL_H_32_LU:
6283 temp64 = tcg_temp_new_i64();
6284 CHECK_REG_PAIR(r3);
6285 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6286 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6287 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6288 break;
6289 case OPC2_32_RR1_MUL_H_32_UL:
6290 temp64 = tcg_temp_new_i64();
6291 CHECK_REG_PAIR(r3);
6292 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6293 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6294 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6295 break;
6296 case OPC2_32_RR1_MUL_H_32_UU:
6297 temp64 = tcg_temp_new_i64();
6298 CHECK_REG_PAIR(r3);
6299 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6300 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6301 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6302 break;
6303 case OPC2_32_RR1_MULM_H_64_LL:
6304 temp64 = tcg_temp_new_i64();
6305 CHECK_REG_PAIR(r3);
6306 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6307 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6308 /* reset V bit */
6309 tcg_gen_movi_tl(cpu_PSW_V, 0);
6310 /* reset AV bit */
6311 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6312 break;
6313 case OPC2_32_RR1_MULM_H_64_LU:
6314 temp64 = tcg_temp_new_i64();
6315 CHECK_REG_PAIR(r3);
6316 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6317 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6318 /* reset V bit */
6319 tcg_gen_movi_tl(cpu_PSW_V, 0);
6320 /* reset AV bit */
6321 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6322 break;
6323 case OPC2_32_RR1_MULM_H_64_UL:
6324 temp64 = tcg_temp_new_i64();
6325 CHECK_REG_PAIR(r3);
6326 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6327 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6328 /* reset V bit */
6329 tcg_gen_movi_tl(cpu_PSW_V, 0);
6330 /* reset AV bit */
6331 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6332 break;
6333 case OPC2_32_RR1_MULM_H_64_UU:
6334 temp64 = tcg_temp_new_i64();
6335 CHECK_REG_PAIR(r3);
6336 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6337 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6338 /* reset V bit */
6339 tcg_gen_movi_tl(cpu_PSW_V, 0);
6340 /* reset AV bit */
6341 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6342 break;
6343 case OPC2_32_RR1_MULR_H_16_LL:
6344 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6345 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6346 break;
6347 case OPC2_32_RR1_MULR_H_16_LU:
6348 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6349 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6350 break;
6351 case OPC2_32_RR1_MULR_H_16_UL:
6352 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6353 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6354 break;
6355 case OPC2_32_RR1_MULR_H_16_UU:
6356 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6357 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6358 break;
6359 default:
6360 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6361 }
6362 }
6363
6364 static void decode_rr1_mulq(DisasContext *ctx)
6365 {
6366 uint32_t op2;
6367 int r1, r2, r3;
6368 uint32_t n;
6369
6370 TCGv temp, temp2;
6371
6372 r1 = MASK_OP_RR1_S1(ctx->opcode);
6373 r2 = MASK_OP_RR1_S2(ctx->opcode);
6374 r3 = MASK_OP_RR1_D(ctx->opcode);
6375 n = MASK_OP_RR1_N(ctx->opcode);
6376 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6377
6378 temp = tcg_temp_new();
6379 temp2 = tcg_temp_new();
6380
6381 switch (op2) {
6382 case OPC2_32_RR1_MUL_Q_32:
6383 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
6384 break;
6385 case OPC2_32_RR1_MUL_Q_64:
6386 CHECK_REG_PAIR(r3);
6387 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6388 n, 0);
6389 break;
6390 case OPC2_32_RR1_MUL_Q_32_L:
6391 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6392 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6393 break;
6394 case OPC2_32_RR1_MUL_Q_64_L:
6395 CHECK_REG_PAIR(r3);
6396 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6397 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6398 break;
6399 case OPC2_32_RR1_MUL_Q_32_U:
6400 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6401 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6402 break;
6403 case OPC2_32_RR1_MUL_Q_64_U:
6404 CHECK_REG_PAIR(r3);
6405 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6406 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6407 break;
6408 case OPC2_32_RR1_MUL_Q_32_LL:
6409 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6410 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6411 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6412 break;
6413 case OPC2_32_RR1_MUL_Q_32_UU:
6414 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6415 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6416 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6417 break;
6418 case OPC2_32_RR1_MULR_Q_32_L:
6419 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6420 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6421 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6422 break;
6423 case OPC2_32_RR1_MULR_Q_32_U:
6424 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6425 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6426 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6427 break;
6428 default:
6429 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6430 }
6431 }
6432
6433 /* RR2 format */
6434 static void decode_rr2_mul(DisasContext *ctx)
6435 {
6436 uint32_t op2;
6437 int r1, r2, r3;
6438
6439 op2 = MASK_OP_RR2_OP2(ctx->opcode);
6440 r1 = MASK_OP_RR2_S1(ctx->opcode);
6441 r2 = MASK_OP_RR2_S2(ctx->opcode);
6442 r3 = MASK_OP_RR2_D(ctx->opcode);
6443 switch (op2) {
6444 case OPC2_32_RR2_MUL_32:
6445 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6446 break;
6447 case OPC2_32_RR2_MUL_64:
6448 CHECK_REG_PAIR(r3);
6449 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6450 cpu_gpr_d[r2]);
6451 break;
6452 case OPC2_32_RR2_MULS_32:
6453 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6454 cpu_gpr_d[r2]);
6455 break;
6456 case OPC2_32_RR2_MUL_U_64:
6457 CHECK_REG_PAIR(r3);
6458 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6459 cpu_gpr_d[r2]);
6460 break;
6461 case OPC2_32_RR2_MULS_U_32:
6462 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6463 cpu_gpr_d[r2]);
6464 break;
6465 default:
6466 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6467 }
6468 }
6469
6470 /* RRPW format */
6471 static void decode_rrpw_extract_insert(DisasContext *ctx)
6472 {
6473 uint32_t op2;
6474 int r1, r2, r3;
6475 int32_t pos, width;
6476 TCGv temp;
6477
6478 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
6479 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6480 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6481 r3 = MASK_OP_RRPW_D(ctx->opcode);
6482 pos = MASK_OP_RRPW_POS(ctx->opcode);
6483 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
6484
6485 switch (op2) {
6486 case OPC2_32_RRPW_EXTR:
6487 if (width == 0) {
6488 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6489 break;
6490 }
6491
6492 if (pos + width <= 32) {
6493 /* optimize special cases */
6494 if ((pos == 0) && (width == 8)) {
6495 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6496 } else if ((pos == 0) && (width == 16)) {
6497 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6498 } else {
6499 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
6500 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
6501 }
6502 }
6503 break;
6504 case OPC2_32_RRPW_EXTR_U:
6505 if (width == 0) {
6506 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6507 } else {
6508 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
6509 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
6510 }
6511 break;
6512 case OPC2_32_RRPW_IMASK:
6513 CHECK_REG_PAIR(r3);
6514
6515 if (pos + width <= 32) {
6516 temp = tcg_temp_new();
6517 tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos);
6518 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
6519 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
6520 }
6521
6522 break;
6523 case OPC2_32_RRPW_INSERT:
6524 if (pos + width <= 32) {
6525 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
6526 pos, width);
6527 }
6528 break;
6529 default:
6530 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6531 }
6532 }
6533
6534 /* RRR format */
6535 static void decode_rrr_cond_select(DisasContext *ctx)
6536 {
6537 uint32_t op2;
6538 int r1, r2, r3, r4;
6539 TCGv temp;
6540
6541 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6542 r1 = MASK_OP_RRR_S1(ctx->opcode);
6543 r2 = MASK_OP_RRR_S2(ctx->opcode);
6544 r3 = MASK_OP_RRR_S3(ctx->opcode);
6545 r4 = MASK_OP_RRR_D(ctx->opcode);
6546
6547 switch (op2) {
6548 case OPC2_32_RRR_CADD:
6549 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
6550 cpu_gpr_d[r4], cpu_gpr_d[r3]);
6551 break;
6552 case OPC2_32_RRR_CADDN:
6553 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6554 cpu_gpr_d[r3]);
6555 break;
6556 case OPC2_32_RRR_CSUB:
6557 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6558 cpu_gpr_d[r3]);
6559 break;
6560 case OPC2_32_RRR_CSUBN:
6561 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6562 cpu_gpr_d[r3]);
6563 break;
6564 case OPC2_32_RRR_SEL:
6565 temp = tcg_const_i32(0);
6566 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6567 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6568 break;
6569 case OPC2_32_RRR_SELN:
6570 temp = tcg_const_i32(0);
6571 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6572 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6573 break;
6574 default:
6575 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6576 }
6577 }
6578
6579 static void decode_rrr_divide(DisasContext *ctx)
6580 {
6581 uint32_t op2;
6582
6583 int r1, r2, r3, r4;
6584
6585 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6586 r1 = MASK_OP_RRR_S1(ctx->opcode);
6587 r2 = MASK_OP_RRR_S2(ctx->opcode);
6588 r3 = MASK_OP_RRR_S3(ctx->opcode);
6589 r4 = MASK_OP_RRR_D(ctx->opcode);
6590
6591 switch (op2) {
6592 case OPC2_32_RRR_DVADJ:
6593 CHECK_REG_PAIR(r3);
6594 CHECK_REG_PAIR(r4);
6595 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6596 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6597 break;
6598 case OPC2_32_RRR_DVSTEP:
6599 CHECK_REG_PAIR(r3);
6600 CHECK_REG_PAIR(r4);
6601 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6602 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6603 break;
6604 case OPC2_32_RRR_DVSTEP_U:
6605 CHECK_REG_PAIR(r3);
6606 CHECK_REG_PAIR(r4);
6607 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6608 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6609 break;
6610 case OPC2_32_RRR_IXMAX:
6611 CHECK_REG_PAIR(r3);
6612 CHECK_REG_PAIR(r4);
6613 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6614 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6615 break;
6616 case OPC2_32_RRR_IXMAX_U:
6617 CHECK_REG_PAIR(r3);
6618 CHECK_REG_PAIR(r4);
6619 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6620 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6621 break;
6622 case OPC2_32_RRR_IXMIN:
6623 CHECK_REG_PAIR(r3);
6624 CHECK_REG_PAIR(r4);
6625 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6626 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6627 break;
6628 case OPC2_32_RRR_IXMIN_U:
6629 CHECK_REG_PAIR(r3);
6630 CHECK_REG_PAIR(r4);
6631 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6632 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6633 break;
6634 case OPC2_32_RRR_PACK:
6635 CHECK_REG_PAIR(r3);
6636 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
6637 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6638 break;
6639 case OPC2_32_RRR_ADD_F:
6640 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
6641 break;
6642 case OPC2_32_RRR_SUB_F:
6643 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
6644 break;
6645 case OPC2_32_RRR_MADD_F:
6646 gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6647 cpu_gpr_d[r2], cpu_gpr_d[r3]);
6648 break;
6649 case OPC2_32_RRR_MSUB_F:
6650 gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6651 cpu_gpr_d[r2], cpu_gpr_d[r3]);
6652 break;
6653 default:
6654 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6655 }
6656 }
6657
6658 /* RRR2 format */
6659 static void decode_rrr2_madd(DisasContext *ctx)
6660 {
6661 uint32_t op2;
6662 uint32_t r1, r2, r3, r4;
6663
6664 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6665 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6666 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6667 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6668 r4 = MASK_OP_RRR2_D(ctx->opcode);
6669 switch (op2) {
6670 case OPC2_32_RRR2_MADD_32:
6671 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6672 cpu_gpr_d[r2]);
6673 break;
6674 case OPC2_32_RRR2_MADD_64:
6675 CHECK_REG_PAIR(r4);
6676 CHECK_REG_PAIR(r3);
6677 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6678 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6679 break;
6680 case OPC2_32_RRR2_MADDS_32:
6681 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6682 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6683 break;
6684 case OPC2_32_RRR2_MADDS_64:
6685 CHECK_REG_PAIR(r4);
6686 CHECK_REG_PAIR(r3);
6687 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6688 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6689 break;
6690 case OPC2_32_RRR2_MADD_U_64:
6691 CHECK_REG_PAIR(r4);
6692 CHECK_REG_PAIR(r3);
6693 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6694 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6695 break;
6696 case OPC2_32_RRR2_MADDS_U_32:
6697 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6698 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6699 break;
6700 case OPC2_32_RRR2_MADDS_U_64:
6701 CHECK_REG_PAIR(r4);
6702 CHECK_REG_PAIR(r3);
6703 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6704 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6705 break;
6706 default:
6707 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6708 }
6709 }
6710
6711 static void decode_rrr2_msub(DisasContext *ctx)
6712 {
6713 uint32_t op2;
6714 uint32_t r1, r2, r3, r4;
6715
6716 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6717 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6718 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6719 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6720 r4 = MASK_OP_RRR2_D(ctx->opcode);
6721
6722 switch (op2) {
6723 case OPC2_32_RRR2_MSUB_32:
6724 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6725 cpu_gpr_d[r2]);
6726 break;
6727 case OPC2_32_RRR2_MSUB_64:
6728 CHECK_REG_PAIR(r4);
6729 CHECK_REG_PAIR(r3);
6730 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6731 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6732 break;
6733 case OPC2_32_RRR2_MSUBS_32:
6734 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6735 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6736 break;
6737 case OPC2_32_RRR2_MSUBS_64:
6738 CHECK_REG_PAIR(r4);
6739 CHECK_REG_PAIR(r3);
6740 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6741 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6742 break;
6743 case OPC2_32_RRR2_MSUB_U_64:
6744 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6745 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6746 break;
6747 case OPC2_32_RRR2_MSUBS_U_32:
6748 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6749 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6750 break;
6751 case OPC2_32_RRR2_MSUBS_U_64:
6752 CHECK_REG_PAIR(r4);
6753 CHECK_REG_PAIR(r3);
6754 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6755 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6756 break;
6757 default:
6758 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6759 }
6760 }
6761
6762 /* RRR1 format */
6763 static void decode_rrr1_madd(DisasContext *ctx)
6764 {
6765 uint32_t op2;
6766 uint32_t r1, r2, r3, r4, n;
6767
6768 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6769 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6770 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6771 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6772 r4 = MASK_OP_RRR1_D(ctx->opcode);
6773 n = MASK_OP_RRR1_N(ctx->opcode);
6774
6775 switch (op2) {
6776 case OPC2_32_RRR1_MADD_H_LL:
6777 CHECK_REG_PAIR(r4);
6778 CHECK_REG_PAIR(r3);
6779 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6780 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6781 break;
6782 case OPC2_32_RRR1_MADD_H_LU:
6783 CHECK_REG_PAIR(r4);
6784 CHECK_REG_PAIR(r3);
6785 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6786 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6787 break;
6788 case OPC2_32_RRR1_MADD_H_UL:
6789 CHECK_REG_PAIR(r4);
6790 CHECK_REG_PAIR(r3);
6791 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6792 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6793 break;
6794 case OPC2_32_RRR1_MADD_H_UU:
6795 CHECK_REG_PAIR(r4);
6796 CHECK_REG_PAIR(r3);
6797 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6798 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6799 break;
6800 case OPC2_32_RRR1_MADDS_H_LL:
6801 CHECK_REG_PAIR(r4);
6802 CHECK_REG_PAIR(r3);
6803 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6804 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6805 break;
6806 case OPC2_32_RRR1_MADDS_H_LU:
6807 CHECK_REG_PAIR(r4);
6808 CHECK_REG_PAIR(r3);
6809 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6810 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6811 break;
6812 case OPC2_32_RRR1_MADDS_H_UL:
6813 CHECK_REG_PAIR(r4);
6814 CHECK_REG_PAIR(r3);
6815 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6816 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6817 break;
6818 case OPC2_32_RRR1_MADDS_H_UU:
6819 CHECK_REG_PAIR(r4);
6820 CHECK_REG_PAIR(r3);
6821 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6822 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6823 break;
6824 case OPC2_32_RRR1_MADDM_H_LL:
6825 CHECK_REG_PAIR(r4);
6826 CHECK_REG_PAIR(r3);
6827 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6828 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6829 break;
6830 case OPC2_32_RRR1_MADDM_H_LU:
6831 CHECK_REG_PAIR(r4);
6832 CHECK_REG_PAIR(r3);
6833 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6834 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6835 break;
6836 case OPC2_32_RRR1_MADDM_H_UL:
6837 CHECK_REG_PAIR(r4);
6838 CHECK_REG_PAIR(r3);
6839 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6840 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6841 break;
6842 case OPC2_32_RRR1_MADDM_H_UU:
6843 CHECK_REG_PAIR(r4);
6844 CHECK_REG_PAIR(r3);
6845 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6846 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6847 break;
6848 case OPC2_32_RRR1_MADDMS_H_LL:
6849 CHECK_REG_PAIR(r4);
6850 CHECK_REG_PAIR(r3);
6851 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6852 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6853 break;
6854 case OPC2_32_RRR1_MADDMS_H_LU:
6855 CHECK_REG_PAIR(r4);
6856 CHECK_REG_PAIR(r3);
6857 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6858 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6859 break;
6860 case OPC2_32_RRR1_MADDMS_H_UL:
6861 CHECK_REG_PAIR(r4);
6862 CHECK_REG_PAIR(r3);
6863 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6864 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6865 break;
6866 case OPC2_32_RRR1_MADDMS_H_UU:
6867 CHECK_REG_PAIR(r4);
6868 CHECK_REG_PAIR(r3);
6869 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6870 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6871 break;
6872 case OPC2_32_RRR1_MADDR_H_LL:
6873 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6874 cpu_gpr_d[r2], n, MODE_LL);
6875 break;
6876 case OPC2_32_RRR1_MADDR_H_LU:
6877 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6878 cpu_gpr_d[r2], n, MODE_LU);
6879 break;
6880 case OPC2_32_RRR1_MADDR_H_UL:
6881 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6882 cpu_gpr_d[r2], n, MODE_UL);
6883 break;
6884 case OPC2_32_RRR1_MADDR_H_UU:
6885 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6886 cpu_gpr_d[r2], n, MODE_UU);
6887 break;
6888 case OPC2_32_RRR1_MADDRS_H_LL:
6889 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6890 cpu_gpr_d[r2], n, MODE_LL);
6891 break;
6892 case OPC2_32_RRR1_MADDRS_H_LU:
6893 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6894 cpu_gpr_d[r2], n, MODE_LU);
6895 break;
6896 case OPC2_32_RRR1_MADDRS_H_UL:
6897 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6898 cpu_gpr_d[r2], n, MODE_UL);
6899 break;
6900 case OPC2_32_RRR1_MADDRS_H_UU:
6901 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6902 cpu_gpr_d[r2], n, MODE_UU);
6903 break;
6904 default:
6905 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
6906 }
6907 }
6908
6909 static void decode_rrr1_maddq_h(DisasContext *ctx)
6910 {
6911 uint32_t op2;
6912 uint32_t r1, r2, r3, r4, n;
6913 TCGv temp, temp2;
6914
6915 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6916 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6917 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6918 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6919 r4 = MASK_OP_RRR1_D(ctx->opcode);
6920 n = MASK_OP_RRR1_N(ctx->opcode);
6921
6922 temp = tcg_const_i32(n);
6923 temp2 = tcg_temp_new();
6924
6925 switch (op2) {
6926 case OPC2_32_RRR1_MADD_Q_32:
6927 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6928 cpu_gpr_d[r2], n, 32);
6929 break;
6930 case OPC2_32_RRR1_MADD_Q_64:
6931 CHECK_REG_PAIR(r4);
6932 CHECK_REG_PAIR(r3);
6933 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6934 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6935 n);
6936 break;
6937 case OPC2_32_RRR1_MADD_Q_32_L:
6938 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6939 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6940 temp, n, 16);
6941 break;
6942 case OPC2_32_RRR1_MADD_Q_64_L:
6943 CHECK_REG_PAIR(r4);
6944 CHECK_REG_PAIR(r3);
6945 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6946 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6947 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6948 n);
6949 break;
6950 case OPC2_32_RRR1_MADD_Q_32_U:
6951 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6952 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6953 temp, n, 16);
6954 break;
6955 case OPC2_32_RRR1_MADD_Q_64_U:
6956 CHECK_REG_PAIR(r4);
6957 CHECK_REG_PAIR(r3);
6958 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6959 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6960 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
6961 n);
6962 break;
6963 case OPC2_32_RRR1_MADD_Q_32_LL:
6964 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6965 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6966 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6967 break;
6968 case OPC2_32_RRR1_MADD_Q_64_LL:
6969 CHECK_REG_PAIR(r4);
6970 CHECK_REG_PAIR(r3);
6971 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6972 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6973 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6974 cpu_gpr_d[r3+1], temp, temp2, n);
6975 break;
6976 case OPC2_32_RRR1_MADD_Q_32_UU:
6977 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6978 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6979 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
6980 break;
6981 case OPC2_32_RRR1_MADD_Q_64_UU:
6982 CHECK_REG_PAIR(r4);
6983 CHECK_REG_PAIR(r3);
6984 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6985 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6986 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6987 cpu_gpr_d[r3+1], temp, temp2, n);
6988 break;
6989 case OPC2_32_RRR1_MADDS_Q_32:
6990 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6991 cpu_gpr_d[r2], n, 32);
6992 break;
6993 case OPC2_32_RRR1_MADDS_Q_64:
6994 CHECK_REG_PAIR(r4);
6995 CHECK_REG_PAIR(r3);
6996 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6997 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6998 n);
6999 break;
7000 case OPC2_32_RRR1_MADDS_Q_32_L:
7001 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7002 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7003 temp, n, 16);
7004 break;
7005 case OPC2_32_RRR1_MADDS_Q_64_L:
7006 CHECK_REG_PAIR(r4);
7007 CHECK_REG_PAIR(r3);
7008 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7009 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7010 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7011 n);
7012 break;
7013 case OPC2_32_RRR1_MADDS_Q_32_U:
7014 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7015 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7016 temp, n, 16);
7017 break;
7018 case OPC2_32_RRR1_MADDS_Q_64_U:
7019 CHECK_REG_PAIR(r4);
7020 CHECK_REG_PAIR(r3);
7021 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7022 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7023 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7024 n);
7025 break;
7026 case OPC2_32_RRR1_MADDS_Q_32_LL:
7027 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7028 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7029 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7030 break;
7031 case OPC2_32_RRR1_MADDS_Q_64_LL:
7032 CHECK_REG_PAIR(r4);
7033 CHECK_REG_PAIR(r3);
7034 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7035 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7036 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7037 cpu_gpr_d[r3+1], temp, temp2, n);
7038 break;
7039 case OPC2_32_RRR1_MADDS_Q_32_UU:
7040 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7041 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7042 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7043 break;
7044 case OPC2_32_RRR1_MADDS_Q_64_UU:
7045 CHECK_REG_PAIR(r4);
7046 CHECK_REG_PAIR(r3);
7047 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7048 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7049 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7050 cpu_gpr_d[r3+1], temp, temp2, n);
7051 break;
7052 case OPC2_32_RRR1_MADDR_H_64_UL:
7053 CHECK_REG_PAIR(r3);
7054 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7055 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7056 break;
7057 case OPC2_32_RRR1_MADDRS_H_64_UL:
7058 CHECK_REG_PAIR(r3);
7059 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7060 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7061 break;
7062 case OPC2_32_RRR1_MADDR_Q_32_LL:
7063 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7064 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7065 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7066 break;
7067 case OPC2_32_RRR1_MADDR_Q_32_UU:
7068 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7069 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7070 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7071 break;
7072 case OPC2_32_RRR1_MADDRS_Q_32_LL:
7073 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7074 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7075 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7076 break;
7077 case OPC2_32_RRR1_MADDRS_Q_32_UU:
7078 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7079 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7080 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7081 break;
7082 default:
7083 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7084 }
7085 }
7086
7087 static void decode_rrr1_maddsu_h(DisasContext *ctx)
7088 {
7089 uint32_t op2;
7090 uint32_t r1, r2, r3, r4, n;
7091
7092 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7093 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7094 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7095 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7096 r4 = MASK_OP_RRR1_D(ctx->opcode);
7097 n = MASK_OP_RRR1_N(ctx->opcode);
7098
7099 switch (op2) {
7100 case OPC2_32_RRR1_MADDSU_H_32_LL:
7101 CHECK_REG_PAIR(r4);
7102 CHECK_REG_PAIR(r3);
7103 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7104 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7105 break;
7106 case OPC2_32_RRR1_MADDSU_H_32_LU:
7107 CHECK_REG_PAIR(r4);
7108 CHECK_REG_PAIR(r3);
7109 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7110 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7111 break;
7112 case OPC2_32_RRR1_MADDSU_H_32_UL:
7113 CHECK_REG_PAIR(r4);
7114 CHECK_REG_PAIR(r3);
7115 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7116 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7117 break;
7118 case OPC2_32_RRR1_MADDSU_H_32_UU:
7119 CHECK_REG_PAIR(r4);
7120 CHECK_REG_PAIR(r3);
7121 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7122 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7123 break;
7124 case OPC2_32_RRR1_MADDSUS_H_32_LL:
7125 CHECK_REG_PAIR(r4);
7126 CHECK_REG_PAIR(r3);
7127 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7128 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7129 n, MODE_LL);
7130 break;
7131 case OPC2_32_RRR1_MADDSUS_H_32_LU:
7132 CHECK_REG_PAIR(r4);
7133 CHECK_REG_PAIR(r3);
7134 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7135 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7136 n, MODE_LU);
7137 break;
7138 case OPC2_32_RRR1_MADDSUS_H_32_UL:
7139 CHECK_REG_PAIR(r4);
7140 CHECK_REG_PAIR(r3);
7141 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7142 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7143 n, MODE_UL);
7144 break;
7145 case OPC2_32_RRR1_MADDSUS_H_32_UU:
7146 CHECK_REG_PAIR(r4);
7147 CHECK_REG_PAIR(r3);
7148 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7149 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7150 n, MODE_UU);
7151 break;
7152 case OPC2_32_RRR1_MADDSUM_H_64_LL:
7153 CHECK_REG_PAIR(r4);
7154 CHECK_REG_PAIR(r3);
7155 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7156 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7157 n, MODE_LL);
7158 break;
7159 case OPC2_32_RRR1_MADDSUM_H_64_LU:
7160 CHECK_REG_PAIR(r4);
7161 CHECK_REG_PAIR(r3);
7162 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7163 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7164 n, MODE_LU);
7165 break;
7166 case OPC2_32_RRR1_MADDSUM_H_64_UL:
7167 CHECK_REG_PAIR(r4);
7168 CHECK_REG_PAIR(r3);
7169 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7170 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7171 n, MODE_UL);
7172 break;
7173 case OPC2_32_RRR1_MADDSUM_H_64_UU:
7174 CHECK_REG_PAIR(r4);
7175 CHECK_REG_PAIR(r3);
7176 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7177 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7178 n, MODE_UU);
7179 break;
7180 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
7181 CHECK_REG_PAIR(r4);
7182 CHECK_REG_PAIR(r3);
7183 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7184 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7185 n, MODE_LL);
7186 break;
7187 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
7188 CHECK_REG_PAIR(r4);
7189 CHECK_REG_PAIR(r3);
7190 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7191 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7192 n, MODE_LU);
7193 break;
7194 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
7195 CHECK_REG_PAIR(r4);
7196 CHECK_REG_PAIR(r3);
7197 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7198 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7199 n, MODE_UL);
7200 break;
7201 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
7202 CHECK_REG_PAIR(r4);
7203 CHECK_REG_PAIR(r3);
7204 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7205 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7206 n, MODE_UU);
7207 break;
7208 case OPC2_32_RRR1_MADDSUR_H_16_LL:
7209 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7210 cpu_gpr_d[r2], n, MODE_LL);
7211 break;
7212 case OPC2_32_RRR1_MADDSUR_H_16_LU:
7213 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7214 cpu_gpr_d[r2], n, MODE_LU);
7215 break;
7216 case OPC2_32_RRR1_MADDSUR_H_16_UL:
7217 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7218 cpu_gpr_d[r2], n, MODE_UL);
7219 break;
7220 case OPC2_32_RRR1_MADDSUR_H_16_UU:
7221 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7222 cpu_gpr_d[r2], n, MODE_UU);
7223 break;
7224 case OPC2_32_RRR1_MADDSURS_H_16_LL:
7225 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7226 cpu_gpr_d[r2], n, MODE_LL);
7227 break;
7228 case OPC2_32_RRR1_MADDSURS_H_16_LU:
7229 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7230 cpu_gpr_d[r2], n, MODE_LU);
7231 break;
7232 case OPC2_32_RRR1_MADDSURS_H_16_UL:
7233 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7234 cpu_gpr_d[r2], n, MODE_UL);
7235 break;
7236 case OPC2_32_RRR1_MADDSURS_H_16_UU:
7237 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7238 cpu_gpr_d[r2], n, MODE_UU);
7239 break;
7240 default:
7241 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7242 }
7243 }
7244
7245 static void decode_rrr1_msub(DisasContext *ctx)
7246 {
7247 uint32_t op2;
7248 uint32_t r1, r2, r3, r4, n;
7249
7250 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7251 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7252 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7253 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7254 r4 = MASK_OP_RRR1_D(ctx->opcode);
7255 n = MASK_OP_RRR1_N(ctx->opcode);
7256
7257 switch (op2) {
7258 case OPC2_32_RRR1_MSUB_H_LL:
7259 CHECK_REG_PAIR(r4);
7260 CHECK_REG_PAIR(r3);
7261 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7262 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7263 break;
7264 case OPC2_32_RRR1_MSUB_H_LU:
7265 CHECK_REG_PAIR(r4);
7266 CHECK_REG_PAIR(r3);
7267 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7268 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7269 break;
7270 case OPC2_32_RRR1_MSUB_H_UL:
7271 CHECK_REG_PAIR(r4);
7272 CHECK_REG_PAIR(r3);
7273 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7274 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7275 break;
7276 case OPC2_32_RRR1_MSUB_H_UU:
7277 CHECK_REG_PAIR(r4);
7278 CHECK_REG_PAIR(r3);
7279 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7280 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7281 break;
7282 case OPC2_32_RRR1_MSUBS_H_LL:
7283 CHECK_REG_PAIR(r4);
7284 CHECK_REG_PAIR(r3);
7285 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7286 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7287 break;
7288 case OPC2_32_RRR1_MSUBS_H_LU:
7289 CHECK_REG_PAIR(r4);
7290 CHECK_REG_PAIR(r3);
7291 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7292 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7293 break;
7294 case OPC2_32_RRR1_MSUBS_H_UL:
7295 CHECK_REG_PAIR(r4);
7296 CHECK_REG_PAIR(r3);
7297 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7298 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7299 break;
7300 case OPC2_32_RRR1_MSUBS_H_UU:
7301 CHECK_REG_PAIR(r4);
7302 CHECK_REG_PAIR(r3);
7303 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7304 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7305 break;
7306 case OPC2_32_RRR1_MSUBM_H_LL:
7307 CHECK_REG_PAIR(r4);
7308 CHECK_REG_PAIR(r3);
7309 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7310 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7311 break;
7312 case OPC2_32_RRR1_MSUBM_H_LU:
7313 CHECK_REG_PAIR(r4);
7314 CHECK_REG_PAIR(r3);
7315 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7316 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7317 break;
7318 case OPC2_32_RRR1_MSUBM_H_UL:
7319 CHECK_REG_PAIR(r4);
7320 CHECK_REG_PAIR(r3);
7321 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7322 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7323 break;
7324 case OPC2_32_RRR1_MSUBM_H_UU:
7325 CHECK_REG_PAIR(r4);
7326 CHECK_REG_PAIR(r3);
7327 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7328 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7329 break;
7330 case OPC2_32_RRR1_MSUBMS_H_LL:
7331 CHECK_REG_PAIR(r4);
7332 CHECK_REG_PAIR(r3);
7333 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7334 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7335 break;
7336 case OPC2_32_RRR1_MSUBMS_H_LU:
7337 CHECK_REG_PAIR(r4);
7338 CHECK_REG_PAIR(r3);
7339 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7340 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7341 break;
7342 case OPC2_32_RRR1_MSUBMS_H_UL:
7343 CHECK_REG_PAIR(r4);
7344 CHECK_REG_PAIR(r3);
7345 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7346 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7347 break;
7348 case OPC2_32_RRR1_MSUBMS_H_UU:
7349 CHECK_REG_PAIR(r4);
7350 CHECK_REG_PAIR(r3);
7351 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7352 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7353 break;
7354 case OPC2_32_RRR1_MSUBR_H_LL:
7355 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7356 cpu_gpr_d[r2], n, MODE_LL);
7357 break;
7358 case OPC2_32_RRR1_MSUBR_H_LU:
7359 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7360 cpu_gpr_d[r2], n, MODE_LU);
7361 break;
7362 case OPC2_32_RRR1_MSUBR_H_UL:
7363 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7364 cpu_gpr_d[r2], n, MODE_UL);
7365 break;
7366 case OPC2_32_RRR1_MSUBR_H_UU:
7367 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7368 cpu_gpr_d[r2], n, MODE_UU);
7369 break;
7370 case OPC2_32_RRR1_MSUBRS_H_LL:
7371 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7372 cpu_gpr_d[r2], n, MODE_LL);
7373 break;
7374 case OPC2_32_RRR1_MSUBRS_H_LU:
7375 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7376 cpu_gpr_d[r2], n, MODE_LU);
7377 break;
7378 case OPC2_32_RRR1_MSUBRS_H_UL:
7379 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7380 cpu_gpr_d[r2], n, MODE_UL);
7381 break;
7382 case OPC2_32_RRR1_MSUBRS_H_UU:
7383 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7384 cpu_gpr_d[r2], n, MODE_UU);
7385 break;
7386 default:
7387 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7388 }
7389 }
7390
7391 static void decode_rrr1_msubq_h(DisasContext *ctx)
7392 {
7393 uint32_t op2;
7394 uint32_t r1, r2, r3, r4, n;
7395 TCGv temp, temp2;
7396
7397 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7398 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7399 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7400 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7401 r4 = MASK_OP_RRR1_D(ctx->opcode);
7402 n = MASK_OP_RRR1_N(ctx->opcode);
7403
7404 temp = tcg_const_i32(n);
7405 temp2 = tcg_temp_new();
7406
7407 switch (op2) {
7408 case OPC2_32_RRR1_MSUB_Q_32:
7409 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7410 cpu_gpr_d[r2], n, 32);
7411 break;
7412 case OPC2_32_RRR1_MSUB_Q_64:
7413 CHECK_REG_PAIR(r4);
7414 CHECK_REG_PAIR(r3);
7415 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7416 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7417 n);
7418 break;
7419 case OPC2_32_RRR1_MSUB_Q_32_L:
7420 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7421 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7422 temp, n, 16);
7423 break;
7424 case OPC2_32_RRR1_MSUB_Q_64_L:
7425 CHECK_REG_PAIR(r4);
7426 CHECK_REG_PAIR(r3);
7427 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7428 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7429 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7430 n);
7431 break;
7432 case OPC2_32_RRR1_MSUB_Q_32_U:
7433 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7434 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7435 temp, n, 16);
7436 break;
7437 case OPC2_32_RRR1_MSUB_Q_64_U:
7438 CHECK_REG_PAIR(r4);
7439 CHECK_REG_PAIR(r3);
7440 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7441 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7442 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7443 n);
7444 break;
7445 case OPC2_32_RRR1_MSUB_Q_32_LL:
7446 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7447 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7448 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7449 break;
7450 case OPC2_32_RRR1_MSUB_Q_64_LL:
7451 CHECK_REG_PAIR(r4);
7452 CHECK_REG_PAIR(r3);
7453 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7454 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7455 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7456 cpu_gpr_d[r3+1], temp, temp2, n);
7457 break;
7458 case OPC2_32_RRR1_MSUB_Q_32_UU:
7459 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7460 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7461 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7462 break;
7463 case OPC2_32_RRR1_MSUB_Q_64_UU:
7464 CHECK_REG_PAIR(r4);
7465 CHECK_REG_PAIR(r3);
7466 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7467 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7468 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7469 cpu_gpr_d[r3+1], temp, temp2, n);
7470 break;
7471 case OPC2_32_RRR1_MSUBS_Q_32:
7472 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7473 cpu_gpr_d[r2], n, 32);
7474 break;
7475 case OPC2_32_RRR1_MSUBS_Q_64:
7476 CHECK_REG_PAIR(r4);
7477 CHECK_REG_PAIR(r3);
7478 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7479 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7480 n);
7481 break;
7482 case OPC2_32_RRR1_MSUBS_Q_32_L:
7483 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7484 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7485 temp, n, 16);
7486 break;
7487 case OPC2_32_RRR1_MSUBS_Q_64_L:
7488 CHECK_REG_PAIR(r4);
7489 CHECK_REG_PAIR(r3);
7490 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7491 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7492 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7493 n);
7494 break;
7495 case OPC2_32_RRR1_MSUBS_Q_32_U:
7496 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7497 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7498 temp, n, 16);
7499 break;
7500 case OPC2_32_RRR1_MSUBS_Q_64_U:
7501 CHECK_REG_PAIR(r4);
7502 CHECK_REG_PAIR(r3);
7503 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7504 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7505 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7506 n);
7507 break;
7508 case OPC2_32_RRR1_MSUBS_Q_32_LL:
7509 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7510 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7511 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7512 break;
7513 case OPC2_32_RRR1_MSUBS_Q_64_LL:
7514 CHECK_REG_PAIR(r4);
7515 CHECK_REG_PAIR(r3);
7516 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7517 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7518 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7519 cpu_gpr_d[r3+1], temp, temp2, n);
7520 break;
7521 case OPC2_32_RRR1_MSUBS_Q_32_UU:
7522 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7523 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7524 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7525 break;
7526 case OPC2_32_RRR1_MSUBS_Q_64_UU:
7527 CHECK_REG_PAIR(r4);
7528 CHECK_REG_PAIR(r3);
7529 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7530 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7531 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7532 cpu_gpr_d[r3+1], temp, temp2, n);
7533 break;
7534 case OPC2_32_RRR1_MSUBR_H_64_UL:
7535 CHECK_REG_PAIR(r3);
7536 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7537 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7538 break;
7539 case OPC2_32_RRR1_MSUBRS_H_64_UL:
7540 CHECK_REG_PAIR(r3);
7541 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7542 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7543 break;
7544 case OPC2_32_RRR1_MSUBR_Q_32_LL:
7545 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7546 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7547 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7548 break;
7549 case OPC2_32_RRR1_MSUBR_Q_32_UU:
7550 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7551 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7552 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7553 break;
7554 case OPC2_32_RRR1_MSUBRS_Q_32_LL:
7555 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7556 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7557 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7558 break;
7559 case OPC2_32_RRR1_MSUBRS_Q_32_UU:
7560 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7561 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7562 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7563 break;
7564 default:
7565 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7566 }
7567 }
7568
7569 static void decode_rrr1_msubad_h(DisasContext *ctx)
7570 {
7571 uint32_t op2;
7572 uint32_t r1, r2, r3, r4, n;
7573
7574 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7575 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7576 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7577 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7578 r4 = MASK_OP_RRR1_D(ctx->opcode);
7579 n = MASK_OP_RRR1_N(ctx->opcode);
7580
7581 switch (op2) {
7582 case OPC2_32_RRR1_MSUBAD_H_32_LL:
7583 CHECK_REG_PAIR(r4);
7584 CHECK_REG_PAIR(r3);
7585 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7586 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7587 break;
7588 case OPC2_32_RRR1_MSUBAD_H_32_LU:
7589 CHECK_REG_PAIR(r4);
7590 CHECK_REG_PAIR(r3);
7591 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7592 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7593 break;
7594 case OPC2_32_RRR1_MSUBAD_H_32_UL:
7595 CHECK_REG_PAIR(r4);
7596 CHECK_REG_PAIR(r3);
7597 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7598 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7599 break;
7600 case OPC2_32_RRR1_MSUBAD_H_32_UU:
7601 CHECK_REG_PAIR(r4);
7602 CHECK_REG_PAIR(r3);
7603 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7604 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7605 break;
7606 case OPC2_32_RRR1_MSUBADS_H_32_LL:
7607 CHECK_REG_PAIR(r4);
7608 CHECK_REG_PAIR(r3);
7609 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7610 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7611 n, MODE_LL);
7612 break;
7613 case OPC2_32_RRR1_MSUBADS_H_32_LU:
7614 CHECK_REG_PAIR(r4);
7615 CHECK_REG_PAIR(r3);
7616 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7617 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7618 n, MODE_LU);
7619 break;
7620 case OPC2_32_RRR1_MSUBADS_H_32_UL:
7621 CHECK_REG_PAIR(r4);
7622 CHECK_REG_PAIR(r3);
7623 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7624 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7625 n, MODE_UL);
7626 break;
7627 case OPC2_32_RRR1_MSUBADS_H_32_UU:
7628 CHECK_REG_PAIR(r4);
7629 CHECK_REG_PAIR(r3);
7630 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7631 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7632 n, MODE_UU);
7633 break;
7634 case OPC2_32_RRR1_MSUBADM_H_64_LL:
7635 CHECK_REG_PAIR(r4);
7636 CHECK_REG_PAIR(r3);
7637 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7638 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7639 n, MODE_LL);
7640 break;
7641 case OPC2_32_RRR1_MSUBADM_H_64_LU:
7642 CHECK_REG_PAIR(r4);
7643 CHECK_REG_PAIR(r3);
7644 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7645 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7646 n, MODE_LU);
7647 break;
7648 case OPC2_32_RRR1_MSUBADM_H_64_UL:
7649 CHECK_REG_PAIR(r4);
7650 CHECK_REG_PAIR(r3);
7651 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7652 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7653 n, MODE_UL);
7654 break;
7655 case OPC2_32_RRR1_MSUBADM_H_64_UU:
7656 CHECK_REG_PAIR(r4);
7657 CHECK_REG_PAIR(r3);
7658 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7659 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7660 n, MODE_UU);
7661 break;
7662 case OPC2_32_RRR1_MSUBADMS_H_64_LL:
7663 CHECK_REG_PAIR(r4);
7664 CHECK_REG_PAIR(r3);
7665 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7666 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7667 n, MODE_LL);
7668 break;
7669 case OPC2_32_RRR1_MSUBADMS_H_64_LU:
7670 CHECK_REG_PAIR(r4);
7671 CHECK_REG_PAIR(r3);
7672 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7673 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7674 n, MODE_LU);
7675 break;
7676 case OPC2_32_RRR1_MSUBADMS_H_64_UL:
7677 CHECK_REG_PAIR(r4);
7678 CHECK_REG_PAIR(r3);
7679 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7680 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7681 n, MODE_UL);
7682 break;
7683 case OPC2_32_RRR1_MSUBADMS_H_64_UU:
7684 CHECK_REG_PAIR(r4);
7685 CHECK_REG_PAIR(r3);
7686 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7687 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7688 n, MODE_UU);
7689 break;
7690 case OPC2_32_RRR1_MSUBADR_H_16_LL:
7691 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7692 cpu_gpr_d[r2], n, MODE_LL);
7693 break;
7694 case OPC2_32_RRR1_MSUBADR_H_16_LU:
7695 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7696 cpu_gpr_d[r2], n, MODE_LU);
7697 break;
7698 case OPC2_32_RRR1_MSUBADR_H_16_UL:
7699 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7700 cpu_gpr_d[r2], n, MODE_UL);
7701 break;
7702 case OPC2_32_RRR1_MSUBADR_H_16_UU:
7703 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7704 cpu_gpr_d[r2], n, MODE_UU);
7705 break;
7706 case OPC2_32_RRR1_MSUBADRS_H_16_LL:
7707 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7708 cpu_gpr_d[r2], n, MODE_LL);
7709 break;
7710 case OPC2_32_RRR1_MSUBADRS_H_16_LU:
7711 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7712 cpu_gpr_d[r2], n, MODE_LU);
7713 break;
7714 case OPC2_32_RRR1_MSUBADRS_H_16_UL:
7715 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7716 cpu_gpr_d[r2], n, MODE_UL);
7717 break;
7718 case OPC2_32_RRR1_MSUBADRS_H_16_UU:
7719 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7720 cpu_gpr_d[r2], n, MODE_UU);
7721 break;
7722 default:
7723 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7724 }
7725 }
7726
7727 /* RRRR format */
7728 static void decode_rrrr_extract_insert(DisasContext *ctx)
7729 {
7730 uint32_t op2;
7731 int r1, r2, r3, r4;
7732 TCGv tmp_width, tmp_pos;
7733
7734 r1 = MASK_OP_RRRR_S1(ctx->opcode);
7735 r2 = MASK_OP_RRRR_S2(ctx->opcode);
7736 r3 = MASK_OP_RRRR_S3(ctx->opcode);
7737 r4 = MASK_OP_RRRR_D(ctx->opcode);
7738 op2 = MASK_OP_RRRR_OP2(ctx->opcode);
7739
7740 tmp_pos = tcg_temp_new();
7741 tmp_width = tcg_temp_new();
7742
7743 switch (op2) {
7744 case OPC2_32_RRRR_DEXTR:
7745 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7746 if (r1 == r2) {
7747 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7748 } else {
7749 TCGv msw = tcg_temp_new();
7750 TCGv zero = tcg_constant_tl(0);
7751 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
7752 tcg_gen_subfi_tl(msw, 32, tmp_pos);
7753 tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw);
7754 /*
7755 * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined
7756 * behaviour. So check that case here and set the low bits to zero
7757 * which effectivly returns cpu_gpr_d[r1]
7758 */
7759 tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw);
7760 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw);
7761 }
7762 break;
7763 case OPC2_32_RRRR_EXTR:
7764 case OPC2_32_RRRR_EXTR_U:
7765 CHECK_REG_PAIR(r3);
7766 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7767 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7768 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
7769 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7770 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7771 tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
7772 if (op2 == OPC2_32_RRRR_EXTR) {
7773 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7774 } else {
7775 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7776 }
7777 break;
7778 case OPC2_32_RRRR_INSERT:
7779 CHECK_REG_PAIR(r3);
7780 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7781 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7782 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
7783 tmp_pos);
7784 break;
7785 default:
7786 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7787 }
7788 }
7789
7790 /* RRRW format */
7791 static void decode_rrrw_extract_insert(DisasContext *ctx)
7792 {
7793 uint32_t op2;
7794 int r1, r2, r3, r4;
7795 int32_t width;
7796
7797 TCGv temp, temp2;
7798
7799 op2 = MASK_OP_RRRW_OP2(ctx->opcode);
7800 r1 = MASK_OP_RRRW_S1(ctx->opcode);
7801 r2 = MASK_OP_RRRW_S2(ctx->opcode);
7802 r3 = MASK_OP_RRRW_S3(ctx->opcode);
7803 r4 = MASK_OP_RRRW_D(ctx->opcode);
7804 width = MASK_OP_RRRW_WIDTH(ctx->opcode);
7805
7806 temp = tcg_temp_new();
7807
7808 switch (op2) {
7809 case OPC2_32_RRRW_EXTR:
7810 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7811 tcg_gen_addi_tl(temp, temp, width);
7812 tcg_gen_subfi_tl(temp, 32, temp);
7813 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7814 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
7815 break;
7816 case OPC2_32_RRRW_EXTR_U:
7817 if (width == 0) {
7818 tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
7819 } else {
7820 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7821 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7822 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
7823 }
7824 break;
7825 case OPC2_32_RRRW_IMASK:
7826 temp2 = tcg_temp_new();
7827
7828 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7829 tcg_gen_movi_tl(temp2, (1 << width) - 1);
7830 tcg_gen_shl_tl(temp2, temp2, temp);
7831 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
7832 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
7833 break;
7834 case OPC2_32_RRRW_INSERT:
7835 temp2 = tcg_temp_new();
7836
7837 tcg_gen_movi_tl(temp, width);
7838 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
7839 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
7840 break;
7841 default:
7842 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7843 }
7844 }
7845
7846 /* SYS Format*/
7847 static void decode_sys_interrupts(DisasContext *ctx)
7848 {
7849 uint32_t op2;
7850 uint32_t r1;
7851 TCGLabel *l1;
7852 TCGv tmp;
7853
7854 op2 = MASK_OP_SYS_OP2(ctx->opcode);
7855 r1 = MASK_OP_SYS_S1D(ctx->opcode);
7856
7857 switch (op2) {
7858 case OPC2_32_SYS_DEBUG:
7859 /* raise EXCP_DEBUG */
7860 break;
7861 case OPC2_32_SYS_DISABLE:
7862 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3);
7863 break;
7864 case OPC2_32_SYS_DSYNC:
7865 break;
7866 case OPC2_32_SYS_ENABLE:
7867 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3);
7868 break;
7869 case OPC2_32_SYS_ISYNC:
7870 break;
7871 case OPC2_32_SYS_NOP:
7872 break;
7873 case OPC2_32_SYS_RET:
7874 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
7875 break;
7876 case OPC2_32_SYS_FRET:
7877 gen_fret(ctx);
7878 break;
7879 case OPC2_32_SYS_RFE:
7880 gen_helper_rfe(cpu_env);
7881 tcg_gen_exit_tb(NULL, 0);
7882 ctx->base.is_jmp = DISAS_NORETURN;
7883 break;
7884 case OPC2_32_SYS_RFM:
7885 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
7886 tmp = tcg_temp_new();
7887 l1 = gen_new_label();
7888
7889 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
7890 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
7891 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
7892 gen_helper_rfm(cpu_env);
7893 gen_set_label(l1);
7894 tcg_gen_exit_tb(NULL, 0);
7895 ctx->base.is_jmp = DISAS_NORETURN;
7896 } else {
7897 /* generate privilege trap */
7898 }
7899 break;
7900 case OPC2_32_SYS_RSLCX:
7901 gen_helper_rslcx(cpu_env);
7902 break;
7903 case OPC2_32_SYS_SVLCX:
7904 gen_helper_svlcx(cpu_env);
7905 break;
7906 case OPC2_32_SYS_RESTORE:
7907 if (has_feature(ctx, TRICORE_FEATURE_16)) {
7908 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
7909 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
7910 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
7911 } /* else raise privilege trap */
7912 } else {
7913 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7914 }
7915 break;
7916 case OPC2_32_SYS_TRAPSV:
7917 l1 = gen_new_label();
7918 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1);
7919 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF);
7920 gen_set_label(l1);
7921 break;
7922 case OPC2_32_SYS_TRAPV:
7923 l1 = gen_new_label();
7924 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1);
7925 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF);
7926 gen_set_label(l1);
7927 break;
7928 default:
7929 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
7930 }
7931 }
7932
7933 static void decode_32Bit_opc(DisasContext *ctx)
7934 {
7935 int op1;
7936 int32_t r1, r2, r3;
7937 int32_t address, const16;
7938 int8_t b, const4;
7939 int32_t bpos;
7940 TCGv temp, temp2, temp3;
7941
7942 op1 = MASK_OP_MAJOR(ctx->opcode);
7943
7944 /* handle JNZ.T opcode only being 7 bit long */
7945 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
7946 op1 = OPCM_32_BRN_JTT;
7947 }
7948
7949 switch (op1) {
7950 /* ABS-format */
7951 case OPCM_32_ABS_LDW:
7952 decode_abs_ldw(ctx);
7953 break;
7954 case OPCM_32_ABS_LDB:
7955 decode_abs_ldb(ctx);
7956 break;
7957 case OPCM_32_ABS_LDMST_SWAP:
7958 decode_abs_ldst_swap(ctx);
7959 break;
7960 case OPCM_32_ABS_LDST_CONTEXT:
7961 decode_abs_ldst_context(ctx);
7962 break;
7963 case OPCM_32_ABS_STORE:
7964 decode_abs_store(ctx);
7965 break;
7966 case OPCM_32_ABS_STOREB_H:
7967 decode_abs_storeb_h(ctx);
7968 break;
7969 case OPC1_32_ABS_STOREQ:
7970 address = MASK_OP_ABS_OFF18(ctx->opcode);
7971 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7972 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7973 temp2 = tcg_temp_new();
7974
7975 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
7976 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
7977 break;
7978 case OPC1_32_ABS_LD_Q:
7979 address = MASK_OP_ABS_OFF18(ctx->opcode);
7980 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7981 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7982
7983 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
7984 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
7985 break;
7986 case OPC1_32_ABS_LEA:
7987 address = MASK_OP_ABS_OFF18(ctx->opcode);
7988 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7989 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
7990 break;
7991 /* ABSB-format */
7992 case OPC1_32_ABSB_ST_T:
7993 address = MASK_OP_ABS_OFF18(ctx->opcode);
7994 b = MASK_OP_ABSB_B(ctx->opcode);
7995 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
7996
7997 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7998 temp2 = tcg_temp_new();
7999
8000 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
8001 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
8002 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
8003 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
8004 break;
8005 /* B-format */
8006 case OPC1_32_B_CALL:
8007 case OPC1_32_B_CALLA:
8008 case OPC1_32_B_FCALL:
8009 case OPC1_32_B_FCALLA:
8010 case OPC1_32_B_J:
8011 case OPC1_32_B_JA:
8012 case OPC1_32_B_JL:
8013 case OPC1_32_B_JLA:
8014 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
8015 gen_compute_branch(ctx, op1, 0, 0, 0, address);
8016 break;
8017 /* Bit-format */
8018 case OPCM_32_BIT_ANDACC:
8019 decode_bit_andacc(ctx);
8020 break;
8021 case OPCM_32_BIT_LOGICAL_T1:
8022 decode_bit_logical_t(ctx);
8023 break;
8024 case OPCM_32_BIT_INSERT:
8025 decode_bit_insert(ctx);
8026 break;
8027 case OPCM_32_BIT_LOGICAL_T2:
8028 decode_bit_logical_t2(ctx);
8029 break;
8030 case OPCM_32_BIT_ORAND:
8031 decode_bit_orand(ctx);
8032 break;
8033 case OPCM_32_BIT_SH_LOGIC1:
8034 decode_bit_sh_logic1(ctx);
8035 break;
8036 case OPCM_32_BIT_SH_LOGIC2:
8037 decode_bit_sh_logic2(ctx);
8038 break;
8039 /* BO Format */
8040 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
8041 decode_bo_addrmode_post_pre_base(ctx);
8042 break;
8043 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
8044 decode_bo_addrmode_bitreverse_circular(ctx);
8045 break;
8046 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
8047 decode_bo_addrmode_ld_post_pre_base(ctx);
8048 break;
8049 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
8050 decode_bo_addrmode_ld_bitreverse_circular(ctx);
8051 break;
8052 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
8053 decode_bo_addrmode_stctx_post_pre_base(ctx);
8054 break;
8055 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
8056 decode_bo_addrmode_ldmst_bitreverse_circular(ctx);
8057 break;
8058 /* BOL-format */
8059 case OPC1_32_BOL_LD_A_LONGOFF:
8060 case OPC1_32_BOL_LD_W_LONGOFF:
8061 case OPC1_32_BOL_LEA_LONGOFF:
8062 case OPC1_32_BOL_ST_W_LONGOFF:
8063 case OPC1_32_BOL_ST_A_LONGOFF:
8064 case OPC1_32_BOL_LD_B_LONGOFF:
8065 case OPC1_32_BOL_LD_BU_LONGOFF:
8066 case OPC1_32_BOL_LD_H_LONGOFF:
8067 case OPC1_32_BOL_LD_HU_LONGOFF:
8068 case OPC1_32_BOL_ST_B_LONGOFF:
8069 case OPC1_32_BOL_ST_H_LONGOFF:
8070 decode_bol_opc(ctx, op1);
8071 break;
8072 /* BRC Format */
8073 case OPCM_32_BRC_EQ_NEQ:
8074 case OPCM_32_BRC_GE:
8075 case OPCM_32_BRC_JLT:
8076 case OPCM_32_BRC_JNE:
8077 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
8078 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
8079 r1 = MASK_OP_BRC_S1(ctx->opcode);
8080 gen_compute_branch(ctx, op1, r1, 0, const4, address);
8081 break;
8082 /* BRN Format */
8083 case OPCM_32_BRN_JTT:
8084 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
8085 r1 = MASK_OP_BRN_S1(ctx->opcode);
8086 gen_compute_branch(ctx, op1, r1, 0, 0, address);
8087 break;
8088 /* BRR Format */
8089 case OPCM_32_BRR_EQ_NEQ:
8090 case OPCM_32_BRR_ADDR_EQ_NEQ:
8091 case OPCM_32_BRR_GE:
8092 case OPCM_32_BRR_JLT:
8093 case OPCM_32_BRR_JNE:
8094 case OPCM_32_BRR_JNZ:
8095 case OPCM_32_BRR_LOOP:
8096 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
8097 r2 = MASK_OP_BRR_S2(ctx->opcode);
8098 r1 = MASK_OP_BRR_S1(ctx->opcode);
8099 gen_compute_branch(ctx, op1, r1, r2, 0, address);
8100 break;
8101 /* RC Format */
8102 case OPCM_32_RC_LOGICAL_SHIFT:
8103 decode_rc_logical_shift(ctx);
8104 break;
8105 case OPCM_32_RC_ACCUMULATOR:
8106 decode_rc_accumulator(ctx);
8107 break;
8108 case OPCM_32_RC_SERVICEROUTINE:
8109 decode_rc_serviceroutine(ctx);
8110 break;
8111 case OPCM_32_RC_MUL:
8112 decode_rc_mul(ctx);
8113 break;
8114 /* RCPW Format */
8115 case OPCM_32_RCPW_MASK_INSERT:
8116 decode_rcpw_insert(ctx);
8117 break;
8118 /* RCRR Format */
8119 case OPC1_32_RCRR_INSERT:
8120 r1 = MASK_OP_RCRR_S1(ctx->opcode);
8121 r2 = MASK_OP_RCRR_S3(ctx->opcode);
8122 r3 = MASK_OP_RCRR_D(ctx->opcode);
8123 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
8124 temp = tcg_const_i32(const16);
8125 temp2 = tcg_temp_new(); /* width*/
8126 temp3 = tcg_temp_new(); /* pos */
8127
8128 CHECK_REG_PAIR(r3);
8129
8130 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
8131 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
8132
8133 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
8134 break;
8135 /* RCRW Format */
8136 case OPCM_32_RCRW_MASK_INSERT:
8137 decode_rcrw_insert(ctx);
8138 break;
8139 /* RCR Format */
8140 case OPCM_32_RCR_COND_SELECT:
8141 decode_rcr_cond_select(ctx);
8142 break;
8143 case OPCM_32_RCR_MADD:
8144 decode_rcr_madd(ctx);
8145 break;
8146 case OPCM_32_RCR_MSUB:
8147 decode_rcr_msub(ctx);
8148 break;
8149 /* RLC Format */
8150 case OPC1_32_RLC_ADDI:
8151 case OPC1_32_RLC_ADDIH:
8152 case OPC1_32_RLC_ADDIH_A:
8153 case OPC1_32_RLC_MFCR:
8154 case OPC1_32_RLC_MOV:
8155 case OPC1_32_RLC_MOV_64:
8156 case OPC1_32_RLC_MOV_U:
8157 case OPC1_32_RLC_MOV_H:
8158 case OPC1_32_RLC_MOVH_A:
8159 case OPC1_32_RLC_MTCR:
8160 decode_rlc_opc(ctx, op1);
8161 break;
8162 /* RR Format */
8163 case OPCM_32_RR_ACCUMULATOR:
8164 decode_rr_accumulator(ctx);
8165 break;
8166 case OPCM_32_RR_LOGICAL_SHIFT:
8167 decode_rr_logical_shift(ctx);
8168 break;
8169 case OPCM_32_RR_ADDRESS:
8170 decode_rr_address(ctx);
8171 break;
8172 case OPCM_32_RR_IDIRECT:
8173 decode_rr_idirect(ctx);
8174 break;
8175 case OPCM_32_RR_DIVIDE:
8176 decode_rr_divide(ctx);
8177 break;
8178 /* RR1 Format */
8179 case OPCM_32_RR1_MUL:
8180 decode_rr1_mul(ctx);
8181 break;
8182 case OPCM_32_RR1_MULQ:
8183 decode_rr1_mulq(ctx);
8184 break;
8185 /* RR2 format */
8186 case OPCM_32_RR2_MUL:
8187 decode_rr2_mul(ctx);
8188 break;
8189 /* RRPW format */
8190 case OPCM_32_RRPW_EXTRACT_INSERT:
8191 decode_rrpw_extract_insert(ctx);
8192 break;
8193 case OPC1_32_RRPW_DEXTR:
8194 r1 = MASK_OP_RRPW_S1(ctx->opcode);
8195 r2 = MASK_OP_RRPW_S2(ctx->opcode);
8196 r3 = MASK_OP_RRPW_D(ctx->opcode);
8197 const16 = MASK_OP_RRPW_POS(ctx->opcode);
8198
8199 tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1],
8200 32 - const16);
8201 break;
8202 /* RRR Format */
8203 case OPCM_32_RRR_COND_SELECT:
8204 decode_rrr_cond_select(ctx);
8205 break;
8206 case OPCM_32_RRR_DIVIDE:
8207 decode_rrr_divide(ctx);
8208 break;
8209 /* RRR2 Format */
8210 case OPCM_32_RRR2_MADD:
8211 decode_rrr2_madd(ctx);
8212 break;
8213 case OPCM_32_RRR2_MSUB:
8214 decode_rrr2_msub(ctx);
8215 break;
8216 /* RRR1 format */
8217 case OPCM_32_RRR1_MADD:
8218 decode_rrr1_madd(ctx);
8219 break;
8220 case OPCM_32_RRR1_MADDQ_H:
8221 decode_rrr1_maddq_h(ctx);
8222 break;
8223 case OPCM_32_RRR1_MADDSU_H:
8224 decode_rrr1_maddsu_h(ctx);
8225 break;
8226 case OPCM_32_RRR1_MSUB_H:
8227 decode_rrr1_msub(ctx);
8228 break;
8229 case OPCM_32_RRR1_MSUB_Q:
8230 decode_rrr1_msubq_h(ctx);
8231 break;
8232 case OPCM_32_RRR1_MSUBAD_H:
8233 decode_rrr1_msubad_h(ctx);
8234 break;
8235 /* RRRR format */
8236 case OPCM_32_RRRR_EXTRACT_INSERT:
8237 decode_rrrr_extract_insert(ctx);
8238 break;
8239 /* RRRW format */
8240 case OPCM_32_RRRW_EXTRACT_INSERT:
8241 decode_rrrw_extract_insert(ctx);
8242 break;
8243 /* SYS format */
8244 case OPCM_32_SYS_INTERRUPTS:
8245 decode_sys_interrupts(ctx);
8246 break;
8247 case OPC1_32_SYS_RSTV:
8248 tcg_gen_movi_tl(cpu_PSW_V, 0);
8249 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
8250 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
8251 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
8252 break;
8253 default:
8254 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
8255 }
8256 }
8257
8258 static bool tricore_insn_is_16bit(uint32_t insn)
8259 {
8260 return (insn & 0x1) == 0;
8261 }
8262
8263 static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
8264 CPUState *cs)
8265 {
8266 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8267 CPUTriCoreState *env = cs->env_ptr;
8268 ctx->mem_idx = cpu_mmu_index(env, false);
8269 ctx->hflags = (uint32_t)ctx->base.tb->flags;
8270 ctx->features = env->features;
8271 }
8272
8273 static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu)
8274 {
8275 }
8276
8277 static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
8278 {
8279 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8280
8281 tcg_gen_insn_start(ctx->base.pc_next);
8282 }
8283
8284 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
8285 {
8286 /*
8287 * Return true if the insn at ctx->base.pc_next might cross a page boundary.
8288 * (False positives are OK, false negatives are not.)
8289 * Our caller ensures we are only called if dc->base.pc_next is less than
8290 * 4 bytes from the page boundary, so we cross the page if the first
8291 * 16 bits indicate that this is a 32 bit insn.
8292 */
8293 uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
8294
8295 return !tricore_insn_is_16bit(insn);
8296 }
8297
8298
8299 static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
8300 {
8301 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8302 CPUTriCoreState *env = cpu->env_ptr;
8303 uint16_t insn_lo;
8304 bool is_16bit;
8305
8306 insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
8307 is_16bit = tricore_insn_is_16bit(insn_lo);
8308 if (is_16bit) {
8309 ctx->opcode = insn_lo;
8310 ctx->pc_succ_insn = ctx->base.pc_next + 2;
8311 decode_16Bit_opc(ctx);
8312 } else {
8313 uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
8314 ctx->opcode = insn_hi << 16 | insn_lo;
8315 ctx->pc_succ_insn = ctx->base.pc_next + 4;
8316 decode_32Bit_opc(ctx);
8317 }
8318 ctx->base.pc_next = ctx->pc_succ_insn;
8319
8320 if (ctx->base.is_jmp == DISAS_NEXT) {
8321 target_ulong page_start;
8322
8323 page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
8324 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE
8325 || (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - 3
8326 && insn_crosses_page(env, ctx))) {
8327 ctx->base.is_jmp = DISAS_TOO_MANY;
8328 }
8329 }
8330 }
8331
8332 static void tricore_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
8333 {
8334 DisasContext *ctx = container_of(dcbase, DisasContext, base);
8335
8336 switch (ctx->base.is_jmp) {
8337 case DISAS_TOO_MANY:
8338 gen_goto_tb(ctx, 0, ctx->base.pc_next);
8339 break;
8340 case DISAS_NORETURN:
8341 break;
8342 default:
8343 g_assert_not_reached();
8344 }
8345 }
8346
8347 static void tricore_tr_disas_log(const DisasContextBase *dcbase,
8348 CPUState *cpu, FILE *logfile)
8349 {
8350 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
8351 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
8352 }
8353
8354 static const TranslatorOps tricore_tr_ops = {
8355 .init_disas_context = tricore_tr_init_disas_context,
8356 .tb_start = tricore_tr_tb_start,
8357 .insn_start = tricore_tr_insn_start,
8358 .translate_insn = tricore_tr_translate_insn,
8359 .tb_stop = tricore_tr_tb_stop,
8360 .disas_log = tricore_tr_disas_log,
8361 };
8362
8363
8364 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
8365 target_ulong pc, void *host_pc)
8366 {
8367 DisasContext ctx;
8368 translator_loop(cs, tb, max_insns, pc, host_pc,
8369 &tricore_tr_ops, &ctx.base);
8370 }
8371
8372 /*
8373 *
8374 * Initialization
8375 *
8376 */
8377
8378 void cpu_state_reset(CPUTriCoreState *env)
8379 {
8380 /* Reset Regs to Default Value */
8381 env->PSW = 0xb80;
8382 fpu_set_state(env);
8383 }
8384
8385 static void tricore_tcg_init_csfr(void)
8386 {
8387 cpu_PCXI = tcg_global_mem_new(cpu_env,
8388 offsetof(CPUTriCoreState, PCXI), "PCXI");
8389 cpu_PSW = tcg_global_mem_new(cpu_env,
8390 offsetof(CPUTriCoreState, PSW), "PSW");
8391 cpu_PC = tcg_global_mem_new(cpu_env,
8392 offsetof(CPUTriCoreState, PC), "PC");
8393 cpu_ICR = tcg_global_mem_new(cpu_env,
8394 offsetof(CPUTriCoreState, ICR), "ICR");
8395 }
8396
8397 void tricore_tcg_init(void)
8398 {
8399 int i;
8400
8401 /* reg init */
8402 for (i = 0 ; i < 16 ; i++) {
8403 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
8404 offsetof(CPUTriCoreState, gpr_a[i]),
8405 regnames_a[i]);
8406 }
8407 for (i = 0 ; i < 16 ; i++) {
8408 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env,
8409 offsetof(CPUTriCoreState, gpr_d[i]),
8410 regnames_d[i]);
8411 }
8412 tricore_tcg_init_csfr();
8413 /* init PSW flag cache */
8414 cpu_PSW_C = tcg_global_mem_new(cpu_env,
8415 offsetof(CPUTriCoreState, PSW_USB_C),
8416 "PSW_C");
8417 cpu_PSW_V = tcg_global_mem_new(cpu_env,
8418 offsetof(CPUTriCoreState, PSW_USB_V),
8419 "PSW_V");
8420 cpu_PSW_SV = tcg_global_mem_new(cpu_env,
8421 offsetof(CPUTriCoreState, PSW_USB_SV),
8422 "PSW_SV");
8423 cpu_PSW_AV = tcg_global_mem_new(cpu_env,
8424 offsetof(CPUTriCoreState, PSW_USB_AV),
8425 "PSW_AV");
8426 cpu_PSW_SAV = tcg_global_mem_new(cpu_env,
8427 offsetof(CPUTriCoreState, PSW_USB_SAV),
8428 "PSW_SAV");
8429 }
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