target/unicore32/cpu.h

   1 /*
   2  * UniCore32 virtual CPU header
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or (at your option) any
   9  * later version. See the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef UNICORE32_CPU_H
  13 #define UNICORE32_CPU_H
  14
  15 #include "qemu-common.h"
  16 #include "cpu-qom.h"
  17 #include "exec/cpu-defs.h"
  18
  19 typedef struct CPUUniCore32State {
  20     /* Regs for current mode.  */
  21     uint32_t regs[32];
  22     /* Frequently accessed ASR bits are stored separately for efficiently.
  23        This contains all the other bits.  Use asr_{read,write} to access
  24        the whole ASR.  */
  25     uint32_t uncached_asr;
  26     uint32_t bsr;
  27
  28     /* Banked registers.  */
  29     uint32_t banked_bsr[6];
  30     uint32_t banked_r29[6];
  31     uint32_t banked_r30[6];
  32
  33     /* asr flag cache for faster execution */
  34     uint32_t CF; /* 0 or 1 */
  35     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  36     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
  37     uint32_t ZF; /* Z set if zero.  */
  38
  39     /* System control coprocessor (cp0) */
  40     struct {
  41         uint32_t c0_cpuid;
  42         uint32_t c0_cachetype;
  43         uint32_t c1_sys; /* System control register.  */
  44         uint32_t c2_base; /* MMU translation table base.  */
  45         uint32_t c3_faultstatus; /* Fault status registers.  */
  46         uint32_t c4_faultaddr; /* Fault address registers.  */
  47         uint32_t c5_cacheop; /* Cache operation registers.  */
  48         uint32_t c6_tlbop; /* TLB operation registers. */
  49     } cp0;
  50
  51     /* UniCore-F64 coprocessor state.  */
  52     struct {
  53         float64 regs[16];
  54         uint32_t xregs[32];
  55         float_status fp_status;
  56     } ucf64;
  57
  58     CPU_COMMON
  59
  60     /* Internal CPU feature flags.  */
  61     uint32_t features;
  62
  63 } CPUUniCore32State;
  64
  65 /**
  66  * UniCore32CPU:
  67  * @env: #CPUUniCore32State
  68  *
  69  * A UniCore32 CPU.
  70  */
  71 struct UniCore32CPU {
  72     /*< private >*/
  73     CPUState parent_obj;
  74     /*< public >*/
  75
  76     CPUUniCore32State env;
  77 };
  78
  79 static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
  80 {
  81     return container_of(env, UniCore32CPU, env);
  82 }
  83
  84 #define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e))
  85
  86 #define ENV_OFFSET offsetof(UniCore32CPU, env)
  87
  88 void uc32_cpu_do_interrupt(CPUState *cpu);
  89 bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);
  90 void uc32_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
  91 hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  92
  93 #define ASR_M                   (0x1f)
  94 #define ASR_MODE_USER           (0x10)
  95 #define ASR_MODE_INTR           (0x12)
  96 #define ASR_MODE_PRIV           (0x13)
  97 #define ASR_MODE_TRAP           (0x17)
  98 #define ASR_MODE_EXTN           (0x1b)
  99 #define ASR_MODE_SUSR           (0x1f)
 100 #define ASR_I                   (1 << 7)
 101 #define ASR_V                   (1 << 28)
 102 #define ASR_C                   (1 << 29)
 103 #define ASR_Z                   (1 << 30)
 104 #define ASR_N                   (1 << 31)
 105 #define ASR_NZCV                (ASR_N | ASR_Z | ASR_C | ASR_V)
 106 #define ASR_RESERVED            (~(ASR_M | ASR_I | ASR_NZCV))
 107
 108 #define UC32_EXCP_PRIV          (1)
 109 #define UC32_EXCP_ITRAP         (2)
 110 #define UC32_EXCP_DTRAP         (3)
 111 #define UC32_EXCP_INTR          (4)
 112
 113 /* Return the current ASR value.  */
 114 target_ulong cpu_asr_read(CPUUniCore32State *env1);
 115 /* Set the ASR.  Note that some bits of mask must be all-set or all-clear.  */
 116 void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
 117
 118 /* UniCore-F64 system registers.  */
 119 #define UC32_UCF64_FPSCR                (31)
 120 #define UCF64_FPSCR_MASK                (0x27ffffff)
 121 #define UCF64_FPSCR_RND_MASK            (0x7)
 122 #define UCF64_FPSCR_RND(r)              (((r) >>  0) & UCF64_FPSCR_RND_MASK)
 123 #define UCF64_FPSCR_TRAPEN_MASK         (0x7f)
 124 #define UCF64_FPSCR_TRAPEN(r)           (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
 125 #define UCF64_FPSCR_FLAG_MASK           (0x3ff)
 126 #define UCF64_FPSCR_FLAG(r)             (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
 127 #define UCF64_FPSCR_FLAG_ZERO           (1 << 17)
 128 #define UCF64_FPSCR_FLAG_INFINITY       (1 << 18)
 129 #define UCF64_FPSCR_FLAG_INVALID        (1 << 19)
 130 #define UCF64_FPSCR_FLAG_UNDERFLOW      (1 << 20)
 131 #define UCF64_FPSCR_FLAG_OVERFLOW       (1 << 21)
 132 #define UCF64_FPSCR_FLAG_INEXACT        (1 << 22)
 133 #define UCF64_FPSCR_FLAG_HUGEINT        (1 << 23)
 134 #define UCF64_FPSCR_FLAG_DENORMAL       (1 << 24)
 135 #define UCF64_FPSCR_FLAG_UNIMP          (1 << 25)
 136 #define UCF64_FPSCR_FLAG_DIVZERO        (1 << 26)
 137
 138 #define UC32_HWCAP_CMOV                 4 /* 1 << 2 */
 139 #define UC32_HWCAP_UCF64                8 /* 1 << 3 */
 140
 141 #define cpu_signal_handler              uc32_cpu_signal_handler
 142
 143 int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 144
 145 /* MMU modes definitions */
 146 #define MMU_MODE0_SUFFIX _kernel
 147 #define MMU_MODE1_SUFFIX _user
 148 #define MMU_USER_IDX 1
 149 static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
 150 {
 151     return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
 152 }
 153
 154 typedef CPUUniCore32State CPUArchState;
 155 typedef UniCore32CPU ArchCPU;
 156
 157 #include "exec/cpu-all.h"
 158
 159 #define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU
 160 #define UNICORE32_CPU_TYPE_NAME(model) model UNICORE32_CPU_TYPE_SUFFIX
 161 #define CPU_RESOLVING_TYPE TYPE_UNICORE32_CPU
 162
 163 static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
 164                                         target_ulong *cs_base, uint32_t *flags)
 165 {
 166     *pc = env->regs[31];
 167     *cs_base = 0;
 168     *flags = 0;
 169     if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
 170         *flags |= (1 << 6);
 171     }
 172 }
 173
 174 bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 175                        MMUAccessType access_type, int mmu_idx,
 176                        bool probe, uintptr_t retaddr);
 177 void uc32_translate_init(void);
 178 void switch_mode(CPUUniCore32State *, int);
 179
 180 #endif /* UNICORE32_CPU_H */