2 * UniCore32 translation
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
14 #include "disas/disas.h"
15 #include "exec/exec-all.h"
18 #include "exec/cpu_ldst.h"
19 #include "exec/translator.h"
21 #include "exec/helper-proto.h"
22 #include "exec/helper-gen.h"
24 #include "trace-tcg.h"
28 /* internal defines */
29 typedef struct DisasContext
{
32 /* Nonzero if this instruction has been conditionally skipped. */
34 /* The label that will be jumped to when the instruction is skipped. */
36 struct TranslationBlock
*tb
;
37 int singlestep_enabled
;
38 #ifndef CONFIG_USER_ONLY
43 #ifndef CONFIG_USER_ONLY
44 #define IS_USER(s) (s->user)
49 /* is_jmp field values */
50 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
51 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
52 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
53 /* These instructions trap after executing, so defer them until after the
54 conditional executions state has been updated. */
55 #define DISAS_SYSCALL DISAS_TARGET_3
57 static TCGv_env cpu_env
;
58 static TCGv_i32 cpu_R
[32];
60 /* FIXME: These should be removed. */
61 static TCGv cpu_F0s
, cpu_F1s
;
62 static TCGv_i64 cpu_F0d
, cpu_F1d
;
64 #include "exec/gen-icount.h"
66 static const char *regnames
[] = {
67 "r00", "r01", "r02", "r03", "r04", "r05", "r06", "r07",
68 "r08", "r09", "r10", "r11", "r12", "r13", "r14", "r15",
69 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
70 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "pc" };
72 /* initialize TCG globals. */
73 void uc32_translate_init(void)
77 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
78 tcg_ctx
->tcg_env
= cpu_env
;
80 for (i
= 0; i
< 32; i
++) {
81 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
82 offsetof(CPUUniCore32State
, regs
[i
]), regnames
[i
]);
88 /* Allocate a temporary variable. */
89 static TCGv_i32
new_tmp(void)
92 return tcg_temp_new_i32();
95 /* Release a temporary variable. */
96 static void dead_tmp(TCGv tmp
)
102 static inline TCGv
load_cpu_offset(int offset
)
104 TCGv tmp
= new_tmp();
105 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
109 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
111 static inline void store_cpu_offset(TCGv var
, int offset
)
113 tcg_gen_st_i32(var
, cpu_env
, offset
);
117 #define store_cpu_field(var, name) \
118 store_cpu_offset(var, offsetof(CPUUniCore32State, name))
120 /* Set a variable to the value of a CPU register. */
121 static void load_reg_var(DisasContext
*s
, TCGv var
, int reg
)
125 /* normaly, since we updated PC */
127 tcg_gen_movi_i32(var
, addr
);
129 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
133 /* Create a new temporary and set it to the value of a CPU register. */
134 static inline TCGv
load_reg(DisasContext
*s
, int reg
)
136 TCGv tmp
= new_tmp();
137 load_reg_var(s
, tmp
, reg
);
141 /* Set a CPU register. The source must be a temporary and will be
143 static void store_reg(DisasContext
*s
, int reg
, TCGv var
)
146 tcg_gen_andi_i32(var
, var
, ~3);
147 s
->is_jmp
= DISAS_JUMP
;
149 tcg_gen_mov_i32(cpu_R
[reg
], var
);
153 /* Value extensions. */
154 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
155 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
156 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
157 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
159 #define UCOP_REG_M (((insn) >> 0) & 0x1f)
160 #define UCOP_REG_N (((insn) >> 19) & 0x1f)
161 #define UCOP_REG_D (((insn) >> 14) & 0x1f)
162 #define UCOP_REG_S (((insn) >> 9) & 0x1f)
163 #define UCOP_REG_LO (((insn) >> 14) & 0x1f)
164 #define UCOP_REG_HI (((insn) >> 9) & 0x1f)
165 #define UCOP_SH_OP (((insn) >> 6) & 0x03)
166 #define UCOP_SH_IM (((insn) >> 9) & 0x1f)
167 #define UCOP_OPCODES (((insn) >> 25) & 0x0f)
168 #define UCOP_IMM_9 (((insn) >> 0) & 0x1ff)
169 #define UCOP_IMM10 (((insn) >> 0) & 0x3ff)
170 #define UCOP_IMM14 (((insn) >> 0) & 0x3fff)
171 #define UCOP_COND (((insn) >> 25) & 0x0f)
172 #define UCOP_CMOV_COND (((insn) >> 19) & 0x0f)
173 #define UCOP_CPNUM (((insn) >> 10) & 0x0f)
174 #define UCOP_UCF64_FMT (((insn) >> 24) & 0x03)
175 #define UCOP_UCF64_FUNC (((insn) >> 6) & 0x0f)
176 #define UCOP_UCF64_COND (((insn) >> 6) & 0x0f)
178 #define UCOP_SET(i) ((insn) & (1 << (i)))
179 #define UCOP_SET_P UCOP_SET(28)
180 #define UCOP_SET_U UCOP_SET(27)
181 #define UCOP_SET_B UCOP_SET(26)
182 #define UCOP_SET_W UCOP_SET(25)
183 #define UCOP_SET_L UCOP_SET(24)
184 #define UCOP_SET_S UCOP_SET(24)
186 #define ILLEGAL cpu_abort(CPU(cpu), \
187 "Illegal UniCore32 instruction %x at line %d!", \
190 #ifndef CONFIG_USER_ONLY
191 static void disas_cp0_insn(CPUUniCore32State
*env
, DisasContext
*s
,
194 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
195 TCGv tmp
, tmp2
, tmp3
;
196 if ((insn
& 0xfe000000) == 0xe0000000) {
199 tcg_gen_movi_i32(tmp2
, UCOP_REG_N
);
200 tcg_gen_movi_i32(tmp3
, UCOP_IMM10
);
203 gen_helper_cp0_get(tmp
, cpu_env
, tmp2
, tmp3
);
204 store_reg(s
, UCOP_REG_D
, tmp
);
206 tmp
= load_reg(s
, UCOP_REG_D
);
207 gen_helper_cp0_set(cpu_env
, tmp
, tmp2
, tmp3
);
217 static void disas_ocd_insn(CPUUniCore32State
*env
, DisasContext
*s
,
220 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
223 if ((insn
& 0xff003fff) == 0xe1000400) {
225 * movc rd, pp.nn, #imm9
227 * nn: UCOP_REG_N (must be 0)
230 if (UCOP_REG_N
== 0) {
232 tcg_gen_movi_i32(tmp
, 0);
233 store_reg(s
, UCOP_REG_D
, tmp
);
239 if ((insn
& 0xff003fff) == 0xe0000401) {
241 * movc pp.nn, rn, #imm9
243 * nn: UCOP_REG_N (must be 1)
246 if (UCOP_REG_N
== 1) {
247 tmp
= load_reg(s
, UCOP_REG_D
);
248 gen_helper_cp1_putc(tmp
);
259 static inline void gen_set_asr(TCGv var
, uint32_t mask
)
261 TCGv tmp_mask
= tcg_const_i32(mask
);
262 gen_helper_asr_write(cpu_env
, var
, tmp_mask
);
263 tcg_temp_free_i32(tmp_mask
);
265 /* Set NZCV flags from the high 4 bits of var. */
266 #define gen_set_nzcv(var) gen_set_asr(var, ASR_NZCV)
268 static void gen_exception(int excp
)
270 TCGv tmp
= new_tmp();
271 tcg_gen_movi_i32(tmp
, excp
);
272 gen_helper_exception(cpu_env
, tmp
);
276 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
278 /* Set CF to the top bit of var. */
279 static void gen_set_CF_bit31(TCGv var
)
281 TCGv tmp
= new_tmp();
282 tcg_gen_shri_i32(tmp
, var
, 31);
287 /* Set N and Z flags from var. */
288 static inline void gen_logic_CC(TCGv var
)
290 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, NF
));
291 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, ZF
));
294 /* dest = T0 + T1 + CF. */
295 static void gen_add_carry(TCGv dest
, TCGv t0
, TCGv t1
)
298 tcg_gen_add_i32(dest
, t0
, t1
);
299 tmp
= load_cpu_field(CF
);
300 tcg_gen_add_i32(dest
, dest
, tmp
);
304 /* dest = T0 - T1 + CF - 1. */
305 static void gen_sub_carry(TCGv dest
, TCGv t0
, TCGv t1
)
308 tcg_gen_sub_i32(dest
, t0
, t1
);
309 tmp
= load_cpu_field(CF
);
310 tcg_gen_add_i32(dest
, dest
, tmp
);
311 tcg_gen_subi_i32(dest
, dest
, 1);
315 static void shifter_out_im(TCGv var
, int shift
)
317 TCGv tmp
= new_tmp();
319 tcg_gen_andi_i32(tmp
, var
, 1);
321 tcg_gen_shri_i32(tmp
, var
, shift
);
323 tcg_gen_andi_i32(tmp
, tmp
, 1);
330 /* Shift by immediate. Includes special handling for shift == 0. */
331 static inline void gen_uc32_shift_im(TCGv var
, int shiftop
, int shift
,
338 shifter_out_im(var
, 32 - shift
);
340 tcg_gen_shli_i32(var
, var
, shift
);
346 tcg_gen_shri_i32(var
, var
, 31);
349 tcg_gen_movi_i32(var
, 0);
352 shifter_out_im(var
, shift
- 1);
354 tcg_gen_shri_i32(var
, var
, shift
);
362 shifter_out_im(var
, shift
- 1);
367 tcg_gen_sari_i32(var
, var
, shift
);
369 case 3: /* ROR/RRX */
372 shifter_out_im(var
, shift
- 1);
374 tcg_gen_rotri_i32(var
, var
, shift
); break;
376 TCGv tmp
= load_cpu_field(CF
);
378 shifter_out_im(var
, 0);
380 tcg_gen_shri_i32(var
, var
, 1);
381 tcg_gen_shli_i32(tmp
, tmp
, 31);
382 tcg_gen_or_i32(var
, var
, tmp
);
388 static inline void gen_uc32_shift_reg(TCGv var
, int shiftop
,
389 TCGv shift
, int flags
)
394 gen_helper_shl_cc(var
, cpu_env
, var
, shift
);
397 gen_helper_shr_cc(var
, cpu_env
, var
, shift
);
400 gen_helper_sar_cc(var
, cpu_env
, var
, shift
);
403 gen_helper_ror_cc(var
, cpu_env
, var
, shift
);
409 gen_helper_shl(var
, var
, shift
);
412 gen_helper_shr(var
, var
, shift
);
415 gen_helper_sar(var
, var
, shift
);
418 tcg_gen_andi_i32(shift
, shift
, 0x1f);
419 tcg_gen_rotr_i32(var
, var
, shift
);
426 static void gen_test_cc(int cc
, TCGLabel
*label
)
434 tmp
= load_cpu_field(ZF
);
435 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
438 tmp
= load_cpu_field(ZF
);
439 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
442 tmp
= load_cpu_field(CF
);
443 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
446 tmp
= load_cpu_field(CF
);
447 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
450 tmp
= load_cpu_field(NF
);
451 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
454 tmp
= load_cpu_field(NF
);
455 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
458 tmp
= load_cpu_field(VF
);
459 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
462 tmp
= load_cpu_field(VF
);
463 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
465 case 8: /* hi: C && !Z */
466 inv
= gen_new_label();
467 tmp
= load_cpu_field(CF
);
468 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
470 tmp
= load_cpu_field(ZF
);
471 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
474 case 9: /* ls: !C || Z */
475 tmp
= load_cpu_field(CF
);
476 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
478 tmp
= load_cpu_field(ZF
);
479 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
481 case 10: /* ge: N == V -> N ^ V == 0 */
482 tmp
= load_cpu_field(VF
);
483 tmp2
= load_cpu_field(NF
);
484 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
486 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
488 case 11: /* lt: N != V -> N ^ V != 0 */
489 tmp
= load_cpu_field(VF
);
490 tmp2
= load_cpu_field(NF
);
491 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
493 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
495 case 12: /* gt: !Z && N == V */
496 inv
= gen_new_label();
497 tmp
= load_cpu_field(ZF
);
498 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
500 tmp
= load_cpu_field(VF
);
501 tmp2
= load_cpu_field(NF
);
502 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
504 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
507 case 13: /* le: Z || N != V */
508 tmp
= load_cpu_field(ZF
);
509 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
511 tmp
= load_cpu_field(VF
);
512 tmp2
= load_cpu_field(NF
);
513 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
515 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
518 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
524 static const uint8_t table_logic_cc
[16] = {
525 1, /* and */ 1, /* xor */ 0, /* sub */ 0, /* rsb */
526 0, /* add */ 0, /* adc */ 0, /* sbc */ 0, /* rsc */
527 1, /* andl */ 1, /* xorl */ 0, /* cmp */ 0, /* cmn */
528 1, /* orr */ 1, /* mov */ 1, /* bic */ 1, /* mvn */
531 /* Set PC state from an immediate address. */
532 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
534 s
->is_jmp
= DISAS_UPDATE
;
535 tcg_gen_movi_i32(cpu_R
[31], addr
& ~3);
538 /* Set PC state from var. var is marked as dead. */
539 static inline void gen_bx(DisasContext
*s
, TCGv var
)
541 s
->is_jmp
= DISAS_UPDATE
;
542 tcg_gen_andi_i32(cpu_R
[31], var
, ~3);
546 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv var
)
548 store_reg(s
, reg
, var
);
551 static inline TCGv
gen_ld8s(TCGv addr
, int index
)
553 TCGv tmp
= new_tmp();
554 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
558 static inline TCGv
gen_ld8u(TCGv addr
, int index
)
560 TCGv tmp
= new_tmp();
561 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
565 static inline TCGv
gen_ld16s(TCGv addr
, int index
)
567 TCGv tmp
= new_tmp();
568 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
572 static inline TCGv
gen_ld16u(TCGv addr
, int index
)
574 TCGv tmp
= new_tmp();
575 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
579 static inline TCGv
gen_ld32(TCGv addr
, int index
)
581 TCGv tmp
= new_tmp();
582 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
586 static inline void gen_st8(TCGv val
, TCGv addr
, int index
)
588 tcg_gen_qemu_st8(val
, addr
, index
);
592 static inline void gen_st16(TCGv val
, TCGv addr
, int index
)
594 tcg_gen_qemu_st16(val
, addr
, index
);
598 static inline void gen_st32(TCGv val
, TCGv addr
, int index
)
600 tcg_gen_qemu_st32(val
, addr
, index
);
604 static inline void gen_set_pc_im(uint32_t val
)
606 tcg_gen_movi_i32(cpu_R
[31], val
);
609 /* Force a TB lookup after an instruction that changes the CPU state. */
610 static inline void gen_lookup_tb(DisasContext
*s
)
612 tcg_gen_movi_i32(cpu_R
[31], s
->pc
& ~1);
613 s
->is_jmp
= DISAS_UPDATE
;
616 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
629 tcg_gen_addi_i32(var
, var
, val
);
633 offset
= load_reg(s
, UCOP_REG_M
);
634 gen_uc32_shift_im(offset
, UCOP_SH_OP
, UCOP_SH_IM
, 0);
636 tcg_gen_sub_i32(var
, var
, offset
);
638 tcg_gen_add_i32(var
, var
, offset
);
644 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
652 val
= (insn
& 0x1f) | ((insn
>> 4) & 0x3e0);
657 tcg_gen_addi_i32(var
, var
, val
);
661 offset
= load_reg(s
, UCOP_REG_M
);
663 tcg_gen_sub_i32(var
, var
, offset
);
665 tcg_gen_add_i32(var
, var
, offset
);
671 static inline long ucf64_reg_offset(int reg
)
674 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
675 + offsetof(CPU_DoubleU
, l
.upper
);
677 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
678 + offsetof(CPU_DoubleU
, l
.lower
);
682 #define ucf64_gen_ld32(reg) load_cpu_offset(ucf64_reg_offset(reg))
683 #define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
685 /* UniCore-F64 single load/store I_offset */
686 static void do_ucf64_ldst_i(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
688 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
693 addr
= load_reg(s
, UCOP_REG_N
);
694 if (!UCOP_SET_P
&& !UCOP_SET_W
) {
699 offset
= UCOP_IMM10
<< 2;
704 tcg_gen_addi_i32(addr
, addr
, offset
);
708 if (UCOP_SET_L
) { /* load */
709 tmp
= gen_ld32(addr
, IS_USER(s
));
710 ucf64_gen_st32(tmp
, UCOP_REG_D
);
712 tmp
= ucf64_gen_ld32(UCOP_REG_D
);
713 gen_st32(tmp
, addr
, IS_USER(s
));
717 offset
= UCOP_IMM10
<< 2;
722 tcg_gen_addi_i32(addr
, addr
, offset
);
726 store_reg(s
, UCOP_REG_N
, addr
);
732 /* UniCore-F64 load/store multiple words */
733 static void do_ucf64_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
735 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
741 if (UCOP_REG_D
!= 0) {
744 if (UCOP_REG_N
== 31) {
747 if ((insn
<< 24) == 0) {
751 addr
= load_reg(s
, UCOP_REG_N
);
754 for (i
= 0; i
< 8; i
++) {
761 if (UCOP_SET_P
) { /* pre increment */
762 tcg_gen_addi_i32(addr
, addr
, 4);
763 } /* unnecessary to do anything when post increment */
765 if (UCOP_SET_P
) { /* pre decrement */
766 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
767 } else { /* post decrement */
769 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
774 freg
= ((insn
>> 8) & 3) << 3; /* freg should be 0, 8, 16, 24 */
776 for (i
= 0, j
= 0; i
< 8; i
++, freg
++) {
781 if (UCOP_SET_L
) { /* load */
782 tmp
= gen_ld32(addr
, IS_USER(s
));
783 ucf64_gen_st32(tmp
, freg
);
785 tmp
= ucf64_gen_ld32(freg
);
786 gen_st32(tmp
, addr
, IS_USER(s
));
790 /* unnecessary to add after the last transfer */
792 tcg_gen_addi_i32(addr
, addr
, 4);
796 if (UCOP_SET_W
) { /* write back */
798 if (!UCOP_SET_P
) { /* post increment */
799 tcg_gen_addi_i32(addr
, addr
, 4);
800 } /* unnecessary to do anything when pre increment */
805 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
809 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
812 store_reg(s
, UCOP_REG_N
, addr
);
818 /* UniCore-F64 mrc/mcr */
819 static void do_ucf64_trans(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
821 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
824 if ((insn
& 0xfe0003ff) == 0xe2000000) {
825 /* control register */
826 if ((UCOP_REG_N
!= UC32_UCF64_FPSCR
) || (UCOP_REG_D
== 31)) {
832 gen_helper_ucf64_get_fpscr(tmp
, cpu_env
);
833 store_reg(s
, UCOP_REG_D
, tmp
);
836 tmp
= load_reg(s
, UCOP_REG_D
);
837 gen_helper_ucf64_set_fpscr(cpu_env
, tmp
);
843 if ((insn
& 0xfe0003ff) == 0xe0000000) {
844 /* general register */
845 if (UCOP_REG_D
== 31) {
848 if (UCOP_SET(24)) { /* MFF */
849 tmp
= ucf64_gen_ld32(UCOP_REG_N
);
850 store_reg(s
, UCOP_REG_D
, tmp
);
852 tmp
= load_reg(s
, UCOP_REG_D
);
853 ucf64_gen_st32(tmp
, UCOP_REG_N
);
857 if ((insn
& 0xfb000000) == 0xe9000000) {
859 if (UCOP_REG_D
!= 31) {
862 if (UCOP_UCF64_COND
& 0x8) {
867 tcg_gen_movi_i32(tmp
, UCOP_UCF64_COND
);
869 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
870 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
871 gen_helper_ucf64_cmpd(cpu_F0d
, cpu_F1d
, tmp
, cpu_env
);
873 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
874 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
875 gen_helper_ucf64_cmps(cpu_F0s
, cpu_F1s
, tmp
, cpu_env
);
883 /* UniCore-F64 convert instructions */
884 static void do_ucf64_fcvt(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
886 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
888 if (UCOP_UCF64_FMT
== 3) {
891 if (UCOP_REG_N
!= 0) {
894 switch (UCOP_UCF64_FUNC
) {
896 switch (UCOP_UCF64_FMT
) {
898 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
899 gen_helper_ucf64_df2sf(cpu_F0s
, cpu_F0d
, cpu_env
);
900 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
903 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
904 gen_helper_ucf64_si2sf(cpu_F0s
, cpu_F0s
, cpu_env
);
905 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
913 switch (UCOP_UCF64_FMT
) {
915 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
916 gen_helper_ucf64_sf2df(cpu_F0d
, cpu_F0s
, cpu_env
);
917 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
920 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
921 gen_helper_ucf64_si2df(cpu_F0d
, cpu_F0s
, cpu_env
);
922 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
930 switch (UCOP_UCF64_FMT
) {
932 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
933 gen_helper_ucf64_sf2si(cpu_F0s
, cpu_F0s
, cpu_env
);
934 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
937 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
938 gen_helper_ucf64_df2si(cpu_F0s
, cpu_F0d
, cpu_env
);
939 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
951 /* UniCore-F64 compare instructions */
952 static void do_ucf64_fcmp(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
954 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
959 if (UCOP_REG_D
!= 0) {
965 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
966 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
967 /* gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, cpu_env); */
969 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
970 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
971 /* gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, cpu_env); */
975 #define gen_helper_ucf64_movs(x, y) do { } while (0)
976 #define gen_helper_ucf64_movd(x, y) do { } while (0)
978 #define UCF64_OP1(name) do { \
979 if (UCOP_REG_N != 0) { \
982 switch (UCOP_UCF64_FMT) { \
984 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
985 ucf64_reg_offset(UCOP_REG_M)); \
986 gen_helper_ucf64_##name##s(cpu_F0s, cpu_F0s); \
987 tcg_gen_st_i32(cpu_F0s, cpu_env, \
988 ucf64_reg_offset(UCOP_REG_D)); \
991 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
992 ucf64_reg_offset(UCOP_REG_M)); \
993 gen_helper_ucf64_##name##d(cpu_F0d, cpu_F0d); \
994 tcg_gen_st_i64(cpu_F0d, cpu_env, \
995 ucf64_reg_offset(UCOP_REG_D)); \
1003 #define UCF64_OP2(name) do { \
1004 switch (UCOP_UCF64_FMT) { \
1006 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
1007 ucf64_reg_offset(UCOP_REG_N)); \
1008 tcg_gen_ld_i32(cpu_F1s, cpu_env, \
1009 ucf64_reg_offset(UCOP_REG_M)); \
1010 gen_helper_ucf64_##name##s(cpu_F0s, \
1011 cpu_F0s, cpu_F1s, cpu_env); \
1012 tcg_gen_st_i32(cpu_F0s, cpu_env, \
1013 ucf64_reg_offset(UCOP_REG_D)); \
1016 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
1017 ucf64_reg_offset(UCOP_REG_N)); \
1018 tcg_gen_ld_i64(cpu_F1d, cpu_env, \
1019 ucf64_reg_offset(UCOP_REG_M)); \
1020 gen_helper_ucf64_##name##d(cpu_F0d, \
1021 cpu_F0d, cpu_F1d, cpu_env); \
1022 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1023 ucf64_reg_offset(UCOP_REG_D)); \
1031 /* UniCore-F64 data processing */
1032 static void do_ucf64_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1034 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1036 if (UCOP_UCF64_FMT
== 3) {
1039 switch (UCOP_UCF64_FUNC
) {
1066 /* Disassemble an F64 instruction */
1067 static void disas_ucf64_insn(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1069 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1071 if (!UCOP_SET(29)) {
1073 do_ucf64_ldst_m(env
, s
, insn
);
1075 do_ucf64_ldst_i(env
, s
, insn
);
1079 switch ((insn
>> 26) & 0x3) {
1081 do_ucf64_datap(env
, s
, insn
);
1087 do_ucf64_fcvt(env
, s
, insn
);
1090 do_ucf64_fcmp(env
, s
, insn
);
1094 do_ucf64_trans(env
, s
, insn
);
1099 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1101 #ifndef CONFIG_USER_ONLY
1102 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1108 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint32_t dest
)
1110 if (use_goto_tb(s
, dest
)) {
1112 gen_set_pc_im(dest
);
1113 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
1115 gen_set_pc_im(dest
);
1120 static inline void gen_jmp(DisasContext
*s
, uint32_t dest
)
1122 if (unlikely(s
->singlestep_enabled
)) {
1123 /* An indirect jump so that we still trigger the debug exception. */
1126 gen_goto_tb(s
, 0, dest
);
1127 s
->is_jmp
= DISAS_TB_JUMP
;
1131 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
1132 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int bsr
, TCGv t0
)
1136 /* ??? This is also undefined in system mode. */
1141 tmp
= load_cpu_field(bsr
);
1142 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
1143 tcg_gen_andi_i32(t0
, t0
, mask
);
1144 tcg_gen_or_i32(tmp
, tmp
, t0
);
1145 store_cpu_field(tmp
, bsr
);
1147 gen_set_asr(t0
, mask
);
1154 /* Generate an old-style exception return. Marks pc as dead. */
1155 static void gen_exception_return(DisasContext
*s
, TCGv pc
)
1158 store_reg(s
, 31, pc
);
1159 tmp
= load_cpu_field(bsr
);
1160 gen_set_asr(tmp
, 0xffffffff);
1162 s
->is_jmp
= DISAS_UPDATE
;
1165 static void disas_coproc_insn(CPUUniCore32State
*env
, DisasContext
*s
,
1168 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1170 switch (UCOP_CPNUM
) {
1171 #ifndef CONFIG_USER_ONLY
1173 disas_cp0_insn(env
, s
, insn
);
1176 disas_ocd_insn(env
, s
, insn
);
1180 disas_ucf64_insn(env
, s
, insn
);
1183 /* Unknown coprocessor. */
1184 cpu_abort(CPU(cpu
), "Unknown coprocessor!");
1188 /* data processing instructions */
1189 static void do_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1191 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1196 if (UCOP_OPCODES
== 0x0f || UCOP_OPCODES
== 0x0d) {
1197 if (UCOP_SET(23)) { /* CMOV instructions */
1198 if ((UCOP_CMOV_COND
== 0xe) || (UCOP_CMOV_COND
== 0xf)) {
1201 /* if not always execute, we generate a conditional jump to
1203 s
->condlabel
= gen_new_label();
1204 gen_test_cc(UCOP_CMOV_COND
^ 1, s
->condlabel
);
1209 logic_cc
= table_logic_cc
[UCOP_OPCODES
] & (UCOP_SET_S
>> 24);
1213 /* immediate operand */
1216 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1219 tcg_gen_movi_i32(tmp2
, val
);
1220 if (logic_cc
&& UCOP_SH_IM
) {
1221 gen_set_CF_bit31(tmp2
);
1225 tmp2
= load_reg(s
, UCOP_REG_M
);
1227 tmp
= load_reg(s
, UCOP_REG_S
);
1228 gen_uc32_shift_reg(tmp2
, UCOP_SH_OP
, tmp
, logic_cc
);
1230 gen_uc32_shift_im(tmp2
, UCOP_SH_OP
, UCOP_SH_IM
, logic_cc
);
1234 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1235 tmp
= load_reg(s
, UCOP_REG_N
);
1240 switch (UCOP_OPCODES
) {
1242 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1246 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1249 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1253 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1256 if (UCOP_SET_S
&& UCOP_REG_D
== 31) {
1257 /* SUBS r31, ... is used for exception return. */
1261 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1262 gen_exception_return(s
, tmp
);
1265 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1267 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
1269 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1274 gen_helper_sub_cc(tmp
, cpu_env
, tmp2
, tmp
);
1276 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
1278 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1282 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1284 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1286 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1290 gen_helper_adc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1292 gen_add_carry(tmp
, tmp
, tmp2
);
1294 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1298 gen_helper_sbc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1300 gen_sub_carry(tmp
, tmp
, tmp2
);
1302 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1306 gen_helper_sbc_cc(tmp
, cpu_env
, tmp2
, tmp
);
1308 gen_sub_carry(tmp
, tmp2
, tmp
);
1310 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1314 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1321 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1328 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1334 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1339 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1343 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1346 if (logic_cc
&& UCOP_REG_D
== 31) {
1347 /* MOVS r31, ... is used for exception return. */
1351 gen_exception_return(s
, tmp2
);
1356 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1360 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1364 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1368 tcg_gen_not_i32(tmp2
, tmp2
);
1372 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1375 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1381 static void do_mult(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1383 TCGv tmp
, tmp2
, tmp3
, tmp4
;
1387 tmp
= load_reg(s
, UCOP_REG_M
);
1388 tmp2
= load_reg(s
, UCOP_REG_N
);
1390 tcg_gen_muls2_i32(tmp
, tmp2
, tmp
, tmp2
);
1392 tcg_gen_mulu2_i32(tmp
, tmp2
, tmp
, tmp2
);
1394 if (UCOP_SET(25)) { /* mult accumulate */
1395 tmp3
= load_reg(s
, UCOP_REG_LO
);
1396 tmp4
= load_reg(s
, UCOP_REG_HI
);
1397 tcg_gen_add2_i32(tmp
, tmp2
, tmp
, tmp2
, tmp3
, tmp4
);
1401 store_reg(s
, UCOP_REG_LO
, tmp
);
1402 store_reg(s
, UCOP_REG_HI
, tmp2
);
1405 tmp
= load_reg(s
, UCOP_REG_M
);
1406 tmp2
= load_reg(s
, UCOP_REG_N
);
1407 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
1411 tmp2
= load_reg(s
, UCOP_REG_S
);
1412 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1418 store_reg(s
, UCOP_REG_D
, tmp
);
1422 /* miscellaneous instructions */
1423 static void do_misc(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1425 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1429 if ((insn
& 0xffffffe0) == 0x10ffc120) {
1430 /* Trivial implementation equivalent to bx. */
1431 tmp
= load_reg(s
, UCOP_REG_M
);
1436 if ((insn
& 0xfbffc000) == 0x30ffc000) {
1437 /* PSR = immediate */
1440 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1443 tcg_gen_movi_i32(tmp
, val
);
1444 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1450 if ((insn
& 0xfbffffe0) == 0x12ffc020) {
1451 /* PSR.flag = reg */
1452 tmp
= load_reg(s
, UCOP_REG_M
);
1453 if (gen_set_psr(s
, ASR_NZCV
, UCOP_SET_B
, tmp
)) {
1459 if ((insn
& 0xfbffffe0) == 0x10ffc020) {
1461 tmp
= load_reg(s
, UCOP_REG_M
);
1462 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1468 if ((insn
& 0xfbf83fff) == 0x10f80000) {
1474 tmp
= load_cpu_field(bsr
);
1477 gen_helper_asr_read(tmp
, cpu_env
);
1479 store_reg(s
, UCOP_REG_D
, tmp
);
1483 if ((insn
& 0xfbf83fe0) == 0x12f80120) {
1485 tmp
= load_reg(s
, UCOP_REG_M
);
1488 tcg_gen_not_i32(tmp
, tmp
);
1490 tcg_gen_clzi_i32(tmp
, tmp
, 32);
1491 store_reg(s
, UCOP_REG_D
, tmp
);
1499 /* load/store I_offset and R_offset */
1500 static void do_ldst_ir(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1502 unsigned int mmu_idx
;
1506 tmp2
= load_reg(s
, UCOP_REG_N
);
1507 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1511 gen_add_data_offset(s
, insn
, tmp2
);
1517 tmp
= gen_ld8u(tmp2
, mmu_idx
);
1519 tmp
= gen_ld32(tmp2
, mmu_idx
);
1523 tmp
= load_reg(s
, UCOP_REG_D
);
1525 gen_st8(tmp
, tmp2
, mmu_idx
);
1527 gen_st32(tmp
, tmp2
, mmu_idx
);
1531 gen_add_data_offset(s
, insn
, tmp2
);
1532 store_reg(s
, UCOP_REG_N
, tmp2
);
1533 } else if (UCOP_SET_W
) {
1534 store_reg(s
, UCOP_REG_N
, tmp2
);
1539 /* Complete the load. */
1540 if (UCOP_REG_D
== 31) {
1543 store_reg(s
, UCOP_REG_D
, tmp
);
1548 /* SWP instruction */
1549 static void do_swap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1551 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1556 if ((insn
& 0xff003fe0) != 0x40000120) {
1560 /* ??? This is not really atomic. However we know
1561 we never have multiple CPUs running in parallel,
1562 so it is good enough. */
1563 addr
= load_reg(s
, UCOP_REG_N
);
1564 tmp
= load_reg(s
, UCOP_REG_M
);
1566 tmp2
= gen_ld8u(addr
, IS_USER(s
));
1567 gen_st8(tmp
, addr
, IS_USER(s
));
1569 tmp2
= gen_ld32(addr
, IS_USER(s
));
1570 gen_st32(tmp
, addr
, IS_USER(s
));
1573 store_reg(s
, UCOP_REG_D
, tmp2
);
1576 /* load/store hw/sb */
1577 static void do_ldst_hwsb(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1579 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1583 if (UCOP_SH_OP
== 0) {
1584 do_swap(env
, s
, insn
);
1588 addr
= load_reg(s
, UCOP_REG_N
);
1590 gen_add_datah_offset(s
, insn
, addr
);
1593 if (UCOP_SET_L
) { /* load */
1594 switch (UCOP_SH_OP
) {
1596 tmp
= gen_ld16u(addr
, IS_USER(s
));
1599 tmp
= gen_ld8s(addr
, IS_USER(s
));
1601 default: /* see do_swap */
1603 tmp
= gen_ld16s(addr
, IS_USER(s
));
1606 } else { /* store */
1607 if (UCOP_SH_OP
!= 1) {
1610 tmp
= load_reg(s
, UCOP_REG_D
);
1611 gen_st16(tmp
, addr
, IS_USER(s
));
1613 /* Perform base writeback before the loaded value to
1614 ensure correct behavior with overlapping index registers. */
1616 gen_add_datah_offset(s
, insn
, addr
);
1617 store_reg(s
, UCOP_REG_N
, addr
);
1618 } else if (UCOP_SET_W
) {
1619 store_reg(s
, UCOP_REG_N
, addr
);
1624 /* Complete the load. */
1625 store_reg(s
, UCOP_REG_D
, tmp
);
1629 /* load/store multiple words */
1630 static void do_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1632 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1633 unsigned int val
, i
, mmu_idx
;
1634 int j
, n
, reg
, user
, loaded_base
;
1643 /* XXX: store correct base if write back */
1645 if (UCOP_SET_B
) { /* S bit in instruction table */
1647 ILLEGAL
; /* only usable in supervisor mode */
1649 if (UCOP_SET(18) == 0) { /* pc reg */
1654 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1655 addr
= load_reg(s
, UCOP_REG_N
);
1657 /* compute total size */
1659 TCGV_UNUSED(loaded_var
);
1661 for (i
= 0; i
< 6; i
++) {
1666 for (i
= 9; i
< 19; i
++) {
1671 /* XXX: test invalid n == 0 case ? */
1675 tcg_gen_addi_i32(addr
, addr
, 4);
1677 /* post increment */
1682 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1684 /* post decrement */
1686 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1692 reg
= UCOP_SET(6) ? 16 : 0;
1693 for (i
= 0; i
< 19; i
++, reg
++) {
1698 if (UCOP_SET_L
) { /* load */
1699 tmp
= gen_ld32(addr
, mmu_idx
);
1703 tmp2
= tcg_const_i32(reg
);
1704 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
1705 tcg_temp_free_i32(tmp2
);
1707 } else if (reg
== UCOP_REG_N
) {
1711 store_reg(s
, reg
, tmp
);
1713 } else { /* store */
1715 /* special case: r31 = PC + 4 */
1718 tcg_gen_movi_i32(tmp
, val
);
1721 tmp2
= tcg_const_i32(reg
);
1722 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
1723 tcg_temp_free_i32(tmp2
);
1725 tmp
= load_reg(s
, reg
);
1727 gen_st32(tmp
, addr
, mmu_idx
);
1730 /* no need to add after the last transfer */
1732 tcg_gen_addi_i32(addr
, addr
, 4);
1736 if (UCOP_SET_W
) { /* write back */
1741 /* post increment */
1742 tcg_gen_addi_i32(addr
, addr
, 4);
1748 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1751 /* post decrement */
1752 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1755 store_reg(s
, UCOP_REG_N
, addr
);
1760 store_reg(s
, UCOP_REG_N
, loaded_var
);
1762 if (UCOP_SET_B
&& !user
) {
1763 /* Restore ASR from BSR. */
1764 tmp
= load_cpu_field(bsr
);
1765 gen_set_asr(tmp
, 0xffffffff);
1767 s
->is_jmp
= DISAS_UPDATE
;
1771 /* branch (and link) */
1772 static void do_branch(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1774 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1779 if (UCOP_COND
== 0xf) {
1783 if (UCOP_COND
!= 0xe) {
1784 /* if not always execute, we generate a conditional jump to
1786 s
->condlabel
= gen_new_label();
1787 gen_test_cc(UCOP_COND
^ 1, s
->condlabel
);
1791 val
= (int32_t)s
->pc
;
1794 tcg_gen_movi_i32(tmp
, val
);
1795 store_reg(s
, 30, tmp
);
1797 offset
= (((int32_t)insn
<< 8) >> 8);
1798 val
+= (offset
<< 2); /* unicore is pc+4 */
1802 static void disas_uc32_insn(CPUUniCore32State
*env
, DisasContext
*s
)
1804 UniCore32CPU
*cpu
= uc32_env_get_cpu(env
);
1807 insn
= cpu_ldl_code(env
, s
->pc
);
1810 /* UniCore instructions class:
1811 * AAAB BBBC xxxx xxxx xxxx xxxD xxEx xxxx
1812 * AAA : see switch case
1813 * BBBB : opcodes or cond or PUBW
1818 switch (insn
>> 29) {
1820 if (UCOP_SET(5) && UCOP_SET(8) && !UCOP_SET(28)) {
1821 do_mult(env
, s
, insn
);
1826 do_misc(env
, s
, insn
);
1830 if (((UCOP_OPCODES
>> 2) == 2) && !UCOP_SET_S
) {
1831 do_misc(env
, s
, insn
);
1834 do_datap(env
, s
, insn
);
1838 if (UCOP_SET(8) && UCOP_SET(5)) {
1839 do_ldst_hwsb(env
, s
, insn
);
1842 if (UCOP_SET(8) || UCOP_SET(5)) {
1846 do_ldst_ir(env
, s
, insn
);
1851 ILLEGAL
; /* extended instructions */
1853 do_ldst_m(env
, s
, insn
);
1856 do_branch(env
, s
, insn
);
1860 disas_coproc_insn(env
, s
, insn
);
1863 if (!UCOP_SET(28)) {
1864 disas_coproc_insn(env
, s
, insn
);
1867 if ((insn
& 0xff000000) == 0xff000000) { /* syscall */
1868 gen_set_pc_im(s
->pc
);
1869 s
->is_jmp
= DISAS_SYSCALL
;
1876 /* generate intermediate code for basic block 'tb'. */
1877 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
)
1879 CPUUniCore32State
*env
= cs
->env_ptr
;
1880 DisasContext dc1
, *dc
= &dc1
;
1881 target_ulong pc_start
;
1882 uint32_t next_page_start
;
1886 /* generate intermediate code */
1893 dc
->is_jmp
= DISAS_NEXT
;
1895 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
1897 cpu_F0s
= tcg_temp_new_i32();
1898 cpu_F1s
= tcg_temp_new_i32();
1899 cpu_F0d
= tcg_temp_new_i64();
1900 cpu_F1d
= tcg_temp_new_i64();
1901 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1903 max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
1904 if (max_insns
== 0) {
1905 max_insns
= CF_COUNT_MASK
;
1907 if (max_insns
> TCG_MAX_INSNS
) {
1908 max_insns
= TCG_MAX_INSNS
;
1911 #ifndef CONFIG_USER_ONLY
1912 if ((env
->uncached_asr
& ASR_M
) == ASR_MODE_USER
) {
1921 tcg_gen_insn_start(dc
->pc
);
1924 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
1925 gen_set_pc_im(dc
->pc
);
1926 gen_exception(EXCP_DEBUG
);
1927 dc
->is_jmp
= DISAS_JUMP
;
1928 /* The address covered by the breakpoint must be included in
1929 [tb->pc, tb->pc + tb->size) in order to for it to be
1930 properly cleared -- thus we increment the PC here so that
1931 the logic setting tb->size below does the right thing. */
1933 goto done_generating
;
1936 if (num_insns
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
1940 disas_uc32_insn(env
, dc
);
1943 fprintf(stderr
, "Internal resource leak before %08x\n", dc
->pc
);
1947 if (dc
->condjmp
&& !dc
->is_jmp
) {
1948 gen_set_label(dc
->condlabel
);
1951 /* Translation stops when a conditional branch is encountered.
1952 * Otherwise the subsequent code could get translated several times.
1953 * Also stop translation when a page boundary is reached. This
1954 * ensures prefetch aborts occur at the right place. */
1955 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
1956 !cs
->singlestep_enabled
&&
1958 dc
->pc
< next_page_start
&&
1959 num_insns
< max_insns
);
1961 if (tb_cflags(tb
) & CF_LAST_IO
) {
1963 /* FIXME: This can theoretically happen with self-modifying
1965 cpu_abort(cs
, "IO on conditional branch instruction");
1970 /* At this stage dc->condjmp will only be set when the skipped
1971 instruction was a conditional branch or trap, and the PC has
1972 already been written. */
1973 if (unlikely(cs
->singlestep_enabled
)) {
1974 /* Make sure the pc is updated, and raise a debug exception. */
1976 if (dc
->is_jmp
== DISAS_SYSCALL
) {
1977 gen_exception(UC32_EXCP_PRIV
);
1979 gen_exception(EXCP_DEBUG
);
1981 gen_set_label(dc
->condlabel
);
1983 if (dc
->condjmp
|| !dc
->is_jmp
) {
1984 gen_set_pc_im(dc
->pc
);
1987 if (dc
->is_jmp
== DISAS_SYSCALL
&& !dc
->condjmp
) {
1988 gen_exception(UC32_EXCP_PRIV
);
1990 gen_exception(EXCP_DEBUG
);
1993 /* While branches must always occur at the end of an IT block,
1994 there are a few other things that can cause us to terminate
1995 the TB in the middel of an IT block:
1996 - Exception generating instructions (bkpt, swi, undefined).
1998 - Hardware watchpoints.
1999 Hardware breakpoints have already been handled and skip this code.
2001 switch (dc
->is_jmp
) {
2003 gen_goto_tb(dc
, 1, dc
->pc
);
2008 /* indicate that the hash table must be used to find the next TB */
2012 /* nothing more to generate */
2015 gen_exception(UC32_EXCP_PRIV
);
2019 gen_set_label(dc
->condlabel
);
2020 gen_goto_tb(dc
, 1, dc
->pc
);
2026 gen_tb_end(tb
, num_insns
);
2029 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
2030 && qemu_log_in_addr_range(pc_start
)) {
2032 qemu_log("----------------\n");
2033 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
2034 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
, 0);
2039 tb
->size
= dc
->pc
- pc_start
;
2040 tb
->icount
= num_insns
;
2043 static const char *cpu_mode_names
[16] = {
2044 "USER", "REAL", "INTR", "PRIV", "UM14", "UM15", "UM16", "TRAP",
2045 "UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
2048 #undef UCF64_DUMP_STATE
2049 #ifdef UCF64_DUMP_STATE
2050 static void cpu_dump_state_ucf64(CPUUniCore32State
*env
, FILE *f
,
2051 fprintf_function cpu_fprintf
, int flags
)
2059 /* ??? This assumes float64 and double have the same layout.
2060 Oh well, it's only debug dumps. */
2066 for (i
= 0; i
< 16; i
++) {
2067 d
.d
= env
->ucf64
.regs
[i
];
2071 cpu_fprintf(f
, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
2072 i
* 2, (int)s0
.i
, s0
.s
,
2073 i
* 2 + 1, (int)s1
.i
, s1
.s
);
2074 cpu_fprintf(f
, " d%02d=%" PRIx64
"(%8g)\n",
2075 i
, (uint64_t)d0
.f64
, d0
.d
);
2077 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->ucf64
.xregs
[UC32_UCF64_FPSCR
]);
2080 #define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
2083 void uc32_cpu_dump_state(CPUState
*cs
, FILE *f
,
2084 fprintf_function cpu_fprintf
, int flags
)
2086 UniCore32CPU
*cpu
= UNICORE32_CPU(cs
);
2087 CPUUniCore32State
*env
= &cpu
->env
;
2091 for (i
= 0; i
< 32; i
++) {
2092 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
2094 cpu_fprintf(f
, "\n");
2096 cpu_fprintf(f
, " ");
2099 psr
= cpu_asr_read(env
);
2100 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %s\n",
2102 psr
& (1 << 31) ? 'N' : '-',
2103 psr
& (1 << 30) ? 'Z' : '-',
2104 psr
& (1 << 29) ? 'C' : '-',
2105 psr
& (1 << 28) ? 'V' : '-',
2106 cpu_mode_names
[psr
& 0xf]);
2108 cpu_dump_state_ucf64(env
, f
, cpu_fprintf
, flags
);
2111 void restore_state_to_opc(CPUUniCore32State
*env
, TranslationBlock
*tb
,
2114 env
->regs
[31] = data
[0];