target/xtensa/core-de212/xtensa-modules.c

   1 /* Xtensa configuration-specific ISA information.
   2
   3    Copyright (c) 2003-2015 Tensilica Inc.
   4
   5    Permission is hereby granted, free of charge, to any person obtaining
   6    a copy of this software and associated documentation files (the
   7    "Software"), to deal in the Software without restriction, including
   8    without limitation the rights to use, copy, modify, merge, publish,
   9    distribute, sublicense, and/or sell copies of the Software, and to
  10    permit persons to whom the Software is furnished to do so, subject to
  11    the following conditions:
  12
  13    The above copyright notice and this permission notice shall be included
  14    in all copies or substantial portions of the Software.
  15
  16    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  17    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  19    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  20    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
  23
  24 #include "qemu/osdep.h"
  25 #include "xtensa-isa.h"
  26 #include "xtensa-isa-internal.h"
  27
  28 \f
  29 /* Sysregs.  */
  30
  31 static xtensa_sysreg_internal sysregs[] = {
  32   { "LBEG", 0, 0 },
  33   { "LEND", 1, 0 },
  34   { "LCOUNT", 2, 0 },
  35   { "ACCLO", 16, 0 },
  36   { "ACCHI", 17, 0 },
  37   { "M0", 32, 0 },
  38   { "M1", 33, 0 },
  39   { "M2", 34, 0 },
  40   { "M3", 35, 0 },
  41   { "MMID", 89, 0 },
  42   { "DDR", 104, 0 },
  43   { "CONFIGID0", 176, 0 },
  44   { "CONFIGID1", 208, 0 },
  45   { "INTERRUPT", 226, 0 },
  46   { "INTCLEAR", 227, 0 },
  47   { "CCOUNT", 234, 0 },
  48   { "PRID", 235, 0 },
  49   { "ICOUNT", 236, 0 },
  50   { "CCOMPARE0", 240, 0 },
  51   { "CCOMPARE1", 241, 0 },
  52   { "CCOMPARE2", 242, 0 },
  53   { "VECBASE", 231, 0 },
  54   { "EPC1", 177, 0 },
  55   { "EPC2", 178, 0 },
  56   { "EPC3", 179, 0 },
  57   { "EPC4", 180, 0 },
  58   { "EPC5", 181, 0 },
  59   { "EPC6", 182, 0 },
  60   { "EPC7", 183, 0 },
  61   { "EXCSAVE1", 209, 0 },
  62   { "EXCSAVE2", 210, 0 },
  63   { "EXCSAVE3", 211, 0 },
  64   { "EXCSAVE4", 212, 0 },
  65   { "EXCSAVE5", 213, 0 },
  66   { "EXCSAVE6", 214, 0 },
  67   { "EXCSAVE7", 215, 0 },
  68   { "EPS2", 194, 0 },
  69   { "EPS3", 195, 0 },
  70   { "EPS4", 196, 0 },
  71   { "EPS5", 197, 0 },
  72   { "EPS6", 198, 0 },
  73   { "EPS7", 199, 0 },
  74   { "EXCCAUSE", 232, 0 },
  75   { "DEPC", 192, 0 },
  76   { "EXCVADDR", 238, 0 },
  77   { "WINDOWBASE", 72, 0 },
  78   { "WINDOWSTART", 73, 0 },
  79   { "SAR", 3, 0 },
  80   { "PS", 230, 0 },
  81   { "MISC0", 244, 0 },
  82   { "MISC1", 245, 0 },
  83   { "INTENABLE", 228, 0 },
  84   { "DBREAKA0", 144, 0 },
  85   { "DBREAKC0", 160, 0 },
  86   { "DBREAKA1", 145, 0 },
  87   { "DBREAKC1", 161, 0 },
  88   { "IBREAKA0", 128, 0 },
  89   { "IBREAKA1", 129, 0 },
  90   { "IBREAKENABLE", 96, 0 },
  91   { "ICOUNTLEVEL", 237, 0 },
  92   { "DEBUGCAUSE", 233, 0 },
  93   { "SCOMPARE1", 12, 0 },
  94   { "ATOMCTL", 99, 0 },
  95   { "EXPSTATE", 230, 1 }
  96 };
  97
  98 #define NUM_SYSREGS 64
  99 #define MAX_SPECIAL_REG 245
 100 #define MAX_USER_REG 230
 101
 102 \f
 103 /* Processor states.  */
 104
 105 static xtensa_state_internal states[] = {
 106   { "LCOUNT", 32, 0 },
 107   { "PC", 32, 0 },
 108   { "ICOUNT", 32, 0 },
 109   { "DDR", 32, 0 },
 110   { "INTERRUPT", 22, 0 },
 111   { "CCOUNT", 32, 0 },
 112   { "XTSYNC", 1, 0 },
 113   { "VECBASE", 22, 0 },
 114   { "EPC1", 32, 0 },
 115   { "EPC2", 32, 0 },
 116   { "EPC3", 32, 0 },
 117   { "EPC4", 32, 0 },
 118   { "EPC5", 32, 0 },
 119   { "EPC6", 32, 0 },
 120   { "EPC7", 32, 0 },
 121   { "EXCSAVE1", 32, 0 },
 122   { "EXCSAVE2", 32, 0 },
 123   { "EXCSAVE3", 32, 0 },
 124   { "EXCSAVE4", 32, 0 },
 125   { "EXCSAVE5", 32, 0 },
 126   { "EXCSAVE6", 32, 0 },
 127   { "EXCSAVE7", 32, 0 },
 128   { "EPS2", 13, 0 },
 129   { "EPS3", 13, 0 },
 130   { "EPS4", 13, 0 },
 131   { "EPS5", 13, 0 },
 132   { "EPS6", 13, 0 },
 133   { "EPS7", 13, 0 },
 134   { "EXCCAUSE", 6, 0 },
 135   { "PSINTLEVEL", 4, 0 },
 136   { "PSUM", 1, 0 },
 137   { "PSWOE", 1, 0 },
 138   { "PSEXCM", 1, 0 },
 139   { "DEPC", 32, 0 },
 140   { "EXCVADDR", 32, 0 },
 141   { "WindowBase", 3, 0 },
 142   { "WindowStart", 8, 0 },
 143   { "PSCALLINC", 2, 0 },
 144   { "PSOWB", 4, 0 },
 145   { "LBEG", 32, 0 },
 146   { "LEND", 32, 0 },
 147   { "SAR", 6, 0 },
 148   { "MISC0", 32, 0 },
 149   { "MISC1", 32, 0 },
 150   { "ACC", 40, 0 },
 151   { "InOCDMode", 1, 0 },
 152   { "INTENABLE", 22, 0 },
 153   { "DBREAKA0", 32, 0 },
 154   { "DBREAKC0", 8, 0 },
 155   { "DBREAKA1", 32, 0 },
 156   { "DBREAKC1", 8, 0 },
 157   { "IBREAKA0", 32, 0 },
 158   { "IBREAKA1", 32, 0 },
 159   { "IBREAKENABLE", 2, 0 },
 160   { "ICOUNTLEVEL", 4, 0 },
 161   { "DEBUGCAUSE", 6, 0 },
 162   { "DBNUM", 4, 0 },
 163   { "CCOMPARE0", 32, 0 },
 164   { "CCOMPARE1", 32, 0 },
 165   { "CCOMPARE2", 32, 0 },
 166   { "SCOMPARE1", 32, 0 },
 167   { "ATOMCTL", 6, 0 },
 168   { "ERI_RAW_INTERLOCK", 1, 0 },
 169   { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
 170 };
 171
 172 #define NUM_STATES 64
 173
 174 enum xtensa_state_id {
 175   STATE_LCOUNT,
 176   STATE_PC,
 177   STATE_ICOUNT,
 178   STATE_DDR,
 179   STATE_INTERRUPT,
 180   STATE_CCOUNT,
 181   STATE_XTSYNC,
 182   STATE_VECBASE,
 183   STATE_EPC1,
 184   STATE_EPC2,
 185   STATE_EPC3,
 186   STATE_EPC4,
 187   STATE_EPC5,
 188   STATE_EPC6,
 189   STATE_EPC7,
 190   STATE_EXCSAVE1,
 191   STATE_EXCSAVE2,
 192   STATE_EXCSAVE3,
 193   STATE_EXCSAVE4,
 194   STATE_EXCSAVE5,
 195   STATE_EXCSAVE6,
 196   STATE_EXCSAVE7,
 197   STATE_EPS2,
 198   STATE_EPS3,
 199   STATE_EPS4,
 200   STATE_EPS5,
 201   STATE_EPS6,
 202   STATE_EPS7,
 203   STATE_EXCCAUSE,
 204   STATE_PSINTLEVEL,
 205   STATE_PSUM,
 206   STATE_PSWOE,
 207   STATE_PSEXCM,
 208   STATE_DEPC,
 209   STATE_EXCVADDR,
 210   STATE_WindowBase,
 211   STATE_WindowStart,
 212   STATE_PSCALLINC,
 213   STATE_PSOWB,
 214   STATE_LBEG,
 215   STATE_LEND,
 216   STATE_SAR,
 217   STATE_MISC0,
 218   STATE_MISC1,
 219   STATE_ACC,
 220   STATE_InOCDMode,
 221   STATE_INTENABLE,
 222   STATE_DBREAKA0,
 223   STATE_DBREAKC0,
 224   STATE_DBREAKA1,
 225   STATE_DBREAKC1,
 226   STATE_IBREAKA0,
 227   STATE_IBREAKA1,
 228   STATE_IBREAKENABLE,
 229   STATE_ICOUNTLEVEL,
 230   STATE_DEBUGCAUSE,
 231   STATE_DBNUM,
 232   STATE_CCOMPARE0,
 233   STATE_CCOMPARE1,
 234   STATE_CCOMPARE2,
 235   STATE_SCOMPARE1,
 236   STATE_ATOMCTL,
 237   STATE_ERI_RAW_INTERLOCK,
 238   STATE_EXPSTATE
 239 };
 240
 241 \f
 242 /* Field definitions.  */
 243
 244 static unsigned
 245 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
 246 {
 247   unsigned tie_t = 0;
 248   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 249   return tie_t;
 250 }
 251
 252 static void
 253 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 254 {
 255   uint32 tie_t;
 256   tie_t = (val << 28) >> 28;
 257   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 258 }
 259
 260 static unsigned
 261 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
 262 {
 263   unsigned tie_t = 0;
 264   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 265   return tie_t;
 266 }
 267
 268 static void
 269 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 270 {
 271   uint32 tie_t;
 272   tie_t = (val << 28) >> 28;
 273   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 274 }
 275
 276 static unsigned
 277 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
 278 {
 279   unsigned tie_t = 0;
 280   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 281   return tie_t;
 282 }
 283
 284 static void
 285 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 286 {
 287   uint32 tie_t;
 288   tie_t = (val << 28) >> 28;
 289   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 290 }
 291
 292 static unsigned
 293 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
 294 {
 295   unsigned tie_t = 0;
 296   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
 297   return tie_t;
 298 }
 299
 300 static void
 301 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 302 {
 303   uint32 tie_t;
 304   tie_t = (val << 28) >> 28;
 305   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
 306 }
 307
 308 static unsigned
 309 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
 310 {
 311   unsigned tie_t = 0;
 312   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 313   return tie_t;
 314 }
 315
 316 static void
 317 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 318 {
 319   uint32 tie_t;
 320   tie_t = (val << 28) >> 28;
 321   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 322 }
 323
 324 static unsigned
 325 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
 326 {
 327   unsigned tie_t = 0;
 328   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 329   return tie_t;
 330 }
 331
 332 static void
 333 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 334 {
 335   uint32 tie_t;
 336   tie_t = (val << 28) >> 28;
 337   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 338 }
 339
 340 static unsigned
 341 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
 342 {
 343   unsigned tie_t = 0;
 344   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
 345   return tie_t;
 346 }
 347
 348 static void
 349 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 350 {
 351   uint32 tie_t;
 352   tie_t = (val << 30) >> 30;
 353   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
 354 }
 355
 356 static unsigned
 357 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
 358 {
 359   unsigned tie_t = 0;
 360   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
 361   return tie_t;
 362 }
 363
 364 static void
 365 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 366 {
 367   uint32 tie_t;
 368   tie_t = (val << 30) >> 30;
 369   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
 370 }
 371
 372 static unsigned
 373 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
 374 {
 375   unsigned tie_t = 0;
 376   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 377   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 378   return tie_t;
 379 }
 380
 381 static void
 382 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 383 {
 384   uint32 tie_t;
 385   tie_t = (val << 28) >> 28;
 386   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 387   tie_t = (val << 24) >> 28;
 388   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 389 }
 390
 391 static unsigned
 392 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
 393 {
 394   unsigned tie_t = 0;
 395   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
 396   return tie_t;
 397 }
 398
 399 static void
 400 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 401 {
 402   uint32 tie_t;
 403   tie_t = (val << 29) >> 29;
 404   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
 405 }
 406
 407 static unsigned
 408 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
 409 {
 410   unsigned tie_t = 0;
 411   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
 412   return tie_t;
 413 }
 414
 415 static void
 416 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 417 {
 418   uint32 tie_t;
 419   tie_t = (val << 31) >> 31;
 420   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
 421 }
 422
 423 static unsigned
 424 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
 425 {
 426   unsigned tie_t = 0;
 427   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
 428   return tie_t;
 429 }
 430
 431 static void
 432 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 433 {
 434   uint32 tie_t;
 435   tie_t = (val << 30) >> 30;
 436   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
 437 }
 438
 439 static unsigned
 440 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
 441 {
 442   unsigned tie_t = 0;
 443   tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
 444   return tie_t;
 445 }
 446
 447 static void
 448 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 449 {
 450   uint32 tie_t;
 451   tie_t = (val << 30) >> 30;
 452   insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
 453 }
 454
 455 static unsigned
 456 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
 457 {
 458   unsigned tie_t = 0;
 459   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
 460   return tie_t;
 461 }
 462
 463 static void
 464 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 465 {
 466   uint32 tie_t;
 467   tie_t = (val << 31) >> 31;
 468   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
 469 }
 470
 471 static unsigned
 472 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
 473 {
 474   unsigned tie_t = 0;
 475   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
 476   return tie_t;
 477 }
 478
 479 static void
 480 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 481 {
 482   uint32 tie_t;
 483   tie_t = (val << 30) >> 30;
 484   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
 485 }
 486
 487 static unsigned
 488 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
 489 {
 490   unsigned tie_t = 0;
 491   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 492   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 493   return tie_t;
 494 }
 495
 496 static void
 497 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 498 {
 499   uint32 tie_t;
 500   tie_t = (val << 28) >> 28;
 501   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 502   tie_t = (val << 24) >> 28;
 503   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 504 }
 505
 506 static unsigned
 507 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
 508 {
 509   unsigned tie_t = 0;
 510   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
 511   return tie_t;
 512 }
 513
 514 static void
 515 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 516 {
 517   uint32 tie_t;
 518   tie_t = (val << 29) >> 29;
 519   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
 520 }
 521
 522 static unsigned
 523 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
 524 {
 525   unsigned tie_t = 0;
 526   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 527   return tie_t;
 528 }
 529
 530 static void
 531 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 532 {
 533   uint32 tie_t;
 534   tie_t = (val << 28) >> 28;
 535   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 536 }
 537
 538 static unsigned
 539 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
 540 {
 541   unsigned tie_t = 0;
 542   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 543   return tie_t;
 544 }
 545
 546 static void
 547 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 548 {
 549   uint32 tie_t;
 550   tie_t = (val << 28) >> 28;
 551   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 552 }
 553
 554 static unsigned
 555 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
 556 {
 557   unsigned tie_t = 0;
 558   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 559   return tie_t;
 560 }
 561
 562 static void
 563 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 564 {
 565   uint32 tie_t;
 566   tie_t = (val << 28) >> 28;
 567   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 568 }
 569
 570 static unsigned
 571 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
 572 {
 573   unsigned tie_t = 0;
 574   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 575   return tie_t;
 576 }
 577
 578 static void
 579 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 580 {
 581   uint32 tie_t;
 582   tie_t = (val << 28) >> 28;
 583   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 584 }
 585
 586 static unsigned
 587 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
 588 {
 589   unsigned tie_t = 0;
 590   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
 591   return tie_t;
 592 }
 593
 594 static void
 595 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 596 {
 597   uint32 tie_t;
 598   tie_t = (val << 31) >> 31;
 599   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
 600 }
 601
 602 static unsigned
 603 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
 604 {
 605   unsigned tie_t = 0;
 606   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
 607   return tie_t;
 608 }
 609
 610 static void
 611 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 612 {
 613   uint32 tie_t;
 614   tie_t = (val << 31) >> 31;
 615   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
 616 }
 617
 618 static unsigned
 619 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
 620 {
 621   unsigned tie_t = 0;
 622   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 623   return tie_t;
 624 }
 625
 626 static void
 627 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 628 {
 629   uint32 tie_t;
 630   tie_t = (val << 28) >> 28;
 631   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 632 }
 633
 634 static unsigned
 635 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
 636 {
 637   unsigned tie_t = 0;
 638   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 639   return tie_t;
 640 }
 641
 642 static void
 643 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 644 {
 645   uint32 tie_t;
 646   tie_t = (val << 28) >> 28;
 647   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 648 }
 649
 650 static unsigned
 651 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
 652 {
 653   unsigned tie_t = 0;
 654   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
 655   return tie_t;
 656 }
 657
 658 static void
 659 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 660 {
 661   uint32 tie_t;
 662   tie_t = (val << 31) >> 31;
 663   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
 664 }
 665
 666 static unsigned
 667 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
 668 {
 669   unsigned tie_t = 0;
 670   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
 671   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 672   return tie_t;
 673 }
 674
 675 static void
 676 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 677 {
 678   uint32 tie_t;
 679   tie_t = (val << 28) >> 28;
 680   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 681   tie_t = (val << 27) >> 31;
 682   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
 683 }
 684
 685 static unsigned
 686 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
 687 {
 688   unsigned tie_t = 0;
 689   tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
 690   return tie_t;
 691 }
 692
 693 static void
 694 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 695 {
 696   uint32 tie_t;
 697   tie_t = (val << 20) >> 20;
 698   insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
 699 }
 700
 701 static unsigned
 702 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
 703 {
 704   unsigned tie_t = 0;
 705   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
 706   return tie_t;
 707 }
 708
 709 static void
 710 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 711 {
 712   uint32 tie_t;
 713   tie_t = (val << 24) >> 24;
 714   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
 715 }
 716
 717 static unsigned
 718 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
 719 {
 720   unsigned tie_t = 0;
 721   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 722   return tie_t;
 723 }
 724
 725 static void
 726 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 727 {
 728   uint32 tie_t;
 729   tie_t = (val << 28) >> 28;
 730   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 731 }
 732
 733 static unsigned
 734 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
 735 {
 736   unsigned tie_t = 0;
 737   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 738   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
 739   return tie_t;
 740 }
 741
 742 static void
 743 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 744 {
 745   uint32 tie_t;
 746   tie_t = (val << 24) >> 24;
 747   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
 748   tie_t = (val << 20) >> 28;
 749   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 750 }
 751
 752 static unsigned
 753 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
 754 {
 755   unsigned tie_t = 0;
 756   tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
 757   return tie_t;
 758 }
 759
 760 static void
 761 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 762 {
 763   uint32 tie_t;
 764   tie_t = (val << 16) >> 16;
 765   insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
 766 }
 767
 768 static unsigned
 769 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
 770 {
 771   unsigned tie_t = 0;
 772   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
 773   return tie_t;
 774 }
 775
 776 static void
 777 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 778 {
 779   uint32 tie_t;
 780   tie_t = (val << 14) >> 14;
 781   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
 782 }
 783
 784 static unsigned
 785 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
 786 {
 787   unsigned tie_t = 0;
 788   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 789   return tie_t;
 790 }
 791
 792 static void
 793 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 794 {
 795   uint32 tie_t;
 796   tie_t = (val << 28) >> 28;
 797   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 798 }
 799
 800 static unsigned
 801 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
 802 {
 803   unsigned tie_t = 0;
 804   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
 805   return tie_t;
 806 }
 807
 808 static void
 809 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 810 {
 811   uint32 tie_t;
 812   tie_t = (val << 31) >> 31;
 813   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
 814 }
 815
 816 static unsigned
 817 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
 818 {
 819   unsigned tie_t = 0;
 820   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 821   return tie_t;
 822 }
 823
 824 static void
 825 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 826 {
 827   uint32 tie_t;
 828   tie_t = (val << 31) >> 31;
 829   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 830 }
 831
 832 static unsigned
 833 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
 834 {
 835   unsigned tie_t = 0;
 836   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
 837   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 838   return tie_t;
 839 }
 840
 841 static void
 842 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 843 {
 844   uint32 tie_t;
 845   tie_t = (val << 28) >> 28;
 846   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 847   tie_t = (val << 27) >> 31;
 848   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
 849 }
 850
 851 static unsigned
 852 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
 853 {
 854   unsigned tie_t = 0;
 855   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
 856   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 857   return tie_t;
 858 }
 859
 860 static void
 861 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 862 {
 863   uint32 tie_t;
 864   tie_t = (val << 28) >> 28;
 865   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 866   tie_t = (val << 27) >> 31;
 867   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
 868 }
 869
 870 static unsigned
 871 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
 872 {
 873   unsigned tie_t = 0;
 874   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
 875   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 876   return tie_t;
 877 }
 878
 879 static void
 880 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 881 {
 882   uint32 tie_t;
 883   tie_t = (val << 28) >> 28;
 884   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 885   tie_t = (val << 27) >> 31;
 886   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
 887 }
 888
 889 static unsigned
 890 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
 891 {
 892   unsigned tie_t = 0;
 893   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 894   return tie_t;
 895 }
 896
 897 static void
 898 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 899 {
 900   uint32 tie_t;
 901   tie_t = (val << 31) >> 31;
 902   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 903 }
 904
 905 static unsigned
 906 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
 907 {
 908   unsigned tie_t = 0;
 909   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
 910   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 911   return tie_t;
 912 }
 913
 914 static void
 915 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 916 {
 917   uint32 tie_t;
 918   tie_t = (val << 28) >> 28;
 919   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 920   tie_t = (val << 27) >> 31;
 921   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
 922 }
 923
 924 static unsigned
 925 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
 926 {
 927   unsigned tie_t = 0;
 928   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 929   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 930   return tie_t;
 931 }
 932
 933 static void
 934 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 935 {
 936   uint32 tie_t;
 937   tie_t = (val << 28) >> 28;
 938   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 939   tie_t = (val << 24) >> 28;
 940   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 941 }
 942
 943 static unsigned
 944 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
 945 {
 946   unsigned tie_t = 0;
 947   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 948   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 949   return tie_t;
 950 }
 951
 952 static void
 953 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 954 {
 955   uint32 tie_t;
 956   tie_t = (val << 28) >> 28;
 957   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 958   tie_t = (val << 24) >> 28;
 959   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 960 }
 961
 962 static unsigned
 963 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
 964 {
 965   unsigned tie_t = 0;
 966   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 967   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 968   return tie_t;
 969 }
 970
 971 static void
 972 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 973 {
 974   uint32 tie_t;
 975   tie_t = (val << 28) >> 28;
 976   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 977   tie_t = (val << 24) >> 28;
 978   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 979 }
 980
 981 static unsigned
 982 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
 983 {
 984   unsigned tie_t = 0;
 985   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 986   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 987   return tie_t;
 988 }
 989
 990 static void
 991 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 992 {
 993   uint32 tie_t;
 994   tie_t = (val << 28) >> 28;
 995   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 996   tie_t = (val << 24) >> 28;
 997   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 998 }
 999
1000 static unsigned
1001 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1002 {
1003   unsigned tie_t = 0;
1004   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1005   return tie_t;
1006 }
1007
1008 static void
1009 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1010 {
1011   uint32 tie_t;
1012   tie_t = (val << 28) >> 28;
1013   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1014 }
1015
1016 static unsigned
1017 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1018 {
1019   unsigned tie_t = 0;
1020   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1021   return tie_t;
1022 }
1023
1024 static void
1025 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1026 {
1027   uint32 tie_t;
1028   tie_t = (val << 28) >> 28;
1029   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1030 }
1031
1032 static unsigned
1033 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1034 {
1035   unsigned tie_t = 0;
1036   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1037   return tie_t;
1038 }
1039
1040 static void
1041 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1042 {
1043   uint32 tie_t;
1044   tie_t = (val << 28) >> 28;
1045   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1046 }
1047
1048 static unsigned
1049 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1050 {
1051   unsigned tie_t = 0;
1052   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1053   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1054   return tie_t;
1055 }
1056
1057 static void
1058 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1059 {
1060   uint32 tie_t;
1061   tie_t = (val << 30) >> 30;
1062   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1063   tie_t = (val << 28) >> 30;
1064   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1065 }
1066
1067 static unsigned
1068 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1069 {
1070   unsigned tie_t = 0;
1071   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1072   return tie_t;
1073 }
1074
1075 static void
1076 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1077 {
1078   uint32 tie_t;
1079   tie_t = (val << 31) >> 31;
1080   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1081 }
1082
1083 static unsigned
1084 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1085 {
1086   unsigned tie_t = 0;
1087   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1088   return tie_t;
1089 }
1090
1091 static void
1092 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1093 {
1094   uint32 tie_t;
1095   tie_t = (val << 28) >> 28;
1096   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1097 }
1098
1099 static unsigned
1100 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1101 {
1102   unsigned tie_t = 0;
1103   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1104   return tie_t;
1105 }
1106
1107 static void
1108 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1109 {
1110   uint32 tie_t;
1111   tie_t = (val << 28) >> 28;
1112   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1113 }
1114
1115 static unsigned
1116 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1117 {
1118   unsigned tie_t = 0;
1119   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1120   return tie_t;
1121 }
1122
1123 static void
1124 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1125 {
1126   uint32 tie_t;
1127   tie_t = (val << 30) >> 30;
1128   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1129 }
1130
1131 static unsigned
1132 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1133 {
1134   unsigned tie_t = 0;
1135   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1136   return tie_t;
1137 }
1138
1139 static void
1140 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1141 {
1142   uint32 tie_t;
1143   tie_t = (val << 30) >> 30;
1144   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1145 }
1146
1147 static unsigned
1148 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1149 {
1150   unsigned tie_t = 0;
1151   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1152   return tie_t;
1153 }
1154
1155 static void
1156 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1157 {
1158   uint32 tie_t;
1159   tie_t = (val << 28) >> 28;
1160   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1161 }
1162
1163 static unsigned
1164 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1165 {
1166   unsigned tie_t = 0;
1167   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1168   return tie_t;
1169 }
1170
1171 static void
1172 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1173 {
1174   uint32 tie_t;
1175   tie_t = (val << 28) >> 28;
1176   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1177 }
1178
1179 static unsigned
1180 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1181 {
1182   unsigned tie_t = 0;
1183   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1184   return tie_t;
1185 }
1186
1187 static void
1188 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1189 {
1190   uint32 tie_t;
1191   tie_t = (val << 29) >> 29;
1192   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1193 }
1194
1195 static unsigned
1196 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1197 {
1198   unsigned tie_t = 0;
1199   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1200   return tie_t;
1201 }
1202
1203 static void
1204 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1205 {
1206   uint32 tie_t;
1207   tie_t = (val << 29) >> 29;
1208   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1209 }
1210
1211 static unsigned
1212 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1213 {
1214   unsigned tie_t = 0;
1215   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1216   return tie_t;
1217 }
1218
1219 static void
1220 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1221 {
1222   uint32 tie_t;
1223   tie_t = (val << 31) >> 31;
1224   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1225 }
1226
1227 static unsigned
1228 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1229 {
1230   unsigned tie_t = 0;
1231   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1232   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1233   return tie_t;
1234 }
1235
1236 static void
1237 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1238 {
1239   uint32 tie_t;
1240   tie_t = (val << 28) >> 28;
1241   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1242   tie_t = (val << 26) >> 30;
1243   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1244 }
1245
1246 static unsigned
1247 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1248 {
1249   unsigned tie_t = 0;
1250   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1251   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1252   return tie_t;
1253 }
1254
1255 static void
1256 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1257 {
1258   uint32 tie_t;
1259   tie_t = (val << 28) >> 28;
1260   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1261   tie_t = (val << 26) >> 30;
1262   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1263 }
1264
1265 static unsigned
1266 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1267 {
1268   unsigned tie_t = 0;
1269   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1270   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1271   return tie_t;
1272 }
1273
1274 static void
1275 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1276 {
1277   uint32 tie_t;
1278   tie_t = (val << 28) >> 28;
1279   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1280   tie_t = (val << 25) >> 29;
1281   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1282 }
1283
1284 static unsigned
1285 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1286 {
1287   unsigned tie_t = 0;
1288   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1289   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1290   return tie_t;
1291 }
1292
1293 static void
1294 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1295 {
1296   uint32 tie_t;
1297   tie_t = (val << 28) >> 28;
1298   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1299   tie_t = (val << 25) >> 29;
1300   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1301 }
1302
1303 static unsigned
1304 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1305 {
1306   unsigned tie_t = 0;
1307   tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1308   return tie_t;
1309 }
1310
1311 static void
1312 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1313 {
1314   uint32 tie_t;
1315   tie_t = (val << 31) >> 31;
1316   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1317 }
1318
1319 static unsigned
1320 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1321 {
1322   unsigned tie_t = 0;
1323   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1324   return tie_t;
1325 }
1326
1327 static void
1328 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1329 {
1330   uint32 tie_t;
1331   tie_t = (val << 31) >> 31;
1332   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1333 }
1334
1335 static unsigned
1336 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1337 {
1338   unsigned tie_t = 0;
1339   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1340   return tie_t;
1341 }
1342
1343 static void
1344 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1345 {
1346   uint32 tie_t;
1347   tie_t = (val << 31) >> 31;
1348   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1349 }
1350
1351 static unsigned
1352 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1353 {
1354   unsigned tie_t = 0;
1355   tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1356   return tie_t;
1357 }
1358
1359 static void
1360 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1361 {
1362   uint32 tie_t;
1363   tie_t = (val << 31) >> 31;
1364   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1365 }
1366
1367 static unsigned
1368 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1369 {
1370   unsigned tie_t = 0;
1371   tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1372   return tie_t;
1373 }
1374
1375 static void
1376 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1377 {
1378   uint32 tie_t;
1379   tie_t = (val << 17) >> 17;
1380   insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1381 }
1382
1383 static unsigned
1384 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1385 {
1386   unsigned tie_t = 0;
1387   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1388   return tie_t;
1389 }
1390
1391 static void
1392 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1393 {
1394   uint32 tie_t;
1395   tie_t = (val << 14) >> 14;
1396   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1397 }
1398
1399 static unsigned
1400 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
1401 {
1402   unsigned tie_t = 0;
1403   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1404   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1405   return tie_t;
1406 }
1407
1408 static void
1409 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1410 {
1411   uint32 tie_t;
1412   tie_t = (val << 28) >> 28;
1413   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1414   tie_t = (val << 27) >> 31;
1415   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1416 }
1417
1418 static unsigned
1419 Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
1420 {
1421   unsigned tie_t = 0;
1422   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1423   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1424   return tie_t;
1425 }
1426
1427 static void
1428 Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1429 {
1430   uint32 tie_t;
1431   tie_t = (val << 28) >> 28;
1432   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1433   tie_t = (val << 27) >> 31;
1434   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1435 }
1436
1437 static unsigned
1438 Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
1439 {
1440   unsigned tie_t = 0;
1441   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
1442   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1443   return tie_t;
1444 }
1445
1446 static void
1447 Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1448 {
1449   uint32 tie_t;
1450   tie_t = (val << 28) >> 28;
1451   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1452   tie_t = (val << 27) >> 31;
1453   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
1454 }
1455
1456 static unsigned
1457 Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
1458 {
1459   unsigned tie_t = 0;
1460   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1461   return tie_t;
1462 }
1463
1464 static void
1465 Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1466 {
1467   uint32 tie_t;
1468   tie_t = (val << 29) >> 29;
1469   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1470 }
1471
1472 static unsigned
1473 Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
1474 {
1475   unsigned tie_t = 0;
1476   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
1477   return tie_t;
1478 }
1479
1480 static void
1481 Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1482 {
1483   uint32 tie_t;
1484   tie_t = (val << 29) >> 29;
1485   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
1486 }
1487
1488 static void
1489 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1490                     uint32 val ATTRIBUTE_UNUSED)
1491 {
1492   /* Do nothing.  */
1493 }
1494
1495 static unsigned
1496 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1497 {
1498   return 0;
1499 }
1500
1501 static unsigned
1502 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1503 {
1504   return 4;
1505 }
1506
1507 static unsigned
1508 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1509 {
1510   return 8;
1511 }
1512
1513 static unsigned
1514 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1515 {
1516   return 12;
1517 }
1518
1519 static unsigned
1520 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1521 {
1522   return 0;
1523 }
1524
1525 static unsigned
1526 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1527 {
1528   return 1;
1529 }
1530
1531 static unsigned
1532 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1533 {
1534   return 2;
1535 }
1536
1537 static unsigned
1538 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1539 {
1540   return 3;
1541 }
1542
1543 enum xtensa_field_id {
1544   FIELD_t,
1545   FIELD_bbi4,
1546   FIELD_bbi,
1547   FIELD_imm12,
1548   FIELD_imm8,
1549   FIELD_s,
1550   FIELD_imm12b,
1551   FIELD_imm16,
1552   FIELD_m,
1553   FIELD_n,
1554   FIELD_offset,
1555   FIELD_op0,
1556   FIELD_op1,
1557   FIELD_op2,
1558   FIELD_r,
1559   FIELD_sa4,
1560   FIELD_sae4,
1561   FIELD_sae,
1562   FIELD_sal,
1563   FIELD_sargt,
1564   FIELD_sas4,
1565   FIELD_sas,
1566   FIELD_sr,
1567   FIELD_st,
1568   FIELD_thi3,
1569   FIELD_imm4,
1570   FIELD_mn,
1571   FIELD_i,
1572   FIELD_imm6lo,
1573   FIELD_imm6hi,
1574   FIELD_imm7lo,
1575   FIELD_imm7hi,
1576   FIELD_z,
1577   FIELD_imm6,
1578   FIELD_imm7,
1579   FIELD_r3,
1580   FIELD_rbit2,
1581   FIELD_rhi,
1582   FIELD_t3,
1583   FIELD_tbit2,
1584   FIELD_tlo,
1585   FIELD_w,
1586   FIELD_y,
1587   FIELD_x,
1588   FIELD_xt_wbr15_imm,
1589   FIELD_xt_wbr18_imm,
1590   FIELD_bitindex,
1591   FIELD_s3to1,
1592   FIELD__ar0,
1593   FIELD__ar4,
1594   FIELD__ar8,
1595   FIELD__ar12,
1596   FIELD__mr0,
1597   FIELD__mr1,
1598   FIELD__mr2,
1599   FIELD__mr3
1600 };
1601
1602 \f
1603 /* Functional units.  */
1604
1605 #define funcUnits 0
1606
1607 \f
1608 /* Register files.  */
1609
1610 enum xtensa_regfile_id {
1611   REGFILE_AR,
1612   REGFILE_MR
1613 };
1614
1615 static xtensa_regfile_internal regfiles[] = {
1616   { "AR", "a", REGFILE_AR, 32, 32 },
1617   { "MR", "m", REGFILE_MR, 32, 4 }
1618 };
1619
1620 \f
1621 /* Interfaces.  */
1622
1623 static xtensa_interface_internal interfaces[] = {
1624   { "ERI_RD_Out", 14, 0, 0, 'o' },
1625   { "ERI_RD_In", 32, 0, 1, 'i' },
1626   { "ERI_RD_Rdy", 1, 0, 0, 'i' },
1627   { "ERI_WR_Out", 46, 0, 2, 'o' },
1628   { "ERI_WR_In", 1, 0, 3, 'i' },
1629   { "IMPWIRE", 32, 0, 4, 'i' }
1630 };
1631
1632 enum xtensa_interface_id {
1633   INTERFACE_ERI_RD_Out,
1634   INTERFACE_ERI_RD_In,
1635   INTERFACE_ERI_RD_Rdy,
1636   INTERFACE_ERI_WR_Out,
1637   INTERFACE_ERI_WR_In,
1638   INTERFACE_IMPWIRE
1639 };
1640
1641
1642 /* Constant tables.  */
1643
1644 /* constant table ai4c */
1645 static const unsigned CONST_TBL_ai4c_0[] = {
1646   0xffffffff,
1647   0x1,
1648   0x2,
1649   0x3,
1650   0x4,
1651   0x5,
1652   0x6,
1653   0x7,
1654   0x8,
1655   0x9,
1656   0xa,
1657   0xb,
1658   0xc,
1659   0xd,
1660   0xe,
1661   0xf,
1662   0
1663 };
1664
1665 /* constant table b4c */
1666 static const unsigned CONST_TBL_b4c_0[] = {
1667   0xffffffff,
1668   0x1,
1669   0x2,
1670   0x3,
1671   0x4,
1672   0x5,
1673   0x6,
1674   0x7,
1675   0x8,
1676   0xa,
1677   0xc,
1678   0x10,
1679   0x20,
1680   0x40,
1681   0x80,
1682   0x100,
1683   0
1684 };
1685
1686 /* constant table b4cu */
1687 static const unsigned CONST_TBL_b4cu_0[] = {
1688   0x8000,
1689   0x10000,
1690   0x2,
1691   0x3,
1692   0x4,
1693   0x5,
1694   0x6,
1695   0x7,
1696   0x8,
1697   0xa,
1698   0xc,
1699   0x10,
1700   0x20,
1701   0x40,
1702   0x80,
1703   0x100,
1704   0
1705 };
1706
1707 \f
1708 /* Instruction operands.  */
1709
1710 static int
1711 OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
1712 {
1713   *valp += 2;
1714   return 0;
1715 }
1716
1717 static int
1718 OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
1719 {
1720   int error;
1721   error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
1722   *valp = *valp & 1;
1723   return error;
1724 }
1725
1726 static int
1727 OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
1728 {
1729   unsigned soffsetx4_out_0;
1730   unsigned soffsetx4_in_0;
1731   soffsetx4_in_0 = *valp & 0x3ffff;
1732   soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
1733   *valp = soffsetx4_out_0;
1734   return 0;
1735 }
1736
1737 static int
1738 OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
1739 {
1740   unsigned soffsetx4_in_0;
1741   unsigned soffsetx4_out_0;
1742   soffsetx4_out_0 = *valp;
1743   soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
1744   *valp = soffsetx4_in_0;
1745   return 0;
1746 }
1747
1748 static int
1749 OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
1750 {
1751   unsigned uimm12x8_out_0;
1752   unsigned uimm12x8_in_0;
1753   uimm12x8_in_0 = *valp & 0xfff;
1754   uimm12x8_out_0 = uimm12x8_in_0 << 3;
1755   *valp = uimm12x8_out_0;
1756   return 0;
1757 }
1758
1759 static int
1760 OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
1761 {
1762   unsigned uimm12x8_in_0;
1763   unsigned uimm12x8_out_0;
1764   uimm12x8_out_0 = *valp;
1765   uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
1766   *valp = uimm12x8_in_0;
1767   return 0;
1768 }
1769
1770 static int
1771 OperandSem_opnd_sem_simm4_decode (uint32 *valp)
1772 {
1773   unsigned simm4_out_0;
1774   unsigned simm4_in_0;
1775   simm4_in_0 = *valp & 0xf;
1776   simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
1777   *valp = simm4_out_0;
1778   return 0;
1779 }
1780
1781 static int
1782 OperandSem_opnd_sem_simm4_encode (uint32 *valp)
1783 {
1784   unsigned simm4_in_0;
1785   unsigned simm4_out_0;
1786   simm4_out_0 = *valp;
1787   simm4_in_0 = (simm4_out_0 & 0xf);
1788   *valp = simm4_in_0;
1789   return 0;
1790 }
1791
1792 static int
1793 OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
1794 {
1795   return 0;
1796 }
1797
1798 static int
1799 OperandSem_opnd_sem_AR_encode (uint32 *valp)
1800 {
1801   int error;
1802   error = (*valp >= 32);
1803   return error;
1804 }
1805
1806 static int
1807 OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1808 {
1809   return 0;
1810 }
1811
1812 static int
1813 OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
1814 {
1815   int error;
1816   error = (*valp >= 32);
1817   return error;
1818 }
1819
1820 static int
1821 OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
1822 {
1823   return 0;
1824 }
1825
1826 static int
1827 OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
1828 {
1829   int error;
1830   error = (*valp >= 32);
1831   return error;
1832 }
1833
1834 static int
1835 OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
1836 {
1837   return 0;
1838 }
1839
1840 static int
1841 OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
1842 {
1843   int error;
1844   error = (*valp >= 32);
1845   return error;
1846 }
1847
1848 static int
1849 OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
1850 {
1851   return 0;
1852 }
1853
1854 static int
1855 OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
1856 {
1857   int error;
1858   error = (*valp >= 32);
1859   return error;
1860 }
1861
1862 static int
1863 OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
1864 {
1865   return 0;
1866 }
1867
1868 static int
1869 OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
1870 {
1871   int error;
1872   error = (*valp >= 32);
1873   return error;
1874 }
1875
1876 static int
1877 OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
1878 {
1879   unsigned immrx4_out_0;
1880   unsigned immrx4_in_0;
1881   immrx4_in_0 = *valp & 0xf;
1882   immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
1883   *valp = immrx4_out_0;
1884   return 0;
1885 }
1886
1887 static int
1888 OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
1889 {
1890   unsigned immrx4_in_0;
1891   unsigned immrx4_out_0;
1892   immrx4_out_0 = *valp;
1893   immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
1894   *valp = immrx4_in_0;
1895   return 0;
1896 }
1897
1898 static int
1899 OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
1900 {
1901   unsigned lsi4x4_out_0;
1902   unsigned lsi4x4_in_0;
1903   lsi4x4_in_0 = *valp & 0xf;
1904   lsi4x4_out_0 = lsi4x4_in_0 << 2;
1905   *valp = lsi4x4_out_0;
1906   return 0;
1907 }
1908
1909 static int
1910 OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
1911 {
1912   unsigned lsi4x4_in_0;
1913   unsigned lsi4x4_out_0;
1914   lsi4x4_out_0 = *valp;
1915   lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
1916   *valp = lsi4x4_in_0;
1917   return 0;
1918 }
1919
1920 static int
1921 OperandSem_opnd_sem_simm7_decode (uint32 *valp)
1922 {
1923   unsigned simm7_out_0;
1924   unsigned simm7_in_0;
1925   simm7_in_0 = *valp & 0x7f;
1926   simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
1927   *valp = simm7_out_0;
1928   return 0;
1929 }
1930
1931 static int
1932 OperandSem_opnd_sem_simm7_encode (uint32 *valp)
1933 {
1934   unsigned simm7_in_0;
1935   unsigned simm7_out_0;
1936   simm7_out_0 = *valp;
1937   simm7_in_0 = (simm7_out_0 & 0x7f);
1938   *valp = simm7_in_0;
1939   return 0;
1940 }
1941
1942 static int
1943 OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
1944 {
1945   unsigned uimm6_out_0;
1946   unsigned uimm6_in_0;
1947   uimm6_in_0 = *valp & 0x3f;
1948   uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
1949   *valp = uimm6_out_0;
1950   return 0;
1951 }
1952
1953 static int
1954 OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
1955 {
1956   unsigned uimm6_in_0;
1957   unsigned uimm6_out_0;
1958   uimm6_out_0 = *valp;
1959   uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
1960   *valp = uimm6_in_0;
1961   return 0;
1962 }
1963
1964 static int
1965 OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
1966 {
1967   unsigned ai4const_out_0;
1968   unsigned ai4const_in_0;
1969   ai4const_in_0 = *valp & 0xf;
1970   ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
1971   *valp = ai4const_out_0;
1972   return 0;
1973 }
1974
1975 static int
1976 OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
1977 {
1978   unsigned ai4const_in_0;
1979   unsigned ai4const_out_0;
1980   ai4const_out_0 = *valp;
1981   switch (ai4const_out_0)
1982     {
1983     case 0xffffffff: ai4const_in_0 = 0; break;
1984     case 0x1: ai4const_in_0 = 0x1; break;
1985     case 0x2: ai4const_in_0 = 0x2; break;
1986     case 0x3: ai4const_in_0 = 0x3; break;
1987     case 0x4: ai4const_in_0 = 0x4; break;
1988     case 0x5: ai4const_in_0 = 0x5; break;
1989     case 0x6: ai4const_in_0 = 0x6; break;
1990     case 0x7: ai4const_in_0 = 0x7; break;
1991     case 0x8: ai4const_in_0 = 0x8; break;
1992     case 0x9: ai4const_in_0 = 0x9; break;
1993     case 0xa: ai4const_in_0 = 0xa; break;
1994     case 0xb: ai4const_in_0 = 0xb; break;
1995     case 0xc: ai4const_in_0 = 0xc; break;
1996     case 0xd: ai4const_in_0 = 0xd; break;
1997     case 0xe: ai4const_in_0 = 0xe; break;
1998     default: ai4const_in_0 = 0xf; break;
1999     }
2000   *valp = ai4const_in_0;
2001   return 0;
2002 }
2003
2004 static int
2005 OperandSem_opnd_sem_b4const_decode (uint32 *valp)
2006 {
2007   unsigned b4const_out_0;
2008   unsigned b4const_in_0;
2009   b4const_in_0 = *valp & 0xf;
2010   b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
2011   *valp = b4const_out_0;
2012   return 0;
2013 }
2014
2015 static int
2016 OperandSem_opnd_sem_b4const_encode (uint32 *valp)
2017 {
2018   unsigned b4const_in_0;
2019   unsigned b4const_out_0;
2020   b4const_out_0 = *valp;
2021   switch (b4const_out_0)
2022     {
2023     case 0xffffffff: b4const_in_0 = 0; break;
2024     case 0x1: b4const_in_0 = 0x1; break;
2025     case 0x2: b4const_in_0 = 0x2; break;
2026     case 0x3: b4const_in_0 = 0x3; break;
2027     case 0x4: b4const_in_0 = 0x4; break;
2028     case 0x5: b4const_in_0 = 0x5; break;
2029     case 0x6: b4const_in_0 = 0x6; break;
2030     case 0x7: b4const_in_0 = 0x7; break;
2031     case 0x8: b4const_in_0 = 0x8; break;
2032     case 0xa: b4const_in_0 = 0x9; break;
2033     case 0xc: b4const_in_0 = 0xa; break;
2034     case 0x10: b4const_in_0 = 0xb; break;
2035     case 0x20: b4const_in_0 = 0xc; break;
2036     case 0x40: b4const_in_0 = 0xd; break;
2037     case 0x80: b4const_in_0 = 0xe; break;
2038     default: b4const_in_0 = 0xf; break;
2039     }
2040   *valp = b4const_in_0;
2041   return 0;
2042 }
2043
2044 static int
2045 OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
2046 {
2047   unsigned b4constu_out_0;
2048   unsigned b4constu_in_0;
2049   b4constu_in_0 = *valp & 0xf;
2050   b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
2051   *valp = b4constu_out_0;
2052   return 0;
2053 }
2054
2055 static int
2056 OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
2057 {
2058   unsigned b4constu_in_0;
2059   unsigned b4constu_out_0;
2060   b4constu_out_0 = *valp;
2061   switch (b4constu_out_0)
2062     {
2063     case 0x8000: b4constu_in_0 = 0; break;
2064     case 0x10000: b4constu_in_0 = 0x1; break;
2065     case 0x2: b4constu_in_0 = 0x2; break;
2066     case 0x3: b4constu_in_0 = 0x3; break;
2067     case 0x4: b4constu_in_0 = 0x4; break;
2068     case 0x5: b4constu_in_0 = 0x5; break;
2069     case 0x6: b4constu_in_0 = 0x6; break;
2070     case 0x7: b4constu_in_0 = 0x7; break;
2071     case 0x8: b4constu_in_0 = 0x8; break;
2072     case 0xa: b4constu_in_0 = 0x9; break;
2073     case 0xc: b4constu_in_0 = 0xa; break;
2074     case 0x10: b4constu_in_0 = 0xb; break;
2075     case 0x20: b4constu_in_0 = 0xc; break;
2076     case 0x40: b4constu_in_0 = 0xd; break;
2077     case 0x80: b4constu_in_0 = 0xe; break;
2078     default: b4constu_in_0 = 0xf; break;
2079     }
2080   *valp = b4constu_in_0;
2081   return 0;
2082 }
2083
2084 static int
2085 OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
2086 {
2087   unsigned uimm8_out_0;
2088   unsigned uimm8_in_0;
2089   uimm8_in_0 = *valp & 0xff;
2090   uimm8_out_0 = uimm8_in_0;
2091   *valp = uimm8_out_0;
2092   return 0;
2093 }
2094
2095 static int
2096 OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
2097 {
2098   unsigned uimm8_in_0;
2099   unsigned uimm8_out_0;
2100   uimm8_out_0 = *valp;
2101   uimm8_in_0 = (uimm8_out_0 & 0xff);
2102   *valp = uimm8_in_0;
2103   return 0;
2104 }
2105
2106 static int
2107 OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
2108 {
2109   unsigned uimm8x2_out_0;
2110   unsigned uimm8x2_in_0;
2111   uimm8x2_in_0 = *valp & 0xff;
2112   uimm8x2_out_0 = uimm8x2_in_0 << 1;
2113   *valp = uimm8x2_out_0;
2114   return 0;
2115 }
2116
2117 static int
2118 OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
2119 {
2120   unsigned uimm8x2_in_0;
2121   unsigned uimm8x2_out_0;
2122   uimm8x2_out_0 = *valp;
2123   uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
2124   *valp = uimm8x2_in_0;
2125   return 0;
2126 }
2127
2128 static int
2129 OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
2130 {
2131   unsigned uimm8x4_out_0;
2132   unsigned uimm8x4_in_0;
2133   uimm8x4_in_0 = *valp & 0xff;
2134   uimm8x4_out_0 = uimm8x4_in_0 << 2;
2135   *valp = uimm8x4_out_0;
2136   return 0;
2137 }
2138
2139 static int
2140 OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
2141 {
2142   unsigned uimm8x4_in_0;
2143   unsigned uimm8x4_out_0;
2144   uimm8x4_out_0 = *valp;
2145   uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
2146   *valp = uimm8x4_in_0;
2147   return 0;
2148 }
2149
2150 static int
2151 OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
2152 {
2153   unsigned uimm4x16_out_0;
2154   unsigned uimm4x16_in_0;
2155   uimm4x16_in_0 = *valp & 0xf;
2156   uimm4x16_out_0 = uimm4x16_in_0 << 4;
2157   *valp = uimm4x16_out_0;
2158   return 0;
2159 }
2160
2161 static int
2162 OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
2163 {
2164   unsigned uimm4x16_in_0;
2165   unsigned uimm4x16_out_0;
2166   uimm4x16_out_0 = *valp;
2167   uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
2168   *valp = uimm4x16_in_0;
2169   return 0;
2170 }
2171
2172 static int
2173 OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
2174 {
2175   unsigned uimmrx4_out_0;
2176   unsigned uimmrx4_in_0;
2177   uimmrx4_in_0 = *valp & 0xf;
2178   uimmrx4_out_0 = uimmrx4_in_0 << 2;
2179   *valp = uimmrx4_out_0;
2180   return 0;
2181 }
2182
2183 static int
2184 OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
2185 {
2186   unsigned uimmrx4_in_0;
2187   unsigned uimmrx4_out_0;
2188   uimmrx4_out_0 = *valp;
2189   uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
2190   *valp = uimmrx4_in_0;
2191   return 0;
2192 }
2193
2194 static int
2195 OperandSem_opnd_sem_simm8_decode (uint32 *valp)
2196 {
2197   unsigned simm8_out_0;
2198   unsigned simm8_in_0;
2199   simm8_in_0 = *valp & 0xff;
2200   simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
2201   *valp = simm8_out_0;
2202   return 0;
2203 }
2204
2205 static int
2206 OperandSem_opnd_sem_simm8_encode (uint32 *valp)
2207 {
2208   unsigned simm8_in_0;
2209   unsigned simm8_out_0;
2210   simm8_out_0 = *valp;
2211   simm8_in_0 = (simm8_out_0 & 0xff);
2212   *valp = simm8_in_0;
2213   return 0;
2214 }
2215
2216 static int
2217 OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
2218 {
2219   unsigned simm8x256_out_0;
2220   unsigned simm8x256_in_0;
2221   simm8x256_in_0 = *valp & 0xff;
2222   simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
2223   *valp = simm8x256_out_0;
2224   return 0;
2225 }
2226
2227 static int
2228 OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
2229 {
2230   unsigned simm8x256_in_0;
2231   unsigned simm8x256_out_0;
2232   simm8x256_out_0 = *valp;
2233   simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
2234   *valp = simm8x256_in_0;
2235   return 0;
2236 }
2237
2238 static int
2239 OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
2240 {
2241   unsigned simm12b_out_0;
2242   unsigned simm12b_in_0;
2243   simm12b_in_0 = *valp & 0xfff;
2244   simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
2245   *valp = simm12b_out_0;
2246   return 0;
2247 }
2248
2249 static int
2250 OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
2251 {
2252   unsigned simm12b_in_0;
2253   unsigned simm12b_out_0;
2254   simm12b_out_0 = *valp;
2255   simm12b_in_0 = (simm12b_out_0 & 0xfff);
2256   *valp = simm12b_in_0;
2257   return 0;
2258 }
2259
2260 static int
2261 OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
2262 {
2263   unsigned msalp32_out_0;
2264   unsigned msalp32_in_0;
2265   msalp32_in_0 = *valp & 0x1f;
2266   msalp32_out_0 = 0x20 - msalp32_in_0;
2267   *valp = msalp32_out_0;
2268   return 0;
2269 }
2270
2271 static int
2272 OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
2273 {
2274   unsigned msalp32_in_0;
2275   unsigned msalp32_out_0;
2276   msalp32_out_0 = *valp;
2277   msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
2278   *valp = msalp32_in_0;
2279   return 0;
2280 }
2281
2282 static int
2283 OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
2284 {
2285   unsigned op2p1_out_0;
2286   unsigned op2p1_in_0;
2287   op2p1_in_0 = *valp & 0xf;
2288   op2p1_out_0 = op2p1_in_0 + 0x1;
2289   *valp = op2p1_out_0;
2290   return 0;
2291 }
2292
2293 static int
2294 OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
2295 {
2296   unsigned op2p1_in_0;
2297   unsigned op2p1_out_0;
2298   op2p1_out_0 = *valp;
2299   op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
2300   *valp = op2p1_in_0;
2301   return 0;
2302 }
2303
2304 static int
2305 OperandSem_opnd_sem_label8_decode (uint32 *valp)
2306 {
2307   unsigned label8_out_0;
2308   unsigned label8_in_0;
2309   label8_in_0 = *valp & 0xff;
2310   label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
2311   *valp = label8_out_0;
2312   return 0;
2313 }
2314
2315 static int
2316 OperandSem_opnd_sem_label8_encode (uint32 *valp)
2317 {
2318   unsigned label8_in_0;
2319   unsigned label8_out_0;
2320   label8_out_0 = *valp;
2321   label8_in_0 = (label8_out_0 - 0x4) & 0xff;
2322   *valp = label8_in_0;
2323   return 0;
2324 }
2325
2326 static int
2327 OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
2328 {
2329   unsigned ulabel8_out_0;
2330   unsigned ulabel8_in_0;
2331   ulabel8_in_0 = *valp & 0xff;
2332   ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
2333   *valp = ulabel8_out_0;
2334   return 0;
2335 }
2336
2337 static int
2338 OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
2339 {
2340   unsigned ulabel8_in_0;
2341   unsigned ulabel8_out_0;
2342   ulabel8_out_0 = *valp;
2343   ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
2344   *valp = ulabel8_in_0;
2345   return 0;
2346 }
2347
2348 static int
2349 OperandSem_opnd_sem_label12_decode (uint32 *valp)
2350 {
2351   unsigned label12_out_0;
2352   unsigned label12_in_0;
2353   label12_in_0 = *valp & 0xfff;
2354   label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
2355   *valp = label12_out_0;
2356   return 0;
2357 }
2358
2359 static int
2360 OperandSem_opnd_sem_label12_encode (uint32 *valp)
2361 {
2362   unsigned label12_in_0;
2363   unsigned label12_out_0;
2364   label12_out_0 = *valp;
2365   label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
2366   *valp = label12_in_0;
2367   return 0;
2368 }
2369
2370 static int
2371 OperandSem_opnd_sem_soffset_decode (uint32 *valp)
2372 {
2373   unsigned soffset_out_0;
2374   unsigned soffset_in_0;
2375   soffset_in_0 = *valp & 0x3ffff;
2376   soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
2377   *valp = soffset_out_0;
2378   return 0;
2379 }
2380
2381 static int
2382 OperandSem_opnd_sem_soffset_encode (uint32 *valp)
2383 {
2384   unsigned soffset_in_0;
2385   unsigned soffset_out_0;
2386   soffset_out_0 = *valp;
2387   soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
2388   *valp = soffset_in_0;
2389   return 0;
2390 }
2391
2392 static int
2393 OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
2394 {
2395   unsigned uimm16x4_out_0;
2396   unsigned uimm16x4_in_0;
2397   uimm16x4_in_0 = *valp & 0xffff;
2398   uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
2399   *valp = uimm16x4_out_0;
2400   return 0;
2401 }
2402
2403 static int
2404 OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
2405 {
2406   unsigned uimm16x4_in_0;
2407   unsigned uimm16x4_out_0;
2408   uimm16x4_out_0 = *valp;
2409   uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
2410   *valp = uimm16x4_in_0;
2411   return 0;
2412 }
2413
2414 static int
2415 OperandSem_opnd_sem_bbi_decode (uint32 *valp)
2416 {
2417   unsigned bbi_out_0;
2418   unsigned bbi_in_0;
2419   bbi_in_0 = *valp & 0x1f;
2420   bbi_out_0 = (0 << 5) | bbi_in_0;
2421   *valp = bbi_out_0;
2422   return 0;
2423 }
2424
2425 static int
2426 OperandSem_opnd_sem_bbi_encode (uint32 *valp)
2427 {
2428   unsigned bbi_in_0;
2429   unsigned bbi_out_0;
2430   bbi_out_0 = *valp;
2431   bbi_in_0 = (bbi_out_0 & 0x1f);
2432   *valp = bbi_in_0;
2433   return 0;
2434 }
2435
2436 static int
2437 OperandSem_opnd_sem_s_decode (uint32 *valp)
2438 {
2439   unsigned s_out_0;
2440   unsigned s_in_0;
2441   s_in_0 = *valp & 0xf;
2442   s_out_0 = (0 << 4) | s_in_0;
2443   *valp = s_out_0;
2444   return 0;
2445 }
2446
2447 static int
2448 OperandSem_opnd_sem_s_encode (uint32 *valp)
2449 {
2450   unsigned s_in_0;
2451   unsigned s_out_0;
2452   s_out_0 = *valp;
2453   s_in_0 = (s_out_0 & 0xf);
2454   *valp = s_in_0;
2455   return 0;
2456 }
2457
2458 static int
2459 OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
2460 {
2461   return 0;
2462 }
2463
2464 static int
2465 OperandSem_opnd_sem_MR_encode (uint32 *valp)
2466 {
2467   int error;
2468   error = (*valp >= 4);
2469   return error;
2470 }
2471
2472 static int
2473 OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
2474 {
2475   return 0;
2476 }
2477
2478 static int
2479 OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
2480 {
2481   int error;
2482   error = (*valp >= 4);
2483   return error;
2484 }
2485
2486 static int
2487 OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
2488 {
2489   return 0;
2490 }
2491
2492 static int
2493 OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
2494 {
2495   int error;
2496   error = (*valp >= 4);
2497   return error;
2498 }
2499
2500 static int
2501 OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
2502 {
2503   return 0;
2504 }
2505
2506 static int
2507 OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
2508 {
2509   int error;
2510   error = (*valp >= 4);
2511   return error;
2512 }
2513
2514 static int
2515 OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
2516 {
2517   return 0;
2518 }
2519
2520 static int
2521 OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
2522 {
2523   int error;
2524   error = (*valp >= 4);
2525   return error;
2526 }
2527
2528 static int
2529 OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
2530 {
2531   return 0;
2532 }
2533
2534 static int
2535 OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
2536 {
2537   int error;
2538   error = (*valp >= 4);
2539   return error;
2540 }
2541
2542 static int
2543 OperandSem_opnd_sem_immt_decode (uint32 *valp)
2544 {
2545   unsigned immt_out_0;
2546   unsigned immt_in_0;
2547   immt_in_0 = *valp & 0xf;
2548   immt_out_0 = immt_in_0;
2549   *valp = immt_out_0;
2550   return 0;
2551 }
2552
2553 static int
2554 OperandSem_opnd_sem_immt_encode (uint32 *valp)
2555 {
2556   unsigned immt_in_0;
2557   unsigned immt_out_0;
2558   immt_out_0 = *valp;
2559   immt_in_0 = immt_out_0 & 0xf;
2560   *valp = immt_in_0;
2561   return 0;
2562 }
2563
2564 static int
2565 OperandSem_opnd_sem_tp7_decode (uint32 *valp)
2566 {
2567   unsigned tp7_out_0;
2568   unsigned tp7_in_0;
2569   tp7_in_0 = *valp & 0xf;
2570   tp7_out_0 = tp7_in_0 + 0x7;
2571   *valp = tp7_out_0;
2572   return 0;
2573 }
2574
2575 static int
2576 OperandSem_opnd_sem_tp7_encode (uint32 *valp)
2577 {
2578   unsigned tp7_in_0;
2579   unsigned tp7_out_0;
2580   tp7_out_0 = *valp;
2581   tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
2582   *valp = tp7_in_0;
2583   return 0;
2584 }
2585
2586 static int
2587 OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
2588 {
2589   unsigned xt_wbr15_label_out_0;
2590   unsigned xt_wbr15_label_in_0;
2591   xt_wbr15_label_in_0 = *valp & 0x7fff;
2592   xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
2593   *valp = xt_wbr15_label_out_0;
2594   return 0;
2595 }
2596
2597 static int
2598 OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
2599 {
2600   unsigned xt_wbr15_label_in_0;
2601   unsigned xt_wbr15_label_out_0;
2602   xt_wbr15_label_out_0 = *valp;
2603   xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
2604   *valp = xt_wbr15_label_in_0;
2605   return 0;
2606 }
2607
2608 static int
2609 OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
2610 {
2611   unsigned xt_wbr18_label_out_0;
2612   unsigned xt_wbr18_label_in_0;
2613   xt_wbr18_label_in_0 = *valp & 0x3ffff;
2614   xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
2615   *valp = xt_wbr18_label_out_0;
2616   return 0;
2617 }
2618
2619 static int
2620 OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
2621 {
2622   unsigned xt_wbr18_label_in_0;
2623   unsigned xt_wbr18_label_out_0;
2624   xt_wbr18_label_out_0 = *valp;
2625   xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
2626   *valp = xt_wbr18_label_in_0;
2627   return 0;
2628 }
2629
2630 static int
2631 OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
2632 {
2633   unsigned bitindex_out_0;
2634   unsigned bitindex_in_0;
2635   bitindex_in_0 = *valp & 0x1f;
2636   bitindex_out_0 = (0 << 5) | bitindex_in_0;
2637   *valp = bitindex_out_0;
2638   return 0;
2639 }
2640
2641 static int
2642 OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
2643 {
2644   unsigned bitindex_in_0;
2645   unsigned bitindex_out_0;
2646   bitindex_out_0 = *valp;
2647   bitindex_in_0 = (bitindex_out_0 & 0x1f);
2648   *valp = bitindex_in_0;
2649   return 0;
2650 }
2651
2652 static int
2653 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
2654 {
2655   *valp -= (pc & ~0x3);
2656   return 0;
2657 }
2658
2659 static int
2660 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
2661 {
2662   *valp += (pc & ~0x3);
2663   return 0;
2664 }
2665
2666 static int
2667 Operand_uimm6_ator (uint32 *valp, uint32 pc)
2668 {
2669   *valp -= pc;
2670   return 0;
2671 }
2672
2673 static int
2674 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
2675 {
2676   *valp += pc;
2677   return 0;
2678 }
2679
2680 static int
2681 Operand_label8_ator (uint32 *valp, uint32 pc)
2682 {
2683   *valp -= pc;
2684   return 0;
2685 }
2686
2687 static int
2688 Operand_label8_rtoa (uint32 *valp, uint32 pc)
2689 {
2690   *valp += pc;
2691   return 0;
2692 }
2693
2694 static int
2695 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2696 {
2697   *valp -= pc;
2698   return 0;
2699 }
2700
2701 static int
2702 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2703 {
2704   *valp += pc;
2705   return 0;
2706 }
2707
2708 static int
2709 Operand_label12_ator (uint32 *valp, uint32 pc)
2710 {
2711   *valp -= pc;
2712   return 0;
2713 }
2714
2715 static int
2716 Operand_label12_rtoa (uint32 *valp, uint32 pc)
2717 {
2718   *valp += pc;
2719   return 0;
2720 }
2721
2722 static int
2723 Operand_soffset_ator (uint32 *valp, uint32 pc)
2724 {
2725   *valp -= pc;
2726   return 0;
2727 }
2728
2729 static int
2730 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2731 {
2732   *valp += pc;
2733   return 0;
2734 }
2735
2736 static int
2737 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2738 {
2739   *valp -= ((pc + 3) & ~0x3);
2740   return 0;
2741 }
2742
2743 static int
2744 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2745 {
2746   *valp += ((pc + 3) & ~0x3);
2747   return 0;
2748 }
2749
2750 static int
2751 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
2752 {
2753   *valp -= pc;
2754   return 0;
2755 }
2756
2757 static int
2758 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
2759 {
2760   *valp += pc;
2761   return 0;
2762 }
2763
2764 static int
2765 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
2766 {
2767   *valp -= pc;
2768   return 0;
2769 }
2770
2771 static int
2772 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
2773 {
2774   *valp += pc;
2775   return 0;
2776 }
2777
2778 static xtensa_operand_internal operands[] = {
2779   { "soffsetx4", FIELD_offset, -1, 0,
2780     XTENSA_OPERAND_IS_PCRELATIVE,
2781     OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
2782     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
2783   { "uimm12x8", FIELD_imm12, -1, 0,
2784     0,
2785     OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
2786     0, 0 },
2787   { "simm4", FIELD_mn, -1, 0,
2788     0,
2789     OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
2790     0, 0 },
2791   { "arr", FIELD_r, REGFILE_AR, 1,
2792     XTENSA_OPERAND_IS_REGISTER,
2793     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2794     0, 0 },
2795   { "ars", FIELD_s, REGFILE_AR, 1,
2796     XTENSA_OPERAND_IS_REGISTER,
2797     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2798     0, 0 },
2799   { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
2800     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2801     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2802     0, 0 },
2803   { "art", FIELD_t, REGFILE_AR, 1,
2804     XTENSA_OPERAND_IS_REGISTER,
2805     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
2806     0, 0 },
2807   { "ar0", FIELD__ar0, REGFILE_AR, 1,
2808     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2809     OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
2810     0, 0 },
2811   { "ar4", FIELD__ar4, REGFILE_AR, 1,
2812     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2813     OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
2814     0, 0 },
2815   { "ar8", FIELD__ar8, REGFILE_AR, 1,
2816     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2817     OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
2818     0, 0 },
2819   { "ar12", FIELD__ar12, REGFILE_AR, 1,
2820     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2821     OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
2822     0, 0 },
2823   { "ars_entry", FIELD_s, REGFILE_AR, 1,
2824     XTENSA_OPERAND_IS_REGISTER,
2825     OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
2826     0, 0 },
2827   { "immrx4", FIELD_r, -1, 0,
2828     0,
2829     OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
2830     0, 0 },
2831   { "lsi4x4", FIELD_r, -1, 0,
2832     0,
2833     OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
2834     0, 0 },
2835   { "simm7", FIELD_imm7, -1, 0,
2836     0,
2837     OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
2838     0, 0 },
2839   { "uimm6", FIELD_imm6, -1, 0,
2840     XTENSA_OPERAND_IS_PCRELATIVE,
2841     OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
2842     Operand_uimm6_ator, Operand_uimm6_rtoa },
2843   { "ai4const", FIELD_t, -1, 0,
2844     0,
2845     OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
2846     0, 0 },
2847   { "b4const", FIELD_r, -1, 0,
2848     0,
2849     OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
2850     0, 0 },
2851   { "b4constu", FIELD_r, -1, 0,
2852     0,
2853     OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
2854     0, 0 },
2855   { "uimm8", FIELD_imm8, -1, 0,
2856     0,
2857     OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
2858     0, 0 },
2859   { "uimm8x2", FIELD_imm8, -1, 0,
2860     0,
2861     OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
2862     0, 0 },
2863   { "uimm8x4", FIELD_imm8, -1, 0,
2864     0,
2865     OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
2866     0, 0 },
2867   { "uimm4x16", FIELD_op2, -1, 0,
2868     0,
2869     OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
2870     0, 0 },
2871   { "uimmrx4", FIELD_r, -1, 0,
2872     0,
2873     OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
2874     0, 0 },
2875   { "simm8", FIELD_imm8, -1, 0,
2876     0,
2877     OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
2878     0, 0 },
2879   { "simm8x256", FIELD_imm8, -1, 0,
2880     0,
2881     OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
2882     0, 0 },
2883   { "simm12b", FIELD_imm12b, -1, 0,
2884     0,
2885     OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
2886     0, 0 },
2887   { "msalp32", FIELD_sal, -1, 0,
2888     0,
2889     OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
2890     0, 0 },
2891   { "op2p1", FIELD_op2, -1, 0,
2892     0,
2893     OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
2894     0, 0 },
2895   { "label8", FIELD_imm8, -1, 0,
2896     XTENSA_OPERAND_IS_PCRELATIVE,
2897     OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
2898     Operand_label8_ator, Operand_label8_rtoa },
2899   { "ulabel8", FIELD_imm8, -1, 0,
2900     XTENSA_OPERAND_IS_PCRELATIVE,
2901     OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
2902     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
2903   { "label12", FIELD_imm12, -1, 0,
2904     XTENSA_OPERAND_IS_PCRELATIVE,
2905     OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
2906     Operand_label12_ator, Operand_label12_rtoa },
2907   { "soffset", FIELD_offset, -1, 0,
2908     XTENSA_OPERAND_IS_PCRELATIVE,
2909     OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
2910     Operand_soffset_ator, Operand_soffset_rtoa },
2911   { "uimm16x4", FIELD_imm16, -1, 0,
2912     XTENSA_OPERAND_IS_PCRELATIVE,
2913     OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
2914     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
2915   { "bbi", FIELD_bbi, -1, 0,
2916     0,
2917     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2918     0, 0 },
2919   { "sae", FIELD_sae, -1, 0,
2920     0,
2921     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2922     0, 0 },
2923   { "sas", FIELD_sas, -1, 0,
2924     0,
2925     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2926     0, 0 },
2927   { "sargt", FIELD_sargt, -1, 0,
2928     0,
2929     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
2930     0, 0 },
2931   { "s", FIELD_s, -1, 0,
2932     0,
2933     OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
2934     0, 0 },
2935   { "mx", FIELD_x, REGFILE_MR, 1,
2936     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2937     OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
2938     0, 0 },
2939   { "my", FIELD_y, REGFILE_MR, 1,
2940     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
2941     OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
2942     0, 0 },
2943   { "mw", FIELD_w, REGFILE_MR, 1,
2944     XTENSA_OPERAND_IS_REGISTER,
2945     OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
2946     0, 0 },
2947   { "mr0", FIELD__mr0, REGFILE_MR, 1,
2948     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2949     OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
2950     0, 0 },
2951   { "mr1", FIELD__mr1, REGFILE_MR, 1,
2952     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2953     OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
2954     0, 0 },
2955   { "mr2", FIELD__mr2, REGFILE_MR, 1,
2956     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2957     OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
2958     0, 0 },
2959   { "mr3", FIELD__mr3, REGFILE_MR, 1,
2960     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
2961     OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
2962     0, 0 },
2963   { "immt", FIELD_t, -1, 0,
2964     0,
2965     OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
2966     0, 0 },
2967   { "imms", FIELD_s, -1, 0,
2968     0,
2969     OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
2970     0, 0 },
2971   { "tp7", FIELD_t, -1, 0,
2972     0,
2973     OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
2974     0, 0 },
2975   { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
2976     XTENSA_OPERAND_IS_PCRELATIVE,
2977     OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
2978     Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
2979   { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
2980     XTENSA_OPERAND_IS_PCRELATIVE,
2981     OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
2982     Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
2983   { "bitindex", FIELD_bitindex, -1, 0,
2984     0,
2985     OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
2986     0, 0 },
2987   { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
2988   { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
2989   { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
2990   { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
2991   { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
2992   { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
2993   { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
2994   { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
2995   { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
2996   { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
2997   { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
2998   { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
2999   { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
3000   { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
3001   { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
3002   { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
3003   { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
3004   { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
3005   { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
3006   { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
3007   { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
3008   { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
3009   { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
3010   { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
3011   { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
3012   { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
3013   { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
3014   { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
3015   { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
3016   { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
3017   { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
3018   { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
3019   { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
3020   { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
3021   { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
3022   { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
3023   { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
3024   { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
3025   { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
3026   { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
3027   { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
3028   { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
3029 };
3030
3031 enum xtensa_operand_id {
3032   OPERAND_soffsetx4,
3033   OPERAND_uimm12x8,
3034   OPERAND_simm4,
3035   OPERAND_arr,
3036   OPERAND_ars,
3037   OPERAND__ars_invisible,
3038   OPERAND_art,
3039   OPERAND_ar0,
3040   OPERAND_ar4,
3041   OPERAND_ar8,
3042   OPERAND_ar12,
3043   OPERAND_ars_entry,
3044   OPERAND_immrx4,
3045   OPERAND_lsi4x4,
3046   OPERAND_simm7,
3047   OPERAND_uimm6,
3048   OPERAND_ai4const,
3049   OPERAND_b4const,
3050   OPERAND_b4constu,
3051   OPERAND_uimm8,
3052   OPERAND_uimm8x2,
3053   OPERAND_uimm8x4,
3054   OPERAND_uimm4x16,
3055   OPERAND_uimmrx4,
3056   OPERAND_simm8,
3057   OPERAND_simm8x256,
3058   OPERAND_simm12b,
3059   OPERAND_msalp32,
3060   OPERAND_op2p1,
3061   OPERAND_label8,
3062   OPERAND_ulabel8,
3063   OPERAND_label12,
3064   OPERAND_soffset,
3065   OPERAND_uimm16x4,
3066   OPERAND_bbi,
3067   OPERAND_sae,
3068   OPERAND_sas,
3069   OPERAND_sargt,
3070   OPERAND_s,
3071   OPERAND_mx,
3072   OPERAND_my,
3073   OPERAND_mw,
3074   OPERAND_mr0,
3075   OPERAND_mr1,
3076   OPERAND_mr2,
3077   OPERAND_mr3,
3078   OPERAND_immt,
3079   OPERAND_imms,
3080   OPERAND_tp7,
3081   OPERAND_xt_wbr15_label,
3082   OPERAND_xt_wbr18_label,
3083   OPERAND_bitindex,
3084   OPERAND_t,
3085   OPERAND_bbi4,
3086   OPERAND_imm12,
3087   OPERAND_imm8,
3088   OPERAND_imm12b,
3089   OPERAND_imm16,
3090   OPERAND_m,
3091   OPERAND_n,
3092   OPERAND_offset,
3093   OPERAND_op0,
3094   OPERAND_op1,
3095   OPERAND_op2,
3096   OPERAND_r,
3097   OPERAND_sa4,
3098   OPERAND_sae4,
3099   OPERAND_sal,
3100   OPERAND_sas4,
3101   OPERAND_sr,
3102   OPERAND_st,
3103   OPERAND_thi3,
3104   OPERAND_imm4,
3105   OPERAND_mn,
3106   OPERAND_i,
3107   OPERAND_imm6lo,
3108   OPERAND_imm6hi,
3109   OPERAND_imm7lo,
3110   OPERAND_imm7hi,
3111   OPERAND_z,
3112   OPERAND_imm6,
3113   OPERAND_imm7,
3114   OPERAND_r3,
3115   OPERAND_rbit2,
3116   OPERAND_rhi,
3117   OPERAND_t3,
3118   OPERAND_tbit2,
3119   OPERAND_tlo,
3120   OPERAND_w,
3121   OPERAND_y,
3122   OPERAND_x,
3123   OPERAND_xt_wbr15_imm,
3124   OPERAND_xt_wbr18_imm,
3125   OPERAND_s3to1
3126 };
3127
3128 \f
3129 /* Iclass table.  */
3130
3131 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
3132   { { STATE_PSEXCM }, 'o' },
3133   { { STATE_EPC1 }, 'i' }
3134 };
3135
3136 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
3137   { { STATE_DEPC }, 'i' }
3138 };
3139
3140 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
3141   { { OPERAND_soffsetx4 }, 'i' },
3142   { { OPERAND_ar12 }, 'o' }
3143 };
3144
3145 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
3146   { { STATE_PSCALLINC }, 'o' }
3147 };
3148
3149 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
3150   { { OPERAND_soffsetx4 }, 'i' },
3151   { { OPERAND_ar8 }, 'o' }
3152 };
3153
3154 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
3155   { { STATE_PSCALLINC }, 'o' }
3156 };
3157
3158 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
3159   { { OPERAND_soffsetx4 }, 'i' },
3160   { { OPERAND_ar4 }, 'o' }
3161 };
3162
3163 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
3164   { { STATE_PSCALLINC }, 'o' }
3165 };
3166
3167 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
3168   { { OPERAND_ars }, 'i' },
3169   { { OPERAND_ar12 }, 'o' }
3170 };
3171
3172 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
3173   { { STATE_PSCALLINC }, 'o' }
3174 };
3175
3176 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
3177   { { OPERAND_ars }, 'i' },
3178   { { OPERAND_ar8 }, 'o' }
3179 };
3180
3181 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
3182   { { STATE_PSCALLINC }, 'o' }
3183 };
3184
3185 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
3186   { { OPERAND_ars }, 'i' },
3187   { { OPERAND_ar4 }, 'o' }
3188 };
3189
3190 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
3191   { { STATE_PSCALLINC }, 'o' }
3192 };
3193
3194 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
3195   { { OPERAND_ars_entry }, 's' },
3196   { { OPERAND_ars }, 'i' },
3197   { { OPERAND_uimm12x8 }, 'i' }
3198 };
3199
3200 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
3201   { { STATE_PSCALLINC }, 'i' },
3202   { { STATE_PSEXCM }, 'i' },
3203   { { STATE_PSWOE }, 'i' },
3204   { { STATE_WindowBase }, 'm' },
3205   { { STATE_WindowStart }, 'm' }
3206 };
3207
3208 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
3209   { { OPERAND_art }, 'o' },
3210   { { OPERAND_ars }, 'i' }
3211 };
3212
3213 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
3214   { { STATE_WindowBase }, 'i' },
3215   { { STATE_WindowStart }, 'i' }
3216 };
3217
3218 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
3219   { { OPERAND_simm4 }, 'i' }
3220 };
3221
3222 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
3223   { { STATE_WindowBase }, 'm' }
3224 };
3225
3226 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
3227   { { OPERAND__ars_invisible }, 'i' }
3228 };
3229
3230 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
3231   { { STATE_WindowBase }, 'm' },
3232   { { STATE_WindowStart }, 'm' },
3233   { { STATE_PSCALLINC }, 'o' },
3234   { { STATE_PSEXCM }, 'i' },
3235   { { STATE_PSWOE }, 'i' }
3236 };
3237
3238 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
3239   { { STATE_EPC1 }, 'i' },
3240   { { STATE_PSEXCM }, 'o' },
3241   { { STATE_WindowBase }, 'm' },
3242   { { STATE_WindowStart }, 'm' },
3243   { { STATE_PSOWB }, 'i' }
3244 };
3245
3246 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
3247   { { OPERAND_art }, 'o' },
3248   { { OPERAND_ars }, 'i' },
3249   { { OPERAND_immrx4 }, 'i' }
3250 };
3251
3252 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
3253   { { OPERAND_art }, 'i' },
3254   { { OPERAND_ars }, 'i' },
3255   { { OPERAND_immrx4 }, 'i' }
3256 };
3257
3258 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
3259   { { OPERAND_art }, 'o' }
3260 };
3261
3262 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
3263   { { STATE_WindowBase }, 'i' }
3264 };
3265
3266 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
3267   { { OPERAND_art }, 'i' }
3268 };
3269
3270 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
3271   { { STATE_WindowBase }, 'o' }
3272 };
3273
3274 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
3275   { { OPERAND_art }, 'm' }
3276 };
3277
3278 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3279   { { STATE_WindowBase }, 'm' }
3280 };
3281
3282 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3283   { { OPERAND_art }, 'o' }
3284 };
3285
3286 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3287   { { STATE_WindowStart }, 'i' }
3288 };
3289
3290 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3291   { { OPERAND_art }, 'i' }
3292 };
3293
3294 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3295   { { STATE_WindowStart }, 'o' }
3296 };
3297
3298 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3299   { { OPERAND_art }, 'm' }
3300 };
3301
3302 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3303   { { STATE_WindowStart }, 'm' }
3304 };
3305
3306 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3307   { { OPERAND_arr }, 'o' },
3308   { { OPERAND_ars }, 'i' },
3309   { { OPERAND_art }, 'i' }
3310 };
3311
3312 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3313   { { OPERAND_arr }, 'o' },
3314   { { OPERAND_ars }, 'i' },
3315   { { OPERAND_ai4const }, 'i' }
3316 };
3317
3318 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3319   { { OPERAND_ars }, 'i' },
3320   { { OPERAND_uimm6 }, 'i' }
3321 };
3322
3323 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3324   { { OPERAND_art }, 'o' },
3325   { { OPERAND_ars }, 'i' },
3326   { { OPERAND_lsi4x4 }, 'i' }
3327 };
3328
3329 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3330   { { OPERAND_art }, 'o' },
3331   { { OPERAND_ars }, 'i' }
3332 };
3333
3334 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3335   { { OPERAND_ars }, 'o' },
3336   { { OPERAND_simm7 }, 'i' }
3337 };
3338
3339 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3340   { { OPERAND__ars_invisible }, 'i' }
3341 };
3342
3343 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3344   { { OPERAND_art }, 'i' },
3345   { { OPERAND_ars }, 'i' },
3346   { { OPERAND_lsi4x4 }, 'i' }
3347 };
3348
3349 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3350   { { OPERAND_art }, 'o' },
3351   { { OPERAND_ars }, 'i' },
3352   { { OPERAND_simm8 }, 'i' }
3353 };
3354
3355 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3356   { { OPERAND_art }, 'o' },
3357   { { OPERAND_ars }, 'i' },
3358   { { OPERAND_simm8x256 }, 'i' }
3359 };
3360
3361 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3362   { { OPERAND_arr }, 'o' },
3363   { { OPERAND_ars }, 'i' },
3364   { { OPERAND_art }, 'i' }
3365 };
3366
3367 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3368   { { OPERAND_arr }, 'o' },
3369   { { OPERAND_ars }, 'i' },
3370   { { OPERAND_art }, 'i' }
3371 };
3372
3373 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3374   { { OPERAND_ars }, 'i' },
3375   { { OPERAND_b4const }, 'i' },
3376   { { OPERAND_label8 }, 'i' }
3377 };
3378
3379 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
3380   { { OPERAND_ars }, 'i' },
3381   { { OPERAND_bbi }, 'i' },
3382   { { OPERAND_label8 }, 'i' }
3383 };
3384
3385 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
3386   { { OPERAND_ars }, 'i' },
3387   { { OPERAND_b4constu }, 'i' },
3388   { { OPERAND_label8 }, 'i' }
3389 };
3390
3391 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
3392   { { OPERAND_ars }, 'i' },
3393   { { OPERAND_art }, 'i' },
3394   { { OPERAND_label8 }, 'i' }
3395 };
3396
3397 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
3398   { { OPERAND_ars }, 'i' },
3399   { { OPERAND_label12 }, 'i' }
3400 };
3401
3402 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
3403   { { OPERAND_soffsetx4 }, 'i' },
3404   { { OPERAND_ar0 }, 'o' }
3405 };
3406
3407 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
3408   { { OPERAND_ars }, 'i' },
3409   { { OPERAND_ar0 }, 'o' }
3410 };
3411
3412 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
3413   { { OPERAND_arr }, 'o' },
3414   { { OPERAND_art }, 'i' },
3415   { { OPERAND_sae }, 'i' },
3416   { { OPERAND_op2p1 }, 'i' }
3417 };
3418
3419 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
3420   { { OPERAND_soffset }, 'i' }
3421 };
3422
3423 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
3424   { { OPERAND_ars }, 'i' }
3425 };
3426
3427 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
3428   { { OPERAND_art }, 'o' },
3429   { { OPERAND_ars }, 'i' },
3430   { { OPERAND_uimm8x2 }, 'i' }
3431 };
3432
3433 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
3434   { { OPERAND_art }, 'o' },
3435   { { OPERAND_ars }, 'i' },
3436   { { OPERAND_uimm8x2 }, 'i' }
3437 };
3438
3439 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
3440   { { OPERAND_art }, 'o' },
3441   { { OPERAND_ars }, 'i' },
3442   { { OPERAND_uimm8x4 }, 'i' }
3443 };
3444
3445 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
3446   { { OPERAND_art }, 'o' },
3447   { { OPERAND_uimm16x4 }, 'i' }
3448 };
3449
3450 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
3451   { { OPERAND_art }, 'o' },
3452   { { OPERAND_ars }, 'i' },
3453   { { OPERAND_uimm8 }, 'i' }
3454 };
3455
3456 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
3457   { { OPERAND_ars }, 'i' },
3458   { { OPERAND_ulabel8 }, 'i' }
3459 };
3460
3461 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
3462   { { STATE_LBEG }, 'o' },
3463   { { STATE_LEND }, 'o' },
3464   { { STATE_LCOUNT }, 'o' }
3465 };
3466
3467 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
3468   { { OPERAND_ars }, 'i' },
3469   { { OPERAND_ulabel8 }, 'i' }
3470 };
3471
3472 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
3473   { { STATE_LBEG }, 'o' },
3474   { { STATE_LEND }, 'o' },
3475   { { STATE_LCOUNT }, 'o' }
3476 };
3477
3478 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
3479   { { OPERAND_art }, 'o' },
3480   { { OPERAND_simm12b }, 'i' }
3481 };
3482
3483 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
3484   { { OPERAND_arr }, 'm' },
3485   { { OPERAND_ars }, 'i' },
3486   { { OPERAND_art }, 'i' }
3487 };
3488
3489 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
3490   { { OPERAND_arr }, 'o' },
3491   { { OPERAND_art }, 'i' }
3492 };
3493
3494 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
3495   { { OPERAND__ars_invisible }, 'i' }
3496 };
3497
3498 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
3499   { { OPERAND_art }, 'i' },
3500   { { OPERAND_ars }, 'i' },
3501   { { OPERAND_uimm8x2 }, 'i' }
3502 };
3503
3504 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
3505   { { OPERAND_art }, 'i' },
3506   { { OPERAND_ars }, 'i' },
3507   { { OPERAND_uimm8x4 }, 'i' }
3508 };
3509
3510 static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
3511   { { OPERAND_art }, 'i' },
3512   { { OPERAND_ars }, 'i' },
3513   { { OPERAND_uimmrx4 }, 'i' }
3514 };
3515
3516 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
3517   { { OPERAND_art }, 'i' },
3518   { { OPERAND_ars }, 'i' },
3519   { { OPERAND_uimm8 }, 'i' }
3520 };
3521
3522 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
3523   { { OPERAND_ars }, 'i' }
3524 };
3525
3526 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
3527   { { STATE_SAR }, 'o' }
3528 };
3529
3530 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
3531   { { OPERAND_sas }, 'i' }
3532 };
3533
3534 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
3535   { { STATE_SAR }, 'o' }
3536 };
3537
3538 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
3539   { { OPERAND_arr }, 'o' },
3540   { { OPERAND_ars }, 'i' }
3541 };
3542
3543 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
3544   { { STATE_SAR }, 'i' }
3545 };
3546
3547 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
3548   { { OPERAND_arr }, 'o' },
3549   { { OPERAND_ars }, 'i' },
3550   { { OPERAND_art }, 'i' }
3551 };
3552
3553 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
3554   { { STATE_SAR }, 'i' }
3555 };
3556
3557 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
3558   { { OPERAND_arr }, 'o' },
3559   { { OPERAND_art }, 'i' }
3560 };
3561
3562 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
3563   { { STATE_SAR }, 'i' }
3564 };
3565
3566 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
3567   { { OPERAND_arr }, 'o' },
3568   { { OPERAND_ars }, 'i' },
3569   { { OPERAND_msalp32 }, 'i' }
3570 };
3571
3572 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
3573   { { OPERAND_arr }, 'o' },
3574   { { OPERAND_art }, 'i' },
3575   { { OPERAND_sargt }, 'i' }
3576 };
3577
3578 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
3579   { { OPERAND_arr }, 'o' },
3580   { { OPERAND_art }, 'i' },
3581   { { OPERAND_s }, 'i' }
3582 };
3583
3584 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
3585   { { STATE_XTSYNC }, 'i' }
3586 };
3587
3588 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
3589   { { OPERAND_art }, 'o' },
3590   { { OPERAND_s }, 'i' }
3591 };
3592
3593 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
3594   { { STATE_PSWOE }, 'i' },
3595   { { STATE_PSCALLINC }, 'i' },
3596   { { STATE_PSOWB }, 'i' },
3597   { { STATE_PSUM }, 'i' },
3598   { { STATE_PSEXCM }, 'i' },
3599   { { STATE_PSINTLEVEL }, 'm' }
3600 };
3601
3602 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
3603   { { OPERAND_art }, 'o' }
3604 };
3605
3606 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
3607   { { STATE_LEND }, 'i' }
3608 };
3609
3610 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
3611   { { OPERAND_art }, 'i' }
3612 };
3613
3614 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
3615   { { STATE_LEND }, 'o' }
3616 };
3617
3618 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
3619   { { OPERAND_art }, 'm' }
3620 };
3621
3622 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
3623   { { STATE_LEND }, 'm' }
3624 };
3625
3626 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
3627   { { OPERAND_art }, 'o' }
3628 };
3629
3630 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
3631   { { STATE_LCOUNT }, 'i' }
3632 };
3633
3634 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
3635   { { OPERAND_art }, 'i' }
3636 };
3637
3638 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
3639   { { STATE_XTSYNC }, 'o' },
3640   { { STATE_LCOUNT }, 'o' }
3641 };
3642
3643 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
3644   { { OPERAND_art }, 'm' }
3645 };
3646
3647 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
3648   { { STATE_XTSYNC }, 'o' },
3649   { { STATE_LCOUNT }, 'm' }
3650 };
3651
3652 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
3653   { { OPERAND_art }, 'o' }
3654 };
3655
3656 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
3657   { { STATE_LBEG }, 'i' }
3658 };
3659
3660 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
3661   { { OPERAND_art }, 'i' }
3662 };
3663
3664 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
3665   { { STATE_LBEG }, 'o' }
3666 };
3667
3668 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
3669   { { OPERAND_art }, 'm' }
3670 };
3671
3672 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
3673   { { STATE_LBEG }, 'm' }
3674 };
3675
3676 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
3677   { { OPERAND_art }, 'o' }
3678 };
3679
3680 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
3681   { { STATE_SAR }, 'i' }
3682 };
3683
3684 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
3685   { { OPERAND_art }, 'i' }
3686 };
3687
3688 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
3689   { { STATE_SAR }, 'o' },
3690   { { STATE_XTSYNC }, 'o' }
3691 };
3692
3693 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
3694   { { OPERAND_art }, 'm' }
3695 };
3696
3697 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
3698   { { STATE_SAR }, 'm' }
3699 };
3700
3701 static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
3702   { { OPERAND_art }, 'o' }
3703 };
3704
3705 static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
3706   { { OPERAND_art }, 'i' }
3707 };
3708
3709 static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
3710   { { OPERAND_art }, 'm' }
3711 };
3712
3713 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
3714   { { OPERAND_art }, 'o' }
3715 };
3716
3717 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
3718   { { OPERAND_art }, 'i' }
3719 };
3720
3721 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
3722   { { OPERAND_art }, 'm' }
3723 };
3724
3725 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
3726   { { OPERAND_art }, 'o' }
3727 };
3728
3729 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
3730   { { OPERAND_art }, 'i' }
3731 };
3732
3733 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
3734   { { OPERAND_art }, 'o' }
3735 };
3736
3737 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
3738   { { OPERAND_art }, 'o' }
3739 };
3740
3741 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
3742   { { STATE_PSWOE }, 'i' },
3743   { { STATE_PSCALLINC }, 'i' },
3744   { { STATE_PSOWB }, 'i' },
3745   { { STATE_PSUM }, 'i' },
3746   { { STATE_PSEXCM }, 'i' },
3747   { { STATE_PSINTLEVEL }, 'i' }
3748 };
3749
3750 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
3751   { { OPERAND_art }, 'i' }
3752 };
3753
3754 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
3755   { { STATE_PSWOE }, 'o' },
3756   { { STATE_PSCALLINC }, 'o' },
3757   { { STATE_PSOWB }, 'o' },
3758   { { STATE_PSUM }, 'o' },
3759   { { STATE_PSEXCM }, 'o' },
3760   { { STATE_PSINTLEVEL }, 'o' }
3761 };
3762
3763 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
3764   { { OPERAND_art }, 'm' }
3765 };
3766
3767 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
3768   { { STATE_PSWOE }, 'm' },
3769   { { STATE_PSCALLINC }, 'm' },
3770   { { STATE_PSOWB }, 'm' },
3771   { { STATE_PSUM }, 'm' },
3772   { { STATE_PSEXCM }, 'm' },
3773   { { STATE_PSINTLEVEL }, 'm' }
3774 };
3775
3776 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
3777   { { OPERAND_art }, 'o' }
3778 };
3779
3780 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
3781   { { STATE_EPC1 }, 'i' }
3782 };
3783
3784 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
3785   { { OPERAND_art }, 'i' }
3786 };
3787
3788 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
3789   { { STATE_EPC1 }, 'o' }
3790 };
3791
3792 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
3793   { { OPERAND_art }, 'm' }
3794 };
3795
3796 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
3797   { { STATE_EPC1 }, 'm' }
3798 };
3799
3800 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
3801   { { OPERAND_art }, 'o' }
3802 };
3803
3804 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
3805   { { STATE_EXCSAVE1 }, 'i' }
3806 };
3807
3808 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
3809   { { OPERAND_art }, 'i' }
3810 };
3811
3812 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
3813   { { STATE_EXCSAVE1 }, 'o' }
3814 };
3815
3816 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
3817   { { OPERAND_art }, 'm' }
3818 };
3819
3820 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
3821   { { STATE_EXCSAVE1 }, 'm' }
3822 };
3823
3824 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
3825   { { OPERAND_art }, 'o' }
3826 };
3827
3828 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
3829   { { STATE_EPC2 }, 'i' }
3830 };
3831
3832 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
3833   { { OPERAND_art }, 'i' }
3834 };
3835
3836 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
3837   { { STATE_EPC2 }, 'o' }
3838 };
3839
3840 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
3841   { { OPERAND_art }, 'm' }
3842 };
3843
3844 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
3845   { { STATE_EPC2 }, 'm' }
3846 };
3847
3848 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
3849   { { OPERAND_art }, 'o' }
3850 };
3851
3852 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
3853   { { STATE_EXCSAVE2 }, 'i' }
3854 };
3855
3856 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
3857   { { OPERAND_art }, 'i' }
3858 };
3859
3860 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
3861   { { STATE_EXCSAVE2 }, 'o' }
3862 };
3863
3864 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
3865   { { OPERAND_art }, 'm' }
3866 };
3867
3868 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
3869   { { STATE_EXCSAVE2 }, 'm' }
3870 };
3871
3872 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
3873   { { OPERAND_art }, 'o' }
3874 };
3875
3876 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
3877   { { STATE_EPC3 }, 'i' }
3878 };
3879
3880 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
3881   { { OPERAND_art }, 'i' }
3882 };
3883
3884 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
3885   { { STATE_EPC3 }, 'o' }
3886 };
3887
3888 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
3889   { { OPERAND_art }, 'm' }
3890 };
3891
3892 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
3893   { { STATE_EPC3 }, 'm' }
3894 };
3895
3896 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
3897   { { OPERAND_art }, 'o' }
3898 };
3899
3900 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
3901   { { STATE_EXCSAVE3 }, 'i' }
3902 };
3903
3904 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
3905   { { OPERAND_art }, 'i' }
3906 };
3907
3908 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
3909   { { STATE_EXCSAVE3 }, 'o' }
3910 };
3911
3912 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
3913   { { OPERAND_art }, 'm' }
3914 };
3915
3916 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
3917   { { STATE_EXCSAVE3 }, 'm' }
3918 };
3919
3920 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
3921   { { OPERAND_art }, 'o' }
3922 };
3923
3924 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
3925   { { STATE_EPC4 }, 'i' }
3926 };
3927
3928 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
3929   { { OPERAND_art }, 'i' }
3930 };
3931
3932 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
3933   { { STATE_EPC4 }, 'o' }
3934 };
3935
3936 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
3937   { { OPERAND_art }, 'm' }
3938 };
3939
3940 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
3941   { { STATE_EPC4 }, 'm' }
3942 };
3943
3944 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
3945   { { OPERAND_art }, 'o' }
3946 };
3947
3948 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
3949   { { STATE_EXCSAVE4 }, 'i' }
3950 };
3951
3952 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
3953   { { OPERAND_art }, 'i' }
3954 };
3955
3956 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
3957   { { STATE_EXCSAVE4 }, 'o' }
3958 };
3959
3960 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
3961   { { OPERAND_art }, 'm' }
3962 };
3963
3964 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
3965   { { STATE_EXCSAVE4 }, 'm' }
3966 };
3967
3968 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
3969   { { OPERAND_art }, 'o' }
3970 };
3971
3972 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
3973   { { STATE_EPC5 }, 'i' }
3974 };
3975
3976 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
3977   { { OPERAND_art }, 'i' }
3978 };
3979
3980 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
3981   { { STATE_EPC5 }, 'o' }
3982 };
3983
3984 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
3985   { { OPERAND_art }, 'm' }
3986 };
3987
3988 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
3989   { { STATE_EPC5 }, 'm' }
3990 };
3991
3992 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
3993   { { OPERAND_art }, 'o' }
3994 };
3995
3996 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
3997   { { STATE_EXCSAVE5 }, 'i' }
3998 };
3999
4000 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
4001   { { OPERAND_art }, 'i' }
4002 };
4003
4004 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
4005   { { STATE_EXCSAVE5 }, 'o' }
4006 };
4007
4008 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
4009   { { OPERAND_art }, 'm' }
4010 };
4011
4012 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
4013   { { STATE_EXCSAVE5 }, 'm' }
4014 };
4015
4016 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
4017   { { OPERAND_art }, 'o' }
4018 };
4019
4020 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
4021   { { STATE_EPC6 }, 'i' }
4022 };
4023
4024 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
4025   { { OPERAND_art }, 'i' }
4026 };
4027
4028 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
4029   { { STATE_EPC6 }, 'o' }
4030 };
4031
4032 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
4033   { { OPERAND_art }, 'm' }
4034 };
4035
4036 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
4037   { { STATE_EPC6 }, 'm' }
4038 };
4039
4040 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
4041   { { OPERAND_art }, 'o' }
4042 };
4043
4044 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
4045   { { STATE_EXCSAVE6 }, 'i' }
4046 };
4047
4048 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
4049   { { OPERAND_art }, 'i' }
4050 };
4051
4052 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
4053   { { STATE_EXCSAVE6 }, 'o' }
4054 };
4055
4056 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
4057   { { OPERAND_art }, 'm' }
4058 };
4059
4060 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
4061   { { STATE_EXCSAVE6 }, 'm' }
4062 };
4063
4064 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
4065   { { OPERAND_art }, 'o' }
4066 };
4067
4068 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
4069   { { STATE_EPC7 }, 'i' }
4070 };
4071
4072 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
4073   { { OPERAND_art }, 'i' }
4074 };
4075
4076 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
4077   { { STATE_EPC7 }, 'o' }
4078 };
4079
4080 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
4081   { { OPERAND_art }, 'm' }
4082 };
4083
4084 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
4085   { { STATE_EPC7 }, 'm' }
4086 };
4087
4088 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
4089   { { OPERAND_art }, 'o' }
4090 };
4091
4092 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
4093   { { STATE_EXCSAVE7 }, 'i' }
4094 };
4095
4096 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
4097   { { OPERAND_art }, 'i' }
4098 };
4099
4100 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
4101   { { STATE_EXCSAVE7 }, 'o' }
4102 };
4103
4104 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
4105   { { OPERAND_art }, 'm' }
4106 };
4107
4108 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
4109   { { STATE_EXCSAVE7 }, 'm' }
4110 };
4111
4112 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
4113   { { OPERAND_art }, 'o' }
4114 };
4115
4116 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
4117   { { STATE_EPS2 }, 'i' }
4118 };
4119
4120 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
4121   { { OPERAND_art }, 'i' }
4122 };
4123
4124 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
4125   { { STATE_EPS2 }, 'o' }
4126 };
4127
4128 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
4129   { { OPERAND_art }, 'm' }
4130 };
4131
4132 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
4133   { { STATE_EPS2 }, 'm' }
4134 };
4135
4136 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
4137   { { OPERAND_art }, 'o' }
4138 };
4139
4140 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
4141   { { STATE_EPS3 }, 'i' }
4142 };
4143
4144 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
4145   { { OPERAND_art }, 'i' }
4146 };
4147
4148 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
4149   { { STATE_EPS3 }, 'o' }
4150 };
4151
4152 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
4153   { { OPERAND_art }, 'm' }
4154 };
4155
4156 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
4157   { { STATE_EPS3 }, 'm' }
4158 };
4159
4160 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
4161   { { OPERAND_art }, 'o' }
4162 };
4163
4164 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
4165   { { STATE_EPS4 }, 'i' }
4166 };
4167
4168 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
4169   { { OPERAND_art }, 'i' }
4170 };
4171
4172 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
4173   { { STATE_EPS4 }, 'o' }
4174 };
4175
4176 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
4177   { { OPERAND_art }, 'm' }
4178 };
4179
4180 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
4181   { { STATE_EPS4 }, 'm' }
4182 };
4183
4184 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
4185   { { OPERAND_art }, 'o' }
4186 };
4187
4188 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
4189   { { STATE_EPS5 }, 'i' }
4190 };
4191
4192 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
4193   { { OPERAND_art }, 'i' }
4194 };
4195
4196 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
4197   { { STATE_EPS5 }, 'o' }
4198 };
4199
4200 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
4201   { { OPERAND_art }, 'm' }
4202 };
4203
4204 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
4205   { { STATE_EPS5 }, 'm' }
4206 };
4207
4208 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
4209   { { OPERAND_art }, 'o' }
4210 };
4211
4212 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
4213   { { STATE_EPS6 }, 'i' }
4214 };
4215
4216 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
4217   { { OPERAND_art }, 'i' }
4218 };
4219
4220 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
4221   { { STATE_EPS6 }, 'o' }
4222 };
4223
4224 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
4225   { { OPERAND_art }, 'm' }
4226 };
4227
4228 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
4229   { { STATE_EPS6 }, 'm' }
4230 };
4231
4232 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
4233   { { OPERAND_art }, 'o' }
4234 };
4235
4236 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
4237   { { STATE_EPS7 }, 'i' }
4238 };
4239
4240 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
4241   { { OPERAND_art }, 'i' }
4242 };
4243
4244 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
4245   { { STATE_EPS7 }, 'o' }
4246 };
4247
4248 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
4249   { { OPERAND_art }, 'm' }
4250 };
4251
4252 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
4253   { { STATE_EPS7 }, 'm' }
4254 };
4255
4256 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
4257   { { OPERAND_art }, 'o' }
4258 };
4259
4260 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
4261   { { STATE_EXCVADDR }, 'i' }
4262 };
4263
4264 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
4265   { { OPERAND_art }, 'i' }
4266 };
4267
4268 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
4269   { { STATE_EXCVADDR }, 'o' }
4270 };
4271
4272 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
4273   { { OPERAND_art }, 'm' }
4274 };
4275
4276 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
4277   { { STATE_EXCVADDR }, 'm' }
4278 };
4279
4280 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
4281   { { OPERAND_art }, 'o' }
4282 };
4283
4284 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
4285   { { STATE_DEPC }, 'i' }
4286 };
4287
4288 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
4289   { { OPERAND_art }, 'i' }
4290 };
4291
4292 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
4293   { { STATE_DEPC }, 'o' }
4294 };
4295
4296 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
4297   { { OPERAND_art }, 'm' }
4298 };
4299
4300 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
4301   { { STATE_DEPC }, 'm' }
4302 };
4303
4304 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
4305   { { OPERAND_art }, 'o' }
4306 };
4307
4308 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
4309   { { STATE_EXCCAUSE }, 'i' },
4310   { { STATE_XTSYNC }, 'i' }
4311 };
4312
4313 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
4314   { { OPERAND_art }, 'i' }
4315 };
4316
4317 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
4318   { { STATE_EXCCAUSE }, 'o' }
4319 };
4320
4321 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
4322   { { OPERAND_art }, 'm' }
4323 };
4324
4325 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
4326   { { STATE_EXCCAUSE }, 'm' }
4327 };
4328
4329 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
4330   { { OPERAND_art }, 'o' }
4331 };
4332
4333 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
4334   { { STATE_MISC0 }, 'i' }
4335 };
4336
4337 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
4338   { { OPERAND_art }, 'i' }
4339 };
4340
4341 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
4342   { { STATE_MISC0 }, 'o' }
4343 };
4344
4345 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
4346   { { OPERAND_art }, 'm' }
4347 };
4348
4349 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
4350   { { STATE_MISC0 }, 'm' }
4351 };
4352
4353 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
4354   { { OPERAND_art }, 'o' }
4355 };
4356
4357 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
4358   { { STATE_MISC1 }, 'i' }
4359 };
4360
4361 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
4362   { { OPERAND_art }, 'i' }
4363 };
4364
4365 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
4366   { { STATE_MISC1 }, 'o' }
4367 };
4368
4369 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
4370   { { OPERAND_art }, 'm' }
4371 };
4372
4373 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
4374   { { STATE_MISC1 }, 'm' }
4375 };
4376
4377 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
4378   { { OPERAND_art }, 'o' }
4379 };
4380
4381 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
4382   { { OPERAND_art }, 'o' }
4383 };
4384
4385 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
4386   { { STATE_VECBASE }, 'i' }
4387 };
4388
4389 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
4390   { { OPERAND_art }, 'i' }
4391 };
4392
4393 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
4394   { { STATE_VECBASE }, 'o' }
4395 };
4396
4397 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
4398   { { OPERAND_art }, 'm' }
4399 };
4400
4401 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
4402   { { STATE_VECBASE }, 'm' }
4403 };
4404
4405 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
4406   { { OPERAND_arr }, 'o' },
4407   { { OPERAND_ars }, 'i' },
4408   { { OPERAND_art }, 'i' }
4409 };
4410
4411 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
4412   { { OPERAND_arr }, 'o' },
4413   { { OPERAND_ars }, 'i' },
4414   { { OPERAND_art }, 'i' }
4415 };
4416
4417 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
4418   { { OPERAND_ars }, 'i' },
4419   { { OPERAND_art }, 'i' }
4420 };
4421
4422 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
4423   { { STATE_ACC }, 'o' }
4424 };
4425
4426 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
4427   { { OPERAND_ars }, 'i' },
4428   { { OPERAND_my }, 'i' }
4429 };
4430
4431 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
4432   { { STATE_ACC }, 'o' }
4433 };
4434
4435 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
4436   { { OPERAND_mx }, 'i' },
4437   { { OPERAND_art }, 'i' }
4438 };
4439
4440 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
4441   { { STATE_ACC }, 'o' }
4442 };
4443
4444 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
4445   { { OPERAND_mx }, 'i' },
4446   { { OPERAND_my }, 'i' }
4447 };
4448
4449 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
4450   { { STATE_ACC }, 'o' }
4451 };
4452
4453 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
4454   { { OPERAND_ars }, 'i' },
4455   { { OPERAND_art }, 'i' }
4456 };
4457
4458 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
4459   { { STATE_ACC }, 'm' }
4460 };
4461
4462 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
4463   { { OPERAND_ars }, 'i' },
4464   { { OPERAND_my }, 'i' }
4465 };
4466
4467 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
4468   { { STATE_ACC }, 'm' }
4469 };
4470
4471 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
4472   { { OPERAND_mx }, 'i' },
4473   { { OPERAND_art }, 'i' }
4474 };
4475
4476 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
4477   { { STATE_ACC }, 'm' }
4478 };
4479
4480 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
4481   { { OPERAND_mx }, 'i' },
4482   { { OPERAND_my }, 'i' }
4483 };
4484
4485 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
4486   { { STATE_ACC }, 'm' }
4487 };
4488
4489 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
4490   { { OPERAND_mw }, 'o' },
4491   { { OPERAND_ars }, 'm' },
4492   { { OPERAND_mx }, 'i' },
4493   { { OPERAND_art }, 'i' }
4494 };
4495
4496 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
4497   { { STATE_ACC }, 'm' }
4498 };
4499
4500 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
4501   { { OPERAND_mw }, 'o' },
4502   { { OPERAND_ars }, 'm' },
4503   { { OPERAND_mx }, 'i' },
4504   { { OPERAND_my }, 'i' }
4505 };
4506
4507 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
4508   { { STATE_ACC }, 'm' }
4509 };
4510
4511 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
4512   { { OPERAND_mw }, 'o' },
4513   { { OPERAND_ars }, 'm' }
4514 };
4515
4516 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
4517   { { OPERAND_art }, 'o' },
4518   { { OPERAND_mr0 }, 'i' }
4519 };
4520
4521 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
4522   { { OPERAND_art }, 'i' },
4523   { { OPERAND_mr0 }, 'o' }
4524 };
4525
4526 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
4527   { { OPERAND_art }, 'm' },
4528   { { OPERAND_mr0 }, 'm' }
4529 };
4530
4531 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
4532   { { OPERAND_art }, 'o' },
4533   { { OPERAND_mr1 }, 'i' }
4534 };
4535
4536 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
4537   { { OPERAND_art }, 'i' },
4538   { { OPERAND_mr1 }, 'o' }
4539 };
4540
4541 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
4542   { { OPERAND_art }, 'm' },
4543   { { OPERAND_mr1 }, 'm' }
4544 };
4545
4546 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
4547   { { OPERAND_art }, 'o' },
4548   { { OPERAND_mr2 }, 'i' }
4549 };
4550
4551 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
4552   { { OPERAND_art }, 'i' },
4553   { { OPERAND_mr2 }, 'o' }
4554 };
4555
4556 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
4557   { { OPERAND_art }, 'm' },
4558   { { OPERAND_mr2 }, 'm' }
4559 };
4560
4561 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
4562   { { OPERAND_art }, 'o' },
4563   { { OPERAND_mr3 }, 'i' }
4564 };
4565
4566 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
4567   { { OPERAND_art }, 'i' },
4568   { { OPERAND_mr3 }, 'o' }
4569 };
4570
4571 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
4572   { { OPERAND_art }, 'm' },
4573   { { OPERAND_mr3 }, 'm' }
4574 };
4575
4576 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
4577   { { OPERAND_art }, 'o' }
4578 };
4579
4580 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
4581   { { STATE_ACC }, 'i' }
4582 };
4583
4584 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
4585   { { OPERAND_art }, 'i' }
4586 };
4587
4588 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
4589   { { STATE_ACC }, 'm' }
4590 };
4591
4592 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
4593   { { OPERAND_art }, 'm' }
4594 };
4595
4596 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
4597   { { STATE_ACC }, 'm' }
4598 };
4599
4600 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
4601   { { OPERAND_art }, 'o' }
4602 };
4603
4604 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
4605   { { STATE_ACC }, 'i' }
4606 };
4607
4608 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
4609   { { OPERAND_art }, 'i' }
4610 };
4611
4612 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
4613   { { STATE_ACC }, 'm' }
4614 };
4615
4616 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
4617   { { OPERAND_art }, 'm' }
4618 };
4619
4620 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
4621   { { STATE_ACC }, 'm' }
4622 };
4623
4624 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
4625   { { OPERAND_s }, 'i' }
4626 };
4627
4628 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
4629   { { STATE_PSWOE }, 'o' },
4630   { { STATE_PSCALLINC }, 'o' },
4631   { { STATE_PSOWB }, 'o' },
4632   { { STATE_PSUM }, 'o' },
4633   { { STATE_PSEXCM }, 'o' },
4634   { { STATE_PSINTLEVEL }, 'o' },
4635   { { STATE_EPC1 }, 'i' },
4636   { { STATE_EPC2 }, 'i' },
4637   { { STATE_EPC3 }, 'i' },
4638   { { STATE_EPC4 }, 'i' },
4639   { { STATE_EPC5 }, 'i' },
4640   { { STATE_EPC6 }, 'i' },
4641   { { STATE_EPC7 }, 'i' },
4642   { { STATE_EPS2 }, 'i' },
4643   { { STATE_EPS3 }, 'i' },
4644   { { STATE_EPS4 }, 'i' },
4645   { { STATE_EPS5 }, 'i' },
4646   { { STATE_EPS6 }, 'i' },
4647   { { STATE_EPS7 }, 'i' },
4648   { { STATE_InOCDMode }, 'm' }
4649 };
4650
4651 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
4652   { { OPERAND_s }, 'i' }
4653 };
4654
4655 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
4656   { { STATE_PSINTLEVEL }, 'o' }
4657 };
4658
4659 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
4660   { { OPERAND_art }, 'o' }
4661 };
4662
4663 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
4664   { { STATE_INTERRUPT }, 'i' }
4665 };
4666
4667 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
4668   { { OPERAND_art }, 'i' }
4669 };
4670
4671 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
4672   { { STATE_XTSYNC }, 'o' },
4673   { { STATE_INTERRUPT }, 'm' }
4674 };
4675
4676 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
4677   { { OPERAND_art }, 'i' }
4678 };
4679
4680 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
4681   { { STATE_XTSYNC }, 'o' },
4682   { { STATE_INTERRUPT }, 'm' }
4683 };
4684
4685 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
4686   { { OPERAND_art }, 'o' }
4687 };
4688
4689 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
4690   { { STATE_INTENABLE }, 'i' }
4691 };
4692
4693 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
4694   { { OPERAND_art }, 'i' }
4695 };
4696
4697 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
4698   { { STATE_INTENABLE }, 'o' }
4699 };
4700
4701 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
4702   { { OPERAND_art }, 'm' }
4703 };
4704
4705 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
4706   { { STATE_INTENABLE }, 'm' }
4707 };
4708
4709 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
4710   { { OPERAND_imms }, 'i' },
4711   { { OPERAND_immt }, 'i' }
4712 };
4713
4714 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
4715   { { STATE_PSEXCM }, 'i' },
4716   { { STATE_PSINTLEVEL }, 'i' }
4717 };
4718
4719 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
4720   { { OPERAND_imms }, 'i' }
4721 };
4722
4723 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
4724   { { STATE_PSEXCM }, 'i' },
4725   { { STATE_PSINTLEVEL }, 'i' }
4726 };
4727
4728 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
4729   { { OPERAND_art }, 'o' }
4730 };
4731
4732 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
4733   { { STATE_DBREAKA0 }, 'i' }
4734 };
4735
4736 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
4737   { { OPERAND_art }, 'i' }
4738 };
4739
4740 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
4741   { { STATE_DBREAKA0 }, 'o' },
4742   { { STATE_XTSYNC }, 'o' }
4743 };
4744
4745 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
4746   { { OPERAND_art }, 'm' }
4747 };
4748
4749 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
4750   { { STATE_DBREAKA0 }, 'm' },
4751   { { STATE_XTSYNC }, 'o' }
4752 };
4753
4754 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
4755   { { OPERAND_art }, 'o' }
4756 };
4757
4758 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
4759   { { STATE_DBREAKC0 }, 'i' }
4760 };
4761
4762 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
4763   { { OPERAND_art }, 'i' }
4764 };
4765
4766 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
4767   { { STATE_DBREAKC0 }, 'o' },
4768   { { STATE_XTSYNC }, 'o' }
4769 };
4770
4771 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
4772   { { OPERAND_art }, 'm' }
4773 };
4774
4775 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
4776   { { STATE_DBREAKC0 }, 'm' },
4777   { { STATE_XTSYNC }, 'o' }
4778 };
4779
4780 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
4781   { { OPERAND_art }, 'o' }
4782 };
4783
4784 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
4785   { { STATE_DBREAKA1 }, 'i' }
4786 };
4787
4788 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
4789   { { OPERAND_art }, 'i' }
4790 };
4791
4792 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
4793   { { STATE_DBREAKA1 }, 'o' },
4794   { { STATE_XTSYNC }, 'o' }
4795 };
4796
4797 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
4798   { { OPERAND_art }, 'm' }
4799 };
4800
4801 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
4802   { { STATE_DBREAKA1 }, 'm' },
4803   { { STATE_XTSYNC }, 'o' }
4804 };
4805
4806 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
4807   { { OPERAND_art }, 'o' }
4808 };
4809
4810 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
4811   { { STATE_DBREAKC1 }, 'i' }
4812 };
4813
4814 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
4815   { { OPERAND_art }, 'i' }
4816 };
4817
4818 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
4819   { { STATE_DBREAKC1 }, 'o' },
4820   { { STATE_XTSYNC }, 'o' }
4821 };
4822
4823 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
4824   { { OPERAND_art }, 'm' }
4825 };
4826
4827 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
4828   { { STATE_DBREAKC1 }, 'm' },
4829   { { STATE_XTSYNC }, 'o' }
4830 };
4831
4832 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
4833   { { OPERAND_art }, 'o' }
4834 };
4835
4836 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
4837   { { STATE_IBREAKA0 }, 'i' }
4838 };
4839
4840 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
4841   { { OPERAND_art }, 'i' }
4842 };
4843
4844 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
4845   { { STATE_IBREAKA0 }, 'o' }
4846 };
4847
4848 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
4849   { { OPERAND_art }, 'm' }
4850 };
4851
4852 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
4853   { { STATE_IBREAKA0 }, 'm' }
4854 };
4855
4856 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
4857   { { OPERAND_art }, 'o' }
4858 };
4859
4860 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
4861   { { STATE_IBREAKA1 }, 'i' }
4862 };
4863
4864 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
4865   { { OPERAND_art }, 'i' }
4866 };
4867
4868 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
4869   { { STATE_IBREAKA1 }, 'o' }
4870 };
4871
4872 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
4873   { { OPERAND_art }, 'm' }
4874 };
4875
4876 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
4877   { { STATE_IBREAKA1 }, 'm' }
4878 };
4879
4880 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
4881   { { OPERAND_art }, 'o' }
4882 };
4883
4884 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
4885   { { STATE_IBREAKENABLE }, 'i' }
4886 };
4887
4888 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
4889   { { OPERAND_art }, 'i' }
4890 };
4891
4892 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
4893   { { STATE_IBREAKENABLE }, 'o' }
4894 };
4895
4896 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
4897   { { OPERAND_art }, 'm' }
4898 };
4899
4900 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
4901   { { STATE_IBREAKENABLE }, 'm' }
4902 };
4903
4904 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
4905   { { OPERAND_art }, 'o' }
4906 };
4907
4908 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
4909   { { STATE_DEBUGCAUSE }, 'i' },
4910   { { STATE_DBNUM }, 'i' }
4911 };
4912
4913 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
4914   { { OPERAND_art }, 'i' }
4915 };
4916
4917 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
4918   { { STATE_DEBUGCAUSE }, 'o' },
4919   { { STATE_DBNUM }, 'o' }
4920 };
4921
4922 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
4923   { { OPERAND_art }, 'm' }
4924 };
4925
4926 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
4927   { { STATE_DEBUGCAUSE }, 'm' },
4928   { { STATE_DBNUM }, 'm' }
4929 };
4930
4931 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
4932   { { OPERAND_art }, 'o' }
4933 };
4934
4935 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
4936   { { STATE_ICOUNT }, 'i' }
4937 };
4938
4939 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
4940   { { OPERAND_art }, 'i' }
4941 };
4942
4943 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
4944   { { STATE_XTSYNC }, 'o' },
4945   { { STATE_ICOUNT }, 'o' }
4946 };
4947
4948 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
4949   { { OPERAND_art }, 'm' }
4950 };
4951
4952 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
4953   { { STATE_XTSYNC }, 'o' },
4954   { { STATE_ICOUNT }, 'm' }
4955 };
4956
4957 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
4958   { { OPERAND_art }, 'o' }
4959 };
4960
4961 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
4962   { { STATE_ICOUNTLEVEL }, 'i' }
4963 };
4964
4965 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
4966   { { OPERAND_art }, 'i' }
4967 };
4968
4969 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
4970   { { STATE_ICOUNTLEVEL }, 'o' }
4971 };
4972
4973 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
4974   { { OPERAND_art }, 'm' }
4975 };
4976
4977 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
4978   { { STATE_ICOUNTLEVEL }, 'm' }
4979 };
4980
4981 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
4982   { { OPERAND_art }, 'o' }
4983 };
4984
4985 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
4986   { { STATE_DDR }, 'i' }
4987 };
4988
4989 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
4990   { { OPERAND_art }, 'i' }
4991 };
4992
4993 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
4994   { { STATE_XTSYNC }, 'o' },
4995   { { STATE_DDR }, 'o' }
4996 };
4997
4998 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
4999   { { OPERAND_art }, 'm' }
5000 };
5001
5002 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
5003   { { STATE_XTSYNC }, 'o' },
5004   { { STATE_DDR }, 'm' }
5005 };
5006
5007 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
5008   { { OPERAND_ars }, 'm' }
5009 };
5010
5011 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
5012   { { STATE_XTSYNC }, 'o' },
5013   { { STATE_InOCDMode }, 'i' },
5014   { { STATE_DDR }, 'o' }
5015 };
5016
5017 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
5018   { { OPERAND_ars }, 'm' }
5019 };
5020
5021 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
5022   { { STATE_InOCDMode }, 'i' },
5023   { { STATE_DDR }, 'i' }
5024 };
5025
5026 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
5027   { { OPERAND_imms }, 'i' }
5028 };
5029
5030 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
5031   { { STATE_InOCDMode }, 'm' },
5032   { { STATE_EPC6 }, 'i' },
5033   { { STATE_PSWOE }, 'o' },
5034   { { STATE_PSCALLINC }, 'o' },
5035   { { STATE_PSOWB }, 'o' },
5036   { { STATE_PSUM }, 'o' },
5037   { { STATE_PSEXCM }, 'o' },
5038   { { STATE_PSINTLEVEL }, 'o' },
5039   { { STATE_EPS6 }, 'i' }
5040 };
5041
5042 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
5043   { { STATE_InOCDMode }, 'm' }
5044 };
5045
5046 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
5047   { { OPERAND_art }, 'i' }
5048 };
5049
5050 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
5051   { { STATE_XTSYNC }, 'o' }
5052 };
5053
5054 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
5055   { { OPERAND_art }, 'o' }
5056 };
5057
5058 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
5059   { { STATE_CCOUNT }, 'i' }
5060 };
5061
5062 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
5063   { { OPERAND_art }, 'i' }
5064 };
5065
5066 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
5067   { { STATE_XTSYNC }, 'o' },
5068   { { STATE_CCOUNT }, 'o' }
5069 };
5070
5071 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
5072   { { OPERAND_art }, 'm' }
5073 };
5074
5075 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
5076   { { STATE_XTSYNC }, 'o' },
5077   { { STATE_CCOUNT }, 'm' }
5078 };
5079
5080 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
5081   { { OPERAND_art }, 'o' }
5082 };
5083
5084 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
5085   { { STATE_CCOMPARE0 }, 'i' }
5086 };
5087
5088 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
5089   { { OPERAND_art }, 'i' }
5090 };
5091
5092 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
5093   { { STATE_CCOMPARE0 }, 'o' },
5094   { { STATE_INTERRUPT }, 'm' }
5095 };
5096
5097 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
5098   { { OPERAND_art }, 'm' }
5099 };
5100
5101 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
5102   { { STATE_CCOMPARE0 }, 'm' },
5103   { { STATE_INTERRUPT }, 'm' }
5104 };
5105
5106 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
5107   { { OPERAND_art }, 'o' }
5108 };
5109
5110 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
5111   { { STATE_CCOMPARE1 }, 'i' }
5112 };
5113
5114 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
5115   { { OPERAND_art }, 'i' }
5116 };
5117
5118 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
5119   { { STATE_CCOMPARE1 }, 'o' },
5120   { { STATE_INTERRUPT }, 'm' }
5121 };
5122
5123 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
5124   { { OPERAND_art }, 'm' }
5125 };
5126
5127 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
5128   { { STATE_CCOMPARE1 }, 'm' },
5129   { { STATE_INTERRUPT }, 'm' }
5130 };
5131
5132 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
5133   { { OPERAND_art }, 'o' }
5134 };
5135
5136 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
5137   { { STATE_CCOMPARE2 }, 'i' }
5138 };
5139
5140 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
5141   { { OPERAND_art }, 'i' }
5142 };
5143
5144 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
5145   { { STATE_CCOMPARE2 }, 'o' },
5146   { { STATE_INTERRUPT }, 'm' }
5147 };
5148
5149 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
5150   { { OPERAND_art }, 'm' }
5151 };
5152
5153 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
5154   { { STATE_CCOMPARE2 }, 'm' },
5155   { { STATE_INTERRUPT }, 'm' }
5156 };
5157
5158 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
5159   { { OPERAND_ars }, 'i' },
5160   { { OPERAND_uimm8x4 }, 'i' }
5161 };
5162
5163 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
5164   { { OPERAND_ars }, 'i' },
5165   { { OPERAND_uimm4x16 }, 'i' }
5166 };
5167
5168 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
5169   { { OPERAND_ars }, 'i' },
5170   { { OPERAND_uimm8x4 }, 'i' }
5171 };
5172
5173 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
5174   { { OPERAND_art }, 'o' },
5175   { { OPERAND_ars }, 'i' }
5176 };
5177
5178 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
5179   { { OPERAND_art }, 'i' },
5180   { { OPERAND_ars }, 'i' }
5181 };
5182
5183 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
5184   { { OPERAND_ars }, 'i' },
5185   { { OPERAND_uimm8x4 }, 'i' }
5186 };
5187
5188 static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = {
5189   { { OPERAND_ars }, 'm' }
5190 };
5191
5192 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
5193   { { OPERAND_ars }, 'i' },
5194   { { OPERAND_uimm4x16 }, 'i' }
5195 };
5196
5197 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
5198   { { OPERAND_ars }, 'i' },
5199   { { OPERAND_uimm8x4 }, 'i' }
5200 };
5201
5202 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
5203   { { OPERAND_ars }, 'i' },
5204   { { OPERAND_uimm8x4 }, 'i' }
5205 };
5206
5207 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
5208   { { OPERAND_ars }, 'i' },
5209   { { OPERAND_uimm4x16 }, 'i' }
5210 };
5211
5212 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
5213   { { OPERAND_art }, 'i' },
5214   { { OPERAND_ars }, 'i' }
5215 };
5216
5217 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
5218   { { OPERAND_art }, 'o' },
5219   { { OPERAND_ars }, 'i' }
5220 };
5221
5222 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
5223   { { OPERAND_ars }, 'i' }
5224 };
5225
5226 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
5227   { { STATE_XTSYNC }, 'o' }
5228 };
5229
5230 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
5231   { { OPERAND_art }, 'o' },
5232   { { OPERAND_ars }, 'i' }
5233 };
5234
5235 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
5236   { { OPERAND_art }, 'i' },
5237   { { OPERAND_ars }, 'i' }
5238 };
5239
5240 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
5241   { { STATE_XTSYNC }, 'o' }
5242 };
5243
5244 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
5245   { { OPERAND_ars }, 'i' }
5246 };
5247
5248 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
5249   { { OPERAND_art }, 'o' },
5250   { { OPERAND_ars }, 'i' }
5251 };
5252
5253 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
5254   { { OPERAND_art }, 'i' },
5255   { { OPERAND_ars }, 'i' }
5256 };
5257
5258 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
5259   { { OPERAND_arr }, 'o' },
5260   { { OPERAND_ars }, 'i' },
5261   { { OPERAND_tp7 }, 'i' }
5262 };
5263
5264 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
5265   { { OPERAND_arr }, 'o' },
5266   { { OPERAND_ars }, 'i' },
5267   { { OPERAND_art }, 'i' }
5268 };
5269
5270 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
5271   { { OPERAND_art }, 'o' },
5272   { { OPERAND_ars }, 'i' }
5273 };
5274
5275 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
5276   { { OPERAND_arr }, 'o' },
5277   { { OPERAND_ars }, 'i' },
5278   { { OPERAND_tp7 }, 'i' }
5279 };
5280
5281 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
5282   { { OPERAND_art }, 'o' },
5283   { { OPERAND_ars }, 'i' },
5284   { { OPERAND_uimm8x4 }, 'i' }
5285 };
5286
5287 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
5288   { { OPERAND_art }, 'i' },
5289   { { OPERAND_ars }, 'i' },
5290   { { OPERAND_uimm8x4 }, 'i' }
5291 };
5292
5293 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
5294   { { OPERAND_art }, 'm' },
5295   { { OPERAND_ars }, 'i' },
5296   { { OPERAND_uimm8x4 }, 'i' }
5297 };
5298
5299 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
5300   { { STATE_SCOMPARE1 }, 'i' },
5301   { { STATE_XTSYNC }, 'i' },
5302   { { STATE_SCOMPARE1 }, 'i' }
5303 };
5304
5305 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
5306   { { OPERAND_art }, 'o' }
5307 };
5308
5309 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
5310   { { STATE_SCOMPARE1 }, 'i' }
5311 };
5312
5313 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
5314   { { OPERAND_art }, 'i' }
5315 };
5316
5317 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
5318   { { STATE_SCOMPARE1 }, 'o' }
5319 };
5320
5321 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
5322   { { OPERAND_art }, 'm' }
5323 };
5324
5325 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
5326   { { STATE_SCOMPARE1 }, 'm' }
5327 };
5328
5329 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
5330   { { OPERAND_art }, 'o' }
5331 };
5332
5333 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
5334   { { STATE_ATOMCTL }, 'i' }
5335 };
5336
5337 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
5338   { { OPERAND_art }, 'i' }
5339 };
5340
5341 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
5342   { { STATE_ATOMCTL }, 'o' },
5343   { { STATE_XTSYNC }, 'o' }
5344 };
5345
5346 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
5347   { { OPERAND_art }, 'm' }
5348 };
5349
5350 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
5351   { { STATE_ATOMCTL }, 'm' },
5352   { { STATE_XTSYNC }, 'o' }
5353 };
5354
5355 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
5356   { { OPERAND_arr }, 'o' },
5357   { { OPERAND_ars }, 'i' },
5358   { { OPERAND_art }, 'i' }
5359 };
5360
5361 static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
5362   { { OPERAND_art }, 'o' },
5363   { { OPERAND_ars }, 'i' }
5364 };
5365
5366 static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
5367   { { STATE_ERI_RAW_INTERLOCK }, 'i' }
5368 };
5369
5370 static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
5371   INTERFACE_ERI_RD_In,
5372   INTERFACE_ERI_RD_Out
5373 };
5374
5375 static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
5376   { { OPERAND_art }, 'i' },
5377   { { OPERAND_ars }, 'i' }
5378 };
5379
5380 static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
5381   { { STATE_ERI_RAW_INTERLOCK }, 'o' }
5382 };
5383
5384 static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
5385   INTERFACE_ERI_WR_In,
5386   INTERFACE_ERI_WR_Out
5387 };
5388
5389 static xtensa_arg_internal Iclass_rur_expstate_args[] = {
5390   { { OPERAND_arr }, 'o' }
5391 };
5392
5393 static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
5394   { { STATE_EXPSTATE }, 'i' }
5395 };
5396
5397 static xtensa_arg_internal Iclass_wur_expstate_args[] = {
5398   { { OPERAND_art }, 'i' }
5399 };
5400
5401 static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
5402   { { STATE_EXPSTATE }, 'o' }
5403 };
5404
5405 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
5406   { { OPERAND_art }, 'o' }
5407 };
5408
5409 static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
5410   INTERFACE_IMPWIRE
5411 };
5412
5413 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
5414   { { OPERAND_bitindex }, 'i' }
5415 };
5416
5417 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
5418   { { STATE_EXPSTATE }, 'm' }
5419 };
5420
5421 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
5422   { { OPERAND_bitindex }, 'i' }
5423 };
5424
5425 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
5426   { { STATE_EXPSTATE }, 'm' }
5427 };
5428
5429 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
5430   { { OPERAND_art }, 'i' },
5431   { { OPERAND_ars }, 'i' }
5432 };
5433
5434 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
5435   { { STATE_EXPSTATE }, 'm' }
5436 };
5437
5438 static xtensa_iclass_internal iclasses[] = {
5439   { 0, 0 /* xt_iclass_excw */,
5440     0, 0, 0, 0 },
5441   { 0, 0 /* xt_iclass_rfe */,
5442     2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
5443   { 0, 0 /* xt_iclass_rfde */,
5444     1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
5445   { 0, 0 /* xt_iclass_syscall */,
5446     0, 0, 0, 0 },
5447   { 2, Iclass_xt_iclass_call12_args,
5448     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
5449   { 2, Iclass_xt_iclass_call8_args,
5450     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
5451   { 2, Iclass_xt_iclass_call4_args,
5452     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
5453   { 2, Iclass_xt_iclass_callx12_args,
5454     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
5455   { 2, Iclass_xt_iclass_callx8_args,
5456     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
5457   { 2, Iclass_xt_iclass_callx4_args,
5458     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
5459   { 3, Iclass_xt_iclass_entry_args,
5460     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
5461   { 2, Iclass_xt_iclass_movsp_args,
5462     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
5463   { 1, Iclass_xt_iclass_rotw_args,
5464     1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
5465   { 1, Iclass_xt_iclass_retw_args,
5466     5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
5467   { 0, 0 /* xt_iclass_rfwou */,
5468     5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
5469   { 3, Iclass_xt_iclass_l32e_args,
5470     0, 0, 0, 0 },
5471   { 3, Iclass_xt_iclass_s32e_args,
5472     0, 0, 0, 0 },
5473   { 1, Iclass_xt_iclass_rsr_windowbase_args,
5474     1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
5475   { 1, Iclass_xt_iclass_wsr_windowbase_args,
5476     1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
5477   { 1, Iclass_xt_iclass_xsr_windowbase_args,
5478     1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
5479   { 1, Iclass_xt_iclass_rsr_windowstart_args,
5480     1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
5481   { 1, Iclass_xt_iclass_wsr_windowstart_args,
5482     1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
5483   { 1, Iclass_xt_iclass_xsr_windowstart_args,
5484     1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
5485   { 3, Iclass_xt_iclass_add_n_args,
5486     0, 0, 0, 0 },
5487   { 3, Iclass_xt_iclass_addi_n_args,
5488     0, 0, 0, 0 },
5489   { 2, Iclass_xt_iclass_bz6_args,
5490     0, 0, 0, 0 },
5491   { 0, 0 /* xt_iclass_ill_n */,
5492     0, 0, 0, 0 },
5493   { 3, Iclass_xt_iclass_loadi4_args,
5494     0, 0, 0, 0 },
5495   { 2, Iclass_xt_iclass_mov_n_args,
5496     0, 0, 0, 0 },
5497   { 2, Iclass_xt_iclass_movi_n_args,
5498     0, 0, 0, 0 },
5499   { 0, 0 /* xt_iclass_nopn */,
5500     0, 0, 0, 0 },
5501   { 1, Iclass_xt_iclass_retn_args,
5502     0, 0, 0, 0 },
5503   { 3, Iclass_xt_iclass_storei4_args,
5504     0, 0, 0, 0 },
5505   { 3, Iclass_xt_iclass_addi_args,
5506     0, 0, 0, 0 },
5507   { 3, Iclass_xt_iclass_addmi_args,
5508     0, 0, 0, 0 },
5509   { 3, Iclass_xt_iclass_addsub_args,
5510     0, 0, 0, 0 },
5511   { 3, Iclass_xt_iclass_bit_args,
5512     0, 0, 0, 0 },
5513   { 3, Iclass_xt_iclass_bsi8_args,
5514     0, 0, 0, 0 },
5515   { 3, Iclass_xt_iclass_bsi8b_args,
5516     0, 0, 0, 0 },
5517   { 3, Iclass_xt_iclass_bsi8u_args,
5518     0, 0, 0, 0 },
5519   { 3, Iclass_xt_iclass_bst8_args,
5520     0, 0, 0, 0 },
5521   { 2, Iclass_xt_iclass_bsz12_args,
5522     0, 0, 0, 0 },
5523   { 2, Iclass_xt_iclass_call0_args,
5524     0, 0, 0, 0 },
5525   { 2, Iclass_xt_iclass_callx0_args,
5526     0, 0, 0, 0 },
5527   { 4, Iclass_xt_iclass_exti_args,
5528     0, 0, 0, 0 },
5529   { 0, 0 /* xt_iclass_ill */,
5530     0, 0, 0, 0 },
5531   { 1, Iclass_xt_iclass_jump_args,
5532     0, 0, 0, 0 },
5533   { 1, Iclass_xt_iclass_jumpx_args,
5534     0, 0, 0, 0 },
5535   { 3, Iclass_xt_iclass_l16ui_args,
5536     0, 0, 0, 0 },
5537   { 3, Iclass_xt_iclass_l16si_args,
5538     0, 0, 0, 0 },
5539   { 3, Iclass_xt_iclass_l32i_args,
5540     0, 0, 0, 0 },
5541   { 2, Iclass_xt_iclass_l32r_args,
5542     0, 0, 0, 0 },
5543   { 3, Iclass_xt_iclass_l8i_args,
5544     0, 0, 0, 0 },
5545   { 2, Iclass_xt_iclass_loop_args,
5546     3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
5547   { 2, Iclass_xt_iclass_loopz_args,
5548     3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
5549   { 2, Iclass_xt_iclass_movi_args,
5550     0, 0, 0, 0 },
5551   { 3, Iclass_xt_iclass_movz_args,
5552     0, 0, 0, 0 },
5553   { 2, Iclass_xt_iclass_neg_args,
5554     0, 0, 0, 0 },
5555   { 0, 0 /* xt_iclass_nop */,
5556     0, 0, 0, 0 },
5557   { 1, Iclass_xt_iclass_return_args,
5558     0, 0, 0, 0 },
5559   { 0, 0 /* xt_iclass_simcall */,
5560     0, 0, 0, 0 },
5561   { 3, Iclass_xt_iclass_s16i_args,
5562     0, 0, 0, 0 },
5563   { 3, Iclass_xt_iclass_s32i_args,
5564     0, 0, 0, 0 },
5565   { 3, Iclass_xt_iclass_s32nb_args,
5566     0, 0, 0, 0 },
5567   { 3, Iclass_xt_iclass_s8i_args,
5568     0, 0, 0, 0 },
5569   { 1, Iclass_xt_iclass_sar_args,
5570     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
5571   { 1, Iclass_xt_iclass_sari_args,
5572     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
5573   { 2, Iclass_xt_iclass_shifts_args,
5574     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
5575   { 3, Iclass_xt_iclass_shiftst_args,
5576     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
5577   { 2, Iclass_xt_iclass_shiftt_args,
5578     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
5579   { 3, Iclass_xt_iclass_slli_args,
5580     0, 0, 0, 0 },
5581   { 3, Iclass_xt_iclass_srai_args,
5582     0, 0, 0, 0 },
5583   { 3, Iclass_xt_iclass_srli_args,
5584     0, 0, 0, 0 },
5585   { 0, 0 /* xt_iclass_memw */,
5586     0, 0, 0, 0 },
5587   { 0, 0 /* xt_iclass_extw */,
5588     0, 0, 0, 0 },
5589   { 0, 0 /* xt_iclass_isync */,
5590     0, 0, 0, 0 },
5591   { 0, 0 /* xt_iclass_sync */,
5592     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
5593   { 2, Iclass_xt_iclass_rsil_args,
5594     6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
5595   { 1, Iclass_xt_iclass_rsr_lend_args,
5596     1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
5597   { 1, Iclass_xt_iclass_wsr_lend_args,
5598     1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
5599   { 1, Iclass_xt_iclass_xsr_lend_args,
5600     1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
5601   { 1, Iclass_xt_iclass_rsr_lcount_args,
5602     1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
5603   { 1, Iclass_xt_iclass_wsr_lcount_args,
5604     2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
5605   { 1, Iclass_xt_iclass_xsr_lcount_args,
5606     2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
5607   { 1, Iclass_xt_iclass_rsr_lbeg_args,
5608     1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
5609   { 1, Iclass_xt_iclass_wsr_lbeg_args,
5610     1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
5611   { 1, Iclass_xt_iclass_xsr_lbeg_args,
5612     1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
5613   { 1, Iclass_xt_iclass_rsr_sar_args,
5614     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
5615   { 1, Iclass_xt_iclass_wsr_sar_args,
5616     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
5617   { 1, Iclass_xt_iclass_xsr_sar_args,
5618     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
5619   { 1, Iclass_xt_iclass_rsr_memctl_args,
5620     0, 0, 0, 0 },
5621   { 1, Iclass_xt_iclass_wsr_memctl_args,
5622     0, 0, 0, 0 },
5623   { 1, Iclass_xt_iclass_xsr_memctl_args,
5624     0, 0, 0, 0 },
5625   { 1, Iclass_xt_iclass_rsr_litbase_args,
5626     0, 0, 0, 0 },
5627   { 1, Iclass_xt_iclass_wsr_litbase_args,
5628     0, 0, 0, 0 },
5629   { 1, Iclass_xt_iclass_xsr_litbase_args,
5630     0, 0, 0, 0 },
5631   { 1, Iclass_xt_iclass_rsr_configid0_args,
5632     0, 0, 0, 0 },
5633   { 1, Iclass_xt_iclass_wsr_configid0_args,
5634     0, 0, 0, 0 },
5635   { 1, Iclass_xt_iclass_rsr_configid1_args,
5636     0, 0, 0, 0 },
5637   { 1, Iclass_xt_iclass_rsr_ps_args,
5638     6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
5639   { 1, Iclass_xt_iclass_wsr_ps_args,
5640     6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
5641   { 1, Iclass_xt_iclass_xsr_ps_args,
5642     6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
5643   { 1, Iclass_xt_iclass_rsr_epc1_args,
5644     1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
5645   { 1, Iclass_xt_iclass_wsr_epc1_args,
5646     1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
5647   { 1, Iclass_xt_iclass_xsr_epc1_args,
5648     1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
5649   { 1, Iclass_xt_iclass_rsr_excsave1_args,
5650     1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
5651   { 1, Iclass_xt_iclass_wsr_excsave1_args,
5652     1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
5653   { 1, Iclass_xt_iclass_xsr_excsave1_args,
5654     1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
5655   { 1, Iclass_xt_iclass_rsr_epc2_args,
5656     1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
5657   { 1, Iclass_xt_iclass_wsr_epc2_args,
5658     1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
5659   { 1, Iclass_xt_iclass_xsr_epc2_args,
5660     1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
5661   { 1, Iclass_xt_iclass_rsr_excsave2_args,
5662     1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
5663   { 1, Iclass_xt_iclass_wsr_excsave2_args,
5664     1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
5665   { 1, Iclass_xt_iclass_xsr_excsave2_args,
5666     1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
5667   { 1, Iclass_xt_iclass_rsr_epc3_args,
5668     1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
5669   { 1, Iclass_xt_iclass_wsr_epc3_args,
5670     1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
5671   { 1, Iclass_xt_iclass_xsr_epc3_args,
5672     1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
5673   { 1, Iclass_xt_iclass_rsr_excsave3_args,
5674     1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
5675   { 1, Iclass_xt_iclass_wsr_excsave3_args,
5676     1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
5677   { 1, Iclass_xt_iclass_xsr_excsave3_args,
5678     1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
5679   { 1, Iclass_xt_iclass_rsr_epc4_args,
5680     1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
5681   { 1, Iclass_xt_iclass_wsr_epc4_args,
5682     1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
5683   { 1, Iclass_xt_iclass_xsr_epc4_args,
5684     1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
5685   { 1, Iclass_xt_iclass_rsr_excsave4_args,
5686     1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
5687   { 1, Iclass_xt_iclass_wsr_excsave4_args,
5688     1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
5689   { 1, Iclass_xt_iclass_xsr_excsave4_args,
5690     1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
5691   { 1, Iclass_xt_iclass_rsr_epc5_args,
5692     1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
5693   { 1, Iclass_xt_iclass_wsr_epc5_args,
5694     1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
5695   { 1, Iclass_xt_iclass_xsr_epc5_args,
5696     1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
5697   { 1, Iclass_xt_iclass_rsr_excsave5_args,
5698     1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
5699   { 1, Iclass_xt_iclass_wsr_excsave5_args,
5700     1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
5701   { 1, Iclass_xt_iclass_xsr_excsave5_args,
5702     1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
5703   { 1, Iclass_xt_iclass_rsr_epc6_args,
5704     1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
5705   { 1, Iclass_xt_iclass_wsr_epc6_args,
5706     1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
5707   { 1, Iclass_xt_iclass_xsr_epc6_args,
5708     1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
5709   { 1, Iclass_xt_iclass_rsr_excsave6_args,
5710     1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
5711   { 1, Iclass_xt_iclass_wsr_excsave6_args,
5712     1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
5713   { 1, Iclass_xt_iclass_xsr_excsave6_args,
5714     1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
5715   { 1, Iclass_xt_iclass_rsr_epc7_args,
5716     1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
5717   { 1, Iclass_xt_iclass_wsr_epc7_args,
5718     1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
5719   { 1, Iclass_xt_iclass_xsr_epc7_args,
5720     1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
5721   { 1, Iclass_xt_iclass_rsr_excsave7_args,
5722     1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
5723   { 1, Iclass_xt_iclass_wsr_excsave7_args,
5724     1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
5725   { 1, Iclass_xt_iclass_xsr_excsave7_args,
5726     1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
5727   { 1, Iclass_xt_iclass_rsr_eps2_args,
5728     1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
5729   { 1, Iclass_xt_iclass_wsr_eps2_args,
5730     1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
5731   { 1, Iclass_xt_iclass_xsr_eps2_args,
5732     1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
5733   { 1, Iclass_xt_iclass_rsr_eps3_args,
5734     1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
5735   { 1, Iclass_xt_iclass_wsr_eps3_args,
5736     1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
5737   { 1, Iclass_xt_iclass_xsr_eps3_args,
5738     1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
5739   { 1, Iclass_xt_iclass_rsr_eps4_args,
5740     1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
5741   { 1, Iclass_xt_iclass_wsr_eps4_args,
5742     1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
5743   { 1, Iclass_xt_iclass_xsr_eps4_args,
5744     1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
5745   { 1, Iclass_xt_iclass_rsr_eps5_args,
5746     1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
5747   { 1, Iclass_xt_iclass_wsr_eps5_args,
5748     1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
5749   { 1, Iclass_xt_iclass_xsr_eps5_args,
5750     1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
5751   { 1, Iclass_xt_iclass_rsr_eps6_args,
5752     1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
5753   { 1, Iclass_xt_iclass_wsr_eps6_args,
5754     1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
5755   { 1, Iclass_xt_iclass_xsr_eps6_args,
5756     1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
5757   { 1, Iclass_xt_iclass_rsr_eps7_args,
5758     1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
5759   { 1, Iclass_xt_iclass_wsr_eps7_args,
5760     1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
5761   { 1, Iclass_xt_iclass_xsr_eps7_args,
5762     1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
5763   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
5764     1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
5765   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
5766     1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
5767   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
5768     1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
5769   { 1, Iclass_xt_iclass_rsr_depc_args,
5770     1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
5771   { 1, Iclass_xt_iclass_wsr_depc_args,
5772     1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
5773   { 1, Iclass_xt_iclass_xsr_depc_args,
5774     1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
5775   { 1, Iclass_xt_iclass_rsr_exccause_args,
5776     2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
5777   { 1, Iclass_xt_iclass_wsr_exccause_args,
5778     1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
5779   { 1, Iclass_xt_iclass_xsr_exccause_args,
5780     1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
5781   { 1, Iclass_xt_iclass_rsr_misc0_args,
5782     1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
5783   { 1, Iclass_xt_iclass_wsr_misc0_args,
5784     1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
5785   { 1, Iclass_xt_iclass_xsr_misc0_args,
5786     1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
5787   { 1, Iclass_xt_iclass_rsr_misc1_args,
5788     1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
5789   { 1, Iclass_xt_iclass_wsr_misc1_args,
5790     1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
5791   { 1, Iclass_xt_iclass_xsr_misc1_args,
5792     1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
5793   { 1, Iclass_xt_iclass_rsr_prid_args,
5794     0, 0, 0, 0 },
5795   { 1, Iclass_xt_iclass_rsr_vecbase_args,
5796     1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
5797   { 1, Iclass_xt_iclass_wsr_vecbase_args,
5798     1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
5799   { 1, Iclass_xt_iclass_xsr_vecbase_args,
5800     1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
5801   { 3, Iclass_xt_mul16_args,
5802     0, 0, 0, 0 },
5803   { 3, Iclass_xt_mul32_args,
5804     0, 0, 0, 0 },
5805   { 2, Iclass_xt_iclass_mac16_aa_args,
5806     1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
5807   { 2, Iclass_xt_iclass_mac16_ad_args,
5808     1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
5809   { 2, Iclass_xt_iclass_mac16_da_args,
5810     1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
5811   { 2, Iclass_xt_iclass_mac16_dd_args,
5812     1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
5813   { 2, Iclass_xt_iclass_mac16a_aa_args,
5814     1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
5815   { 2, Iclass_xt_iclass_mac16a_ad_args,
5816     1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
5817   { 2, Iclass_xt_iclass_mac16a_da_args,
5818     1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
5819   { 2, Iclass_xt_iclass_mac16a_dd_args,
5820     1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
5821   { 4, Iclass_xt_iclass_mac16al_da_args,
5822     1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
5823   { 4, Iclass_xt_iclass_mac16al_dd_args,
5824     1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
5825   { 2, Iclass_xt_iclass_mac16_l_args,
5826     0, 0, 0, 0 },
5827   { 2, Iclass_xt_iclass_rsr_m0_args,
5828     0, 0, 0, 0 },
5829   { 2, Iclass_xt_iclass_wsr_m0_args,
5830     0, 0, 0, 0 },
5831   { 2, Iclass_xt_iclass_xsr_m0_args,
5832     0, 0, 0, 0 },
5833   { 2, Iclass_xt_iclass_rsr_m1_args,
5834     0, 0, 0, 0 },
5835   { 2, Iclass_xt_iclass_wsr_m1_args,
5836     0, 0, 0, 0 },
5837   { 2, Iclass_xt_iclass_xsr_m1_args,
5838     0, 0, 0, 0 },
5839   { 2, Iclass_xt_iclass_rsr_m2_args,
5840     0, 0, 0, 0 },
5841   { 2, Iclass_xt_iclass_wsr_m2_args,
5842     0, 0, 0, 0 },
5843   { 2, Iclass_xt_iclass_xsr_m2_args,
5844     0, 0, 0, 0 },
5845   { 2, Iclass_xt_iclass_rsr_m3_args,
5846     0, 0, 0, 0 },
5847   { 2, Iclass_xt_iclass_wsr_m3_args,
5848     0, 0, 0, 0 },
5849   { 2, Iclass_xt_iclass_xsr_m3_args,
5850     0, 0, 0, 0 },
5851   { 1, Iclass_xt_iclass_rsr_acclo_args,
5852     1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
5853   { 1, Iclass_xt_iclass_wsr_acclo_args,
5854     1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
5855   { 1, Iclass_xt_iclass_xsr_acclo_args,
5856     1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
5857   { 1, Iclass_xt_iclass_rsr_acchi_args,
5858     1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
5859   { 1, Iclass_xt_iclass_wsr_acchi_args,
5860     1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
5861   { 1, Iclass_xt_iclass_xsr_acchi_args,
5862     1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
5863   { 1, Iclass_xt_iclass_rfi_args,
5864     20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
5865   { 1, Iclass_xt_iclass_wait_args,
5866     1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
5867   { 1, Iclass_xt_iclass_rsr_interrupt_args,
5868     1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
5869   { 1, Iclass_xt_iclass_wsr_intset_args,
5870     2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
5871   { 1, Iclass_xt_iclass_wsr_intclear_args,
5872     2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
5873   { 1, Iclass_xt_iclass_rsr_intenable_args,
5874     1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
5875   { 1, Iclass_xt_iclass_wsr_intenable_args,
5876     1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
5877   { 1, Iclass_xt_iclass_xsr_intenable_args,
5878     1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
5879   { 2, Iclass_xt_iclass_break_args,
5880     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
5881   { 1, Iclass_xt_iclass_break_n_args,
5882     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
5883   { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
5884     1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
5885   { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
5886     2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
5887   { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
5888     2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
5889   { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
5890     1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
5891   { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
5892     2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
5893   { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
5894     2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
5895   { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
5896     1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
5897   { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
5898     2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
5899   { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
5900     2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
5901   { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
5902     1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
5903   { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
5904     2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
5905   { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
5906     2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
5907   { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
5908     1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
5909   { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
5910     1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
5911   { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
5912     1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
5913   { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
5914     1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
5915   { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
5916     1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
5917   { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
5918     1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
5919   { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
5920     1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
5921   { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
5922     1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
5923   { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
5924     1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
5925   { 1, Iclass_xt_iclass_rsr_debugcause_args,
5926     2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
5927   { 1, Iclass_xt_iclass_wsr_debugcause_args,
5928     2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
5929   { 1, Iclass_xt_iclass_xsr_debugcause_args,
5930     2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
5931   { 1, Iclass_xt_iclass_rsr_icount_args,
5932     1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
5933   { 1, Iclass_xt_iclass_wsr_icount_args,
5934     2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
5935   { 1, Iclass_xt_iclass_xsr_icount_args,
5936     2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
5937   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
5938     1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
5939   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
5940     1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
5941   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
5942     1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
5943   { 1, Iclass_xt_iclass_rsr_ddr_args,
5944     1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
5945   { 1, Iclass_xt_iclass_wsr_ddr_args,
5946     2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
5947   { 1, Iclass_xt_iclass_xsr_ddr_args,
5948     2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
5949   { 1, Iclass_xt_iclass_lddr32_p_args,
5950     3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
5951   { 1, Iclass_xt_iclass_sddr32_p_args,
5952     2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
5953   { 1, Iclass_xt_iclass_rfdo_args,
5954     9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
5955   { 0, 0 /* xt_iclass_rfdd */,
5956     1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
5957   { 1, Iclass_xt_iclass_wsr_mmid_args,
5958     1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
5959   { 1, Iclass_xt_iclass_rsr_ccount_args,
5960     1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
5961   { 1, Iclass_xt_iclass_wsr_ccount_args,
5962     2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
5963   { 1, Iclass_xt_iclass_xsr_ccount_args,
5964     2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
5965   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
5966     1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
5967   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
5968     2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
5969   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
5970     2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
5971   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
5972     1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
5973   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
5974     2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
5975   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
5976     2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
5977   { 1, Iclass_xt_iclass_rsr_ccompare2_args,
5978     1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
5979   { 1, Iclass_xt_iclass_wsr_ccompare2_args,
5980     2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
5981   { 1, Iclass_xt_iclass_xsr_ccompare2_args,
5982     2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
5983   { 2, Iclass_xt_iclass_icache_args,
5984     0, 0, 0, 0 },
5985   { 2, Iclass_xt_iclass_icache_lock_args,
5986     0, 0, 0, 0 },
5987   { 2, Iclass_xt_iclass_icache_inv_args,
5988     0, 0, 0, 0 },
5989   { 2, Iclass_xt_iclass_licx_args,
5990     0, 0, 0, 0 },
5991   { 2, Iclass_xt_iclass_sicx_args,
5992     0, 0, 0, 0 },
5993   { 2, Iclass_xt_iclass_dcache_args,
5994     0, 0, 0, 0 },
5995   { 1, Iclass_xt_iclass_dcache_dyn_args,
5996     0, 0, 0, 0 },
5997   { 2, Iclass_xt_iclass_dcache_ind_args,
5998     0, 0, 0, 0 },
5999   { 2, Iclass_xt_iclass_dcache_inv_args,
6000     0, 0, 0, 0 },
6001   { 2, Iclass_xt_iclass_dpf_args,
6002     0, 0, 0, 0 },
6003   { 2, Iclass_xt_iclass_dcache_lock_args,
6004     0, 0, 0, 0 },
6005   { 2, Iclass_xt_iclass_sdct_args,
6006     0, 0, 0, 0 },
6007   { 2, Iclass_xt_iclass_ldct_args,
6008     0, 0, 0, 0 },
6009   { 1, Iclass_xt_iclass_idtlb_args,
6010     1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
6011   { 2, Iclass_xt_iclass_rdtlb_args,
6012     0, 0, 0, 0 },
6013   { 2, Iclass_xt_iclass_wdtlb_args,
6014     1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
6015   { 1, Iclass_xt_iclass_iitlb_args,
6016     0, 0, 0, 0 },
6017   { 2, Iclass_xt_iclass_ritlb_args,
6018     0, 0, 0, 0 },
6019   { 2, Iclass_xt_iclass_witlb_args,
6020     0, 0, 0, 0 },
6021   { 3, Iclass_xt_iclass_clamp_args,
6022     0, 0, 0, 0 },
6023   { 3, Iclass_xt_iclass_minmax_args,
6024     0, 0, 0, 0 },
6025   { 2, Iclass_xt_iclass_nsa_args,
6026     0, 0, 0, 0 },
6027   { 3, Iclass_xt_iclass_sx_args,
6028     0, 0, 0, 0 },
6029   { 3, Iclass_xt_iclass_l32ai_args,
6030     0, 0, 0, 0 },
6031   { 3, Iclass_xt_iclass_s32ri_args,
6032     0, 0, 0, 0 },
6033   { 3, Iclass_xt_iclass_s32c1i_args,
6034     3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
6035   { 1, Iclass_xt_iclass_rsr_scompare1_args,
6036     1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
6037   { 1, Iclass_xt_iclass_wsr_scompare1_args,
6038     1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
6039   { 1, Iclass_xt_iclass_xsr_scompare1_args,
6040     1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
6041   { 1, Iclass_xt_iclass_rsr_atomctl_args,
6042     1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
6043   { 1, Iclass_xt_iclass_wsr_atomctl_args,
6044     2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
6045   { 1, Iclass_xt_iclass_xsr_atomctl_args,
6046     2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
6047   { 3, Iclass_xt_iclass_div_args,
6048     0, 0, 0, 0 },
6049   { 2, Iclass_xt_iclass_rer_args,
6050     1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
6051   { 2, Iclass_xt_iclass_wer_args,
6052     1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
6053   { 1, Iclass_rur_expstate_args,
6054     1, Iclass_rur_expstate_stateArgs, 0, 0 },
6055   { 1, Iclass_wur_expstate_args,
6056     1, Iclass_wur_expstate_stateArgs, 0, 0 },
6057   { 1, Iclass_iclass_READ_IMPWIRE_args,
6058     0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
6059   { 1, Iclass_iclass_SETB_EXPSTATE_args,
6060     1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
6061   { 1, Iclass_iclass_CLRB_EXPSTATE_args,
6062     1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
6063   { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
6064     1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
6065 };
6066
6067 enum xtensa_iclass_id {
6068   ICLASS_xt_iclass_excw,
6069   ICLASS_xt_iclass_rfe,
6070   ICLASS_xt_iclass_rfde,
6071   ICLASS_xt_iclass_syscall,
6072   ICLASS_xt_iclass_call12,
6073   ICLASS_xt_iclass_call8,
6074   ICLASS_xt_iclass_call4,
6075   ICLASS_xt_iclass_callx12,
6076   ICLASS_xt_iclass_callx8,
6077   ICLASS_xt_iclass_callx4,
6078   ICLASS_xt_iclass_entry,
6079   ICLASS_xt_iclass_movsp,
6080   ICLASS_xt_iclass_rotw,
6081   ICLASS_xt_iclass_retw,
6082   ICLASS_xt_iclass_rfwou,
6083   ICLASS_xt_iclass_l32e,
6084   ICLASS_xt_iclass_s32e,
6085   ICLASS_xt_iclass_rsr_windowbase,
6086   ICLASS_xt_iclass_wsr_windowbase,
6087   ICLASS_xt_iclass_xsr_windowbase,
6088   ICLASS_xt_iclass_rsr_windowstart,
6089   ICLASS_xt_iclass_wsr_windowstart,
6090   ICLASS_xt_iclass_xsr_windowstart,
6091   ICLASS_xt_iclass_add_n,
6092   ICLASS_xt_iclass_addi_n,
6093   ICLASS_xt_iclass_bz6,
6094   ICLASS_xt_iclass_ill_n,
6095   ICLASS_xt_iclass_loadi4,
6096   ICLASS_xt_iclass_mov_n,
6097   ICLASS_xt_iclass_movi_n,
6098   ICLASS_xt_iclass_nopn,
6099   ICLASS_xt_iclass_retn,
6100   ICLASS_xt_iclass_storei4,
6101   ICLASS_xt_iclass_addi,
6102   ICLASS_xt_iclass_addmi,
6103   ICLASS_xt_iclass_addsub,
6104   ICLASS_xt_iclass_bit,
6105   ICLASS_xt_iclass_bsi8,
6106   ICLASS_xt_iclass_bsi8b,
6107   ICLASS_xt_iclass_bsi8u,
6108   ICLASS_xt_iclass_bst8,
6109   ICLASS_xt_iclass_bsz12,
6110   ICLASS_xt_iclass_call0,
6111   ICLASS_xt_iclass_callx0,
6112   ICLASS_xt_iclass_exti,
6113   ICLASS_xt_iclass_ill,
6114   ICLASS_xt_iclass_jump,
6115   ICLASS_xt_iclass_jumpx,
6116   ICLASS_xt_iclass_l16ui,
6117   ICLASS_xt_iclass_l16si,
6118   ICLASS_xt_iclass_l32i,
6119   ICLASS_xt_iclass_l32r,
6120   ICLASS_xt_iclass_l8i,
6121   ICLASS_xt_iclass_loop,
6122   ICLASS_xt_iclass_loopz,
6123   ICLASS_xt_iclass_movi,
6124   ICLASS_xt_iclass_movz,
6125   ICLASS_xt_iclass_neg,
6126   ICLASS_xt_iclass_nop,
6127   ICLASS_xt_iclass_return,
6128   ICLASS_xt_iclass_simcall,
6129   ICLASS_xt_iclass_s16i,
6130   ICLASS_xt_iclass_s32i,
6131   ICLASS_xt_iclass_s32nb,
6132   ICLASS_xt_iclass_s8i,
6133   ICLASS_xt_iclass_sar,
6134   ICLASS_xt_iclass_sari,
6135   ICLASS_xt_iclass_shifts,
6136   ICLASS_xt_iclass_shiftst,
6137   ICLASS_xt_iclass_shiftt,
6138   ICLASS_xt_iclass_slli,
6139   ICLASS_xt_iclass_srai,
6140   ICLASS_xt_iclass_srli,
6141   ICLASS_xt_iclass_memw,
6142   ICLASS_xt_iclass_extw,
6143   ICLASS_xt_iclass_isync,
6144   ICLASS_xt_iclass_sync,
6145   ICLASS_xt_iclass_rsil,
6146   ICLASS_xt_iclass_rsr_lend,
6147   ICLASS_xt_iclass_wsr_lend,
6148   ICLASS_xt_iclass_xsr_lend,
6149   ICLASS_xt_iclass_rsr_lcount,
6150   ICLASS_xt_iclass_wsr_lcount,
6151   ICLASS_xt_iclass_xsr_lcount,
6152   ICLASS_xt_iclass_rsr_lbeg,
6153   ICLASS_xt_iclass_wsr_lbeg,
6154   ICLASS_xt_iclass_xsr_lbeg,
6155   ICLASS_xt_iclass_rsr_sar,
6156   ICLASS_xt_iclass_wsr_sar,
6157   ICLASS_xt_iclass_xsr_sar,
6158   ICLASS_xt_iclass_rsr_memctl,
6159   ICLASS_xt_iclass_wsr_memctl,
6160   ICLASS_xt_iclass_xsr_memctl,
6161   ICLASS_xt_iclass_rsr_litbase,
6162   ICLASS_xt_iclass_wsr_litbase,
6163   ICLASS_xt_iclass_xsr_litbase,
6164   ICLASS_xt_iclass_rsr_configid0,
6165   ICLASS_xt_iclass_wsr_configid0,
6166   ICLASS_xt_iclass_rsr_configid1,
6167   ICLASS_xt_iclass_rsr_ps,
6168   ICLASS_xt_iclass_wsr_ps,
6169   ICLASS_xt_iclass_xsr_ps,
6170   ICLASS_xt_iclass_rsr_epc1,
6171   ICLASS_xt_iclass_wsr_epc1,
6172   ICLASS_xt_iclass_xsr_epc1,
6173   ICLASS_xt_iclass_rsr_excsave1,
6174   ICLASS_xt_iclass_wsr_excsave1,
6175   ICLASS_xt_iclass_xsr_excsave1,
6176   ICLASS_xt_iclass_rsr_epc2,
6177   ICLASS_xt_iclass_wsr_epc2,
6178   ICLASS_xt_iclass_xsr_epc2,
6179   ICLASS_xt_iclass_rsr_excsave2,
6180   ICLASS_xt_iclass_wsr_excsave2,
6181   ICLASS_xt_iclass_xsr_excsave2,
6182   ICLASS_xt_iclass_rsr_epc3,
6183   ICLASS_xt_iclass_wsr_epc3,
6184   ICLASS_xt_iclass_xsr_epc3,
6185   ICLASS_xt_iclass_rsr_excsave3,
6186   ICLASS_xt_iclass_wsr_excsave3,
6187   ICLASS_xt_iclass_xsr_excsave3,
6188   ICLASS_xt_iclass_rsr_epc4,
6189   ICLASS_xt_iclass_wsr_epc4,
6190   ICLASS_xt_iclass_xsr_epc4,
6191   ICLASS_xt_iclass_rsr_excsave4,
6192   ICLASS_xt_iclass_wsr_excsave4,
6193   ICLASS_xt_iclass_xsr_excsave4,
6194   ICLASS_xt_iclass_rsr_epc5,
6195   ICLASS_xt_iclass_wsr_epc5,
6196   ICLASS_xt_iclass_xsr_epc5,
6197   ICLASS_xt_iclass_rsr_excsave5,
6198   ICLASS_xt_iclass_wsr_excsave5,
6199   ICLASS_xt_iclass_xsr_excsave5,
6200   ICLASS_xt_iclass_rsr_epc6,
6201   ICLASS_xt_iclass_wsr_epc6,
6202   ICLASS_xt_iclass_xsr_epc6,
6203   ICLASS_xt_iclass_rsr_excsave6,
6204   ICLASS_xt_iclass_wsr_excsave6,
6205   ICLASS_xt_iclass_xsr_excsave6,
6206   ICLASS_xt_iclass_rsr_epc7,
6207   ICLASS_xt_iclass_wsr_epc7,
6208   ICLASS_xt_iclass_xsr_epc7,
6209   ICLASS_xt_iclass_rsr_excsave7,
6210   ICLASS_xt_iclass_wsr_excsave7,
6211   ICLASS_xt_iclass_xsr_excsave7,
6212   ICLASS_xt_iclass_rsr_eps2,
6213   ICLASS_xt_iclass_wsr_eps2,
6214   ICLASS_xt_iclass_xsr_eps2,
6215   ICLASS_xt_iclass_rsr_eps3,
6216   ICLASS_xt_iclass_wsr_eps3,
6217   ICLASS_xt_iclass_xsr_eps3,
6218   ICLASS_xt_iclass_rsr_eps4,
6219   ICLASS_xt_iclass_wsr_eps4,
6220   ICLASS_xt_iclass_xsr_eps4,
6221   ICLASS_xt_iclass_rsr_eps5,
6222   ICLASS_xt_iclass_wsr_eps5,
6223   ICLASS_xt_iclass_xsr_eps5,
6224   ICLASS_xt_iclass_rsr_eps6,
6225   ICLASS_xt_iclass_wsr_eps6,
6226   ICLASS_xt_iclass_xsr_eps6,
6227   ICLASS_xt_iclass_rsr_eps7,
6228   ICLASS_xt_iclass_wsr_eps7,
6229   ICLASS_xt_iclass_xsr_eps7,
6230   ICLASS_xt_iclass_rsr_excvaddr,
6231   ICLASS_xt_iclass_wsr_excvaddr,
6232   ICLASS_xt_iclass_xsr_excvaddr,
6233   ICLASS_xt_iclass_rsr_depc,
6234   ICLASS_xt_iclass_wsr_depc,
6235   ICLASS_xt_iclass_xsr_depc,
6236   ICLASS_xt_iclass_rsr_exccause,
6237   ICLASS_xt_iclass_wsr_exccause,
6238   ICLASS_xt_iclass_xsr_exccause,
6239   ICLASS_xt_iclass_rsr_misc0,
6240   ICLASS_xt_iclass_wsr_misc0,
6241   ICLASS_xt_iclass_xsr_misc0,
6242   ICLASS_xt_iclass_rsr_misc1,
6243   ICLASS_xt_iclass_wsr_misc1,
6244   ICLASS_xt_iclass_xsr_misc1,
6245   ICLASS_xt_iclass_rsr_prid,
6246   ICLASS_xt_iclass_rsr_vecbase,
6247   ICLASS_xt_iclass_wsr_vecbase,
6248   ICLASS_xt_iclass_xsr_vecbase,
6249   ICLASS_xt_mul16,
6250   ICLASS_xt_mul32,
6251   ICLASS_xt_iclass_mac16_aa,
6252   ICLASS_xt_iclass_mac16_ad,
6253   ICLASS_xt_iclass_mac16_da,
6254   ICLASS_xt_iclass_mac16_dd,
6255   ICLASS_xt_iclass_mac16a_aa,
6256   ICLASS_xt_iclass_mac16a_ad,
6257   ICLASS_xt_iclass_mac16a_da,
6258   ICLASS_xt_iclass_mac16a_dd,
6259   ICLASS_xt_iclass_mac16al_da,
6260   ICLASS_xt_iclass_mac16al_dd,
6261   ICLASS_xt_iclass_mac16_l,
6262   ICLASS_xt_iclass_rsr_m0,
6263   ICLASS_xt_iclass_wsr_m0,
6264   ICLASS_xt_iclass_xsr_m0,
6265   ICLASS_xt_iclass_rsr_m1,
6266   ICLASS_xt_iclass_wsr_m1,
6267   ICLASS_xt_iclass_xsr_m1,
6268   ICLASS_xt_iclass_rsr_m2,
6269   ICLASS_xt_iclass_wsr_m2,
6270   ICLASS_xt_iclass_xsr_m2,
6271   ICLASS_xt_iclass_rsr_m3,
6272   ICLASS_xt_iclass_wsr_m3,
6273   ICLASS_xt_iclass_xsr_m3,
6274   ICLASS_xt_iclass_rsr_acclo,
6275   ICLASS_xt_iclass_wsr_acclo,
6276   ICLASS_xt_iclass_xsr_acclo,
6277   ICLASS_xt_iclass_rsr_acchi,
6278   ICLASS_xt_iclass_wsr_acchi,
6279   ICLASS_xt_iclass_xsr_acchi,
6280   ICLASS_xt_iclass_rfi,
6281   ICLASS_xt_iclass_wait,
6282   ICLASS_xt_iclass_rsr_interrupt,
6283   ICLASS_xt_iclass_wsr_intset,
6284   ICLASS_xt_iclass_wsr_intclear,
6285   ICLASS_xt_iclass_rsr_intenable,
6286   ICLASS_xt_iclass_wsr_intenable,
6287   ICLASS_xt_iclass_xsr_intenable,
6288   ICLASS_xt_iclass_break,
6289   ICLASS_xt_iclass_break_n,
6290   ICLASS_xt_iclass_rsr_dbreaka0,
6291   ICLASS_xt_iclass_wsr_dbreaka0,
6292   ICLASS_xt_iclass_xsr_dbreaka0,
6293   ICLASS_xt_iclass_rsr_dbreakc0,
6294   ICLASS_xt_iclass_wsr_dbreakc0,
6295   ICLASS_xt_iclass_xsr_dbreakc0,
6296   ICLASS_xt_iclass_rsr_dbreaka1,
6297   ICLASS_xt_iclass_wsr_dbreaka1,
6298   ICLASS_xt_iclass_xsr_dbreaka1,
6299   ICLASS_xt_iclass_rsr_dbreakc1,
6300   ICLASS_xt_iclass_wsr_dbreakc1,
6301   ICLASS_xt_iclass_xsr_dbreakc1,
6302   ICLASS_xt_iclass_rsr_ibreaka0,
6303   ICLASS_xt_iclass_wsr_ibreaka0,
6304   ICLASS_xt_iclass_xsr_ibreaka0,
6305   ICLASS_xt_iclass_rsr_ibreaka1,
6306   ICLASS_xt_iclass_wsr_ibreaka1,
6307   ICLASS_xt_iclass_xsr_ibreaka1,
6308   ICLASS_xt_iclass_rsr_ibreakenable,
6309   ICLASS_xt_iclass_wsr_ibreakenable,
6310   ICLASS_xt_iclass_xsr_ibreakenable,
6311   ICLASS_xt_iclass_rsr_debugcause,
6312   ICLASS_xt_iclass_wsr_debugcause,
6313   ICLASS_xt_iclass_xsr_debugcause,
6314   ICLASS_xt_iclass_rsr_icount,
6315   ICLASS_xt_iclass_wsr_icount,
6316   ICLASS_xt_iclass_xsr_icount,
6317   ICLASS_xt_iclass_rsr_icountlevel,
6318   ICLASS_xt_iclass_wsr_icountlevel,
6319   ICLASS_xt_iclass_xsr_icountlevel,
6320   ICLASS_xt_iclass_rsr_ddr,
6321   ICLASS_xt_iclass_wsr_ddr,
6322   ICLASS_xt_iclass_xsr_ddr,
6323   ICLASS_xt_iclass_lddr32_p,
6324   ICLASS_xt_iclass_sddr32_p,
6325   ICLASS_xt_iclass_rfdo,
6326   ICLASS_xt_iclass_rfdd,
6327   ICLASS_xt_iclass_wsr_mmid,
6328   ICLASS_xt_iclass_rsr_ccount,
6329   ICLASS_xt_iclass_wsr_ccount,
6330   ICLASS_xt_iclass_xsr_ccount,
6331   ICLASS_xt_iclass_rsr_ccompare0,
6332   ICLASS_xt_iclass_wsr_ccompare0,
6333   ICLASS_xt_iclass_xsr_ccompare0,
6334   ICLASS_xt_iclass_rsr_ccompare1,
6335   ICLASS_xt_iclass_wsr_ccompare1,
6336   ICLASS_xt_iclass_xsr_ccompare1,
6337   ICLASS_xt_iclass_rsr_ccompare2,
6338   ICLASS_xt_iclass_wsr_ccompare2,
6339   ICLASS_xt_iclass_xsr_ccompare2,
6340   ICLASS_xt_iclass_icache,
6341   ICLASS_xt_iclass_icache_lock,
6342   ICLASS_xt_iclass_icache_inv,
6343   ICLASS_xt_iclass_licx,
6344   ICLASS_xt_iclass_sicx,
6345   ICLASS_xt_iclass_dcache,
6346   ICLASS_xt_iclass_dcache_dyn,
6347   ICLASS_xt_iclass_dcache_ind,
6348   ICLASS_xt_iclass_dcache_inv,
6349   ICLASS_xt_iclass_dpf,
6350   ICLASS_xt_iclass_dcache_lock,
6351   ICLASS_xt_iclass_sdct,
6352   ICLASS_xt_iclass_ldct,
6353   ICLASS_xt_iclass_idtlb,
6354   ICLASS_xt_iclass_rdtlb,
6355   ICLASS_xt_iclass_wdtlb,
6356   ICLASS_xt_iclass_iitlb,
6357   ICLASS_xt_iclass_ritlb,
6358   ICLASS_xt_iclass_witlb,
6359   ICLASS_xt_iclass_clamp,
6360   ICLASS_xt_iclass_minmax,
6361   ICLASS_xt_iclass_nsa,
6362   ICLASS_xt_iclass_sx,
6363   ICLASS_xt_iclass_l32ai,
6364   ICLASS_xt_iclass_s32ri,
6365   ICLASS_xt_iclass_s32c1i,
6366   ICLASS_xt_iclass_rsr_scompare1,
6367   ICLASS_xt_iclass_wsr_scompare1,
6368   ICLASS_xt_iclass_xsr_scompare1,
6369   ICLASS_xt_iclass_rsr_atomctl,
6370   ICLASS_xt_iclass_wsr_atomctl,
6371   ICLASS_xt_iclass_xsr_atomctl,
6372   ICLASS_xt_iclass_div,
6373   ICLASS_xt_iclass_rer,
6374   ICLASS_xt_iclass_wer,
6375   ICLASS_rur_expstate,
6376   ICLASS_wur_expstate,
6377   ICLASS_iclass_READ_IMPWIRE,
6378   ICLASS_iclass_SETB_EXPSTATE,
6379   ICLASS_iclass_CLRB_EXPSTATE,
6380   ICLASS_iclass_WRMSK_EXPSTATE
6381 };
6382
6383 \f
6384 /*  Opcode encodings.  */
6385
6386 static void
6387 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6388 {
6389   slotbuf[0] = 0x2080;
6390 }
6391
6392 static void
6393 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
6394 {
6395   slotbuf[0] = 0x3000;
6396 }
6397
6398 static void
6399 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
6400 {
6401   slotbuf[0] = 0x3200;
6402 }
6403
6404 static void
6405 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6406 {
6407   slotbuf[0] = 0x5000;
6408 }
6409
6410 static void
6411 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
6412 {
6413   slotbuf[0] = 0x35;
6414 }
6415
6416 static void
6417 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6418 {
6419   slotbuf[0] = 0x25;
6420 }
6421
6422 static void
6423 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6424 {
6425   slotbuf[0] = 0x15;
6426 }
6427
6428 static void
6429 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
6430 {
6431   slotbuf[0] = 0xf0;
6432 }
6433
6434 static void
6435 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6436 {
6437   slotbuf[0] = 0xe0;
6438 }
6439
6440 static void
6441 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6442 {
6443   slotbuf[0] = 0xd0;
6444 }
6445
6446 static void
6447 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
6448 {
6449   slotbuf[0] = 0x36;
6450 }
6451
6452 static void
6453 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
6454 {
6455   slotbuf[0] = 0x1000;
6456 }
6457
6458 static void
6459 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6460 {
6461   slotbuf[0] = 0x408000;
6462 }
6463
6464 static void
6465 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
6466 {
6467   slotbuf[0] = 0x90;
6468 }
6469
6470 static void
6471 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6472 {
6473   slotbuf[0] = 0xf01d;
6474 }
6475
6476 static void
6477 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
6478 {
6479   slotbuf[0] = 0x3400;
6480 }
6481
6482 static void
6483 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6484 {
6485   slotbuf[0] = 0x3500;
6486 }
6487
6488 static void
6489 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
6490 {
6491   slotbuf[0] = 0x90000;
6492 }
6493
6494 static void
6495 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
6496 {
6497   slotbuf[0] = 0x490000;
6498 }
6499
6500 static void
6501 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6502 {
6503   slotbuf[0] = 0x34800;
6504 }
6505
6506 static void
6507 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6508 {
6509   slotbuf[0] = 0x134800;
6510 }
6511
6512 static void
6513 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
6514 {
6515   slotbuf[0] = 0x614800;
6516 }
6517
6518 static void
6519 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6520 {
6521   slotbuf[0] = 0x34900;
6522 }
6523
6524 static void
6525 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6526 {
6527   slotbuf[0] = 0x134900;
6528 }
6529
6530 static void
6531 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
6532 {
6533   slotbuf[0] = 0x614900;
6534 }
6535
6536 static void
6537 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6538 {
6539   slotbuf[0] = 0xa;
6540 }
6541
6542 static void
6543 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6544 {
6545   slotbuf[0] = 0xb;
6546 }
6547
6548 static void
6549 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6550 {
6551   slotbuf[0] = 0x8c;
6552 }
6553
6554 static void
6555 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6556 {
6557   slotbuf[0] = 0xcc;
6558 }
6559
6560 static void
6561 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6562 {
6563   slotbuf[0] = 0xf06d;
6564 }
6565
6566 static void
6567 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6568 {
6569   slotbuf[0] = 0x8;
6570 }
6571
6572 static void
6573 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6574 {
6575   slotbuf[0] = 0xd;
6576 }
6577
6578 static void
6579 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6580 {
6581   slotbuf[0] = 0xc;
6582 }
6583
6584 static void
6585 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6586 {
6587   slotbuf[0] = 0xf03d;
6588 }
6589
6590 static void
6591 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
6592 {
6593   slotbuf[0] = 0xf00d;
6594 }
6595
6596 static void
6597 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
6598 {
6599   slotbuf[0] = 0x9;
6600 }
6601
6602 static void
6603 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6604 {
6605   slotbuf[0] = 0xc002;
6606 }
6607
6608 static void
6609 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6610 {
6611   slotbuf[0] = 0xd002;
6612 }
6613
6614 static void
6615 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
6616 {
6617   slotbuf[0] = 0x800000;
6618 }
6619
6620 static void
6621 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
6622 {
6623   slotbuf[0] = 0xc00000;
6624 }
6625
6626 static void
6627 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6628 {
6629   slotbuf[0] = 0x900000;
6630 }
6631
6632 static void
6633 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6634 {
6635   slotbuf[0] = 0xa00000;
6636 }
6637
6638 static void
6639 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6640 {
6641   slotbuf[0] = 0xb00000;
6642 }
6643
6644 static void
6645 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
6646 {
6647   slotbuf[0] = 0xd00000;
6648 }
6649
6650 static void
6651 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
6652 {
6653   slotbuf[0] = 0xe00000;
6654 }
6655
6656 static void
6657 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
6658 {
6659   slotbuf[0] = 0xf00000;
6660 }
6661
6662 static void
6663 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
6664 {
6665   slotbuf[0] = 0x100000;
6666 }
6667
6668 static void
6669 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
6670 {
6671   slotbuf[0] = 0x200000;
6672 }
6673
6674 static void
6675 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
6676 {
6677   slotbuf[0] = 0x300000;
6678 }
6679
6680 static void
6681 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6682 {
6683   slotbuf[0] = 0x26;
6684 }
6685
6686 static void
6687 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
6688 {
6689   slotbuf[0] = 0x66;
6690 }
6691
6692 static void
6693 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
6694 {
6695   slotbuf[0] = 0xe6;
6696 }
6697
6698 static void
6699 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
6700 {
6701   slotbuf[0] = 0xa6;
6702 }
6703
6704 static void
6705 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
6706 {
6707   slotbuf[0] = 0x6007;
6708 }
6709
6710 static void
6711 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6712 {
6713   slotbuf[0] = 0xe007;
6714 }
6715
6716 static void
6717 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6718 {
6719   slotbuf[0] = 0xf6;
6720 }
6721
6722 static void
6723 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6724 {
6725   slotbuf[0] = 0xb6;
6726 }
6727
6728 static void
6729 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
6730 {
6731   slotbuf[0] = 0x1007;
6732 }
6733
6734 static void
6735 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
6736 {
6737   slotbuf[0] = 0x9007;
6738 }
6739
6740 static void
6741 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
6742 {
6743   slotbuf[0] = 0xa007;
6744 }
6745
6746 static void
6747 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
6748 {
6749   slotbuf[0] = 0x2007;
6750 }
6751
6752 static void
6753 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6754 {
6755   slotbuf[0] = 0xb007;
6756 }
6757
6758 static void
6759 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
6760 {
6761   slotbuf[0] = 0x3007;
6762 }
6763
6764 static void
6765 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
6766 {
6767   slotbuf[0] = 0x8007;
6768 }
6769
6770 static void
6771 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
6772 {
6773   slotbuf[0] = 0x7;
6774 }
6775
6776 static void
6777 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
6778 {
6779   slotbuf[0] = 0x4007;
6780 }
6781
6782 static void
6783 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6784 {
6785   slotbuf[0] = 0xc007;
6786 }
6787
6788 static void
6789 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
6790 {
6791   slotbuf[0] = 0x5007;
6792 }
6793
6794 static void
6795 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
6796 {
6797   slotbuf[0] = 0xd007;
6798 }
6799
6800 static void
6801 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6802 {
6803   slotbuf[0] = 0x16;
6804 }
6805
6806 static void
6807 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6808 {
6809   slotbuf[0] = 0x56;
6810 }
6811
6812 static void
6813 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6814 {
6815   slotbuf[0] = 0xd6;
6816 }
6817
6818 static void
6819 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6820 {
6821   slotbuf[0] = 0x96;
6822 }
6823
6824 static void
6825 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6826 {
6827   slotbuf[0] = 0x5;
6828 }
6829
6830 static void
6831 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
6832 {
6833   slotbuf[0] = 0xc0;
6834 }
6835
6836 static void
6837 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6838 {
6839   slotbuf[0] = 0x40000;
6840 }
6841
6842 static void
6843 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
6844 {
6845   slotbuf[0] = 0;
6846 }
6847
6848 static void
6849 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
6850 {
6851   slotbuf[0] = 0x6;
6852 }
6853
6854 static void
6855 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
6856 {
6857   slotbuf[0] = 0xa0;
6858 }
6859
6860 static void
6861 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6862 {
6863   slotbuf[0] = 0x1002;
6864 }
6865
6866 static void
6867 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
6868 {
6869   slotbuf[0] = 0x9002;
6870 }
6871
6872 static void
6873 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6874 {
6875   slotbuf[0] = 0x2002;
6876 }
6877
6878 static void
6879 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
6880 {
6881   slotbuf[0] = 0x1;
6882 }
6883
6884 static void
6885 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
6886 {
6887   slotbuf[0] = 0x2;
6888 }
6889
6890 static void
6891 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6892 {
6893   slotbuf[0] = 0x8076;
6894 }
6895
6896 static void
6897 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6898 {
6899   slotbuf[0] = 0x9076;
6900 }
6901
6902 static void
6903 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6904 {
6905   slotbuf[0] = 0xa076;
6906 }
6907
6908 static void
6909 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
6910 {
6911   slotbuf[0] = 0xa002;
6912 }
6913
6914 static void
6915 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6916 {
6917   slotbuf[0] = 0x830000;
6918 }
6919
6920 static void
6921 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6922 {
6923   slotbuf[0] = 0x930000;
6924 }
6925
6926 static void
6927 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
6928 {
6929   slotbuf[0] = 0xa30000;
6930 }
6931
6932 static void
6933 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
6934 {
6935   slotbuf[0] = 0xb30000;
6936 }
6937
6938 static void
6939 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
6940 {
6941   slotbuf[0] = 0x600000;
6942 }
6943
6944 static void
6945 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
6946 {
6947   slotbuf[0] = 0x600100;
6948 }
6949
6950 static void
6951 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
6952 {
6953   slotbuf[0] = 0x20f0;
6954 }
6955
6956 static void
6957 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
6958 {
6959   slotbuf[0] = 0x80;
6960 }
6961
6962 static void
6963 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
6964 {
6965   slotbuf[0] = 0x5100;
6966 }
6967
6968 static void
6969 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6970 {
6971   slotbuf[0] = 0x5002;
6972 }
6973
6974 static void
6975 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6976 {
6977   slotbuf[0] = 0x6002;
6978 }
6979
6980 static void
6981 Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
6982 {
6983   slotbuf[0] = 0x590000;
6984 }
6985
6986 static void
6987 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
6988 {
6989   slotbuf[0] = 0x4002;
6990 }
6991
6992 static void
6993 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
6994 {
6995   slotbuf[0] = 0x400000;
6996 }
6997
6998 static void
6999 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7000 {
7001   slotbuf[0] = 0x401000;
7002 }
7003
7004 static void
7005 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
7006 {
7007   slotbuf[0] = 0x402000;
7008 }
7009
7010 static void
7011 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
7012 {
7013   slotbuf[0] = 0x403000;
7014 }
7015
7016 static void
7017 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
7018 {
7019   slotbuf[0] = 0x404000;
7020 }
7021
7022 static void
7023 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7024 {
7025   slotbuf[0] = 0xa10000;
7026 }
7027
7028 static void
7029 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
7030 {
7031   slotbuf[0] = 0x810000;
7032 }
7033
7034 static void
7035 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7036 {
7037   slotbuf[0] = 0x910000;
7038 }
7039
7040 static void
7041 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
7042 {
7043   slotbuf[0] = 0xb10000;
7044 }
7045
7046 static void
7047 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
7048 {
7049   slotbuf[0] = 0x10000;
7050 }
7051
7052 static void
7053 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
7054 {
7055   slotbuf[0] = 0x210000;
7056 }
7057
7058 static void
7059 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
7060 {
7061   slotbuf[0] = 0x410000;
7062 }
7063
7064 static void
7065 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
7066 {
7067   slotbuf[0] = 0x20c0;
7068 }
7069
7070 static void
7071 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
7072 {
7073   slotbuf[0] = 0x20d0;
7074 }
7075
7076 static void
7077 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7078 {
7079   slotbuf[0] = 0x2000;
7080 }
7081
7082 static void
7083 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7084 {
7085   slotbuf[0] = 0x2010;
7086 }
7087
7088 static void
7089 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7090 {
7091   slotbuf[0] = 0x2020;
7092 }
7093
7094 static void
7095 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
7096 {
7097   slotbuf[0] = 0x2030;
7098 }
7099
7100 static void
7101 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
7102 {
7103   slotbuf[0] = 0x6000;
7104 }
7105
7106 static void
7107 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
7108 {
7109   slotbuf[0] = 0x30100;
7110 }
7111
7112 static void
7113 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
7114 {
7115   slotbuf[0] = 0x130100;
7116 }
7117
7118 static void
7119 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
7120 {
7121   slotbuf[0] = 0x610100;
7122 }
7123
7124 static void
7125 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7126 {
7127   slotbuf[0] = 0x30200;
7128 }
7129
7130 static void
7131 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7132 {
7133   slotbuf[0] = 0x130200;
7134 }
7135
7136 static void
7137 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
7138 {
7139   slotbuf[0] = 0x610200;
7140 }
7141
7142 static void
7143 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7144 {
7145   slotbuf[0] = 0x30000;
7146 }
7147
7148 static void
7149 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7150 {
7151   slotbuf[0] = 0x130000;
7152 }
7153
7154 static void
7155 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
7156 {
7157   slotbuf[0] = 0x610000;
7158 }
7159
7160 static void
7161 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
7162 {
7163   slotbuf[0] = 0x30300;
7164 }
7165
7166 static void
7167 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
7168 {
7169   slotbuf[0] = 0x130300;
7170 }
7171
7172 static void
7173 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
7174 {
7175   slotbuf[0] = 0x610300;
7176 }
7177
7178 static void
7179 Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7180 {
7181   slotbuf[0] = 0x36100;
7182 }
7183
7184 static void
7185 Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7186 {
7187   slotbuf[0] = 0x136100;
7188 }
7189
7190 static void
7191 Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7192 {
7193   slotbuf[0] = 0x616100;
7194 }
7195
7196 static void
7197 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7198 {
7199   slotbuf[0] = 0x30500;
7200 }
7201
7202 static void
7203 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7204 {
7205   slotbuf[0] = 0x130500;
7206 }
7207
7208 static void
7209 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7210 {
7211   slotbuf[0] = 0x610500;
7212 }
7213
7214 static void
7215 Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7216 {
7217   slotbuf[0] = 0x3b000;
7218 }
7219
7220 static void
7221 Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7222 {
7223   slotbuf[0] = 0x13b000;
7224 }
7225
7226 static void
7227 Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7228 {
7229   slotbuf[0] = 0x3d000;
7230 }
7231
7232 static void
7233 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7234 {
7235   slotbuf[0] = 0x3e600;
7236 }
7237
7238 static void
7239 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7240 {
7241   slotbuf[0] = 0x13e600;
7242 }
7243
7244 static void
7245 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
7246 {
7247   slotbuf[0] = 0x61e600;
7248 }
7249
7250 static void
7251 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7252 {
7253   slotbuf[0] = 0x3b100;
7254 }
7255
7256 static void
7257 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7258 {
7259   slotbuf[0] = 0x13b100;
7260 }
7261
7262 static void
7263 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7264 {
7265   slotbuf[0] = 0x61b100;
7266 }
7267
7268 static void
7269 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7270 {
7271   slotbuf[0] = 0x3d100;
7272 }
7273
7274 static void
7275 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7276 {
7277   slotbuf[0] = 0x13d100;
7278 }
7279
7280 static void
7281 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7282 {
7283   slotbuf[0] = 0x61d100;
7284 }
7285
7286 static void
7287 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7288 {
7289   slotbuf[0] = 0x3b200;
7290 }
7291
7292 static void
7293 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7294 {
7295   slotbuf[0] = 0x13b200;
7296 }
7297
7298 static void
7299 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7300 {
7301   slotbuf[0] = 0x61b200;
7302 }
7303
7304 static void
7305 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7306 {
7307   slotbuf[0] = 0x3d200;
7308 }
7309
7310 static void
7311 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7312 {
7313   slotbuf[0] = 0x13d200;
7314 }
7315
7316 static void
7317 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7318 {
7319   slotbuf[0] = 0x61d200;
7320 }
7321
7322 static void
7323 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7324 {
7325   slotbuf[0] = 0x3b300;
7326 }
7327
7328 static void
7329 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7330 {
7331   slotbuf[0] = 0x13b300;
7332 }
7333
7334 static void
7335 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7336 {
7337   slotbuf[0] = 0x61b300;
7338 }
7339
7340 static void
7341 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7342 {
7343   slotbuf[0] = 0x3d300;
7344 }
7345
7346 static void
7347 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7348 {
7349   slotbuf[0] = 0x13d300;
7350 }
7351
7352 static void
7353 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7354 {
7355   slotbuf[0] = 0x61d300;
7356 }
7357
7358 static void
7359 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7360 {
7361   slotbuf[0] = 0x3b400;
7362 }
7363
7364 static void
7365 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7366 {
7367   slotbuf[0] = 0x13b400;
7368 }
7369
7370 static void
7371 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7372 {
7373   slotbuf[0] = 0x61b400;
7374 }
7375
7376 static void
7377 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7378 {
7379   slotbuf[0] = 0x3d400;
7380 }
7381
7382 static void
7383 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7384 {
7385   slotbuf[0] = 0x13d400;
7386 }
7387
7388 static void
7389 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7390 {
7391   slotbuf[0] = 0x61d400;
7392 }
7393
7394 static void
7395 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7396 {
7397   slotbuf[0] = 0x3b500;
7398 }
7399
7400 static void
7401 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7402 {
7403   slotbuf[0] = 0x13b500;
7404 }
7405
7406 static void
7407 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7408 {
7409   slotbuf[0] = 0x61b500;
7410 }
7411
7412 static void
7413 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7414 {
7415   slotbuf[0] = 0x3d500;
7416 }
7417
7418 static void
7419 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7420 {
7421   slotbuf[0] = 0x13d500;
7422 }
7423
7424 static void
7425 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7426 {
7427   slotbuf[0] = 0x61d500;
7428 }
7429
7430 static void
7431 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7432 {
7433   slotbuf[0] = 0x3b600;
7434 }
7435
7436 static void
7437 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7438 {
7439   slotbuf[0] = 0x13b600;
7440 }
7441
7442 static void
7443 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7444 {
7445   slotbuf[0] = 0x61b600;
7446 }
7447
7448 static void
7449 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7450 {
7451   slotbuf[0] = 0x3d600;
7452 }
7453
7454 static void
7455 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7456 {
7457   slotbuf[0] = 0x13d600;
7458 }
7459
7460 static void
7461 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7462 {
7463   slotbuf[0] = 0x61d600;
7464 }
7465
7466 static void
7467 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7468 {
7469   slotbuf[0] = 0x3b700;
7470 }
7471
7472 static void
7473 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7474 {
7475   slotbuf[0] = 0x13b700;
7476 }
7477
7478 static void
7479 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7480 {
7481   slotbuf[0] = 0x61b700;
7482 }
7483
7484 static void
7485 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7486 {
7487   slotbuf[0] = 0x3d700;
7488 }
7489
7490 static void
7491 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7492 {
7493   slotbuf[0] = 0x13d700;
7494 }
7495
7496 static void
7497 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7498 {
7499   slotbuf[0] = 0x61d700;
7500 }
7501
7502 static void
7503 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7504 {
7505   slotbuf[0] = 0x3c200;
7506 }
7507
7508 static void
7509 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7510 {
7511   slotbuf[0] = 0x13c200;
7512 }
7513
7514 static void
7515 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
7516 {
7517   slotbuf[0] = 0x61c200;
7518 }
7519
7520 static void
7521 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7522 {
7523   slotbuf[0] = 0x3c300;
7524 }
7525
7526 static void
7527 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7528 {
7529   slotbuf[0] = 0x13c300;
7530 }
7531
7532 static void
7533 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
7534 {
7535   slotbuf[0] = 0x61c300;
7536 }
7537
7538 static void
7539 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7540 {
7541   slotbuf[0] = 0x3c400;
7542 }
7543
7544 static void
7545 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7546 {
7547   slotbuf[0] = 0x13c400;
7548 }
7549
7550 static void
7551 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
7552 {
7553   slotbuf[0] = 0x61c400;
7554 }
7555
7556 static void
7557 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7558 {
7559   slotbuf[0] = 0x3c500;
7560 }
7561
7562 static void
7563 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7564 {
7565   slotbuf[0] = 0x13c500;
7566 }
7567
7568 static void
7569 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
7570 {
7571   slotbuf[0] = 0x61c500;
7572 }
7573
7574 static void
7575 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7576 {
7577   slotbuf[0] = 0x3c600;
7578 }
7579
7580 static void
7581 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7582 {
7583   slotbuf[0] = 0x13c600;
7584 }
7585
7586 static void
7587 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
7588 {
7589   slotbuf[0] = 0x61c600;
7590 }
7591
7592 static void
7593 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7594 {
7595   slotbuf[0] = 0x3c700;
7596 }
7597
7598 static void
7599 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7600 {
7601   slotbuf[0] = 0x13c700;
7602 }
7603
7604 static void
7605 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
7606 {
7607   slotbuf[0] = 0x61c700;
7608 }
7609
7610 static void
7611 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7612 {
7613   slotbuf[0] = 0x3ee00;
7614 }
7615
7616 static void
7617 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7618 {
7619   slotbuf[0] = 0x13ee00;
7620 }
7621
7622 static void
7623 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
7624 {
7625   slotbuf[0] = 0x61ee00;
7626 }
7627
7628 static void
7629 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7630 {
7631   slotbuf[0] = 0x3c000;
7632 }
7633
7634 static void
7635 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7636 {
7637   slotbuf[0] = 0x13c000;
7638 }
7639
7640 static void
7641 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
7642 {
7643   slotbuf[0] = 0x61c000;
7644 }
7645
7646 static void
7647 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7648 {
7649   slotbuf[0] = 0x3e800;
7650 }
7651
7652 static void
7653 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7654 {
7655   slotbuf[0] = 0x13e800;
7656 }
7657
7658 static void
7659 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
7660 {
7661   slotbuf[0] = 0x61e800;
7662 }
7663
7664 static void
7665 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7666 {
7667   slotbuf[0] = 0x3f400;
7668 }
7669
7670 static void
7671 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7672 {
7673   slotbuf[0] = 0x13f400;
7674 }
7675
7676 static void
7677 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
7678 {
7679   slotbuf[0] = 0x61f400;
7680 }
7681
7682 static void
7683 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7684 {
7685   slotbuf[0] = 0x3f500;
7686 }
7687
7688 static void
7689 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7690 {
7691   slotbuf[0] = 0x13f500;
7692 }
7693
7694 static void
7695 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
7696 {
7697   slotbuf[0] = 0x61f500;
7698 }
7699
7700 static void
7701 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
7702 {
7703   slotbuf[0] = 0x3eb00;
7704 }
7705
7706 static void
7707 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7708 {
7709   slotbuf[0] = 0x3e700;
7710 }
7711
7712 static void
7713 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7714 {
7715   slotbuf[0] = 0x13e700;
7716 }
7717
7718 static void
7719 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
7720 {
7721   slotbuf[0] = 0x61e700;
7722 }
7723
7724 static void
7725 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
7726 {
7727   slotbuf[0] = 0xc10000;
7728 }
7729
7730 static void
7731 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
7732 {
7733   slotbuf[0] = 0xd10000;
7734 }
7735
7736 static void
7737 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
7738 {
7739   slotbuf[0] = 0x820000;
7740 }
7741
7742 static void
7743 Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7744 {
7745   slotbuf[0] = 0x740004;
7746 }
7747
7748 static void
7749 Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7750 {
7751   slotbuf[0] = 0x750004;
7752 }
7753
7754 static void
7755 Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7756 {
7757   slotbuf[0] = 0x760004;
7758 }
7759
7760 static void
7761 Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7762 {
7763   slotbuf[0] = 0x770004;
7764 }
7765
7766 static void
7767 Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7768 {
7769   slotbuf[0] = 0x700004;
7770 }
7771
7772 static void
7773 Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7774 {
7775   slotbuf[0] = 0x710004;
7776 }
7777
7778 static void
7779 Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7780 {
7781   slotbuf[0] = 0x720004;
7782 }
7783
7784 static void
7785 Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7786 {
7787   slotbuf[0] = 0x730004;
7788 }
7789
7790 static void
7791 Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7792 {
7793   slotbuf[0] = 0x340004;
7794 }
7795
7796 static void
7797 Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7798 {
7799   slotbuf[0] = 0x350004;
7800 }
7801
7802 static void
7803 Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7804 {
7805   slotbuf[0] = 0x360004;
7806 }
7807
7808 static void
7809 Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7810 {
7811   slotbuf[0] = 0x370004;
7812 }
7813
7814 static void
7815 Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7816 {
7817   slotbuf[0] = 0x640004;
7818 }
7819
7820 static void
7821 Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7822 {
7823   slotbuf[0] = 0x650004;
7824 }
7825
7826 static void
7827 Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7828 {
7829   slotbuf[0] = 0x660004;
7830 }
7831
7832 static void
7833 Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7834 {
7835   slotbuf[0] = 0x670004;
7836 }
7837
7838 static void
7839 Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7840 {
7841   slotbuf[0] = 0x240004;
7842 }
7843
7844 static void
7845 Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7846 {
7847   slotbuf[0] = 0x250004;
7848 }
7849
7850 static void
7851 Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7852 {
7853   slotbuf[0] = 0x260004;
7854 }
7855
7856 static void
7857 Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7858 {
7859   slotbuf[0] = 0x270004;
7860 }
7861
7862 static void
7863 Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7864 {
7865   slotbuf[0] = 0x780004;
7866 }
7867
7868 static void
7869 Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7870 {
7871   slotbuf[0] = 0x790004;
7872 }
7873
7874 static void
7875 Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7876 {
7877   slotbuf[0] = 0x7a0004;
7878 }
7879
7880 static void
7881 Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7882 {
7883   slotbuf[0] = 0x7b0004;
7884 }
7885
7886 static void
7887 Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7888 {
7889   slotbuf[0] = 0x7c0004;
7890 }
7891
7892 static void
7893 Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7894 {
7895   slotbuf[0] = 0x7d0004;
7896 }
7897
7898 static void
7899 Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7900 {
7901   slotbuf[0] = 0x7e0004;
7902 }
7903
7904 static void
7905 Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7906 {
7907   slotbuf[0] = 0x7f0004;
7908 }
7909
7910 static void
7911 Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7912 {
7913   slotbuf[0] = 0x380004;
7914 }
7915
7916 static void
7917 Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7918 {
7919   slotbuf[0] = 0x390004;
7920 }
7921
7922 static void
7923 Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7924 {
7925   slotbuf[0] = 0x3a0004;
7926 }
7927
7928 static void
7929 Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7930 {
7931   slotbuf[0] = 0x3b0004;
7932 }
7933
7934 static void
7935 Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7936 {
7937   slotbuf[0] = 0x3c0004;
7938 }
7939
7940 static void
7941 Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7942 {
7943   slotbuf[0] = 0x3d0004;
7944 }
7945
7946 static void
7947 Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7948 {
7949   slotbuf[0] = 0x3e0004;
7950 }
7951
7952 static void
7953 Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7954 {
7955   slotbuf[0] = 0x3f0004;
7956 }
7957
7958 static void
7959 Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7960 {
7961   slotbuf[0] = 0x680004;
7962 }
7963
7964 static void
7965 Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7966 {
7967   slotbuf[0] = 0x690004;
7968 }
7969
7970 static void
7971 Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7972 {
7973   slotbuf[0] = 0x6a0004;
7974 }
7975
7976 static void
7977 Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7978 {
7979   slotbuf[0] = 0x6b0004;
7980 }
7981
7982 static void
7983 Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
7984 {
7985   slotbuf[0] = 0x6c0004;
7986 }
7987
7988 static void
7989 Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
7990 {
7991   slotbuf[0] = 0x6d0004;
7992 }
7993
7994 static void
7995 Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
7996 {
7997   slotbuf[0] = 0x6e0004;
7998 }
7999
8000 static void
8001 Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8002 {
8003   slotbuf[0] = 0x6f0004;
8004 }
8005
8006 static void
8007 Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
8008 {
8009   slotbuf[0] = 0x280004;
8010 }
8011
8012 static void
8013 Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8014 {
8015   slotbuf[0] = 0x290004;
8016 }
8017
8018 static void
8019 Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8020 {
8021   slotbuf[0] = 0x2a0004;
8022 }
8023
8024 static void
8025 Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8026 {
8027   slotbuf[0] = 0x2b0004;
8028 }
8029
8030 static void
8031 Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
8032 {
8033   slotbuf[0] = 0x2c0004;
8034 }
8035
8036 static void
8037 Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8038 {
8039   slotbuf[0] = 0x2d0004;
8040 }
8041
8042 static void
8043 Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8044 {
8045   slotbuf[0] = 0x2e0004;
8046 }
8047
8048 static void
8049 Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
8050 {
8051   slotbuf[0] = 0x2f0004;
8052 }
8053
8054 static void
8055 Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8056 {
8057   slotbuf[0] = 0x580004;
8058 }
8059
8060 static void
8061 Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8062 {
8063   slotbuf[0] = 0x480004;
8064 }
8065
8066 static void
8067 Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8068 {
8069   slotbuf[0] = 0x590004;
8070 }
8071
8072 static void
8073 Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8074 {
8075   slotbuf[0] = 0x490004;
8076 }
8077
8078 static void
8079 Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8080 {
8081   slotbuf[0] = 0x5a0004;
8082 }
8083
8084 static void
8085 Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8086 {
8087   slotbuf[0] = 0x4a0004;
8088 }
8089
8090 static void
8091 Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8092 {
8093   slotbuf[0] = 0x5b0004;
8094 }
8095
8096 static void
8097 Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8098 {
8099   slotbuf[0] = 0x4b0004;
8100 }
8101
8102 static void
8103 Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8104 {
8105   slotbuf[0] = 0x180004;
8106 }
8107
8108 static void
8109 Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8110 {
8111   slotbuf[0] = 0x80004;
8112 }
8113
8114 static void
8115 Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8116 {
8117   slotbuf[0] = 0x190004;
8118 }
8119
8120 static void
8121 Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8122 {
8123   slotbuf[0] = 0x90004;
8124 }
8125
8126 static void
8127 Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8128 {
8129   slotbuf[0] = 0x1a0004;
8130 }
8131
8132 static void
8133 Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8134 {
8135   slotbuf[0] = 0xa0004;
8136 }
8137
8138 static void
8139 Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8140 {
8141   slotbuf[0] = 0x1b0004;
8142 }
8143
8144 static void
8145 Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8146 {
8147   slotbuf[0] = 0xb0004;
8148 }
8149
8150 static void
8151 Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
8152 {
8153   slotbuf[0] = 0x900004;
8154 }
8155
8156 static void
8157 Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
8158 {
8159   slotbuf[0] = 0x800004;
8160 }
8161
8162 static void
8163 Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8164 {
8165   slotbuf[0] = 0x32000;
8166 }
8167
8168 static void
8169 Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8170 {
8171   slotbuf[0] = 0x132000;
8172 }
8173
8174 static void
8175 Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8176 {
8177   slotbuf[0] = 0x612000;
8178 }
8179
8180 static void
8181 Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8182 {
8183   slotbuf[0] = 0x32100;
8184 }
8185
8186 static void
8187 Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8188 {
8189   slotbuf[0] = 0x132100;
8190 }
8191
8192 static void
8193 Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8194 {
8195   slotbuf[0] = 0x612100;
8196 }
8197
8198 static void
8199 Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8200 {
8201   slotbuf[0] = 0x32200;
8202 }
8203
8204 static void
8205 Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8206 {
8207   slotbuf[0] = 0x132200;
8208 }
8209
8210 static void
8211 Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8212 {
8213   slotbuf[0] = 0x612200;
8214 }
8215
8216 static void
8217 Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
8218 {
8219   slotbuf[0] = 0x32300;
8220 }
8221
8222 static void
8223 Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
8224 {
8225   slotbuf[0] = 0x132300;
8226 }
8227
8228 static void
8229 Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
8230 {
8231   slotbuf[0] = 0x612300;
8232 }
8233
8234 static void
8235 Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8236 {
8237   slotbuf[0] = 0x31000;
8238 }
8239
8240 static void
8241 Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8242 {
8243   slotbuf[0] = 0x131000;
8244 }
8245
8246 static void
8247 Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8248 {
8249   slotbuf[0] = 0x611000;
8250 }
8251
8252 static void
8253 Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8254 {
8255   slotbuf[0] = 0x31100;
8256 }
8257
8258 static void
8259 Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8260 {
8261   slotbuf[0] = 0x131100;
8262 }
8263
8264 static void
8265 Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8266 {
8267   slotbuf[0] = 0x611100;
8268 }
8269
8270 static void
8271 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8272 {
8273   slotbuf[0] = 0x3010;
8274 }
8275
8276 static void
8277 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
8278 {
8279   slotbuf[0] = 0x7000;
8280 }
8281
8282 static void
8283 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
8284 {
8285   slotbuf[0] = 0x3e200;
8286 }
8287
8288 static void
8289 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
8290 {
8291   slotbuf[0] = 0x13e200;
8292 }
8293
8294 static void
8295 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
8296 {
8297   slotbuf[0] = 0x13e300;
8298 }
8299
8300 static void
8301 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8302 {
8303   slotbuf[0] = 0x3e400;
8304 }
8305
8306 static void
8307 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8308 {
8309   slotbuf[0] = 0x13e400;
8310 }
8311
8312 static void
8313 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8314 {
8315   slotbuf[0] = 0x61e400;
8316 }
8317
8318 static void
8319 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
8320 {
8321   slotbuf[0] = 0x4000;
8322 }
8323
8324 static void
8325 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
8326 {
8327   slotbuf[0] = 0xf02d;
8328 }
8329
8330 static void
8331 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8332 {
8333   slotbuf[0] = 0x39000;
8334 }
8335
8336 static void
8337 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8338 {
8339   slotbuf[0] = 0x139000;
8340 }
8341
8342 static void
8343 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8344 {
8345   slotbuf[0] = 0x619000;
8346 }
8347
8348 static void
8349 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8350 {
8351   slotbuf[0] = 0x3a000;
8352 }
8353
8354 static void
8355 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8356 {
8357   slotbuf[0] = 0x13a000;
8358 }
8359
8360 static void
8361 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8362 {
8363   slotbuf[0] = 0x61a000;
8364 }
8365
8366 static void
8367 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8368 {
8369   slotbuf[0] = 0x39100;
8370 }
8371
8372 static void
8373 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8374 {
8375   slotbuf[0] = 0x139100;
8376 }
8377
8378 static void
8379 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8380 {
8381   slotbuf[0] = 0x619100;
8382 }
8383
8384 static void
8385 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8386 {
8387   slotbuf[0] = 0x3a100;
8388 }
8389
8390 static void
8391 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8392 {
8393   slotbuf[0] = 0x13a100;
8394 }
8395
8396 static void
8397 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8398 {
8399   slotbuf[0] = 0x61a100;
8400 }
8401
8402 static void
8403 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8404 {
8405   slotbuf[0] = 0x38000;
8406 }
8407
8408 static void
8409 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8410 {
8411   slotbuf[0] = 0x138000;
8412 }
8413
8414 static void
8415 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8416 {
8417   slotbuf[0] = 0x618000;
8418 }
8419
8420 static void
8421 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8422 {
8423   slotbuf[0] = 0x38100;
8424 }
8425
8426 static void
8427 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8428 {
8429   slotbuf[0] = 0x138100;
8430 }
8431
8432 static void
8433 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8434 {
8435   slotbuf[0] = 0x618100;
8436 }
8437
8438 static void
8439 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8440 {
8441   slotbuf[0] = 0x36000;
8442 }
8443
8444 static void
8445 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8446 {
8447   slotbuf[0] = 0x136000;
8448 }
8449
8450 static void
8451 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
8452 {
8453   slotbuf[0] = 0x616000;
8454 }
8455
8456 static void
8457 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
8458 {
8459   slotbuf[0] = 0x3e900;
8460 }
8461
8462 static void
8463 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
8464 {
8465   slotbuf[0] = 0x13e900;
8466 }
8467
8468 static void
8469 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
8470 {
8471   slotbuf[0] = 0x61e900;
8472 }
8473
8474 static void
8475 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8476 {
8477   slotbuf[0] = 0x3ec00;
8478 }
8479
8480 static void
8481 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8482 {
8483   slotbuf[0] = 0x13ec00;
8484 }
8485
8486 static void
8487 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8488 {
8489   slotbuf[0] = 0x61ec00;
8490 }
8491
8492 static void
8493 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
8494 {
8495   slotbuf[0] = 0x3ed00;
8496 }
8497
8498 static void
8499 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
8500 {
8501   slotbuf[0] = 0x13ed00;
8502 }
8503
8504 static void
8505 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
8506 {
8507   slotbuf[0] = 0x61ed00;
8508 }
8509
8510 static void
8511 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8512 {
8513   slotbuf[0] = 0x36800;
8514 }
8515
8516 static void
8517 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8518 {
8519   slotbuf[0] = 0x136800;
8520 }
8521
8522 static void
8523 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8524 {
8525   slotbuf[0] = 0x616800;
8526 }
8527
8528 static void
8529 Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
8530 {
8531   slotbuf[0] = 0x70e0;
8532 }
8533
8534 static void
8535 Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
8536 {
8537   slotbuf[0] = 0x70f0;
8538 }
8539
8540 static void
8541 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8542 {
8543   slotbuf[0] = 0xf1e000;
8544 }
8545
8546 static void
8547 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
8548 {
8549   slotbuf[0] = 0xf1e010;
8550 }
8551
8552 static void
8553 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
8554 {
8555   slotbuf[0] = 0x135900;
8556 }
8557
8558 static void
8559 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8560 {
8561   slotbuf[0] = 0x3ea00;
8562 }
8563
8564 static void
8565 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8566 {
8567   slotbuf[0] = 0x13ea00;
8568 }
8569
8570 static void
8571 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
8572 {
8573   slotbuf[0] = 0x61ea00;
8574 }
8575
8576 static void
8577 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8578 {
8579   slotbuf[0] = 0x3f000;
8580 }
8581
8582 static void
8583 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8584 {
8585   slotbuf[0] = 0x13f000;
8586 }
8587
8588 static void
8589 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8590 {
8591   slotbuf[0] = 0x61f000;
8592 }
8593
8594 static void
8595 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8596 {
8597   slotbuf[0] = 0x3f100;
8598 }
8599
8600 static void
8601 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8602 {
8603   slotbuf[0] = 0x13f100;
8604 }
8605
8606 static void
8607 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8608 {
8609   slotbuf[0] = 0x61f100;
8610 }
8611
8612 static void
8613 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8614 {
8615   slotbuf[0] = 0x3f200;
8616 }
8617
8618 static void
8619 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8620 {
8621   slotbuf[0] = 0x13f200;
8622 }
8623
8624 static void
8625 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
8626 {
8627   slotbuf[0] = 0x61f200;
8628 }
8629
8630 static void
8631 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
8632 {
8633   slotbuf[0] = 0x70c2;
8634 }
8635
8636 static void
8637 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8638 {
8639   slotbuf[0] = 0x70e2;
8640 }
8641
8642 static void
8643 Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8644 {
8645   slotbuf[0] = 0x70d2;
8646 }
8647
8648 static void
8649 Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8650 {
8651   slotbuf[0] = 0x270d2;
8652 }
8653
8654 static void
8655 Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8656 {
8657   slotbuf[0] = 0x370d2;
8658 }
8659
8660 static void
8661 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
8662 {
8663   slotbuf[0] = 0x70f2;
8664 }
8665
8666 static void
8667 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
8668 {
8669   slotbuf[0] = 0xf10000;
8670 }
8671
8672 static void
8673 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
8674 {
8675   slotbuf[0] = 0xf12000;
8676 }
8677
8678 static void
8679 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
8680 {
8681   slotbuf[0] = 0xf11000;
8682 }
8683
8684 static void
8685 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
8686 {
8687   slotbuf[0] = 0xf13000;
8688 }
8689
8690 static void
8691 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8692 {
8693   slotbuf[0] = 0x7042;
8694 }
8695
8696 static void
8697 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8698 {
8699   slotbuf[0] = 0x7052;
8700 }
8701
8702 static void
8703 Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
8704 {
8705   slotbuf[0] = 0xf7082;
8706 }
8707
8708 static void
8709 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8710 {
8711   slotbuf[0] = 0x47082;
8712 }
8713
8714 static void
8715 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8716 {
8717   slotbuf[0] = 0x57082;
8718 }
8719
8720 static void
8721 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
8722 {
8723   slotbuf[0] = 0x7062;
8724 }
8725
8726 static void
8727 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
8728 {
8729   slotbuf[0] = 0x7072;
8730 }
8731
8732 static void
8733 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
8734 {
8735   slotbuf[0] = 0x7002;
8736 }
8737
8738 static void
8739 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
8740 {
8741   slotbuf[0] = 0x7012;
8742 }
8743
8744 static void
8745 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
8746 {
8747   slotbuf[0] = 0x7022;
8748 }
8749
8750 static void
8751 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
8752 {
8753   slotbuf[0] = 0x7032;
8754 }
8755
8756 static void
8757 Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8758 {
8759   slotbuf[0] = 0x7082;
8760 }
8761
8762 static void
8763 Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8764 {
8765   slotbuf[0] = 0x27082;
8766 }
8767
8768 static void
8769 Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8770 {
8771   slotbuf[0] = 0x37082;
8772 }
8773
8774 static void
8775 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
8776 {
8777   slotbuf[0] = 0xf19000;
8778 }
8779
8780 static void
8781 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
8782 {
8783   slotbuf[0] = 0xf18000;
8784 }
8785
8786 static void
8787 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8788 {
8789   slotbuf[0] = 0x50c000;
8790 }
8791
8792 static void
8793 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8794 {
8795   slotbuf[0] = 0x50d000;
8796 }
8797
8798 static void
8799 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8800 {
8801   slotbuf[0] = 0x50b000;
8802 }
8803
8804 static void
8805 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8806 {
8807   slotbuf[0] = 0x50f000;
8808 }
8809
8810 static void
8811 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8812 {
8813   slotbuf[0] = 0x50e000;
8814 }
8815
8816 static void
8817 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8818 {
8819   slotbuf[0] = 0x504000;
8820 }
8821
8822 static void
8823 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8824 {
8825   slotbuf[0] = 0x505000;
8826 }
8827
8828 static void
8829 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
8830 {
8831   slotbuf[0] = 0x503000;
8832 }
8833
8834 static void
8835 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8836 {
8837   slotbuf[0] = 0x507000;
8838 }
8839
8840 static void
8841 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
8842 {
8843   slotbuf[0] = 0x506000;
8844 }
8845
8846 static void
8847 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
8848 {
8849   slotbuf[0] = 0x330000;
8850 }
8851
8852 static void
8853 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
8854 {
8855   slotbuf[0] = 0x430000;
8856 }
8857
8858 static void
8859 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
8860 {
8861   slotbuf[0] = 0x530000;
8862 }
8863
8864 static void
8865 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8866 {
8867   slotbuf[0] = 0x630000;
8868 }
8869
8870 static void
8871 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8872 {
8873   slotbuf[0] = 0x730000;
8874 }
8875
8876 static void
8877 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
8878 {
8879   slotbuf[0] = 0x40e000;
8880 }
8881
8882 static void
8883 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
8884 {
8885   slotbuf[0] = 0x40f000;
8886 }
8887
8888 static void
8889 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
8890 {
8891   slotbuf[0] = 0x230000;
8892 }
8893
8894 static void
8895 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
8896 {
8897   slotbuf[0] = 0xb002;
8898 }
8899
8900 static void
8901 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
8902 {
8903   slotbuf[0] = 0xf002;
8904 }
8905
8906 static void
8907 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
8908 {
8909   slotbuf[0] = 0xe002;
8910 }
8911
8912 static void
8913 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8914 {
8915   slotbuf[0] = 0x30c00;
8916 }
8917
8918 static void
8919 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8920 {
8921   slotbuf[0] = 0x130c00;
8922 }
8923
8924 static void
8925 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
8926 {
8927   slotbuf[0] = 0x610c00;
8928 }
8929
8930 static void
8931 Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8932 {
8933   slotbuf[0] = 0x36300;
8934 }
8935
8936 static void
8937 Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8938 {
8939   slotbuf[0] = 0x136300;
8940 }
8941
8942 static void
8943 Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
8944 {
8945   slotbuf[0] = 0x616300;
8946 }
8947
8948 static void
8949 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
8950 {
8951   slotbuf[0] = 0xc20000;
8952 }
8953
8954 static void
8955 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
8956 {
8957   slotbuf[0] = 0xd20000;
8958 }
8959
8960 static void
8961 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
8962 {
8963   slotbuf[0] = 0xe20000;
8964 }
8965
8966 static void
8967 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
8968 {
8969   slotbuf[0] = 0xf20000;
8970 }
8971
8972 static void
8973 Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
8974 {
8975   slotbuf[0] = 0x406000;
8976 }
8977
8978 static void
8979 Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
8980 {
8981   slotbuf[0] = 0x407000;
8982 }
8983
8984 static void
8985 Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
8986 {
8987   slotbuf[0] = 0xe30e60;
8988 }
8989
8990 static void
8991 Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
8992 {
8993   slotbuf[0] = 0xf3e600;
8994 }
8995
8996 static void
8997 Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
8998 {
8999   slotbuf[0] = 0xe0000;
9000 }
9001
9002 static void
9003 Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
9004 {
9005   slotbuf[0] = 0xe1000;
9006 }
9007
9008 static void
9009 Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
9010 {
9011   slotbuf[0] = 0xe1200;
9012 }
9013
9014 static void
9015 Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
9016 {
9017   slotbuf[0] = 0xe2000;
9018 }
9019
9020 static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
9021   Opcode_excw_Slot_inst_encode, 0, 0
9022 };
9023
9024 static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
9025   Opcode_rfe_Slot_inst_encode, 0, 0
9026 };
9027
9028 static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
9029   Opcode_rfde_Slot_inst_encode, 0, 0
9030 };
9031
9032 static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
9033   Opcode_syscall_Slot_inst_encode, 0, 0
9034 };
9035
9036 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
9037   Opcode_call12_Slot_inst_encode, 0, 0
9038 };
9039
9040 static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
9041   Opcode_call8_Slot_inst_encode, 0, 0
9042 };
9043
9044 static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
9045   Opcode_call4_Slot_inst_encode, 0, 0
9046 };
9047
9048 static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
9049   Opcode_callx12_Slot_inst_encode, 0, 0
9050 };
9051
9052 static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
9053   Opcode_callx8_Slot_inst_encode, 0, 0
9054 };
9055
9056 static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
9057   Opcode_callx4_Slot_inst_encode, 0, 0
9058 };
9059
9060 static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
9061   Opcode_entry_Slot_inst_encode, 0, 0
9062 };
9063
9064 static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
9065   Opcode_movsp_Slot_inst_encode, 0, 0
9066 };
9067
9068 static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
9069   Opcode_rotw_Slot_inst_encode, 0, 0
9070 };
9071
9072 static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
9073   Opcode_retw_Slot_inst_encode, 0, 0
9074 };
9075
9076 static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
9077   0, 0, Opcode_retw_n_Slot_inst16b_encode
9078 };
9079
9080 static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
9081   Opcode_rfwo_Slot_inst_encode, 0, 0
9082 };
9083
9084 static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
9085   Opcode_rfwu_Slot_inst_encode, 0, 0
9086 };
9087
9088 static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
9089   Opcode_l32e_Slot_inst_encode, 0, 0
9090 };
9091
9092 static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
9093   Opcode_s32e_Slot_inst_encode, 0, 0
9094 };
9095
9096 static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
9097   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
9098 };
9099
9100 static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
9101   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
9102 };
9103
9104 static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
9105   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
9106 };
9107
9108 static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
9109   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
9110 };
9111
9112 static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
9113   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
9114 };
9115
9116 static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
9117   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
9118 };
9119
9120 static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
9121   0, Opcode_add_n_Slot_inst16a_encode, 0
9122 };
9123
9124 static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
9125   0, Opcode_addi_n_Slot_inst16a_encode, 0
9126 };
9127
9128 static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
9129   0, 0, Opcode_beqz_n_Slot_inst16b_encode
9130 };
9131
9132 static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
9133   0, 0, Opcode_bnez_n_Slot_inst16b_encode
9134 };
9135
9136 static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
9137   0, 0, Opcode_ill_n_Slot_inst16b_encode
9138 };
9139
9140 static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
9141   0, Opcode_l32i_n_Slot_inst16a_encode, 0
9142 };
9143
9144 static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
9145   0, 0, Opcode_mov_n_Slot_inst16b_encode
9146 };
9147
9148 static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
9149   0, 0, Opcode_movi_n_Slot_inst16b_encode
9150 };
9151
9152 static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
9153   0, 0, Opcode_nop_n_Slot_inst16b_encode
9154 };
9155
9156 static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
9157   0, 0, Opcode_ret_n_Slot_inst16b_encode
9158 };
9159
9160 static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
9161   0, Opcode_s32i_n_Slot_inst16a_encode, 0
9162 };
9163
9164 static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
9165   Opcode_addi_Slot_inst_encode, 0, 0
9166 };
9167
9168 static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
9169   Opcode_addmi_Slot_inst_encode, 0, 0
9170 };
9171
9172 static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
9173   Opcode_add_Slot_inst_encode, 0, 0
9174 };
9175
9176 static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
9177   Opcode_sub_Slot_inst_encode, 0, 0
9178 };
9179
9180 static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
9181   Opcode_addx2_Slot_inst_encode, 0, 0
9182 };
9183
9184 static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
9185   Opcode_addx4_Slot_inst_encode, 0, 0
9186 };
9187
9188 static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
9189   Opcode_addx8_Slot_inst_encode, 0, 0
9190 };
9191
9192 static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
9193   Opcode_subx2_Slot_inst_encode, 0, 0
9194 };
9195
9196 static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
9197   Opcode_subx4_Slot_inst_encode, 0, 0
9198 };
9199
9200 static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
9201   Opcode_subx8_Slot_inst_encode, 0, 0
9202 };
9203
9204 static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
9205   Opcode_and_Slot_inst_encode, 0, 0
9206 };
9207
9208 static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
9209   Opcode_or_Slot_inst_encode, 0, 0
9210 };
9211
9212 static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
9213   Opcode_xor_Slot_inst_encode, 0, 0
9214 };
9215
9216 static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
9217   Opcode_beqi_Slot_inst_encode, 0, 0
9218 };
9219
9220 static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
9221   Opcode_bnei_Slot_inst_encode, 0, 0
9222 };
9223
9224 static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
9225   Opcode_bgei_Slot_inst_encode, 0, 0
9226 };
9227
9228 static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
9229   Opcode_blti_Slot_inst_encode, 0, 0
9230 };
9231
9232 static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
9233   Opcode_bbci_Slot_inst_encode, 0, 0
9234 };
9235
9236 static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
9237   Opcode_bbsi_Slot_inst_encode, 0, 0
9238 };
9239
9240 static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
9241   Opcode_bgeui_Slot_inst_encode, 0, 0
9242 };
9243
9244 static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
9245   Opcode_bltui_Slot_inst_encode, 0, 0
9246 };
9247
9248 static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
9249   Opcode_beq_Slot_inst_encode, 0, 0
9250 };
9251
9252 static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
9253   Opcode_bne_Slot_inst_encode, 0, 0
9254 };
9255
9256 static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
9257   Opcode_bge_Slot_inst_encode, 0, 0
9258 };
9259
9260 static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
9261   Opcode_blt_Slot_inst_encode, 0, 0
9262 };
9263
9264 static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
9265   Opcode_bgeu_Slot_inst_encode, 0, 0
9266 };
9267
9268 static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
9269   Opcode_bltu_Slot_inst_encode, 0, 0
9270 };
9271
9272 static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
9273   Opcode_bany_Slot_inst_encode, 0, 0
9274 };
9275
9276 static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
9277   Opcode_bnone_Slot_inst_encode, 0, 0
9278 };
9279
9280 static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
9281   Opcode_ball_Slot_inst_encode, 0, 0
9282 };
9283
9284 static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
9285   Opcode_bnall_Slot_inst_encode, 0, 0
9286 };
9287
9288 static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
9289   Opcode_bbc_Slot_inst_encode, 0, 0
9290 };
9291
9292 static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
9293   Opcode_bbs_Slot_inst_encode, 0, 0
9294 };
9295
9296 static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
9297   Opcode_beqz_Slot_inst_encode, 0, 0
9298 };
9299
9300 static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
9301   Opcode_bnez_Slot_inst_encode, 0, 0
9302 };
9303
9304 static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
9305   Opcode_bgez_Slot_inst_encode, 0, 0
9306 };
9307
9308 static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
9309   Opcode_bltz_Slot_inst_encode, 0, 0
9310 };
9311
9312 static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
9313   Opcode_call0_Slot_inst_encode, 0, 0
9314 };
9315
9316 static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
9317   Opcode_callx0_Slot_inst_encode, 0, 0
9318 };
9319
9320 static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
9321   Opcode_extui_Slot_inst_encode, 0, 0
9322 };
9323
9324 static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
9325   Opcode_ill_Slot_inst_encode, 0, 0
9326 };
9327
9328 static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
9329   Opcode_j_Slot_inst_encode, 0, 0
9330 };
9331
9332 static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
9333   Opcode_jx_Slot_inst_encode, 0, 0
9334 };
9335
9336 static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
9337   Opcode_l16ui_Slot_inst_encode, 0, 0
9338 };
9339
9340 static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
9341   Opcode_l16si_Slot_inst_encode, 0, 0
9342 };
9343
9344 static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
9345   Opcode_l32i_Slot_inst_encode, 0, 0
9346 };
9347
9348 static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
9349   Opcode_l32r_Slot_inst_encode, 0, 0
9350 };
9351
9352 static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
9353   Opcode_l8ui_Slot_inst_encode, 0, 0
9354 };
9355
9356 static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
9357   Opcode_loop_Slot_inst_encode, 0, 0
9358 };
9359
9360 static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
9361   Opcode_loopnez_Slot_inst_encode, 0, 0
9362 };
9363
9364 static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
9365   Opcode_loopgtz_Slot_inst_encode, 0, 0
9366 };
9367
9368 static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
9369   Opcode_movi_Slot_inst_encode, 0, 0
9370 };
9371
9372 static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
9373   Opcode_moveqz_Slot_inst_encode, 0, 0
9374 };
9375
9376 static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
9377   Opcode_movnez_Slot_inst_encode, 0, 0
9378 };
9379
9380 static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
9381   Opcode_movltz_Slot_inst_encode, 0, 0
9382 };
9383
9384 static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
9385   Opcode_movgez_Slot_inst_encode, 0, 0
9386 };
9387
9388 static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
9389   Opcode_neg_Slot_inst_encode, 0, 0
9390 };
9391
9392 static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
9393   Opcode_abs_Slot_inst_encode, 0, 0
9394 };
9395
9396 static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
9397   Opcode_nop_Slot_inst_encode, 0, 0
9398 };
9399
9400 static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
9401   Opcode_ret_Slot_inst_encode, 0, 0
9402 };
9403
9404 static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
9405   Opcode_simcall_Slot_inst_encode, 0, 0
9406 };
9407
9408 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
9409   Opcode_s16i_Slot_inst_encode, 0, 0
9410 };
9411
9412 static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
9413   Opcode_s32i_Slot_inst_encode, 0, 0
9414 };
9415
9416 static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
9417   Opcode_s32nb_Slot_inst_encode, 0, 0
9418 };
9419
9420 static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
9421   Opcode_s8i_Slot_inst_encode, 0, 0
9422 };
9423
9424 static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
9425   Opcode_ssr_Slot_inst_encode, 0, 0
9426 };
9427
9428 static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
9429   Opcode_ssl_Slot_inst_encode, 0, 0
9430 };
9431
9432 static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
9433   Opcode_ssa8l_Slot_inst_encode, 0, 0
9434 };
9435
9436 static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
9437   Opcode_ssa8b_Slot_inst_encode, 0, 0
9438 };
9439
9440 static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
9441   Opcode_ssai_Slot_inst_encode, 0, 0
9442 };
9443
9444 static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
9445   Opcode_sll_Slot_inst_encode, 0, 0
9446 };
9447
9448 static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
9449   Opcode_src_Slot_inst_encode, 0, 0
9450 };
9451
9452 static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
9453   Opcode_srl_Slot_inst_encode, 0, 0
9454 };
9455
9456 static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
9457   Opcode_sra_Slot_inst_encode, 0, 0
9458 };
9459
9460 static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
9461   Opcode_slli_Slot_inst_encode, 0, 0
9462 };
9463
9464 static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
9465   Opcode_srai_Slot_inst_encode, 0, 0
9466 };
9467
9468 static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
9469   Opcode_srli_Slot_inst_encode, 0, 0
9470 };
9471
9472 static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
9473   Opcode_memw_Slot_inst_encode, 0, 0
9474 };
9475
9476 static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
9477   Opcode_extw_Slot_inst_encode, 0, 0
9478 };
9479
9480 static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
9481   Opcode_isync_Slot_inst_encode, 0, 0
9482 };
9483
9484 static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
9485   Opcode_rsync_Slot_inst_encode, 0, 0
9486 };
9487
9488 static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
9489   Opcode_esync_Slot_inst_encode, 0, 0
9490 };
9491
9492 static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
9493   Opcode_dsync_Slot_inst_encode, 0, 0
9494 };
9495
9496 static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
9497   Opcode_rsil_Slot_inst_encode, 0, 0
9498 };
9499
9500 static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
9501   Opcode_rsr_lend_Slot_inst_encode, 0, 0
9502 };
9503
9504 static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
9505   Opcode_wsr_lend_Slot_inst_encode, 0, 0
9506 };
9507
9508 static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
9509   Opcode_xsr_lend_Slot_inst_encode, 0, 0
9510 };
9511
9512 static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
9513   Opcode_rsr_lcount_Slot_inst_encode, 0, 0
9514 };
9515
9516 static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
9517   Opcode_wsr_lcount_Slot_inst_encode, 0, 0
9518 };
9519
9520 static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
9521   Opcode_xsr_lcount_Slot_inst_encode, 0, 0
9522 };
9523
9524 static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
9525   Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
9526 };
9527
9528 static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
9529   Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
9530 };
9531
9532 static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
9533   Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
9534 };
9535
9536 static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
9537   Opcode_rsr_sar_Slot_inst_encode, 0, 0
9538 };
9539
9540 static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
9541   Opcode_wsr_sar_Slot_inst_encode, 0, 0
9542 };
9543
9544 static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
9545   Opcode_xsr_sar_Slot_inst_encode, 0, 0
9546 };
9547
9548 static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
9549   Opcode_rsr_memctl_Slot_inst_encode, 0, 0
9550 };
9551
9552 static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
9553   Opcode_wsr_memctl_Slot_inst_encode, 0, 0
9554 };
9555
9556 static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
9557   Opcode_xsr_memctl_Slot_inst_encode, 0, 0
9558 };
9559
9560 static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
9561   Opcode_rsr_litbase_Slot_inst_encode, 0, 0
9562 };
9563
9564 static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
9565   Opcode_wsr_litbase_Slot_inst_encode, 0, 0
9566 };
9567
9568 static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
9569   Opcode_xsr_litbase_Slot_inst_encode, 0, 0
9570 };
9571
9572 static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
9573   Opcode_rsr_configid0_Slot_inst_encode, 0, 0
9574 };
9575
9576 static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
9577   Opcode_wsr_configid0_Slot_inst_encode, 0, 0
9578 };
9579
9580 static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
9581   Opcode_rsr_configid1_Slot_inst_encode, 0, 0
9582 };
9583
9584 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
9585   Opcode_rsr_ps_Slot_inst_encode, 0, 0
9586 };
9587
9588 static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
9589   Opcode_wsr_ps_Slot_inst_encode, 0, 0
9590 };
9591
9592 static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
9593   Opcode_xsr_ps_Slot_inst_encode, 0, 0
9594 };
9595
9596 static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
9597   Opcode_rsr_epc1_Slot_inst_encode, 0, 0
9598 };
9599
9600 static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
9601   Opcode_wsr_epc1_Slot_inst_encode, 0, 0
9602 };
9603
9604 static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
9605   Opcode_xsr_epc1_Slot_inst_encode, 0, 0
9606 };
9607
9608 static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
9609   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
9610 };
9611
9612 static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
9613   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
9614 };
9615
9616 static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
9617   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
9618 };
9619
9620 static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
9621   Opcode_rsr_epc2_Slot_inst_encode, 0, 0
9622 };
9623
9624 static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
9625   Opcode_wsr_epc2_Slot_inst_encode, 0, 0
9626 };
9627
9628 static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
9629   Opcode_xsr_epc2_Slot_inst_encode, 0, 0
9630 };
9631
9632 static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
9633   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
9634 };
9635
9636 static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
9637   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
9638 };
9639
9640 static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
9641   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
9642 };
9643
9644 static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
9645   Opcode_rsr_epc3_Slot_inst_encode, 0, 0
9646 };
9647
9648 static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
9649   Opcode_wsr_epc3_Slot_inst_encode, 0, 0
9650 };
9651
9652 static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
9653   Opcode_xsr_epc3_Slot_inst_encode, 0, 0
9654 };
9655
9656 static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
9657   Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
9658 };
9659
9660 static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
9661   Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
9662 };
9663
9664 static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
9665   Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
9666 };
9667
9668 static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
9669   Opcode_rsr_epc4_Slot_inst_encode, 0, 0
9670 };
9671
9672 static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
9673   Opcode_wsr_epc4_Slot_inst_encode, 0, 0
9674 };
9675
9676 static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
9677   Opcode_xsr_epc4_Slot_inst_encode, 0, 0
9678 };
9679
9680 static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
9681   Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
9682 };
9683
9684 static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
9685   Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
9686 };
9687
9688 static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
9689   Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
9690 };
9691
9692 static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
9693   Opcode_rsr_epc5_Slot_inst_encode, 0, 0
9694 };
9695
9696 static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
9697   Opcode_wsr_epc5_Slot_inst_encode, 0, 0
9698 };
9699
9700 static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
9701   Opcode_xsr_epc5_Slot_inst_encode, 0, 0
9702 };
9703
9704 static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
9705   Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
9706 };
9707
9708 static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
9709   Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
9710 };
9711
9712 static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
9713   Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
9714 };
9715
9716 static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
9717   Opcode_rsr_epc6_Slot_inst_encode, 0, 0
9718 };
9719
9720 static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
9721   Opcode_wsr_epc6_Slot_inst_encode, 0, 0
9722 };
9723
9724 static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
9725   Opcode_xsr_epc6_Slot_inst_encode, 0, 0
9726 };
9727
9728 static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
9729   Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
9730 };
9731
9732 static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
9733   Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
9734 };
9735
9736 static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
9737   Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
9738 };
9739
9740 static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
9741   Opcode_rsr_epc7_Slot_inst_encode, 0, 0
9742 };
9743
9744 static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
9745   Opcode_wsr_epc7_Slot_inst_encode, 0, 0
9746 };
9747
9748 static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
9749   Opcode_xsr_epc7_Slot_inst_encode, 0, 0
9750 };
9751
9752 static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
9753   Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
9754 };
9755
9756 static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
9757   Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
9758 };
9759
9760 static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
9761   Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
9762 };
9763
9764 static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
9765   Opcode_rsr_eps2_Slot_inst_encode, 0, 0
9766 };
9767
9768 static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
9769   Opcode_wsr_eps2_Slot_inst_encode, 0, 0
9770 };
9771
9772 static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
9773   Opcode_xsr_eps2_Slot_inst_encode, 0, 0
9774 };
9775
9776 static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
9777   Opcode_rsr_eps3_Slot_inst_encode, 0, 0
9778 };
9779
9780 static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
9781   Opcode_wsr_eps3_Slot_inst_encode, 0, 0
9782 };
9783
9784 static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
9785   Opcode_xsr_eps3_Slot_inst_encode, 0, 0
9786 };
9787
9788 static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
9789   Opcode_rsr_eps4_Slot_inst_encode, 0, 0
9790 };
9791
9792 static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
9793   Opcode_wsr_eps4_Slot_inst_encode, 0, 0
9794 };
9795
9796 static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
9797   Opcode_xsr_eps4_Slot_inst_encode, 0, 0
9798 };
9799
9800 static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
9801   Opcode_rsr_eps5_Slot_inst_encode, 0, 0
9802 };
9803
9804 static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
9805   Opcode_wsr_eps5_Slot_inst_encode, 0, 0
9806 };
9807
9808 static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
9809   Opcode_xsr_eps5_Slot_inst_encode, 0, 0
9810 };
9811
9812 static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
9813   Opcode_rsr_eps6_Slot_inst_encode, 0, 0
9814 };
9815
9816 static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
9817   Opcode_wsr_eps6_Slot_inst_encode, 0, 0
9818 };
9819
9820 static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
9821   Opcode_xsr_eps6_Slot_inst_encode, 0, 0
9822 };
9823
9824 static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
9825   Opcode_rsr_eps7_Slot_inst_encode, 0, 0
9826 };
9827
9828 static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
9829   Opcode_wsr_eps7_Slot_inst_encode, 0, 0
9830 };
9831
9832 static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
9833   Opcode_xsr_eps7_Slot_inst_encode, 0, 0
9834 };
9835
9836 static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
9837   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
9838 };
9839
9840 static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
9841   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
9842 };
9843
9844 static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
9845   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
9846 };
9847
9848 static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
9849   Opcode_rsr_depc_Slot_inst_encode, 0, 0
9850 };
9851
9852 static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
9853   Opcode_wsr_depc_Slot_inst_encode, 0, 0
9854 };
9855
9856 static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
9857   Opcode_xsr_depc_Slot_inst_encode, 0, 0
9858 };
9859
9860 static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
9861   Opcode_rsr_exccause_Slot_inst_encode, 0, 0
9862 };
9863
9864 static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
9865   Opcode_wsr_exccause_Slot_inst_encode, 0, 0
9866 };
9867
9868 static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
9869   Opcode_xsr_exccause_Slot_inst_encode, 0, 0
9870 };
9871
9872 static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
9873   Opcode_rsr_misc0_Slot_inst_encode, 0, 0
9874 };
9875
9876 static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
9877   Opcode_wsr_misc0_Slot_inst_encode, 0, 0
9878 };
9879
9880 static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
9881   Opcode_xsr_misc0_Slot_inst_encode, 0, 0
9882 };
9883
9884 static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
9885   Opcode_rsr_misc1_Slot_inst_encode, 0, 0
9886 };
9887
9888 static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
9889   Opcode_wsr_misc1_Slot_inst_encode, 0, 0
9890 };
9891
9892 static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
9893   Opcode_xsr_misc1_Slot_inst_encode, 0, 0
9894 };
9895
9896 static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
9897   Opcode_rsr_prid_Slot_inst_encode, 0, 0
9898 };
9899
9900 static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
9901   Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
9902 };
9903
9904 static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
9905   Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
9906 };
9907
9908 static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
9909   Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
9910 };
9911
9912 static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
9913   Opcode_mul16u_Slot_inst_encode, 0, 0
9914 };
9915
9916 static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
9917   Opcode_mul16s_Slot_inst_encode, 0, 0
9918 };
9919
9920 static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
9921   Opcode_mull_Slot_inst_encode, 0, 0
9922 };
9923
9924 static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
9925   Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
9926 };
9927
9928 static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
9929   Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
9930 };
9931
9932 static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
9933   Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
9934 };
9935
9936 static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
9937   Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
9938 };
9939
9940 static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
9941   Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
9942 };
9943
9944 static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
9945   Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
9946 };
9947
9948 static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
9949   Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
9950 };
9951
9952 static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
9953   Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
9954 };
9955
9956 static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
9957   Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
9958 };
9959
9960 static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
9961   Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
9962 };
9963
9964 static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
9965   Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
9966 };
9967
9968 static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
9969   Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
9970 };
9971
9972 static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
9973   Opcode_mul_da_ll_Slot_inst_encode, 0, 0
9974 };
9975
9976 static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
9977   Opcode_mul_da_hl_Slot_inst_encode, 0, 0
9978 };
9979
9980 static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
9981   Opcode_mul_da_lh_Slot_inst_encode, 0, 0
9982 };
9983
9984 static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
9985   Opcode_mul_da_hh_Slot_inst_encode, 0, 0
9986 };
9987
9988 static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
9989   Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
9990 };
9991
9992 static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
9993   Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
9994 };
9995
9996 static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
9997   Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
9998 };
9999
10000 static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
10001   Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
10002 };
10003
10004 static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
10005   Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
10006 };
10007
10008 static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
10009   Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
10010 };
10011
10012 static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
10013   Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
10014 };
10015
10016 static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
10017   Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
10018 };
10019
10020 static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
10021   Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
10022 };
10023
10024 static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
10025   Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
10026 };
10027
10028 static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
10029   Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
10030 };
10031
10032 static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
10033   Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
10034 };
10035
10036 static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
10037   Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
10038 };
10039
10040 static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
10041   Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
10042 };
10043
10044 static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
10045   Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
10046 };
10047
10048 static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
10049   Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
10050 };
10051
10052 static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
10053   Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
10054 };
10055
10056 static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
10057   Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
10058 };
10059
10060 static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
10061   Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
10062 };
10063
10064 static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
10065   Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
10066 };
10067
10068 static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
10069   Opcode_mula_da_ll_Slot_inst_encode, 0, 0
10070 };
10071
10072 static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
10073   Opcode_mula_da_hl_Slot_inst_encode, 0, 0
10074 };
10075
10076 static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
10077   Opcode_mula_da_lh_Slot_inst_encode, 0, 0
10078 };
10079
10080 static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
10081   Opcode_mula_da_hh_Slot_inst_encode, 0, 0
10082 };
10083
10084 static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
10085   Opcode_muls_da_ll_Slot_inst_encode, 0, 0
10086 };
10087
10088 static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
10089   Opcode_muls_da_hl_Slot_inst_encode, 0, 0
10090 };
10091
10092 static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
10093   Opcode_muls_da_lh_Slot_inst_encode, 0, 0
10094 };
10095
10096 static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
10097   Opcode_muls_da_hh_Slot_inst_encode, 0, 0
10098 };
10099
10100 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
10101   Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
10102 };
10103
10104 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
10105   Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
10106 };
10107
10108 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
10109   Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
10110 };
10111
10112 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
10113   Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
10114 };
10115
10116 static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
10117   Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
10118 };
10119
10120 static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
10121   Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
10122 };
10123
10124 static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
10125   Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
10126 };
10127
10128 static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
10129   Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
10130 };
10131
10132 static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
10133   Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
10134 };
10135
10136 static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
10137   Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
10138 };
10139
10140 static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
10141   Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
10142 };
10143
10144 static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
10145   Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
10146 };
10147
10148 static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
10149   Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
10150 };
10151
10152 static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
10153   Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
10154 };
10155
10156 static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
10157   Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
10158 };
10159
10160 static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
10161   Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
10162 };
10163
10164 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
10165   Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
10166 };
10167
10168 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
10169   Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
10170 };
10171
10172 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
10173   Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
10174 };
10175
10176 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
10177   Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
10178 };
10179
10180 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
10181   Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
10182 };
10183
10184 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
10185   Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
10186 };
10187
10188 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
10189   Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
10190 };
10191
10192 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
10193   Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
10194 };
10195
10196 static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
10197   Opcode_lddec_Slot_inst_encode, 0, 0
10198 };
10199
10200 static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
10201   Opcode_ldinc_Slot_inst_encode, 0, 0
10202 };
10203
10204 static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
10205   Opcode_rsr_m0_Slot_inst_encode, 0, 0
10206 };
10207
10208 static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
10209   Opcode_wsr_m0_Slot_inst_encode, 0, 0
10210 };
10211
10212 static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
10213   Opcode_xsr_m0_Slot_inst_encode, 0, 0
10214 };
10215
10216 static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
10217   Opcode_rsr_m1_Slot_inst_encode, 0, 0
10218 };
10219
10220 static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
10221   Opcode_wsr_m1_Slot_inst_encode, 0, 0
10222 };
10223
10224 static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
10225   Opcode_xsr_m1_Slot_inst_encode, 0, 0
10226 };
10227
10228 static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
10229   Opcode_rsr_m2_Slot_inst_encode, 0, 0
10230 };
10231
10232 static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
10233   Opcode_wsr_m2_Slot_inst_encode, 0, 0
10234 };
10235
10236 static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
10237   Opcode_xsr_m2_Slot_inst_encode, 0, 0
10238 };
10239
10240 static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
10241   Opcode_rsr_m3_Slot_inst_encode, 0, 0
10242 };
10243
10244 static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
10245   Opcode_wsr_m3_Slot_inst_encode, 0, 0
10246 };
10247
10248 static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
10249   Opcode_xsr_m3_Slot_inst_encode, 0, 0
10250 };
10251
10252 static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
10253   Opcode_rsr_acclo_Slot_inst_encode, 0, 0
10254 };
10255
10256 static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
10257   Opcode_wsr_acclo_Slot_inst_encode, 0, 0
10258 };
10259
10260 static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
10261   Opcode_xsr_acclo_Slot_inst_encode, 0, 0
10262 };
10263
10264 static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
10265   Opcode_rsr_acchi_Slot_inst_encode, 0, 0
10266 };
10267
10268 static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
10269   Opcode_wsr_acchi_Slot_inst_encode, 0, 0
10270 };
10271
10272 static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
10273   Opcode_xsr_acchi_Slot_inst_encode, 0, 0
10274 };
10275
10276 static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
10277   Opcode_rfi_Slot_inst_encode, 0, 0
10278 };
10279
10280 static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
10281   Opcode_waiti_Slot_inst_encode, 0, 0
10282 };
10283
10284 static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
10285   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
10286 };
10287
10288 static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
10289   Opcode_wsr_intset_Slot_inst_encode, 0, 0
10290 };
10291
10292 static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
10293   Opcode_wsr_intclear_Slot_inst_encode, 0, 0
10294 };
10295
10296 static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
10297   Opcode_rsr_intenable_Slot_inst_encode, 0, 0
10298 };
10299
10300 static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
10301   Opcode_wsr_intenable_Slot_inst_encode, 0, 0
10302 };
10303
10304 static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
10305   Opcode_xsr_intenable_Slot_inst_encode, 0, 0
10306 };
10307
10308 static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
10309   Opcode_break_Slot_inst_encode, 0, 0
10310 };
10311
10312 static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
10313   0, 0, Opcode_break_n_Slot_inst16b_encode
10314 };
10315
10316 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
10317   Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
10318 };
10319
10320 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
10321   Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
10322 };
10323
10324 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
10325   Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
10326 };
10327
10328 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
10329   Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
10330 };
10331
10332 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
10333   Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
10334 };
10335
10336 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
10337   Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
10338 };
10339
10340 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
10341   Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
10342 };
10343
10344 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
10345   Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
10346 };
10347
10348 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
10349   Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
10350 };
10351
10352 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
10353   Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
10354 };
10355
10356 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
10357   Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
10358 };
10359
10360 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
10361   Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
10362 };
10363
10364 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
10365   Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
10366 };
10367
10368 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
10369   Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
10370 };
10371
10372 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
10373   Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
10374 };
10375
10376 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
10377   Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
10378 };
10379
10380 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
10381   Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
10382 };
10383
10384 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
10385   Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
10386 };
10387
10388 static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
10389   Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
10390 };
10391
10392 static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
10393   Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
10394 };
10395
10396 static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
10397   Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
10398 };
10399
10400 static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
10401   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
10402 };
10403
10404 static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
10405   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
10406 };
10407
10408 static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
10409   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
10410 };
10411
10412 static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
10413   Opcode_rsr_icount_Slot_inst_encode, 0, 0
10414 };
10415
10416 static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
10417   Opcode_wsr_icount_Slot_inst_encode, 0, 0
10418 };
10419
10420 static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
10421   Opcode_xsr_icount_Slot_inst_encode, 0, 0
10422 };
10423
10424 static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
10425   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
10426 };
10427
10428 static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
10429   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
10430 };
10431
10432 static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
10433   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
10434 };
10435
10436 static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
10437   Opcode_rsr_ddr_Slot_inst_encode, 0, 0
10438 };
10439
10440 static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
10441   Opcode_wsr_ddr_Slot_inst_encode, 0, 0
10442 };
10443
10444 static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
10445   Opcode_xsr_ddr_Slot_inst_encode, 0, 0
10446 };
10447
10448 static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
10449   Opcode_lddr32_p_Slot_inst_encode, 0, 0
10450 };
10451
10452 static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
10453   Opcode_sddr32_p_Slot_inst_encode, 0, 0
10454 };
10455
10456 static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
10457   Opcode_rfdo_Slot_inst_encode, 0, 0
10458 };
10459
10460 static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
10461   Opcode_rfdd_Slot_inst_encode, 0, 0
10462 };
10463
10464 static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
10465   Opcode_wsr_mmid_Slot_inst_encode, 0, 0
10466 };
10467
10468 static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
10469   Opcode_rsr_ccount_Slot_inst_encode, 0, 0
10470 };
10471
10472 static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
10473   Opcode_wsr_ccount_Slot_inst_encode, 0, 0
10474 };
10475
10476 static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
10477   Opcode_xsr_ccount_Slot_inst_encode, 0, 0
10478 };
10479
10480 static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
10481   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
10482 };
10483
10484 static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
10485   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
10486 };
10487
10488 static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
10489   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
10490 };
10491
10492 static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
10493   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
10494 };
10495
10496 static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
10497   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
10498 };
10499
10500 static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
10501   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
10502 };
10503
10504 static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
10505   Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
10506 };
10507
10508 static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
10509   Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
10510 };
10511
10512 static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
10513   Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
10514 };
10515
10516 static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
10517   Opcode_ipf_Slot_inst_encode, 0, 0
10518 };
10519
10520 static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
10521   Opcode_ihi_Slot_inst_encode, 0, 0
10522 };
10523
10524 static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
10525   Opcode_ipfl_Slot_inst_encode, 0, 0
10526 };
10527
10528 static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
10529   Opcode_ihu_Slot_inst_encode, 0, 0
10530 };
10531
10532 static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
10533   Opcode_iiu_Slot_inst_encode, 0, 0
10534 };
10535
10536 static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
10537   Opcode_iii_Slot_inst_encode, 0, 0
10538 };
10539
10540 static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
10541   Opcode_lict_Slot_inst_encode, 0, 0
10542 };
10543
10544 static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
10545   Opcode_licw_Slot_inst_encode, 0, 0
10546 };
10547
10548 static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
10549   Opcode_sict_Slot_inst_encode, 0, 0
10550 };
10551
10552 static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
10553   Opcode_sicw_Slot_inst_encode, 0, 0
10554 };
10555
10556 static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
10557   Opcode_dhwb_Slot_inst_encode, 0, 0
10558 };
10559
10560 static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
10561   Opcode_dhwbi_Slot_inst_encode, 0, 0
10562 };
10563
10564 static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = {
10565   Opcode_diwbui_p_Slot_inst_encode, 0, 0
10566 };
10567
10568 static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
10569   Opcode_diwb_Slot_inst_encode, 0, 0
10570 };
10571
10572 static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
10573   Opcode_diwbi_Slot_inst_encode, 0, 0
10574 };
10575
10576 static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
10577   Opcode_dhi_Slot_inst_encode, 0, 0
10578 };
10579
10580 static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
10581   Opcode_dii_Slot_inst_encode, 0, 0
10582 };
10583
10584 static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
10585   Opcode_dpfr_Slot_inst_encode, 0, 0
10586 };
10587
10588 static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
10589   Opcode_dpfw_Slot_inst_encode, 0, 0
10590 };
10591
10592 static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
10593   Opcode_dpfro_Slot_inst_encode, 0, 0
10594 };
10595
10596 static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
10597   Opcode_dpfwo_Slot_inst_encode, 0, 0
10598 };
10599
10600 static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
10601   Opcode_dpfl_Slot_inst_encode, 0, 0
10602 };
10603
10604 static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
10605   Opcode_dhu_Slot_inst_encode, 0, 0
10606 };
10607
10608 static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
10609   Opcode_diu_Slot_inst_encode, 0, 0
10610 };
10611
10612 static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
10613   Opcode_sdct_Slot_inst_encode, 0, 0
10614 };
10615
10616 static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
10617   Opcode_ldct_Slot_inst_encode, 0, 0
10618 };
10619
10620 static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
10621   Opcode_idtlb_Slot_inst_encode, 0, 0
10622 };
10623
10624 static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
10625   Opcode_pdtlb_Slot_inst_encode, 0, 0
10626 };
10627
10628 static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
10629   Opcode_rdtlb0_Slot_inst_encode, 0, 0
10630 };
10631
10632 static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
10633   Opcode_rdtlb1_Slot_inst_encode, 0, 0
10634 };
10635
10636 static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
10637   Opcode_wdtlb_Slot_inst_encode, 0, 0
10638 };
10639
10640 static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
10641   Opcode_iitlb_Slot_inst_encode, 0, 0
10642 };
10643
10644 static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
10645   Opcode_pitlb_Slot_inst_encode, 0, 0
10646 };
10647
10648 static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
10649   Opcode_ritlb0_Slot_inst_encode, 0, 0
10650 };
10651
10652 static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
10653   Opcode_ritlb1_Slot_inst_encode, 0, 0
10654 };
10655
10656 static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
10657   Opcode_witlb_Slot_inst_encode, 0, 0
10658 };
10659
10660 static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
10661   Opcode_clamps_Slot_inst_encode, 0, 0
10662 };
10663
10664 static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
10665   Opcode_min_Slot_inst_encode, 0, 0
10666 };
10667
10668 static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
10669   Opcode_max_Slot_inst_encode, 0, 0
10670 };
10671
10672 static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
10673   Opcode_minu_Slot_inst_encode, 0, 0
10674 };
10675
10676 static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
10677   Opcode_maxu_Slot_inst_encode, 0, 0
10678 };
10679
10680 static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
10681   Opcode_nsa_Slot_inst_encode, 0, 0
10682 };
10683
10684 static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
10685   Opcode_nsau_Slot_inst_encode, 0, 0
10686 };
10687
10688 static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
10689   Opcode_sext_Slot_inst_encode, 0, 0
10690 };
10691
10692 static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
10693   Opcode_l32ai_Slot_inst_encode, 0, 0
10694 };
10695
10696 static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
10697   Opcode_s32ri_Slot_inst_encode, 0, 0
10698 };
10699
10700 static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
10701   Opcode_s32c1i_Slot_inst_encode, 0, 0
10702 };
10703
10704 static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
10705   Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
10706 };
10707
10708 static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
10709   Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
10710 };
10711
10712 static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
10713   Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
10714 };
10715
10716 static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
10717   Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
10718 };
10719
10720 static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
10721   Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
10722 };
10723
10724 static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
10725   Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
10726 };
10727
10728 static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
10729   Opcode_quou_Slot_inst_encode, 0, 0
10730 };
10731
10732 static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
10733   Opcode_quos_Slot_inst_encode, 0, 0
10734 };
10735
10736 static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
10737   Opcode_remu_Slot_inst_encode, 0, 0
10738 };
10739
10740 static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
10741   Opcode_rems_Slot_inst_encode, 0, 0
10742 };
10743
10744 static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
10745   Opcode_rer_Slot_inst_encode, 0, 0
10746 };
10747
10748 static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
10749   Opcode_wer_Slot_inst_encode, 0, 0
10750 };
10751
10752 static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
10753   Opcode_rur_expstate_Slot_inst_encode, 0, 0
10754 };
10755
10756 static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
10757   Opcode_wur_expstate_Slot_inst_encode, 0, 0
10758 };
10759
10760 static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
10761   Opcode_read_impwire_Slot_inst_encode, 0, 0
10762 };
10763
10764 static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
10765   Opcode_setb_expstate_Slot_inst_encode, 0, 0
10766 };
10767
10768 static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
10769   Opcode_clrb_expstate_Slot_inst_encode, 0, 0
10770 };
10771
10772 static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
10773   Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
10774 };
10775
10776
10777
10778
10779 \f
10780 /* Opcode table.  */
10781
10782 static xtensa_opcode_internal opcodes[] = {
10783   { "excw", ICLASS_xt_iclass_excw,
10784     0,
10785     Opcode_excw_encode_fns, 0, 0 },
10786   { "rfe", ICLASS_xt_iclass_rfe,
10787     XTENSA_OPCODE_IS_JUMP,
10788     Opcode_rfe_encode_fns, 0, 0 },
10789   { "rfde", ICLASS_xt_iclass_rfde,
10790     XTENSA_OPCODE_IS_JUMP,
10791     Opcode_rfde_encode_fns, 0, 0 },
10792   { "syscall", ICLASS_xt_iclass_syscall,
10793     0,
10794     Opcode_syscall_encode_fns, 0, 0 },
10795   { "call12", ICLASS_xt_iclass_call12,
10796     XTENSA_OPCODE_IS_CALL,
10797     Opcode_call12_encode_fns, 0, 0 },
10798   { "call8", ICLASS_xt_iclass_call8,
10799     XTENSA_OPCODE_IS_CALL,
10800     Opcode_call8_encode_fns, 0, 0 },
10801   { "call4", ICLASS_xt_iclass_call4,
10802     XTENSA_OPCODE_IS_CALL,
10803     Opcode_call4_encode_fns, 0, 0 },
10804   { "callx12", ICLASS_xt_iclass_callx12,
10805     XTENSA_OPCODE_IS_CALL,
10806     Opcode_callx12_encode_fns, 0, 0 },
10807   { "callx8", ICLASS_xt_iclass_callx8,
10808     XTENSA_OPCODE_IS_CALL,
10809     Opcode_callx8_encode_fns, 0, 0 },
10810   { "callx4", ICLASS_xt_iclass_callx4,
10811     XTENSA_OPCODE_IS_CALL,
10812     Opcode_callx4_encode_fns, 0, 0 },
10813   { "entry", ICLASS_xt_iclass_entry,
10814     0,
10815     Opcode_entry_encode_fns, 0, 0 },
10816   { "movsp", ICLASS_xt_iclass_movsp,
10817     0,
10818     Opcode_movsp_encode_fns, 0, 0 },
10819   { "rotw", ICLASS_xt_iclass_rotw,
10820     0,
10821     Opcode_rotw_encode_fns, 0, 0 },
10822   { "retw", ICLASS_xt_iclass_retw,
10823     XTENSA_OPCODE_IS_JUMP,
10824     Opcode_retw_encode_fns, 0, 0 },
10825   { "retw.n", ICLASS_xt_iclass_retw,
10826     XTENSA_OPCODE_IS_JUMP,
10827     Opcode_retw_n_encode_fns, 0, 0 },
10828   { "rfwo", ICLASS_xt_iclass_rfwou,
10829     XTENSA_OPCODE_IS_JUMP,
10830     Opcode_rfwo_encode_fns, 0, 0 },
10831   { "rfwu", ICLASS_xt_iclass_rfwou,
10832     XTENSA_OPCODE_IS_JUMP,
10833     Opcode_rfwu_encode_fns, 0, 0 },
10834   { "l32e", ICLASS_xt_iclass_l32e,
10835     0,
10836     Opcode_l32e_encode_fns, 0, 0 },
10837   { "s32e", ICLASS_xt_iclass_s32e,
10838     0,
10839     Opcode_s32e_encode_fns, 0, 0 },
10840   { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
10841     0,
10842     Opcode_rsr_windowbase_encode_fns, 0, 0 },
10843   { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
10844     0,
10845     Opcode_wsr_windowbase_encode_fns, 0, 0 },
10846   { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
10847     0,
10848     Opcode_xsr_windowbase_encode_fns, 0, 0 },
10849   { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
10850     0,
10851     Opcode_rsr_windowstart_encode_fns, 0, 0 },
10852   { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
10853     0,
10854     Opcode_wsr_windowstart_encode_fns, 0, 0 },
10855   { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
10856     0,
10857     Opcode_xsr_windowstart_encode_fns, 0, 0 },
10858   { "add.n", ICLASS_xt_iclass_add_n,
10859     0,
10860     Opcode_add_n_encode_fns, 0, 0 },
10861   { "addi.n", ICLASS_xt_iclass_addi_n,
10862     0,
10863     Opcode_addi_n_encode_fns, 0, 0 },
10864   { "beqz.n", ICLASS_xt_iclass_bz6,
10865     XTENSA_OPCODE_IS_BRANCH,
10866     Opcode_beqz_n_encode_fns, 0, 0 },
10867   { "bnez.n", ICLASS_xt_iclass_bz6,
10868     XTENSA_OPCODE_IS_BRANCH,
10869     Opcode_bnez_n_encode_fns, 0, 0 },
10870   { "ill.n", ICLASS_xt_iclass_ill_n,
10871     0,
10872     Opcode_ill_n_encode_fns, 0, 0 },
10873   { "l32i.n", ICLASS_xt_iclass_loadi4,
10874     0,
10875     Opcode_l32i_n_encode_fns, 0, 0 },
10876   { "mov.n", ICLASS_xt_iclass_mov_n,
10877     0,
10878     Opcode_mov_n_encode_fns, 0, 0 },
10879   { "movi.n", ICLASS_xt_iclass_movi_n,
10880     0,
10881     Opcode_movi_n_encode_fns, 0, 0 },
10882   { "nop.n", ICLASS_xt_iclass_nopn,
10883     0,
10884     Opcode_nop_n_encode_fns, 0, 0 },
10885   { "ret.n", ICLASS_xt_iclass_retn,
10886     XTENSA_OPCODE_IS_JUMP,
10887     Opcode_ret_n_encode_fns, 0, 0 },
10888   { "s32i.n", ICLASS_xt_iclass_storei4,
10889     0,
10890     Opcode_s32i_n_encode_fns, 0, 0 },
10891   { "addi", ICLASS_xt_iclass_addi,
10892     0,
10893     Opcode_addi_encode_fns, 0, 0 },
10894   { "addmi", ICLASS_xt_iclass_addmi,
10895     0,
10896     Opcode_addmi_encode_fns, 0, 0 },
10897   { "add", ICLASS_xt_iclass_addsub,
10898     0,
10899     Opcode_add_encode_fns, 0, 0 },
10900   { "sub", ICLASS_xt_iclass_addsub,
10901     0,
10902     Opcode_sub_encode_fns, 0, 0 },
10903   { "addx2", ICLASS_xt_iclass_addsub,
10904     0,
10905     Opcode_addx2_encode_fns, 0, 0 },
10906   { "addx4", ICLASS_xt_iclass_addsub,
10907     0,
10908     Opcode_addx4_encode_fns, 0, 0 },
10909   { "addx8", ICLASS_xt_iclass_addsub,
10910     0,
10911     Opcode_addx8_encode_fns, 0, 0 },
10912   { "subx2", ICLASS_xt_iclass_addsub,
10913     0,
10914     Opcode_subx2_encode_fns, 0, 0 },
10915   { "subx4", ICLASS_xt_iclass_addsub,
10916     0,
10917     Opcode_subx4_encode_fns, 0, 0 },
10918   { "subx8", ICLASS_xt_iclass_addsub,
10919     0,
10920     Opcode_subx8_encode_fns, 0, 0 },
10921   { "and", ICLASS_xt_iclass_bit,
10922     0,
10923     Opcode_and_encode_fns, 0, 0 },
10924   { "or", ICLASS_xt_iclass_bit,
10925     0,
10926     Opcode_or_encode_fns, 0, 0 },
10927   { "xor", ICLASS_xt_iclass_bit,
10928     0,
10929     Opcode_xor_encode_fns, 0, 0 },
10930   { "beqi", ICLASS_xt_iclass_bsi8,
10931     XTENSA_OPCODE_IS_BRANCH,
10932     Opcode_beqi_encode_fns, 0, 0 },
10933   { "bnei", ICLASS_xt_iclass_bsi8,
10934     XTENSA_OPCODE_IS_BRANCH,
10935     Opcode_bnei_encode_fns, 0, 0 },
10936   { "bgei", ICLASS_xt_iclass_bsi8,
10937     XTENSA_OPCODE_IS_BRANCH,
10938     Opcode_bgei_encode_fns, 0, 0 },
10939   { "blti", ICLASS_xt_iclass_bsi8,
10940     XTENSA_OPCODE_IS_BRANCH,
10941     Opcode_blti_encode_fns, 0, 0 },
10942   { "bbci", ICLASS_xt_iclass_bsi8b,
10943     XTENSA_OPCODE_IS_BRANCH,
10944     Opcode_bbci_encode_fns, 0, 0 },
10945   { "bbsi", ICLASS_xt_iclass_bsi8b,
10946     XTENSA_OPCODE_IS_BRANCH,
10947     Opcode_bbsi_encode_fns, 0, 0 },
10948   { "bgeui", ICLASS_xt_iclass_bsi8u,
10949     XTENSA_OPCODE_IS_BRANCH,
10950     Opcode_bgeui_encode_fns, 0, 0 },
10951   { "bltui", ICLASS_xt_iclass_bsi8u,
10952     XTENSA_OPCODE_IS_BRANCH,
10953     Opcode_bltui_encode_fns, 0, 0 },
10954   { "beq", ICLASS_xt_iclass_bst8,
10955     XTENSA_OPCODE_IS_BRANCH,
10956     Opcode_beq_encode_fns, 0, 0 },
10957   { "bne", ICLASS_xt_iclass_bst8,
10958     XTENSA_OPCODE_IS_BRANCH,
10959     Opcode_bne_encode_fns, 0, 0 },
10960   { "bge", ICLASS_xt_iclass_bst8,
10961     XTENSA_OPCODE_IS_BRANCH,
10962     Opcode_bge_encode_fns, 0, 0 },
10963   { "blt", ICLASS_xt_iclass_bst8,
10964     XTENSA_OPCODE_IS_BRANCH,
10965     Opcode_blt_encode_fns, 0, 0 },
10966   { "bgeu", ICLASS_xt_iclass_bst8,
10967     XTENSA_OPCODE_IS_BRANCH,
10968     Opcode_bgeu_encode_fns, 0, 0 },
10969   { "bltu", ICLASS_xt_iclass_bst8,
10970     XTENSA_OPCODE_IS_BRANCH,
10971     Opcode_bltu_encode_fns, 0, 0 },
10972   { "bany", ICLASS_xt_iclass_bst8,
10973     XTENSA_OPCODE_IS_BRANCH,
10974     Opcode_bany_encode_fns, 0, 0 },
10975   { "bnone", ICLASS_xt_iclass_bst8,
10976     XTENSA_OPCODE_IS_BRANCH,
10977     Opcode_bnone_encode_fns, 0, 0 },
10978   { "ball", ICLASS_xt_iclass_bst8,
10979     XTENSA_OPCODE_IS_BRANCH,
10980     Opcode_ball_encode_fns, 0, 0 },
10981   { "bnall", ICLASS_xt_iclass_bst8,
10982     XTENSA_OPCODE_IS_BRANCH,
10983     Opcode_bnall_encode_fns, 0, 0 },
10984   { "bbc", ICLASS_xt_iclass_bst8,
10985     XTENSA_OPCODE_IS_BRANCH,
10986     Opcode_bbc_encode_fns, 0, 0 },
10987   { "bbs", ICLASS_xt_iclass_bst8,
10988     XTENSA_OPCODE_IS_BRANCH,
10989     Opcode_bbs_encode_fns, 0, 0 },
10990   { "beqz", ICLASS_xt_iclass_bsz12,
10991     XTENSA_OPCODE_IS_BRANCH,
10992     Opcode_beqz_encode_fns, 0, 0 },
10993   { "bnez", ICLASS_xt_iclass_bsz12,
10994     XTENSA_OPCODE_IS_BRANCH,
10995     Opcode_bnez_encode_fns, 0, 0 },
10996   { "bgez", ICLASS_xt_iclass_bsz12,
10997     XTENSA_OPCODE_IS_BRANCH,
10998     Opcode_bgez_encode_fns, 0, 0 },
10999   { "bltz", ICLASS_xt_iclass_bsz12,
11000     XTENSA_OPCODE_IS_BRANCH,
11001     Opcode_bltz_encode_fns, 0, 0 },
11002   { "call0", ICLASS_xt_iclass_call0,
11003     XTENSA_OPCODE_IS_CALL,
11004     Opcode_call0_encode_fns, 0, 0 },
11005   { "callx0", ICLASS_xt_iclass_callx0,
11006     XTENSA_OPCODE_IS_CALL,
11007     Opcode_callx0_encode_fns, 0, 0 },
11008   { "extui", ICLASS_xt_iclass_exti,
11009     0,
11010     Opcode_extui_encode_fns, 0, 0 },
11011   { "ill", ICLASS_xt_iclass_ill,
11012     0,
11013     Opcode_ill_encode_fns, 0, 0 },
11014   { "j", ICLASS_xt_iclass_jump,
11015     XTENSA_OPCODE_IS_JUMP,
11016     Opcode_j_encode_fns, 0, 0 },
11017   { "jx", ICLASS_xt_iclass_jumpx,
11018     XTENSA_OPCODE_IS_JUMP,
11019     Opcode_jx_encode_fns, 0, 0 },
11020   { "l16ui", ICLASS_xt_iclass_l16ui,
11021     0,
11022     Opcode_l16ui_encode_fns, 0, 0 },
11023   { "l16si", ICLASS_xt_iclass_l16si,
11024     0,
11025     Opcode_l16si_encode_fns, 0, 0 },
11026   { "l32i", ICLASS_xt_iclass_l32i,
11027     0,
11028     Opcode_l32i_encode_fns, 0, 0 },
11029   { "l32r", ICLASS_xt_iclass_l32r,
11030     0,
11031     Opcode_l32r_encode_fns, 0, 0 },
11032   { "l8ui", ICLASS_xt_iclass_l8i,
11033     0,
11034     Opcode_l8ui_encode_fns, 0, 0 },
11035   { "loop", ICLASS_xt_iclass_loop,
11036     XTENSA_OPCODE_IS_LOOP,
11037     Opcode_loop_encode_fns, 0, 0 },
11038   { "loopnez", ICLASS_xt_iclass_loopz,
11039     XTENSA_OPCODE_IS_LOOP,
11040     Opcode_loopnez_encode_fns, 0, 0 },
11041   { "loopgtz", ICLASS_xt_iclass_loopz,
11042     XTENSA_OPCODE_IS_LOOP,
11043     Opcode_loopgtz_encode_fns, 0, 0 },
11044   { "movi", ICLASS_xt_iclass_movi,
11045     0,
11046     Opcode_movi_encode_fns, 0, 0 },
11047   { "moveqz", ICLASS_xt_iclass_movz,
11048     0,
11049     Opcode_moveqz_encode_fns, 0, 0 },
11050   { "movnez", ICLASS_xt_iclass_movz,
11051     0,
11052     Opcode_movnez_encode_fns, 0, 0 },
11053   { "movltz", ICLASS_xt_iclass_movz,
11054     0,
11055     Opcode_movltz_encode_fns, 0, 0 },
11056   { "movgez", ICLASS_xt_iclass_movz,
11057     0,
11058     Opcode_movgez_encode_fns, 0, 0 },
11059   { "neg", ICLASS_xt_iclass_neg,
11060     0,
11061     Opcode_neg_encode_fns, 0, 0 },
11062   { "abs", ICLASS_xt_iclass_neg,
11063     0,
11064     Opcode_abs_encode_fns, 0, 0 },
11065   { "nop", ICLASS_xt_iclass_nop,
11066     0,
11067     Opcode_nop_encode_fns, 0, 0 },
11068   { "ret", ICLASS_xt_iclass_return,
11069     XTENSA_OPCODE_IS_JUMP,
11070     Opcode_ret_encode_fns, 0, 0 },
11071   { "simcall", ICLASS_xt_iclass_simcall,
11072     0,
11073     Opcode_simcall_encode_fns, 0, 0 },
11074   { "s16i", ICLASS_xt_iclass_s16i,
11075     0,
11076     Opcode_s16i_encode_fns, 0, 0 },
11077   { "s32i", ICLASS_xt_iclass_s32i,
11078     0,
11079     Opcode_s32i_encode_fns, 0, 0 },
11080   { "s32nb", ICLASS_xt_iclass_s32nb,
11081     0,
11082     Opcode_s32nb_encode_fns, 0, 0 },
11083   { "s8i", ICLASS_xt_iclass_s8i,
11084     0,
11085     Opcode_s8i_encode_fns, 0, 0 },
11086   { "ssr", ICLASS_xt_iclass_sar,
11087     0,
11088     Opcode_ssr_encode_fns, 0, 0 },
11089   { "ssl", ICLASS_xt_iclass_sar,
11090     0,
11091     Opcode_ssl_encode_fns, 0, 0 },
11092   { "ssa8l", ICLASS_xt_iclass_sar,
11093     0,
11094     Opcode_ssa8l_encode_fns, 0, 0 },
11095   { "ssa8b", ICLASS_xt_iclass_sar,
11096     0,
11097     Opcode_ssa8b_encode_fns, 0, 0 },
11098   { "ssai", ICLASS_xt_iclass_sari,
11099     0,
11100     Opcode_ssai_encode_fns, 0, 0 },
11101   { "sll", ICLASS_xt_iclass_shifts,
11102     0,
11103     Opcode_sll_encode_fns, 0, 0 },
11104   { "src", ICLASS_xt_iclass_shiftst,
11105     0,
11106     Opcode_src_encode_fns, 0, 0 },
11107   { "srl", ICLASS_xt_iclass_shiftt,
11108     0,
11109     Opcode_srl_encode_fns, 0, 0 },
11110   { "sra", ICLASS_xt_iclass_shiftt,
11111     0,
11112     Opcode_sra_encode_fns, 0, 0 },
11113   { "slli", ICLASS_xt_iclass_slli,
11114     0,
11115     Opcode_slli_encode_fns, 0, 0 },
11116   { "srai", ICLASS_xt_iclass_srai,
11117     0,
11118     Opcode_srai_encode_fns, 0, 0 },
11119   { "srli", ICLASS_xt_iclass_srli,
11120     0,
11121     Opcode_srli_encode_fns, 0, 0 },
11122   { "memw", ICLASS_xt_iclass_memw,
11123     0,
11124     Opcode_memw_encode_fns, 0, 0 },
11125   { "extw", ICLASS_xt_iclass_extw,
11126     0,
11127     Opcode_extw_encode_fns, 0, 0 },
11128   { "isync", ICLASS_xt_iclass_isync,
11129     0,
11130     Opcode_isync_encode_fns, 0, 0 },
11131   { "rsync", ICLASS_xt_iclass_sync,
11132     0,
11133     Opcode_rsync_encode_fns, 0, 0 },
11134   { "esync", ICLASS_xt_iclass_sync,
11135     0,
11136     Opcode_esync_encode_fns, 0, 0 },
11137   { "dsync", ICLASS_xt_iclass_sync,
11138     0,
11139     Opcode_dsync_encode_fns, 0, 0 },
11140   { "rsil", ICLASS_xt_iclass_rsil,
11141     0,
11142     Opcode_rsil_encode_fns, 0, 0 },
11143   { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
11144     0,
11145     Opcode_rsr_lend_encode_fns, 0, 0 },
11146   { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
11147     0,
11148     Opcode_wsr_lend_encode_fns, 0, 0 },
11149   { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
11150     0,
11151     Opcode_xsr_lend_encode_fns, 0, 0 },
11152   { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
11153     0,
11154     Opcode_rsr_lcount_encode_fns, 0, 0 },
11155   { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
11156     0,
11157     Opcode_wsr_lcount_encode_fns, 0, 0 },
11158   { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
11159     0,
11160     Opcode_xsr_lcount_encode_fns, 0, 0 },
11161   { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
11162     0,
11163     Opcode_rsr_lbeg_encode_fns, 0, 0 },
11164   { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
11165     0,
11166     Opcode_wsr_lbeg_encode_fns, 0, 0 },
11167   { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
11168     0,
11169     Opcode_xsr_lbeg_encode_fns, 0, 0 },
11170   { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
11171     0,
11172     Opcode_rsr_sar_encode_fns, 0, 0 },
11173   { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
11174     0,
11175     Opcode_wsr_sar_encode_fns, 0, 0 },
11176   { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
11177     0,
11178     Opcode_xsr_sar_encode_fns, 0, 0 },
11179   { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
11180     0,
11181     Opcode_rsr_memctl_encode_fns, 0, 0 },
11182   { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
11183     0,
11184     Opcode_wsr_memctl_encode_fns, 0, 0 },
11185   { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
11186     0,
11187     Opcode_xsr_memctl_encode_fns, 0, 0 },
11188   { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
11189     0,
11190     Opcode_rsr_litbase_encode_fns, 0, 0 },
11191   { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
11192     0,
11193     Opcode_wsr_litbase_encode_fns, 0, 0 },
11194   { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
11195     0,
11196     Opcode_xsr_litbase_encode_fns, 0, 0 },
11197   { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
11198     0,
11199     Opcode_rsr_configid0_encode_fns, 0, 0 },
11200   { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
11201     0,
11202     Opcode_wsr_configid0_encode_fns, 0, 0 },
11203   { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
11204     0,
11205     Opcode_rsr_configid1_encode_fns, 0, 0 },
11206   { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
11207     0,
11208     Opcode_rsr_ps_encode_fns, 0, 0 },
11209   { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
11210     0,
11211     Opcode_wsr_ps_encode_fns, 0, 0 },
11212   { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
11213     0,
11214     Opcode_xsr_ps_encode_fns, 0, 0 },
11215   { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
11216     0,
11217     Opcode_rsr_epc1_encode_fns, 0, 0 },
11218   { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
11219     0,
11220     Opcode_wsr_epc1_encode_fns, 0, 0 },
11221   { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
11222     0,
11223     Opcode_xsr_epc1_encode_fns, 0, 0 },
11224   { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
11225     0,
11226     Opcode_rsr_excsave1_encode_fns, 0, 0 },
11227   { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
11228     0,
11229     Opcode_wsr_excsave1_encode_fns, 0, 0 },
11230   { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
11231     0,
11232     Opcode_xsr_excsave1_encode_fns, 0, 0 },
11233   { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
11234     0,
11235     Opcode_rsr_epc2_encode_fns, 0, 0 },
11236   { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
11237     0,
11238     Opcode_wsr_epc2_encode_fns, 0, 0 },
11239   { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
11240     0,
11241     Opcode_xsr_epc2_encode_fns, 0, 0 },
11242   { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
11243     0,
11244     Opcode_rsr_excsave2_encode_fns, 0, 0 },
11245   { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
11246     0,
11247     Opcode_wsr_excsave2_encode_fns, 0, 0 },
11248   { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
11249     0,
11250     Opcode_xsr_excsave2_encode_fns, 0, 0 },
11251   { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
11252     0,
11253     Opcode_rsr_epc3_encode_fns, 0, 0 },
11254   { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
11255     0,
11256     Opcode_wsr_epc3_encode_fns, 0, 0 },
11257   { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
11258     0,
11259     Opcode_xsr_epc3_encode_fns, 0, 0 },
11260   { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
11261     0,
11262     Opcode_rsr_excsave3_encode_fns, 0, 0 },
11263   { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
11264     0,
11265     Opcode_wsr_excsave3_encode_fns, 0, 0 },
11266   { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
11267     0,
11268     Opcode_xsr_excsave3_encode_fns, 0, 0 },
11269   { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
11270     0,
11271     Opcode_rsr_epc4_encode_fns, 0, 0 },
11272   { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
11273     0,
11274     Opcode_wsr_epc4_encode_fns, 0, 0 },
11275   { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
11276     0,
11277     Opcode_xsr_epc4_encode_fns, 0, 0 },
11278   { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
11279     0,
11280     Opcode_rsr_excsave4_encode_fns, 0, 0 },
11281   { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
11282     0,
11283     Opcode_wsr_excsave4_encode_fns, 0, 0 },
11284   { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
11285     0,
11286     Opcode_xsr_excsave4_encode_fns, 0, 0 },
11287   { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
11288     0,
11289     Opcode_rsr_epc5_encode_fns, 0, 0 },
11290   { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
11291     0,
11292     Opcode_wsr_epc5_encode_fns, 0, 0 },
11293   { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
11294     0,
11295     Opcode_xsr_epc5_encode_fns, 0, 0 },
11296   { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
11297     0,
11298     Opcode_rsr_excsave5_encode_fns, 0, 0 },
11299   { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
11300     0,
11301     Opcode_wsr_excsave5_encode_fns, 0, 0 },
11302   { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
11303     0,
11304     Opcode_xsr_excsave5_encode_fns, 0, 0 },
11305   { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
11306     0,
11307     Opcode_rsr_epc6_encode_fns, 0, 0 },
11308   { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
11309     0,
11310     Opcode_wsr_epc6_encode_fns, 0, 0 },
11311   { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
11312     0,
11313     Opcode_xsr_epc6_encode_fns, 0, 0 },
11314   { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
11315     0,
11316     Opcode_rsr_excsave6_encode_fns, 0, 0 },
11317   { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
11318     0,
11319     Opcode_wsr_excsave6_encode_fns, 0, 0 },
11320   { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
11321     0,
11322     Opcode_xsr_excsave6_encode_fns, 0, 0 },
11323   { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
11324     0,
11325     Opcode_rsr_epc7_encode_fns, 0, 0 },
11326   { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
11327     0,
11328     Opcode_wsr_epc7_encode_fns, 0, 0 },
11329   { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
11330     0,
11331     Opcode_xsr_epc7_encode_fns, 0, 0 },
11332   { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
11333     0,
11334     Opcode_rsr_excsave7_encode_fns, 0, 0 },
11335   { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
11336     0,
11337     Opcode_wsr_excsave7_encode_fns, 0, 0 },
11338   { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
11339     0,
11340     Opcode_xsr_excsave7_encode_fns, 0, 0 },
11341   { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
11342     0,
11343     Opcode_rsr_eps2_encode_fns, 0, 0 },
11344   { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
11345     0,
11346     Opcode_wsr_eps2_encode_fns, 0, 0 },
11347   { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
11348     0,
11349     Opcode_xsr_eps2_encode_fns, 0, 0 },
11350   { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
11351     0,
11352     Opcode_rsr_eps3_encode_fns, 0, 0 },
11353   { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
11354     0,
11355     Opcode_wsr_eps3_encode_fns, 0, 0 },
11356   { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
11357     0,
11358     Opcode_xsr_eps3_encode_fns, 0, 0 },
11359   { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
11360     0,
11361     Opcode_rsr_eps4_encode_fns, 0, 0 },
11362   { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
11363     0,
11364     Opcode_wsr_eps4_encode_fns, 0, 0 },
11365   { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
11366     0,
11367     Opcode_xsr_eps4_encode_fns, 0, 0 },
11368   { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
11369     0,
11370     Opcode_rsr_eps5_encode_fns, 0, 0 },
11371   { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
11372     0,
11373     Opcode_wsr_eps5_encode_fns, 0, 0 },
11374   { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
11375     0,
11376     Opcode_xsr_eps5_encode_fns, 0, 0 },
11377   { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
11378     0,
11379     Opcode_rsr_eps6_encode_fns, 0, 0 },
11380   { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
11381     0,
11382     Opcode_wsr_eps6_encode_fns, 0, 0 },
11383   { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
11384     0,
11385     Opcode_xsr_eps6_encode_fns, 0, 0 },
11386   { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
11387     0,
11388     Opcode_rsr_eps7_encode_fns, 0, 0 },
11389   { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
11390     0,
11391     Opcode_wsr_eps7_encode_fns, 0, 0 },
11392   { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
11393     0,
11394     Opcode_xsr_eps7_encode_fns, 0, 0 },
11395   { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
11396     0,
11397     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
11398   { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
11399     0,
11400     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
11401   { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
11402     0,
11403     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
11404   { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
11405     0,
11406     Opcode_rsr_depc_encode_fns, 0, 0 },
11407   { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
11408     0,
11409     Opcode_wsr_depc_encode_fns, 0, 0 },
11410   { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
11411     0,
11412     Opcode_xsr_depc_encode_fns, 0, 0 },
11413   { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
11414     0,
11415     Opcode_rsr_exccause_encode_fns, 0, 0 },
11416   { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
11417     0,
11418     Opcode_wsr_exccause_encode_fns, 0, 0 },
11419   { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
11420     0,
11421     Opcode_xsr_exccause_encode_fns, 0, 0 },
11422   { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
11423     0,
11424     Opcode_rsr_misc0_encode_fns, 0, 0 },
11425   { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
11426     0,
11427     Opcode_wsr_misc0_encode_fns, 0, 0 },
11428   { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
11429     0,
11430     Opcode_xsr_misc0_encode_fns, 0, 0 },
11431   { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
11432     0,
11433     Opcode_rsr_misc1_encode_fns, 0, 0 },
11434   { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
11435     0,
11436     Opcode_wsr_misc1_encode_fns, 0, 0 },
11437   { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
11438     0,
11439     Opcode_xsr_misc1_encode_fns, 0, 0 },
11440   { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
11441     0,
11442     Opcode_rsr_prid_encode_fns, 0, 0 },
11443   { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
11444     0,
11445     Opcode_rsr_vecbase_encode_fns, 0, 0 },
11446   { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
11447     0,
11448     Opcode_wsr_vecbase_encode_fns, 0, 0 },
11449   { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
11450     0,
11451     Opcode_xsr_vecbase_encode_fns, 0, 0 },
11452   { "mul16u", ICLASS_xt_mul16,
11453     0,
11454     Opcode_mul16u_encode_fns, 0, 0 },
11455   { "mul16s", ICLASS_xt_mul16,
11456     0,
11457     Opcode_mul16s_encode_fns, 0, 0 },
11458   { "mull", ICLASS_xt_mul32,
11459     0,
11460     Opcode_mull_encode_fns, 0, 0 },
11461   { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
11462     0,
11463     Opcode_mul_aa_ll_encode_fns, 0, 0 },
11464   { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
11465     0,
11466     Opcode_mul_aa_hl_encode_fns, 0, 0 },
11467   { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
11468     0,
11469     Opcode_mul_aa_lh_encode_fns, 0, 0 },
11470   { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
11471     0,
11472     Opcode_mul_aa_hh_encode_fns, 0, 0 },
11473   { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
11474     0,
11475     Opcode_umul_aa_ll_encode_fns, 0, 0 },
11476   { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
11477     0,
11478     Opcode_umul_aa_hl_encode_fns, 0, 0 },
11479   { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
11480     0,
11481     Opcode_umul_aa_lh_encode_fns, 0, 0 },
11482   { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
11483     0,
11484     Opcode_umul_aa_hh_encode_fns, 0, 0 },
11485   { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
11486     0,
11487     Opcode_mul_ad_ll_encode_fns, 0, 0 },
11488   { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
11489     0,
11490     Opcode_mul_ad_hl_encode_fns, 0, 0 },
11491   { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
11492     0,
11493     Opcode_mul_ad_lh_encode_fns, 0, 0 },
11494   { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
11495     0,
11496     Opcode_mul_ad_hh_encode_fns, 0, 0 },
11497   { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
11498     0,
11499     Opcode_mul_da_ll_encode_fns, 0, 0 },
11500   { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
11501     0,
11502     Opcode_mul_da_hl_encode_fns, 0, 0 },
11503   { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
11504     0,
11505     Opcode_mul_da_lh_encode_fns, 0, 0 },
11506   { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
11507     0,
11508     Opcode_mul_da_hh_encode_fns, 0, 0 },
11509   { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
11510     0,
11511     Opcode_mul_dd_ll_encode_fns, 0, 0 },
11512   { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
11513     0,
11514     Opcode_mul_dd_hl_encode_fns, 0, 0 },
11515   { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
11516     0,
11517     Opcode_mul_dd_lh_encode_fns, 0, 0 },
11518   { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
11519     0,
11520     Opcode_mul_dd_hh_encode_fns, 0, 0 },
11521   { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
11522     0,
11523     Opcode_mula_aa_ll_encode_fns, 0, 0 },
11524   { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
11525     0,
11526     Opcode_mula_aa_hl_encode_fns, 0, 0 },
11527   { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
11528     0,
11529     Opcode_mula_aa_lh_encode_fns, 0, 0 },
11530   { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
11531     0,
11532     Opcode_mula_aa_hh_encode_fns, 0, 0 },
11533   { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
11534     0,
11535     Opcode_muls_aa_ll_encode_fns, 0, 0 },
11536   { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
11537     0,
11538     Opcode_muls_aa_hl_encode_fns, 0, 0 },
11539   { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
11540     0,
11541     Opcode_muls_aa_lh_encode_fns, 0, 0 },
11542   { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
11543     0,
11544     Opcode_muls_aa_hh_encode_fns, 0, 0 },
11545   { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
11546     0,
11547     Opcode_mula_ad_ll_encode_fns, 0, 0 },
11548   { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
11549     0,
11550     Opcode_mula_ad_hl_encode_fns, 0, 0 },
11551   { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
11552     0,
11553     Opcode_mula_ad_lh_encode_fns, 0, 0 },
11554   { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
11555     0,
11556     Opcode_mula_ad_hh_encode_fns, 0, 0 },
11557   { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
11558     0,
11559     Opcode_muls_ad_ll_encode_fns, 0, 0 },
11560   { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
11561     0,
11562     Opcode_muls_ad_hl_encode_fns, 0, 0 },
11563   { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
11564     0,
11565     Opcode_muls_ad_lh_encode_fns, 0, 0 },
11566   { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
11567     0,
11568     Opcode_muls_ad_hh_encode_fns, 0, 0 },
11569   { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
11570     0,
11571     Opcode_mula_da_ll_encode_fns, 0, 0 },
11572   { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
11573     0,
11574     Opcode_mula_da_hl_encode_fns, 0, 0 },
11575   { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
11576     0,
11577     Opcode_mula_da_lh_encode_fns, 0, 0 },
11578   { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
11579     0,
11580     Opcode_mula_da_hh_encode_fns, 0, 0 },
11581   { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
11582     0,
11583     Opcode_muls_da_ll_encode_fns, 0, 0 },
11584   { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
11585     0,
11586     Opcode_muls_da_hl_encode_fns, 0, 0 },
11587   { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
11588     0,
11589     Opcode_muls_da_lh_encode_fns, 0, 0 },
11590   { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
11591     0,
11592     Opcode_muls_da_hh_encode_fns, 0, 0 },
11593   { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
11594     0,
11595     Opcode_mula_dd_ll_encode_fns, 0, 0 },
11596   { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
11597     0,
11598     Opcode_mula_dd_hl_encode_fns, 0, 0 },
11599   { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
11600     0,
11601     Opcode_mula_dd_lh_encode_fns, 0, 0 },
11602   { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
11603     0,
11604     Opcode_mula_dd_hh_encode_fns, 0, 0 },
11605   { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
11606     0,
11607     Opcode_muls_dd_ll_encode_fns, 0, 0 },
11608   { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
11609     0,
11610     Opcode_muls_dd_hl_encode_fns, 0, 0 },
11611   { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
11612     0,
11613     Opcode_muls_dd_lh_encode_fns, 0, 0 },
11614   { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
11615     0,
11616     Opcode_muls_dd_hh_encode_fns, 0, 0 },
11617   { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
11618     0,
11619     Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
11620   { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
11621     0,
11622     Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
11623   { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
11624     0,
11625     Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
11626   { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
11627     0,
11628     Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
11629   { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
11630     0,
11631     Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
11632   { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
11633     0,
11634     Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
11635   { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
11636     0,
11637     Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
11638   { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
11639     0,
11640     Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
11641   { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
11642     0,
11643     Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
11644   { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
11645     0,
11646     Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
11647   { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
11648     0,
11649     Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
11650   { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
11651     0,
11652     Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
11653   { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
11654     0,
11655     Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
11656   { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
11657     0,
11658     Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
11659   { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
11660     0,
11661     Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
11662   { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
11663     0,
11664     Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
11665   { "lddec", ICLASS_xt_iclass_mac16_l,
11666     0,
11667     Opcode_lddec_encode_fns, 0, 0 },
11668   { "ldinc", ICLASS_xt_iclass_mac16_l,
11669     0,
11670     Opcode_ldinc_encode_fns, 0, 0 },
11671   { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
11672     0,
11673     Opcode_rsr_m0_encode_fns, 0, 0 },
11674   { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
11675     0,
11676     Opcode_wsr_m0_encode_fns, 0, 0 },
11677   { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
11678     0,
11679     Opcode_xsr_m0_encode_fns, 0, 0 },
11680   { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
11681     0,
11682     Opcode_rsr_m1_encode_fns, 0, 0 },
11683   { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
11684     0,
11685     Opcode_wsr_m1_encode_fns, 0, 0 },
11686   { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
11687     0,
11688     Opcode_xsr_m1_encode_fns, 0, 0 },
11689   { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
11690     0,
11691     Opcode_rsr_m2_encode_fns, 0, 0 },
11692   { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
11693     0,
11694     Opcode_wsr_m2_encode_fns, 0, 0 },
11695   { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
11696     0,
11697     Opcode_xsr_m2_encode_fns, 0, 0 },
11698   { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
11699     0,
11700     Opcode_rsr_m3_encode_fns, 0, 0 },
11701   { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
11702     0,
11703     Opcode_wsr_m3_encode_fns, 0, 0 },
11704   { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
11705     0,
11706     Opcode_xsr_m3_encode_fns, 0, 0 },
11707   { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
11708     0,
11709     Opcode_rsr_acclo_encode_fns, 0, 0 },
11710   { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
11711     0,
11712     Opcode_wsr_acclo_encode_fns, 0, 0 },
11713   { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
11714     0,
11715     Opcode_xsr_acclo_encode_fns, 0, 0 },
11716   { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
11717     0,
11718     Opcode_rsr_acchi_encode_fns, 0, 0 },
11719   { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
11720     0,
11721     Opcode_wsr_acchi_encode_fns, 0, 0 },
11722   { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
11723     0,
11724     Opcode_xsr_acchi_encode_fns, 0, 0 },
11725   { "rfi", ICLASS_xt_iclass_rfi,
11726     XTENSA_OPCODE_IS_JUMP,
11727     Opcode_rfi_encode_fns, 0, 0 },
11728   { "waiti", ICLASS_xt_iclass_wait,
11729     0,
11730     Opcode_waiti_encode_fns, 0, 0 },
11731   { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
11732     0,
11733     Opcode_rsr_interrupt_encode_fns, 0, 0 },
11734   { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
11735     0,
11736     Opcode_wsr_intset_encode_fns, 0, 0 },
11737   { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
11738     0,
11739     Opcode_wsr_intclear_encode_fns, 0, 0 },
11740   { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
11741     0,
11742     Opcode_rsr_intenable_encode_fns, 0, 0 },
11743   { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
11744     0,
11745     Opcode_wsr_intenable_encode_fns, 0, 0 },
11746   { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
11747     0,
11748     Opcode_xsr_intenable_encode_fns, 0, 0 },
11749   { "break", ICLASS_xt_iclass_break,
11750     0,
11751     Opcode_break_encode_fns, 0, 0 },
11752   { "break.n", ICLASS_xt_iclass_break_n,
11753     0,
11754     Opcode_break_n_encode_fns, 0, 0 },
11755   { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
11756     0,
11757     Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
11758   { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
11759     0,
11760     Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
11761   { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
11762     0,
11763     Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
11764   { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
11765     0,
11766     Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
11767   { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
11768     0,
11769     Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
11770   { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
11771     0,
11772     Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
11773   { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
11774     0,
11775     Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
11776   { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
11777     0,
11778     Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
11779   { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
11780     0,
11781     Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
11782   { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
11783     0,
11784     Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
11785   { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
11786     0,
11787     Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
11788   { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
11789     0,
11790     Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
11791   { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
11792     0,
11793     Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
11794   { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
11795     0,
11796     Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
11797   { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
11798     0,
11799     Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
11800   { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
11801     0,
11802     Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
11803   { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
11804     0,
11805     Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
11806   { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
11807     0,
11808     Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
11809   { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
11810     0,
11811     Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
11812   { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
11813     0,
11814     Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
11815   { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
11816     0,
11817     Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
11818   { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
11819     0,
11820     Opcode_rsr_debugcause_encode_fns, 0, 0 },
11821   { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
11822     0,
11823     Opcode_wsr_debugcause_encode_fns, 0, 0 },
11824   { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
11825     0,
11826     Opcode_xsr_debugcause_encode_fns, 0, 0 },
11827   { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
11828     0,
11829     Opcode_rsr_icount_encode_fns, 0, 0 },
11830   { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
11831     0,
11832     Opcode_wsr_icount_encode_fns, 0, 0 },
11833   { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
11834     0,
11835     Opcode_xsr_icount_encode_fns, 0, 0 },
11836   { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
11837     0,
11838     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
11839   { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
11840     0,
11841     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
11842   { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
11843     0,
11844     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
11845   { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
11846     0,
11847     Opcode_rsr_ddr_encode_fns, 0, 0 },
11848   { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
11849     0,
11850     Opcode_wsr_ddr_encode_fns, 0, 0 },
11851   { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
11852     0,
11853     Opcode_xsr_ddr_encode_fns, 0, 0 },
11854   { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
11855     0,
11856     Opcode_lddr32_p_encode_fns, 0, 0 },
11857   { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
11858     0,
11859     Opcode_sddr32_p_encode_fns, 0, 0 },
11860   { "rfdo", ICLASS_xt_iclass_rfdo,
11861     XTENSA_OPCODE_IS_JUMP,
11862     Opcode_rfdo_encode_fns, 0, 0 },
11863   { "rfdd", ICLASS_xt_iclass_rfdd,
11864     XTENSA_OPCODE_IS_JUMP,
11865     Opcode_rfdd_encode_fns, 0, 0 },
11866   { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
11867     0,
11868     Opcode_wsr_mmid_encode_fns, 0, 0 },
11869   { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
11870     0,
11871     Opcode_rsr_ccount_encode_fns, 0, 0 },
11872   { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
11873     0,
11874     Opcode_wsr_ccount_encode_fns, 0, 0 },
11875   { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
11876     0,
11877     Opcode_xsr_ccount_encode_fns, 0, 0 },
11878   { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
11879     0,
11880     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
11881   { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
11882     0,
11883     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
11884   { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
11885     0,
11886     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
11887   { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
11888     0,
11889     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
11890   { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
11891     0,
11892     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
11893   { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
11894     0,
11895     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
11896   { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
11897     0,
11898     Opcode_rsr_ccompare2_encode_fns, 0, 0 },
11899   { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
11900     0,
11901     Opcode_wsr_ccompare2_encode_fns, 0, 0 },
11902   { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
11903     0,
11904     Opcode_xsr_ccompare2_encode_fns, 0, 0 },
11905   { "ipf", ICLASS_xt_iclass_icache,
11906     0,
11907     Opcode_ipf_encode_fns, 0, 0 },
11908   { "ihi", ICLASS_xt_iclass_icache,
11909     0,
11910     Opcode_ihi_encode_fns, 0, 0 },
11911   { "ipfl", ICLASS_xt_iclass_icache_lock,
11912     0,
11913     Opcode_ipfl_encode_fns, 0, 0 },
11914   { "ihu", ICLASS_xt_iclass_icache_lock,
11915     0,
11916     Opcode_ihu_encode_fns, 0, 0 },
11917   { "iiu", ICLASS_xt_iclass_icache_lock,
11918     0,
11919     Opcode_iiu_encode_fns, 0, 0 },
11920   { "iii", ICLASS_xt_iclass_icache_inv,
11921     0,
11922     Opcode_iii_encode_fns, 0, 0 },
11923   { "lict", ICLASS_xt_iclass_licx,
11924     0,
11925     Opcode_lict_encode_fns, 0, 0 },
11926   { "licw", ICLASS_xt_iclass_licx,
11927     0,
11928     Opcode_licw_encode_fns, 0, 0 },
11929   { "sict", ICLASS_xt_iclass_sicx,
11930     0,
11931     Opcode_sict_encode_fns, 0, 0 },
11932   { "sicw", ICLASS_xt_iclass_sicx,
11933     0,
11934     Opcode_sicw_encode_fns, 0, 0 },
11935   { "dhwb", ICLASS_xt_iclass_dcache,
11936     0,
11937     Opcode_dhwb_encode_fns, 0, 0 },
11938   { "dhwbi", ICLASS_xt_iclass_dcache,
11939     0,
11940     Opcode_dhwbi_encode_fns, 0, 0 },
11941   { "diwbui.p", ICLASS_xt_iclass_dcache_dyn,
11942     0,
11943     Opcode_diwbui_p_encode_fns, 0, 0 },
11944   { "diwb", ICLASS_xt_iclass_dcache_ind,
11945     0,
11946     Opcode_diwb_encode_fns, 0, 0 },
11947   { "diwbi", ICLASS_xt_iclass_dcache_ind,
11948     0,
11949     Opcode_diwbi_encode_fns, 0, 0 },
11950   { "dhi", ICLASS_xt_iclass_dcache_inv,
11951     0,
11952     Opcode_dhi_encode_fns, 0, 0 },
11953   { "dii", ICLASS_xt_iclass_dcache_inv,
11954     0,
11955     Opcode_dii_encode_fns, 0, 0 },
11956   { "dpfr", ICLASS_xt_iclass_dpf,
11957     0,
11958     Opcode_dpfr_encode_fns, 0, 0 },
11959   { "dpfw", ICLASS_xt_iclass_dpf,
11960     0,
11961     Opcode_dpfw_encode_fns, 0, 0 },
11962   { "dpfro", ICLASS_xt_iclass_dpf,
11963     0,
11964     Opcode_dpfro_encode_fns, 0, 0 },
11965   { "dpfwo", ICLASS_xt_iclass_dpf,
11966     0,
11967     Opcode_dpfwo_encode_fns, 0, 0 },
11968   { "dpfl", ICLASS_xt_iclass_dcache_lock,
11969     0,
11970     Opcode_dpfl_encode_fns, 0, 0 },
11971   { "dhu", ICLASS_xt_iclass_dcache_lock,
11972     0,
11973     Opcode_dhu_encode_fns, 0, 0 },
11974   { "diu", ICLASS_xt_iclass_dcache_lock,
11975     0,
11976     Opcode_diu_encode_fns, 0, 0 },
11977   { "sdct", ICLASS_xt_iclass_sdct,
11978     0,
11979     Opcode_sdct_encode_fns, 0, 0 },
11980   { "ldct", ICLASS_xt_iclass_ldct,
11981     0,
11982     Opcode_ldct_encode_fns, 0, 0 },
11983   { "idtlb", ICLASS_xt_iclass_idtlb,
11984     0,
11985     Opcode_idtlb_encode_fns, 0, 0 },
11986   { "pdtlb", ICLASS_xt_iclass_rdtlb,
11987     0,
11988     Opcode_pdtlb_encode_fns, 0, 0 },
11989   { "rdtlb0", ICLASS_xt_iclass_rdtlb,
11990     0,
11991     Opcode_rdtlb0_encode_fns, 0, 0 },
11992   { "rdtlb1", ICLASS_xt_iclass_rdtlb,
11993     0,
11994     Opcode_rdtlb1_encode_fns, 0, 0 },
11995   { "wdtlb", ICLASS_xt_iclass_wdtlb,
11996     0,
11997     Opcode_wdtlb_encode_fns, 0, 0 },
11998   { "iitlb", ICLASS_xt_iclass_iitlb,
11999     0,
12000     Opcode_iitlb_encode_fns, 0, 0 },
12001   { "pitlb", ICLASS_xt_iclass_ritlb,
12002     0,
12003     Opcode_pitlb_encode_fns, 0, 0 },
12004   { "ritlb0", ICLASS_xt_iclass_ritlb,
12005     0,
12006     Opcode_ritlb0_encode_fns, 0, 0 },
12007   { "ritlb1", ICLASS_xt_iclass_ritlb,
12008     0,
12009     Opcode_ritlb1_encode_fns, 0, 0 },
12010   { "witlb", ICLASS_xt_iclass_witlb,
12011     0,
12012     Opcode_witlb_encode_fns, 0, 0 },
12013   { "clamps", ICLASS_xt_iclass_clamp,
12014     0,
12015     Opcode_clamps_encode_fns, 0, 0 },
12016   { "min", ICLASS_xt_iclass_minmax,
12017     0,
12018     Opcode_min_encode_fns, 0, 0 },
12019   { "max", ICLASS_xt_iclass_minmax,
12020     0,
12021     Opcode_max_encode_fns, 0, 0 },
12022   { "minu", ICLASS_xt_iclass_minmax,
12023     0,
12024     Opcode_minu_encode_fns, 0, 0 },
12025   { "maxu", ICLASS_xt_iclass_minmax,
12026     0,
12027     Opcode_maxu_encode_fns, 0, 0 },
12028   { "nsa", ICLASS_xt_iclass_nsa,
12029     0,
12030     Opcode_nsa_encode_fns, 0, 0 },
12031   { "nsau", ICLASS_xt_iclass_nsa,
12032     0,
12033     Opcode_nsau_encode_fns, 0, 0 },
12034   { "sext", ICLASS_xt_iclass_sx,
12035     0,
12036     Opcode_sext_encode_fns, 0, 0 },
12037   { "l32ai", ICLASS_xt_iclass_l32ai,
12038     0,
12039     Opcode_l32ai_encode_fns, 0, 0 },
12040   { "s32ri", ICLASS_xt_iclass_s32ri,
12041     0,
12042     Opcode_s32ri_encode_fns, 0, 0 },
12043   { "s32c1i", ICLASS_xt_iclass_s32c1i,
12044     0,
12045     Opcode_s32c1i_encode_fns, 0, 0 },
12046   { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
12047     0,
12048     Opcode_rsr_scompare1_encode_fns, 0, 0 },
12049   { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
12050     0,
12051     Opcode_wsr_scompare1_encode_fns, 0, 0 },
12052   { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
12053     0,
12054     Opcode_xsr_scompare1_encode_fns, 0, 0 },
12055   { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
12056     0,
12057     Opcode_rsr_atomctl_encode_fns, 0, 0 },
12058   { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
12059     0,
12060     Opcode_wsr_atomctl_encode_fns, 0, 0 },
12061   { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
12062     0,
12063     Opcode_xsr_atomctl_encode_fns, 0, 0 },
12064   { "quou", ICLASS_xt_iclass_div,
12065     0,
12066     Opcode_quou_encode_fns, 0, 0 },
12067   { "quos", ICLASS_xt_iclass_div,
12068     0,
12069     Opcode_quos_encode_fns, 0, 0 },
12070   { "remu", ICLASS_xt_iclass_div,
12071     0,
12072     Opcode_remu_encode_fns, 0, 0 },
12073   { "rems", ICLASS_xt_iclass_div,
12074     0,
12075     Opcode_rems_encode_fns, 0, 0 },
12076   { "rer", ICLASS_xt_iclass_rer,
12077     0,
12078     Opcode_rer_encode_fns, 0, 0 },
12079   { "wer", ICLASS_xt_iclass_wer,
12080     0,
12081     Opcode_wer_encode_fns, 0, 0 },
12082   { "rur.expstate", ICLASS_rur_expstate,
12083     0,
12084     Opcode_rur_expstate_encode_fns, 0, 0 },
12085   { "wur.expstate", ICLASS_wur_expstate,
12086     0,
12087     Opcode_wur_expstate_encode_fns, 0, 0 },
12088   { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
12089     0,
12090     Opcode_read_impwire_encode_fns, 0, 0 },
12091   { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
12092     0,
12093     Opcode_setb_expstate_encode_fns, 0, 0 },
12094   { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
12095     0,
12096     Opcode_clrb_expstate_encode_fns, 0, 0 },
12097   { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
12098     0,
12099     Opcode_wrmsk_expstate_encode_fns, 0, 0 }
12100 };
12101
12102 enum xtensa_opcode_id {
12103   OPCODE_EXCW,
12104   OPCODE_RFE,
12105   OPCODE_RFDE,
12106   OPCODE_SYSCALL,
12107   OPCODE_CALL12,
12108   OPCODE_CALL8,
12109   OPCODE_CALL4,
12110   OPCODE_CALLX12,
12111   OPCODE_CALLX8,
12112   OPCODE_CALLX4,
12113   OPCODE_ENTRY,
12114   OPCODE_MOVSP,
12115   OPCODE_ROTW,
12116   OPCODE_RETW,
12117   OPCODE_RETW_N,
12118   OPCODE_RFWO,
12119   OPCODE_RFWU,
12120   OPCODE_L32E,
12121   OPCODE_S32E,
12122   OPCODE_RSR_WINDOWBASE,
12123   OPCODE_WSR_WINDOWBASE,
12124   OPCODE_XSR_WINDOWBASE,
12125   OPCODE_RSR_WINDOWSTART,
12126   OPCODE_WSR_WINDOWSTART,
12127   OPCODE_XSR_WINDOWSTART,
12128   OPCODE_ADD_N,
12129   OPCODE_ADDI_N,
12130   OPCODE_BEQZ_N,
12131   OPCODE_BNEZ_N,
12132   OPCODE_ILL_N,
12133   OPCODE_L32I_N,
12134   OPCODE_MOV_N,
12135   OPCODE_MOVI_N,
12136   OPCODE_NOP_N,
12137   OPCODE_RET_N,
12138   OPCODE_S32I_N,
12139   OPCODE_ADDI,
12140   OPCODE_ADDMI,
12141   OPCODE_ADD,
12142   OPCODE_SUB,
12143   OPCODE_ADDX2,
12144   OPCODE_ADDX4,
12145   OPCODE_ADDX8,
12146   OPCODE_SUBX2,
12147   OPCODE_SUBX4,
12148   OPCODE_SUBX8,
12149   OPCODE_AND,
12150   OPCODE_OR,
12151   OPCODE_XOR,
12152   OPCODE_BEQI,
12153   OPCODE_BNEI,
12154   OPCODE_BGEI,
12155   OPCODE_BLTI,
12156   OPCODE_BBCI,
12157   OPCODE_BBSI,
12158   OPCODE_BGEUI,
12159   OPCODE_BLTUI,
12160   OPCODE_BEQ,
12161   OPCODE_BNE,
12162   OPCODE_BGE,
12163   OPCODE_BLT,
12164   OPCODE_BGEU,
12165   OPCODE_BLTU,
12166   OPCODE_BANY,
12167   OPCODE_BNONE,
12168   OPCODE_BALL,
12169   OPCODE_BNALL,
12170   OPCODE_BBC,
12171   OPCODE_BBS,
12172   OPCODE_BEQZ,
12173   OPCODE_BNEZ,
12174   OPCODE_BGEZ,
12175   OPCODE_BLTZ,
12176   OPCODE_CALL0,
12177   OPCODE_CALLX0,
12178   OPCODE_EXTUI,
12179   OPCODE_ILL,
12180   OPCODE_J,
12181   OPCODE_JX,
12182   OPCODE_L16UI,
12183   OPCODE_L16SI,
12184   OPCODE_L32I,
12185   OPCODE_L32R,
12186   OPCODE_L8UI,
12187   OPCODE_LOOP,
12188   OPCODE_LOOPNEZ,
12189   OPCODE_LOOPGTZ,
12190   OPCODE_MOVI,
12191   OPCODE_MOVEQZ,
12192   OPCODE_MOVNEZ,
12193   OPCODE_MOVLTZ,
12194   OPCODE_MOVGEZ,
12195   OPCODE_NEG,
12196   OPCODE_ABS,
12197   OPCODE_NOP,
12198   OPCODE_RET,
12199   OPCODE_SIMCALL,
12200   OPCODE_S16I,
12201   OPCODE_S32I,
12202   OPCODE_S32NB,
12203   OPCODE_S8I,
12204   OPCODE_SSR,
12205   OPCODE_SSL,
12206   OPCODE_SSA8L,
12207   OPCODE_SSA8B,
12208   OPCODE_SSAI,
12209   OPCODE_SLL,
12210   OPCODE_SRC,
12211   OPCODE_SRL,
12212   OPCODE_SRA,
12213   OPCODE_SLLI,
12214   OPCODE_SRAI,
12215   OPCODE_SRLI,
12216   OPCODE_MEMW,
12217   OPCODE_EXTW,
12218   OPCODE_ISYNC,
12219   OPCODE_RSYNC,
12220   OPCODE_ESYNC,
12221   OPCODE_DSYNC,
12222   OPCODE_RSIL,
12223   OPCODE_RSR_LEND,
12224   OPCODE_WSR_LEND,
12225   OPCODE_XSR_LEND,
12226   OPCODE_RSR_LCOUNT,
12227   OPCODE_WSR_LCOUNT,
12228   OPCODE_XSR_LCOUNT,
12229   OPCODE_RSR_LBEG,
12230   OPCODE_WSR_LBEG,
12231   OPCODE_XSR_LBEG,
12232   OPCODE_RSR_SAR,
12233   OPCODE_WSR_SAR,
12234   OPCODE_XSR_SAR,
12235   OPCODE_RSR_MEMCTL,
12236   OPCODE_WSR_MEMCTL,
12237   OPCODE_XSR_MEMCTL,
12238   OPCODE_RSR_LITBASE,
12239   OPCODE_WSR_LITBASE,
12240   OPCODE_XSR_LITBASE,
12241   OPCODE_RSR_CONFIGID0,
12242   OPCODE_WSR_CONFIGID0,
12243   OPCODE_RSR_CONFIGID1,
12244   OPCODE_RSR_PS,
12245   OPCODE_WSR_PS,
12246   OPCODE_XSR_PS,
12247   OPCODE_RSR_EPC1,
12248   OPCODE_WSR_EPC1,
12249   OPCODE_XSR_EPC1,
12250   OPCODE_RSR_EXCSAVE1,
12251   OPCODE_WSR_EXCSAVE1,
12252   OPCODE_XSR_EXCSAVE1,
12253   OPCODE_RSR_EPC2,
12254   OPCODE_WSR_EPC2,
12255   OPCODE_XSR_EPC2,
12256   OPCODE_RSR_EXCSAVE2,
12257   OPCODE_WSR_EXCSAVE2,
12258   OPCODE_XSR_EXCSAVE2,
12259   OPCODE_RSR_EPC3,
12260   OPCODE_WSR_EPC3,
12261   OPCODE_XSR_EPC3,
12262   OPCODE_RSR_EXCSAVE3,
12263   OPCODE_WSR_EXCSAVE3,
12264   OPCODE_XSR_EXCSAVE3,
12265   OPCODE_RSR_EPC4,
12266   OPCODE_WSR_EPC4,
12267   OPCODE_XSR_EPC4,
12268   OPCODE_RSR_EXCSAVE4,
12269   OPCODE_WSR_EXCSAVE4,
12270   OPCODE_XSR_EXCSAVE4,
12271   OPCODE_RSR_EPC5,
12272   OPCODE_WSR_EPC5,
12273   OPCODE_XSR_EPC5,
12274   OPCODE_RSR_EXCSAVE5,
12275   OPCODE_WSR_EXCSAVE5,
12276   OPCODE_XSR_EXCSAVE5,
12277   OPCODE_RSR_EPC6,
12278   OPCODE_WSR_EPC6,
12279   OPCODE_XSR_EPC6,
12280   OPCODE_RSR_EXCSAVE6,
12281   OPCODE_WSR_EXCSAVE6,
12282   OPCODE_XSR_EXCSAVE6,
12283   OPCODE_RSR_EPC7,
12284   OPCODE_WSR_EPC7,
12285   OPCODE_XSR_EPC7,
12286   OPCODE_RSR_EXCSAVE7,
12287   OPCODE_WSR_EXCSAVE7,
12288   OPCODE_XSR_EXCSAVE7,
12289   OPCODE_RSR_EPS2,
12290   OPCODE_WSR_EPS2,
12291   OPCODE_XSR_EPS2,
12292   OPCODE_RSR_EPS3,
12293   OPCODE_WSR_EPS3,
12294   OPCODE_XSR_EPS3,
12295   OPCODE_RSR_EPS4,
12296   OPCODE_WSR_EPS4,
12297   OPCODE_XSR_EPS4,
12298   OPCODE_RSR_EPS5,
12299   OPCODE_WSR_EPS5,
12300   OPCODE_XSR_EPS5,
12301   OPCODE_RSR_EPS6,
12302   OPCODE_WSR_EPS6,
12303   OPCODE_XSR_EPS6,
12304   OPCODE_RSR_EPS7,
12305   OPCODE_WSR_EPS7,
12306   OPCODE_XSR_EPS7,
12307   OPCODE_RSR_EXCVADDR,
12308   OPCODE_WSR_EXCVADDR,
12309   OPCODE_XSR_EXCVADDR,
12310   OPCODE_RSR_DEPC,
12311   OPCODE_WSR_DEPC,
12312   OPCODE_XSR_DEPC,
12313   OPCODE_RSR_EXCCAUSE,
12314   OPCODE_WSR_EXCCAUSE,
12315   OPCODE_XSR_EXCCAUSE,
12316   OPCODE_RSR_MISC0,
12317   OPCODE_WSR_MISC0,
12318   OPCODE_XSR_MISC0,
12319   OPCODE_RSR_MISC1,
12320   OPCODE_WSR_MISC1,
12321   OPCODE_XSR_MISC1,
12322   OPCODE_RSR_PRID,
12323   OPCODE_RSR_VECBASE,
12324   OPCODE_WSR_VECBASE,
12325   OPCODE_XSR_VECBASE,
12326   OPCODE_MUL16U,
12327   OPCODE_MUL16S,
12328   OPCODE_MULL,
12329   OPCODE_MUL_AA_LL,
12330   OPCODE_MUL_AA_HL,
12331   OPCODE_MUL_AA_LH,
12332   OPCODE_MUL_AA_HH,
12333   OPCODE_UMUL_AA_LL,
12334   OPCODE_UMUL_AA_HL,
12335   OPCODE_UMUL_AA_LH,
12336   OPCODE_UMUL_AA_HH,
12337   OPCODE_MUL_AD_LL,
12338   OPCODE_MUL_AD_HL,
12339   OPCODE_MUL_AD_LH,
12340   OPCODE_MUL_AD_HH,
12341   OPCODE_MUL_DA_LL,
12342   OPCODE_MUL_DA_HL,
12343   OPCODE_MUL_DA_LH,
12344   OPCODE_MUL_DA_HH,
12345   OPCODE_MUL_DD_LL,
12346   OPCODE_MUL_DD_HL,
12347   OPCODE_MUL_DD_LH,
12348   OPCODE_MUL_DD_HH,
12349   OPCODE_MULA_AA_LL,
12350   OPCODE_MULA_AA_HL,
12351   OPCODE_MULA_AA_LH,
12352   OPCODE_MULA_AA_HH,
12353   OPCODE_MULS_AA_LL,
12354   OPCODE_MULS_AA_HL,
12355   OPCODE_MULS_AA_LH,
12356   OPCODE_MULS_AA_HH,
12357   OPCODE_MULA_AD_LL,
12358   OPCODE_MULA_AD_HL,
12359   OPCODE_MULA_AD_LH,
12360   OPCODE_MULA_AD_HH,
12361   OPCODE_MULS_AD_LL,
12362   OPCODE_MULS_AD_HL,
12363   OPCODE_MULS_AD_LH,
12364   OPCODE_MULS_AD_HH,
12365   OPCODE_MULA_DA_LL,
12366   OPCODE_MULA_DA_HL,
12367   OPCODE_MULA_DA_LH,
12368   OPCODE_MULA_DA_HH,
12369   OPCODE_MULS_DA_LL,
12370   OPCODE_MULS_DA_HL,
12371   OPCODE_MULS_DA_LH,
12372   OPCODE_MULS_DA_HH,
12373   OPCODE_MULA_DD_LL,
12374   OPCODE_MULA_DD_HL,
12375   OPCODE_MULA_DD_LH,
12376   OPCODE_MULA_DD_HH,
12377   OPCODE_MULS_DD_LL,
12378   OPCODE_MULS_DD_HL,
12379   OPCODE_MULS_DD_LH,
12380   OPCODE_MULS_DD_HH,
12381   OPCODE_MULA_DA_LL_LDDEC,
12382   OPCODE_MULA_DA_LL_LDINC,
12383   OPCODE_MULA_DA_HL_LDDEC,
12384   OPCODE_MULA_DA_HL_LDINC,
12385   OPCODE_MULA_DA_LH_LDDEC,
12386   OPCODE_MULA_DA_LH_LDINC,
12387   OPCODE_MULA_DA_HH_LDDEC,
12388   OPCODE_MULA_DA_HH_LDINC,
12389   OPCODE_MULA_DD_LL_LDDEC,
12390   OPCODE_MULA_DD_LL_LDINC,
12391   OPCODE_MULA_DD_HL_LDDEC,
12392   OPCODE_MULA_DD_HL_LDINC,
12393   OPCODE_MULA_DD_LH_LDDEC,
12394   OPCODE_MULA_DD_LH_LDINC,
12395   OPCODE_MULA_DD_HH_LDDEC,
12396   OPCODE_MULA_DD_HH_LDINC,
12397   OPCODE_LDDEC,
12398   OPCODE_LDINC,
12399   OPCODE_RSR_M0,
12400   OPCODE_WSR_M0,
12401   OPCODE_XSR_M0,
12402   OPCODE_RSR_M1,
12403   OPCODE_WSR_M1,
12404   OPCODE_XSR_M1,
12405   OPCODE_RSR_M2,
12406   OPCODE_WSR_M2,
12407   OPCODE_XSR_M2,
12408   OPCODE_RSR_M3,
12409   OPCODE_WSR_M3,
12410   OPCODE_XSR_M3,
12411   OPCODE_RSR_ACCLO,
12412   OPCODE_WSR_ACCLO,
12413   OPCODE_XSR_ACCLO,
12414   OPCODE_RSR_ACCHI,
12415   OPCODE_WSR_ACCHI,
12416   OPCODE_XSR_ACCHI,
12417   OPCODE_RFI,
12418   OPCODE_WAITI,
12419   OPCODE_RSR_INTERRUPT,
12420   OPCODE_WSR_INTSET,
12421   OPCODE_WSR_INTCLEAR,
12422   OPCODE_RSR_INTENABLE,
12423   OPCODE_WSR_INTENABLE,
12424   OPCODE_XSR_INTENABLE,
12425   OPCODE_BREAK,
12426   OPCODE_BREAK_N,
12427   OPCODE_RSR_DBREAKA0,
12428   OPCODE_WSR_DBREAKA0,
12429   OPCODE_XSR_DBREAKA0,
12430   OPCODE_RSR_DBREAKC0,
12431   OPCODE_WSR_DBREAKC0,
12432   OPCODE_XSR_DBREAKC0,
12433   OPCODE_RSR_DBREAKA1,
12434   OPCODE_WSR_DBREAKA1,
12435   OPCODE_XSR_DBREAKA1,
12436   OPCODE_RSR_DBREAKC1,
12437   OPCODE_WSR_DBREAKC1,
12438   OPCODE_XSR_DBREAKC1,
12439   OPCODE_RSR_IBREAKA0,
12440   OPCODE_WSR_IBREAKA0,
12441   OPCODE_XSR_IBREAKA0,
12442   OPCODE_RSR_IBREAKA1,
12443   OPCODE_WSR_IBREAKA1,
12444   OPCODE_XSR_IBREAKA1,
12445   OPCODE_RSR_IBREAKENABLE,
12446   OPCODE_WSR_IBREAKENABLE,
12447   OPCODE_XSR_IBREAKENABLE,
12448   OPCODE_RSR_DEBUGCAUSE,
12449   OPCODE_WSR_DEBUGCAUSE,
12450   OPCODE_XSR_DEBUGCAUSE,
12451   OPCODE_RSR_ICOUNT,
12452   OPCODE_WSR_ICOUNT,
12453   OPCODE_XSR_ICOUNT,
12454   OPCODE_RSR_ICOUNTLEVEL,
12455   OPCODE_WSR_ICOUNTLEVEL,
12456   OPCODE_XSR_ICOUNTLEVEL,
12457   OPCODE_RSR_DDR,
12458   OPCODE_WSR_DDR,
12459   OPCODE_XSR_DDR,
12460   OPCODE_LDDR32_P,
12461   OPCODE_SDDR32_P,
12462   OPCODE_RFDO,
12463   OPCODE_RFDD,
12464   OPCODE_WSR_MMID,
12465   OPCODE_RSR_CCOUNT,
12466   OPCODE_WSR_CCOUNT,
12467   OPCODE_XSR_CCOUNT,
12468   OPCODE_RSR_CCOMPARE0,
12469   OPCODE_WSR_CCOMPARE0,
12470   OPCODE_XSR_CCOMPARE0,
12471   OPCODE_RSR_CCOMPARE1,
12472   OPCODE_WSR_CCOMPARE1,
12473   OPCODE_XSR_CCOMPARE1,
12474   OPCODE_RSR_CCOMPARE2,
12475   OPCODE_WSR_CCOMPARE2,
12476   OPCODE_XSR_CCOMPARE2,
12477   OPCODE_IPF,
12478   OPCODE_IHI,
12479   OPCODE_IPFL,
12480   OPCODE_IHU,
12481   OPCODE_IIU,
12482   OPCODE_III,
12483   OPCODE_LICT,
12484   OPCODE_LICW,
12485   OPCODE_SICT,
12486   OPCODE_SICW,
12487   OPCODE_DHWB,
12488   OPCODE_DHWBI,
12489   OPCODE_DIWBUI_P,
12490   OPCODE_DIWB,
12491   OPCODE_DIWBI,
12492   OPCODE_DHI,
12493   OPCODE_DII,
12494   OPCODE_DPFR,
12495   OPCODE_DPFW,
12496   OPCODE_DPFRO,
12497   OPCODE_DPFWO,
12498   OPCODE_DPFL,
12499   OPCODE_DHU,
12500   OPCODE_DIU,
12501   OPCODE_SDCT,
12502   OPCODE_LDCT,
12503   OPCODE_IDTLB,
12504   OPCODE_PDTLB,
12505   OPCODE_RDTLB0,
12506   OPCODE_RDTLB1,
12507   OPCODE_WDTLB,
12508   OPCODE_IITLB,
12509   OPCODE_PITLB,
12510   OPCODE_RITLB0,
12511   OPCODE_RITLB1,
12512   OPCODE_WITLB,
12513   OPCODE_CLAMPS,
12514   OPCODE_MIN,
12515   OPCODE_MAX,
12516   OPCODE_MINU,
12517   OPCODE_MAXU,
12518   OPCODE_NSA,
12519   OPCODE_NSAU,
12520   OPCODE_SEXT,
12521   OPCODE_L32AI,
12522   OPCODE_S32RI,
12523   OPCODE_S32C1I,
12524   OPCODE_RSR_SCOMPARE1,
12525   OPCODE_WSR_SCOMPARE1,
12526   OPCODE_XSR_SCOMPARE1,
12527   OPCODE_RSR_ATOMCTL,
12528   OPCODE_WSR_ATOMCTL,
12529   OPCODE_XSR_ATOMCTL,
12530   OPCODE_QUOU,
12531   OPCODE_QUOS,
12532   OPCODE_REMU,
12533   OPCODE_REMS,
12534   OPCODE_RER,
12535   OPCODE_WER,
12536   OPCODE_RUR_EXPSTATE,
12537   OPCODE_WUR_EXPSTATE,
12538   OPCODE_READ_IMPWIRE,
12539   OPCODE_SETB_EXPSTATE,
12540   OPCODE_CLRB_EXPSTATE,
12541   OPCODE_WRMSK_EXPSTATE
12542 };
12543
12544 \f
12545 /* Slot-specific opcode decode functions.  */
12546
12547 static int
12548 Slot_inst_decode (const xtensa_insnbuf insn)
12549 {
12550   if (Field_op0_Slot_inst_get (insn) == 0)
12551     {
12552       if (Field_op1_Slot_inst_get (insn) == 0)
12553         {
12554           if (Field_op2_Slot_inst_get (insn) == 0)
12555             {
12556               if (Field_r_Slot_inst_get (insn) == 0)
12557                 {
12558                   if (Field_m_Slot_inst_get (insn) == 0 &&
12559                       Field_s_Slot_inst_get (insn) == 0 &&
12560                       Field_n_Slot_inst_get (insn) == 0)
12561                     return OPCODE_ILL;
12562                   if (Field_m_Slot_inst_get (insn) == 2)
12563                     {
12564                       if (Field_n_Slot_inst_get (insn) == 0)
12565                         return OPCODE_RET;
12566                       if (Field_n_Slot_inst_get (insn) == 1)
12567                         return OPCODE_RETW;
12568                       if (Field_n_Slot_inst_get (insn) == 2)
12569                         return OPCODE_JX;
12570                     }
12571                   if (Field_m_Slot_inst_get (insn) == 3)
12572                     {
12573                       if (Field_n_Slot_inst_get (insn) == 0)
12574                         return OPCODE_CALLX0;
12575                       if (Field_n_Slot_inst_get (insn) == 1)
12576                         return OPCODE_CALLX4;
12577                       if (Field_n_Slot_inst_get (insn) == 2)
12578                         return OPCODE_CALLX8;
12579                       if (Field_n_Slot_inst_get (insn) == 3)
12580                         return OPCODE_CALLX12;
12581                     }
12582                 }
12583               if (Field_r_Slot_inst_get (insn) == 1)
12584                 return OPCODE_MOVSP;
12585               if (Field_r_Slot_inst_get (insn) == 2)
12586                 {
12587                   if (Field_s_Slot_inst_get (insn) == 0)
12588                     {
12589                       if (Field_t_Slot_inst_get (insn) == 0)
12590                         return OPCODE_ISYNC;
12591                       if (Field_t_Slot_inst_get (insn) == 1)
12592                         return OPCODE_RSYNC;
12593                       if (Field_t_Slot_inst_get (insn) == 2)
12594                         return OPCODE_ESYNC;
12595                       if (Field_t_Slot_inst_get (insn) == 3)
12596                         return OPCODE_DSYNC;
12597                       if (Field_t_Slot_inst_get (insn) == 8)
12598                         return OPCODE_EXCW;
12599                       if (Field_t_Slot_inst_get (insn) == 12)
12600                         return OPCODE_MEMW;
12601                       if (Field_t_Slot_inst_get (insn) == 13)
12602                         return OPCODE_EXTW;
12603                       if (Field_t_Slot_inst_get (insn) == 15)
12604                         return OPCODE_NOP;
12605                     }
12606                 }
12607               if (Field_r_Slot_inst_get (insn) == 3)
12608                 {
12609                   if (Field_t_Slot_inst_get (insn) == 0)
12610                     {
12611                       if (Field_s_Slot_inst_get (insn) == 0)
12612                         return OPCODE_RFE;
12613                       if (Field_s_Slot_inst_get (insn) == 2)
12614                         return OPCODE_RFDE;
12615                       if (Field_s_Slot_inst_get (insn) == 4)
12616                         return OPCODE_RFWO;
12617                       if (Field_s_Slot_inst_get (insn) == 5)
12618                         return OPCODE_RFWU;
12619                     }
12620                   if (Field_t_Slot_inst_get (insn) == 1)
12621                     return OPCODE_RFI;
12622                 }
12623               if (Field_r_Slot_inst_get (insn) == 4)
12624                 return OPCODE_BREAK;
12625               if (Field_r_Slot_inst_get (insn) == 5)
12626                 {
12627                   if (Field_s_Slot_inst_get (insn) == 0 &&
12628                       Field_t_Slot_inst_get (insn) == 0)
12629                     return OPCODE_SYSCALL;
12630                   if (Field_s_Slot_inst_get (insn) == 1 &&
12631                       Field_t_Slot_inst_get (insn) == 0)
12632                     return OPCODE_SIMCALL;
12633                 }
12634               if (Field_r_Slot_inst_get (insn) == 6)
12635                 return OPCODE_RSIL;
12636               if (Field_r_Slot_inst_get (insn) == 7 &&
12637                   Field_t_Slot_inst_get (insn) == 0)
12638                 return OPCODE_WAITI;
12639               if (Field_r_Slot_inst_get (insn) == 7)
12640                 {
12641                   if (Field_t_Slot_inst_get (insn) == 14)
12642                     return OPCODE_LDDR32_P;
12643                   if (Field_t_Slot_inst_get (insn) == 15)
12644                     return OPCODE_SDDR32_P;
12645                 }
12646             }
12647           if (Field_op2_Slot_inst_get (insn) == 1)
12648             return OPCODE_AND;
12649           if (Field_op2_Slot_inst_get (insn) == 2)
12650             return OPCODE_OR;
12651           if (Field_op2_Slot_inst_get (insn) == 3)
12652             return OPCODE_XOR;
12653           if (Field_op2_Slot_inst_get (insn) == 4)
12654             {
12655               if (Field_r_Slot_inst_get (insn) == 0 &&
12656                   Field_t_Slot_inst_get (insn) == 0)
12657                 return OPCODE_SSR;
12658               if (Field_r_Slot_inst_get (insn) == 1 &&
12659                   Field_t_Slot_inst_get (insn) == 0)
12660                 return OPCODE_SSL;
12661               if (Field_r_Slot_inst_get (insn) == 2 &&
12662                   Field_t_Slot_inst_get (insn) == 0)
12663                 return OPCODE_SSA8L;
12664               if (Field_r_Slot_inst_get (insn) == 3 &&
12665                   Field_t_Slot_inst_get (insn) == 0)
12666                 return OPCODE_SSA8B;
12667               if (Field_r_Slot_inst_get (insn) == 4 &&
12668                   Field_thi3_Slot_inst_get (insn) == 0)
12669                 return OPCODE_SSAI;
12670               if (Field_r_Slot_inst_get (insn) == 6)
12671                 return OPCODE_RER;
12672               if (Field_r_Slot_inst_get (insn) == 7)
12673                 return OPCODE_WER;
12674               if (Field_r_Slot_inst_get (insn) == 8 &&
12675                   Field_s_Slot_inst_get (insn) == 0)
12676                 return OPCODE_ROTW;
12677               if (Field_r_Slot_inst_get (insn) == 14)
12678                 return OPCODE_NSA;
12679               if (Field_r_Slot_inst_get (insn) == 15)
12680                 return OPCODE_NSAU;
12681             }
12682           if (Field_op2_Slot_inst_get (insn) == 5)
12683             {
12684               if (Field_r_Slot_inst_get (insn) == 3)
12685                 return OPCODE_RITLB0;
12686               if (Field_r_Slot_inst_get (insn) == 4 &&
12687                   Field_t_Slot_inst_get (insn) == 0)
12688                 return OPCODE_IITLB;
12689               if (Field_r_Slot_inst_get (insn) == 5)
12690                 return OPCODE_PITLB;
12691               if (Field_r_Slot_inst_get (insn) == 6)
12692                 return OPCODE_WITLB;
12693               if (Field_r_Slot_inst_get (insn) == 7)
12694                 return OPCODE_RITLB1;
12695               if (Field_r_Slot_inst_get (insn) == 11)
12696                 return OPCODE_RDTLB0;
12697               if (Field_r_Slot_inst_get (insn) == 12 &&
12698                   Field_t_Slot_inst_get (insn) == 0)
12699                 return OPCODE_IDTLB;
12700               if (Field_r_Slot_inst_get (insn) == 13)
12701                 return OPCODE_PDTLB;
12702               if (Field_r_Slot_inst_get (insn) == 14)
12703                 return OPCODE_WDTLB;
12704               if (Field_r_Slot_inst_get (insn) == 15)
12705                 return OPCODE_RDTLB1;
12706             }
12707           if (Field_op2_Slot_inst_get (insn) == 6)
12708             {
12709               if (Field_s_Slot_inst_get (insn) == 0)
12710                 return OPCODE_NEG;
12711               if (Field_s_Slot_inst_get (insn) == 1)
12712                 return OPCODE_ABS;
12713             }
12714           if (Field_op2_Slot_inst_get (insn) == 8)
12715             return OPCODE_ADD;
12716           if (Field_op2_Slot_inst_get (insn) == 9)
12717             return OPCODE_ADDX2;
12718           if (Field_op2_Slot_inst_get (insn) == 10)
12719             return OPCODE_ADDX4;
12720           if (Field_op2_Slot_inst_get (insn) == 11)
12721             return OPCODE_ADDX8;
12722           if (Field_op2_Slot_inst_get (insn) == 12)
12723             return OPCODE_SUB;
12724           if (Field_op2_Slot_inst_get (insn) == 13)
12725             return OPCODE_SUBX2;
12726           if (Field_op2_Slot_inst_get (insn) == 14)
12727             return OPCODE_SUBX4;
12728           if (Field_op2_Slot_inst_get (insn) == 15)
12729             return OPCODE_SUBX8;
12730         }
12731       if (Field_op1_Slot_inst_get (insn) == 1)
12732         {
12733           if ((Field_op2_Slot_inst_get (insn) == 0 ||
12734                Field_op2_Slot_inst_get (insn) == 1))
12735             return OPCODE_SLLI;
12736           if ((Field_op2_Slot_inst_get (insn) == 2 ||
12737                Field_op2_Slot_inst_get (insn) == 3))
12738             return OPCODE_SRAI;
12739           if (Field_op2_Slot_inst_get (insn) == 4)
12740             return OPCODE_SRLI;
12741           if (Field_op2_Slot_inst_get (insn) == 6)
12742             {
12743               if (Field_sr_Slot_inst_get (insn) == 0)
12744                 return OPCODE_XSR_LBEG;
12745               if (Field_sr_Slot_inst_get (insn) == 1)
12746                 return OPCODE_XSR_LEND;
12747               if (Field_sr_Slot_inst_get (insn) == 2)
12748                 return OPCODE_XSR_LCOUNT;
12749               if (Field_sr_Slot_inst_get (insn) == 3)
12750                 return OPCODE_XSR_SAR;
12751               if (Field_sr_Slot_inst_get (insn) == 5)
12752                 return OPCODE_XSR_LITBASE;
12753               if (Field_sr_Slot_inst_get (insn) == 12)
12754                 return OPCODE_XSR_SCOMPARE1;
12755               if (Field_sr_Slot_inst_get (insn) == 16)
12756                 return OPCODE_XSR_ACCLO;
12757               if (Field_sr_Slot_inst_get (insn) == 17)
12758                 return OPCODE_XSR_ACCHI;
12759               if (Field_sr_Slot_inst_get (insn) == 32)
12760                 return OPCODE_XSR_M0;
12761               if (Field_sr_Slot_inst_get (insn) == 33)
12762                 return OPCODE_XSR_M1;
12763               if (Field_sr_Slot_inst_get (insn) == 34)
12764                 return OPCODE_XSR_M2;
12765               if (Field_sr_Slot_inst_get (insn) == 35)
12766                 return OPCODE_XSR_M3;
12767               if (Field_sr_Slot_inst_get (insn) == 72)
12768                 return OPCODE_XSR_WINDOWBASE;
12769               if (Field_sr_Slot_inst_get (insn) == 73)
12770                 return OPCODE_XSR_WINDOWSTART;
12771               if (Field_sr_Slot_inst_get (insn) == 96)
12772                 return OPCODE_XSR_IBREAKENABLE;
12773               if (Field_sr_Slot_inst_get (insn) == 97)
12774                 return OPCODE_XSR_MEMCTL;
12775               if (Field_sr_Slot_inst_get (insn) == 99)
12776                 return OPCODE_XSR_ATOMCTL;
12777               if (Field_sr_Slot_inst_get (insn) == 104)
12778                 return OPCODE_XSR_DDR;
12779               if (Field_sr_Slot_inst_get (insn) == 128)
12780                 return OPCODE_XSR_IBREAKA0;
12781               if (Field_sr_Slot_inst_get (insn) == 129)
12782                 return OPCODE_XSR_IBREAKA1;
12783               if (Field_sr_Slot_inst_get (insn) == 144)
12784                 return OPCODE_XSR_DBREAKA0;
12785               if (Field_sr_Slot_inst_get (insn) == 145)
12786                 return OPCODE_XSR_DBREAKA1;
12787               if (Field_sr_Slot_inst_get (insn) == 160)
12788                 return OPCODE_XSR_DBREAKC0;
12789               if (Field_sr_Slot_inst_get (insn) == 161)
12790                 return OPCODE_XSR_DBREAKC1;
12791               if (Field_sr_Slot_inst_get (insn) == 177)
12792                 return OPCODE_XSR_EPC1;
12793               if (Field_sr_Slot_inst_get (insn) == 178)
12794                 return OPCODE_XSR_EPC2;
12795               if (Field_sr_Slot_inst_get (insn) == 179)
12796                 return OPCODE_XSR_EPC3;
12797               if (Field_sr_Slot_inst_get (insn) == 180)
12798                 return OPCODE_XSR_EPC4;
12799               if (Field_sr_Slot_inst_get (insn) == 181)
12800                 return OPCODE_XSR_EPC5;
12801               if (Field_sr_Slot_inst_get (insn) == 182)
12802                 return OPCODE_XSR_EPC6;
12803               if (Field_sr_Slot_inst_get (insn) == 183)
12804                 return OPCODE_XSR_EPC7;
12805               if (Field_sr_Slot_inst_get (insn) == 192)
12806                 return OPCODE_XSR_DEPC;
12807               if (Field_sr_Slot_inst_get (insn) == 194)
12808                 return OPCODE_XSR_EPS2;
12809               if (Field_sr_Slot_inst_get (insn) == 195)
12810                 return OPCODE_XSR_EPS3;
12811               if (Field_sr_Slot_inst_get (insn) == 196)
12812                 return OPCODE_XSR_EPS4;
12813               if (Field_sr_Slot_inst_get (insn) == 197)
12814                 return OPCODE_XSR_EPS5;
12815               if (Field_sr_Slot_inst_get (insn) == 198)
12816                 return OPCODE_XSR_EPS6;
12817               if (Field_sr_Slot_inst_get (insn) == 199)
12818                 return OPCODE_XSR_EPS7;
12819               if (Field_sr_Slot_inst_get (insn) == 209)
12820                 return OPCODE_XSR_EXCSAVE1;
12821               if (Field_sr_Slot_inst_get (insn) == 210)
12822                 return OPCODE_XSR_EXCSAVE2;
12823               if (Field_sr_Slot_inst_get (insn) == 211)
12824                 return OPCODE_XSR_EXCSAVE3;
12825               if (Field_sr_Slot_inst_get (insn) == 212)
12826                 return OPCODE_XSR_EXCSAVE4;
12827               if (Field_sr_Slot_inst_get (insn) == 213)
12828                 return OPCODE_XSR_EXCSAVE5;
12829               if (Field_sr_Slot_inst_get (insn) == 214)
12830                 return OPCODE_XSR_EXCSAVE6;
12831               if (Field_sr_Slot_inst_get (insn) == 215)
12832                 return OPCODE_XSR_EXCSAVE7;
12833               if (Field_sr_Slot_inst_get (insn) == 228)
12834                 return OPCODE_XSR_INTENABLE;
12835               if (Field_sr_Slot_inst_get (insn) == 230)
12836                 return OPCODE_XSR_PS;
12837               if (Field_sr_Slot_inst_get (insn) == 231)
12838                 return OPCODE_XSR_VECBASE;
12839               if (Field_sr_Slot_inst_get (insn) == 232)
12840                 return OPCODE_XSR_EXCCAUSE;
12841               if (Field_sr_Slot_inst_get (insn) == 233)
12842                 return OPCODE_XSR_DEBUGCAUSE;
12843               if (Field_sr_Slot_inst_get (insn) == 234)
12844                 return OPCODE_XSR_CCOUNT;
12845               if (Field_sr_Slot_inst_get (insn) == 236)
12846                 return OPCODE_XSR_ICOUNT;
12847               if (Field_sr_Slot_inst_get (insn) == 237)
12848                 return OPCODE_XSR_ICOUNTLEVEL;
12849               if (Field_sr_Slot_inst_get (insn) == 238)
12850                 return OPCODE_XSR_EXCVADDR;
12851               if (Field_sr_Slot_inst_get (insn) == 240)
12852                 return OPCODE_XSR_CCOMPARE0;
12853               if (Field_sr_Slot_inst_get (insn) == 241)
12854                 return OPCODE_XSR_CCOMPARE1;
12855               if (Field_sr_Slot_inst_get (insn) == 242)
12856                 return OPCODE_XSR_CCOMPARE2;
12857               if (Field_sr_Slot_inst_get (insn) == 244)
12858                 return OPCODE_XSR_MISC0;
12859               if (Field_sr_Slot_inst_get (insn) == 245)
12860                 return OPCODE_XSR_MISC1;
12861             }
12862           if (Field_op2_Slot_inst_get (insn) == 8)
12863             return OPCODE_SRC;
12864           if (Field_op2_Slot_inst_get (insn) == 9 &&
12865               Field_s_Slot_inst_get (insn) == 0)
12866             return OPCODE_SRL;
12867           if (Field_op2_Slot_inst_get (insn) == 10 &&
12868               Field_t_Slot_inst_get (insn) == 0)
12869             return OPCODE_SLL;
12870           if (Field_op2_Slot_inst_get (insn) == 11 &&
12871               Field_s_Slot_inst_get (insn) == 0)
12872             return OPCODE_SRA;
12873           if (Field_op2_Slot_inst_get (insn) == 12)
12874             return OPCODE_MUL16U;
12875           if (Field_op2_Slot_inst_get (insn) == 13)
12876             return OPCODE_MUL16S;
12877           if (Field_op2_Slot_inst_get (insn) == 15)
12878             {
12879               if (Field_r_Slot_inst_get (insn) == 0)
12880                 return OPCODE_LICT;
12881               if (Field_r_Slot_inst_get (insn) == 1)
12882                 return OPCODE_SICT;
12883               if (Field_r_Slot_inst_get (insn) == 2)
12884                 return OPCODE_LICW;
12885               if (Field_r_Slot_inst_get (insn) == 3)
12886                 return OPCODE_SICW;
12887               if (Field_r_Slot_inst_get (insn) == 8)
12888                 return OPCODE_LDCT;
12889               if (Field_r_Slot_inst_get (insn) == 9)
12890                 return OPCODE_SDCT;
12891               if (Field_r_Slot_inst_get (insn) == 14 &&
12892                   Field_t_Slot_inst_get (insn) == 0)
12893                 return OPCODE_RFDO;
12894               if (Field_r_Slot_inst_get (insn) == 14 &&
12895                   Field_t_Slot_inst_get (insn) == 1)
12896                 return OPCODE_RFDD;
12897             }
12898         }
12899       if (Field_op1_Slot_inst_get (insn) == 2)
12900         {
12901           if (Field_op2_Slot_inst_get (insn) == 8)
12902             return OPCODE_MULL;
12903           if (Field_op2_Slot_inst_get (insn) == 12)
12904             return OPCODE_QUOU;
12905           if (Field_op2_Slot_inst_get (insn) == 13)
12906             return OPCODE_QUOS;
12907           if (Field_op2_Slot_inst_get (insn) == 14)
12908             return OPCODE_REMU;
12909           if (Field_op2_Slot_inst_get (insn) == 15)
12910             return OPCODE_REMS;
12911         }
12912       if (Field_op1_Slot_inst_get (insn) == 3)
12913         {
12914           if (Field_op2_Slot_inst_get (insn) == 0)
12915             {
12916               if (Field_sr_Slot_inst_get (insn) == 0)
12917                 return OPCODE_RSR_LBEG;
12918               if (Field_sr_Slot_inst_get (insn) == 1)
12919                 return OPCODE_RSR_LEND;
12920               if (Field_sr_Slot_inst_get (insn) == 2)
12921                 return OPCODE_RSR_LCOUNT;
12922               if (Field_sr_Slot_inst_get (insn) == 3)
12923                 return OPCODE_RSR_SAR;
12924               if (Field_sr_Slot_inst_get (insn) == 5)
12925                 return OPCODE_RSR_LITBASE;
12926               if (Field_sr_Slot_inst_get (insn) == 12)
12927                 return OPCODE_RSR_SCOMPARE1;
12928               if (Field_sr_Slot_inst_get (insn) == 16)
12929                 return OPCODE_RSR_ACCLO;
12930               if (Field_sr_Slot_inst_get (insn) == 17)
12931                 return OPCODE_RSR_ACCHI;
12932               if (Field_sr_Slot_inst_get (insn) == 32)
12933                 return OPCODE_RSR_M0;
12934               if (Field_sr_Slot_inst_get (insn) == 33)
12935                 return OPCODE_RSR_M1;
12936               if (Field_sr_Slot_inst_get (insn) == 34)
12937                 return OPCODE_RSR_M2;
12938               if (Field_sr_Slot_inst_get (insn) == 35)
12939                 return OPCODE_RSR_M3;
12940               if (Field_sr_Slot_inst_get (insn) == 72)
12941                 return OPCODE_RSR_WINDOWBASE;
12942               if (Field_sr_Slot_inst_get (insn) == 73)
12943                 return OPCODE_RSR_WINDOWSTART;
12944               if (Field_sr_Slot_inst_get (insn) == 96)
12945                 return OPCODE_RSR_IBREAKENABLE;
12946               if (Field_sr_Slot_inst_get (insn) == 97)
12947                 return OPCODE_RSR_MEMCTL;
12948               if (Field_sr_Slot_inst_get (insn) == 99)
12949                 return OPCODE_RSR_ATOMCTL;
12950               if (Field_sr_Slot_inst_get (insn) == 104)
12951                 return OPCODE_RSR_DDR;
12952               if (Field_sr_Slot_inst_get (insn) == 128)
12953                 return OPCODE_RSR_IBREAKA0;
12954               if (Field_sr_Slot_inst_get (insn) == 129)
12955                 return OPCODE_RSR_IBREAKA1;
12956               if (Field_sr_Slot_inst_get (insn) == 144)
12957                 return OPCODE_RSR_DBREAKA0;
12958               if (Field_sr_Slot_inst_get (insn) == 145)
12959                 return OPCODE_RSR_DBREAKA1;
12960               if (Field_sr_Slot_inst_get (insn) == 160)
12961                 return OPCODE_RSR_DBREAKC0;
12962               if (Field_sr_Slot_inst_get (insn) == 161)
12963                 return OPCODE_RSR_DBREAKC1;
12964               if (Field_sr_Slot_inst_get (insn) == 176)
12965                 return OPCODE_RSR_CONFIGID0;
12966               if (Field_sr_Slot_inst_get (insn) == 177)
12967                 return OPCODE_RSR_EPC1;
12968               if (Field_sr_Slot_inst_get (insn) == 178)
12969                 return OPCODE_RSR_EPC2;
12970               if (Field_sr_Slot_inst_get (insn) == 179)
12971                 return OPCODE_RSR_EPC3;
12972               if (Field_sr_Slot_inst_get (insn) == 180)
12973                 return OPCODE_RSR_EPC4;
12974               if (Field_sr_Slot_inst_get (insn) == 181)
12975                 return OPCODE_RSR_EPC5;
12976               if (Field_sr_Slot_inst_get (insn) == 182)
12977                 return OPCODE_RSR_EPC6;
12978               if (Field_sr_Slot_inst_get (insn) == 183)
12979                 return OPCODE_RSR_EPC7;
12980               if (Field_sr_Slot_inst_get (insn) == 192)
12981                 return OPCODE_RSR_DEPC;
12982               if (Field_sr_Slot_inst_get (insn) == 194)
12983                 return OPCODE_RSR_EPS2;
12984               if (Field_sr_Slot_inst_get (insn) == 195)
12985                 return OPCODE_RSR_EPS3;
12986               if (Field_sr_Slot_inst_get (insn) == 196)
12987                 return OPCODE_RSR_EPS4;
12988               if (Field_sr_Slot_inst_get (insn) == 197)
12989                 return OPCODE_RSR_EPS5;
12990               if (Field_sr_Slot_inst_get (insn) == 198)
12991                 return OPCODE_RSR_EPS6;
12992               if (Field_sr_Slot_inst_get (insn) == 199)
12993                 return OPCODE_RSR_EPS7;
12994               if (Field_sr_Slot_inst_get (insn) == 208)
12995                 return OPCODE_RSR_CONFIGID1;
12996               if (Field_sr_Slot_inst_get (insn) == 209)
12997                 return OPCODE_RSR_EXCSAVE1;
12998               if (Field_sr_Slot_inst_get (insn) == 210)
12999                 return OPCODE_RSR_EXCSAVE2;
13000               if (Field_sr_Slot_inst_get (insn) == 211)
13001                 return OPCODE_RSR_EXCSAVE3;
13002               if (Field_sr_Slot_inst_get (insn) == 212)
13003                 return OPCODE_RSR_EXCSAVE4;
13004               if (Field_sr_Slot_inst_get (insn) == 213)
13005                 return OPCODE_RSR_EXCSAVE5;
13006               if (Field_sr_Slot_inst_get (insn) == 214)
13007                 return OPCODE_RSR_EXCSAVE6;
13008               if (Field_sr_Slot_inst_get (insn) == 215)
13009                 return OPCODE_RSR_EXCSAVE7;
13010               if (Field_sr_Slot_inst_get (insn) == 226)
13011                 return OPCODE_RSR_INTERRUPT;
13012               if (Field_sr_Slot_inst_get (insn) == 228)
13013                 return OPCODE_RSR_INTENABLE;
13014               if (Field_sr_Slot_inst_get (insn) == 230)
13015                 return OPCODE_RSR_PS;
13016               if (Field_sr_Slot_inst_get (insn) == 231)
13017                 return OPCODE_RSR_VECBASE;
13018               if (Field_sr_Slot_inst_get (insn) == 232)
13019                 return OPCODE_RSR_EXCCAUSE;
13020               if (Field_sr_Slot_inst_get (insn) == 233)
13021                 return OPCODE_RSR_DEBUGCAUSE;
13022               if (Field_sr_Slot_inst_get (insn) == 234)
13023                 return OPCODE_RSR_CCOUNT;
13024               if (Field_sr_Slot_inst_get (insn) == 235)
13025                 return OPCODE_RSR_PRID;
13026               if (Field_sr_Slot_inst_get (insn) == 236)
13027                 return OPCODE_RSR_ICOUNT;
13028               if (Field_sr_Slot_inst_get (insn) == 237)
13029                 return OPCODE_RSR_ICOUNTLEVEL;
13030               if (Field_sr_Slot_inst_get (insn) == 238)
13031                 return OPCODE_RSR_EXCVADDR;
13032               if (Field_sr_Slot_inst_get (insn) == 240)
13033                 return OPCODE_RSR_CCOMPARE0;
13034               if (Field_sr_Slot_inst_get (insn) == 241)
13035                 return OPCODE_RSR_CCOMPARE1;
13036               if (Field_sr_Slot_inst_get (insn) == 242)
13037                 return OPCODE_RSR_CCOMPARE2;
13038               if (Field_sr_Slot_inst_get (insn) == 244)
13039                 return OPCODE_RSR_MISC0;
13040               if (Field_sr_Slot_inst_get (insn) == 245)
13041                 return OPCODE_RSR_MISC1;
13042             }
13043           if (Field_op2_Slot_inst_get (insn) == 1)
13044             {
13045               if (Field_sr_Slot_inst_get (insn) == 0)
13046                 return OPCODE_WSR_LBEG;
13047               if (Field_sr_Slot_inst_get (insn) == 1)
13048                 return OPCODE_WSR_LEND;
13049               if (Field_sr_Slot_inst_get (insn) == 2)
13050                 return OPCODE_WSR_LCOUNT;
13051               if (Field_sr_Slot_inst_get (insn) == 3)
13052                 return OPCODE_WSR_SAR;
13053               if (Field_sr_Slot_inst_get (insn) == 5)
13054                 return OPCODE_WSR_LITBASE;
13055               if (Field_sr_Slot_inst_get (insn) == 12)
13056                 return OPCODE_WSR_SCOMPARE1;
13057               if (Field_sr_Slot_inst_get (insn) == 16)
13058                 return OPCODE_WSR_ACCLO;
13059               if (Field_sr_Slot_inst_get (insn) == 17)
13060                 return OPCODE_WSR_ACCHI;
13061               if (Field_sr_Slot_inst_get (insn) == 32)
13062                 return OPCODE_WSR_M0;
13063               if (Field_sr_Slot_inst_get (insn) == 33)
13064                 return OPCODE_WSR_M1;
13065               if (Field_sr_Slot_inst_get (insn) == 34)
13066                 return OPCODE_WSR_M2;
13067               if (Field_sr_Slot_inst_get (insn) == 35)
13068                 return OPCODE_WSR_M3;
13069               if (Field_sr_Slot_inst_get (insn) == 72)
13070                 return OPCODE_WSR_WINDOWBASE;
13071               if (Field_sr_Slot_inst_get (insn) == 73)
13072                 return OPCODE_WSR_WINDOWSTART;
13073               if (Field_sr_Slot_inst_get (insn) == 89)
13074                 return OPCODE_WSR_MMID;
13075               if (Field_sr_Slot_inst_get (insn) == 96)
13076                 return OPCODE_WSR_IBREAKENABLE;
13077               if (Field_sr_Slot_inst_get (insn) == 97)
13078                 return OPCODE_WSR_MEMCTL;
13079               if (Field_sr_Slot_inst_get (insn) == 99)
13080                 return OPCODE_WSR_ATOMCTL;
13081               if (Field_sr_Slot_inst_get (insn) == 104)
13082                 return OPCODE_WSR_DDR;
13083               if (Field_sr_Slot_inst_get (insn) == 128)
13084                 return OPCODE_WSR_IBREAKA0;
13085               if (Field_sr_Slot_inst_get (insn) == 129)
13086                 return OPCODE_WSR_IBREAKA1;
13087               if (Field_sr_Slot_inst_get (insn) == 144)
13088                 return OPCODE_WSR_DBREAKA0;
13089               if (Field_sr_Slot_inst_get (insn) == 145)
13090                 return OPCODE_WSR_DBREAKA1;
13091               if (Field_sr_Slot_inst_get (insn) == 160)
13092                 return OPCODE_WSR_DBREAKC0;
13093               if (Field_sr_Slot_inst_get (insn) == 161)
13094                 return OPCODE_WSR_DBREAKC1;
13095               if (Field_sr_Slot_inst_get (insn) == 176)
13096                 return OPCODE_WSR_CONFIGID0;
13097               if (Field_sr_Slot_inst_get (insn) == 177)
13098                 return OPCODE_WSR_EPC1;
13099               if (Field_sr_Slot_inst_get (insn) == 178)
13100                 return OPCODE_WSR_EPC2;
13101               if (Field_sr_Slot_inst_get (insn) == 179)
13102                 return OPCODE_WSR_EPC3;
13103               if (Field_sr_Slot_inst_get (insn) == 180)
13104                 return OPCODE_WSR_EPC4;
13105               if (Field_sr_Slot_inst_get (insn) == 181)
13106                 return OPCODE_WSR_EPC5;
13107               if (Field_sr_Slot_inst_get (insn) == 182)
13108                 return OPCODE_WSR_EPC6;
13109               if (Field_sr_Slot_inst_get (insn) == 183)
13110                 return OPCODE_WSR_EPC7;
13111               if (Field_sr_Slot_inst_get (insn) == 192)
13112                 return OPCODE_WSR_DEPC;
13113               if (Field_sr_Slot_inst_get (insn) == 194)
13114                 return OPCODE_WSR_EPS2;
13115               if (Field_sr_Slot_inst_get (insn) == 195)
13116                 return OPCODE_WSR_EPS3;
13117               if (Field_sr_Slot_inst_get (insn) == 196)
13118                 return OPCODE_WSR_EPS4;
13119               if (Field_sr_Slot_inst_get (insn) == 197)
13120                 return OPCODE_WSR_EPS5;
13121               if (Field_sr_Slot_inst_get (insn) == 198)
13122                 return OPCODE_WSR_EPS6;
13123               if (Field_sr_Slot_inst_get (insn) == 199)
13124                 return OPCODE_WSR_EPS7;
13125               if (Field_sr_Slot_inst_get (insn) == 209)
13126                 return OPCODE_WSR_EXCSAVE1;
13127               if (Field_sr_Slot_inst_get (insn) == 210)
13128                 return OPCODE_WSR_EXCSAVE2;
13129               if (Field_sr_Slot_inst_get (insn) == 211)
13130                 return OPCODE_WSR_EXCSAVE3;
13131               if (Field_sr_Slot_inst_get (insn) == 212)
13132                 return OPCODE_WSR_EXCSAVE4;
13133               if (Field_sr_Slot_inst_get (insn) == 213)
13134                 return OPCODE_WSR_EXCSAVE5;
13135               if (Field_sr_Slot_inst_get (insn) == 214)
13136                 return OPCODE_WSR_EXCSAVE6;
13137               if (Field_sr_Slot_inst_get (insn) == 215)
13138                 return OPCODE_WSR_EXCSAVE7;
13139               if (Field_sr_Slot_inst_get (insn) == 226)
13140                 return OPCODE_WSR_INTSET;
13141               if (Field_sr_Slot_inst_get (insn) == 227)
13142                 return OPCODE_WSR_INTCLEAR;
13143               if (Field_sr_Slot_inst_get (insn) == 228)
13144                 return OPCODE_WSR_INTENABLE;
13145               if (Field_sr_Slot_inst_get (insn) == 230)
13146                 return OPCODE_WSR_PS;
13147               if (Field_sr_Slot_inst_get (insn) == 231)
13148                 return OPCODE_WSR_VECBASE;
13149               if (Field_sr_Slot_inst_get (insn) == 232)
13150                 return OPCODE_WSR_EXCCAUSE;
13151               if (Field_sr_Slot_inst_get (insn) == 233)
13152                 return OPCODE_WSR_DEBUGCAUSE;
13153               if (Field_sr_Slot_inst_get (insn) == 234)
13154                 return OPCODE_WSR_CCOUNT;
13155               if (Field_sr_Slot_inst_get (insn) == 236)
13156                 return OPCODE_WSR_ICOUNT;
13157               if (Field_sr_Slot_inst_get (insn) == 237)
13158                 return OPCODE_WSR_ICOUNTLEVEL;
13159               if (Field_sr_Slot_inst_get (insn) == 238)
13160                 return OPCODE_WSR_EXCVADDR;
13161               if (Field_sr_Slot_inst_get (insn) == 240)
13162                 return OPCODE_WSR_CCOMPARE0;
13163               if (Field_sr_Slot_inst_get (insn) == 241)
13164                 return OPCODE_WSR_CCOMPARE1;
13165               if (Field_sr_Slot_inst_get (insn) == 242)
13166                 return OPCODE_WSR_CCOMPARE2;
13167               if (Field_sr_Slot_inst_get (insn) == 244)
13168                 return OPCODE_WSR_MISC0;
13169               if (Field_sr_Slot_inst_get (insn) == 245)
13170                 return OPCODE_WSR_MISC1;
13171             }
13172           if (Field_op2_Slot_inst_get (insn) == 2)
13173             return OPCODE_SEXT;
13174           if (Field_op2_Slot_inst_get (insn) == 3)
13175             return OPCODE_CLAMPS;
13176           if (Field_op2_Slot_inst_get (insn) == 4)
13177             return OPCODE_MIN;
13178           if (Field_op2_Slot_inst_get (insn) == 5)
13179             return OPCODE_MAX;
13180           if (Field_op2_Slot_inst_get (insn) == 6)
13181             return OPCODE_MINU;
13182           if (Field_op2_Slot_inst_get (insn) == 7)
13183             return OPCODE_MAXU;
13184           if (Field_op2_Slot_inst_get (insn) == 8)
13185             return OPCODE_MOVEQZ;
13186           if (Field_op2_Slot_inst_get (insn) == 9)
13187             return OPCODE_MOVNEZ;
13188           if (Field_op2_Slot_inst_get (insn) == 10)
13189             return OPCODE_MOVLTZ;
13190           if (Field_op2_Slot_inst_get (insn) == 11)
13191             return OPCODE_MOVGEZ;
13192           if (Field_op2_Slot_inst_get (insn) == 14)
13193             {
13194               if (Field_st_Slot_inst_get (insn) == 230)
13195                 return OPCODE_RUR_EXPSTATE;
13196             }
13197           if (Field_op2_Slot_inst_get (insn) == 15)
13198             {
13199               if (Field_sr_Slot_inst_get (insn) == 230)
13200                 return OPCODE_WUR_EXPSTATE;
13201             }
13202         }
13203       if ((Field_op1_Slot_inst_get (insn) == 4 ||
13204            Field_op1_Slot_inst_get (insn) == 5))
13205         return OPCODE_EXTUI;
13206       if (Field_op1_Slot_inst_get (insn) == 9)
13207         {
13208           if (Field_op2_Slot_inst_get (insn) == 0)
13209             return OPCODE_L32E;
13210           if (Field_op2_Slot_inst_get (insn) == 4)
13211             return OPCODE_S32E;
13212           if (Field_op2_Slot_inst_get (insn) == 5)
13213             return OPCODE_S32NB;
13214         }
13215       if (Field_r_Slot_inst_get (insn) == 0 &&
13216           Field_s_Slot_inst_get (insn) == 0 &&
13217           Field_op2_Slot_inst_get (insn) == 0 &&
13218           Field_op1_Slot_inst_get (insn) == 14)
13219         return OPCODE_READ_IMPWIRE;
13220       if (Field_r_Slot_inst_get (insn) == 1 &&
13221           Field_s3to1_Slot_inst_get (insn) == 0 &&
13222           Field_op2_Slot_inst_get (insn) == 0 &&
13223           Field_op1_Slot_inst_get (insn) == 14)
13224         return OPCODE_SETB_EXPSTATE;
13225       if (Field_r_Slot_inst_get (insn) == 1 &&
13226           Field_s3to1_Slot_inst_get (insn) == 1 &&
13227           Field_op2_Slot_inst_get (insn) == 0 &&
13228           Field_op1_Slot_inst_get (insn) == 14)
13229         return OPCODE_CLRB_EXPSTATE;
13230       if (Field_r_Slot_inst_get (insn) == 2 &&
13231           Field_op2_Slot_inst_get (insn) == 0 &&
13232           Field_op1_Slot_inst_get (insn) == 14)
13233         return OPCODE_WRMSK_EXPSTATE;
13234     }
13235   if (Field_op0_Slot_inst_get (insn) == 1)
13236     return OPCODE_L32R;
13237   if (Field_op0_Slot_inst_get (insn) == 2)
13238     {
13239       if (Field_r_Slot_inst_get (insn) == 0)
13240         return OPCODE_L8UI;
13241       if (Field_r_Slot_inst_get (insn) == 1)
13242         return OPCODE_L16UI;
13243       if (Field_r_Slot_inst_get (insn) == 2)
13244         return OPCODE_L32I;
13245       if (Field_r_Slot_inst_get (insn) == 4)
13246         return OPCODE_S8I;
13247       if (Field_r_Slot_inst_get (insn) == 5)
13248         return OPCODE_S16I;
13249       if (Field_r_Slot_inst_get (insn) == 6)
13250         return OPCODE_S32I;
13251       if (Field_r_Slot_inst_get (insn) == 7)
13252         {
13253           if (Field_t_Slot_inst_get (insn) == 0)
13254             return OPCODE_DPFR;
13255           if (Field_t_Slot_inst_get (insn) == 1)
13256             return OPCODE_DPFW;
13257           if (Field_t_Slot_inst_get (insn) == 2)
13258             return OPCODE_DPFRO;
13259           if (Field_t_Slot_inst_get (insn) == 3)
13260             return OPCODE_DPFWO;
13261           if (Field_t_Slot_inst_get (insn) == 4)
13262             return OPCODE_DHWB;
13263           if (Field_t_Slot_inst_get (insn) == 5)
13264             return OPCODE_DHWBI;
13265           if (Field_t_Slot_inst_get (insn) == 6)
13266             return OPCODE_DHI;
13267           if (Field_t_Slot_inst_get (insn) == 7)
13268             return OPCODE_DII;
13269           if (Field_t_Slot_inst_get (insn) == 8)
13270             {
13271               if (Field_op1_Slot_inst_get (insn) == 0)
13272                 return OPCODE_DPFL;
13273               if (Field_op1_Slot_inst_get (insn) == 2)
13274                 return OPCODE_DHU;
13275               if (Field_op1_Slot_inst_get (insn) == 3)
13276                 return OPCODE_DIU;
13277               if (Field_op1_Slot_inst_get (insn) == 4)
13278                 return OPCODE_DIWB;
13279               if (Field_op1_Slot_inst_get (insn) == 5)
13280                 return OPCODE_DIWBI;
13281               if (Field_op1_Slot_inst_get (insn) == 15 &&
13282                   Field_op2_Slot_inst_get (insn) == 0)
13283                 return OPCODE_DIWBUI_P;
13284             }
13285           if (Field_t_Slot_inst_get (insn) == 12)
13286             return OPCODE_IPF;
13287           if (Field_t_Slot_inst_get (insn) == 13)
13288             {
13289               if (Field_op1_Slot_inst_get (insn) == 0)
13290                 return OPCODE_IPFL;
13291               if (Field_op1_Slot_inst_get (insn) == 2)
13292                 return OPCODE_IHU;
13293               if (Field_op1_Slot_inst_get (insn) == 3)
13294                 return OPCODE_IIU;
13295             }
13296           if (Field_t_Slot_inst_get (insn) == 14)
13297             return OPCODE_IHI;
13298           if (Field_t_Slot_inst_get (insn) == 15)
13299             return OPCODE_III;
13300         }
13301       if (Field_r_Slot_inst_get (insn) == 9)
13302         return OPCODE_L16SI;
13303       if (Field_r_Slot_inst_get (insn) == 10)
13304         return OPCODE_MOVI;
13305       if (Field_r_Slot_inst_get (insn) == 11)
13306         return OPCODE_L32AI;
13307       if (Field_r_Slot_inst_get (insn) == 12)
13308         return OPCODE_ADDI;
13309       if (Field_r_Slot_inst_get (insn) == 13)
13310         return OPCODE_ADDMI;
13311       if (Field_r_Slot_inst_get (insn) == 14)
13312         return OPCODE_S32C1I;
13313       if (Field_r_Slot_inst_get (insn) == 15)
13314         return OPCODE_S32RI;
13315     }
13316   if (Field_op0_Slot_inst_get (insn) == 4)
13317     {
13318       if (Field_op2_Slot_inst_get (insn) == 0)
13319         {
13320           if (Field_op1_Slot_inst_get (insn) == 8 &&
13321               Field_t3_Slot_inst_get (insn) == 0 &&
13322               Field_tlo_Slot_inst_get (insn) == 0 &&
13323               Field_r3_Slot_inst_get (insn) == 0)
13324             return OPCODE_MULA_DD_LL_LDINC;
13325           if (Field_op1_Slot_inst_get (insn) == 9 &&
13326               Field_t3_Slot_inst_get (insn) == 0 &&
13327               Field_tlo_Slot_inst_get (insn) == 0 &&
13328               Field_r3_Slot_inst_get (insn) == 0)
13329             return OPCODE_MULA_DD_HL_LDINC;
13330           if (Field_op1_Slot_inst_get (insn) == 10 &&
13331               Field_t3_Slot_inst_get (insn) == 0 &&
13332               Field_tlo_Slot_inst_get (insn) == 0 &&
13333               Field_r3_Slot_inst_get (insn) == 0)
13334             return OPCODE_MULA_DD_LH_LDINC;
13335           if (Field_op1_Slot_inst_get (insn) == 11 &&
13336               Field_t3_Slot_inst_get (insn) == 0 &&
13337               Field_tlo_Slot_inst_get (insn) == 0 &&
13338               Field_r3_Slot_inst_get (insn) == 0)
13339             return OPCODE_MULA_DD_HH_LDINC;
13340         }
13341       if (Field_op2_Slot_inst_get (insn) == 1)
13342         {
13343           if (Field_op1_Slot_inst_get (insn) == 8 &&
13344               Field_t3_Slot_inst_get (insn) == 0 &&
13345               Field_tlo_Slot_inst_get (insn) == 0 &&
13346               Field_r3_Slot_inst_get (insn) == 0)
13347             return OPCODE_MULA_DD_LL_LDDEC;
13348           if (Field_op1_Slot_inst_get (insn) == 9 &&
13349               Field_t3_Slot_inst_get (insn) == 0 &&
13350               Field_tlo_Slot_inst_get (insn) == 0 &&
13351               Field_r3_Slot_inst_get (insn) == 0)
13352             return OPCODE_MULA_DD_HL_LDDEC;
13353           if (Field_op1_Slot_inst_get (insn) == 10 &&
13354               Field_t3_Slot_inst_get (insn) == 0 &&
13355               Field_tlo_Slot_inst_get (insn) == 0 &&
13356               Field_r3_Slot_inst_get (insn) == 0)
13357             return OPCODE_MULA_DD_LH_LDDEC;
13358           if (Field_op1_Slot_inst_get (insn) == 11 &&
13359               Field_t3_Slot_inst_get (insn) == 0 &&
13360               Field_tlo_Slot_inst_get (insn) == 0 &&
13361               Field_r3_Slot_inst_get (insn) == 0)
13362             return OPCODE_MULA_DD_HH_LDDEC;
13363         }
13364       if (Field_op2_Slot_inst_get (insn) == 2)
13365         {
13366           if (Field_op1_Slot_inst_get (insn) == 4 &&
13367               Field_s_Slot_inst_get (insn) == 0 &&
13368               Field_w_Slot_inst_get (insn) == 0 &&
13369               Field_r3_Slot_inst_get (insn) == 0 &&
13370               Field_t3_Slot_inst_get (insn) == 0 &&
13371               Field_tlo_Slot_inst_get (insn) == 0)
13372             return OPCODE_MUL_DD_LL;
13373           if (Field_op1_Slot_inst_get (insn) == 5 &&
13374               Field_s_Slot_inst_get (insn) == 0 &&
13375               Field_w_Slot_inst_get (insn) == 0 &&
13376               Field_r3_Slot_inst_get (insn) == 0 &&
13377               Field_t3_Slot_inst_get (insn) == 0 &&
13378               Field_tlo_Slot_inst_get (insn) == 0)
13379             return OPCODE_MUL_DD_HL;
13380           if (Field_op1_Slot_inst_get (insn) == 6 &&
13381               Field_s_Slot_inst_get (insn) == 0 &&
13382               Field_w_Slot_inst_get (insn) == 0 &&
13383               Field_r3_Slot_inst_get (insn) == 0 &&
13384               Field_t3_Slot_inst_get (insn) == 0 &&
13385               Field_tlo_Slot_inst_get (insn) == 0)
13386             return OPCODE_MUL_DD_LH;
13387           if (Field_op1_Slot_inst_get (insn) == 7 &&
13388               Field_s_Slot_inst_get (insn) == 0 &&
13389               Field_w_Slot_inst_get (insn) == 0 &&
13390               Field_r3_Slot_inst_get (insn) == 0 &&
13391               Field_t3_Slot_inst_get (insn) == 0 &&
13392               Field_tlo_Slot_inst_get (insn) == 0)
13393             return OPCODE_MUL_DD_HH;
13394           if (Field_op1_Slot_inst_get (insn) == 8 &&
13395               Field_s_Slot_inst_get (insn) == 0 &&
13396               Field_w_Slot_inst_get (insn) == 0 &&
13397               Field_r3_Slot_inst_get (insn) == 0 &&
13398               Field_t3_Slot_inst_get (insn) == 0 &&
13399               Field_tlo_Slot_inst_get (insn) == 0)
13400             return OPCODE_MULA_DD_LL;
13401           if (Field_op1_Slot_inst_get (insn) == 9 &&
13402               Field_s_Slot_inst_get (insn) == 0 &&
13403               Field_w_Slot_inst_get (insn) == 0 &&
13404               Field_r3_Slot_inst_get (insn) == 0 &&
13405               Field_t3_Slot_inst_get (insn) == 0 &&
13406               Field_tlo_Slot_inst_get (insn) == 0)
13407             return OPCODE_MULA_DD_HL;
13408           if (Field_op1_Slot_inst_get (insn) == 10 &&
13409               Field_s_Slot_inst_get (insn) == 0 &&
13410               Field_w_Slot_inst_get (insn) == 0 &&
13411               Field_r3_Slot_inst_get (insn) == 0 &&
13412               Field_t3_Slot_inst_get (insn) == 0 &&
13413               Field_tlo_Slot_inst_get (insn) == 0)
13414             return OPCODE_MULA_DD_LH;
13415           if (Field_op1_Slot_inst_get (insn) == 11 &&
13416               Field_s_Slot_inst_get (insn) == 0 &&
13417               Field_w_Slot_inst_get (insn) == 0 &&
13418               Field_r3_Slot_inst_get (insn) == 0 &&
13419               Field_t3_Slot_inst_get (insn) == 0 &&
13420               Field_tlo_Slot_inst_get (insn) == 0)
13421             return OPCODE_MULA_DD_HH;
13422           if (Field_op1_Slot_inst_get (insn) == 12 &&
13423               Field_s_Slot_inst_get (insn) == 0 &&
13424               Field_w_Slot_inst_get (insn) == 0 &&
13425               Field_r3_Slot_inst_get (insn) == 0 &&
13426               Field_t3_Slot_inst_get (insn) == 0 &&
13427               Field_tlo_Slot_inst_get (insn) == 0)
13428             return OPCODE_MULS_DD_LL;
13429           if (Field_op1_Slot_inst_get (insn) == 13 &&
13430               Field_s_Slot_inst_get (insn) == 0 &&
13431               Field_w_Slot_inst_get (insn) == 0 &&
13432               Field_r3_Slot_inst_get (insn) == 0 &&
13433               Field_t3_Slot_inst_get (insn) == 0 &&
13434               Field_tlo_Slot_inst_get (insn) == 0)
13435             return OPCODE_MULS_DD_HL;
13436           if (Field_op1_Slot_inst_get (insn) == 14 &&
13437               Field_s_Slot_inst_get (insn) == 0 &&
13438               Field_w_Slot_inst_get (insn) == 0 &&
13439               Field_r3_Slot_inst_get (insn) == 0 &&
13440               Field_t3_Slot_inst_get (insn) == 0 &&
13441               Field_tlo_Slot_inst_get (insn) == 0)
13442             return OPCODE_MULS_DD_LH;
13443           if (Field_op1_Slot_inst_get (insn) == 15 &&
13444               Field_s_Slot_inst_get (insn) == 0 &&
13445               Field_w_Slot_inst_get (insn) == 0 &&
13446               Field_r3_Slot_inst_get (insn) == 0 &&
13447               Field_t3_Slot_inst_get (insn) == 0 &&
13448               Field_tlo_Slot_inst_get (insn) == 0)
13449             return OPCODE_MULS_DD_HH;
13450         }
13451       if (Field_op2_Slot_inst_get (insn) == 3)
13452         {
13453           if (Field_op1_Slot_inst_get (insn) == 4 &&
13454               Field_r_Slot_inst_get (insn) == 0 &&
13455               Field_t3_Slot_inst_get (insn) == 0 &&
13456               Field_tlo_Slot_inst_get (insn) == 0)
13457             return OPCODE_MUL_AD_LL;
13458           if (Field_op1_Slot_inst_get (insn) == 5 &&
13459               Field_r_Slot_inst_get (insn) == 0 &&
13460               Field_t3_Slot_inst_get (insn) == 0 &&
13461               Field_tlo_Slot_inst_get (insn) == 0)
13462             return OPCODE_MUL_AD_HL;
13463           if (Field_op1_Slot_inst_get (insn) == 6 &&
13464               Field_r_Slot_inst_get (insn) == 0 &&
13465               Field_t3_Slot_inst_get (insn) == 0 &&
13466               Field_tlo_Slot_inst_get (insn) == 0)
13467             return OPCODE_MUL_AD_LH;
13468           if (Field_op1_Slot_inst_get (insn) == 7 &&
13469               Field_r_Slot_inst_get (insn) == 0 &&
13470               Field_t3_Slot_inst_get (insn) == 0 &&
13471               Field_tlo_Slot_inst_get (insn) == 0)
13472             return OPCODE_MUL_AD_HH;
13473           if (Field_op1_Slot_inst_get (insn) == 8 &&
13474               Field_r_Slot_inst_get (insn) == 0 &&
13475               Field_t3_Slot_inst_get (insn) == 0 &&
13476               Field_tlo_Slot_inst_get (insn) == 0)
13477             return OPCODE_MULA_AD_LL;
13478           if (Field_op1_Slot_inst_get (insn) == 9 &&
13479               Field_r_Slot_inst_get (insn) == 0 &&
13480               Field_t3_Slot_inst_get (insn) == 0 &&
13481               Field_tlo_Slot_inst_get (insn) == 0)
13482             return OPCODE_MULA_AD_HL;
13483           if (Field_op1_Slot_inst_get (insn) == 10 &&
13484               Field_r_Slot_inst_get (insn) == 0 &&
13485               Field_t3_Slot_inst_get (insn) == 0 &&
13486               Field_tlo_Slot_inst_get (insn) == 0)
13487             return OPCODE_MULA_AD_LH;
13488           if (Field_op1_Slot_inst_get (insn) == 11 &&
13489               Field_r_Slot_inst_get (insn) == 0 &&
13490               Field_t3_Slot_inst_get (insn) == 0 &&
13491               Field_tlo_Slot_inst_get (insn) == 0)
13492             return OPCODE_MULA_AD_HH;
13493           if (Field_op1_Slot_inst_get (insn) == 12 &&
13494               Field_r_Slot_inst_get (insn) == 0 &&
13495               Field_t3_Slot_inst_get (insn) == 0 &&
13496               Field_tlo_Slot_inst_get (insn) == 0)
13497             return OPCODE_MULS_AD_LL;
13498           if (Field_op1_Slot_inst_get (insn) == 13 &&
13499               Field_r_Slot_inst_get (insn) == 0 &&
13500               Field_t3_Slot_inst_get (insn) == 0 &&
13501               Field_tlo_Slot_inst_get (insn) == 0)
13502             return OPCODE_MULS_AD_HL;
13503           if (Field_op1_Slot_inst_get (insn) == 14 &&
13504               Field_r_Slot_inst_get (insn) == 0 &&
13505               Field_t3_Slot_inst_get (insn) == 0 &&
13506               Field_tlo_Slot_inst_get (insn) == 0)
13507             return OPCODE_MULS_AD_LH;
13508           if (Field_op1_Slot_inst_get (insn) == 15 &&
13509               Field_r_Slot_inst_get (insn) == 0 &&
13510               Field_t3_Slot_inst_get (insn) == 0 &&
13511               Field_tlo_Slot_inst_get (insn) == 0)
13512             return OPCODE_MULS_AD_HH;
13513         }
13514       if (Field_op2_Slot_inst_get (insn) == 4)
13515         {
13516           if (Field_op1_Slot_inst_get (insn) == 8 &&
13517               Field_r3_Slot_inst_get (insn) == 0)
13518             return OPCODE_MULA_DA_LL_LDINC;
13519           if (Field_op1_Slot_inst_get (insn) == 9 &&
13520               Field_r3_Slot_inst_get (insn) == 0)
13521             return OPCODE_MULA_DA_HL_LDINC;
13522           if (Field_op1_Slot_inst_get (insn) == 10 &&
13523               Field_r3_Slot_inst_get (insn) == 0)
13524             return OPCODE_MULA_DA_LH_LDINC;
13525           if (Field_op1_Slot_inst_get (insn) == 11 &&
13526               Field_r3_Slot_inst_get (insn) == 0)
13527             return OPCODE_MULA_DA_HH_LDINC;
13528         }
13529       if (Field_op2_Slot_inst_get (insn) == 5)
13530         {
13531           if (Field_op1_Slot_inst_get (insn) == 8 &&
13532               Field_r3_Slot_inst_get (insn) == 0)
13533             return OPCODE_MULA_DA_LL_LDDEC;
13534           if (Field_op1_Slot_inst_get (insn) == 9 &&
13535               Field_r3_Slot_inst_get (insn) == 0)
13536             return OPCODE_MULA_DA_HL_LDDEC;
13537           if (Field_op1_Slot_inst_get (insn) == 10 &&
13538               Field_r3_Slot_inst_get (insn) == 0)
13539             return OPCODE_MULA_DA_LH_LDDEC;
13540           if (Field_op1_Slot_inst_get (insn) == 11 &&
13541               Field_r3_Slot_inst_get (insn) == 0)
13542             return OPCODE_MULA_DA_HH_LDDEC;
13543         }
13544       if (Field_op2_Slot_inst_get (insn) == 6)
13545         {
13546           if (Field_op1_Slot_inst_get (insn) == 4 &&
13547               Field_s_Slot_inst_get (insn) == 0 &&
13548               Field_w_Slot_inst_get (insn) == 0 &&
13549               Field_r3_Slot_inst_get (insn) == 0)
13550             return OPCODE_MUL_DA_LL;
13551           if (Field_op1_Slot_inst_get (insn) == 5 &&
13552               Field_s_Slot_inst_get (insn) == 0 &&
13553               Field_w_Slot_inst_get (insn) == 0 &&
13554               Field_r3_Slot_inst_get (insn) == 0)
13555             return OPCODE_MUL_DA_HL;
13556           if (Field_op1_Slot_inst_get (insn) == 6 &&
13557               Field_s_Slot_inst_get (insn) == 0 &&
13558               Field_w_Slot_inst_get (insn) == 0 &&
13559               Field_r3_Slot_inst_get (insn) == 0)
13560             return OPCODE_MUL_DA_LH;
13561           if (Field_op1_Slot_inst_get (insn) == 7 &&
13562               Field_s_Slot_inst_get (insn) == 0 &&
13563               Field_w_Slot_inst_get (insn) == 0 &&
13564               Field_r3_Slot_inst_get (insn) == 0)
13565             return OPCODE_MUL_DA_HH;
13566           if (Field_op1_Slot_inst_get (insn) == 8 &&
13567               Field_s_Slot_inst_get (insn) == 0 &&
13568               Field_w_Slot_inst_get (insn) == 0 &&
13569               Field_r3_Slot_inst_get (insn) == 0)
13570             return OPCODE_MULA_DA_LL;
13571           if (Field_op1_Slot_inst_get (insn) == 9 &&
13572               Field_s_Slot_inst_get (insn) == 0 &&
13573               Field_w_Slot_inst_get (insn) == 0 &&
13574               Field_r3_Slot_inst_get (insn) == 0)
13575             return OPCODE_MULA_DA_HL;
13576           if (Field_op1_Slot_inst_get (insn) == 10 &&
13577               Field_s_Slot_inst_get (insn) == 0 &&
13578               Field_w_Slot_inst_get (insn) == 0 &&
13579               Field_r3_Slot_inst_get (insn) == 0)
13580             return OPCODE_MULA_DA_LH;
13581           if (Field_op1_Slot_inst_get (insn) == 11 &&
13582               Field_s_Slot_inst_get (insn) == 0 &&
13583               Field_w_Slot_inst_get (insn) == 0 &&
13584               Field_r3_Slot_inst_get (insn) == 0)
13585             return OPCODE_MULA_DA_HH;
13586           if (Field_op1_Slot_inst_get (insn) == 12 &&
13587               Field_s_Slot_inst_get (insn) == 0 &&
13588               Field_w_Slot_inst_get (insn) == 0 &&
13589               Field_r3_Slot_inst_get (insn) == 0)
13590             return OPCODE_MULS_DA_LL;
13591           if (Field_op1_Slot_inst_get (insn) == 13 &&
13592               Field_s_Slot_inst_get (insn) == 0 &&
13593               Field_w_Slot_inst_get (insn) == 0 &&
13594               Field_r3_Slot_inst_get (insn) == 0)
13595             return OPCODE_MULS_DA_HL;
13596           if (Field_op1_Slot_inst_get (insn) == 14 &&
13597               Field_s_Slot_inst_get (insn) == 0 &&
13598               Field_w_Slot_inst_get (insn) == 0 &&
13599               Field_r3_Slot_inst_get (insn) == 0)
13600             return OPCODE_MULS_DA_LH;
13601           if (Field_op1_Slot_inst_get (insn) == 15 &&
13602               Field_s_Slot_inst_get (insn) == 0 &&
13603               Field_w_Slot_inst_get (insn) == 0 &&
13604               Field_r3_Slot_inst_get (insn) == 0)
13605             return OPCODE_MULS_DA_HH;
13606         }
13607       if (Field_op2_Slot_inst_get (insn) == 7)
13608         {
13609           if (Field_op1_Slot_inst_get (insn) == 0 &&
13610               Field_r_Slot_inst_get (insn) == 0)
13611             return OPCODE_UMUL_AA_LL;
13612           if (Field_op1_Slot_inst_get (insn) == 1 &&
13613               Field_r_Slot_inst_get (insn) == 0)
13614             return OPCODE_UMUL_AA_HL;
13615           if (Field_op1_Slot_inst_get (insn) == 2 &&
13616               Field_r_Slot_inst_get (insn) == 0)
13617             return OPCODE_UMUL_AA_LH;
13618           if (Field_op1_Slot_inst_get (insn) == 3 &&
13619               Field_r_Slot_inst_get (insn) == 0)
13620             return OPCODE_UMUL_AA_HH;
13621           if (Field_op1_Slot_inst_get (insn) == 4 &&
13622               Field_r_Slot_inst_get (insn) == 0)
13623             return OPCODE_MUL_AA_LL;
13624           if (Field_op1_Slot_inst_get (insn) == 5 &&
13625               Field_r_Slot_inst_get (insn) == 0)
13626             return OPCODE_MUL_AA_HL;
13627           if (Field_op1_Slot_inst_get (insn) == 6 &&
13628               Field_r_Slot_inst_get (insn) == 0)
13629             return OPCODE_MUL_AA_LH;
13630           if (Field_op1_Slot_inst_get (insn) == 7 &&
13631               Field_r_Slot_inst_get (insn) == 0)
13632             return OPCODE_MUL_AA_HH;
13633           if (Field_op1_Slot_inst_get (insn) == 8 &&
13634               Field_r_Slot_inst_get (insn) == 0)
13635             return OPCODE_MULA_AA_LL;
13636           if (Field_op1_Slot_inst_get (insn) == 9 &&
13637               Field_r_Slot_inst_get (insn) == 0)
13638             return OPCODE_MULA_AA_HL;
13639           if (Field_op1_Slot_inst_get (insn) == 10 &&
13640               Field_r_Slot_inst_get (insn) == 0)
13641             return OPCODE_MULA_AA_LH;
13642           if (Field_op1_Slot_inst_get (insn) == 11 &&
13643               Field_r_Slot_inst_get (insn) == 0)
13644             return OPCODE_MULA_AA_HH;
13645           if (Field_op1_Slot_inst_get (insn) == 12 &&
13646               Field_r_Slot_inst_get (insn) == 0)
13647             return OPCODE_MULS_AA_LL;
13648           if (Field_op1_Slot_inst_get (insn) == 13 &&
13649               Field_r_Slot_inst_get (insn) == 0)
13650             return OPCODE_MULS_AA_HL;
13651           if (Field_op1_Slot_inst_get (insn) == 14 &&
13652               Field_r_Slot_inst_get (insn) == 0)
13653             return OPCODE_MULS_AA_LH;
13654           if (Field_op1_Slot_inst_get (insn) == 15 &&
13655               Field_r_Slot_inst_get (insn) == 0)
13656             return OPCODE_MULS_AA_HH;
13657         }
13658       if (Field_op2_Slot_inst_get (insn) == 8)
13659         {
13660           if (Field_op1_Slot_inst_get (insn) == 0 &&
13661               Field_t_Slot_inst_get (insn) == 0 &&
13662               Field_rhi_Slot_inst_get (insn) == 0)
13663             return OPCODE_LDINC;
13664         }
13665       if (Field_op2_Slot_inst_get (insn) == 9)
13666         {
13667           if (Field_op1_Slot_inst_get (insn) == 0 &&
13668               Field_t_Slot_inst_get (insn) == 0 &&
13669               Field_rhi_Slot_inst_get (insn) == 0)
13670             return OPCODE_LDDEC;
13671         }
13672     }
13673   if (Field_op0_Slot_inst_get (insn) == 5)
13674     {
13675       if (Field_n_Slot_inst_get (insn) == 0)
13676         return OPCODE_CALL0;
13677       if (Field_n_Slot_inst_get (insn) == 1)
13678         return OPCODE_CALL4;
13679       if (Field_n_Slot_inst_get (insn) == 2)
13680         return OPCODE_CALL8;
13681       if (Field_n_Slot_inst_get (insn) == 3)
13682         return OPCODE_CALL12;
13683     }
13684   if (Field_op0_Slot_inst_get (insn) == 6)
13685     {
13686       if (Field_n_Slot_inst_get (insn) == 0)
13687         return OPCODE_J;
13688       if (Field_n_Slot_inst_get (insn) == 1)
13689         {
13690           if (Field_m_Slot_inst_get (insn) == 0)
13691             return OPCODE_BEQZ;
13692           if (Field_m_Slot_inst_get (insn) == 1)
13693             return OPCODE_BNEZ;
13694           if (Field_m_Slot_inst_get (insn) == 2)
13695             return OPCODE_BLTZ;
13696           if (Field_m_Slot_inst_get (insn) == 3)
13697             return OPCODE_BGEZ;
13698         }
13699       if (Field_n_Slot_inst_get (insn) == 2)
13700         {
13701           if (Field_m_Slot_inst_get (insn) == 0)
13702             return OPCODE_BEQI;
13703           if (Field_m_Slot_inst_get (insn) == 1)
13704             return OPCODE_BNEI;
13705           if (Field_m_Slot_inst_get (insn) == 2)
13706             return OPCODE_BLTI;
13707           if (Field_m_Slot_inst_get (insn) == 3)
13708             return OPCODE_BGEI;
13709         }
13710       if (Field_n_Slot_inst_get (insn) == 3)
13711         {
13712           if (Field_m_Slot_inst_get (insn) == 0)
13713             return OPCODE_ENTRY;
13714           if (Field_m_Slot_inst_get (insn) == 1)
13715             {
13716               if (Field_r_Slot_inst_get (insn) == 8)
13717                 return OPCODE_LOOP;
13718               if (Field_r_Slot_inst_get (insn) == 9)
13719                 return OPCODE_LOOPNEZ;
13720               if (Field_r_Slot_inst_get (insn) == 10)
13721                 return OPCODE_LOOPGTZ;
13722             }
13723           if (Field_m_Slot_inst_get (insn) == 2)
13724             return OPCODE_BLTUI;
13725           if (Field_m_Slot_inst_get (insn) == 3)
13726             return OPCODE_BGEUI;
13727         }
13728     }
13729   if (Field_op0_Slot_inst_get (insn) == 7)
13730     {
13731       if (Field_r_Slot_inst_get (insn) == 0)
13732         return OPCODE_BNONE;
13733       if (Field_r_Slot_inst_get (insn) == 1)
13734         return OPCODE_BEQ;
13735       if (Field_r_Slot_inst_get (insn) == 2)
13736         return OPCODE_BLT;
13737       if (Field_r_Slot_inst_get (insn) == 3)
13738         return OPCODE_BLTU;
13739       if (Field_r_Slot_inst_get (insn) == 4)
13740         return OPCODE_BALL;
13741       if (Field_r_Slot_inst_get (insn) == 5)
13742         return OPCODE_BBC;
13743       if ((Field_r_Slot_inst_get (insn) == 6 ||
13744            Field_r_Slot_inst_get (insn) == 7))
13745         return OPCODE_BBCI;
13746       if (Field_r_Slot_inst_get (insn) == 8)
13747         return OPCODE_BANY;
13748       if (Field_r_Slot_inst_get (insn) == 9)
13749         return OPCODE_BNE;
13750       if (Field_r_Slot_inst_get (insn) == 10)
13751         return OPCODE_BGE;
13752       if (Field_r_Slot_inst_get (insn) == 11)
13753         return OPCODE_BGEU;
13754       if (Field_r_Slot_inst_get (insn) == 12)
13755         return OPCODE_BNALL;
13756       if (Field_r_Slot_inst_get (insn) == 13)
13757         return OPCODE_BBS;
13758       if ((Field_r_Slot_inst_get (insn) == 14 ||
13759            Field_r_Slot_inst_get (insn) == 15))
13760         return OPCODE_BBSI;
13761     }
13762   return XTENSA_UNDEFINED;
13763 }
13764
13765 static int
13766 Slot_inst16b_decode (const xtensa_insnbuf insn)
13767 {
13768   if (Field_op0_Slot_inst16b_get (insn) == 12)
13769     {
13770       if (Field_i_Slot_inst16b_get (insn) == 0)
13771         return OPCODE_MOVI_N;
13772       if (Field_i_Slot_inst16b_get (insn) == 1)
13773         {
13774           if (Field_z_Slot_inst16b_get (insn) == 0)
13775             return OPCODE_BEQZ_N;
13776           if (Field_z_Slot_inst16b_get (insn) == 1)
13777             return OPCODE_BNEZ_N;
13778         }
13779     }
13780   if (Field_op0_Slot_inst16b_get (insn) == 13)
13781     {
13782       if (Field_r_Slot_inst16b_get (insn) == 0)
13783         return OPCODE_MOV_N;
13784       if (Field_r_Slot_inst16b_get (insn) == 15)
13785         {
13786           if (Field_t_Slot_inst16b_get (insn) == 0)
13787             return OPCODE_RET_N;
13788           if (Field_t_Slot_inst16b_get (insn) == 1)
13789             return OPCODE_RETW_N;
13790           if (Field_t_Slot_inst16b_get (insn) == 2)
13791             return OPCODE_BREAK_N;
13792           if (Field_t_Slot_inst16b_get (insn) == 3 &&
13793               Field_s_Slot_inst16b_get (insn) == 0)
13794             return OPCODE_NOP_N;
13795           if (Field_t_Slot_inst16b_get (insn) == 6 &&
13796               Field_s_Slot_inst16b_get (insn) == 0)
13797             return OPCODE_ILL_N;
13798         }
13799     }
13800   return XTENSA_UNDEFINED;
13801 }
13802
13803 static int
13804 Slot_inst16a_decode (const xtensa_insnbuf insn)
13805 {
13806   if (Field_op0_Slot_inst16a_get (insn) == 8)
13807     return OPCODE_L32I_N;
13808   if (Field_op0_Slot_inst16a_get (insn) == 9)
13809     return OPCODE_S32I_N;
13810   if (Field_op0_Slot_inst16a_get (insn) == 10)
13811     return OPCODE_ADD_N;
13812   if (Field_op0_Slot_inst16a_get (insn) == 11)
13813     return OPCODE_ADDI_N;
13814   return XTENSA_UNDEFINED;
13815 }
13816
13817 \f
13818 /* Instruction slots.  */
13819
13820 static void
13821 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
13822                             xtensa_insnbuf slotbuf)
13823 {
13824   slotbuf[0] = (insn[0] & 0xffffff);
13825 }
13826
13827 static void
13828 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
13829                             const xtensa_insnbuf slotbuf)
13830 {
13831   insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
13832 }
13833
13834 static void
13835 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
13836                                 xtensa_insnbuf slotbuf)
13837 {
13838   slotbuf[0] = (insn[0] & 0xffff);
13839 }
13840
13841 static void
13842 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
13843                                 const xtensa_insnbuf slotbuf)
13844 {
13845   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13846 }
13847
13848 static void
13849 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
13850                                 xtensa_insnbuf slotbuf)
13851 {
13852   slotbuf[0] = (insn[0] & 0xffff);
13853 }
13854
13855 static void
13856 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
13857                                 const xtensa_insnbuf slotbuf)
13858 {
13859   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
13860 }
13861
13862 static xtensa_get_field_fn
13863 Slot_inst_get_field_fns[] = {
13864   Field_t_Slot_inst_get,
13865   Field_bbi4_Slot_inst_get,
13866   Field_bbi_Slot_inst_get,
13867   Field_imm12_Slot_inst_get,
13868   Field_imm8_Slot_inst_get,
13869   Field_s_Slot_inst_get,
13870   Field_imm12b_Slot_inst_get,
13871   Field_imm16_Slot_inst_get,
13872   Field_m_Slot_inst_get,
13873   Field_n_Slot_inst_get,
13874   Field_offset_Slot_inst_get,
13875   Field_op0_Slot_inst_get,
13876   Field_op1_Slot_inst_get,
13877   Field_op2_Slot_inst_get,
13878   Field_r_Slot_inst_get,
13879   Field_sa4_Slot_inst_get,
13880   Field_sae4_Slot_inst_get,
13881   Field_sae_Slot_inst_get,
13882   Field_sal_Slot_inst_get,
13883   Field_sargt_Slot_inst_get,
13884   Field_sas4_Slot_inst_get,
13885   Field_sas_Slot_inst_get,
13886   Field_sr_Slot_inst_get,
13887   Field_st_Slot_inst_get,
13888   Field_thi3_Slot_inst_get,
13889   Field_imm4_Slot_inst_get,
13890   Field_mn_Slot_inst_get,
13891   0,
13892   0,
13893   0,
13894   0,
13895   0,
13896   0,
13897   0,
13898   0,
13899   Field_r3_Slot_inst_get,
13900   Field_rbit2_Slot_inst_get,
13901   Field_rhi_Slot_inst_get,
13902   Field_t3_Slot_inst_get,
13903   Field_tbit2_Slot_inst_get,
13904   Field_tlo_Slot_inst_get,
13905   Field_w_Slot_inst_get,
13906   Field_y_Slot_inst_get,
13907   Field_x_Slot_inst_get,
13908   Field_xt_wbr15_imm_Slot_inst_get,
13909   Field_xt_wbr18_imm_Slot_inst_get,
13910   Field_bitindex_Slot_inst_get,
13911   Field_s3to1_Slot_inst_get,
13912   Implicit_Field_ar0_get,
13913   Implicit_Field_ar4_get,
13914   Implicit_Field_ar8_get,
13915   Implicit_Field_ar12_get,
13916   Implicit_Field_mr0_get,
13917   Implicit_Field_mr1_get,
13918   Implicit_Field_mr2_get,
13919   Implicit_Field_mr3_get
13920 };
13921
13922 static xtensa_set_field_fn
13923 Slot_inst_set_field_fns[] = {
13924   Field_t_Slot_inst_set,
13925   Field_bbi4_Slot_inst_set,
13926   Field_bbi_Slot_inst_set,
13927   Field_imm12_Slot_inst_set,
13928   Field_imm8_Slot_inst_set,
13929   Field_s_Slot_inst_set,
13930   Field_imm12b_Slot_inst_set,
13931   Field_imm16_Slot_inst_set,
13932   Field_m_Slot_inst_set,
13933   Field_n_Slot_inst_set,
13934   Field_offset_Slot_inst_set,
13935   Field_op0_Slot_inst_set,
13936   Field_op1_Slot_inst_set,
13937   Field_op2_Slot_inst_set,
13938   Field_r_Slot_inst_set,
13939   Field_sa4_Slot_inst_set,
13940   Field_sae4_Slot_inst_set,
13941   Field_sae_Slot_inst_set,
13942   Field_sal_Slot_inst_set,
13943   Field_sargt_Slot_inst_set,
13944   Field_sas4_Slot_inst_set,
13945   Field_sas_Slot_inst_set,
13946   Field_sr_Slot_inst_set,
13947   Field_st_Slot_inst_set,
13948   Field_thi3_Slot_inst_set,
13949   Field_imm4_Slot_inst_set,
13950   Field_mn_Slot_inst_set,
13951   0,
13952   0,
13953   0,
13954   0,
13955   0,
13956   0,
13957   0,
13958   0,
13959   Field_r3_Slot_inst_set,
13960   Field_rbit2_Slot_inst_set,
13961   Field_rhi_Slot_inst_set,
13962   Field_t3_Slot_inst_set,
13963   Field_tbit2_Slot_inst_set,
13964   Field_tlo_Slot_inst_set,
13965   Field_w_Slot_inst_set,
13966   Field_y_Slot_inst_set,
13967   Field_x_Slot_inst_set,
13968   Field_xt_wbr15_imm_Slot_inst_set,
13969   Field_xt_wbr18_imm_Slot_inst_set,
13970   Field_bitindex_Slot_inst_set,
13971   Field_s3to1_Slot_inst_set,
13972   Implicit_Field_set,
13973   Implicit_Field_set,
13974   Implicit_Field_set,
13975   Implicit_Field_set,
13976   Implicit_Field_set,
13977   Implicit_Field_set,
13978   Implicit_Field_set,
13979   Implicit_Field_set
13980 };
13981
13982 static xtensa_get_field_fn
13983 Slot_inst16a_get_field_fns[] = {
13984   Field_t_Slot_inst16a_get,
13985   0,
13986   0,
13987   0,
13988   0,
13989   Field_s_Slot_inst16a_get,
13990   0,
13991   0,
13992   0,
13993   0,
13994   0,
13995   Field_op0_Slot_inst16a_get,
13996   0,
13997   0,
13998   Field_r_Slot_inst16a_get,
13999   0,
14000   0,
14001   0,
14002   0,
14003   0,
14004   0,
14005   0,
14006   Field_sr_Slot_inst16a_get,
14007   Field_st_Slot_inst16a_get,
14008   0,
14009   Field_imm4_Slot_inst16a_get,
14010   0,
14011   Field_i_Slot_inst16a_get,
14012   Field_imm6lo_Slot_inst16a_get,
14013   Field_imm6hi_Slot_inst16a_get,
14014   Field_imm7lo_Slot_inst16a_get,
14015   Field_imm7hi_Slot_inst16a_get,
14016   Field_z_Slot_inst16a_get,
14017   Field_imm6_Slot_inst16a_get,
14018   Field_imm7_Slot_inst16a_get,
14019   0,
14020   0,
14021   0,
14022   0,
14023   0,
14024   0,
14025   0,
14026   0,
14027   0,
14028   0,
14029   0,
14030   Field_bitindex_Slot_inst16a_get,
14031   Field_s3to1_Slot_inst16a_get,
14032   Implicit_Field_ar0_get,
14033   Implicit_Field_ar4_get,
14034   Implicit_Field_ar8_get,
14035   Implicit_Field_ar12_get,
14036   Implicit_Field_mr0_get,
14037   Implicit_Field_mr1_get,
14038   Implicit_Field_mr2_get,
14039   Implicit_Field_mr3_get
14040 };
14041
14042 static xtensa_set_field_fn
14043 Slot_inst16a_set_field_fns[] = {
14044   Field_t_Slot_inst16a_set,
14045   0,
14046   0,
14047   0,
14048   0,
14049   Field_s_Slot_inst16a_set,
14050   0,
14051   0,
14052   0,
14053   0,
14054   0,
14055   Field_op0_Slot_inst16a_set,
14056   0,
14057   0,
14058   Field_r_Slot_inst16a_set,
14059   0,
14060   0,
14061   0,
14062   0,
14063   0,
14064   0,
14065   0,
14066   Field_sr_Slot_inst16a_set,
14067   Field_st_Slot_inst16a_set,
14068   0,
14069   Field_imm4_Slot_inst16a_set,
14070   0,
14071   Field_i_Slot_inst16a_set,
14072   Field_imm6lo_Slot_inst16a_set,
14073   Field_imm6hi_Slot_inst16a_set,
14074   Field_imm7lo_Slot_inst16a_set,
14075   Field_imm7hi_Slot_inst16a_set,
14076   Field_z_Slot_inst16a_set,
14077   Field_imm6_Slot_inst16a_set,
14078   Field_imm7_Slot_inst16a_set,
14079   0,
14080   0,
14081   0,
14082   0,
14083   0,
14084   0,
14085   0,
14086   0,
14087   0,
14088   0,
14089   0,
14090   Field_bitindex_Slot_inst16a_set,
14091   Field_s3to1_Slot_inst16a_set,
14092   Implicit_Field_set,
14093   Implicit_Field_set,
14094   Implicit_Field_set,
14095   Implicit_Field_set,
14096   Implicit_Field_set,
14097   Implicit_Field_set,
14098   Implicit_Field_set,
14099   Implicit_Field_set
14100 };
14101
14102 static xtensa_get_field_fn
14103 Slot_inst16b_get_field_fns[] = {
14104   Field_t_Slot_inst16b_get,
14105   0,
14106   0,
14107   0,
14108   0,
14109   Field_s_Slot_inst16b_get,
14110   0,
14111   0,
14112   0,
14113   0,
14114   0,
14115   Field_op0_Slot_inst16b_get,
14116   0,
14117   0,
14118   Field_r_Slot_inst16b_get,
14119   0,
14120   0,
14121   0,
14122   0,
14123   0,
14124   0,
14125   0,
14126   Field_sr_Slot_inst16b_get,
14127   Field_st_Slot_inst16b_get,
14128   0,
14129   Field_imm4_Slot_inst16b_get,
14130   0,
14131   Field_i_Slot_inst16b_get,
14132   Field_imm6lo_Slot_inst16b_get,
14133   Field_imm6hi_Slot_inst16b_get,
14134   Field_imm7lo_Slot_inst16b_get,
14135   Field_imm7hi_Slot_inst16b_get,
14136   Field_z_Slot_inst16b_get,
14137   Field_imm6_Slot_inst16b_get,
14138   Field_imm7_Slot_inst16b_get,
14139   0,
14140   0,
14141   0,
14142   0,
14143   0,
14144   0,
14145   0,
14146   0,
14147   0,
14148   0,
14149   0,
14150   Field_bitindex_Slot_inst16b_get,
14151   Field_s3to1_Slot_inst16b_get,
14152   Implicit_Field_ar0_get,
14153   Implicit_Field_ar4_get,
14154   Implicit_Field_ar8_get,
14155   Implicit_Field_ar12_get,
14156   Implicit_Field_mr0_get,
14157   Implicit_Field_mr1_get,
14158   Implicit_Field_mr2_get,
14159   Implicit_Field_mr3_get
14160 };
14161
14162 static xtensa_set_field_fn
14163 Slot_inst16b_set_field_fns[] = {
14164   Field_t_Slot_inst16b_set,
14165   0,
14166   0,
14167   0,
14168   0,
14169   Field_s_Slot_inst16b_set,
14170   0,
14171   0,
14172   0,
14173   0,
14174   0,
14175   Field_op0_Slot_inst16b_set,
14176   0,
14177   0,
14178   Field_r_Slot_inst16b_set,
14179   0,
14180   0,
14181   0,
14182   0,
14183   0,
14184   0,
14185   0,
14186   Field_sr_Slot_inst16b_set,
14187   Field_st_Slot_inst16b_set,
14188   0,
14189   Field_imm4_Slot_inst16b_set,
14190   0,
14191   Field_i_Slot_inst16b_set,
14192   Field_imm6lo_Slot_inst16b_set,
14193   Field_imm6hi_Slot_inst16b_set,
14194   Field_imm7lo_Slot_inst16b_set,
14195   Field_imm7hi_Slot_inst16b_set,
14196   Field_z_Slot_inst16b_set,
14197   Field_imm6_Slot_inst16b_set,
14198   Field_imm7_Slot_inst16b_set,
14199   0,
14200   0,
14201   0,
14202   0,
14203   0,
14204   0,
14205   0,
14206   0,
14207   0,
14208   0,
14209   0,
14210   Field_bitindex_Slot_inst16b_set,
14211   Field_s3to1_Slot_inst16b_set,
14212   Implicit_Field_set,
14213   Implicit_Field_set,
14214   Implicit_Field_set,
14215   Implicit_Field_set,
14216   Implicit_Field_set,
14217   Implicit_Field_set,
14218   Implicit_Field_set,
14219   Implicit_Field_set
14220 };
14221
14222 static xtensa_slot_internal slots[] = {
14223   { "Inst", "x24", 0,
14224     Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
14225     Slot_inst_get_field_fns, Slot_inst_set_field_fns,
14226     Slot_inst_decode, "nop" },
14227   { "Inst16a", "x16a", 0,
14228     Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
14229     Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
14230     Slot_inst16a_decode, "" },
14231   { "Inst16b", "x16b", 0,
14232     Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
14233     Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
14234     Slot_inst16b_decode, "nop.n" }
14235 };
14236
14237 \f
14238 /* Instruction formats.  */
14239
14240 static void
14241 Format_x24_encode (xtensa_insnbuf insn)
14242 {
14243   insn[0] = 0;
14244 }
14245
14246 static void
14247 Format_x16a_encode (xtensa_insnbuf insn)
14248 {
14249   insn[0] = 0x8;
14250 }
14251
14252 static void
14253 Format_x16b_encode (xtensa_insnbuf insn)
14254 {
14255   insn[0] = 0xc;
14256 }
14257
14258 static int Format_x24_slots[] = { 0 };
14259
14260 static int Format_x16a_slots[] = { 1 };
14261
14262 static int Format_x16b_slots[] = { 2 };
14263
14264 static xtensa_format_internal formats[] = {
14265   { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
14266   { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
14267   { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
14268 };
14269
14270
14271 static int
14272 format_decoder (const xtensa_insnbuf insn)
14273 {
14274   if ((insn[0] & 0x8) == 0)
14275     return 0; /* x24 */
14276   if ((insn[0] & 0xc) == 0x8)
14277     return 1; /* x16a */
14278   if ((insn[0] & 0xe) == 0xc)
14279     return 2; /* x16b */
14280   return -1;
14281 }
14282
14283 static int length_table[256] = {
14284   3,
14285   3,
14286   3,
14287   3,
14288   3,
14289   3,
14290   3,
14291   3,
14292   2,
14293   2,
14294   2,
14295   2,
14296   2,
14297   2,
14298   -1,
14299   -1,
14300   3,
14301   3,
14302   3,
14303   3,
14304   3,
14305   3,
14306   3,
14307   3,
14308   2,
14309   2,
14310   2,
14311   2,
14312   2,
14313   2,
14314   -1,
14315   -1,
14316   3,
14317   3,
14318   3,
14319   3,
14320   3,
14321   3,
14322   3,
14323   3,
14324   2,
14325   2,
14326   2,
14327   2,
14328   2,
14329   2,
14330   -1,
14331   -1,
14332   3,
14333   3,
14334   3,
14335   3,
14336   3,
14337   3,
14338   3,
14339   3,
14340   2,
14341   2,
14342   2,
14343   2,
14344   2,
14345   2,
14346   -1,
14347   -1,
14348   3,
14349   3,
14350   3,
14351   3,
14352   3,
14353   3,
14354   3,
14355   3,
14356   2,
14357   2,
14358   2,
14359   2,
14360   2,
14361   2,
14362   -1,
14363   -1,
14364   3,
14365   3,
14366   3,
14367   3,
14368   3,
14369   3,
14370   3,
14371   3,
14372   2,
14373   2,
14374   2,
14375   2,
14376   2,
14377   2,
14378   -1,
14379   -1,
14380   3,
14381   3,
14382   3,
14383   3,
14384   3,
14385   3,
14386   3,
14387   3,
14388   2,
14389   2,
14390   2,
14391   2,
14392   2,
14393   2,
14394   -1,
14395   -1,
14396   3,
14397   3,
14398   3,
14399   3,
14400   3,
14401   3,
14402   3,
14403   3,
14404   2,
14405   2,
14406   2,
14407   2,
14408   2,
14409   2,
14410   -1,
14411   -1,
14412   3,
14413   3,
14414   3,
14415   3,
14416   3,
14417   3,
14418   3,
14419   3,
14420   2,
14421   2,
14422   2,
14423   2,
14424   2,
14425   2,
14426   -1,
14427   -1,
14428   3,
14429   3,
14430   3,
14431   3,
14432   3,
14433   3,
14434   3,
14435   3,
14436   2,
14437   2,
14438   2,
14439   2,
14440   2,
14441   2,
14442   -1,
14443   -1,
14444   3,
14445   3,
14446   3,
14447   3,
14448   3,
14449   3,
14450   3,
14451   3,
14452   2,
14453   2,
14454   2,
14455   2,
14456   2,
14457   2,
14458   -1,
14459   -1,
14460   3,
14461   3,
14462   3,
14463   3,
14464   3,
14465   3,
14466   3,
14467   3,
14468   2,
14469   2,
14470   2,
14471   2,
14472   2,
14473   2,
14474   -1,
14475   -1,
14476   3,
14477   3,
14478   3,
14479   3,
14480   3,
14481   3,
14482   3,
14483   3,
14484   2,
14485   2,
14486   2,
14487   2,
14488   2,
14489   2,
14490   -1,
14491   -1,
14492   3,
14493   3,
14494   3,
14495   3,
14496   3,
14497   3,
14498   3,
14499   3,
14500   2,
14501   2,
14502   2,
14503   2,
14504   2,
14505   2,
14506   -1,
14507   -1,
14508   3,
14509   3,
14510   3,
14511   3,
14512   3,
14513   3,
14514   3,
14515   3,
14516   2,
14517   2,
14518   2,
14519   2,
14520   2,
14521   2,
14522   -1,
14523   -1,
14524   3,
14525   3,
14526   3,
14527   3,
14528   3,
14529   3,
14530   3,
14531   3,
14532   2,
14533   2,
14534   2,
14535   2,
14536   2,
14537   2,
14538   -1,
14539   -1
14540 };
14541
14542 static int
14543 length_decoder (const unsigned char *insn)
14544 {
14545   int l = insn[0];
14546   return length_table[l];
14547 }
14548
14549 \f
14550 /* Top-level ISA structure.  */
14551
14552 xtensa_isa_internal xtensa_modules = {
14553   0 /* little-endian */,
14554   3 /* insn_size */, 0,
14555   3, formats, format_decoder, length_decoder,
14556   3, slots,
14557   56 /* num_fields */,
14558   94, operands,
14559   313, iclasses,
14560   439, opcodes, 0,
14561   2, regfiles,
14562   NUM_STATES, states, 0,
14563   NUM_SYSREGS, sysregs, 0,
14564   { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
14565   6, interfaces, 0,
14566   0, funcUnits, 0
14567 };