target/xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef XTENSA_CPU_H
  29 #define XTENSA_CPU_H
  30
  31 #include "qemu-common.h"
  32 #include "cpu-qom.h"
  33 #include "exec/cpu-defs.h"
  34 #include "xtensa-isa.h"
  35
  36 #define ALIGNED_ONLY
  37
  38 /* Xtensa processors have a weak memory model */
  39 #define TCG_GUEST_DEFAULT_MO      (0)
  40
  41 enum {
  42     /* Additional instructions */
  43     XTENSA_OPTION_CODE_DENSITY,
  44     XTENSA_OPTION_LOOP,
  45     XTENSA_OPTION_EXTENDED_L32R,
  46     XTENSA_OPTION_16_BIT_IMUL,
  47     XTENSA_OPTION_32_BIT_IMUL,
  48     XTENSA_OPTION_32_BIT_IMUL_HIGH,
  49     XTENSA_OPTION_32_BIT_IDIV,
  50     XTENSA_OPTION_MAC16,
  51     XTENSA_OPTION_MISC_OP_NSA,
  52     XTENSA_OPTION_MISC_OP_MINMAX,
  53     XTENSA_OPTION_MISC_OP_SEXT,
  54     XTENSA_OPTION_MISC_OP_CLAMPS,
  55     XTENSA_OPTION_COPROCESSOR,
  56     XTENSA_OPTION_BOOLEAN,
  57     XTENSA_OPTION_FP_COPROCESSOR,
  58     XTENSA_OPTION_MP_SYNCHRO,
  59     XTENSA_OPTION_CONDITIONAL_STORE,
  60     XTENSA_OPTION_ATOMCTL,
  61     XTENSA_OPTION_DEPBITS,
  62
  63     /* Interrupts and exceptions */
  64     XTENSA_OPTION_EXCEPTION,
  65     XTENSA_OPTION_RELOCATABLE_VECTOR,
  66     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  67     XTENSA_OPTION_INTERRUPT,
  68     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  69     XTENSA_OPTION_TIMER_INTERRUPT,
  70
  71     /* Local memory */
  72     XTENSA_OPTION_ICACHE,
  73     XTENSA_OPTION_ICACHE_TEST,
  74     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  75     XTENSA_OPTION_DCACHE,
  76     XTENSA_OPTION_DCACHE_TEST,
  77     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  78     XTENSA_OPTION_IRAM,
  79     XTENSA_OPTION_IROM,
  80     XTENSA_OPTION_DRAM,
  81     XTENSA_OPTION_DROM,
  82     XTENSA_OPTION_XLMI,
  83     XTENSA_OPTION_HW_ALIGNMENT,
  84     XTENSA_OPTION_MEMORY_ECC_PARITY,
  85
  86     /* Memory protection and translation */
  87     XTENSA_OPTION_REGION_PROTECTION,
  88     XTENSA_OPTION_REGION_TRANSLATION,
  89     XTENSA_OPTION_MPU,
  90     XTENSA_OPTION_MMU,
  91     XTENSA_OPTION_CACHEATTR,
  92
  93     /* Other */
  94     XTENSA_OPTION_WINDOWED_REGISTER,
  95     XTENSA_OPTION_PROCESSOR_INTERFACE,
  96     XTENSA_OPTION_MISC_SR,
  97     XTENSA_OPTION_THREAD_POINTER,
  98     XTENSA_OPTION_PROCESSOR_ID,
  99     XTENSA_OPTION_DEBUG,
 100     XTENSA_OPTION_TRACE_PORT,
 101     XTENSA_OPTION_EXTERN_REGS,
 102 };
 103
 104 enum {
 105     EXPSTATE = 230,
 106     THREADPTR = 231,
 107     FCR = 232,
 108     FSR = 233,
 109 };
 110
 111 enum {
 112     LBEG = 0,
 113     LEND = 1,
 114     LCOUNT = 2,
 115     SAR = 3,
 116     BR = 4,
 117     LITBASE = 5,
 118     SCOMPARE1 = 12,
 119     ACCLO = 16,
 120     ACCHI = 17,
 121     MR = 32,
 122     PREFCTL = 40,
 123     WINDOW_BASE = 72,
 124     WINDOW_START = 73,
 125     PTEVADDR = 83,
 126     MMID = 89,
 127     RASID = 90,
 128     MPUENB = 90,
 129     ITLBCFG = 91,
 130     DTLBCFG = 92,
 131     MPUCFG = 92,
 132     ERACCESS = 95,
 133     IBREAKENABLE = 96,
 134     MEMCTL = 97,
 135     CACHEATTR = 98,
 136     CACHEADRDIS = 98,
 137     ATOMCTL = 99,
 138     DDR = 104,
 139     MEPC = 106,
 140     MEPS = 107,
 141     MESAVE = 108,
 142     MESR = 109,
 143     MECR = 110,
 144     MEVADDR = 111,
 145     IBREAKA = 128,
 146     DBREAKA = 144,
 147     DBREAKC = 160,
 148     CONFIGID0 = 176,
 149     EPC1 = 177,
 150     DEPC = 192,
 151     EPS2 = 194,
 152     CONFIGID1 = 208,
 153     EXCSAVE1 = 209,
 154     CPENABLE = 224,
 155     INTSET = 226,
 156     INTCLEAR = 227,
 157     INTENABLE = 228,
 158     PS = 230,
 159     VECBASE = 231,
 160     EXCCAUSE = 232,
 161     DEBUGCAUSE = 233,
 162     CCOUNT = 234,
 163     PRID = 235,
 164     ICOUNT = 236,
 165     ICOUNTLEVEL = 237,
 166     EXCVADDR = 238,
 167     CCOMPARE = 240,
 168     MISC = 244,
 169 };
 170
 171 #define PS_INTLEVEL 0xf
 172 #define PS_INTLEVEL_SHIFT 0
 173
 174 #define PS_EXCM 0x10
 175 #define PS_UM 0x20
 176
 177 #define PS_RING 0xc0
 178 #define PS_RING_SHIFT 6
 179
 180 #define PS_OWB 0xf00
 181 #define PS_OWB_SHIFT 8
 182 #define PS_OWB_LEN 4
 183
 184 #define PS_CALLINC 0x30000
 185 #define PS_CALLINC_SHIFT 16
 186 #define PS_CALLINC_LEN 2
 187
 188 #define PS_WOE 0x40000
 189
 190 #define DEBUGCAUSE_IC 0x1
 191 #define DEBUGCAUSE_IB 0x2
 192 #define DEBUGCAUSE_DB 0x4
 193 #define DEBUGCAUSE_BI 0x8
 194 #define DEBUGCAUSE_BN 0x10
 195 #define DEBUGCAUSE_DI 0x20
 196 #define DEBUGCAUSE_DBNUM 0xf00
 197 #define DEBUGCAUSE_DBNUM_SHIFT 8
 198
 199 #define DBREAKC_SB 0x80000000
 200 #define DBREAKC_LB 0x40000000
 201 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
 202 #define DBREAKC_MASK 0x3f
 203
 204 #define MEMCTL_INIT 0x00800000
 205 #define MEMCTL_IUSEWAYS_SHIFT 18
 206 #define MEMCTL_IUSEWAYS_LEN 5
 207 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
 208 #define MEMCTL_DALLOCWAYS_SHIFT 13
 209 #define MEMCTL_DALLOCWAYS_LEN 5
 210 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
 211 #define MEMCTL_DUSEWAYS_SHIFT 8
 212 #define MEMCTL_DUSEWAYS_LEN 5
 213 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
 214 #define MEMCTL_ISNP 0x4
 215 #define MEMCTL_DSNP 0x2
 216 #define MEMCTL_IL0EN 0x1
 217
 218 #define MAX_INSN_LENGTH 64
 219 #define MAX_INSN_SLOTS 32
 220 #define MAX_OPCODE_ARGS 16
 221 #define MAX_NAREG 64
 222 #define MAX_NINTERRUPT 32
 223 #define MAX_NLEVEL 6
 224 #define MAX_NNMI 1
 225 #define MAX_NCCOMPARE 3
 226 #define MAX_TLB_WAY_SIZE 8
 227 #define MAX_NDBREAK 2
 228 #define MAX_NMEMORY 4
 229 #define MAX_MPU_FOREGROUND_SEGMENTS 32
 230
 231 #define REGION_PAGE_MASK 0xe0000000
 232
 233 #define PAGE_CACHE_MASK    0x700
 234 #define PAGE_CACHE_SHIFT   8
 235 #define PAGE_CACHE_INVALID 0x000
 236 #define PAGE_CACHE_BYPASS  0x100
 237 #define PAGE_CACHE_WT      0x200
 238 #define PAGE_CACHE_WB      0x400
 239 #define PAGE_CACHE_ISOLATE 0x600
 240
 241 enum {
 242     /* Static vectors */
 243     EXC_RESET0,
 244     EXC_RESET1,
 245     EXC_MEMORY_ERROR,
 246
 247     /* Dynamic vectors */
 248     EXC_WINDOW_OVERFLOW4,
 249     EXC_WINDOW_UNDERFLOW4,
 250     EXC_WINDOW_OVERFLOW8,
 251     EXC_WINDOW_UNDERFLOW8,
 252     EXC_WINDOW_OVERFLOW12,
 253     EXC_WINDOW_UNDERFLOW12,
 254     EXC_IRQ,
 255     EXC_KERNEL,
 256     EXC_USER,
 257     EXC_DOUBLE,
 258     EXC_DEBUG,
 259     EXC_MAX
 260 };
 261
 262 enum {
 263     ILLEGAL_INSTRUCTION_CAUSE = 0,
 264     SYSCALL_CAUSE,
 265     INSTRUCTION_FETCH_ERROR_CAUSE,
 266     LOAD_STORE_ERROR_CAUSE,
 267     LEVEL1_INTERRUPT_CAUSE,
 268     ALLOCA_CAUSE,
 269     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 270     PC_VALUE_ERROR_CAUSE,
 271     PRIVILEGED_CAUSE,
 272     LOAD_STORE_ALIGNMENT_CAUSE,
 273     EXTERNAL_REG_PRIVILEGE_CAUSE,
 274     EXCLUSIVE_ERROR_CAUSE,
 275     INSTR_PIF_DATA_ERROR_CAUSE,
 276     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 277     INSTR_PIF_ADDR_ERROR_CAUSE,
 278     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 279     INST_TLB_MISS_CAUSE,
 280     INST_TLB_MULTI_HIT_CAUSE,
 281     INST_FETCH_PRIVILEGE_CAUSE,
 282     INST_FETCH_PROHIBITED_CAUSE = 20,
 283     LOAD_STORE_TLB_MISS_CAUSE = 24,
 284     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 285     LOAD_STORE_PRIVILEGE_CAUSE,
 286     LOAD_PROHIBITED_CAUSE = 28,
 287     STORE_PROHIBITED_CAUSE,
 288
 289     COPROCESSOR0_DISABLED = 32,
 290 };
 291
 292 typedef enum {
 293     INTTYPE_LEVEL,
 294     INTTYPE_EDGE,
 295     INTTYPE_NMI,
 296     INTTYPE_SOFTWARE,
 297     INTTYPE_TIMER,
 298     INTTYPE_DEBUG,
 299     INTTYPE_WRITE_ERR,
 300     INTTYPE_PROFILING,
 301     INTTYPE_IDMA_DONE,
 302     INTTYPE_IDMA_ERR,
 303     INTTYPE_GS_ERR,
 304     INTTYPE_MAX
 305 } interrupt_type;
 306
 307 struct CPUXtensaState;
 308
 309 typedef struct xtensa_tlb_entry {
 310     uint32_t vaddr;
 311     uint32_t paddr;
 312     uint8_t asid;
 313     uint8_t attr;
 314     bool variable;
 315 } xtensa_tlb_entry;
 316
 317 typedef struct xtensa_tlb {
 318     unsigned nways;
 319     const unsigned way_size[10];
 320     bool varway56;
 321     unsigned nrefillentries;
 322 } xtensa_tlb;
 323
 324 typedef struct xtensa_mpu_entry {
 325     uint32_t vaddr;
 326     uint32_t attr;
 327 } xtensa_mpu_entry;
 328
 329 typedef struct XtensaGdbReg {
 330     int targno;
 331     unsigned flags;
 332     int type;
 333     int group;
 334     unsigned size;
 335 } XtensaGdbReg;
 336
 337 typedef struct XtensaGdbRegmap {
 338     int num_regs;
 339     int num_core_regs;
 340     /* PC + a + ar + sr + ur */
 341     XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
 342 } XtensaGdbRegmap;
 343
 344 typedef struct XtensaCcompareTimer {
 345     struct CPUXtensaState *env;
 346     QEMUTimer *timer;
 347 } XtensaCcompareTimer;
 348
 349 typedef struct XtensaMemory {
 350     unsigned num;
 351     struct XtensaMemoryRegion {
 352         uint32_t addr;
 353         uint32_t size;
 354     } location[MAX_NMEMORY];
 355 } XtensaMemory;
 356
 357 typedef struct opcode_arg {
 358     uint32_t imm;
 359     uint32_t raw_imm;
 360     void *in;
 361     void *out;
 362 } OpcodeArg;
 363
 364 typedef struct DisasContext DisasContext;
 365 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[],
 366                                const uint32_t par[]);
 367 typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc,
 368                                      const OpcodeArg arg[],
 369                                      const uint32_t par[]);
 370 typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc,
 371                                          const OpcodeArg arg[],
 372                                          const uint32_t par[]);
 373
 374 enum {
 375     XTENSA_OP_ILL = 0x1,
 376     XTENSA_OP_PRIVILEGED = 0x2,
 377     XTENSA_OP_SYSCALL = 0x4,
 378     XTENSA_OP_DEBUG_BREAK = 0x8,
 379
 380     XTENSA_OP_OVERFLOW = 0x10,
 381     XTENSA_OP_UNDERFLOW = 0x20,
 382     XTENSA_OP_ALLOCA = 0x40,
 383     XTENSA_OP_COPROCESSOR = 0x80,
 384
 385     XTENSA_OP_DIVIDE_BY_ZERO = 0x100,
 386
 387     /* Postprocessing flags */
 388     XTENSA_OP_CHECK_INTERRUPTS = 0x200,
 389     XTENSA_OP_EXIT_TB_M1 = 0x400,
 390     XTENSA_OP_EXIT_TB_0 = 0x800,
 391     XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000,
 392
 393     XTENSA_OP_POSTPROCESS =
 394         XTENSA_OP_CHECK_INTERRUPTS |
 395         XTENSA_OP_EXIT_TB_M1 |
 396         XTENSA_OP_EXIT_TB_0 |
 397         XTENSA_OP_SYNC_REGISTER_WINDOW,
 398
 399     XTENSA_OP_NAME_ARRAY = 0x8000,
 400
 401     XTENSA_OP_CONTROL_FLOW = 0x10000,
 402     XTENSA_OP_STORE = 0x20000,
 403     XTENSA_OP_LOAD = 0x40000,
 404     XTENSA_OP_LOAD_STORE =
 405         XTENSA_OP_LOAD | XTENSA_OP_STORE,
 406 };
 407
 408 typedef struct XtensaOpcodeOps {
 409     const void *name;
 410     XtensaOpcodeOp translate;
 411     XtensaOpcodeBoolTest test_ill;
 412     XtensaOpcodeUintTest test_overflow;
 413     const uint32_t *par;
 414     uint32_t op_flags;
 415     uint32_t coprocessor;
 416 } XtensaOpcodeOps;
 417
 418 typedef struct XtensaOpcodeTranslators {
 419     unsigned num_opcodes;
 420     const XtensaOpcodeOps *opcode;
 421 } XtensaOpcodeTranslators;
 422
 423 extern const XtensaOpcodeTranslators xtensa_core_opcodes;
 424 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
 425
 426 struct XtensaConfig {
 427     const char *name;
 428     uint64_t options;
 429     XtensaGdbRegmap gdb_regmap;
 430     unsigned nareg;
 431     int excm_level;
 432     int ndepc;
 433     unsigned inst_fetch_width;
 434     unsigned max_insn_size;
 435     uint32_t vecbase;
 436     uint32_t exception_vector[EXC_MAX];
 437     unsigned ninterrupt;
 438     unsigned nlevel;
 439     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
 440     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
 441     uint32_t inttype_mask[INTTYPE_MAX];
 442     struct {
 443         uint32_t level;
 444         interrupt_type inttype;
 445     } interrupt[MAX_NINTERRUPT];
 446     unsigned nccompare;
 447     uint32_t timerint[MAX_NCCOMPARE];
 448     unsigned nextint;
 449     unsigned extint[MAX_NINTERRUPT];
 450
 451     unsigned debug_level;
 452     unsigned nibreak;
 453     unsigned ndbreak;
 454
 455     unsigned icache_ways;
 456     unsigned dcache_ways;
 457     unsigned dcache_line_bytes;
 458     uint32_t memctl_mask;
 459
 460     XtensaMemory instrom;
 461     XtensaMemory instram;
 462     XtensaMemory datarom;
 463     XtensaMemory dataram;
 464     XtensaMemory sysrom;
 465     XtensaMemory sysram;
 466
 467     uint32_t configid[2];
 468
 469     void *isa_internal;
 470     xtensa_isa isa;
 471     XtensaOpcodeOps **opcode_ops;
 472     const XtensaOpcodeTranslators **opcode_translators;
 473     xtensa_regfile a_regfile;
 474     void ***regfile;
 475
 476     uint32_t clock_freq_khz;
 477
 478     xtensa_tlb itlb;
 479     xtensa_tlb dtlb;
 480
 481     uint32_t mpu_align;
 482     unsigned n_mpu_fg_segments;
 483     unsigned n_mpu_bg_segments;
 484     const xtensa_mpu_entry *mpu_bg;
 485 };
 486
 487 typedef struct XtensaConfigList {
 488     const XtensaConfig *config;
 489     struct XtensaConfigList *next;
 490 } XtensaConfigList;
 491
 492 #ifdef HOST_WORDS_BIGENDIAN
 493 enum {
 494     FP_F32_HIGH,
 495     FP_F32_LOW,
 496 };
 497 #else
 498 enum {
 499     FP_F32_LOW,
 500     FP_F32_HIGH,
 501 };
 502 #endif
 503
 504 typedef struct CPUXtensaState {
 505     const XtensaConfig *config;
 506     uint32_t regs[16];
 507     uint32_t pc;
 508     uint32_t sregs[256];
 509     uint32_t uregs[256];
 510     uint32_t phys_regs[MAX_NAREG];
 511     union {
 512         float32 f32[2];
 513         float64 f64;
 514     } fregs[16];
 515     float_status fp_status;
 516     uint32_t windowbase_next;
 517     uint32_t exclusive_addr;
 518     uint32_t exclusive_val;
 519
 520 #ifndef CONFIG_USER_ONLY
 521     xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
 522     xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
 523     xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS];
 524     unsigned autorefill_idx;
 525     bool runstall;
 526     AddressSpace *address_space_er;
 527     MemoryRegion *system_er;
 528     int pending_irq_level; /* level of last raised IRQ */
 529     qemu_irq *irq_inputs;
 530     qemu_irq ext_irq_inputs[MAX_NINTERRUPT];
 531     qemu_irq runstall_irq;
 532     XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
 533     uint64_t time_base;
 534     uint64_t ccount_time;
 535     uint32_t ccount_base;
 536 #endif
 537
 538     int exception_taken;
 539     int yield_needed;
 540     unsigned static_vectors;
 541
 542     /* Watchpoints for DBREAK registers */
 543     struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
 544
 545     CPU_COMMON
 546 } CPUXtensaState;
 547
 548 /**
 549  * XtensaCPU:
 550  * @env: #CPUXtensaState
 551  *
 552  * An Xtensa CPU.
 553  */
 554 struct XtensaCPU {
 555     /*< private >*/
 556     CPUState parent_obj;
 557     /*< public >*/
 558
 559     CPUXtensaState env;
 560 };
 561
 562 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
 563 {
 564     return container_of(env, XtensaCPU, env);
 565 }
 566
 567 #define ENV_OFFSET offsetof(XtensaCPU, env)
 568
 569
 570 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 571                          MMUAccessType access_type, int mmu_idx,
 572                          bool probe, uintptr_t retaddr);
 573 void xtensa_cpu_do_interrupt(CPUState *cpu);
 574 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
 575 void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
 576                                       unsigned size, MMUAccessType access_type,
 577                                       int mmu_idx, MemTxAttrs attrs,
 578                                       MemTxResult response, uintptr_t retaddr);
 579 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 580 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 581 void xtensa_count_regs(const XtensaConfig *config,
 582                        unsigned *n_regs, unsigned *n_core_regs);
 583 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 584 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 585 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 586                                     MMUAccessType access_type,
 587                                     int mmu_idx, uintptr_t retaddr);
 588
 589 #define cpu_signal_handler cpu_xtensa_signal_handler
 590 #define cpu_list xtensa_cpu_list
 591
 592 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
 593 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
 594 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
 595
 596 #ifdef TARGET_WORDS_BIGENDIAN
 597 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
 598 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
 599 #else
 600 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
 601 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
 602 #endif
 603 #define XTENSA_DEFAULT_CPU_TYPE \
 604     XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
 605 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
 606     XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
 607
 608 void xtensa_collect_sr_names(const XtensaConfig *config);
 609 void xtensa_translate_init(void);
 610 void **xtensa_get_regfile_by_name(const char *name);
 611 void xtensa_breakpoint_handler(CPUState *cs);
 612 void xtensa_register_core(XtensaConfigList *node);
 613 void xtensa_sim_open_console(Chardev *chr);
 614 void check_interrupts(CPUXtensaState *s);
 615 void xtensa_irq_init(CPUXtensaState *env);
 616 qemu_irq *xtensa_get_extints(CPUXtensaState *env);
 617 qemu_irq xtensa_get_runstall(CPUXtensaState *env);
 618 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 619 void xtensa_cpu_list(void);
 620 void xtensa_sync_window_from_phys(CPUXtensaState *env);
 621 void xtensa_sync_phys_from_window(CPUXtensaState *env);
 622 void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta);
 623 void xtensa_restore_owb(CPUXtensaState *env);
 624 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
 625
 626 static inline void xtensa_select_static_vectors(CPUXtensaState *env,
 627                                                 unsigned n)
 628 {
 629     assert(n < 2);
 630     env->static_vectors = n;
 631 }
 632 void xtensa_runstall(CPUXtensaState *env, bool runstall);
 633
 634 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 635 #define XTENSA_OPTION_ALL (~(uint64_t)0)
 636
 637 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
 638         uint64_t opt)
 639 {
 640     return (config->options & opt) != 0;
 641 }
 642
 643 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 644 {
 645     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
 646 }
 647
 648 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
 649 {
 650     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 651     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 652         level = env->config->excm_level;
 653     }
 654     return level;
 655 }
 656
 657 static inline int xtensa_get_ring(const CPUXtensaState *env)
 658 {
 659     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 660         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 661     } else {
 662         return 0;
 663     }
 664 }
 665
 666 static inline int xtensa_get_cring(const CPUXtensaState *env)
 667 {
 668     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 669             (env->sregs[PS] & PS_EXCM) == 0) {
 670         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 671     } else {
 672         return 0;
 673     }
 674 }
 675
 676 #ifndef CONFIG_USER_ONLY
 677 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 678         uint32_t vaddr, int is_write, int mmu_idx,
 679         uint32_t *paddr, uint32_t *page_size, unsigned *access);
 680 void reset_mmu(CPUXtensaState *env);
 681 void dump_mmu(CPUXtensaState *env);
 682
 683 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
 684 {
 685     return env->system_er;
 686 }
 687 #endif
 688
 689 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
 690 {
 691     return env->sregs[WINDOW_START] |
 692         (env->sregs[WINDOW_START] << env->config->nareg / 4);
 693 }
 694
 695 /* MMU modes definitions */
 696 #define MMU_MODE0_SUFFIX _ring0
 697 #define MMU_MODE1_SUFFIX _ring1
 698 #define MMU_MODE2_SUFFIX _ring2
 699 #define MMU_MODE3_SUFFIX _ring3
 700 #define MMU_USER_IDX 3
 701
 702 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
 703 {
 704     return xtensa_get_cring(env);
 705 }
 706
 707 #define XTENSA_TBFLAG_RING_MASK 0x3
 708 #define XTENSA_TBFLAG_EXCM 0x4
 709 #define XTENSA_TBFLAG_LITBASE 0x8
 710 #define XTENSA_TBFLAG_DEBUG 0x10
 711 #define XTENSA_TBFLAG_ICOUNT 0x20
 712 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
 713 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
 714 #define XTENSA_TBFLAG_EXCEPTION 0x4000
 715 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
 716 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
 717 #define XTENSA_TBFLAG_YIELD 0x20000
 718 #define XTENSA_TBFLAG_CWOE 0x40000
 719 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000
 720 #define XTENSA_TBFLAG_CALLINC_SHIFT 19
 721
 722 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff
 723 #define XTENSA_CSBASE_LEND_SHIFT 0
 724 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
 725 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
 726
 727 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
 728         target_ulong *cs_base, uint32_t *flags)
 729 {
 730     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 731
 732     *pc = env->pc;
 733     *cs_base = 0;
 734     *flags = 0;
 735     *flags |= xtensa_get_ring(env);
 736     if (env->sregs[PS] & PS_EXCM) {
 737         *flags |= XTENSA_TBFLAG_EXCM;
 738     } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
 739         target_ulong lend_dist =
 740             env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
 741
 742         /*
 743          * 0 in the csbase_lend field means that there may not be a loopback
 744          * for any instruction that starts inside this page. Any other value
 745          * means that an instruction that ends at this offset from the page
 746          * start may loop back and will need loopback code to be generated.
 747          *
 748          * lend_dist is 0 when LEND points to the start of the page, but
 749          * no instruction that starts inside this page may end at offset 0,
 750          * so it's still correct.
 751          *
 752          * When an instruction ends at a page boundary it may only start in
 753          * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
 754          * for the TB that contains this instruction.
 755          */
 756         if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
 757             target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
 758
 759             *cs_base = lend_dist;
 760             if (lbeg_off < 256) {
 761                 *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
 762             }
 763         }
 764     }
 765     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
 766             (env->sregs[LITBASE] & 1)) {
 767         *flags |= XTENSA_TBFLAG_LITBASE;
 768     }
 769     if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
 770         if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 771             *flags |= XTENSA_TBFLAG_DEBUG;
 772         }
 773         if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
 774             *flags |= XTENSA_TBFLAG_ICOUNT;
 775         }
 776     }
 777     if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
 778         *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
 779     }
 780     if (cs->singlestep_enabled && env->exception_taken) {
 781         *flags |= XTENSA_TBFLAG_EXCEPTION;
 782     }
 783     if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
 784         (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
 785         uint32_t windowstart = xtensa_replicate_windowstart(env) >>
 786             (env->sregs[WINDOW_BASE] + 1);
 787         uint32_t w = ctz32(windowstart | 0x8);
 788
 789         *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
 790         *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
 791                             PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
 792     } else {
 793         *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
 794     }
 795     if (env->yield_needed) {
 796         *flags |= XTENSA_TBFLAG_YIELD;
 797     }
 798 }
 799
 800 typedef CPUXtensaState CPUArchState;
 801 typedef XtensaCPU ArchCPU;
 802
 803 #include "exec/cpu-all.h"
 804
 805 #endif