2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #define TARGET_LONG_BITS 32
34 /* Xtensa processors have a weak memory model */
35 #define TCG_GUEST_DEFAULT_MO (0)
37 #define CPUArchState struct CPUXtensaState
39 #include "qemu-common.h"
41 #include "exec/cpu-defs.h"
42 #include "xtensa-isa.h"
44 #define NB_MMU_MODES 4
46 #define TARGET_PHYS_ADDR_SPACE_BITS 32
47 #ifdef CONFIG_USER_ONLY
48 #define TARGET_VIRT_ADDR_SPACE_BITS 30
50 #define TARGET_VIRT_ADDR_SPACE_BITS 32
52 #define TARGET_PAGE_BITS 12
55 /* Additional instructions */
56 XTENSA_OPTION_CODE_DENSITY
,
58 XTENSA_OPTION_EXTENDED_L32R
,
59 XTENSA_OPTION_16_BIT_IMUL
,
60 XTENSA_OPTION_32_BIT_IMUL
,
61 XTENSA_OPTION_32_BIT_IMUL_HIGH
,
62 XTENSA_OPTION_32_BIT_IDIV
,
64 XTENSA_OPTION_MISC_OP_NSA
,
65 XTENSA_OPTION_MISC_OP_MINMAX
,
66 XTENSA_OPTION_MISC_OP_SEXT
,
67 XTENSA_OPTION_MISC_OP_CLAMPS
,
68 XTENSA_OPTION_COPROCESSOR
,
69 XTENSA_OPTION_BOOLEAN
,
70 XTENSA_OPTION_FP_COPROCESSOR
,
71 XTENSA_OPTION_MP_SYNCHRO
,
72 XTENSA_OPTION_CONDITIONAL_STORE
,
73 XTENSA_OPTION_ATOMCTL
,
74 XTENSA_OPTION_DEPBITS
,
76 /* Interrupts and exceptions */
77 XTENSA_OPTION_EXCEPTION
,
78 XTENSA_OPTION_RELOCATABLE_VECTOR
,
79 XTENSA_OPTION_UNALIGNED_EXCEPTION
,
80 XTENSA_OPTION_INTERRUPT
,
81 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
82 XTENSA_OPTION_TIMER_INTERRUPT
,
86 XTENSA_OPTION_ICACHE_TEST
,
87 XTENSA_OPTION_ICACHE_INDEX_LOCK
,
89 XTENSA_OPTION_DCACHE_TEST
,
90 XTENSA_OPTION_DCACHE_INDEX_LOCK
,
96 XTENSA_OPTION_HW_ALIGNMENT
,
97 XTENSA_OPTION_MEMORY_ECC_PARITY
,
99 /* Memory protection and translation */
100 XTENSA_OPTION_REGION_PROTECTION
,
101 XTENSA_OPTION_REGION_TRANSLATION
,
103 XTENSA_OPTION_CACHEATTR
,
106 XTENSA_OPTION_WINDOWED_REGISTER
,
107 XTENSA_OPTION_PROCESSOR_INTERFACE
,
108 XTENSA_OPTION_MISC_SR
,
109 XTENSA_OPTION_THREAD_POINTER
,
110 XTENSA_OPTION_PROCESSOR_ID
,
112 XTENSA_OPTION_TRACE_PORT
,
113 XTENSA_OPTION_EXTERN_REGS
,
172 #define PS_INTLEVEL 0xf
173 #define PS_INTLEVEL_SHIFT 0
179 #define PS_RING_SHIFT 6
182 #define PS_OWB_SHIFT 8
185 #define PS_CALLINC 0x30000
186 #define PS_CALLINC_SHIFT 16
187 #define PS_CALLINC_LEN 2
189 #define PS_WOE 0x40000
191 #define DEBUGCAUSE_IC 0x1
192 #define DEBUGCAUSE_IB 0x2
193 #define DEBUGCAUSE_DB 0x4
194 #define DEBUGCAUSE_BI 0x8
195 #define DEBUGCAUSE_BN 0x10
196 #define DEBUGCAUSE_DI 0x20
197 #define DEBUGCAUSE_DBNUM 0xf00
198 #define DEBUGCAUSE_DBNUM_SHIFT 8
200 #define DBREAKC_SB 0x80000000
201 #define DBREAKC_LB 0x40000000
202 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
203 #define DBREAKC_MASK 0x3f
205 #define MEMCTL_INIT 0x00800000
206 #define MEMCTL_IUSEWAYS_SHIFT 18
207 #define MEMCTL_IUSEWAYS_LEN 5
208 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
209 #define MEMCTL_DALLOCWAYS_SHIFT 13
210 #define MEMCTL_DALLOCWAYS_LEN 5
211 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
212 #define MEMCTL_DUSEWAYS_SHIFT 8
213 #define MEMCTL_DUSEWAYS_LEN 5
214 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
215 #define MEMCTL_ISNP 0x4
216 #define MEMCTL_DSNP 0x2
217 #define MEMCTL_IL0EN 0x1
219 #define MAX_INSN_LENGTH 64
220 #define MAX_INSN_SLOTS 32
221 #define MAX_OPCODE_ARGS 16
223 #define MAX_NINTERRUPT 32
226 #define MAX_NCCOMPARE 3
227 #define MAX_TLB_WAY_SIZE 8
228 #define MAX_NDBREAK 2
229 #define MAX_NMEMORY 4
231 #define REGION_PAGE_MASK 0xe0000000
233 #define PAGE_CACHE_MASK 0x700
234 #define PAGE_CACHE_SHIFT 8
235 #define PAGE_CACHE_INVALID 0x000
236 #define PAGE_CACHE_BYPASS 0x100
237 #define PAGE_CACHE_WT 0x200
238 #define PAGE_CACHE_WB 0x400
239 #define PAGE_CACHE_ISOLATE 0x600
247 /* Dynamic vectors */
248 EXC_WINDOW_OVERFLOW4
,
249 EXC_WINDOW_UNDERFLOW4
,
250 EXC_WINDOW_OVERFLOW8
,
251 EXC_WINDOW_UNDERFLOW8
,
252 EXC_WINDOW_OVERFLOW12
,
253 EXC_WINDOW_UNDERFLOW12
,
263 ILLEGAL_INSTRUCTION_CAUSE
= 0,
265 INSTRUCTION_FETCH_ERROR_CAUSE
,
266 LOAD_STORE_ERROR_CAUSE
,
267 LEVEL1_INTERRUPT_CAUSE
,
269 INTEGER_DIVIDE_BY_ZERO_CAUSE
,
270 PRIVILEGED_CAUSE
= 8,
271 LOAD_STORE_ALIGNMENT_CAUSE
,
273 INSTR_PIF_DATA_ERROR_CAUSE
= 12,
274 LOAD_STORE_PIF_DATA_ERROR_CAUSE
,
275 INSTR_PIF_ADDR_ERROR_CAUSE
,
276 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
279 INST_TLB_MULTI_HIT_CAUSE
,
280 INST_FETCH_PRIVILEGE_CAUSE
,
281 INST_FETCH_PROHIBITED_CAUSE
= 20,
282 LOAD_STORE_TLB_MISS_CAUSE
= 24,
283 LOAD_STORE_TLB_MULTI_HIT_CAUSE
,
284 LOAD_STORE_PRIVILEGE_CAUSE
,
285 LOAD_PROHIBITED_CAUSE
= 28,
286 STORE_PROHIBITED_CAUSE
,
288 COPROCESSOR0_DISABLED
= 32,
303 struct CPUXtensaState
;
305 typedef struct xtensa_tlb_entry
{
313 typedef struct xtensa_tlb
{
315 const unsigned way_size
[10];
317 unsigned nrefillentries
;
320 typedef struct XtensaGdbReg
{
328 typedef struct XtensaGdbRegmap
{
331 /* PC + a + ar + sr + ur */
332 XtensaGdbReg reg
[1 + 16 + 64 + 256 + 256];
335 typedef struct XtensaCcompareTimer
{
336 struct CPUXtensaState
*env
;
338 } XtensaCcompareTimer
;
340 typedef struct XtensaMemory
{
342 struct XtensaMemoryRegion
{
345 } location
[MAX_NMEMORY
];
348 typedef struct DisasContext DisasContext
;
349 typedef void (*XtensaOpcodeOp
)(DisasContext
*dc
, const uint32_t arg
[],
350 const uint32_t par
[]);
351 typedef bool (*XtensaOpcodeBoolTest
)(DisasContext
*dc
,
352 const uint32_t arg
[],
353 const uint32_t par
[]);
354 typedef uint32_t (*XtensaOpcodeUintTest
)(DisasContext
*dc
,
355 const uint32_t arg
[],
356 const uint32_t par
[]);
360 XTENSA_OP_PRIVILEGED
= 0x2,
361 XTENSA_OP_SYSCALL
= 0x4,
362 XTENSA_OP_DEBUG_BREAK
= 0x8,
364 XTENSA_OP_OVERFLOW
= 0x10,
365 XTENSA_OP_UNDERFLOW
= 0x20,
366 XTENSA_OP_ALLOCA
= 0x40,
367 XTENSA_OP_COPROCESSOR
= 0x80,
369 XTENSA_OP_DIVIDE_BY_ZERO
= 0x100,
371 XTENSA_OP_CHECK_INTERRUPTS
= 0x200,
372 XTENSA_OP_EXIT_TB_M1
= 0x400,
373 XTENSA_OP_EXIT_TB_0
= 0x800,
375 XTENSA_OP_NAME_ARRAY
= 0x8000,
378 typedef struct XtensaOpcodeOps
{
380 XtensaOpcodeOp translate
;
381 XtensaOpcodeBoolTest test_ill
;
382 XtensaOpcodeUintTest test_overflow
;
385 uint32_t coprocessor
;
388 typedef struct XtensaOpcodeTranslators
{
389 unsigned num_opcodes
;
390 const XtensaOpcodeOps
*opcode
;
391 } XtensaOpcodeTranslators
;
393 extern const XtensaOpcodeTranslators xtensa_core_opcodes
;
394 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
;
396 struct XtensaConfig
{
399 XtensaGdbRegmap gdb_regmap
;
403 unsigned inst_fetch_width
;
404 unsigned max_insn_size
;
406 uint32_t exception_vector
[EXC_MAX
];
409 uint32_t interrupt_vector
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
410 uint32_t level_mask
[MAX_NLEVEL
+ MAX_NNMI
+ 1];
411 uint32_t inttype_mask
[INTTYPE_MAX
];
414 interrupt_type inttype
;
415 } interrupt
[MAX_NINTERRUPT
];
417 uint32_t timerint
[MAX_NCCOMPARE
];
419 unsigned extint
[MAX_NINTERRUPT
];
421 unsigned debug_level
;
425 unsigned icache_ways
;
426 unsigned dcache_ways
;
427 uint32_t memctl_mask
;
429 XtensaMemory instrom
;
430 XtensaMemory instram
;
431 XtensaMemory datarom
;
432 XtensaMemory dataram
;
436 uint32_t configid
[2];
440 XtensaOpcodeOps
**opcode_ops
;
441 const XtensaOpcodeTranslators
**opcode_translators
;
442 xtensa_regfile a_regfile
;
444 uint32_t clock_freq_khz
;
450 typedef struct XtensaConfigList
{
451 const XtensaConfig
*config
;
452 struct XtensaConfigList
*next
;
455 #ifdef HOST_WORDS_BIGENDIAN
467 typedef struct CPUXtensaState
{
468 const XtensaConfig
*config
;
473 uint32_t phys_regs
[MAX_NAREG
];
478 float_status fp_status
;
480 #ifndef CONFIG_USER_ONLY
481 xtensa_tlb_entry itlb
[7][MAX_TLB_WAY_SIZE
];
482 xtensa_tlb_entry dtlb
[10][MAX_TLB_WAY_SIZE
];
483 unsigned autorefill_idx
;
485 AddressSpace
*address_space_er
;
486 MemoryRegion
*system_er
;
487 int pending_irq_level
; /* level of last raised IRQ */
488 qemu_irq
*irq_inputs
;
489 qemu_irq ext_irq_inputs
[MAX_NINTERRUPT
];
490 qemu_irq runstall_irq
;
491 XtensaCcompareTimer ccompare
[MAX_NCCOMPARE
];
493 uint64_t ccount_time
;
494 uint32_t ccount_base
;
499 unsigned static_vectors
;
501 /* Watchpoints for DBREAK registers */
502 struct CPUWatchpoint
*cpu_watchpoint
[MAX_NDBREAK
];
509 * @env: #CPUXtensaState
521 static inline XtensaCPU
*xtensa_env_get_cpu(const CPUXtensaState
*env
)
523 return container_of(env
, XtensaCPU
, env
);
526 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
528 #define ENV_OFFSET offsetof(XtensaCPU, env)
531 int xtensa_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
, int size
,
533 void xtensa_cpu_do_interrupt(CPUState
*cpu
);
534 bool xtensa_cpu_exec_interrupt(CPUState
*cpu
, int interrupt_request
);
535 void xtensa_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
, vaddr addr
,
536 unsigned size
, MMUAccessType access_type
,
537 int mmu_idx
, MemTxAttrs attrs
,
538 MemTxResult response
, uintptr_t retaddr
);
539 void xtensa_cpu_dump_state(CPUState
*cpu
, FILE *f
,
540 fprintf_function cpu_fprintf
, int flags
);
541 hwaddr
xtensa_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
542 void xtensa_count_regs(const XtensaConfig
*config
,
543 unsigned *n_regs
, unsigned *n_core_regs
);
544 int xtensa_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
545 int xtensa_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
546 void xtensa_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
547 MMUAccessType access_type
,
548 int mmu_idx
, uintptr_t retaddr
);
550 #define cpu_signal_handler cpu_xtensa_signal_handler
551 #define cpu_list xtensa_cpu_list
553 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
554 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
555 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
557 #ifdef TARGET_WORDS_BIGENDIAN
558 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
559 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
561 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
562 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
564 #define XTENSA_DEFAULT_CPU_TYPE \
565 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
566 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
567 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
569 void xtensa_translate_init(void);
570 void xtensa_breakpoint_handler(CPUState
*cs
);
571 void xtensa_register_core(XtensaConfigList
*node
);
572 void xtensa_sim_open_console(Chardev
*chr
);
573 void check_interrupts(CPUXtensaState
*s
);
574 void xtensa_irq_init(CPUXtensaState
*env
);
575 qemu_irq
*xtensa_get_extints(CPUXtensaState
*env
);
576 qemu_irq
xtensa_get_runstall(CPUXtensaState
*env
);
577 int cpu_xtensa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
578 void xtensa_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
579 void xtensa_sync_window_from_phys(CPUXtensaState
*env
);
580 void xtensa_sync_phys_from_window(CPUXtensaState
*env
);
581 void xtensa_rotate_window(CPUXtensaState
*env
, uint32_t delta
);
582 void xtensa_restore_owb(CPUXtensaState
*env
);
583 void debug_exception_env(CPUXtensaState
*new_env
, uint32_t cause
);
585 static inline void xtensa_select_static_vectors(CPUXtensaState
*env
,
589 env
->static_vectors
= n
;
591 void xtensa_runstall(CPUXtensaState
*env
, bool runstall
);
593 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
594 #define XTENSA_OPTION_ALL (~(uint64_t)0)
596 static inline bool xtensa_option_bits_enabled(const XtensaConfig
*config
,
599 return (config
->options
& opt
) != 0;
602 static inline bool xtensa_option_enabled(const XtensaConfig
*config
, int opt
)
604 return xtensa_option_bits_enabled(config
, XTENSA_OPTION_BIT(opt
));
607 static inline int xtensa_get_cintlevel(const CPUXtensaState
*env
)
609 int level
= (env
->sregs
[PS
] & PS_INTLEVEL
) >> PS_INTLEVEL_SHIFT
;
610 if ((env
->sregs
[PS
] & PS_EXCM
) && env
->config
->excm_level
> level
) {
611 level
= env
->config
->excm_level
;
616 static inline int xtensa_get_ring(const CPUXtensaState
*env
)
618 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
619 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
625 static inline int xtensa_get_cring(const CPUXtensaState
*env
)
627 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
) &&
628 (env
->sregs
[PS
] & PS_EXCM
) == 0) {
629 return (env
->sregs
[PS
] & PS_RING
) >> PS_RING_SHIFT
;
635 #ifndef CONFIG_USER_ONLY
636 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState
*env
,
637 bool dtlb
, uint32_t way
);
638 void split_tlb_entry_spec_way(const CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
639 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
);
640 int xtensa_tlb_lookup(const CPUXtensaState
*env
, uint32_t addr
, bool dtlb
,
641 uint32_t *pwi
, uint32_t *pei
, uint8_t *pring
);
642 void xtensa_tlb_set_entry_mmu(const CPUXtensaState
*env
,
643 xtensa_tlb_entry
*entry
, bool dtlb
,
644 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
645 void xtensa_tlb_set_entry(CPUXtensaState
*env
, bool dtlb
,
646 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
);
647 int xtensa_get_physical_addr(CPUXtensaState
*env
, bool update_tlb
,
648 uint32_t vaddr
, int is_write
, int mmu_idx
,
649 uint32_t *paddr
, uint32_t *page_size
, unsigned *access
);
650 void reset_mmu(CPUXtensaState
*env
);
651 void dump_mmu(FILE *f
, fprintf_function cpu_fprintf
, CPUXtensaState
*env
);
653 static inline MemoryRegion
*xtensa_get_er_region(CPUXtensaState
*env
)
655 return env
->system_er
;
658 static inline xtensa_tlb_entry
*xtensa_tlb_get_entry(CPUXtensaState
*env
,
659 bool dtlb
, unsigned wi
, unsigned ei
)
667 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState
*env
)
669 return env
->sregs
[WINDOW_START
] |
670 (env
->sregs
[WINDOW_START
] << env
->config
->nareg
/ 4);
673 /* MMU modes definitions */
674 #define MMU_MODE0_SUFFIX _ring0
675 #define MMU_MODE1_SUFFIX _ring1
676 #define MMU_MODE2_SUFFIX _ring2
677 #define MMU_MODE3_SUFFIX _ring3
678 #define MMU_USER_IDX 3
680 static inline int cpu_mmu_index(CPUXtensaState
*env
, bool ifetch
)
682 return xtensa_get_cring(env
);
685 #define XTENSA_TBFLAG_RING_MASK 0x3
686 #define XTENSA_TBFLAG_EXCM 0x4
687 #define XTENSA_TBFLAG_LITBASE 0x8
688 #define XTENSA_TBFLAG_DEBUG 0x10
689 #define XTENSA_TBFLAG_ICOUNT 0x20
690 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
691 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
692 #define XTENSA_TBFLAG_EXCEPTION 0x4000
693 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
694 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
695 #define XTENSA_TBFLAG_YIELD 0x20000
696 #define XTENSA_TBFLAG_CWOE 0x40000
697 #define XTENSA_TBFLAG_CALLINC_MASK 0x180000
698 #define XTENSA_TBFLAG_CALLINC_SHIFT 19
700 #define XTENSA_CSBASE_LEND_MASK 0x0000ffff
701 #define XTENSA_CSBASE_LEND_SHIFT 0
702 #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
703 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
705 static inline void cpu_get_tb_cpu_state(CPUXtensaState
*env
, target_ulong
*pc
,
706 target_ulong
*cs_base
, uint32_t *flags
)
708 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
713 *flags
|= xtensa_get_ring(env
);
714 if (env
->sregs
[PS
] & PS_EXCM
) {
715 *flags
|= XTENSA_TBFLAG_EXCM
;
716 } else if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_LOOP
)) {
717 target_ulong lend_dist
=
718 env
->sregs
[LEND
] - (env
->pc
& -(1u << TARGET_PAGE_BITS
));
721 * 0 in the csbase_lend field means that there may not be a loopback
722 * for any instruction that starts inside this page. Any other value
723 * means that an instruction that ends at this offset from the page
724 * start may loop back and will need loopback code to be generated.
726 * lend_dist is 0 when LEND points to the start of the page, but
727 * no instruction that starts inside this page may end at offset 0,
728 * so it's still correct.
730 * When an instruction ends at a page boundary it may only start in
731 * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
732 * for the TB that contains this instruction.
734 if (lend_dist
< (1u << TARGET_PAGE_BITS
) + env
->config
->max_insn_size
) {
735 target_ulong lbeg_off
= env
->sregs
[LEND
] - env
->sregs
[LBEG
];
737 *cs_base
= lend_dist
;
738 if (lbeg_off
< 256) {
739 *cs_base
|= lbeg_off
<< XTENSA_CSBASE_LBEG_OFF_SHIFT
;
743 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_EXTENDED_L32R
) &&
744 (env
->sregs
[LITBASE
] & 1)) {
745 *flags
|= XTENSA_TBFLAG_LITBASE
;
747 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_DEBUG
)) {
748 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
749 *flags
|= XTENSA_TBFLAG_DEBUG
;
751 if (xtensa_get_cintlevel(env
) < env
->sregs
[ICOUNTLEVEL
]) {
752 *flags
|= XTENSA_TBFLAG_ICOUNT
;
755 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_COPROCESSOR
)) {
756 *flags
|= env
->sregs
[CPENABLE
] << XTENSA_TBFLAG_CPENABLE_SHIFT
;
758 if (cs
->singlestep_enabled
&& env
->exception_taken
) {
759 *flags
|= XTENSA_TBFLAG_EXCEPTION
;
761 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_WINDOWED_REGISTER
) &&
762 (env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) == PS_WOE
) {
763 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
764 (env
->sregs
[WINDOW_BASE
] + 1);
765 uint32_t w
= ctz32(windowstart
| 0x8);
767 *flags
|= (w
<< XTENSA_TBFLAG_WINDOW_SHIFT
) | XTENSA_TBFLAG_CWOE
;
768 *flags
|= extract32(env
->sregs
[PS
], PS_CALLINC_SHIFT
,
769 PS_CALLINC_LEN
) << XTENSA_TBFLAG_CALLINC_SHIFT
;
771 *flags
|= 3 << XTENSA_TBFLAG_WINDOW_SHIFT
;
773 if (env
->yield_needed
) {
774 *flags
|= XTENSA_TBFLAG_YIELD
;
778 #include "exec/cpu-all.h"