target/xtensa/overlay_tool.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
  29         a1, a2, a3, a4, a5, a6) \
  30     { .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
  31 #define XTREG_END { .targno = -1 },
  32
  33 #ifndef XCHAL_HAVE_DEPBITS
  34 #define XCHAL_HAVE_DEPBITS 0
  35 #endif
  36
  37 #ifndef XCHAL_HAVE_DIV32
  38 #define XCHAL_HAVE_DIV32 0
  39 #endif
  40
  41 #ifndef XCHAL_UNALIGNED_LOAD_HW
  42 #define XCHAL_UNALIGNED_LOAD_HW 0
  43 #endif
  44
  45 #ifndef XCHAL_HAVE_VECBASE
  46 #define XCHAL_HAVE_VECBASE 0
  47 #define XCHAL_VECBASE_RESET_VADDR 0
  48 #endif
  49
  50 #ifndef XCHAL_RESET_VECTOR0_VADDR
  51 #define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
  52 #endif
  53
  54 #ifndef XCHAL_RESET_VECTOR1_VADDR
  55 #define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
  56 #endif
  57
  58 #ifndef XCHAL_HW_MIN_VERSION
  59 #define XCHAL_HW_MIN_VERSION 0
  60 #endif
  61
  62 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
  63
  64 #define XTENSA_OPTIONS ( \
  65     XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
  66     XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
  67     XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
  68     XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
  69     XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
  70     XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
  71     XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
  72     XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
  73     XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
  74     XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
  75     XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
  76     XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
  77     XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
  78     XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
  79     XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
  80     XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
  81     XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
  82     XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
  83         XTENSA_OPTION_ATOMCTL) | \
  84     XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
  85     /* Interrupts and exceptions */ \
  86     XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
  87     XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
  88     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
  89         XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
  90     XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
  91     XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
  92         XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
  93     XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
  94     /* Local memory, TODO */ \
  95     XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \
  96     XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
  97             XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
  98     XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \
  99     XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
 100             XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
 101     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
 102     /* Memory protection and translation */ \
 103     XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
 104             XTENSA_OPTION_REGION_PROTECTION) | \
 105     XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
 106             XTENSA_OPTION_REGION_TRANSLATION) | \
 107     XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
 108     XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
 109     /* Other, TODO */ \
 110     XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
 111     XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
 112     XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
 113     XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
 114     XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID))
 115
 116 #ifndef XCHAL_WINDOW_OF4_VECOFS
 117 #define XCHAL_WINDOW_OF4_VECOFS         0x00000000
 118 #define XCHAL_WINDOW_UF4_VECOFS         0x00000040
 119 #define XCHAL_WINDOW_OF8_VECOFS         0x00000080
 120 #define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
 121 #define XCHAL_WINDOW_OF12_VECOFS        0x00000100
 122 #define XCHAL_WINDOW_UF12_VECOFS        0x00000140
 123 #endif
 124
 125 #if XCHAL_HAVE_WINDOWED
 126 #define WINDOW_VECTORS \
 127    [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
 128        XCHAL_WINDOW_VECTORS_VADDR, \
 129    [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
 130        XCHAL_WINDOW_VECTORS_VADDR, \
 131    [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
 132        XCHAL_WINDOW_VECTORS_VADDR, \
 133    [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
 134        XCHAL_WINDOW_VECTORS_VADDR, \
 135    [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
 136        XCHAL_WINDOW_VECTORS_VADDR, \
 137    [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
 138        XCHAL_WINDOW_VECTORS_VADDR,
 139 #else
 140 #define WINDOW_VECTORS
 141 #endif
 142
 143 #define EXCEPTION_VECTORS { \
 144         [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
 145         [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
 146         WINDOW_VECTORS \
 147         [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
 148         [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
 149         [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
 150         [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
 151     }
 152
 153 #define INTERRUPT_VECTORS { \
 154         0, \
 155         0, \
 156         XCHAL_INTLEVEL2_VECTOR_VADDR, \
 157         XCHAL_INTLEVEL3_VECTOR_VADDR, \
 158         XCHAL_INTLEVEL4_VECTOR_VADDR, \
 159         XCHAL_INTLEVEL5_VECTOR_VADDR, \
 160         XCHAL_INTLEVEL6_VECTOR_VADDR, \
 161         XCHAL_INTLEVEL7_VECTOR_VADDR, \
 162     }
 163
 164 #define LEVEL_MASKS { \
 165         [1] = XCHAL_INTLEVEL1_MASK, \
 166         [2] = XCHAL_INTLEVEL2_MASK, \
 167         [3] = XCHAL_INTLEVEL3_MASK, \
 168         [4] = XCHAL_INTLEVEL4_MASK, \
 169         [5] = XCHAL_INTLEVEL5_MASK, \
 170         [6] = XCHAL_INTLEVEL6_MASK, \
 171         [7] = XCHAL_INTLEVEL7_MASK, \
 172     }
 173
 174 #define INTTYPE_MASKS { \
 175         [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
 176         [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
 177         [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
 178     }
 179
 180 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
 181 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
 182 #define XTHAL_INTTYPE_NMI INTTYPE_NMI
 183 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
 184 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
 185 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
 186 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
 187 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
 188 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
 189
 190
 191 #define INTERRUPT(i) { \
 192         .level = XCHAL_INT ## i ## _LEVEL, \
 193         .inttype = XCHAL_INT ## i ## _TYPE, \
 194     }
 195
 196 #define INTERRUPTS { \
 197         [0] = INTERRUPT(0), \
 198         [1] = INTERRUPT(1), \
 199         [2] = INTERRUPT(2), \
 200         [3] = INTERRUPT(3), \
 201         [4] = INTERRUPT(4), \
 202         [5] = INTERRUPT(5), \
 203         [6] = INTERRUPT(6), \
 204         [7] = INTERRUPT(7), \
 205         [8] = INTERRUPT(8), \
 206         [9] = INTERRUPT(9), \
 207         [10] = INTERRUPT(10), \
 208         [11] = INTERRUPT(11), \
 209         [12] = INTERRUPT(12), \
 210         [13] = INTERRUPT(13), \
 211         [14] = INTERRUPT(14), \
 212         [15] = INTERRUPT(15), \
 213         [16] = INTERRUPT(16), \
 214         [17] = INTERRUPT(17), \
 215         [18] = INTERRUPT(18), \
 216         [19] = INTERRUPT(19), \
 217         [20] = INTERRUPT(20), \
 218         [21] = INTERRUPT(21), \
 219         [22] = INTERRUPT(22), \
 220         [23] = INTERRUPT(23), \
 221         [24] = INTERRUPT(24), \
 222         [25] = INTERRUPT(25), \
 223         [26] = INTERRUPT(26), \
 224         [27] = INTERRUPT(27), \
 225         [28] = INTERRUPT(28), \
 226         [29] = INTERRUPT(29), \
 227         [30] = INTERRUPT(30), \
 228         [31] = INTERRUPT(31), \
 229     }
 230
 231 #define TIMERINTS { \
 232         [0] = XCHAL_TIMER0_INTERRUPT, \
 233         [1] = XCHAL_TIMER1_INTERRUPT, \
 234         [2] = XCHAL_TIMER2_INTERRUPT, \
 235     }
 236
 237 #define EXTINTS { \
 238         [0] = XCHAL_EXTINT0_NUM, \
 239         [1] = XCHAL_EXTINT1_NUM, \
 240         [2] = XCHAL_EXTINT2_NUM, \
 241         [3] = XCHAL_EXTINT3_NUM, \
 242         [4] = XCHAL_EXTINT4_NUM, \
 243         [5] = XCHAL_EXTINT5_NUM, \
 244         [6] = XCHAL_EXTINT6_NUM, \
 245         [7] = XCHAL_EXTINT7_NUM, \
 246         [8] = XCHAL_EXTINT8_NUM, \
 247         [9] = XCHAL_EXTINT9_NUM, \
 248         [10] = XCHAL_EXTINT10_NUM, \
 249         [11] = XCHAL_EXTINT11_NUM, \
 250         [12] = XCHAL_EXTINT12_NUM, \
 251         [13] = XCHAL_EXTINT13_NUM, \
 252         [14] = XCHAL_EXTINT14_NUM, \
 253         [15] = XCHAL_EXTINT15_NUM, \
 254         [16] = XCHAL_EXTINT16_NUM, \
 255         [17] = XCHAL_EXTINT17_NUM, \
 256         [18] = XCHAL_EXTINT18_NUM, \
 257         [19] = XCHAL_EXTINT19_NUM, \
 258         [20] = XCHAL_EXTINT20_NUM, \
 259         [21] = XCHAL_EXTINT21_NUM, \
 260         [22] = XCHAL_EXTINT22_NUM, \
 261         [23] = XCHAL_EXTINT23_NUM, \
 262         [24] = XCHAL_EXTINT24_NUM, \
 263         [25] = XCHAL_EXTINT25_NUM, \
 264         [26] = XCHAL_EXTINT26_NUM, \
 265         [27] = XCHAL_EXTINT27_NUM, \
 266         [28] = XCHAL_EXTINT28_NUM, \
 267         [29] = XCHAL_EXTINT29_NUM, \
 268         [30] = XCHAL_EXTINT30_NUM, \
 269         [31] = XCHAL_EXTINT31_NUM, \
 270     }
 271
 272 #define EXCEPTIONS_SECTION \
 273     .excm_level = XCHAL_EXCM_LEVEL, \
 274     .vecbase = XCHAL_VECBASE_RESET_VADDR, \
 275     .exception_vector = EXCEPTION_VECTORS
 276
 277 #define INTERRUPTS_SECTION \
 278     .ninterrupt = XCHAL_NUM_INTERRUPTS, \
 279     .nlevel = XCHAL_NUM_INTLEVELS, \
 280     .interrupt_vector = INTERRUPT_VECTORS, \
 281     .level_mask = LEVEL_MASKS, \
 282     .inttype_mask = INTTYPE_MASKS, \
 283     .interrupt = INTERRUPTS, \
 284     .nccompare = XCHAL_NUM_TIMERS, \
 285     .timerint = TIMERINTS, \
 286     .nextint = XCHAL_NUM_EXTINTERRUPTS, \
 287     .extint = EXTINTS
 288
 289 #if XCHAL_HAVE_PTP_MMU
 290
 291 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \
 292         .nways = ways, \
 293         .way_size = { \
 294             (refill_way_size), (refill_way_size), \
 295             (refill_way_size), (refill_way_size), \
 296             4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
 297         }, \
 298         .varway56 = (way56), \
 299         .nrefillentries = (refill_way_size) * 4, \
 300     }
 301
 302 #define ITLB(varway56) \
 303     TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
 304
 305 #define DTLB(varway56) \
 306     TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
 307
 308 #define TLB_SECTION \
 309     .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
 310     .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
 311
 312 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
 313
 314 #define TLB_TEMPLATE { \
 315         .nways = 1, \
 316         .way_size = { \
 317             8, \
 318         } \
 319     }
 320
 321 #define TLB_SECTION \
 322     .itlb = TLB_TEMPLATE, \
 323     .dtlb = TLB_TEMPLATE
 324
 325 #endif
 326
 327 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
 328 #define REGISTER_CORE(core) \
 329     static void __attribute__((constructor)) register_core(void) \
 330     { \
 331         static XtensaConfigList node = { \
 332             .config = &core, \
 333         }; \
 334         xtensa_finalize_config(&core); \
 335         xtensa_register_core(&node); \
 336     }
 337 #else
 338 #define REGISTER_CORE(core)
 339 #endif
 340
 341 #define DEBUG_SECTION \
 342     .debug_level = XCHAL_DEBUGLEVEL, \
 343     .nibreak = XCHAL_NUM_IBREAK, \
 344     .ndbreak = XCHAL_NUM_DBREAK
 345
 346 #define CONFIG_SECTION \
 347     .configid = { \
 348         XCHAL_HW_CONFIGID0, \
 349         XCHAL_HW_CONFIGID1, \
 350     }
 351
 352 #define DEFAULT_SECTIONS \
 353     .options = XTENSA_OPTIONS, \
 354     .nareg = XCHAL_NUM_AREGS, \
 355     .ndepc = (XCHAL_XEA_VERSION >= 2), \
 356     EXCEPTIONS_SECTION, \
 357     INTERRUPTS_SECTION, \
 358     TLB_SECTION, \
 359     DEBUG_SECTION, \
 360     CONFIG_SECTION
 361
 362
 363 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
 364 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0
 365 #endif
 366 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
 367 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0
 368 #endif
 369 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
 370 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0
 371 #endif
 372 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
 373 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0
 374 #endif
 375 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
 376 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0
 377 #endif
 378 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
 379 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0
 380 #endif
 381
 382
 383 #if XCHAL_NUM_INTERRUPTS <= 0
 384 #define XCHAL_INT0_LEVEL 0
 385 #define XCHAL_INT0_TYPE 0
 386 #endif
 387 #if XCHAL_NUM_INTERRUPTS <= 1
 388 #define XCHAL_INT1_LEVEL 0
 389 #define XCHAL_INT1_TYPE 0
 390 #endif
 391 #if XCHAL_NUM_INTERRUPTS <= 2
 392 #define XCHAL_INT2_LEVEL 0
 393 #define XCHAL_INT2_TYPE 0
 394 #endif
 395 #if XCHAL_NUM_INTERRUPTS <= 3
 396 #define XCHAL_INT3_LEVEL 0
 397 #define XCHAL_INT3_TYPE 0
 398 #endif
 399 #if XCHAL_NUM_INTERRUPTS <= 4
 400 #define XCHAL_INT4_LEVEL 0
 401 #define XCHAL_INT4_TYPE 0
 402 #endif
 403 #if XCHAL_NUM_INTERRUPTS <= 5
 404 #define XCHAL_INT5_LEVEL 0
 405 #define XCHAL_INT5_TYPE 0
 406 #endif
 407 #if XCHAL_NUM_INTERRUPTS <= 6
 408 #define XCHAL_INT6_LEVEL 0
 409 #define XCHAL_INT6_TYPE 0
 410 #endif
 411 #if XCHAL_NUM_INTERRUPTS <= 7
 412 #define XCHAL_INT7_LEVEL 0
 413 #define XCHAL_INT7_TYPE 0
 414 #endif
 415 #if XCHAL_NUM_INTERRUPTS <= 8
 416 #define XCHAL_INT8_LEVEL 0
 417 #define XCHAL_INT8_TYPE 0
 418 #endif
 419 #if XCHAL_NUM_INTERRUPTS <= 9
 420 #define XCHAL_INT9_LEVEL 0
 421 #define XCHAL_INT9_TYPE 0
 422 #endif
 423 #if XCHAL_NUM_INTERRUPTS <= 10
 424 #define XCHAL_INT10_LEVEL 0
 425 #define XCHAL_INT10_TYPE 0
 426 #endif
 427 #if XCHAL_NUM_INTERRUPTS <= 11
 428 #define XCHAL_INT11_LEVEL 0
 429 #define XCHAL_INT11_TYPE 0
 430 #endif
 431 #if XCHAL_NUM_INTERRUPTS <= 12
 432 #define XCHAL_INT12_LEVEL 0
 433 #define XCHAL_INT12_TYPE 0
 434 #endif
 435 #if XCHAL_NUM_INTERRUPTS <= 13
 436 #define XCHAL_INT13_LEVEL 0
 437 #define XCHAL_INT13_TYPE 0
 438 #endif
 439 #if XCHAL_NUM_INTERRUPTS <= 14
 440 #define XCHAL_INT14_LEVEL 0
 441 #define XCHAL_INT14_TYPE 0
 442 #endif
 443 #if XCHAL_NUM_INTERRUPTS <= 15
 444 #define XCHAL_INT15_LEVEL 0
 445 #define XCHAL_INT15_TYPE 0
 446 #endif
 447 #if XCHAL_NUM_INTERRUPTS <= 16
 448 #define XCHAL_INT16_LEVEL 0
 449 #define XCHAL_INT16_TYPE 0
 450 #endif
 451 #if XCHAL_NUM_INTERRUPTS <= 17
 452 #define XCHAL_INT17_LEVEL 0
 453 #define XCHAL_INT17_TYPE 0
 454 #endif
 455 #if XCHAL_NUM_INTERRUPTS <= 18
 456 #define XCHAL_INT18_LEVEL 0
 457 #define XCHAL_INT18_TYPE 0
 458 #endif
 459 #if XCHAL_NUM_INTERRUPTS <= 19
 460 #define XCHAL_INT19_LEVEL 0
 461 #define XCHAL_INT19_TYPE 0
 462 #endif
 463 #if XCHAL_NUM_INTERRUPTS <= 20
 464 #define XCHAL_INT20_LEVEL 0
 465 #define XCHAL_INT20_TYPE 0
 466 #endif
 467 #if XCHAL_NUM_INTERRUPTS <= 21
 468 #define XCHAL_INT21_LEVEL 0
 469 #define XCHAL_INT21_TYPE 0
 470 #endif
 471 #if XCHAL_NUM_INTERRUPTS <= 22
 472 #define XCHAL_INT22_LEVEL 0
 473 #define XCHAL_INT22_TYPE 0
 474 #endif
 475 #if XCHAL_NUM_INTERRUPTS <= 23
 476 #define XCHAL_INT23_LEVEL 0
 477 #define XCHAL_INT23_TYPE 0
 478 #endif
 479 #if XCHAL_NUM_INTERRUPTS <= 24
 480 #define XCHAL_INT24_LEVEL 0
 481 #define XCHAL_INT24_TYPE 0
 482 #endif
 483 #if XCHAL_NUM_INTERRUPTS <= 25
 484 #define XCHAL_INT25_LEVEL 0
 485 #define XCHAL_INT25_TYPE 0
 486 #endif
 487 #if XCHAL_NUM_INTERRUPTS <= 26
 488 #define XCHAL_INT26_LEVEL 0
 489 #define XCHAL_INT26_TYPE 0
 490 #endif
 491 #if XCHAL_NUM_INTERRUPTS <= 27
 492 #define XCHAL_INT27_LEVEL 0
 493 #define XCHAL_INT27_TYPE 0
 494 #endif
 495 #if XCHAL_NUM_INTERRUPTS <= 28
 496 #define XCHAL_INT28_LEVEL 0
 497 #define XCHAL_INT28_TYPE 0
 498 #endif
 499 #if XCHAL_NUM_INTERRUPTS <= 29
 500 #define XCHAL_INT29_LEVEL 0
 501 #define XCHAL_INT29_TYPE 0
 502 #endif
 503 #if XCHAL_NUM_INTERRUPTS <= 30
 504 #define XCHAL_INT30_LEVEL 0
 505 #define XCHAL_INT30_TYPE 0
 506 #endif
 507 #if XCHAL_NUM_INTERRUPTS <= 31
 508 #define XCHAL_INT31_LEVEL 0
 509 #define XCHAL_INT31_TYPE 0
 510 #endif
 511
 512
 513 #if XCHAL_NUM_EXTINTERRUPTS <= 0
 514 #define XCHAL_EXTINT0_NUM 0
 515 #endif
 516 #if XCHAL_NUM_EXTINTERRUPTS <= 1
 517 #define XCHAL_EXTINT1_NUM 0
 518 #endif
 519 #if XCHAL_NUM_EXTINTERRUPTS <= 2
 520 #define XCHAL_EXTINT2_NUM 0
 521 #endif
 522 #if XCHAL_NUM_EXTINTERRUPTS <= 3
 523 #define XCHAL_EXTINT3_NUM 0
 524 #endif
 525 #if XCHAL_NUM_EXTINTERRUPTS <= 4
 526 #define XCHAL_EXTINT4_NUM 0
 527 #endif
 528 #if XCHAL_NUM_EXTINTERRUPTS <= 5
 529 #define XCHAL_EXTINT5_NUM 0
 530 #endif
 531 #if XCHAL_NUM_EXTINTERRUPTS <= 6
 532 #define XCHAL_EXTINT6_NUM 0
 533 #endif
 534 #if XCHAL_NUM_EXTINTERRUPTS <= 7
 535 #define XCHAL_EXTINT7_NUM 0
 536 #endif
 537 #if XCHAL_NUM_EXTINTERRUPTS <= 8
 538 #define XCHAL_EXTINT8_NUM 0
 539 #endif
 540 #if XCHAL_NUM_EXTINTERRUPTS <= 9
 541 #define XCHAL_EXTINT9_NUM 0
 542 #endif
 543 #if XCHAL_NUM_EXTINTERRUPTS <= 10
 544 #define XCHAL_EXTINT10_NUM 0
 545 #endif
 546 #if XCHAL_NUM_EXTINTERRUPTS <= 11
 547 #define XCHAL_EXTINT11_NUM 0
 548 #endif
 549 #if XCHAL_NUM_EXTINTERRUPTS <= 12
 550 #define XCHAL_EXTINT12_NUM 0
 551 #endif
 552 #if XCHAL_NUM_EXTINTERRUPTS <= 13
 553 #define XCHAL_EXTINT13_NUM 0
 554 #endif
 555 #if XCHAL_NUM_EXTINTERRUPTS <= 14
 556 #define XCHAL_EXTINT14_NUM 0
 557 #endif
 558 #if XCHAL_NUM_EXTINTERRUPTS <= 15
 559 #define XCHAL_EXTINT15_NUM 0
 560 #endif
 561 #if XCHAL_NUM_EXTINTERRUPTS <= 16
 562 #define XCHAL_EXTINT16_NUM 0
 563 #endif
 564 #if XCHAL_NUM_EXTINTERRUPTS <= 17
 565 #define XCHAL_EXTINT17_NUM 0
 566 #endif
 567 #if XCHAL_NUM_EXTINTERRUPTS <= 18
 568 #define XCHAL_EXTINT18_NUM 0
 569 #endif
 570 #if XCHAL_NUM_EXTINTERRUPTS <= 19
 571 #define XCHAL_EXTINT19_NUM 0
 572 #endif
 573 #if XCHAL_NUM_EXTINTERRUPTS <= 20
 574 #define XCHAL_EXTINT20_NUM 0
 575 #endif
 576 #if XCHAL_NUM_EXTINTERRUPTS <= 21
 577 #define XCHAL_EXTINT21_NUM 0
 578 #endif
 579 #if XCHAL_NUM_EXTINTERRUPTS <= 22
 580 #define XCHAL_EXTINT22_NUM 0
 581 #endif
 582 #if XCHAL_NUM_EXTINTERRUPTS <= 23
 583 #define XCHAL_EXTINT23_NUM 0
 584 #endif
 585 #if XCHAL_NUM_EXTINTERRUPTS <= 24
 586 #define XCHAL_EXTINT24_NUM 0
 587 #endif
 588 #if XCHAL_NUM_EXTINTERRUPTS <= 25
 589 #define XCHAL_EXTINT25_NUM 0
 590 #endif
 591 #if XCHAL_NUM_EXTINTERRUPTS <= 26
 592 #define XCHAL_EXTINT26_NUM 0
 593 #endif
 594 #if XCHAL_NUM_EXTINTERRUPTS <= 27
 595 #define XCHAL_EXTINT27_NUM 0
 596 #endif
 597 #if XCHAL_NUM_EXTINTERRUPTS <= 28
 598 #define XCHAL_EXTINT28_NUM 0
 599 #endif
 600 #if XCHAL_NUM_EXTINTERRUPTS <= 29
 601 #define XCHAL_EXTINT29_NUM 0
 602 #endif
 603 #if XCHAL_NUM_EXTINTERRUPTS <= 30
 604 #define XCHAL_EXTINT30_NUM 0
 605 #endif
 606 #if XCHAL_NUM_EXTINTERRUPTS <= 31
 607 #define XCHAL_EXTINT31_NUM 0
 608 #endif
 609
 610
 611 #define XTHAL_TIMER_UNCONFIGURED 0