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target/xtensa: fix access ring in l32ex
[mirror_qemu.git] / target / xtensa / translate.c
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qemu/osdep.h"
32
33 #include "cpu.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg/tcg-op.h"
37 #include "qemu/log.h"
38 #include "qemu/qemu-print.h"
39 #include "exec/cpu_ldst.h"
40 #include "semihosting/semihost.h"
41 #include "exec/translator.h"
42
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
45
46 #include "trace-tcg.h"
47 #include "exec/log.h"
48
49
50 struct DisasContext {
51 DisasContextBase base;
52 const XtensaConfig *config;
53 uint32_t pc;
54 int cring;
55 int ring;
56 uint32_t lbeg_off;
57 uint32_t lend;
58
59 bool sar_5bit;
60 bool sar_m32_5bit;
61 bool sar_m32_allocated;
62 TCGv_i32 sar_m32;
63
64 unsigned window;
65 unsigned callinc;
66 bool cwoe;
67
68 bool debug;
69 bool icount;
70 TCGv_i32 next_icount;
71
72 unsigned cpenable;
73
74 uint32_t op_flags;
75 xtensa_insnbuf_word insnbuf[MAX_INSNBUF_LENGTH];
76 xtensa_insnbuf_word slotbuf[MAX_INSNBUF_LENGTH];
77 };
78
79 static TCGv_i32 cpu_pc;
80 static TCGv_i32 cpu_R[16];
81 static TCGv_i32 cpu_FR[16];
82 static TCGv_i64 cpu_FRD[16];
83 static TCGv_i32 cpu_MR[4];
84 static TCGv_i32 cpu_BR[16];
85 static TCGv_i32 cpu_BR4[4];
86 static TCGv_i32 cpu_BR8[2];
87 static TCGv_i32 cpu_SR[256];
88 static TCGv_i32 cpu_UR[256];
89 static TCGv_i32 cpu_windowbase_next;
90 static TCGv_i32 cpu_exclusive_addr;
91 static TCGv_i32 cpu_exclusive_val;
92
93 static GHashTable *xtensa_regfile_table;
94
95 #include "exec/gen-icount.h"
96
97 static char *sr_name[256];
98 static char *ur_name[256];
99
100 void xtensa_collect_sr_names(const XtensaConfig *config)
101 {
102 xtensa_isa isa = config->isa;
103 int n = xtensa_isa_num_sysregs(isa);
104 int i;
105
106 for (i = 0; i < n; ++i) {
107 int sr = xtensa_sysreg_number(isa, i);
108
109 if (sr >= 0 && sr < 256) {
110 const char *name = xtensa_sysreg_name(isa, i);
111 char **pname =
112 (xtensa_sysreg_is_user(isa, i) ? ur_name : sr_name) + sr;
113
114 if (*pname) {
115 if (strstr(*pname, name) == NULL) {
116 char *new_name =
117 malloc(strlen(*pname) + strlen(name) + 2);
118
119 strcpy(new_name, *pname);
120 strcat(new_name, "/");
121 strcat(new_name, name);
122 free(*pname);
123 *pname = new_name;
124 }
125 } else {
126 *pname = strdup(name);
127 }
128 }
129 }
130 }
131
132 void xtensa_translate_init(void)
133 {
134 static const char * const regnames[] = {
135 "ar0", "ar1", "ar2", "ar3",
136 "ar4", "ar5", "ar6", "ar7",
137 "ar8", "ar9", "ar10", "ar11",
138 "ar12", "ar13", "ar14", "ar15",
139 };
140 static const char * const fregnames[] = {
141 "f0", "f1", "f2", "f3",
142 "f4", "f5", "f6", "f7",
143 "f8", "f9", "f10", "f11",
144 "f12", "f13", "f14", "f15",
145 };
146 static const char * const mregnames[] = {
147 "m0", "m1", "m2", "m3",
148 };
149 static const char * const bregnames[] = {
150 "b0", "b1", "b2", "b3",
151 "b4", "b5", "b6", "b7",
152 "b8", "b9", "b10", "b11",
153 "b12", "b13", "b14", "b15",
154 };
155 int i;
156
157 cpu_pc = tcg_global_mem_new_i32(cpu_env,
158 offsetof(CPUXtensaState, pc), "pc");
159
160 for (i = 0; i < 16; i++) {
161 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
162 offsetof(CPUXtensaState, regs[i]),
163 regnames[i]);
164 }
165
166 for (i = 0; i < 16; i++) {
167 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
168 offsetof(CPUXtensaState,
169 fregs[i].f32[FP_F32_LOW]),
170 fregnames[i]);
171 }
172
173 for (i = 0; i < 16; i++) {
174 cpu_FRD[i] = tcg_global_mem_new_i64(cpu_env,
175 offsetof(CPUXtensaState,
176 fregs[i].f64),
177 fregnames[i]);
178 }
179
180 for (i = 0; i < 4; i++) {
181 cpu_MR[i] = tcg_global_mem_new_i32(cpu_env,
182 offsetof(CPUXtensaState,
183 sregs[MR + i]),
184 mregnames[i]);
185 }
186
187 for (i = 0; i < 16; i++) {
188 cpu_BR[i] = tcg_global_mem_new_i32(cpu_env,
189 offsetof(CPUXtensaState,
190 sregs[BR]),
191 bregnames[i]);
192 if (i % 4 == 0) {
193 cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env,
194 offsetof(CPUXtensaState,
195 sregs[BR]),
196 bregnames[i]);
197 }
198 if (i % 8 == 0) {
199 cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env,
200 offsetof(CPUXtensaState,
201 sregs[BR]),
202 bregnames[i]);
203 }
204 }
205
206 for (i = 0; i < 256; ++i) {
207 if (sr_name[i]) {
208 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
209 offsetof(CPUXtensaState,
210 sregs[i]),
211 sr_name[i]);
212 }
213 }
214
215 for (i = 0; i < 256; ++i) {
216 if (ur_name[i]) {
217 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
218 offsetof(CPUXtensaState,
219 uregs[i]),
220 ur_name[i]);
221 }
222 }
223
224 cpu_windowbase_next =
225 tcg_global_mem_new_i32(cpu_env,
226 offsetof(CPUXtensaState, windowbase_next),
227 "windowbase_next");
228 cpu_exclusive_addr =
229 tcg_global_mem_new_i32(cpu_env,
230 offsetof(CPUXtensaState, exclusive_addr),
231 "exclusive_addr");
232 cpu_exclusive_val =
233 tcg_global_mem_new_i32(cpu_env,
234 offsetof(CPUXtensaState, exclusive_val),
235 "exclusive_val");
236 }
237
238 void **xtensa_get_regfile_by_name(const char *name, int entries, int bits)
239 {
240 char *geometry_name;
241 void **res;
242
243 if (xtensa_regfile_table == NULL) {
244 xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal);
245 /*
246 * AR is special. Xtensa translator uses it as a current register
247 * window, but configuration overlays represent it as a complete
248 * physical register file.
249 */
250 g_hash_table_insert(xtensa_regfile_table,
251 (void *)"AR 16x32", (void *)cpu_R);
252 g_hash_table_insert(xtensa_regfile_table,
253 (void *)"AR 32x32", (void *)cpu_R);
254 g_hash_table_insert(xtensa_regfile_table,
255 (void *)"AR 64x32", (void *)cpu_R);
256
257 g_hash_table_insert(xtensa_regfile_table,
258 (void *)"MR 4x32", (void *)cpu_MR);
259
260 g_hash_table_insert(xtensa_regfile_table,
261 (void *)"FR 16x32", (void *)cpu_FR);
262 g_hash_table_insert(xtensa_regfile_table,
263 (void *)"FR 16x64", (void *)cpu_FRD);
264
265 g_hash_table_insert(xtensa_regfile_table,
266 (void *)"BR 16x1", (void *)cpu_BR);
267 g_hash_table_insert(xtensa_regfile_table,
268 (void *)"BR4 4x4", (void *)cpu_BR4);
269 g_hash_table_insert(xtensa_regfile_table,
270 (void *)"BR8 2x8", (void *)cpu_BR8);
271 }
272
273 geometry_name = g_strdup_printf("%s %dx%d", name, entries, bits);
274 res = (void **)g_hash_table_lookup(xtensa_regfile_table, geometry_name);
275 g_free(geometry_name);
276 return res;
277 }
278
279 static inline bool option_enabled(DisasContext *dc, int opt)
280 {
281 return xtensa_option_enabled(dc->config, opt);
282 }
283
284 static void init_sar_tracker(DisasContext *dc)
285 {
286 dc->sar_5bit = false;
287 dc->sar_m32_5bit = false;
288 dc->sar_m32_allocated = false;
289 }
290
291 static void reset_sar_tracker(DisasContext *dc)
292 {
293 if (dc->sar_m32_allocated) {
294 tcg_temp_free(dc->sar_m32);
295 }
296 }
297
298 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
299 {
300 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
301 if (dc->sar_m32_5bit) {
302 tcg_gen_discard_i32(dc->sar_m32);
303 }
304 dc->sar_5bit = true;
305 dc->sar_m32_5bit = false;
306 }
307
308 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
309 {
310 TCGv_i32 tmp = tcg_const_i32(32);
311 if (!dc->sar_m32_allocated) {
312 dc->sar_m32 = tcg_temp_local_new_i32();
313 dc->sar_m32_allocated = true;
314 }
315 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
316 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
317 dc->sar_5bit = false;
318 dc->sar_m32_5bit = true;
319 tcg_temp_free(tmp);
320 }
321
322 static void gen_exception(DisasContext *dc, int excp)
323 {
324 TCGv_i32 tmp = tcg_const_i32(excp);
325 gen_helper_exception(cpu_env, tmp);
326 tcg_temp_free(tmp);
327 }
328
329 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
330 {
331 TCGv_i32 tpc = tcg_const_i32(dc->pc);
332 TCGv_i32 tcause = tcg_const_i32(cause);
333 gen_helper_exception_cause(cpu_env, tpc, tcause);
334 tcg_temp_free(tpc);
335 tcg_temp_free(tcause);
336 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
337 cause == SYSCALL_CAUSE) {
338 dc->base.is_jmp = DISAS_NORETURN;
339 }
340 }
341
342 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
343 TCGv_i32 vaddr)
344 {
345 TCGv_i32 tpc = tcg_const_i32(dc->pc);
346 TCGv_i32 tcause = tcg_const_i32(cause);
347 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
348 tcg_temp_free(tpc);
349 tcg_temp_free(tcause);
350 }
351
352 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
353 {
354 TCGv_i32 tpc = tcg_const_i32(dc->pc);
355 TCGv_i32 tcause = tcg_const_i32(cause);
356 gen_helper_debug_exception(cpu_env, tpc, tcause);
357 tcg_temp_free(tpc);
358 tcg_temp_free(tcause);
359 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
360 dc->base.is_jmp = DISAS_NORETURN;
361 }
362 }
363
364 static bool gen_check_privilege(DisasContext *dc)
365 {
366 #ifndef CONFIG_USER_ONLY
367 if (!dc->cring) {
368 return true;
369 }
370 #endif
371 gen_exception_cause(dc, PRIVILEGED_CAUSE);
372 dc->base.is_jmp = DISAS_NORETURN;
373 return false;
374 }
375
376 static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask)
377 {
378 cp_mask &= ~dc->cpenable;
379
380 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) {
381 gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask));
382 dc->base.is_jmp = DISAS_NORETURN;
383 return false;
384 }
385 return true;
386 }
387
388 static int gen_postprocess(DisasContext *dc, int slot);
389
390 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
391 {
392 tcg_gen_mov_i32(cpu_pc, dest);
393 if (dc->icount) {
394 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
395 }
396 if (dc->base.singlestep_enabled) {
397 gen_exception(dc, EXCP_DEBUG);
398 } else {
399 if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
400 slot = gen_postprocess(dc, slot);
401 }
402 if (slot >= 0) {
403 tcg_gen_goto_tb(slot);
404 tcg_gen_exit_tb(dc->base.tb, slot);
405 } else {
406 tcg_gen_exit_tb(NULL, 0);
407 }
408 }
409 dc->base.is_jmp = DISAS_NORETURN;
410 }
411
412 static void gen_jump(DisasContext *dc, TCGv dest)
413 {
414 gen_jump_slot(dc, dest, -1);
415 }
416
417 static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot)
418 {
419 if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) {
420 return -1;
421 } else {
422 return slot;
423 }
424 }
425
426 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
427 {
428 TCGv_i32 tmp = tcg_const_i32(dest);
429 gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot));
430 tcg_temp_free(tmp);
431 }
432
433 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
434 int slot)
435 {
436 TCGv_i32 tcallinc = tcg_const_i32(callinc);
437
438 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
439 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
440 tcg_temp_free(tcallinc);
441 tcg_gen_movi_i32(cpu_R[callinc << 2],
442 (callinc << 30) | (dc->base.pc_next & 0x3fffffff));
443 gen_jump_slot(dc, dest, slot);
444 }
445
446 static bool gen_check_loop_end(DisasContext *dc, int slot)
447 {
448 if (dc->base.pc_next == dc->lend) {
449 TCGLabel *label = gen_new_label();
450
451 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
452 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
453 if (dc->lbeg_off) {
454 gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot);
455 } else {
456 gen_jump(dc, cpu_SR[LBEG]);
457 }
458 gen_set_label(label);
459 gen_jumpi(dc, dc->base.pc_next, -1);
460 return true;
461 }
462 return false;
463 }
464
465 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
466 {
467 if (!gen_check_loop_end(dc, slot)) {
468 gen_jumpi(dc, dc->base.pc_next, slot);
469 }
470 }
471
472 static void gen_brcond(DisasContext *dc, TCGCond cond,
473 TCGv_i32 t0, TCGv_i32 t1, uint32_t addr)
474 {
475 TCGLabel *label = gen_new_label();
476
477 tcg_gen_brcond_i32(cond, t0, t1, label);
478 gen_jumpi_check_loop_end(dc, 0);
479 gen_set_label(label);
480 gen_jumpi(dc, addr, 1);
481 }
482
483 static void gen_brcondi(DisasContext *dc, TCGCond cond,
484 TCGv_i32 t0, uint32_t t1, uint32_t addr)
485 {
486 TCGv_i32 tmp = tcg_const_i32(t1);
487 gen_brcond(dc, cond, t0, tmp, addr);
488 tcg_temp_free(tmp);
489 }
490
491 static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
492 const uint32_t par[])
493 {
494 return xtensa_option_enabled(dc->config, par[1]) ? 0 : XTENSA_OP_ILL;
495 }
496
497 static uint32_t test_exceptions_ccompare(DisasContext *dc,
498 const OpcodeArg arg[],
499 const uint32_t par[])
500 {
501 unsigned n = par[0] - CCOMPARE;
502
503 if (n >= dc->config->nccompare) {
504 return XTENSA_OP_ILL;
505 }
506 return test_exceptions_sr(dc, arg, par);
507 }
508
509 static uint32_t test_exceptions_dbreak(DisasContext *dc, const OpcodeArg arg[],
510 const uint32_t par[])
511 {
512 unsigned n = MAX_NDBREAK;
513
514 if (par[0] >= DBREAKA && par[0] < DBREAKA + MAX_NDBREAK) {
515 n = par[0] - DBREAKA;
516 }
517 if (par[0] >= DBREAKC && par[0] < DBREAKC + MAX_NDBREAK) {
518 n = par[0] - DBREAKC;
519 }
520 if (n >= dc->config->ndbreak) {
521 return XTENSA_OP_ILL;
522 }
523 return test_exceptions_sr(dc, arg, par);
524 }
525
526 static uint32_t test_exceptions_ibreak(DisasContext *dc, const OpcodeArg arg[],
527 const uint32_t par[])
528 {
529 unsigned n = par[0] - IBREAKA;
530
531 if (n >= dc->config->nibreak) {
532 return XTENSA_OP_ILL;
533 }
534 return test_exceptions_sr(dc, arg, par);
535 }
536
537 static uint32_t test_exceptions_hpi(DisasContext *dc, const OpcodeArg arg[],
538 const uint32_t par[])
539 {
540 unsigned n = MAX_NLEVEL + 1;
541
542 if (par[0] >= EXCSAVE1 && par[0] < EXCSAVE1 + MAX_NLEVEL) {
543 n = par[0] - EXCSAVE1 + 1;
544 }
545 if (par[0] >= EPC1 && par[0] < EPC1 + MAX_NLEVEL) {
546 n = par[0] - EPC1 + 1;
547 }
548 if (par[0] >= EPS2 && par[0] < EPS2 + MAX_NLEVEL - 1) {
549 n = par[0] - EPS2 + 2;
550 }
551 if (n > dc->config->nlevel) {
552 return XTENSA_OP_ILL;
553 }
554 return test_exceptions_sr(dc, arg, par);
555 }
556
557 static void gen_load_store_alignment(DisasContext *dc, int shift,
558 TCGv_i32 addr, bool no_hw_alignment)
559 {
560 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
561 tcg_gen_andi_i32(addr, addr, ~0 << shift);
562 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
563 no_hw_alignment) {
564 TCGLabel *label = gen_new_label();
565 TCGv_i32 tmp = tcg_temp_new_i32();
566 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
567 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
568 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
569 gen_set_label(label);
570 tcg_temp_free(tmp);
571 }
572 }
573
574 #ifndef CONFIG_USER_ONLY
575 static void gen_waiti(DisasContext *dc, uint32_t imm4)
576 {
577 TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
578 TCGv_i32 intlevel = tcg_const_i32(imm4);
579
580 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
581 gen_io_start();
582 }
583 gen_helper_waiti(cpu_env, pc, intlevel);
584 tcg_temp_free(pc);
585 tcg_temp_free(intlevel);
586 }
587 #endif
588
589 static bool gen_window_check(DisasContext *dc, uint32_t mask)
590 {
591 unsigned r = 31 - clz32(mask);
592
593 if (r / 4 > dc->window) {
594 TCGv_i32 pc = tcg_const_i32(dc->pc);
595 TCGv_i32 w = tcg_const_i32(r / 4);
596
597 gen_helper_window_check(cpu_env, pc, w);
598 dc->base.is_jmp = DISAS_NORETURN;
599 return false;
600 }
601 return true;
602 }
603
604 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
605 {
606 TCGv_i32 m = tcg_temp_new_i32();
607
608 if (hi) {
609 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
610 } else {
611 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
612 }
613 return m;
614 }
615
616 static void gen_zero_check(DisasContext *dc, const OpcodeArg arg[])
617 {
618 TCGLabel *label = gen_new_label();
619
620 tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0, label);
621 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
622 gen_set_label(label);
623 }
624
625 static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0)
626 {
627 return xtensa_isa_length_from_chars(dc->config->isa, &op0);
628 }
629
630 static int gen_postprocess(DisasContext *dc, int slot)
631 {
632 uint32_t op_flags = dc->op_flags;
633
634 #ifndef CONFIG_USER_ONLY
635 if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
636 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
637 gen_io_start();
638 }
639 gen_helper_check_interrupts(cpu_env);
640 }
641 #endif
642 if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
643 gen_helper_sync_windowbase(cpu_env);
644 }
645 if (op_flags & XTENSA_OP_EXIT_TB_M1) {
646 slot = -1;
647 }
648 return slot;
649 }
650
651 struct opcode_arg_copy {
652 uint32_t resource;
653 void *temp;
654 OpcodeArg *arg;
655 };
656
657 struct opcode_arg_info {
658 uint32_t resource;
659 int index;
660 };
661
662 struct slot_prop {
663 XtensaOpcodeOps *ops;
664 OpcodeArg arg[MAX_OPCODE_ARGS];
665 struct opcode_arg_info in[MAX_OPCODE_ARGS];
666 struct opcode_arg_info out[MAX_OPCODE_ARGS];
667 unsigned n_in;
668 unsigned n_out;
669 uint32_t op_flags;
670 };
671
672 enum resource_type {
673 RES_REGFILE,
674 RES_STATE,
675 RES_MAX,
676 };
677
678 static uint32_t encode_resource(enum resource_type r, unsigned g, unsigned n)
679 {
680 assert(r < RES_MAX && g < 256 && n < 65536);
681 return (r << 24) | (g << 16) | n;
682 }
683
684 static enum resource_type get_resource_type(uint32_t resource)
685 {
686 return resource >> 24;
687 }
688
689 /*
690 * a depends on b if b must be executed before a,
691 * because a's side effects will destroy b's inputs.
692 */
693 static bool op_depends_on(const struct slot_prop *a,
694 const struct slot_prop *b)
695 {
696 unsigned i = 0;
697 unsigned j = 0;
698
699 if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
700 return true;
701 }
702 if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
703 (b->op_flags & XTENSA_OP_LOAD_STORE)) {
704 return true;
705 }
706 while (i < a->n_out && j < b->n_in) {
707 if (a->out[i].resource < b->in[j].resource) {
708 ++i;
709 } else if (a->out[i].resource > b->in[j].resource) {
710 ++j;
711 } else {
712 return true;
713 }
714 }
715 return false;
716 }
717
718 /*
719 * Try to break a dependency on b, append temporary register copy records
720 * to the end of copy and update n_copy in case of success.
721 * This is not always possible: e.g. control flow must always be the last,
722 * load/store must be first and state dependencies are not supported yet.
723 */
724 static bool break_dependency(struct slot_prop *a,
725 struct slot_prop *b,
726 struct opcode_arg_copy *copy,
727 unsigned *n_copy)
728 {
729 unsigned i = 0;
730 unsigned j = 0;
731 unsigned n = *n_copy;
732 bool rv = false;
733
734 if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
735 return false;
736 }
737 if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
738 (b->op_flags & XTENSA_OP_LOAD_STORE)) {
739 return false;
740 }
741 while (i < a->n_out && j < b->n_in) {
742 if (a->out[i].resource < b->in[j].resource) {
743 ++i;
744 } else if (a->out[i].resource > b->in[j].resource) {
745 ++j;
746 } else {
747 int index = b->in[j].index;
748
749 if (get_resource_type(a->out[i].resource) != RES_REGFILE ||
750 index < 0) {
751 return false;
752 }
753 copy[n].resource = b->in[j].resource;
754 copy[n].arg = b->arg + index;
755 ++n;
756 ++j;
757 rv = true;
758 }
759 }
760 *n_copy = n;
761 return rv;
762 }
763
764 /*
765 * Calculate evaluation order for slot opcodes.
766 * Build opcode order graph and output its nodes in topological sort order.
767 * An edge a -> b in the graph means that opcode a must be followed by
768 * opcode b.
769 */
770 static bool tsort(struct slot_prop *slot,
771 struct slot_prop *sorted[],
772 unsigned n,
773 struct opcode_arg_copy *copy,
774 unsigned *n_copy)
775 {
776 struct tsnode {
777 unsigned n_in_edge;
778 unsigned n_out_edge;
779 unsigned out_edge[MAX_INSN_SLOTS];
780 } node[MAX_INSN_SLOTS];
781
782 unsigned in[MAX_INSN_SLOTS];
783 unsigned i, j;
784 unsigned n_in = 0;
785 unsigned n_out = 0;
786 unsigned n_edge = 0;
787 unsigned in_idx = 0;
788 unsigned node_idx = 0;
789
790 for (i = 0; i < n; ++i) {
791 node[i].n_in_edge = 0;
792 node[i].n_out_edge = 0;
793 }
794
795 for (i = 0; i < n; ++i) {
796 unsigned n_out_edge = 0;
797
798 for (j = 0; j < n; ++j) {
799 if (i != j && op_depends_on(slot + j, slot + i)) {
800 node[i].out_edge[n_out_edge] = j;
801 ++node[j].n_in_edge;
802 ++n_out_edge;
803 ++n_edge;
804 }
805 }
806 node[i].n_out_edge = n_out_edge;
807 }
808
809 for (i = 0; i < n; ++i) {
810 if (!node[i].n_in_edge) {
811 in[n_in] = i;
812 ++n_in;
813 }
814 }
815
816 again:
817 for (; in_idx < n_in; ++in_idx) {
818 i = in[in_idx];
819 sorted[n_out] = slot + i;
820 ++n_out;
821 for (j = 0; j < node[i].n_out_edge; ++j) {
822 --n_edge;
823 if (--node[node[i].out_edge[j]].n_in_edge == 0) {
824 in[n_in] = node[i].out_edge[j];
825 ++n_in;
826 }
827 }
828 }
829 if (n_edge) {
830 for (; node_idx < n; ++node_idx) {
831 struct tsnode *cnode = node + node_idx;
832
833 if (cnode->n_in_edge) {
834 for (j = 0; j < cnode->n_out_edge; ++j) {
835 unsigned k = cnode->out_edge[j];
836
837 if (break_dependency(slot + k, slot + node_idx,
838 copy, n_copy) &&
839 --node[k].n_in_edge == 0) {
840 in[n_in] = k;
841 ++n_in;
842 --n_edge;
843 cnode->out_edge[j] =
844 cnode->out_edge[cnode->n_out_edge - 1];
845 --cnode->n_out_edge;
846 goto again;
847 }
848 }
849 }
850 }
851 }
852 return n_edge == 0;
853 }
854
855 static void opcode_add_resource(struct slot_prop *op,
856 uint32_t resource, char direction,
857 int index)
858 {
859 switch (direction) {
860 case 'm':
861 case 'i':
862 assert(op->n_in < ARRAY_SIZE(op->in));
863 op->in[op->n_in].resource = resource;
864 op->in[op->n_in].index = index;
865 ++op->n_in;
866 /* fall through */
867 case 'o':
868 if (direction == 'm' || direction == 'o') {
869 assert(op->n_out < ARRAY_SIZE(op->out));
870 op->out[op->n_out].resource = resource;
871 op->out[op->n_out].index = index;
872 ++op->n_out;
873 }
874 break;
875 default:
876 g_assert_not_reached();
877 }
878 }
879
880 static int resource_compare(const void *a, const void *b)
881 {
882 const struct opcode_arg_info *pa = a;
883 const struct opcode_arg_info *pb = b;
884
885 return pa->resource < pb->resource ?
886 -1 : (pa->resource > pb->resource ? 1 : 0);
887 }
888
889 static int arg_copy_compare(const void *a, const void *b)
890 {
891 const struct opcode_arg_copy *pa = a;
892 const struct opcode_arg_copy *pb = b;
893
894 return pa->resource < pb->resource ?
895 -1 : (pa->resource > pb->resource ? 1 : 0);
896 }
897
898 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
899 {
900 xtensa_isa isa = dc->config->isa;
901 unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)};
902 unsigned len = xtensa_op0_insn_len(dc, b[0]);
903 xtensa_format fmt;
904 int slot, slots;
905 unsigned i;
906 uint32_t op_flags = 0;
907 struct slot_prop slot_prop[MAX_INSN_SLOTS];
908 struct slot_prop *ordered[MAX_INSN_SLOTS];
909 struct opcode_arg_copy arg_copy[MAX_INSN_SLOTS * MAX_OPCODE_ARGS];
910 unsigned n_arg_copy = 0;
911 uint32_t debug_cause = 0;
912 uint32_t windowed_register = 0;
913 uint32_t coprocessor = 0;
914
915 if (len == XTENSA_UNDEFINED) {
916 qemu_log_mask(LOG_GUEST_ERROR,
917 "unknown instruction length (pc = %08x)\n",
918 dc->pc);
919 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
920 dc->base.pc_next = dc->pc + 1;
921 return;
922 }
923
924 dc->base.pc_next = dc->pc + len;
925 for (i = 1; i < len; ++i) {
926 b[i] = translator_ldub(env, dc->pc + i);
927 }
928 xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
929 fmt = xtensa_format_decode(isa, dc->insnbuf);
930 if (fmt == XTENSA_UNDEFINED) {
931 qemu_log_mask(LOG_GUEST_ERROR,
932 "unrecognized instruction format (pc = %08x)\n",
933 dc->pc);
934 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
935 return;
936 }
937 slots = xtensa_format_num_slots(isa, fmt);
938 for (slot = 0; slot < slots; ++slot) {
939 xtensa_opcode opc;
940 int opnd, vopnd, opnds;
941 OpcodeArg *arg = slot_prop[slot].arg;
942 XtensaOpcodeOps *ops;
943
944 xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf);
945 opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf);
946 if (opc == XTENSA_UNDEFINED) {
947 qemu_log_mask(LOG_GUEST_ERROR,
948 "unrecognized opcode in slot %d (pc = %08x)\n",
949 slot, dc->pc);
950 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
951 return;
952 }
953 opnds = xtensa_opcode_num_operands(isa, opc);
954
955 for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
956 void **register_file = NULL;
957 xtensa_regfile rf;
958
959 if (xtensa_operand_is_register(isa, opc, opnd)) {
960 rf = xtensa_operand_regfile(isa, opc, opnd);
961 register_file = dc->config->regfile[rf];
962
963 if (rf == dc->config->a_regfile) {
964 uint32_t v;
965
966 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
967 dc->slotbuf, &v);
968 xtensa_operand_decode(isa, opc, opnd, &v);
969 windowed_register |= 1u << v;
970 }
971 }
972 if (xtensa_operand_is_visible(isa, opc, opnd)) {
973 uint32_t v;
974
975 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
976 dc->slotbuf, &v);
977 xtensa_operand_decode(isa, opc, opnd, &v);
978 arg[vopnd].raw_imm = v;
979 if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
980 xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc);
981 }
982 arg[vopnd].imm = v;
983 if (register_file) {
984 arg[vopnd].in = register_file[v];
985 arg[vopnd].out = register_file[v];
986 arg[vopnd].num_bits = xtensa_regfile_num_bits(isa, rf);
987 } else {
988 arg[vopnd].num_bits = 32;
989 }
990 ++vopnd;
991 }
992 }
993 ops = dc->config->opcode_ops[opc];
994 slot_prop[slot].ops = ops;
995
996 if (ops) {
997 op_flags |= ops->op_flags;
998 if (ops->test_exceptions) {
999 op_flags |= ops->test_exceptions(dc, arg, ops->par);
1000 }
1001 } else {
1002 qemu_log_mask(LOG_UNIMP,
1003 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
1004 xtensa_opcode_name(isa, opc), slot, dc->pc);
1005 op_flags |= XTENSA_OP_ILL;
1006 }
1007 if (op_flags & XTENSA_OP_ILL) {
1008 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1009 return;
1010 }
1011 if (op_flags & XTENSA_OP_DEBUG_BREAK) {
1012 debug_cause |= ops->par[0];
1013 }
1014 if (ops->test_overflow) {
1015 windowed_register |= ops->test_overflow(dc, arg, ops->par);
1016 }
1017 coprocessor |= ops->coprocessor;
1018
1019 if (slots > 1) {
1020 slot_prop[slot].n_in = 0;
1021 slot_prop[slot].n_out = 0;
1022 slot_prop[slot].op_flags = ops->op_flags & XTENSA_OP_LOAD_STORE;
1023
1024 opnds = xtensa_opcode_num_operands(isa, opc);
1025
1026 for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
1027 bool visible = xtensa_operand_is_visible(isa, opc, opnd);
1028
1029 if (xtensa_operand_is_register(isa, opc, opnd)) {
1030 xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
1031 uint32_t v = 0;
1032
1033 xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
1034 dc->slotbuf, &v);
1035 xtensa_operand_decode(isa, opc, opnd, &v);
1036 opcode_add_resource(slot_prop + slot,
1037 encode_resource(RES_REGFILE, rf, v),
1038 xtensa_operand_inout(isa, opc, opnd),
1039 visible ? vopnd : -1);
1040 }
1041 if (visible) {
1042 ++vopnd;
1043 }
1044 }
1045
1046 opnds = xtensa_opcode_num_stateOperands(isa, opc);
1047
1048 for (opnd = 0; opnd < opnds; ++opnd) {
1049 xtensa_state state = xtensa_stateOperand_state(isa, opc, opnd);
1050
1051 opcode_add_resource(slot_prop + slot,
1052 encode_resource(RES_STATE, 0, state),
1053 xtensa_stateOperand_inout(isa, opc, opnd),
1054 -1);
1055 }
1056 if (xtensa_opcode_is_branch(isa, opc) ||
1057 xtensa_opcode_is_jump(isa, opc) ||
1058 xtensa_opcode_is_loop(isa, opc) ||
1059 xtensa_opcode_is_call(isa, opc)) {
1060 slot_prop[slot].op_flags |= XTENSA_OP_CONTROL_FLOW;
1061 }
1062
1063 qsort(slot_prop[slot].in, slot_prop[slot].n_in,
1064 sizeof(slot_prop[slot].in[0]), resource_compare);
1065 qsort(slot_prop[slot].out, slot_prop[slot].n_out,
1066 sizeof(slot_prop[slot].out[0]), resource_compare);
1067 }
1068 }
1069
1070 if (slots > 1) {
1071 if (!tsort(slot_prop, ordered, slots, arg_copy, &n_arg_copy)) {
1072 qemu_log_mask(LOG_UNIMP,
1073 "Circular resource dependencies (pc = %08x)\n",
1074 dc->pc);
1075 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1076 return;
1077 }
1078 } else {
1079 ordered[0] = slot_prop + 0;
1080 }
1081
1082 if ((op_flags & XTENSA_OP_PRIVILEGED) &&
1083 !gen_check_privilege(dc)) {
1084 return;
1085 }
1086
1087 if (op_flags & XTENSA_OP_SYSCALL) {
1088 gen_exception_cause(dc, SYSCALL_CAUSE);
1089 return;
1090 }
1091
1092 if ((op_flags & XTENSA_OP_DEBUG_BREAK) && dc->debug) {
1093 gen_debug_exception(dc, debug_cause);
1094 return;
1095 }
1096
1097 if (windowed_register && !gen_window_check(dc, windowed_register)) {
1098 return;
1099 }
1100
1101 if (op_flags & XTENSA_OP_UNDERFLOW) {
1102 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1103
1104 gen_helper_test_underflow_retw(cpu_env, tmp);
1105 tcg_temp_free(tmp);
1106 }
1107
1108 if (op_flags & XTENSA_OP_ALLOCA) {
1109 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1110
1111 gen_helper_movsp(cpu_env, tmp);
1112 tcg_temp_free(tmp);
1113 }
1114
1115 if (coprocessor && !gen_check_cpenable(dc, coprocessor)) {
1116 return;
1117 }
1118
1119 if (n_arg_copy) {
1120 uint32_t resource;
1121 void *temp;
1122 unsigned j;
1123
1124 qsort(arg_copy, n_arg_copy, sizeof(*arg_copy), arg_copy_compare);
1125 for (i = j = 0; i < n_arg_copy; ++i) {
1126 if (i == 0 || arg_copy[i].resource != resource) {
1127 resource = arg_copy[i].resource;
1128 if (arg_copy[i].arg->num_bits <= 32) {
1129 temp = tcg_temp_local_new_i32();
1130 tcg_gen_mov_i32(temp, arg_copy[i].arg->in);
1131 } else if (arg_copy[i].arg->num_bits <= 64) {
1132 temp = tcg_temp_local_new_i64();
1133 tcg_gen_mov_i64(temp, arg_copy[i].arg->in);
1134 } else {
1135 g_assert_not_reached();
1136 }
1137 arg_copy[i].temp = temp;
1138
1139 if (i != j) {
1140 arg_copy[j] = arg_copy[i];
1141 }
1142 ++j;
1143 }
1144 arg_copy[i].arg->in = temp;
1145 }
1146 n_arg_copy = j;
1147 }
1148
1149 if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
1150 for (slot = 0; slot < slots; ++slot) {
1151 if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) {
1152 gen_zero_check(dc, slot_prop[slot].arg);
1153 }
1154 }
1155 }
1156
1157 dc->op_flags = op_flags;
1158
1159 for (slot = 0; slot < slots; ++slot) {
1160 struct slot_prop *pslot = ordered[slot];
1161 XtensaOpcodeOps *ops = pslot->ops;
1162
1163 ops->translate(dc, pslot->arg, ops->par);
1164 }
1165
1166 for (i = 0; i < n_arg_copy; ++i) {
1167 if (arg_copy[i].arg->num_bits <= 32) {
1168 tcg_temp_free_i32(arg_copy[i].temp);
1169 } else if (arg_copy[i].arg->num_bits <= 64) {
1170 tcg_temp_free_i64(arg_copy[i].temp);
1171 } else {
1172 g_assert_not_reached();
1173 }
1174 }
1175
1176 if (dc->base.is_jmp == DISAS_NEXT) {
1177 gen_postprocess(dc, 0);
1178 dc->op_flags = 0;
1179 if (op_flags & XTENSA_OP_EXIT_TB_M1) {
1180 /* Change in mmu index, memory mapping or tb->flags; exit tb */
1181 gen_jumpi_check_loop_end(dc, -1);
1182 } else if (op_flags & XTENSA_OP_EXIT_TB_0) {
1183 gen_jumpi_check_loop_end(dc, 0);
1184 } else {
1185 gen_check_loop_end(dc, 0);
1186 }
1187 }
1188 dc->pc = dc->base.pc_next;
1189 }
1190
1191 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
1192 {
1193 uint8_t b0 = cpu_ldub_code(env, dc->pc);
1194 return xtensa_op0_insn_len(dc, b0);
1195 }
1196
1197 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
1198 {
1199 unsigned i;
1200
1201 for (i = 0; i < dc->config->nibreak; ++i) {
1202 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
1203 env->sregs[IBREAKA + i] == dc->pc) {
1204 gen_debug_exception(dc, DEBUGCAUSE_IB);
1205 break;
1206 }
1207 }
1208 }
1209
1210 static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
1211 CPUState *cpu)
1212 {
1213 DisasContext *dc = container_of(dcbase, DisasContext, base);
1214 CPUXtensaState *env = cpu->env_ptr;
1215 uint32_t tb_flags = dc->base.tb->flags;
1216
1217 dc->config = env->config;
1218 dc->pc = dc->base.pc_first;
1219 dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK;
1220 dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring;
1221 dc->lbeg_off = (dc->base.tb->cs_base & XTENSA_CSBASE_LBEG_OFF_MASK) >>
1222 XTENSA_CSBASE_LBEG_OFF_SHIFT;
1223 dc->lend = (dc->base.tb->cs_base & XTENSA_CSBASE_LEND_MASK) +
1224 (dc->base.pc_first & TARGET_PAGE_MASK);
1225 dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG;
1226 dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT;
1227 dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
1228 XTENSA_TBFLAG_CPENABLE_SHIFT;
1229 dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
1230 XTENSA_TBFLAG_WINDOW_SHIFT);
1231 dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE;
1232 dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >>
1233 XTENSA_TBFLAG_CALLINC_SHIFT);
1234 init_sar_tracker(dc);
1235 }
1236
1237 static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
1238 {
1239 DisasContext *dc = container_of(dcbase, DisasContext, base);
1240
1241 if (dc->icount) {
1242 dc->next_icount = tcg_temp_local_new_i32();
1243 }
1244 }
1245
1246 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
1247 {
1248 tcg_gen_insn_start(dcbase->pc_next);
1249 }
1250
1251 static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
1252 const CPUBreakpoint *bp)
1253 {
1254 DisasContext *dc = container_of(dcbase, DisasContext, base);
1255
1256 tcg_gen_movi_i32(cpu_pc, dc->base.pc_next);
1257 gen_exception(dc, EXCP_DEBUG);
1258 dc->base.is_jmp = DISAS_NORETURN;
1259 /* The address covered by the breakpoint must be included in
1260 [tb->pc, tb->pc + tb->size) in order to for it to be
1261 properly cleared -- thus we increment the PC here so that
1262 the logic setting tb->size below does the right thing. */
1263 dc->base.pc_next += 2;
1264 return true;
1265 }
1266
1267 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
1268 {
1269 DisasContext *dc = container_of(dcbase, DisasContext, base);
1270 CPUXtensaState *env = cpu->env_ptr;
1271 target_ulong page_start;
1272
1273 /* These two conditions only apply to the first insn in the TB,
1274 but this is the first TranslateOps hook that allows exiting. */
1275 if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT)
1276 && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) {
1277 gen_exception(dc, EXCP_YIELD);
1278 dc->base.pc_next = dc->pc + 1;
1279 dc->base.is_jmp = DISAS_NORETURN;
1280 return;
1281 }
1282
1283 if (dc->icount) {
1284 TCGLabel *label = gen_new_label();
1285
1286 tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1);
1287 tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label);
1288 tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]);
1289 if (dc->debug) {
1290 gen_debug_exception(dc, DEBUGCAUSE_IC);
1291 }
1292 gen_set_label(label);
1293 }
1294
1295 if (dc->debug) {
1296 gen_ibreak_check(env, dc);
1297 }
1298
1299 disas_xtensa_insn(env, dc);
1300
1301 if (dc->icount) {
1302 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
1303 }
1304
1305 /* End the TB if the next insn will cross into the next page. */
1306 page_start = dc->base.pc_first & TARGET_PAGE_MASK;
1307 if (dc->base.is_jmp == DISAS_NEXT &&
1308 (dc->pc - page_start >= TARGET_PAGE_SIZE ||
1309 dc->pc - page_start + xtensa_insn_len(env, dc) > TARGET_PAGE_SIZE)) {
1310 dc->base.is_jmp = DISAS_TOO_MANY;
1311 }
1312 }
1313
1314 static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
1315 {
1316 DisasContext *dc = container_of(dcbase, DisasContext, base);
1317
1318 reset_sar_tracker(dc);
1319 if (dc->icount) {
1320 tcg_temp_free(dc->next_icount);
1321 }
1322
1323 switch (dc->base.is_jmp) {
1324 case DISAS_NORETURN:
1325 break;
1326 case DISAS_TOO_MANY:
1327 if (dc->base.singlestep_enabled) {
1328 tcg_gen_movi_i32(cpu_pc, dc->pc);
1329 gen_exception(dc, EXCP_DEBUG);
1330 } else {
1331 gen_jumpi(dc, dc->pc, 0);
1332 }
1333 break;
1334 default:
1335 g_assert_not_reached();
1336 }
1337 }
1338
1339 static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
1340 {
1341 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
1342 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
1343 }
1344
1345 static const TranslatorOps xtensa_translator_ops = {
1346 .init_disas_context = xtensa_tr_init_disas_context,
1347 .tb_start = xtensa_tr_tb_start,
1348 .insn_start = xtensa_tr_insn_start,
1349 .breakpoint_check = xtensa_tr_breakpoint_check,
1350 .translate_insn = xtensa_tr_translate_insn,
1351 .tb_stop = xtensa_tr_tb_stop,
1352 .disas_log = xtensa_tr_disas_log,
1353 };
1354
1355 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
1356 {
1357 DisasContext dc = {};
1358 translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb, max_insns);
1359 }
1360
1361 void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1362 {
1363 XtensaCPU *cpu = XTENSA_CPU(cs);
1364 CPUXtensaState *env = &cpu->env;
1365 xtensa_isa isa = env->config->isa;
1366 int i, j;
1367
1368 qemu_fprintf(f, "PC=%08x\n\n", env->pc);
1369
1370 for (i = j = 0; i < xtensa_isa_num_sysregs(isa); ++i) {
1371 const uint32_t *reg =
1372 xtensa_sysreg_is_user(isa, i) ? env->uregs : env->sregs;
1373 int regno = xtensa_sysreg_number(isa, i);
1374
1375 if (regno >= 0) {
1376 qemu_fprintf(f, "%12s=%08x%c",
1377 xtensa_sysreg_name(isa, i),
1378 reg[regno],
1379 (j++ % 4) == 3 ? '\n' : ' ');
1380 }
1381 }
1382
1383 qemu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
1384
1385 for (i = 0; i < 16; ++i) {
1386 qemu_fprintf(f, " A%02d=%08x%c",
1387 i, env->regs[i], (i % 4) == 3 ? '\n' : ' ');
1388 }
1389
1390 xtensa_sync_phys_from_window(env);
1391 qemu_fprintf(f, "\n");
1392
1393 for (i = 0; i < env->config->nareg; ++i) {
1394 qemu_fprintf(f, "AR%02d=%08x ", i, env->phys_regs[i]);
1395 if (i % 4 == 3) {
1396 bool ws = (env->sregs[WINDOW_START] & (1 << (i / 4))) != 0;
1397 bool cw = env->sregs[WINDOW_BASE] == i / 4;
1398
1399 qemu_fprintf(f, "%c%c\n", ws ? '<' : ' ', cw ? '=' : ' ');
1400 }
1401 }
1402
1403 if ((flags & CPU_DUMP_FPU) &&
1404 xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) {
1405 qemu_fprintf(f, "\n");
1406
1407 for (i = 0; i < 16; ++i) {
1408 qemu_fprintf(f, "F%02d=%08x (%-+15.8e)%c", i,
1409 float32_val(env->fregs[i].f32[FP_F32_LOW]),
1410 *(float *)(env->fregs[i].f32 + FP_F32_LOW),
1411 (i % 2) == 1 ? '\n' : ' ');
1412 }
1413 }
1414
1415 if ((flags & CPU_DUMP_FPU) &&
1416 xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR) &&
1417 !xtensa_option_enabled(env->config, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
1418 qemu_fprintf(f, "\n");
1419
1420 for (i = 0; i < 16; ++i) {
1421 qemu_fprintf(f, "F%02d=%016"PRIx64" (%-+24.16le)%c", i,
1422 float64_val(env->fregs[i].f64),
1423 *(double *)(&env->fregs[i].f64),
1424 (i % 2) == 1 ? '\n' : ' ');
1425 }
1426 }
1427 }
1428
1429 void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb,
1430 target_ulong *data)
1431 {
1432 env->pc = data[0];
1433 }
1434
1435 static void translate_abs(DisasContext *dc, const OpcodeArg arg[],
1436 const uint32_t par[])
1437 {
1438 tcg_gen_abs_i32(arg[0].out, arg[1].in);
1439 }
1440
1441 static void translate_add(DisasContext *dc, const OpcodeArg arg[],
1442 const uint32_t par[])
1443 {
1444 tcg_gen_add_i32(arg[0].out, arg[1].in, arg[2].in);
1445 }
1446
1447 static void translate_addi(DisasContext *dc, const OpcodeArg arg[],
1448 const uint32_t par[])
1449 {
1450 tcg_gen_addi_i32(arg[0].out, arg[1].in, arg[2].imm);
1451 }
1452
1453 static void translate_addx(DisasContext *dc, const OpcodeArg arg[],
1454 const uint32_t par[])
1455 {
1456 TCGv_i32 tmp = tcg_temp_new_i32();
1457 tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
1458 tcg_gen_add_i32(arg[0].out, tmp, arg[2].in);
1459 tcg_temp_free(tmp);
1460 }
1461
1462 static void translate_all(DisasContext *dc, const OpcodeArg arg[],
1463 const uint32_t par[])
1464 {
1465 uint32_t shift = par[1];
1466 TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1].imm);
1467 TCGv_i32 tmp = tcg_temp_new_i32();
1468
1469 tcg_gen_and_i32(tmp, arg[1].in, mask);
1470 if (par[0]) {
1471 tcg_gen_addi_i32(tmp, tmp, 1 << arg[1].imm);
1472 } else {
1473 tcg_gen_add_i32(tmp, tmp, mask);
1474 }
1475 tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift);
1476 tcg_gen_deposit_i32(arg[0].out, arg[0].out,
1477 tmp, arg[0].imm, 1);
1478 tcg_temp_free(mask);
1479 tcg_temp_free(tmp);
1480 }
1481
1482 static void translate_and(DisasContext *dc, const OpcodeArg arg[],
1483 const uint32_t par[])
1484 {
1485 tcg_gen_and_i32(arg[0].out, arg[1].in, arg[2].in);
1486 }
1487
1488 static void translate_ball(DisasContext *dc, const OpcodeArg arg[],
1489 const uint32_t par[])
1490 {
1491 TCGv_i32 tmp = tcg_temp_new_i32();
1492 tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
1493 gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm);
1494 tcg_temp_free(tmp);
1495 }
1496
1497 static void translate_bany(DisasContext *dc, const OpcodeArg arg[],
1498 const uint32_t par[])
1499 {
1500 TCGv_i32 tmp = tcg_temp_new_i32();
1501 tcg_gen_and_i32(tmp, arg[0].in, arg[1].in);
1502 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
1503 tcg_temp_free(tmp);
1504 }
1505
1506 static void translate_b(DisasContext *dc, const OpcodeArg arg[],
1507 const uint32_t par[])
1508 {
1509 gen_brcond(dc, par[0], arg[0].in, arg[1].in, arg[2].imm);
1510 }
1511
1512 static void translate_bb(DisasContext *dc, const OpcodeArg arg[],
1513 const uint32_t par[])
1514 {
1515 #ifdef TARGET_WORDS_BIGENDIAN
1516 TCGv_i32 bit = tcg_const_i32(0x80000000u);
1517 #else
1518 TCGv_i32 bit = tcg_const_i32(0x00000001u);
1519 #endif
1520 TCGv_i32 tmp = tcg_temp_new_i32();
1521 tcg_gen_andi_i32(tmp, arg[1].in, 0x1f);
1522 #ifdef TARGET_WORDS_BIGENDIAN
1523 tcg_gen_shr_i32(bit, bit, tmp);
1524 #else
1525 tcg_gen_shl_i32(bit, bit, tmp);
1526 #endif
1527 tcg_gen_and_i32(tmp, arg[0].in, bit);
1528 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
1529 tcg_temp_free(tmp);
1530 tcg_temp_free(bit);
1531 }
1532
1533 static void translate_bbi(DisasContext *dc, const OpcodeArg arg[],
1534 const uint32_t par[])
1535 {
1536 TCGv_i32 tmp = tcg_temp_new_i32();
1537 #ifdef TARGET_WORDS_BIGENDIAN
1538 tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm);
1539 #else
1540 tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm);
1541 #endif
1542 gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
1543 tcg_temp_free(tmp);
1544 }
1545
1546 static void translate_bi(DisasContext *dc, const OpcodeArg arg[],
1547 const uint32_t par[])
1548 {
1549 gen_brcondi(dc, par[0], arg[0].in, arg[1].imm, arg[2].imm);
1550 }
1551
1552 static void translate_bz(DisasContext *dc, const OpcodeArg arg[],
1553 const uint32_t par[])
1554 {
1555 gen_brcondi(dc, par[0], arg[0].in, 0, arg[1].imm);
1556 }
1557
1558 enum {
1559 BOOLEAN_AND,
1560 BOOLEAN_ANDC,
1561 BOOLEAN_OR,
1562 BOOLEAN_ORC,
1563 BOOLEAN_XOR,
1564 };
1565
1566 static void translate_boolean(DisasContext *dc, const OpcodeArg arg[],
1567 const uint32_t par[])
1568 {
1569 static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = {
1570 [BOOLEAN_AND] = tcg_gen_and_i32,
1571 [BOOLEAN_ANDC] = tcg_gen_andc_i32,
1572 [BOOLEAN_OR] = tcg_gen_or_i32,
1573 [BOOLEAN_ORC] = tcg_gen_orc_i32,
1574 [BOOLEAN_XOR] = tcg_gen_xor_i32,
1575 };
1576
1577 TCGv_i32 tmp1 = tcg_temp_new_i32();
1578 TCGv_i32 tmp2 = tcg_temp_new_i32();
1579
1580 tcg_gen_shri_i32(tmp1, arg[1].in, arg[1].imm);
1581 tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm);
1582 op[par[0]](tmp1, tmp1, tmp2);
1583 tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1);
1584 tcg_temp_free(tmp1);
1585 tcg_temp_free(tmp2);
1586 }
1587
1588 static void translate_bp(DisasContext *dc, const OpcodeArg arg[],
1589 const uint32_t par[])
1590 {
1591 TCGv_i32 tmp = tcg_temp_new_i32();
1592
1593 tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm);
1594 gen_brcondi(dc, par[0], tmp, 0, arg[1].imm);
1595 tcg_temp_free(tmp);
1596 }
1597
1598 static void translate_call0(DisasContext *dc, const OpcodeArg arg[],
1599 const uint32_t par[])
1600 {
1601 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
1602 gen_jumpi(dc, arg[0].imm, 0);
1603 }
1604
1605 static void translate_callw(DisasContext *dc, const OpcodeArg arg[],
1606 const uint32_t par[])
1607 {
1608 TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
1609 gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0));
1610 tcg_temp_free(tmp);
1611 }
1612
1613 static void translate_callx0(DisasContext *dc, const OpcodeArg arg[],
1614 const uint32_t par[])
1615 {
1616 TCGv_i32 tmp = tcg_temp_new_i32();
1617 tcg_gen_mov_i32(tmp, arg[0].in);
1618 tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next);
1619 gen_jump(dc, tmp);
1620 tcg_temp_free(tmp);
1621 }
1622
1623 static void translate_callxw(DisasContext *dc, const OpcodeArg arg[],
1624 const uint32_t par[])
1625 {
1626 TCGv_i32 tmp = tcg_temp_new_i32();
1627
1628 tcg_gen_mov_i32(tmp, arg[0].in);
1629 gen_callw_slot(dc, par[0], tmp, -1);
1630 tcg_temp_free(tmp);
1631 }
1632
1633 static void translate_clamps(DisasContext *dc, const OpcodeArg arg[],
1634 const uint32_t par[])
1635 {
1636 TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2].imm);
1637 TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2].imm) - 1);
1638
1639 tcg_gen_smax_i32(tmp1, tmp1, arg[1].in);
1640 tcg_gen_smin_i32(arg[0].out, tmp1, tmp2);
1641 tcg_temp_free(tmp1);
1642 tcg_temp_free(tmp2);
1643 }
1644
1645 static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[],
1646 const uint32_t par[])
1647 {
1648 /* TODO: GPIO32 may be a part of coprocessor */
1649 tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].imm));
1650 }
1651
1652 static void translate_clrex(DisasContext *dc, const OpcodeArg arg[],
1653 const uint32_t par[])
1654 {
1655 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
1656 }
1657
1658 static void translate_const16(DisasContext *dc, const OpcodeArg arg[],
1659 const uint32_t par[])
1660 {
1661 TCGv_i32 c = tcg_const_i32(arg[1].imm);
1662
1663 tcg_gen_deposit_i32(arg[0].out, c, arg[0].in, 16, 16);
1664 tcg_temp_free(c);
1665 }
1666
1667 static void translate_dcache(DisasContext *dc, const OpcodeArg arg[],
1668 const uint32_t par[])
1669 {
1670 TCGv_i32 addr = tcg_temp_new_i32();
1671 TCGv_i32 res = tcg_temp_new_i32();
1672
1673 tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
1674 tcg_gen_qemu_ld8u(res, addr, dc->cring);
1675 tcg_temp_free(addr);
1676 tcg_temp_free(res);
1677 }
1678
1679 static void translate_depbits(DisasContext *dc, const OpcodeArg arg[],
1680 const uint32_t par[])
1681 {
1682 tcg_gen_deposit_i32(arg[1].out, arg[1].in, arg[0].in,
1683 arg[2].imm, arg[3].imm);
1684 }
1685
1686 static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[],
1687 const uint32_t par[])
1688 {
1689 tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes);
1690 }
1691
1692 static uint32_t test_exceptions_entry(DisasContext *dc, const OpcodeArg arg[],
1693 const uint32_t par[])
1694 {
1695 if (arg[0].imm > 3 || !dc->cwoe) {
1696 qemu_log_mask(LOG_GUEST_ERROR,
1697 "Illegal entry instruction(pc = %08x)\n", dc->pc);
1698 return XTENSA_OP_ILL;
1699 } else {
1700 return 0;
1701 }
1702 }
1703
1704 static uint32_t test_overflow_entry(DisasContext *dc, const OpcodeArg arg[],
1705 const uint32_t par[])
1706 {
1707 return 1 << (dc->callinc * 4);
1708 }
1709
1710 static void translate_entry(DisasContext *dc, const OpcodeArg arg[],
1711 const uint32_t par[])
1712 {
1713 TCGv_i32 pc = tcg_const_i32(dc->pc);
1714 TCGv_i32 s = tcg_const_i32(arg[0].imm);
1715 TCGv_i32 imm = tcg_const_i32(arg[1].imm);
1716 gen_helper_entry(cpu_env, pc, s, imm);
1717 tcg_temp_free(imm);
1718 tcg_temp_free(s);
1719 tcg_temp_free(pc);
1720 }
1721
1722 static void translate_extui(DisasContext *dc, const OpcodeArg arg[],
1723 const uint32_t par[])
1724 {
1725 int maskimm = (1 << arg[3].imm) - 1;
1726
1727 TCGv_i32 tmp = tcg_temp_new_i32();
1728 tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm);
1729 tcg_gen_andi_i32(arg[0].out, tmp, maskimm);
1730 tcg_temp_free(tmp);
1731 }
1732
1733 static void translate_getex(DisasContext *dc, const OpcodeArg arg[],
1734 const uint32_t par[])
1735 {
1736 TCGv_i32 tmp = tcg_temp_new_i32();
1737
1738 tcg_gen_extract_i32(tmp, cpu_SR[ATOMCTL], 8, 1);
1739 tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], arg[0].in, 8, 1);
1740 tcg_gen_mov_i32(arg[0].out, tmp);
1741 tcg_temp_free(tmp);
1742 }
1743
1744 static void translate_icache(DisasContext *dc, const OpcodeArg arg[],
1745 const uint32_t par[])
1746 {
1747 #ifndef CONFIG_USER_ONLY
1748 TCGv_i32 addr = tcg_temp_new_i32();
1749
1750 tcg_gen_movi_i32(cpu_pc, dc->pc);
1751 tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
1752 gen_helper_itlb_hit_test(cpu_env, addr);
1753 tcg_temp_free(addr);
1754 #endif
1755 }
1756
1757 static void translate_itlb(DisasContext *dc, const OpcodeArg arg[],
1758 const uint32_t par[])
1759 {
1760 #ifndef CONFIG_USER_ONLY
1761 TCGv_i32 dtlb = tcg_const_i32(par[0]);
1762
1763 gen_helper_itlb(cpu_env, arg[0].in, dtlb);
1764 tcg_temp_free(dtlb);
1765 #endif
1766 }
1767
1768 static void translate_j(DisasContext *dc, const OpcodeArg arg[],
1769 const uint32_t par[])
1770 {
1771 gen_jumpi(dc, arg[0].imm, 0);
1772 }
1773
1774 static void translate_jx(DisasContext *dc, const OpcodeArg arg[],
1775 const uint32_t par[])
1776 {
1777 gen_jump(dc, arg[0].in);
1778 }
1779
1780 static void translate_l32e(DisasContext *dc, const OpcodeArg arg[],
1781 const uint32_t par[])
1782 {
1783 TCGv_i32 addr = tcg_temp_new_i32();
1784
1785 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
1786 gen_load_store_alignment(dc, 2, addr, false);
1787 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, MO_TEUL);
1788 tcg_temp_free(addr);
1789 }
1790
1791 #ifdef CONFIG_USER_ONLY
1792 static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
1793 {
1794 }
1795 #else
1796 static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write)
1797 {
1798 if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
1799 TCGv_i32 tpc = tcg_const_i32(dc->pc);
1800 TCGv_i32 write = tcg_const_i32(is_write);
1801
1802 gen_helper_check_exclusive(cpu_env, tpc, addr, write);
1803 tcg_temp_free(tpc);
1804 tcg_temp_free(write);
1805 }
1806 }
1807 #endif
1808
1809 static void translate_l32ex(DisasContext *dc, const OpcodeArg arg[],
1810 const uint32_t par[])
1811 {
1812 TCGv_i32 addr = tcg_temp_new_i32();
1813
1814 tcg_gen_mov_i32(addr, arg[1].in);
1815 gen_load_store_alignment(dc, 2, addr, true);
1816 gen_check_exclusive(dc, addr, false);
1817 tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->cring, MO_TEUL);
1818 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
1819 tcg_gen_mov_i32(cpu_exclusive_val, arg[0].out);
1820 tcg_temp_free(addr);
1821 }
1822
1823 static void translate_ldst(DisasContext *dc, const OpcodeArg arg[],
1824 const uint32_t par[])
1825 {
1826 TCGv_i32 addr = tcg_temp_new_i32();
1827
1828 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
1829 if (par[0] & MO_SIZE) {
1830 gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]);
1831 }
1832 if (par[2]) {
1833 if (par[1]) {
1834 tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL);
1835 }
1836 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, par[0]);
1837 } else {
1838 tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, par[0]);
1839 if (par[1]) {
1840 tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL);
1841 }
1842 }
1843 tcg_temp_free(addr);
1844 }
1845
1846 static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],
1847 const uint32_t par[])
1848 {
1849 TCGv_i32 tmp;
1850
1851 if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) {
1852 tmp = tcg_const_i32(arg[1].raw_imm - 1);
1853 tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp);
1854 } else {
1855 tmp = tcg_const_i32(arg[1].imm);
1856 }
1857 tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring);
1858 tcg_temp_free(tmp);
1859 }
1860
1861 static void translate_loop(DisasContext *dc, const OpcodeArg arg[],
1862 const uint32_t par[])
1863 {
1864 uint32_t lend = arg[1].imm;
1865
1866 tcg_gen_subi_i32(cpu_SR[LCOUNT], arg[0].in, 1);
1867 tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next);
1868 tcg_gen_movi_i32(cpu_SR[LEND], lend);
1869
1870 if (par[0] != TCG_COND_NEVER) {
1871 TCGLabel *label = gen_new_label();
1872 tcg_gen_brcondi_i32(par[0], arg[0].in, 0, label);
1873 gen_jumpi(dc, lend, 1);
1874 gen_set_label(label);
1875 }
1876
1877 gen_jumpi(dc, dc->base.pc_next, 0);
1878 }
1879
1880 enum {
1881 MAC16_UMUL,
1882 MAC16_MUL,
1883 MAC16_MULA,
1884 MAC16_MULS,
1885 MAC16_NONE,
1886 };
1887
1888 enum {
1889 MAC16_LL,
1890 MAC16_HL,
1891 MAC16_LH,
1892 MAC16_HH,
1893
1894 MAC16_HX = 0x1,
1895 MAC16_XH = 0x2,
1896 };
1897
1898 static void translate_mac16(DisasContext *dc, const OpcodeArg arg[],
1899 const uint32_t par[])
1900 {
1901 int op = par[0];
1902 unsigned half = par[1];
1903 uint32_t ld_offset = par[2];
1904 unsigned off = ld_offset ? 2 : 0;
1905 TCGv_i32 vaddr = tcg_temp_new_i32();
1906 TCGv_i32 mem32 = tcg_temp_new_i32();
1907
1908 if (ld_offset) {
1909 tcg_gen_addi_i32(vaddr, arg[1].in, ld_offset);
1910 gen_load_store_alignment(dc, 2, vaddr, false);
1911 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
1912 }
1913 if (op != MAC16_NONE) {
1914 TCGv_i32 m1 = gen_mac16_m(arg[off].in,
1915 half & MAC16_HX, op == MAC16_UMUL);
1916 TCGv_i32 m2 = gen_mac16_m(arg[off + 1].in,
1917 half & MAC16_XH, op == MAC16_UMUL);
1918
1919 if (op == MAC16_MUL || op == MAC16_UMUL) {
1920 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
1921 if (op == MAC16_UMUL) {
1922 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
1923 } else {
1924 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
1925 }
1926 } else {
1927 TCGv_i32 lo = tcg_temp_new_i32();
1928 TCGv_i32 hi = tcg_temp_new_i32();
1929
1930 tcg_gen_mul_i32(lo, m1, m2);
1931 tcg_gen_sari_i32(hi, lo, 31);
1932 if (op == MAC16_MULA) {
1933 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
1934 cpu_SR[ACCLO], cpu_SR[ACCHI],
1935 lo, hi);
1936 } else {
1937 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
1938 cpu_SR[ACCLO], cpu_SR[ACCHI],
1939 lo, hi);
1940 }
1941 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
1942
1943 tcg_temp_free_i32(lo);
1944 tcg_temp_free_i32(hi);
1945 }
1946 tcg_temp_free(m1);
1947 tcg_temp_free(m2);
1948 }
1949 if (ld_offset) {
1950 tcg_gen_mov_i32(arg[1].out, vaddr);
1951 tcg_gen_mov_i32(cpu_SR[MR + arg[0].imm], mem32);
1952 }
1953 tcg_temp_free(vaddr);
1954 tcg_temp_free(mem32);
1955 }
1956
1957 static void translate_memw(DisasContext *dc, const OpcodeArg arg[],
1958 const uint32_t par[])
1959 {
1960 tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
1961 }
1962
1963 static void translate_smin(DisasContext *dc, const OpcodeArg arg[],
1964 const uint32_t par[])
1965 {
1966 tcg_gen_smin_i32(arg[0].out, arg[1].in, arg[2].in);
1967 }
1968
1969 static void translate_umin(DisasContext *dc, const OpcodeArg arg[],
1970 const uint32_t par[])
1971 {
1972 tcg_gen_umin_i32(arg[0].out, arg[1].in, arg[2].in);
1973 }
1974
1975 static void translate_smax(DisasContext *dc, const OpcodeArg arg[],
1976 const uint32_t par[])
1977 {
1978 tcg_gen_smax_i32(arg[0].out, arg[1].in, arg[2].in);
1979 }
1980
1981 static void translate_umax(DisasContext *dc, const OpcodeArg arg[],
1982 const uint32_t par[])
1983 {
1984 tcg_gen_umax_i32(arg[0].out, arg[1].in, arg[2].in);
1985 }
1986
1987 static void translate_mov(DisasContext *dc, const OpcodeArg arg[],
1988 const uint32_t par[])
1989 {
1990 tcg_gen_mov_i32(arg[0].out, arg[1].in);
1991 }
1992
1993 static void translate_movcond(DisasContext *dc, const OpcodeArg arg[],
1994 const uint32_t par[])
1995 {
1996 TCGv_i32 zero = tcg_const_i32(0);
1997
1998 tcg_gen_movcond_i32(par[0], arg[0].out,
1999 arg[2].in, zero, arg[1].in, arg[0].in);
2000 tcg_temp_free(zero);
2001 }
2002
2003 static void translate_movi(DisasContext *dc, const OpcodeArg arg[],
2004 const uint32_t par[])
2005 {
2006 tcg_gen_movi_i32(arg[0].out, arg[1].imm);
2007 }
2008
2009 static void translate_movp(DisasContext *dc, const OpcodeArg arg[],
2010 const uint32_t par[])
2011 {
2012 TCGv_i32 zero = tcg_const_i32(0);
2013 TCGv_i32 tmp = tcg_temp_new_i32();
2014
2015 tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
2016 tcg_gen_movcond_i32(par[0],
2017 arg[0].out, tmp, zero,
2018 arg[1].in, arg[0].in);
2019 tcg_temp_free(tmp);
2020 tcg_temp_free(zero);
2021 }
2022
2023 static void translate_movsp(DisasContext *dc, const OpcodeArg arg[],
2024 const uint32_t par[])
2025 {
2026 tcg_gen_mov_i32(arg[0].out, arg[1].in);
2027 }
2028
2029 static void translate_mul16(DisasContext *dc, const OpcodeArg arg[],
2030 const uint32_t par[])
2031 {
2032 TCGv_i32 v1 = tcg_temp_new_i32();
2033 TCGv_i32 v2 = tcg_temp_new_i32();
2034
2035 if (par[0]) {
2036 tcg_gen_ext16s_i32(v1, arg[1].in);
2037 tcg_gen_ext16s_i32(v2, arg[2].in);
2038 } else {
2039 tcg_gen_ext16u_i32(v1, arg[1].in);
2040 tcg_gen_ext16u_i32(v2, arg[2].in);
2041 }
2042 tcg_gen_mul_i32(arg[0].out, v1, v2);
2043 tcg_temp_free(v2);
2044 tcg_temp_free(v1);
2045 }
2046
2047 static void translate_mull(DisasContext *dc, const OpcodeArg arg[],
2048 const uint32_t par[])
2049 {
2050 tcg_gen_mul_i32(arg[0].out, arg[1].in, arg[2].in);
2051 }
2052
2053 static void translate_mulh(DisasContext *dc, const OpcodeArg arg[],
2054 const uint32_t par[])
2055 {
2056 TCGv_i32 lo = tcg_temp_new();
2057
2058 if (par[0]) {
2059 tcg_gen_muls2_i32(lo, arg[0].out, arg[1].in, arg[2].in);
2060 } else {
2061 tcg_gen_mulu2_i32(lo, arg[0].out, arg[1].in, arg[2].in);
2062 }
2063 tcg_temp_free(lo);
2064 }
2065
2066 static void translate_neg(DisasContext *dc, const OpcodeArg arg[],
2067 const uint32_t par[])
2068 {
2069 tcg_gen_neg_i32(arg[0].out, arg[1].in);
2070 }
2071
2072 static void translate_nop(DisasContext *dc, const OpcodeArg arg[],
2073 const uint32_t par[])
2074 {
2075 }
2076
2077 static void translate_nsa(DisasContext *dc, const OpcodeArg arg[],
2078 const uint32_t par[])
2079 {
2080 tcg_gen_clrsb_i32(arg[0].out, arg[1].in);
2081 }
2082
2083 static void translate_nsau(DisasContext *dc, const OpcodeArg arg[],
2084 const uint32_t par[])
2085 {
2086 tcg_gen_clzi_i32(arg[0].out, arg[1].in, 32);
2087 }
2088
2089 static void translate_or(DisasContext *dc, const OpcodeArg arg[],
2090 const uint32_t par[])
2091 {
2092 tcg_gen_or_i32(arg[0].out, arg[1].in, arg[2].in);
2093 }
2094
2095 static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[],
2096 const uint32_t par[])
2097 {
2098 #ifndef CONFIG_USER_ONLY
2099 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2100
2101 tcg_gen_movi_i32(cpu_pc, dc->pc);
2102 gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb);
2103 tcg_temp_free(dtlb);
2104 #endif
2105 }
2106
2107 static void translate_pptlb(DisasContext *dc, const OpcodeArg arg[],
2108 const uint32_t par[])
2109 {
2110 #ifndef CONFIG_USER_ONLY
2111 tcg_gen_movi_i32(cpu_pc, dc->pc);
2112 gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in);
2113 #endif
2114 }
2115
2116 static void translate_quos(DisasContext *dc, const OpcodeArg arg[],
2117 const uint32_t par[])
2118 {
2119 TCGLabel *label1 = gen_new_label();
2120 TCGLabel *label2 = gen_new_label();
2121
2122 tcg_gen_brcondi_i32(TCG_COND_NE, arg[1].in, 0x80000000,
2123 label1);
2124 tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0xffffffff,
2125 label1);
2126 tcg_gen_movi_i32(arg[0].out,
2127 par[0] ? 0x80000000 : 0);
2128 tcg_gen_br(label2);
2129 gen_set_label(label1);
2130 if (par[0]) {
2131 tcg_gen_div_i32(arg[0].out,
2132 arg[1].in, arg[2].in);
2133 } else {
2134 tcg_gen_rem_i32(arg[0].out,
2135 arg[1].in, arg[2].in);
2136 }
2137 gen_set_label(label2);
2138 }
2139
2140 static void translate_quou(DisasContext *dc, const OpcodeArg arg[],
2141 const uint32_t par[])
2142 {
2143 tcg_gen_divu_i32(arg[0].out,
2144 arg[1].in, arg[2].in);
2145 }
2146
2147 static void translate_read_impwire(DisasContext *dc, const OpcodeArg arg[],
2148 const uint32_t par[])
2149 {
2150 /* TODO: GPIO32 may be a part of coprocessor */
2151 tcg_gen_movi_i32(arg[0].out, 0);
2152 }
2153
2154 static void translate_remu(DisasContext *dc, const OpcodeArg arg[],
2155 const uint32_t par[])
2156 {
2157 tcg_gen_remu_i32(arg[0].out,
2158 arg[1].in, arg[2].in);
2159 }
2160
2161 static void translate_rer(DisasContext *dc, const OpcodeArg arg[],
2162 const uint32_t par[])
2163 {
2164 gen_helper_rer(arg[0].out, cpu_env, arg[1].in);
2165 }
2166
2167 static void translate_ret(DisasContext *dc, const OpcodeArg arg[],
2168 const uint32_t par[])
2169 {
2170 gen_jump(dc, cpu_R[0]);
2171 }
2172
2173 static uint32_t test_exceptions_retw(DisasContext *dc, const OpcodeArg arg[],
2174 const uint32_t par[])
2175 {
2176 if (!dc->cwoe) {
2177 qemu_log_mask(LOG_GUEST_ERROR,
2178 "Illegal retw instruction(pc = %08x)\n", dc->pc);
2179 return XTENSA_OP_ILL;
2180 } else {
2181 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2182
2183 gen_helper_test_ill_retw(cpu_env, tmp);
2184 tcg_temp_free(tmp);
2185 return 0;
2186 }
2187 }
2188
2189 static void translate_retw(DisasContext *dc, const OpcodeArg arg[],
2190 const uint32_t par[])
2191 {
2192 TCGv_i32 tmp = tcg_const_i32(1);
2193 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
2194 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
2195 cpu_SR[WINDOW_START], tmp);
2196 tcg_gen_movi_i32(tmp, dc->pc);
2197 tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30);
2198 gen_helper_retw(cpu_env, cpu_R[0]);
2199 gen_jump(dc, tmp);
2200 tcg_temp_free(tmp);
2201 }
2202
2203 static void translate_rfde(DisasContext *dc, const OpcodeArg arg[],
2204 const uint32_t par[])
2205 {
2206 gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]);
2207 }
2208
2209 static void translate_rfe(DisasContext *dc, const OpcodeArg arg[],
2210 const uint32_t par[])
2211 {
2212 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
2213 gen_jump(dc, cpu_SR[EPC1]);
2214 }
2215
2216 static void translate_rfi(DisasContext *dc, const OpcodeArg arg[],
2217 const uint32_t par[])
2218 {
2219 tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0].imm - 2]);
2220 gen_jump(dc, cpu_SR[EPC1 + arg[0].imm - 1]);
2221 }
2222
2223 static void translate_rfw(DisasContext *dc, const OpcodeArg arg[],
2224 const uint32_t par[])
2225 {
2226 TCGv_i32 tmp = tcg_const_i32(1);
2227
2228 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
2229 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
2230
2231 if (par[0]) {
2232 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
2233 cpu_SR[WINDOW_START], tmp);
2234 } else {
2235 tcg_gen_or_i32(cpu_SR[WINDOW_START],
2236 cpu_SR[WINDOW_START], tmp);
2237 }
2238
2239 tcg_temp_free(tmp);
2240 gen_helper_restore_owb(cpu_env);
2241 gen_jump(dc, cpu_SR[EPC1]);
2242 }
2243
2244 static void translate_rotw(DisasContext *dc, const OpcodeArg arg[],
2245 const uint32_t par[])
2246 {
2247 tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0].imm);
2248 }
2249
2250 static void translate_rsil(DisasContext *dc, const OpcodeArg arg[],
2251 const uint32_t par[])
2252 {
2253 tcg_gen_mov_i32(arg[0].out, cpu_SR[PS]);
2254 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
2255 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm);
2256 }
2257
2258 static void translate_rsr(DisasContext *dc, const OpcodeArg arg[],
2259 const uint32_t par[])
2260 {
2261 if (sr_name[par[0]]) {
2262 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2263 } else {
2264 tcg_gen_movi_i32(arg[0].out, 0);
2265 }
2266 }
2267
2268 static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
2269 const uint32_t par[])
2270 {
2271 #ifndef CONFIG_USER_ONLY
2272 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2273 gen_io_start();
2274 }
2275 gen_helper_update_ccount(cpu_env);
2276 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2277 #endif
2278 }
2279
2280 static void translate_rsr_ptevaddr(DisasContext *dc, const OpcodeArg arg[],
2281 const uint32_t par[])
2282 {
2283 #ifndef CONFIG_USER_ONLY
2284 TCGv_i32 tmp = tcg_temp_new_i32();
2285
2286 tcg_gen_shri_i32(tmp, cpu_SR[EXCVADDR], 10);
2287 tcg_gen_or_i32(tmp, tmp, cpu_SR[PTEVADDR]);
2288 tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc);
2289 tcg_temp_free(tmp);
2290 #endif
2291 }
2292
2293 static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[],
2294 const uint32_t par[])
2295 {
2296 #ifndef CONFIG_USER_ONLY
2297 static void (* const helper[])(TCGv_i32 r, TCGv_env env, TCGv_i32 a1,
2298 TCGv_i32 a2) = {
2299 gen_helper_rtlb0,
2300 gen_helper_rtlb1,
2301 };
2302 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2303
2304 helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb);
2305 tcg_temp_free(dtlb);
2306 #endif
2307 }
2308
2309 static void translate_rptlb0(DisasContext *dc, const OpcodeArg arg[],
2310 const uint32_t par[])
2311 {
2312 #ifndef CONFIG_USER_ONLY
2313 gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in);
2314 #endif
2315 }
2316
2317 static void translate_rptlb1(DisasContext *dc, const OpcodeArg arg[],
2318 const uint32_t par[])
2319 {
2320 #ifndef CONFIG_USER_ONLY
2321 gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in);
2322 #endif
2323 }
2324
2325 static void translate_rur(DisasContext *dc, const OpcodeArg arg[],
2326 const uint32_t par[])
2327 {
2328 tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]);
2329 }
2330
2331 static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[],
2332 const uint32_t par[])
2333 {
2334 /* TODO: GPIO32 may be a part of coprocessor */
2335 tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0].imm);
2336 }
2337
2338 #ifdef CONFIG_USER_ONLY
2339 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
2340 {
2341 }
2342 #else
2343 static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
2344 {
2345 TCGv_i32 tpc = tcg_const_i32(dc->pc);
2346
2347 gen_helper_check_atomctl(cpu_env, tpc, addr);
2348 tcg_temp_free(tpc);
2349 }
2350 #endif
2351
2352 static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[],
2353 const uint32_t par[])
2354 {
2355 TCGv_i32 tmp = tcg_temp_local_new_i32();
2356 TCGv_i32 addr = tcg_temp_local_new_i32();
2357
2358 tcg_gen_mov_i32(tmp, arg[0].in);
2359 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
2360 gen_load_store_alignment(dc, 2, addr, true);
2361 gen_check_atomctl(dc, addr);
2362 tcg_gen_atomic_cmpxchg_i32(arg[0].out, addr, cpu_SR[SCOMPARE1],
2363 tmp, dc->cring, MO_TEUL);
2364 tcg_temp_free(addr);
2365 tcg_temp_free(tmp);
2366 }
2367
2368 static void translate_s32e(DisasContext *dc, const OpcodeArg arg[],
2369 const uint32_t par[])
2370 {
2371 TCGv_i32 addr = tcg_temp_new_i32();
2372
2373 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
2374 gen_load_store_alignment(dc, 2, addr, false);
2375 tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, MO_TEUL);
2376 tcg_temp_free(addr);
2377 }
2378
2379 static void translate_s32ex(DisasContext *dc, const OpcodeArg arg[],
2380 const uint32_t par[])
2381 {
2382 TCGv_i32 prev = tcg_temp_new_i32();
2383 TCGv_i32 addr = tcg_temp_local_new_i32();
2384 TCGv_i32 res = tcg_temp_local_new_i32();
2385 TCGLabel *label = gen_new_label();
2386
2387 tcg_gen_movi_i32(res, 0);
2388 tcg_gen_mov_i32(addr, arg[1].in);
2389 gen_load_store_alignment(dc, 2, addr, true);
2390 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, label);
2391 gen_check_exclusive(dc, addr, true);
2392 tcg_gen_atomic_cmpxchg_i32(prev, cpu_exclusive_addr, cpu_exclusive_val,
2393 arg[0].in, dc->cring, MO_TEUL);
2394 tcg_gen_setcond_i32(TCG_COND_EQ, res, prev, cpu_exclusive_val);
2395 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_exclusive_val,
2396 prev, cpu_exclusive_val, prev, cpu_exclusive_val);
2397 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
2398 gen_set_label(label);
2399 tcg_gen_extract_i32(arg[0].out, cpu_SR[ATOMCTL], 8, 1);
2400 tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], res, 8, 1);
2401 tcg_temp_free(prev);
2402 tcg_temp_free(addr);
2403 tcg_temp_free(res);
2404 }
2405
2406 static void translate_salt(DisasContext *dc, const OpcodeArg arg[],
2407 const uint32_t par[])
2408 {
2409 tcg_gen_setcond_i32(par[0],
2410 arg[0].out,
2411 arg[1].in, arg[2].in);
2412 }
2413
2414 static void translate_sext(DisasContext *dc, const OpcodeArg arg[],
2415 const uint32_t par[])
2416 {
2417 int shift = 31 - arg[2].imm;
2418
2419 if (shift == 24) {
2420 tcg_gen_ext8s_i32(arg[0].out, arg[1].in);
2421 } else if (shift == 16) {
2422 tcg_gen_ext16s_i32(arg[0].out, arg[1].in);
2423 } else {
2424 TCGv_i32 tmp = tcg_temp_new_i32();
2425 tcg_gen_shli_i32(tmp, arg[1].in, shift);
2426 tcg_gen_sari_i32(arg[0].out, tmp, shift);
2427 tcg_temp_free(tmp);
2428 }
2429 }
2430
2431 static uint32_t test_exceptions_simcall(DisasContext *dc,
2432 const OpcodeArg arg[],
2433 const uint32_t par[])
2434 {
2435 #ifdef CONFIG_USER_ONLY
2436 bool ill = true;
2437 #else
2438 /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
2439 bool ill = dc->config->hw_version <= 250002 && !semihosting_enabled();
2440 #endif
2441 if (ill || !semihosting_enabled()) {
2442 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
2443 }
2444 return ill ? XTENSA_OP_ILL : 0;
2445 }
2446
2447 static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
2448 const uint32_t par[])
2449 {
2450 #ifndef CONFIG_USER_ONLY
2451 if (semihosting_enabled()) {
2452 gen_helper_simcall(cpu_env);
2453 }
2454 #endif
2455 }
2456
2457 /*
2458 * Note: 64 bit ops are used here solely because SAR values
2459 * have range 0..63
2460 */
2461 #define gen_shift_reg(cmd, reg) do { \
2462 TCGv_i64 tmp = tcg_temp_new_i64(); \
2463 tcg_gen_extu_i32_i64(tmp, reg); \
2464 tcg_gen_##cmd##_i64(v, v, tmp); \
2465 tcg_gen_extrl_i64_i32(arg[0].out, v); \
2466 tcg_temp_free_i64(v); \
2467 tcg_temp_free_i64(tmp); \
2468 } while (0)
2469
2470 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2471
2472 static void translate_sll(DisasContext *dc, const OpcodeArg arg[],
2473 const uint32_t par[])
2474 {
2475 if (dc->sar_m32_5bit) {
2476 tcg_gen_shl_i32(arg[0].out, arg[1].in, dc->sar_m32);
2477 } else {
2478 TCGv_i64 v = tcg_temp_new_i64();
2479 TCGv_i32 s = tcg_const_i32(32);
2480 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
2481 tcg_gen_andi_i32(s, s, 0x3f);
2482 tcg_gen_extu_i32_i64(v, arg[1].in);
2483 gen_shift_reg(shl, s);
2484 tcg_temp_free(s);
2485 }
2486 }
2487
2488 static void translate_slli(DisasContext *dc, const OpcodeArg arg[],
2489 const uint32_t par[])
2490 {
2491 if (arg[2].imm == 32) {
2492 qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
2493 arg[0].imm, arg[1].imm);
2494 }
2495 tcg_gen_shli_i32(arg[0].out, arg[1].in, arg[2].imm & 0x1f);
2496 }
2497
2498 static void translate_sra(DisasContext *dc, const OpcodeArg arg[],
2499 const uint32_t par[])
2500 {
2501 if (dc->sar_m32_5bit) {
2502 tcg_gen_sar_i32(arg[0].out, arg[1].in, cpu_SR[SAR]);
2503 } else {
2504 TCGv_i64 v = tcg_temp_new_i64();
2505 tcg_gen_ext_i32_i64(v, arg[1].in);
2506 gen_shift(sar);
2507 }
2508 }
2509
2510 static void translate_srai(DisasContext *dc, const OpcodeArg arg[],
2511 const uint32_t par[])
2512 {
2513 tcg_gen_sari_i32(arg[0].out, arg[1].in, arg[2].imm);
2514 }
2515
2516 static void translate_src(DisasContext *dc, const OpcodeArg arg[],
2517 const uint32_t par[])
2518 {
2519 TCGv_i64 v = tcg_temp_new_i64();
2520 tcg_gen_concat_i32_i64(v, arg[2].in, arg[1].in);
2521 gen_shift(shr);
2522 }
2523
2524 static void translate_srl(DisasContext *dc, const OpcodeArg arg[],
2525 const uint32_t par[])
2526 {
2527 if (dc->sar_m32_5bit) {
2528 tcg_gen_shr_i32(arg[0].out, arg[1].in, cpu_SR[SAR]);
2529 } else {
2530 TCGv_i64 v = tcg_temp_new_i64();
2531 tcg_gen_extu_i32_i64(v, arg[1].in);
2532 gen_shift(shr);
2533 }
2534 }
2535
2536 #undef gen_shift
2537 #undef gen_shift_reg
2538
2539 static void translate_srli(DisasContext *dc, const OpcodeArg arg[],
2540 const uint32_t par[])
2541 {
2542 tcg_gen_shri_i32(arg[0].out, arg[1].in, arg[2].imm);
2543 }
2544
2545 static void translate_ssa8b(DisasContext *dc, const OpcodeArg arg[],
2546 const uint32_t par[])
2547 {
2548 TCGv_i32 tmp = tcg_temp_new_i32();
2549 tcg_gen_shli_i32(tmp, arg[0].in, 3);
2550 gen_left_shift_sar(dc, tmp);
2551 tcg_temp_free(tmp);
2552 }
2553
2554 static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[],
2555 const uint32_t par[])
2556 {
2557 TCGv_i32 tmp = tcg_temp_new_i32();
2558 tcg_gen_shli_i32(tmp, arg[0].in, 3);
2559 gen_right_shift_sar(dc, tmp);
2560 tcg_temp_free(tmp);
2561 }
2562
2563 static void translate_ssai(DisasContext *dc, const OpcodeArg arg[],
2564 const uint32_t par[])
2565 {
2566 TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
2567 gen_right_shift_sar(dc, tmp);
2568 tcg_temp_free(tmp);
2569 }
2570
2571 static void translate_ssl(DisasContext *dc, const OpcodeArg arg[],
2572 const uint32_t par[])
2573 {
2574 gen_left_shift_sar(dc, arg[0].in);
2575 }
2576
2577 static void translate_ssr(DisasContext *dc, const OpcodeArg arg[],
2578 const uint32_t par[])
2579 {
2580 gen_right_shift_sar(dc, arg[0].in);
2581 }
2582
2583 static void translate_sub(DisasContext *dc, const OpcodeArg arg[],
2584 const uint32_t par[])
2585 {
2586 tcg_gen_sub_i32(arg[0].out, arg[1].in, arg[2].in);
2587 }
2588
2589 static void translate_subx(DisasContext *dc, const OpcodeArg arg[],
2590 const uint32_t par[])
2591 {
2592 TCGv_i32 tmp = tcg_temp_new_i32();
2593 tcg_gen_shli_i32(tmp, arg[1].in, par[0]);
2594 tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in);
2595 tcg_temp_free(tmp);
2596 }
2597
2598 static void translate_waiti(DisasContext *dc, const OpcodeArg arg[],
2599 const uint32_t par[])
2600 {
2601 #ifndef CONFIG_USER_ONLY
2602 gen_waiti(dc, arg[0].imm);
2603 #endif
2604 }
2605
2606 static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[],
2607 const uint32_t par[])
2608 {
2609 #ifndef CONFIG_USER_ONLY
2610 TCGv_i32 dtlb = tcg_const_i32(par[0]);
2611
2612 gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb);
2613 tcg_temp_free(dtlb);
2614 #endif
2615 }
2616
2617 static void translate_wptlb(DisasContext *dc, const OpcodeArg arg[],
2618 const uint32_t par[])
2619 {
2620 #ifndef CONFIG_USER_ONLY
2621 gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in);
2622 #endif
2623 }
2624
2625 static void translate_wer(DisasContext *dc, const OpcodeArg arg[],
2626 const uint32_t par[])
2627 {
2628 gen_helper_wer(cpu_env, arg[0].in, arg[1].in);
2629 }
2630
2631 static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
2632 const uint32_t par[])
2633 {
2634 /* TODO: GPIO32 may be a part of coprocessor */
2635 tcg_gen_and_i32(cpu_UR[EXPSTATE], arg[0].in, arg[1].in);
2636 }
2637
2638 static void translate_wsr(DisasContext *dc, const OpcodeArg arg[],
2639 const uint32_t par[])
2640 {
2641 if (sr_name[par[0]]) {
2642 tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2643 }
2644 }
2645
2646 static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[],
2647 const uint32_t par[])
2648 {
2649 if (sr_name[par[0]]) {
2650 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
2651 }
2652 }
2653
2654 static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[],
2655 const uint32_t par[])
2656 {
2657 tcg_gen_ext8s_i32(cpu_SR[par[0]], arg[0].in);
2658 }
2659
2660 static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[],
2661 const uint32_t par[])
2662 {
2663 #ifndef CONFIG_USER_ONLY
2664 uint32_t id = par[0] - CCOMPARE;
2665 TCGv_i32 tmp = tcg_const_i32(id);
2666
2667 assert(id < dc->config->nccompare);
2668 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2669 gen_io_start();
2670 }
2671 tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2672 gen_helper_update_ccompare(cpu_env, tmp);
2673 tcg_temp_free(tmp);
2674 #endif
2675 }
2676
2677 static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[],
2678 const uint32_t par[])
2679 {
2680 #ifndef CONFIG_USER_ONLY
2681 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2682 gen_io_start();
2683 }
2684 gen_helper_wsr_ccount(cpu_env, arg[0].in);
2685 #endif
2686 }
2687
2688 static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[],
2689 const uint32_t par[])
2690 {
2691 #ifndef CONFIG_USER_ONLY
2692 unsigned id = par[0] - DBREAKA;
2693 TCGv_i32 tmp = tcg_const_i32(id);
2694
2695 assert(id < dc->config->ndbreak);
2696 gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in);
2697 tcg_temp_free(tmp);
2698 #endif
2699 }
2700
2701 static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[],
2702 const uint32_t par[])
2703 {
2704 #ifndef CONFIG_USER_ONLY
2705 unsigned id = par[0] - DBREAKC;
2706 TCGv_i32 tmp = tcg_const_i32(id);
2707
2708 assert(id < dc->config->ndbreak);
2709 gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in);
2710 tcg_temp_free(tmp);
2711 #endif
2712 }
2713
2714 static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[],
2715 const uint32_t par[])
2716 {
2717 #ifndef CONFIG_USER_ONLY
2718 unsigned id = par[0] - IBREAKA;
2719 TCGv_i32 tmp = tcg_const_i32(id);
2720
2721 assert(id < dc->config->nibreak);
2722 gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in);
2723 tcg_temp_free(tmp);
2724 #endif
2725 }
2726
2727 static void translate_wsr_ibreakenable(DisasContext *dc, const OpcodeArg arg[],
2728 const uint32_t par[])
2729 {
2730 #ifndef CONFIG_USER_ONLY
2731 gen_helper_wsr_ibreakenable(cpu_env, arg[0].in);
2732 #endif
2733 }
2734
2735 static void translate_wsr_icount(DisasContext *dc, const OpcodeArg arg[],
2736 const uint32_t par[])
2737 {
2738 #ifndef CONFIG_USER_ONLY
2739 if (dc->icount) {
2740 tcg_gen_mov_i32(dc->next_icount, arg[0].in);
2741 } else {
2742 tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2743 }
2744 #endif
2745 }
2746
2747 static void translate_wsr_intclear(DisasContext *dc, const OpcodeArg arg[],
2748 const uint32_t par[])
2749 {
2750 #ifndef CONFIG_USER_ONLY
2751 gen_helper_intclear(cpu_env, arg[0].in);
2752 #endif
2753 }
2754
2755 static void translate_wsr_intset(DisasContext *dc, const OpcodeArg arg[],
2756 const uint32_t par[])
2757 {
2758 #ifndef CONFIG_USER_ONLY
2759 gen_helper_intset(cpu_env, arg[0].in);
2760 #endif
2761 }
2762
2763 static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[],
2764 const uint32_t par[])
2765 {
2766 #ifndef CONFIG_USER_ONLY
2767 gen_helper_wsr_memctl(cpu_env, arg[0].in);
2768 #endif
2769 }
2770
2771 static void translate_wsr_mpuenb(DisasContext *dc, const OpcodeArg arg[],
2772 const uint32_t par[])
2773 {
2774 #ifndef CONFIG_USER_ONLY
2775 gen_helper_wsr_mpuenb(cpu_env, arg[0].in);
2776 #endif
2777 }
2778
2779 static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[],
2780 const uint32_t par[])
2781 {
2782 #ifndef CONFIG_USER_ONLY
2783 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
2784 PS_UM | PS_EXCM | PS_INTLEVEL;
2785
2786 if (option_enabled(dc, XTENSA_OPTION_MMU) ||
2787 option_enabled(dc, XTENSA_OPTION_MPU)) {
2788 mask |= PS_RING;
2789 }
2790 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask);
2791 #endif
2792 }
2793
2794 static void translate_wsr_rasid(DisasContext *dc, const OpcodeArg arg[],
2795 const uint32_t par[])
2796 {
2797 #ifndef CONFIG_USER_ONLY
2798 gen_helper_wsr_rasid(cpu_env, arg[0].in);
2799 #endif
2800 }
2801
2802 static void translate_wsr_sar(DisasContext *dc, const OpcodeArg arg[],
2803 const uint32_t par[])
2804 {
2805 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, 0x3f);
2806 if (dc->sar_m32_5bit) {
2807 tcg_gen_discard_i32(dc->sar_m32);
2808 }
2809 dc->sar_5bit = false;
2810 dc->sar_m32_5bit = false;
2811 }
2812
2813 static void translate_wsr_windowbase(DisasContext *dc, const OpcodeArg arg[],
2814 const uint32_t par[])
2815 {
2816 #ifndef CONFIG_USER_ONLY
2817 tcg_gen_mov_i32(cpu_windowbase_next, arg[0].in);
2818 #endif
2819 }
2820
2821 static void translate_wsr_windowstart(DisasContext *dc, const OpcodeArg arg[],
2822 const uint32_t par[])
2823 {
2824 #ifndef CONFIG_USER_ONLY
2825 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in,
2826 (1 << dc->config->nareg / 4) - 1);
2827 #endif
2828 }
2829
2830 static void translate_wur(DisasContext *dc, const OpcodeArg arg[],
2831 const uint32_t par[])
2832 {
2833 tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in);
2834 }
2835
2836 static void translate_xor(DisasContext *dc, const OpcodeArg arg[],
2837 const uint32_t par[])
2838 {
2839 tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in);
2840 }
2841
2842 static void translate_xsr(DisasContext *dc, const OpcodeArg arg[],
2843 const uint32_t par[])
2844 {
2845 if (sr_name[par[0]]) {
2846 TCGv_i32 tmp = tcg_temp_new_i32();
2847
2848 tcg_gen_mov_i32(tmp, arg[0].in);
2849 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2850 tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
2851 tcg_temp_free(tmp);
2852 } else {
2853 tcg_gen_movi_i32(arg[0].out, 0);
2854 }
2855 }
2856
2857 static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[],
2858 const uint32_t par[])
2859 {
2860 if (sr_name[par[0]]) {
2861 TCGv_i32 tmp = tcg_temp_new_i32();
2862
2863 tcg_gen_mov_i32(tmp, arg[0].in);
2864 tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2865 tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
2866 tcg_temp_free(tmp);
2867 } else {
2868 tcg_gen_movi_i32(arg[0].out, 0);
2869 }
2870 }
2871
2872 static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
2873 const uint32_t par[])
2874 {
2875 #ifndef CONFIG_USER_ONLY
2876 TCGv_i32 tmp = tcg_temp_new_i32();
2877
2878 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
2879 gen_io_start();
2880 }
2881
2882 gen_helper_update_ccount(cpu_env);
2883 tcg_gen_mov_i32(tmp, cpu_SR[par[0]]);
2884 gen_helper_wsr_ccount(cpu_env, arg[0].in);
2885 tcg_gen_mov_i32(arg[0].out, tmp);
2886 tcg_temp_free(tmp);
2887
2888 #endif
2889 }
2890
2891 #define gen_translate_xsr(name) \
2892 static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg[], \
2893 const uint32_t par[]) \
2894 { \
2895 TCGv_i32 tmp = tcg_temp_new_i32(); \
2896 \
2897 if (sr_name[par[0]]) { \
2898 tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
2899 } else { \
2900 tcg_gen_movi_i32(tmp, 0); \
2901 } \
2902 translate_wsr_##name(dc, arg, par); \
2903 tcg_gen_mov_i32(arg[0].out, tmp); \
2904 tcg_temp_free(tmp); \
2905 }
2906
2907 gen_translate_xsr(acchi)
2908 gen_translate_xsr(ccompare)
2909 gen_translate_xsr(dbreaka)
2910 gen_translate_xsr(dbreakc)
2911 gen_translate_xsr(ibreaka)
2912 gen_translate_xsr(ibreakenable)
2913 gen_translate_xsr(icount)
2914 gen_translate_xsr(memctl)
2915 gen_translate_xsr(mpuenb)
2916 gen_translate_xsr(ps)
2917 gen_translate_xsr(rasid)
2918 gen_translate_xsr(sar)
2919 gen_translate_xsr(windowbase)
2920 gen_translate_xsr(windowstart)
2921
2922 #undef gen_translate_xsr
2923
2924 static const XtensaOpcodeOps core_ops[] = {
2925 {
2926 .name = "abs",
2927 .translate = translate_abs,
2928 }, {
2929 .name = (const char * const[]) {
2930 "add", "add.n", NULL,
2931 },
2932 .translate = translate_add,
2933 .op_flags = XTENSA_OP_NAME_ARRAY,
2934 }, {
2935 .name = (const char * const[]) {
2936 "addi", "addi.n", NULL,
2937 },
2938 .translate = translate_addi,
2939 .op_flags = XTENSA_OP_NAME_ARRAY,
2940 }, {
2941 .name = "addmi",
2942 .translate = translate_addi,
2943 }, {
2944 .name = "addx2",
2945 .translate = translate_addx,
2946 .par = (const uint32_t[]){1},
2947 }, {
2948 .name = "addx4",
2949 .translate = translate_addx,
2950 .par = (const uint32_t[]){2},
2951 }, {
2952 .name = "addx8",
2953 .translate = translate_addx,
2954 .par = (const uint32_t[]){3},
2955 }, {
2956 .name = "all4",
2957 .translate = translate_all,
2958 .par = (const uint32_t[]){true, 4},
2959 }, {
2960 .name = "all8",
2961 .translate = translate_all,
2962 .par = (const uint32_t[]){true, 8},
2963 }, {
2964 .name = "and",
2965 .translate = translate_and,
2966 }, {
2967 .name = "andb",
2968 .translate = translate_boolean,
2969 .par = (const uint32_t[]){BOOLEAN_AND},
2970 }, {
2971 .name = "andbc",
2972 .translate = translate_boolean,
2973 .par = (const uint32_t[]){BOOLEAN_ANDC},
2974 }, {
2975 .name = "any4",
2976 .translate = translate_all,
2977 .par = (const uint32_t[]){false, 4},
2978 }, {
2979 .name = "any8",
2980 .translate = translate_all,
2981 .par = (const uint32_t[]){false, 8},
2982 }, {
2983 .name = (const char * const[]) {
2984 "ball", "ball.w15", "ball.w18", NULL,
2985 },
2986 .translate = translate_ball,
2987 .par = (const uint32_t[]){TCG_COND_EQ},
2988 .op_flags = XTENSA_OP_NAME_ARRAY,
2989 }, {
2990 .name = (const char * const[]) {
2991 "bany", "bany.w15", "bany.w18", NULL,
2992 },
2993 .translate = translate_bany,
2994 .par = (const uint32_t[]){TCG_COND_NE},
2995 .op_flags = XTENSA_OP_NAME_ARRAY,
2996 }, {
2997 .name = (const char * const[]) {
2998 "bbc", "bbc.w15", "bbc.w18", NULL,
2999 },
3000 .translate = translate_bb,
3001 .par = (const uint32_t[]){TCG_COND_EQ},
3002 .op_flags = XTENSA_OP_NAME_ARRAY,
3003 }, {
3004 .name = (const char * const[]) {
3005 "bbci", "bbci.w15", "bbci.w18", NULL,
3006 },
3007 .translate = translate_bbi,
3008 .par = (const uint32_t[]){TCG_COND_EQ},
3009 .op_flags = XTENSA_OP_NAME_ARRAY,
3010 }, {
3011 .name = (const char * const[]) {
3012 "bbs", "bbs.w15", "bbs.w18", NULL,
3013 },
3014 .translate = translate_bb,
3015 .par = (const uint32_t[]){TCG_COND_NE},
3016 .op_flags = XTENSA_OP_NAME_ARRAY,
3017 }, {
3018 .name = (const char * const[]) {
3019 "bbsi", "bbsi.w15", "bbsi.w18", NULL,
3020 },
3021 .translate = translate_bbi,
3022 .par = (const uint32_t[]){TCG_COND_NE},
3023 .op_flags = XTENSA_OP_NAME_ARRAY,
3024 }, {
3025 .name = (const char * const[]) {
3026 "beq", "beq.w15", "beq.w18", NULL,
3027 },
3028 .translate = translate_b,
3029 .par = (const uint32_t[]){TCG_COND_EQ},
3030 .op_flags = XTENSA_OP_NAME_ARRAY,
3031 }, {
3032 .name = (const char * const[]) {
3033 "beqi", "beqi.w15", "beqi.w18", NULL,
3034 },
3035 .translate = translate_bi,
3036 .par = (const uint32_t[]){TCG_COND_EQ},
3037 .op_flags = XTENSA_OP_NAME_ARRAY,
3038 }, {
3039 .name = (const char * const[]) {
3040 "beqz", "beqz.n", "beqz.w15", "beqz.w18", NULL,
3041 },
3042 .translate = translate_bz,
3043 .par = (const uint32_t[]){TCG_COND_EQ},
3044 .op_flags = XTENSA_OP_NAME_ARRAY,
3045 }, {
3046 .name = "bf",
3047 .translate = translate_bp,
3048 .par = (const uint32_t[]){TCG_COND_EQ},
3049 }, {
3050 .name = (const char * const[]) {
3051 "bge", "bge.w15", "bge.w18", NULL,
3052 },
3053 .translate = translate_b,
3054 .par = (const uint32_t[]){TCG_COND_GE},
3055 .op_flags = XTENSA_OP_NAME_ARRAY,
3056 }, {
3057 .name = (const char * const[]) {
3058 "bgei", "bgei.w15", "bgei.w18", NULL,
3059 },
3060 .translate = translate_bi,
3061 .par = (const uint32_t[]){TCG_COND_GE},
3062 .op_flags = XTENSA_OP_NAME_ARRAY,
3063 }, {
3064 .name = (const char * const[]) {
3065 "bgeu", "bgeu.w15", "bgeu.w18", NULL,
3066 },
3067 .translate = translate_b,
3068 .par = (const uint32_t[]){TCG_COND_GEU},
3069 .op_flags = XTENSA_OP_NAME_ARRAY,
3070 }, {
3071 .name = (const char * const[]) {
3072 "bgeui", "bgeui.w15", "bgeui.w18", NULL,
3073 },
3074 .translate = translate_bi,
3075 .par = (const uint32_t[]){TCG_COND_GEU},
3076 .op_flags = XTENSA_OP_NAME_ARRAY,
3077 }, {
3078 .name = (const char * const[]) {
3079 "bgez", "bgez.w15", "bgez.w18", NULL,
3080 },
3081 .translate = translate_bz,
3082 .par = (const uint32_t[]){TCG_COND_GE},
3083 .op_flags = XTENSA_OP_NAME_ARRAY,
3084 }, {
3085 .name = (const char * const[]) {
3086 "blt", "blt.w15", "blt.w18", NULL,
3087 },
3088 .translate = translate_b,
3089 .par = (const uint32_t[]){TCG_COND_LT},
3090 .op_flags = XTENSA_OP_NAME_ARRAY,
3091 }, {
3092 .name = (const char * const[]) {
3093 "blti", "blti.w15", "blti.w18", NULL,
3094 },
3095 .translate = translate_bi,
3096 .par = (const uint32_t[]){TCG_COND_LT},
3097 .op_flags = XTENSA_OP_NAME_ARRAY,
3098 }, {
3099 .name = (const char * const[]) {
3100 "bltu", "bltu.w15", "bltu.w18", NULL,
3101 },
3102 .translate = translate_b,
3103 .par = (const uint32_t[]){TCG_COND_LTU},
3104 .op_flags = XTENSA_OP_NAME_ARRAY,
3105 }, {
3106 .name = (const char * const[]) {
3107 "bltui", "bltui.w15", "bltui.w18", NULL,
3108 },
3109 .translate = translate_bi,
3110 .par = (const uint32_t[]){TCG_COND_LTU},
3111 .op_flags = XTENSA_OP_NAME_ARRAY,
3112 }, {
3113 .name = (const char * const[]) {
3114 "bltz", "bltz.w15", "bltz.w18", NULL,
3115 },
3116 .translate = translate_bz,
3117 .par = (const uint32_t[]){TCG_COND_LT},
3118 .op_flags = XTENSA_OP_NAME_ARRAY,
3119 }, {
3120 .name = (const char * const[]) {
3121 "bnall", "bnall.w15", "bnall.w18", NULL,
3122 },
3123 .translate = translate_ball,
3124 .par = (const uint32_t[]){TCG_COND_NE},
3125 .op_flags = XTENSA_OP_NAME_ARRAY,
3126 }, {
3127 .name = (const char * const[]) {
3128 "bne", "bne.w15", "bne.w18", NULL,
3129 },
3130 .translate = translate_b,
3131 .par = (const uint32_t[]){TCG_COND_NE},
3132 .op_flags = XTENSA_OP_NAME_ARRAY,
3133 }, {
3134 .name = (const char * const[]) {
3135 "bnei", "bnei.w15", "bnei.w18", NULL,
3136 },
3137 .translate = translate_bi,
3138 .par = (const uint32_t[]){TCG_COND_NE},
3139 .op_flags = XTENSA_OP_NAME_ARRAY,
3140 }, {
3141 .name = (const char * const[]) {
3142 "bnez", "bnez.n", "bnez.w15", "bnez.w18", NULL,
3143 },
3144 .translate = translate_bz,
3145 .par = (const uint32_t[]){TCG_COND_NE},
3146 .op_flags = XTENSA_OP_NAME_ARRAY,
3147 }, {
3148 .name = (const char * const[]) {
3149 "bnone", "bnone.w15", "bnone.w18", NULL,
3150 },
3151 .translate = translate_bany,
3152 .par = (const uint32_t[]){TCG_COND_EQ},
3153 .op_flags = XTENSA_OP_NAME_ARRAY,
3154 }, {
3155 .name = "break",
3156 .translate = translate_nop,
3157 .par = (const uint32_t[]){DEBUGCAUSE_BI},
3158 .op_flags = XTENSA_OP_DEBUG_BREAK,
3159 }, {
3160 .name = "break.n",
3161 .translate = translate_nop,
3162 .par = (const uint32_t[]){DEBUGCAUSE_BN},
3163 .op_flags = XTENSA_OP_DEBUG_BREAK,
3164 }, {
3165 .name = "bt",
3166 .translate = translate_bp,
3167 .par = (const uint32_t[]){TCG_COND_NE},
3168 }, {
3169 .name = "call0",
3170 .translate = translate_call0,
3171 }, {
3172 .name = "call12",
3173 .translate = translate_callw,
3174 .par = (const uint32_t[]){3},
3175 }, {
3176 .name = "call4",
3177 .translate = translate_callw,
3178 .par = (const uint32_t[]){1},
3179 }, {
3180 .name = "call8",
3181 .translate = translate_callw,
3182 .par = (const uint32_t[]){2},
3183 }, {
3184 .name = "callx0",
3185 .translate = translate_callx0,
3186 }, {
3187 .name = "callx12",
3188 .translate = translate_callxw,
3189 .par = (const uint32_t[]){3},
3190 }, {
3191 .name = "callx4",
3192 .translate = translate_callxw,
3193 .par = (const uint32_t[]){1},
3194 }, {
3195 .name = "callx8",
3196 .translate = translate_callxw,
3197 .par = (const uint32_t[]){2},
3198 }, {
3199 .name = "clamps",
3200 .translate = translate_clamps,
3201 }, {
3202 .name = "clrb_expstate",
3203 .translate = translate_clrb_expstate,
3204 }, {
3205 .name = "clrex",
3206 .translate = translate_clrex,
3207 }, {
3208 .name = "const16",
3209 .translate = translate_const16,
3210 }, {
3211 .name = "depbits",
3212 .translate = translate_depbits,
3213 }, {
3214 .name = "dhi",
3215 .translate = translate_dcache,
3216 .op_flags = XTENSA_OP_PRIVILEGED,
3217 }, {
3218 .name = "dhi.b",
3219 .translate = translate_nop,
3220 }, {
3221 .name = "dhu",
3222 .translate = translate_dcache,
3223 .op_flags = XTENSA_OP_PRIVILEGED,
3224 }, {
3225 .name = "dhwb",
3226 .translate = translate_dcache,
3227 }, {
3228 .name = "dhwb.b",
3229 .translate = translate_nop,
3230 }, {
3231 .name = "dhwbi",
3232 .translate = translate_dcache,
3233 }, {
3234 .name = "dhwbi.b",
3235 .translate = translate_nop,
3236 }, {
3237 .name = "dii",
3238 .translate = translate_nop,
3239 .op_flags = XTENSA_OP_PRIVILEGED,
3240 }, {
3241 .name = "diu",
3242 .translate = translate_nop,
3243 .op_flags = XTENSA_OP_PRIVILEGED,
3244 }, {
3245 .name = "diwb",
3246 .translate = translate_nop,
3247 .op_flags = XTENSA_OP_PRIVILEGED,
3248 }, {
3249 .name = "diwbi",
3250 .translate = translate_nop,
3251 .op_flags = XTENSA_OP_PRIVILEGED,
3252 }, {
3253 .name = "diwbui.p",
3254 .translate = translate_diwbuip,
3255 .op_flags = XTENSA_OP_PRIVILEGED,
3256 }, {
3257 .name = "dpfl",
3258 .translate = translate_dcache,
3259 .op_flags = XTENSA_OP_PRIVILEGED,
3260 }, {
3261 .name = "dpfm.b",
3262 .translate = translate_nop,
3263 }, {
3264 .name = "dpfm.bf",
3265 .translate = translate_nop,
3266 }, {
3267 .name = "dpfr",
3268 .translate = translate_nop,
3269 }, {
3270 .name = "dpfr.b",
3271 .translate = translate_nop,
3272 }, {
3273 .name = "dpfr.bf",
3274 .translate = translate_nop,
3275 }, {
3276 .name = "dpfro",
3277 .translate = translate_nop,
3278 }, {
3279 .name = "dpfw",
3280 .translate = translate_nop,
3281 }, {
3282 .name = "dpfw.b",
3283 .translate = translate_nop,
3284 }, {
3285 .name = "dpfw.bf",
3286 .translate = translate_nop,
3287 }, {
3288 .name = "dpfwo",
3289 .translate = translate_nop,
3290 }, {
3291 .name = "dsync",
3292 .translate = translate_nop,
3293 }, {
3294 .name = "entry",
3295 .translate = translate_entry,
3296 .test_exceptions = test_exceptions_entry,
3297 .test_overflow = test_overflow_entry,
3298 .op_flags = XTENSA_OP_EXIT_TB_M1 |
3299 XTENSA_OP_SYNC_REGISTER_WINDOW,
3300 }, {
3301 .name = "esync",
3302 .translate = translate_nop,
3303 }, {
3304 .name = "excw",
3305 .translate = translate_nop,
3306 }, {
3307 .name = "extui",
3308 .translate = translate_extui,
3309 }, {
3310 .name = "extw",
3311 .translate = translate_memw,
3312 }, {
3313 .name = "getex",
3314 .translate = translate_getex,
3315 }, {
3316 .name = "hwwdtlba",
3317 .op_flags = XTENSA_OP_ILL,
3318 }, {
3319 .name = "hwwitlba",
3320 .op_flags = XTENSA_OP_ILL,
3321 }, {
3322 .name = "idtlb",
3323 .translate = translate_itlb,
3324 .par = (const uint32_t[]){true},
3325 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
3326 }, {
3327 .name = "ihi",
3328 .translate = translate_icache,
3329 }, {
3330 .name = "ihu",
3331 .translate = translate_icache,
3332 .op_flags = XTENSA_OP_PRIVILEGED,
3333 }, {
3334 .name = "iii",
3335 .translate = translate_nop,
3336 .op_flags = XTENSA_OP_PRIVILEGED,
3337 }, {
3338 .name = "iitlb",
3339 .translate = translate_itlb,
3340 .par = (const uint32_t[]){false},
3341 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
3342 }, {
3343 .name = "iiu",
3344 .translate = translate_nop,
3345 .op_flags = XTENSA_OP_PRIVILEGED,
3346 }, {
3347 .name = (const char * const[]) {
3348 "ill", "ill.n", NULL,
3349 },
3350 .op_flags = XTENSA_OP_ILL | XTENSA_OP_NAME_ARRAY,
3351 }, {
3352 .name = "ipf",
3353 .translate = translate_nop,
3354 }, {
3355 .name = "ipfl",
3356 .translate = translate_icache,
3357 .op_flags = XTENSA_OP_PRIVILEGED,
3358 }, {
3359 .name = "isync",
3360 .translate = translate_nop,
3361 }, {
3362 .name = "j",
3363 .translate = translate_j,
3364 }, {
3365 .name = "jx",
3366 .translate = translate_jx,
3367 }, {
3368 .name = "l16si",
3369 .translate = translate_ldst,
3370 .par = (const uint32_t[]){MO_TESW, false, false},
3371 .op_flags = XTENSA_OP_LOAD,
3372 }, {
3373 .name = "l16ui",
3374 .translate = translate_ldst,
3375 .par = (const uint32_t[]){MO_TEUW, false, false},
3376 .op_flags = XTENSA_OP_LOAD,
3377 }, {
3378 .name = "l32ai",
3379 .translate = translate_ldst,
3380 .par = (const uint32_t[]){MO_TEUL, true, false},
3381 .op_flags = XTENSA_OP_LOAD,
3382 }, {
3383 .name = "l32e",
3384 .translate = translate_l32e,
3385 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_LOAD,
3386 }, {
3387 .name = "l32ex",
3388 .translate = translate_l32ex,
3389 .op_flags = XTENSA_OP_LOAD,
3390 }, {
3391 .name = (const char * const[]) {
3392 "l32i", "l32i.n", NULL,
3393 },
3394 .translate = translate_ldst,
3395 .par = (const uint32_t[]){MO_TEUL, false, false},
3396 .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_LOAD,
3397 }, {
3398 .name = "l32r",
3399 .translate = translate_l32r,
3400 .op_flags = XTENSA_OP_LOAD,
3401 }, {
3402 .name = "l8ui",
3403 .translate = translate_ldst,
3404 .par = (const uint32_t[]){MO_UB, false, false},
3405 .op_flags = XTENSA_OP_LOAD,
3406 }, {
3407 .name = "lddec",
3408 .translate = translate_mac16,
3409 .par = (const uint32_t[]){MAC16_NONE, 0, -4},
3410 .op_flags = XTENSA_OP_LOAD,
3411 }, {
3412 .name = "ldinc",
3413 .translate = translate_mac16,
3414 .par = (const uint32_t[]){MAC16_NONE, 0, 4},
3415 .op_flags = XTENSA_OP_LOAD,
3416 }, {
3417 .name = "ldpte",
3418 .op_flags = XTENSA_OP_ILL,
3419 }, {
3420 .name = (const char * const[]) {
3421 "loop", "loop.w15", NULL,
3422 },
3423 .translate = translate_loop,
3424 .par = (const uint32_t[]){TCG_COND_NEVER},
3425 .op_flags = XTENSA_OP_NAME_ARRAY,
3426 }, {
3427 .name = (const char * const[]) {
3428 "loopgtz", "loopgtz.w15", NULL,
3429 },
3430 .translate = translate_loop,
3431 .par = (const uint32_t[]){TCG_COND_GT},
3432 .op_flags = XTENSA_OP_NAME_ARRAY,
3433 }, {
3434 .name = (const char * const[]) {
3435 "loopnez", "loopnez.w15", NULL,
3436 },
3437 .translate = translate_loop,
3438 .par = (const uint32_t[]){TCG_COND_NE},
3439 .op_flags = XTENSA_OP_NAME_ARRAY,
3440 }, {
3441 .name = "max",
3442 .translate = translate_smax,
3443 }, {
3444 .name = "maxu",
3445 .translate = translate_umax,
3446 }, {
3447 .name = "memw",
3448 .translate = translate_memw,
3449 }, {
3450 .name = "min",
3451 .translate = translate_smin,
3452 }, {
3453 .name = "minu",
3454 .translate = translate_umin,
3455 }, {
3456 .name = (const char * const[]) {
3457 "mov", "mov.n", NULL,
3458 },
3459 .translate = translate_mov,
3460 .op_flags = XTENSA_OP_NAME_ARRAY,
3461 }, {
3462 .name = "moveqz",
3463 .translate = translate_movcond,
3464 .par = (const uint32_t[]){TCG_COND_EQ},
3465 }, {
3466 .name = "movf",
3467 .translate = translate_movp,
3468 .par = (const uint32_t[]){TCG_COND_EQ},
3469 }, {
3470 .name = "movgez",
3471 .translate = translate_movcond,
3472 .par = (const uint32_t[]){TCG_COND_GE},
3473 }, {
3474 .name = "movi",
3475 .translate = translate_movi,
3476 }, {
3477 .name = "movi.n",
3478 .translate = translate_movi,
3479 }, {
3480 .name = "movltz",
3481 .translate = translate_movcond,
3482 .par = (const uint32_t[]){TCG_COND_LT},
3483 }, {
3484 .name = "movnez",
3485 .translate = translate_movcond,
3486 .par = (const uint32_t[]){TCG_COND_NE},
3487 }, {
3488 .name = "movsp",
3489 .translate = translate_movsp,
3490 .op_flags = XTENSA_OP_ALLOCA,
3491 }, {
3492 .name = "movt",
3493 .translate = translate_movp,
3494 .par = (const uint32_t[]){TCG_COND_NE},
3495 }, {
3496 .name = "mul.aa.hh",
3497 .translate = translate_mac16,
3498 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3499 }, {
3500 .name = "mul.aa.hl",
3501 .translate = translate_mac16,
3502 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3503 }, {
3504 .name = "mul.aa.lh",
3505 .translate = translate_mac16,
3506 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3507 }, {
3508 .name = "mul.aa.ll",
3509 .translate = translate_mac16,
3510 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3511 }, {
3512 .name = "mul.ad.hh",
3513 .translate = translate_mac16,
3514 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3515 }, {
3516 .name = "mul.ad.hl",
3517 .translate = translate_mac16,
3518 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3519 }, {
3520 .name = "mul.ad.lh",
3521 .translate = translate_mac16,
3522 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3523 }, {
3524 .name = "mul.ad.ll",
3525 .translate = translate_mac16,
3526 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3527 }, {
3528 .name = "mul.da.hh",
3529 .translate = translate_mac16,
3530 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3531 }, {
3532 .name = "mul.da.hl",
3533 .translate = translate_mac16,
3534 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3535 }, {
3536 .name = "mul.da.lh",
3537 .translate = translate_mac16,
3538 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3539 }, {
3540 .name = "mul.da.ll",
3541 .translate = translate_mac16,
3542 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3543 }, {
3544 .name = "mul.dd.hh",
3545 .translate = translate_mac16,
3546 .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0},
3547 }, {
3548 .name = "mul.dd.hl",
3549 .translate = translate_mac16,
3550 .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0},
3551 }, {
3552 .name = "mul.dd.lh",
3553 .translate = translate_mac16,
3554 .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0},
3555 }, {
3556 .name = "mul.dd.ll",
3557 .translate = translate_mac16,
3558 .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0},
3559 }, {
3560 .name = "mul16s",
3561 .translate = translate_mul16,
3562 .par = (const uint32_t[]){true},
3563 }, {
3564 .name = "mul16u",
3565 .translate = translate_mul16,
3566 .par = (const uint32_t[]){false},
3567 }, {
3568 .name = "mula.aa.hh",
3569 .translate = translate_mac16,
3570 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3571 }, {
3572 .name = "mula.aa.hl",
3573 .translate = translate_mac16,
3574 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3575 }, {
3576 .name = "mula.aa.lh",
3577 .translate = translate_mac16,
3578 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3579 }, {
3580 .name = "mula.aa.ll",
3581 .translate = translate_mac16,
3582 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3583 }, {
3584 .name = "mula.ad.hh",
3585 .translate = translate_mac16,
3586 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3587 }, {
3588 .name = "mula.ad.hl",
3589 .translate = translate_mac16,
3590 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3591 }, {
3592 .name = "mula.ad.lh",
3593 .translate = translate_mac16,
3594 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3595 }, {
3596 .name = "mula.ad.ll",
3597 .translate = translate_mac16,
3598 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3599 }, {
3600 .name = "mula.da.hh",
3601 .translate = translate_mac16,
3602 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3603 }, {
3604 .name = "mula.da.hh.lddec",
3605 .translate = translate_mac16,
3606 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4},
3607 }, {
3608 .name = "mula.da.hh.ldinc",
3609 .translate = translate_mac16,
3610 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4},
3611 }, {
3612 .name = "mula.da.hl",
3613 .translate = translate_mac16,
3614 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3615 }, {
3616 .name = "mula.da.hl.lddec",
3617 .translate = translate_mac16,
3618 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4},
3619 }, {
3620 .name = "mula.da.hl.ldinc",
3621 .translate = translate_mac16,
3622 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4},
3623 }, {
3624 .name = "mula.da.lh",
3625 .translate = translate_mac16,
3626 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3627 }, {
3628 .name = "mula.da.lh.lddec",
3629 .translate = translate_mac16,
3630 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4},
3631 }, {
3632 .name = "mula.da.lh.ldinc",
3633 .translate = translate_mac16,
3634 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4},
3635 }, {
3636 .name = "mula.da.ll",
3637 .translate = translate_mac16,
3638 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3639 }, {
3640 .name = "mula.da.ll.lddec",
3641 .translate = translate_mac16,
3642 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4},
3643 }, {
3644 .name = "mula.da.ll.ldinc",
3645 .translate = translate_mac16,
3646 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4},
3647 }, {
3648 .name = "mula.dd.hh",
3649 .translate = translate_mac16,
3650 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0},
3651 }, {
3652 .name = "mula.dd.hh.lddec",
3653 .translate = translate_mac16,
3654 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4},
3655 }, {
3656 .name = "mula.dd.hh.ldinc",
3657 .translate = translate_mac16,
3658 .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4},
3659 }, {
3660 .name = "mula.dd.hl",
3661 .translate = translate_mac16,
3662 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0},
3663 }, {
3664 .name = "mula.dd.hl.lddec",
3665 .translate = translate_mac16,
3666 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4},
3667 }, {
3668 .name = "mula.dd.hl.ldinc",
3669 .translate = translate_mac16,
3670 .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4},
3671 }, {
3672 .name = "mula.dd.lh",
3673 .translate = translate_mac16,
3674 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0},
3675 }, {
3676 .name = "mula.dd.lh.lddec",
3677 .translate = translate_mac16,
3678 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4},
3679 }, {
3680 .name = "mula.dd.lh.ldinc",
3681 .translate = translate_mac16,
3682 .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4},
3683 }, {
3684 .name = "mula.dd.ll",
3685 .translate = translate_mac16,
3686 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0},
3687 }, {
3688 .name = "mula.dd.ll.lddec",
3689 .translate = translate_mac16,
3690 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4},
3691 }, {
3692 .name = "mula.dd.ll.ldinc",
3693 .translate = translate_mac16,
3694 .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4},
3695 }, {
3696 .name = "mull",
3697 .translate = translate_mull,
3698 }, {
3699 .name = "muls.aa.hh",
3700 .translate = translate_mac16,
3701 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3702 }, {
3703 .name = "muls.aa.hl",
3704 .translate = translate_mac16,
3705 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3706 }, {
3707 .name = "muls.aa.lh",
3708 .translate = translate_mac16,
3709 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3710 }, {
3711 .name = "muls.aa.ll",
3712 .translate = translate_mac16,
3713 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3714 }, {
3715 .name = "muls.ad.hh",
3716 .translate = translate_mac16,
3717 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3718 }, {
3719 .name = "muls.ad.hl",
3720 .translate = translate_mac16,
3721 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3722 }, {
3723 .name = "muls.ad.lh",
3724 .translate = translate_mac16,
3725 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3726 }, {
3727 .name = "muls.ad.ll",
3728 .translate = translate_mac16,
3729 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3730 }, {
3731 .name = "muls.da.hh",
3732 .translate = translate_mac16,
3733 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3734 }, {
3735 .name = "muls.da.hl",
3736 .translate = translate_mac16,
3737 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3738 }, {
3739 .name = "muls.da.lh",
3740 .translate = translate_mac16,
3741 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3742 }, {
3743 .name = "muls.da.ll",
3744 .translate = translate_mac16,
3745 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3746 }, {
3747 .name = "muls.dd.hh",
3748 .translate = translate_mac16,
3749 .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0},
3750 }, {
3751 .name = "muls.dd.hl",
3752 .translate = translate_mac16,
3753 .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0},
3754 }, {
3755 .name = "muls.dd.lh",
3756 .translate = translate_mac16,
3757 .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0},
3758 }, {
3759 .name = "muls.dd.ll",
3760 .translate = translate_mac16,
3761 .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0},
3762 }, {
3763 .name = "mulsh",
3764 .translate = translate_mulh,
3765 .par = (const uint32_t[]){true},
3766 }, {
3767 .name = "muluh",
3768 .translate = translate_mulh,
3769 .par = (const uint32_t[]){false},
3770 }, {
3771 .name = "neg",
3772 .translate = translate_neg,
3773 }, {
3774 .name = (const char * const[]) {
3775 "nop", "nop.n", NULL,
3776 },
3777 .translate = translate_nop,
3778 .op_flags = XTENSA_OP_NAME_ARRAY,
3779 }, {
3780 .name = "nsa",
3781 .translate = translate_nsa,
3782 }, {
3783 .name = "nsau",
3784 .translate = translate_nsau,
3785 }, {
3786 .name = "or",
3787 .translate = translate_or,
3788 }, {
3789 .name = "orb",
3790 .translate = translate_boolean,
3791 .par = (const uint32_t[]){BOOLEAN_OR},
3792 }, {
3793 .name = "orbc",
3794 .translate = translate_boolean,
3795 .par = (const uint32_t[]){BOOLEAN_ORC},
3796 }, {
3797 .name = "pdtlb",
3798 .translate = translate_ptlb,
3799 .par = (const uint32_t[]){true},
3800 .op_flags = XTENSA_OP_PRIVILEGED,
3801 }, {
3802 .name = "pfend.a",
3803 .translate = translate_nop,
3804 }, {
3805 .name = "pfend.o",
3806 .translate = translate_nop,
3807 }, {
3808 .name = "pfnxt.f",
3809 .translate = translate_nop,
3810 }, {
3811 .name = "pfwait.a",
3812 .translate = translate_nop,
3813 }, {
3814 .name = "pfwait.r",
3815 .translate = translate_nop,
3816 }, {
3817 .name = "pitlb",
3818 .translate = translate_ptlb,
3819 .par = (const uint32_t[]){false},
3820 .op_flags = XTENSA_OP_PRIVILEGED,
3821 }, {
3822 .name = "pptlb",
3823 .translate = translate_pptlb,
3824 .op_flags = XTENSA_OP_PRIVILEGED,
3825 }, {
3826 .name = "quos",
3827 .translate = translate_quos,
3828 .par = (const uint32_t[]){true},
3829 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3830 }, {
3831 .name = "quou",
3832 .translate = translate_quou,
3833 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3834 }, {
3835 .name = "rdtlb0",
3836 .translate = translate_rtlb,
3837 .par = (const uint32_t[]){true, 0},
3838 .op_flags = XTENSA_OP_PRIVILEGED,
3839 }, {
3840 .name = "rdtlb1",
3841 .translate = translate_rtlb,
3842 .par = (const uint32_t[]){true, 1},
3843 .op_flags = XTENSA_OP_PRIVILEGED,
3844 }, {
3845 .name = "read_impwire",
3846 .translate = translate_read_impwire,
3847 }, {
3848 .name = "rems",
3849 .translate = translate_quos,
3850 .par = (const uint32_t[]){false},
3851 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3852 }, {
3853 .name = "remu",
3854 .translate = translate_remu,
3855 .op_flags = XTENSA_OP_DIVIDE_BY_ZERO,
3856 }, {
3857 .name = "rer",
3858 .translate = translate_rer,
3859 .op_flags = XTENSA_OP_PRIVILEGED,
3860 }, {
3861 .name = (const char * const[]) {
3862 "ret", "ret.n", NULL,
3863 },
3864 .translate = translate_ret,
3865 .op_flags = XTENSA_OP_NAME_ARRAY,
3866 }, {
3867 .name = (const char * const[]) {
3868 "retw", "retw.n", NULL,
3869 },
3870 .translate = translate_retw,
3871 .test_exceptions = test_exceptions_retw,
3872 .op_flags = XTENSA_OP_UNDERFLOW | XTENSA_OP_NAME_ARRAY,
3873 }, {
3874 .name = "rfdd",
3875 .op_flags = XTENSA_OP_ILL,
3876 }, {
3877 .name = "rfde",
3878 .translate = translate_rfde,
3879 .op_flags = XTENSA_OP_PRIVILEGED,
3880 }, {
3881 .name = "rfdo",
3882 .op_flags = XTENSA_OP_ILL,
3883 }, {
3884 .name = "rfe",
3885 .translate = translate_rfe,
3886 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3887 }, {
3888 .name = "rfi",
3889 .translate = translate_rfi,
3890 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3891 }, {
3892 .name = "rfwo",
3893 .translate = translate_rfw,
3894 .par = (const uint32_t[]){true},
3895 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3896 }, {
3897 .name = "rfwu",
3898 .translate = translate_rfw,
3899 .par = (const uint32_t[]){false},
3900 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_CHECK_INTERRUPTS,
3901 }, {
3902 .name = "ritlb0",
3903 .translate = translate_rtlb,
3904 .par = (const uint32_t[]){false, 0},
3905 .op_flags = XTENSA_OP_PRIVILEGED,
3906 }, {
3907 .name = "ritlb1",
3908 .translate = translate_rtlb,
3909 .par = (const uint32_t[]){false, 1},
3910 .op_flags = XTENSA_OP_PRIVILEGED,
3911 }, {
3912 .name = "rptlb0",
3913 .translate = translate_rptlb0,
3914 .op_flags = XTENSA_OP_PRIVILEGED,
3915 }, {
3916 .name = "rptlb1",
3917 .translate = translate_rptlb1,
3918 .op_flags = XTENSA_OP_PRIVILEGED,
3919 }, {
3920 .name = "rotw",
3921 .translate = translate_rotw,
3922 .op_flags = XTENSA_OP_PRIVILEGED |
3923 XTENSA_OP_EXIT_TB_M1 |
3924 XTENSA_OP_SYNC_REGISTER_WINDOW,
3925 }, {
3926 .name = "rsil",
3927 .translate = translate_rsil,
3928 .op_flags =
3929 XTENSA_OP_PRIVILEGED |
3930 XTENSA_OP_EXIT_TB_0 |
3931 XTENSA_OP_CHECK_INTERRUPTS,
3932 }, {
3933 .name = "rsr.176",
3934 .translate = translate_rsr,
3935 .par = (const uint32_t[]){176},
3936 .op_flags = XTENSA_OP_PRIVILEGED,
3937 }, {
3938 .name = "rsr.208",
3939 .translate = translate_rsr,
3940 .par = (const uint32_t[]){208},
3941 .op_flags = XTENSA_OP_PRIVILEGED,
3942 }, {
3943 .name = "rsr.acchi",
3944 .translate = translate_rsr,
3945 .test_exceptions = test_exceptions_sr,
3946 .par = (const uint32_t[]){
3947 ACCHI,
3948 XTENSA_OPTION_MAC16,
3949 },
3950 }, {
3951 .name = "rsr.acclo",
3952 .translate = translate_rsr,
3953 .test_exceptions = test_exceptions_sr,
3954 .par = (const uint32_t[]){
3955 ACCLO,
3956 XTENSA_OPTION_MAC16,
3957 },
3958 }, {
3959 .name = "rsr.atomctl",
3960 .translate = translate_rsr,
3961 .test_exceptions = test_exceptions_sr,
3962 .par = (const uint32_t[]){
3963 ATOMCTL,
3964 XTENSA_OPTION_ATOMCTL,
3965 },
3966 .op_flags = XTENSA_OP_PRIVILEGED,
3967 }, {
3968 .name = "rsr.br",
3969 .translate = translate_rsr,
3970 .test_exceptions = test_exceptions_sr,
3971 .par = (const uint32_t[]){
3972 BR,
3973 XTENSA_OPTION_BOOLEAN,
3974 },
3975 }, {
3976 .name = "rsr.cacheadrdis",
3977 .translate = translate_rsr,
3978 .test_exceptions = test_exceptions_sr,
3979 .par = (const uint32_t[]){
3980 CACHEADRDIS,
3981 XTENSA_OPTION_MPU,
3982 },
3983 .op_flags = XTENSA_OP_PRIVILEGED,
3984 }, {
3985 .name = "rsr.cacheattr",
3986 .translate = translate_rsr,
3987 .test_exceptions = test_exceptions_sr,
3988 .par = (const uint32_t[]){
3989 CACHEATTR,
3990 XTENSA_OPTION_CACHEATTR,
3991 },
3992 .op_flags = XTENSA_OP_PRIVILEGED,
3993 }, {
3994 .name = "rsr.ccompare0",
3995 .translate = translate_rsr,
3996 .test_exceptions = test_exceptions_ccompare,
3997 .par = (const uint32_t[]){
3998 CCOMPARE,
3999 XTENSA_OPTION_TIMER_INTERRUPT,
4000 },
4001 .op_flags = XTENSA_OP_PRIVILEGED,
4002 }, {
4003 .name = "rsr.ccompare1",
4004 .translate = translate_rsr,
4005 .test_exceptions = test_exceptions_ccompare,
4006 .par = (const uint32_t[]){
4007 CCOMPARE + 1,
4008 XTENSA_OPTION_TIMER_INTERRUPT,
4009 },
4010 .op_flags = XTENSA_OP_PRIVILEGED,
4011 }, {
4012 .name = "rsr.ccompare2",
4013 .translate = translate_rsr,
4014 .test_exceptions = test_exceptions_ccompare,
4015 .par = (const uint32_t[]){
4016 CCOMPARE + 2,
4017 XTENSA_OPTION_TIMER_INTERRUPT,
4018 },
4019 .op_flags = XTENSA_OP_PRIVILEGED,
4020 }, {
4021 .name = "rsr.ccount",
4022 .translate = translate_rsr_ccount,
4023 .test_exceptions = test_exceptions_sr,
4024 .par = (const uint32_t[]){
4025 CCOUNT,
4026 XTENSA_OPTION_TIMER_INTERRUPT,
4027 },
4028 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4029 }, {
4030 .name = "rsr.configid0",
4031 .translate = translate_rsr,
4032 .par = (const uint32_t[]){CONFIGID0},
4033 .op_flags = XTENSA_OP_PRIVILEGED,
4034 }, {
4035 .name = "rsr.configid1",
4036 .translate = translate_rsr,
4037 .par = (const uint32_t[]){CONFIGID1},
4038 .op_flags = XTENSA_OP_PRIVILEGED,
4039 }, {
4040 .name = "rsr.cpenable",
4041 .translate = translate_rsr,
4042 .test_exceptions = test_exceptions_sr,
4043 .par = (const uint32_t[]){
4044 CPENABLE,
4045 XTENSA_OPTION_COPROCESSOR,
4046 },
4047 .op_flags = XTENSA_OP_PRIVILEGED,
4048 }, {
4049 .name = "rsr.dbreaka0",
4050 .translate = translate_rsr,
4051 .test_exceptions = test_exceptions_dbreak,
4052 .par = (const uint32_t[]){
4053 DBREAKA,
4054 XTENSA_OPTION_DEBUG,
4055 },
4056 .op_flags = XTENSA_OP_PRIVILEGED,
4057 }, {
4058 .name = "rsr.dbreaka1",
4059 .translate = translate_rsr,
4060 .test_exceptions = test_exceptions_dbreak,
4061 .par = (const uint32_t[]){
4062 DBREAKA + 1,
4063 XTENSA_OPTION_DEBUG,
4064 },
4065 .op_flags = XTENSA_OP_PRIVILEGED,
4066 }, {
4067 .name = "rsr.dbreakc0",
4068 .translate = translate_rsr,
4069 .test_exceptions = test_exceptions_dbreak,
4070 .par = (const uint32_t[]){
4071 DBREAKC,
4072 XTENSA_OPTION_DEBUG,
4073 },
4074 .op_flags = XTENSA_OP_PRIVILEGED,
4075 }, {
4076 .name = "rsr.dbreakc1",
4077 .translate = translate_rsr,
4078 .test_exceptions = test_exceptions_dbreak,
4079 .par = (const uint32_t[]){
4080 DBREAKC + 1,
4081 XTENSA_OPTION_DEBUG,
4082 },
4083 .op_flags = XTENSA_OP_PRIVILEGED,
4084 }, {
4085 .name = "rsr.ddr",
4086 .translate = translate_rsr,
4087 .test_exceptions = test_exceptions_sr,
4088 .par = (const uint32_t[]){
4089 DDR,
4090 XTENSA_OPTION_DEBUG,
4091 },
4092 .op_flags = XTENSA_OP_PRIVILEGED,
4093 }, {
4094 .name = "rsr.debugcause",
4095 .translate = translate_rsr,
4096 .test_exceptions = test_exceptions_sr,
4097 .par = (const uint32_t[]){
4098 DEBUGCAUSE,
4099 XTENSA_OPTION_DEBUG,
4100 },
4101 .op_flags = XTENSA_OP_PRIVILEGED,
4102 }, {
4103 .name = "rsr.depc",
4104 .translate = translate_rsr,
4105 .test_exceptions = test_exceptions_sr,
4106 .par = (const uint32_t[]){
4107 DEPC,
4108 XTENSA_OPTION_EXCEPTION,
4109 },
4110 .op_flags = XTENSA_OP_PRIVILEGED,
4111 }, {
4112 .name = "rsr.dtlbcfg",
4113 .translate = translate_rsr,
4114 .test_exceptions = test_exceptions_sr,
4115 .par = (const uint32_t[]){
4116 DTLBCFG,
4117 XTENSA_OPTION_MMU,
4118 },
4119 .op_flags = XTENSA_OP_PRIVILEGED,
4120 }, {
4121 .name = "rsr.epc1",
4122 .translate = translate_rsr,
4123 .test_exceptions = test_exceptions_sr,
4124 .par = (const uint32_t[]){
4125 EPC1,
4126 XTENSA_OPTION_EXCEPTION,
4127 },
4128 .op_flags = XTENSA_OP_PRIVILEGED,
4129 }, {
4130 .name = "rsr.epc2",
4131 .translate = translate_rsr,
4132 .test_exceptions = test_exceptions_hpi,
4133 .par = (const uint32_t[]){
4134 EPC1 + 1,
4135 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4136 },
4137 .op_flags = XTENSA_OP_PRIVILEGED,
4138 }, {
4139 .name = "rsr.epc3",
4140 .translate = translate_rsr,
4141 .test_exceptions = test_exceptions_hpi,
4142 .par = (const uint32_t[]){
4143 EPC1 + 2,
4144 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4145 },
4146 .op_flags = XTENSA_OP_PRIVILEGED,
4147 }, {
4148 .name = "rsr.epc4",
4149 .translate = translate_rsr,
4150 .test_exceptions = test_exceptions_hpi,
4151 .par = (const uint32_t[]){
4152 EPC1 + 3,
4153 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4154 },
4155 .op_flags = XTENSA_OP_PRIVILEGED,
4156 }, {
4157 .name = "rsr.epc5",
4158 .translate = translate_rsr,
4159 .test_exceptions = test_exceptions_hpi,
4160 .par = (const uint32_t[]){
4161 EPC1 + 4,
4162 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4163 },
4164 .op_flags = XTENSA_OP_PRIVILEGED,
4165 }, {
4166 .name = "rsr.epc6",
4167 .translate = translate_rsr,
4168 .test_exceptions = test_exceptions_hpi,
4169 .par = (const uint32_t[]){
4170 EPC1 + 5,
4171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4172 },
4173 .op_flags = XTENSA_OP_PRIVILEGED,
4174 }, {
4175 .name = "rsr.epc7",
4176 .translate = translate_rsr,
4177 .test_exceptions = test_exceptions_hpi,
4178 .par = (const uint32_t[]){
4179 EPC1 + 6,
4180 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4181 },
4182 .op_flags = XTENSA_OP_PRIVILEGED,
4183 }, {
4184 .name = "rsr.eps2",
4185 .translate = translate_rsr,
4186 .test_exceptions = test_exceptions_hpi,
4187 .par = (const uint32_t[]){
4188 EPS2,
4189 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4190 },
4191 .op_flags = XTENSA_OP_PRIVILEGED,
4192 }, {
4193 .name = "rsr.eps3",
4194 .translate = translate_rsr,
4195 .test_exceptions = test_exceptions_hpi,
4196 .par = (const uint32_t[]){
4197 EPS2 + 1,
4198 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4199 },
4200 .op_flags = XTENSA_OP_PRIVILEGED,
4201 }, {
4202 .name = "rsr.eps4",
4203 .translate = translate_rsr,
4204 .test_exceptions = test_exceptions_hpi,
4205 .par = (const uint32_t[]){
4206 EPS2 + 2,
4207 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4208 },
4209 .op_flags = XTENSA_OP_PRIVILEGED,
4210 }, {
4211 .name = "rsr.eps5",
4212 .translate = translate_rsr,
4213 .test_exceptions = test_exceptions_hpi,
4214 .par = (const uint32_t[]){
4215 EPS2 + 3,
4216 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4217 },
4218 .op_flags = XTENSA_OP_PRIVILEGED,
4219 }, {
4220 .name = "rsr.eps6",
4221 .translate = translate_rsr,
4222 .test_exceptions = test_exceptions_hpi,
4223 .par = (const uint32_t[]){
4224 EPS2 + 4,
4225 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4226 },
4227 .op_flags = XTENSA_OP_PRIVILEGED,
4228 }, {
4229 .name = "rsr.eps7",
4230 .translate = translate_rsr,
4231 .test_exceptions = test_exceptions_hpi,
4232 .par = (const uint32_t[]){
4233 EPS2 + 5,
4234 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4235 },
4236 .op_flags = XTENSA_OP_PRIVILEGED,
4237 }, {
4238 .name = "rsr.eraccess",
4239 .translate = translate_rsr,
4240 .par = (const uint32_t[]){ERACCESS},
4241 .op_flags = XTENSA_OP_PRIVILEGED,
4242 }, {
4243 .name = "rsr.exccause",
4244 .translate = translate_rsr,
4245 .test_exceptions = test_exceptions_sr,
4246 .par = (const uint32_t[]){
4247 EXCCAUSE,
4248 XTENSA_OPTION_EXCEPTION,
4249 },
4250 .op_flags = XTENSA_OP_PRIVILEGED,
4251 }, {
4252 .name = "rsr.excsave1",
4253 .translate = translate_rsr,
4254 .test_exceptions = test_exceptions_sr,
4255 .par = (const uint32_t[]){
4256 EXCSAVE1,
4257 XTENSA_OPTION_EXCEPTION,
4258 },
4259 .op_flags = XTENSA_OP_PRIVILEGED,
4260 }, {
4261 .name = "rsr.excsave2",
4262 .translate = translate_rsr,
4263 .test_exceptions = test_exceptions_hpi,
4264 .par = (const uint32_t[]){
4265 EXCSAVE1 + 1,
4266 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4267 },
4268 .op_flags = XTENSA_OP_PRIVILEGED,
4269 }, {
4270 .name = "rsr.excsave3",
4271 .translate = translate_rsr,
4272 .test_exceptions = test_exceptions_hpi,
4273 .par = (const uint32_t[]){
4274 EXCSAVE1 + 2,
4275 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4276 },
4277 .op_flags = XTENSA_OP_PRIVILEGED,
4278 }, {
4279 .name = "rsr.excsave4",
4280 .translate = translate_rsr,
4281 .test_exceptions = test_exceptions_hpi,
4282 .par = (const uint32_t[]){
4283 EXCSAVE1 + 3,
4284 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4285 },
4286 .op_flags = XTENSA_OP_PRIVILEGED,
4287 }, {
4288 .name = "rsr.excsave5",
4289 .translate = translate_rsr,
4290 .test_exceptions = test_exceptions_hpi,
4291 .par = (const uint32_t[]){
4292 EXCSAVE1 + 4,
4293 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4294 },
4295 .op_flags = XTENSA_OP_PRIVILEGED,
4296 }, {
4297 .name = "rsr.excsave6",
4298 .translate = translate_rsr,
4299 .test_exceptions = test_exceptions_hpi,
4300 .par = (const uint32_t[]){
4301 EXCSAVE1 + 5,
4302 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4303 },
4304 .op_flags = XTENSA_OP_PRIVILEGED,
4305 }, {
4306 .name = "rsr.excsave7",
4307 .translate = translate_rsr,
4308 .test_exceptions = test_exceptions_hpi,
4309 .par = (const uint32_t[]){
4310 EXCSAVE1 + 6,
4311 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
4312 },
4313 .op_flags = XTENSA_OP_PRIVILEGED,
4314 }, {
4315 .name = "rsr.excvaddr",
4316 .translate = translate_rsr,
4317 .test_exceptions = test_exceptions_sr,
4318 .par = (const uint32_t[]){
4319 EXCVADDR,
4320 XTENSA_OPTION_EXCEPTION,
4321 },
4322 .op_flags = XTENSA_OP_PRIVILEGED,
4323 }, {
4324 .name = "rsr.ibreaka0",
4325 .translate = translate_rsr,
4326 .test_exceptions = test_exceptions_ibreak,
4327 .par = (const uint32_t[]){
4328 IBREAKA,
4329 XTENSA_OPTION_DEBUG,
4330 },
4331 .op_flags = XTENSA_OP_PRIVILEGED,
4332 }, {
4333 .name = "rsr.ibreaka1",
4334 .translate = translate_rsr,
4335 .test_exceptions = test_exceptions_ibreak,
4336 .par = (const uint32_t[]){
4337 IBREAKA + 1,
4338 XTENSA_OPTION_DEBUG,
4339 },
4340 .op_flags = XTENSA_OP_PRIVILEGED,
4341 }, {
4342 .name = "rsr.ibreakenable",
4343 .translate = translate_rsr,
4344 .test_exceptions = test_exceptions_sr,
4345 .par = (const uint32_t[]){
4346 IBREAKENABLE,
4347 XTENSA_OPTION_DEBUG,
4348 },
4349 .op_flags = XTENSA_OP_PRIVILEGED,
4350 }, {
4351 .name = "rsr.icount",
4352 .translate = translate_rsr,
4353 .test_exceptions = test_exceptions_sr,
4354 .par = (const uint32_t[]){
4355 ICOUNT,
4356 XTENSA_OPTION_DEBUG,
4357 },
4358 .op_flags = XTENSA_OP_PRIVILEGED,
4359 }, {
4360 .name = "rsr.icountlevel",
4361 .translate = translate_rsr,
4362 .test_exceptions = test_exceptions_sr,
4363 .par = (const uint32_t[]){
4364 ICOUNTLEVEL,
4365 XTENSA_OPTION_DEBUG,
4366 },
4367 .op_flags = XTENSA_OP_PRIVILEGED,
4368 }, {
4369 .name = "rsr.intclear",
4370 .translate = translate_rsr,
4371 .test_exceptions = test_exceptions_sr,
4372 .par = (const uint32_t[]){
4373 INTCLEAR,
4374 XTENSA_OPTION_INTERRUPT,
4375 },
4376 .op_flags = XTENSA_OP_PRIVILEGED,
4377 }, {
4378 .name = "rsr.intenable",
4379 .translate = translate_rsr,
4380 .test_exceptions = test_exceptions_sr,
4381 .par = (const uint32_t[]){
4382 INTENABLE,
4383 XTENSA_OPTION_INTERRUPT,
4384 },
4385 .op_flags = XTENSA_OP_PRIVILEGED,
4386 }, {
4387 .name = "rsr.interrupt",
4388 .translate = translate_rsr_ccount,
4389 .test_exceptions = test_exceptions_sr,
4390 .par = (const uint32_t[]){
4391 INTSET,
4392 XTENSA_OPTION_INTERRUPT,
4393 },
4394 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4395 }, {
4396 .name = "rsr.intset",
4397 .translate = translate_rsr_ccount,
4398 .test_exceptions = test_exceptions_sr,
4399 .par = (const uint32_t[]){
4400 INTSET,
4401 XTENSA_OPTION_INTERRUPT,
4402 },
4403 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4404 }, {
4405 .name = "rsr.itlbcfg",
4406 .translate = translate_rsr,
4407 .test_exceptions = test_exceptions_sr,
4408 .par = (const uint32_t[]){
4409 ITLBCFG,
4410 XTENSA_OPTION_MMU,
4411 },
4412 .op_flags = XTENSA_OP_PRIVILEGED,
4413 }, {
4414 .name = "rsr.lbeg",
4415 .translate = translate_rsr,
4416 .test_exceptions = test_exceptions_sr,
4417 .par = (const uint32_t[]){
4418 LBEG,
4419 XTENSA_OPTION_LOOP,
4420 },
4421 }, {
4422 .name = "rsr.lcount",
4423 .translate = translate_rsr,
4424 .test_exceptions = test_exceptions_sr,
4425 .par = (const uint32_t[]){
4426 LCOUNT,
4427 XTENSA_OPTION_LOOP,
4428 },
4429 }, {
4430 .name = "rsr.lend",
4431 .translate = translate_rsr,
4432 .test_exceptions = test_exceptions_sr,
4433 .par = (const uint32_t[]){
4434 LEND,
4435 XTENSA_OPTION_LOOP,
4436 },
4437 }, {
4438 .name = "rsr.litbase",
4439 .translate = translate_rsr,
4440 .test_exceptions = test_exceptions_sr,
4441 .par = (const uint32_t[]){
4442 LITBASE,
4443 XTENSA_OPTION_EXTENDED_L32R,
4444 },
4445 }, {
4446 .name = "rsr.m0",
4447 .translate = translate_rsr,
4448 .test_exceptions = test_exceptions_sr,
4449 .par = (const uint32_t[]){
4450 MR,
4451 XTENSA_OPTION_MAC16,
4452 },
4453 }, {
4454 .name = "rsr.m1",
4455 .translate = translate_rsr,
4456 .test_exceptions = test_exceptions_sr,
4457 .par = (const uint32_t[]){
4458 MR + 1,
4459 XTENSA_OPTION_MAC16,
4460 },
4461 }, {
4462 .name = "rsr.m2",
4463 .translate = translate_rsr,
4464 .test_exceptions = test_exceptions_sr,
4465 .par = (const uint32_t[]){
4466 MR + 2,
4467 XTENSA_OPTION_MAC16,
4468 },
4469 }, {
4470 .name = "rsr.m3",
4471 .translate = translate_rsr,
4472 .test_exceptions = test_exceptions_sr,
4473 .par = (const uint32_t[]){
4474 MR + 3,
4475 XTENSA_OPTION_MAC16,
4476 },
4477 }, {
4478 .name = "rsr.memctl",
4479 .translate = translate_rsr,
4480 .par = (const uint32_t[]){MEMCTL},
4481 .op_flags = XTENSA_OP_PRIVILEGED,
4482 }, {
4483 .name = "rsr.mecr",
4484 .translate = translate_rsr,
4485 .test_exceptions = test_exceptions_sr,
4486 .par = (const uint32_t[]){
4487 MECR,
4488 XTENSA_OPTION_MEMORY_ECC_PARITY,
4489 },
4490 .op_flags = XTENSA_OP_PRIVILEGED,
4491 }, {
4492 .name = "rsr.mepc",
4493 .translate = translate_rsr,
4494 .test_exceptions = test_exceptions_sr,
4495 .par = (const uint32_t[]){
4496 MEPC,
4497 XTENSA_OPTION_MEMORY_ECC_PARITY,
4498 },
4499 .op_flags = XTENSA_OP_PRIVILEGED,
4500 }, {
4501 .name = "rsr.meps",
4502 .translate = translate_rsr,
4503 .test_exceptions = test_exceptions_sr,
4504 .par = (const uint32_t[]){
4505 MEPS,
4506 XTENSA_OPTION_MEMORY_ECC_PARITY,
4507 },
4508 .op_flags = XTENSA_OP_PRIVILEGED,
4509 }, {
4510 .name = "rsr.mesave",
4511 .translate = translate_rsr,
4512 .test_exceptions = test_exceptions_sr,
4513 .par = (const uint32_t[]){
4514 MESAVE,
4515 XTENSA_OPTION_MEMORY_ECC_PARITY,
4516 },
4517 .op_flags = XTENSA_OP_PRIVILEGED,
4518 }, {
4519 .name = "rsr.mesr",
4520 .translate = translate_rsr,
4521 .test_exceptions = test_exceptions_sr,
4522 .par = (const uint32_t[]){
4523 MESR,
4524 XTENSA_OPTION_MEMORY_ECC_PARITY,
4525 },
4526 .op_flags = XTENSA_OP_PRIVILEGED,
4527 }, {
4528 .name = "rsr.mevaddr",
4529 .translate = translate_rsr,
4530 .test_exceptions = test_exceptions_sr,
4531 .par = (const uint32_t[]){
4532 MESR,
4533 XTENSA_OPTION_MEMORY_ECC_PARITY,
4534 },
4535 .op_flags = XTENSA_OP_PRIVILEGED,
4536 }, {
4537 .name = "rsr.misc0",
4538 .translate = translate_rsr,
4539 .test_exceptions = test_exceptions_sr,
4540 .par = (const uint32_t[]){
4541 MISC,
4542 XTENSA_OPTION_MISC_SR,
4543 },
4544 .op_flags = XTENSA_OP_PRIVILEGED,
4545 }, {
4546 .name = "rsr.misc1",
4547 .translate = translate_rsr,
4548 .test_exceptions = test_exceptions_sr,
4549 .par = (const uint32_t[]){
4550 MISC + 1,
4551 XTENSA_OPTION_MISC_SR,
4552 },
4553 .op_flags = XTENSA_OP_PRIVILEGED,
4554 }, {
4555 .name = "rsr.misc2",
4556 .translate = translate_rsr,
4557 .test_exceptions = test_exceptions_sr,
4558 .par = (const uint32_t[]){
4559 MISC + 2,
4560 XTENSA_OPTION_MISC_SR,
4561 },
4562 .op_flags = XTENSA_OP_PRIVILEGED,
4563 }, {
4564 .name = "rsr.misc3",
4565 .translate = translate_rsr,
4566 .test_exceptions = test_exceptions_sr,
4567 .par = (const uint32_t[]){
4568 MISC + 3,
4569 XTENSA_OPTION_MISC_SR,
4570 },
4571 .op_flags = XTENSA_OP_PRIVILEGED,
4572 }, {
4573 .name = "rsr.mpucfg",
4574 .translate = translate_rsr,
4575 .test_exceptions = test_exceptions_sr,
4576 .par = (const uint32_t[]){
4577 MPUCFG,
4578 XTENSA_OPTION_MPU,
4579 },
4580 .op_flags = XTENSA_OP_PRIVILEGED,
4581 }, {
4582 .name = "rsr.mpuenb",
4583 .translate = translate_rsr,
4584 .test_exceptions = test_exceptions_sr,
4585 .par = (const uint32_t[]){
4586 MPUENB,
4587 XTENSA_OPTION_MPU,
4588 },
4589 .op_flags = XTENSA_OP_PRIVILEGED,
4590 }, {
4591 .name = "rsr.prefctl",
4592 .translate = translate_rsr,
4593 .par = (const uint32_t[]){PREFCTL},
4594 }, {
4595 .name = "rsr.prid",
4596 .translate = translate_rsr,
4597 .test_exceptions = test_exceptions_sr,
4598 .par = (const uint32_t[]){
4599 PRID,
4600 XTENSA_OPTION_PROCESSOR_ID,
4601 },
4602 .op_flags = XTENSA_OP_PRIVILEGED,
4603 }, {
4604 .name = "rsr.ps",
4605 .translate = translate_rsr,
4606 .test_exceptions = test_exceptions_sr,
4607 .par = (const uint32_t[]){
4608 PS,
4609 XTENSA_OPTION_EXCEPTION,
4610 },
4611 .op_flags = XTENSA_OP_PRIVILEGED,
4612 }, {
4613 .name = "rsr.ptevaddr",
4614 .translate = translate_rsr_ptevaddr,
4615 .test_exceptions = test_exceptions_sr,
4616 .par = (const uint32_t[]){
4617 PTEVADDR,
4618 XTENSA_OPTION_MMU,
4619 },
4620 .op_flags = XTENSA_OP_PRIVILEGED,
4621 }, {
4622 .name = "rsr.rasid",
4623 .translate = translate_rsr,
4624 .test_exceptions = test_exceptions_sr,
4625 .par = (const uint32_t[]){
4626 RASID,
4627 XTENSA_OPTION_MMU,
4628 },
4629 .op_flags = XTENSA_OP_PRIVILEGED,
4630 }, {
4631 .name = "rsr.sar",
4632 .translate = translate_rsr,
4633 .par = (const uint32_t[]){SAR},
4634 }, {
4635 .name = "rsr.scompare1",
4636 .translate = translate_rsr,
4637 .test_exceptions = test_exceptions_sr,
4638 .par = (const uint32_t[]){
4639 SCOMPARE1,
4640 XTENSA_OPTION_CONDITIONAL_STORE,
4641 },
4642 }, {
4643 .name = "rsr.vecbase",
4644 .translate = translate_rsr,
4645 .test_exceptions = test_exceptions_sr,
4646 .par = (const uint32_t[]){
4647 VECBASE,
4648 XTENSA_OPTION_RELOCATABLE_VECTOR,
4649 },
4650 .op_flags = XTENSA_OP_PRIVILEGED,
4651 }, {
4652 .name = "rsr.windowbase",
4653 .translate = translate_rsr,
4654 .test_exceptions = test_exceptions_sr,
4655 .par = (const uint32_t[]){
4656 WINDOW_BASE,
4657 XTENSA_OPTION_WINDOWED_REGISTER,
4658 },
4659 .op_flags = XTENSA_OP_PRIVILEGED,
4660 }, {
4661 .name = "rsr.windowstart",
4662 .translate = translate_rsr,
4663 .test_exceptions = test_exceptions_sr,
4664 .par = (const uint32_t[]){
4665 WINDOW_START,
4666 XTENSA_OPTION_WINDOWED_REGISTER,
4667 },
4668 .op_flags = XTENSA_OP_PRIVILEGED,
4669 }, {
4670 .name = "rsync",
4671 .translate = translate_nop,
4672 }, {
4673 .name = "rur.expstate",
4674 .translate = translate_rur,
4675 .par = (const uint32_t[]){EXPSTATE},
4676 }, {
4677 .name = "rur.threadptr",
4678 .translate = translate_rur,
4679 .par = (const uint32_t[]){THREADPTR},
4680 }, {
4681 .name = "s16i",
4682 .translate = translate_ldst,
4683 .par = (const uint32_t[]){MO_TEUW, false, true},
4684 .op_flags = XTENSA_OP_STORE,
4685 }, {
4686 .name = "s32c1i",
4687 .translate = translate_s32c1i,
4688 .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE,
4689 }, {
4690 .name = "s32e",
4691 .translate = translate_s32e,
4692 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_STORE,
4693 }, {
4694 .name = "s32ex",
4695 .translate = translate_s32ex,
4696 .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE,
4697 }, {
4698 .name = (const char * const[]) {
4699 "s32i", "s32i.n", "s32nb", NULL,
4700 },
4701 .translate = translate_ldst,
4702 .par = (const uint32_t[]){MO_TEUL, false, true},
4703 .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_STORE,
4704 }, {
4705 .name = "s32ri",
4706 .translate = translate_ldst,
4707 .par = (const uint32_t[]){MO_TEUL, true, true},
4708 .op_flags = XTENSA_OP_STORE,
4709 }, {
4710 .name = "s8i",
4711 .translate = translate_ldst,
4712 .par = (const uint32_t[]){MO_UB, false, true},
4713 .op_flags = XTENSA_OP_STORE,
4714 }, {
4715 .name = "salt",
4716 .translate = translate_salt,
4717 .par = (const uint32_t[]){TCG_COND_LT},
4718 }, {
4719 .name = "saltu",
4720 .translate = translate_salt,
4721 .par = (const uint32_t[]){TCG_COND_LTU},
4722 }, {
4723 .name = "setb_expstate",
4724 .translate = translate_setb_expstate,
4725 }, {
4726 .name = "sext",
4727 .translate = translate_sext,
4728 }, {
4729 .name = "simcall",
4730 .translate = translate_simcall,
4731 .test_exceptions = test_exceptions_simcall,
4732 .op_flags = XTENSA_OP_PRIVILEGED,
4733 }, {
4734 .name = "sll",
4735 .translate = translate_sll,
4736 }, {
4737 .name = "slli",
4738 .translate = translate_slli,
4739 }, {
4740 .name = "sra",
4741 .translate = translate_sra,
4742 }, {
4743 .name = "srai",
4744 .translate = translate_srai,
4745 }, {
4746 .name = "src",
4747 .translate = translate_src,
4748 }, {
4749 .name = "srl",
4750 .translate = translate_srl,
4751 }, {
4752 .name = "srli",
4753 .translate = translate_srli,
4754 }, {
4755 .name = "ssa8b",
4756 .translate = translate_ssa8b,
4757 }, {
4758 .name = "ssa8l",
4759 .translate = translate_ssa8l,
4760 }, {
4761 .name = "ssai",
4762 .translate = translate_ssai,
4763 }, {
4764 .name = "ssl",
4765 .translate = translate_ssl,
4766 }, {
4767 .name = "ssr",
4768 .translate = translate_ssr,
4769 }, {
4770 .name = "sub",
4771 .translate = translate_sub,
4772 }, {
4773 .name = "subx2",
4774 .translate = translate_subx,
4775 .par = (const uint32_t[]){1},
4776 }, {
4777 .name = "subx4",
4778 .translate = translate_subx,
4779 .par = (const uint32_t[]){2},
4780 }, {
4781 .name = "subx8",
4782 .translate = translate_subx,
4783 .par = (const uint32_t[]){3},
4784 }, {
4785 .name = "syscall",
4786 .op_flags = XTENSA_OP_SYSCALL,
4787 }, {
4788 .name = "umul.aa.hh",
4789 .translate = translate_mac16,
4790 .par = (const uint32_t[]){MAC16_UMUL, MAC16_HH, 0},
4791 }, {
4792 .name = "umul.aa.hl",
4793 .translate = translate_mac16,
4794 .par = (const uint32_t[]){MAC16_UMUL, MAC16_HL, 0},
4795 }, {
4796 .name = "umul.aa.lh",
4797 .translate = translate_mac16,
4798 .par = (const uint32_t[]){MAC16_UMUL, MAC16_LH, 0},
4799 }, {
4800 .name = "umul.aa.ll",
4801 .translate = translate_mac16,
4802 .par = (const uint32_t[]){MAC16_UMUL, MAC16_LL, 0},
4803 }, {
4804 .name = "waiti",
4805 .translate = translate_waiti,
4806 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4807 }, {
4808 .name = "wdtlb",
4809 .translate = translate_wtlb,
4810 .par = (const uint32_t[]){true},
4811 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4812 }, {
4813 .name = "wer",
4814 .translate = translate_wer,
4815 .op_flags = XTENSA_OP_PRIVILEGED,
4816 }, {
4817 .name = "witlb",
4818 .translate = translate_wtlb,
4819 .par = (const uint32_t[]){false},
4820 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4821 }, {
4822 .name = "wptlb",
4823 .translate = translate_wptlb,
4824 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4825 }, {
4826 .name = "wrmsk_expstate",
4827 .translate = translate_wrmsk_expstate,
4828 }, {
4829 .name = "wsr.176",
4830 .op_flags = XTENSA_OP_ILL,
4831 }, {
4832 .name = "wsr.208",
4833 .op_flags = XTENSA_OP_ILL,
4834 }, {
4835 .name = "wsr.acchi",
4836 .translate = translate_wsr_acchi,
4837 .test_exceptions = test_exceptions_sr,
4838 .par = (const uint32_t[]){
4839 ACCHI,
4840 XTENSA_OPTION_MAC16,
4841 },
4842 }, {
4843 .name = "wsr.acclo",
4844 .translate = translate_wsr,
4845 .test_exceptions = test_exceptions_sr,
4846 .par = (const uint32_t[]){
4847 ACCLO,
4848 XTENSA_OPTION_MAC16,
4849 },
4850 }, {
4851 .name = "wsr.atomctl",
4852 .translate = translate_wsr_mask,
4853 .test_exceptions = test_exceptions_sr,
4854 .par = (const uint32_t[]){
4855 ATOMCTL,
4856 XTENSA_OPTION_ATOMCTL,
4857 0x3f,
4858 },
4859 .op_flags = XTENSA_OP_PRIVILEGED,
4860 }, {
4861 .name = "wsr.br",
4862 .translate = translate_wsr_mask,
4863 .test_exceptions = test_exceptions_sr,
4864 .par = (const uint32_t[]){
4865 BR,
4866 XTENSA_OPTION_BOOLEAN,
4867 0xffff,
4868 },
4869 }, {
4870 .name = "wsr.cacheadrdis",
4871 .translate = translate_wsr_mask,
4872 .test_exceptions = test_exceptions_sr,
4873 .par = (const uint32_t[]){
4874 CACHEADRDIS,
4875 XTENSA_OPTION_MPU,
4876 0xff,
4877 },
4878 .op_flags = XTENSA_OP_PRIVILEGED,
4879 }, {
4880 .name = "wsr.cacheattr",
4881 .translate = translate_wsr,
4882 .test_exceptions = test_exceptions_sr,
4883 .par = (const uint32_t[]){
4884 CACHEATTR,
4885 XTENSA_OPTION_CACHEATTR,
4886 },
4887 .op_flags = XTENSA_OP_PRIVILEGED,
4888 }, {
4889 .name = "wsr.ccompare0",
4890 .translate = translate_wsr_ccompare,
4891 .test_exceptions = test_exceptions_ccompare,
4892 .par = (const uint32_t[]){
4893 CCOMPARE,
4894 XTENSA_OPTION_TIMER_INTERRUPT,
4895 },
4896 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4897 }, {
4898 .name = "wsr.ccompare1",
4899 .translate = translate_wsr_ccompare,
4900 .test_exceptions = test_exceptions_ccompare,
4901 .par = (const uint32_t[]){
4902 CCOMPARE + 1,
4903 XTENSA_OPTION_TIMER_INTERRUPT,
4904 },
4905 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4906 }, {
4907 .name = "wsr.ccompare2",
4908 .translate = translate_wsr_ccompare,
4909 .test_exceptions = test_exceptions_ccompare,
4910 .par = (const uint32_t[]){
4911 CCOMPARE + 2,
4912 XTENSA_OPTION_TIMER_INTERRUPT,
4913 },
4914 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4915 }, {
4916 .name = "wsr.ccount",
4917 .translate = translate_wsr_ccount,
4918 .test_exceptions = test_exceptions_sr,
4919 .par = (const uint32_t[]){
4920 CCOUNT,
4921 XTENSA_OPTION_TIMER_INTERRUPT,
4922 },
4923 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
4924 }, {
4925 .name = "wsr.configid0",
4926 .op_flags = XTENSA_OP_ILL,
4927 }, {
4928 .name = "wsr.configid1",
4929 .op_flags = XTENSA_OP_ILL,
4930 }, {
4931 .name = "wsr.cpenable",
4932 .translate = translate_wsr_mask,
4933 .test_exceptions = test_exceptions_sr,
4934 .par = (const uint32_t[]){
4935 CPENABLE,
4936 XTENSA_OPTION_COPROCESSOR,
4937 0xff,
4938 },
4939 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
4940 }, {
4941 .name = "wsr.dbreaka0",
4942 .translate = translate_wsr_dbreaka,
4943 .test_exceptions = test_exceptions_dbreak,
4944 .par = (const uint32_t[]){
4945 DBREAKA,
4946 XTENSA_OPTION_DEBUG,
4947 },
4948 .op_flags = XTENSA_OP_PRIVILEGED,
4949 }, {
4950 .name = "wsr.dbreaka1",
4951 .translate = translate_wsr_dbreaka,
4952 .test_exceptions = test_exceptions_dbreak,
4953 .par = (const uint32_t[]){
4954 DBREAKA + 1,
4955 XTENSA_OPTION_DEBUG,
4956 },
4957 .op_flags = XTENSA_OP_PRIVILEGED,
4958 }, {
4959 .name = "wsr.dbreakc0",
4960 .translate = translate_wsr_dbreakc,
4961 .test_exceptions = test_exceptions_dbreak,
4962 .par = (const uint32_t[]){
4963 DBREAKC,
4964 XTENSA_OPTION_DEBUG,
4965 },
4966 .op_flags = XTENSA_OP_PRIVILEGED,
4967 }, {
4968 .name = "wsr.dbreakc1",
4969 .translate = translate_wsr_dbreakc,
4970 .test_exceptions = test_exceptions_dbreak,
4971 .par = (const uint32_t[]){
4972 DBREAKC + 1,
4973 XTENSA_OPTION_DEBUG,
4974 },
4975 .op_flags = XTENSA_OP_PRIVILEGED,
4976 }, {
4977 .name = "wsr.ddr",
4978 .translate = translate_wsr,
4979 .test_exceptions = test_exceptions_sr,
4980 .par = (const uint32_t[]){
4981 DDR,
4982 XTENSA_OPTION_DEBUG,
4983 },
4984 .op_flags = XTENSA_OP_PRIVILEGED,
4985 }, {
4986 .name = "wsr.debugcause",
4987 .op_flags = XTENSA_OP_ILL,
4988 }, {
4989 .name = "wsr.depc",
4990 .translate = translate_wsr,
4991 .test_exceptions = test_exceptions_sr,
4992 .par = (const uint32_t[]){
4993 DEPC,
4994 XTENSA_OPTION_EXCEPTION,
4995 },
4996 .op_flags = XTENSA_OP_PRIVILEGED,
4997 }, {
4998 .name = "wsr.dtlbcfg",
4999 .translate = translate_wsr_mask,
5000 .test_exceptions = test_exceptions_sr,
5001 .par = (const uint32_t[]){
5002 DTLBCFG,
5003 XTENSA_OPTION_MMU,
5004 0x01130000,
5005 },
5006 .op_flags = XTENSA_OP_PRIVILEGED,
5007 }, {
5008 .name = "wsr.epc1",
5009 .translate = translate_wsr,
5010 .test_exceptions = test_exceptions_sr,
5011 .par = (const uint32_t[]){
5012 EPC1,
5013 XTENSA_OPTION_EXCEPTION,
5014 },
5015 .op_flags = XTENSA_OP_PRIVILEGED,
5016 }, {
5017 .name = "wsr.epc2",
5018 .translate = translate_wsr,
5019 .test_exceptions = test_exceptions_hpi,
5020 .par = (const uint32_t[]){
5021 EPC1 + 1,
5022 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5023 },
5024 .op_flags = XTENSA_OP_PRIVILEGED,
5025 }, {
5026 .name = "wsr.epc3",
5027 .translate = translate_wsr,
5028 .test_exceptions = test_exceptions_hpi,
5029 .par = (const uint32_t[]){
5030 EPC1 + 2,
5031 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5032 },
5033 .op_flags = XTENSA_OP_PRIVILEGED,
5034 }, {
5035 .name = "wsr.epc4",
5036 .translate = translate_wsr,
5037 .test_exceptions = test_exceptions_hpi,
5038 .par = (const uint32_t[]){
5039 EPC1 + 3,
5040 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5041 },
5042 .op_flags = XTENSA_OP_PRIVILEGED,
5043 }, {
5044 .name = "wsr.epc5",
5045 .translate = translate_wsr,
5046 .test_exceptions = test_exceptions_hpi,
5047 .par = (const uint32_t[]){
5048 EPC1 + 4,
5049 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5050 },
5051 .op_flags = XTENSA_OP_PRIVILEGED,
5052 }, {
5053 .name = "wsr.epc6",
5054 .translate = translate_wsr,
5055 .test_exceptions = test_exceptions_hpi,
5056 .par = (const uint32_t[]){
5057 EPC1 + 5,
5058 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5059 },
5060 .op_flags = XTENSA_OP_PRIVILEGED,
5061 }, {
5062 .name = "wsr.epc7",
5063 .translate = translate_wsr,
5064 .test_exceptions = test_exceptions_hpi,
5065 .par = (const uint32_t[]){
5066 EPC1 + 6,
5067 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5068 },
5069 .op_flags = XTENSA_OP_PRIVILEGED,
5070 }, {
5071 .name = "wsr.eps2",
5072 .translate = translate_wsr,
5073 .test_exceptions = test_exceptions_hpi,
5074 .par = (const uint32_t[]){
5075 EPS2,
5076 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5077 },
5078 .op_flags = XTENSA_OP_PRIVILEGED,
5079 }, {
5080 .name = "wsr.eps3",
5081 .translate = translate_wsr,
5082 .test_exceptions = test_exceptions_hpi,
5083 .par = (const uint32_t[]){
5084 EPS2 + 1,
5085 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5086 },
5087 .op_flags = XTENSA_OP_PRIVILEGED,
5088 }, {
5089 .name = "wsr.eps4",
5090 .translate = translate_wsr,
5091 .test_exceptions = test_exceptions_hpi,
5092 .par = (const uint32_t[]){
5093 EPS2 + 2,
5094 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5095 },
5096 .op_flags = XTENSA_OP_PRIVILEGED,
5097 }, {
5098 .name = "wsr.eps5",
5099 .translate = translate_wsr,
5100 .test_exceptions = test_exceptions_hpi,
5101 .par = (const uint32_t[]){
5102 EPS2 + 3,
5103 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5104 },
5105 .op_flags = XTENSA_OP_PRIVILEGED,
5106 }, {
5107 .name = "wsr.eps6",
5108 .translate = translate_wsr,
5109 .test_exceptions = test_exceptions_hpi,
5110 .par = (const uint32_t[]){
5111 EPS2 + 4,
5112 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5113 },
5114 .op_flags = XTENSA_OP_PRIVILEGED,
5115 }, {
5116 .name = "wsr.eps7",
5117 .translate = translate_wsr,
5118 .test_exceptions = test_exceptions_hpi,
5119 .par = (const uint32_t[]){
5120 EPS2 + 5,
5121 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5122 },
5123 .op_flags = XTENSA_OP_PRIVILEGED,
5124 }, {
5125 .name = "wsr.eraccess",
5126 .translate = translate_wsr_mask,
5127 .par = (const uint32_t[]){
5128 ERACCESS,
5129 0,
5130 0xffff,
5131 },
5132 .op_flags = XTENSA_OP_PRIVILEGED,
5133 }, {
5134 .name = "wsr.exccause",
5135 .translate = translate_wsr,
5136 .test_exceptions = test_exceptions_sr,
5137 .par = (const uint32_t[]){
5138 EXCCAUSE,
5139 XTENSA_OPTION_EXCEPTION,
5140 },
5141 .op_flags = XTENSA_OP_PRIVILEGED,
5142 }, {
5143 .name = "wsr.excsave1",
5144 .translate = translate_wsr,
5145 .test_exceptions = test_exceptions_sr,
5146 .par = (const uint32_t[]){
5147 EXCSAVE1,
5148 XTENSA_OPTION_EXCEPTION,
5149 },
5150 .op_flags = XTENSA_OP_PRIVILEGED,
5151 }, {
5152 .name = "wsr.excsave2",
5153 .translate = translate_wsr,
5154 .test_exceptions = test_exceptions_hpi,
5155 .par = (const uint32_t[]){
5156 EXCSAVE1 + 1,
5157 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5158 },
5159 .op_flags = XTENSA_OP_PRIVILEGED,
5160 }, {
5161 .name = "wsr.excsave3",
5162 .translate = translate_wsr,
5163 .test_exceptions = test_exceptions_hpi,
5164 .par = (const uint32_t[]){
5165 EXCSAVE1 + 2,
5166 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5167 },
5168 .op_flags = XTENSA_OP_PRIVILEGED,
5169 }, {
5170 .name = "wsr.excsave4",
5171 .translate = translate_wsr,
5172 .test_exceptions = test_exceptions_hpi,
5173 .par = (const uint32_t[]){
5174 EXCSAVE1 + 3,
5175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5176 },
5177 .op_flags = XTENSA_OP_PRIVILEGED,
5178 }, {
5179 .name = "wsr.excsave5",
5180 .translate = translate_wsr,
5181 .test_exceptions = test_exceptions_hpi,
5182 .par = (const uint32_t[]){
5183 EXCSAVE1 + 4,
5184 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5185 },
5186 .op_flags = XTENSA_OP_PRIVILEGED,
5187 }, {
5188 .name = "wsr.excsave6",
5189 .translate = translate_wsr,
5190 .test_exceptions = test_exceptions_hpi,
5191 .par = (const uint32_t[]){
5192 EXCSAVE1 + 5,
5193 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5194 },
5195 .op_flags = XTENSA_OP_PRIVILEGED,
5196 }, {
5197 .name = "wsr.excsave7",
5198 .translate = translate_wsr,
5199 .test_exceptions = test_exceptions_hpi,
5200 .par = (const uint32_t[]){
5201 EXCSAVE1 + 6,
5202 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5203 },
5204 .op_flags = XTENSA_OP_PRIVILEGED,
5205 }, {
5206 .name = "wsr.excvaddr",
5207 .translate = translate_wsr,
5208 .test_exceptions = test_exceptions_sr,
5209 .par = (const uint32_t[]){
5210 EXCVADDR,
5211 XTENSA_OPTION_EXCEPTION,
5212 },
5213 .op_flags = XTENSA_OP_PRIVILEGED,
5214 }, {
5215 .name = "wsr.ibreaka0",
5216 .translate = translate_wsr_ibreaka,
5217 .test_exceptions = test_exceptions_ibreak,
5218 .par = (const uint32_t[]){
5219 IBREAKA,
5220 XTENSA_OPTION_DEBUG,
5221 },
5222 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5223 }, {
5224 .name = "wsr.ibreaka1",
5225 .translate = translate_wsr_ibreaka,
5226 .test_exceptions = test_exceptions_ibreak,
5227 .par = (const uint32_t[]){
5228 IBREAKA + 1,
5229 XTENSA_OPTION_DEBUG,
5230 },
5231 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5232 }, {
5233 .name = "wsr.ibreakenable",
5234 .translate = translate_wsr_ibreakenable,
5235 .test_exceptions = test_exceptions_sr,
5236 .par = (const uint32_t[]){
5237 IBREAKENABLE,
5238 XTENSA_OPTION_DEBUG,
5239 },
5240 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5241 }, {
5242 .name = "wsr.icount",
5243 .translate = translate_wsr_icount,
5244 .test_exceptions = test_exceptions_sr,
5245 .par = (const uint32_t[]){
5246 ICOUNT,
5247 XTENSA_OPTION_DEBUG,
5248 },
5249 .op_flags = XTENSA_OP_PRIVILEGED,
5250 }, {
5251 .name = "wsr.icountlevel",
5252 .translate = translate_wsr_mask,
5253 .test_exceptions = test_exceptions_sr,
5254 .par = (const uint32_t[]){
5255 ICOUNTLEVEL,
5256 XTENSA_OPTION_DEBUG,
5257 0xf,
5258 },
5259 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5260 }, {
5261 .name = "wsr.intclear",
5262 .translate = translate_wsr_intclear,
5263 .test_exceptions = test_exceptions_sr,
5264 .par = (const uint32_t[]){
5265 INTCLEAR,
5266 XTENSA_OPTION_INTERRUPT,
5267 },
5268 .op_flags =
5269 XTENSA_OP_PRIVILEGED |
5270 XTENSA_OP_EXIT_TB_0 |
5271 XTENSA_OP_CHECK_INTERRUPTS,
5272 }, {
5273 .name = "wsr.intenable",
5274 .translate = translate_wsr,
5275 .test_exceptions = test_exceptions_sr,
5276 .par = (const uint32_t[]){
5277 INTENABLE,
5278 XTENSA_OPTION_INTERRUPT,
5279 },
5280 .op_flags =
5281 XTENSA_OP_PRIVILEGED |
5282 XTENSA_OP_EXIT_TB_0 |
5283 XTENSA_OP_CHECK_INTERRUPTS,
5284 }, {
5285 .name = "wsr.interrupt",
5286 .translate = translate_wsr,
5287 .test_exceptions = test_exceptions_sr,
5288 .par = (const uint32_t[]){
5289 INTSET,
5290 XTENSA_OPTION_INTERRUPT,
5291 },
5292 .op_flags =
5293 XTENSA_OP_PRIVILEGED |
5294 XTENSA_OP_EXIT_TB_0 |
5295 XTENSA_OP_CHECK_INTERRUPTS,
5296 }, {
5297 .name = "wsr.intset",
5298 .translate = translate_wsr_intset,
5299 .test_exceptions = test_exceptions_sr,
5300 .par = (const uint32_t[]){
5301 INTSET,
5302 XTENSA_OPTION_INTERRUPT,
5303 },
5304 .op_flags =
5305 XTENSA_OP_PRIVILEGED |
5306 XTENSA_OP_EXIT_TB_0 |
5307 XTENSA_OP_CHECK_INTERRUPTS,
5308 }, {
5309 .name = "wsr.itlbcfg",
5310 .translate = translate_wsr_mask,
5311 .test_exceptions = test_exceptions_sr,
5312 .par = (const uint32_t[]){
5313 ITLBCFG,
5314 XTENSA_OPTION_MMU,
5315 0x01130000,
5316 },
5317 .op_flags = XTENSA_OP_PRIVILEGED,
5318 }, {
5319 .name = "wsr.lbeg",
5320 .translate = translate_wsr,
5321 .test_exceptions = test_exceptions_sr,
5322 .par = (const uint32_t[]){
5323 LBEG,
5324 XTENSA_OPTION_LOOP,
5325 },
5326 .op_flags = XTENSA_OP_EXIT_TB_M1,
5327 }, {
5328 .name = "wsr.lcount",
5329 .translate = translate_wsr,
5330 .test_exceptions = test_exceptions_sr,
5331 .par = (const uint32_t[]){
5332 LCOUNT,
5333 XTENSA_OPTION_LOOP,
5334 },
5335 }, {
5336 .name = "wsr.lend",
5337 .translate = translate_wsr,
5338 .test_exceptions = test_exceptions_sr,
5339 .par = (const uint32_t[]){
5340 LEND,
5341 XTENSA_OPTION_LOOP,
5342 },
5343 .op_flags = XTENSA_OP_EXIT_TB_M1,
5344 }, {
5345 .name = "wsr.litbase",
5346 .translate = translate_wsr_mask,
5347 .test_exceptions = test_exceptions_sr,
5348 .par = (const uint32_t[]){
5349 LITBASE,
5350 XTENSA_OPTION_EXTENDED_L32R,
5351 0xfffff001,
5352 },
5353 .op_flags = XTENSA_OP_EXIT_TB_M1,
5354 }, {
5355 .name = "wsr.m0",
5356 .translate = translate_wsr,
5357 .test_exceptions = test_exceptions_sr,
5358 .par = (const uint32_t[]){
5359 MR,
5360 XTENSA_OPTION_MAC16,
5361 },
5362 }, {
5363 .name = "wsr.m1",
5364 .translate = translate_wsr,
5365 .test_exceptions = test_exceptions_sr,
5366 .par = (const uint32_t[]){
5367 MR + 1,
5368 XTENSA_OPTION_MAC16,
5369 },
5370 }, {
5371 .name = "wsr.m2",
5372 .translate = translate_wsr,
5373 .test_exceptions = test_exceptions_sr,
5374 .par = (const uint32_t[]){
5375 MR + 2,
5376 XTENSA_OPTION_MAC16,
5377 },
5378 }, {
5379 .name = "wsr.m3",
5380 .translate = translate_wsr,
5381 .test_exceptions = test_exceptions_sr,
5382 .par = (const uint32_t[]){
5383 MR + 3,
5384 XTENSA_OPTION_MAC16,
5385 },
5386 }, {
5387 .name = "wsr.memctl",
5388 .translate = translate_wsr_memctl,
5389 .par = (const uint32_t[]){MEMCTL},
5390 .op_flags = XTENSA_OP_PRIVILEGED,
5391 }, {
5392 .name = "wsr.mecr",
5393 .translate = translate_wsr,
5394 .test_exceptions = test_exceptions_sr,
5395 .par = (const uint32_t[]){
5396 MECR,
5397 XTENSA_OPTION_MEMORY_ECC_PARITY,
5398 },
5399 .op_flags = XTENSA_OP_PRIVILEGED,
5400 }, {
5401 .name = "wsr.mepc",
5402 .translate = translate_wsr,
5403 .test_exceptions = test_exceptions_sr,
5404 .par = (const uint32_t[]){
5405 MEPC,
5406 XTENSA_OPTION_MEMORY_ECC_PARITY,
5407 },
5408 .op_flags = XTENSA_OP_PRIVILEGED,
5409 }, {
5410 .name = "wsr.meps",
5411 .translate = translate_wsr,
5412 .test_exceptions = test_exceptions_sr,
5413 .par = (const uint32_t[]){
5414 MEPS,
5415 XTENSA_OPTION_MEMORY_ECC_PARITY,
5416 },
5417 .op_flags = XTENSA_OP_PRIVILEGED,
5418 }, {
5419 .name = "wsr.mesave",
5420 .translate = translate_wsr,
5421 .test_exceptions = test_exceptions_sr,
5422 .par = (const uint32_t[]){
5423 MESAVE,
5424 XTENSA_OPTION_MEMORY_ECC_PARITY,
5425 },
5426 .op_flags = XTENSA_OP_PRIVILEGED,
5427 }, {
5428 .name = "wsr.mesr",
5429 .translate = translate_wsr,
5430 .test_exceptions = test_exceptions_sr,
5431 .par = (const uint32_t[]){
5432 MESR,
5433 XTENSA_OPTION_MEMORY_ECC_PARITY,
5434 },
5435 .op_flags = XTENSA_OP_PRIVILEGED,
5436 }, {
5437 .name = "wsr.mevaddr",
5438 .translate = translate_wsr,
5439 .test_exceptions = test_exceptions_sr,
5440 .par = (const uint32_t[]){
5441 MESR,
5442 XTENSA_OPTION_MEMORY_ECC_PARITY,
5443 },
5444 .op_flags = XTENSA_OP_PRIVILEGED,
5445 }, {
5446 .name = "wsr.misc0",
5447 .translate = translate_wsr,
5448 .test_exceptions = test_exceptions_sr,
5449 .par = (const uint32_t[]){
5450 MISC,
5451 XTENSA_OPTION_MISC_SR,
5452 },
5453 .op_flags = XTENSA_OP_PRIVILEGED,
5454 }, {
5455 .name = "wsr.misc1",
5456 .translate = translate_wsr,
5457 .test_exceptions = test_exceptions_sr,
5458 .par = (const uint32_t[]){
5459 MISC + 1,
5460 XTENSA_OPTION_MISC_SR,
5461 },
5462 .op_flags = XTENSA_OP_PRIVILEGED,
5463 }, {
5464 .name = "wsr.misc2",
5465 .translate = translate_wsr,
5466 .test_exceptions = test_exceptions_sr,
5467 .par = (const uint32_t[]){
5468 MISC + 2,
5469 XTENSA_OPTION_MISC_SR,
5470 },
5471 .op_flags = XTENSA_OP_PRIVILEGED,
5472 }, {
5473 .name = "wsr.misc3",
5474 .translate = translate_wsr,
5475 .test_exceptions = test_exceptions_sr,
5476 .par = (const uint32_t[]){
5477 MISC + 3,
5478 XTENSA_OPTION_MISC_SR,
5479 },
5480 .op_flags = XTENSA_OP_PRIVILEGED,
5481 }, {
5482 .name = "wsr.mmid",
5483 .translate = translate_wsr,
5484 .test_exceptions = test_exceptions_sr,
5485 .par = (const uint32_t[]){
5486 MMID,
5487 XTENSA_OPTION_TRACE_PORT,
5488 },
5489 .op_flags = XTENSA_OP_PRIVILEGED,
5490 }, {
5491 .name = "wsr.mpuenb",
5492 .translate = translate_wsr_mpuenb,
5493 .test_exceptions = test_exceptions_sr,
5494 .par = (const uint32_t[]){
5495 MPUENB,
5496 XTENSA_OPTION_MPU,
5497 },
5498 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5499 }, {
5500 .name = "wsr.prefctl",
5501 .translate = translate_wsr,
5502 .par = (const uint32_t[]){PREFCTL},
5503 }, {
5504 .name = "wsr.prid",
5505 .op_flags = XTENSA_OP_ILL,
5506 }, {
5507 .name = "wsr.ps",
5508 .translate = translate_wsr_ps,
5509 .test_exceptions = test_exceptions_sr,
5510 .par = (const uint32_t[]){
5511 PS,
5512 XTENSA_OPTION_EXCEPTION,
5513 },
5514 .op_flags =
5515 XTENSA_OP_PRIVILEGED |
5516 XTENSA_OP_EXIT_TB_M1 |
5517 XTENSA_OP_CHECK_INTERRUPTS,
5518 }, {
5519 .name = "wsr.ptevaddr",
5520 .translate = translate_wsr_mask,
5521 .test_exceptions = test_exceptions_sr,
5522 .par = (const uint32_t[]){
5523 PTEVADDR,
5524 XTENSA_OPTION_MMU,
5525 0xffc00000,
5526 },
5527 .op_flags = XTENSA_OP_PRIVILEGED,
5528 }, {
5529 .name = "wsr.rasid",
5530 .translate = translate_wsr_rasid,
5531 .test_exceptions = test_exceptions_sr,
5532 .par = (const uint32_t[]){
5533 RASID,
5534 XTENSA_OPTION_MMU,
5535 },
5536 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5537 }, {
5538 .name = "wsr.sar",
5539 .translate = translate_wsr_sar,
5540 .par = (const uint32_t[]){SAR},
5541 }, {
5542 .name = "wsr.scompare1",
5543 .translate = translate_wsr,
5544 .test_exceptions = test_exceptions_sr,
5545 .par = (const uint32_t[]){
5546 SCOMPARE1,
5547 XTENSA_OPTION_CONDITIONAL_STORE,
5548 },
5549 }, {
5550 .name = "wsr.vecbase",
5551 .translate = translate_wsr,
5552 .test_exceptions = test_exceptions_sr,
5553 .par = (const uint32_t[]){
5554 VECBASE,
5555 XTENSA_OPTION_RELOCATABLE_VECTOR,
5556 },
5557 .op_flags = XTENSA_OP_PRIVILEGED,
5558 }, {
5559 .name = "wsr.windowbase",
5560 .translate = translate_wsr_windowbase,
5561 .test_exceptions = test_exceptions_sr,
5562 .par = (const uint32_t[]){
5563 WINDOW_BASE,
5564 XTENSA_OPTION_WINDOWED_REGISTER,
5565 },
5566 .op_flags = XTENSA_OP_PRIVILEGED |
5567 XTENSA_OP_EXIT_TB_M1 |
5568 XTENSA_OP_SYNC_REGISTER_WINDOW,
5569 }, {
5570 .name = "wsr.windowstart",
5571 .translate = translate_wsr_windowstart,
5572 .test_exceptions = test_exceptions_sr,
5573 .par = (const uint32_t[]){
5574 WINDOW_START,
5575 XTENSA_OPTION_WINDOWED_REGISTER,
5576 },
5577 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5578 }, {
5579 .name = "wur.expstate",
5580 .translate = translate_wur,
5581 .par = (const uint32_t[]){EXPSTATE},
5582 }, {
5583 .name = "wur.threadptr",
5584 .translate = translate_wur,
5585 .par = (const uint32_t[]){THREADPTR},
5586 }, {
5587 .name = "xor",
5588 .translate = translate_xor,
5589 }, {
5590 .name = "xorb",
5591 .translate = translate_boolean,
5592 .par = (const uint32_t[]){BOOLEAN_XOR},
5593 }, {
5594 .name = "xsr.176",
5595 .op_flags = XTENSA_OP_ILL,
5596 }, {
5597 .name = "xsr.208",
5598 .op_flags = XTENSA_OP_ILL,
5599 }, {
5600 .name = "xsr.acchi",
5601 .translate = translate_xsr_acchi,
5602 .test_exceptions = test_exceptions_sr,
5603 .par = (const uint32_t[]){
5604 ACCHI,
5605 XTENSA_OPTION_MAC16,
5606 },
5607 }, {
5608 .name = "xsr.acclo",
5609 .translate = translate_xsr,
5610 .test_exceptions = test_exceptions_sr,
5611 .par = (const uint32_t[]){
5612 ACCLO,
5613 XTENSA_OPTION_MAC16,
5614 },
5615 }, {
5616 .name = "xsr.atomctl",
5617 .translate = translate_xsr_mask,
5618 .test_exceptions = test_exceptions_sr,
5619 .par = (const uint32_t[]){
5620 ATOMCTL,
5621 XTENSA_OPTION_ATOMCTL,
5622 0x3f,
5623 },
5624 .op_flags = XTENSA_OP_PRIVILEGED,
5625 }, {
5626 .name = "xsr.br",
5627 .translate = translate_xsr_mask,
5628 .test_exceptions = test_exceptions_sr,
5629 .par = (const uint32_t[]){
5630 BR,
5631 XTENSA_OPTION_BOOLEAN,
5632 0xffff,
5633 },
5634 }, {
5635 .name = "xsr.cacheadrdis",
5636 .translate = translate_xsr_mask,
5637 .test_exceptions = test_exceptions_sr,
5638 .par = (const uint32_t[]){
5639 CACHEADRDIS,
5640 XTENSA_OPTION_MPU,
5641 0xff,
5642 },
5643 .op_flags = XTENSA_OP_PRIVILEGED,
5644 }, {
5645 .name = "xsr.cacheattr",
5646 .translate = translate_xsr,
5647 .test_exceptions = test_exceptions_sr,
5648 .par = (const uint32_t[]){
5649 CACHEATTR,
5650 XTENSA_OPTION_CACHEATTR,
5651 },
5652 .op_flags = XTENSA_OP_PRIVILEGED,
5653 }, {
5654 .name = "xsr.ccompare0",
5655 .translate = translate_xsr_ccompare,
5656 .test_exceptions = test_exceptions_ccompare,
5657 .par = (const uint32_t[]){
5658 CCOMPARE,
5659 XTENSA_OPTION_TIMER_INTERRUPT,
5660 },
5661 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5662 }, {
5663 .name = "xsr.ccompare1",
5664 .translate = translate_xsr_ccompare,
5665 .test_exceptions = test_exceptions_ccompare,
5666 .par = (const uint32_t[]){
5667 CCOMPARE + 1,
5668 XTENSA_OPTION_TIMER_INTERRUPT,
5669 },
5670 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5671 }, {
5672 .name = "xsr.ccompare2",
5673 .translate = translate_xsr_ccompare,
5674 .test_exceptions = test_exceptions_ccompare,
5675 .par = (const uint32_t[]){
5676 CCOMPARE + 2,
5677 XTENSA_OPTION_TIMER_INTERRUPT,
5678 },
5679 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5680 }, {
5681 .name = "xsr.ccount",
5682 .translate = translate_xsr_ccount,
5683 .test_exceptions = test_exceptions_sr,
5684 .par = (const uint32_t[]){
5685 CCOUNT,
5686 XTENSA_OPTION_TIMER_INTERRUPT,
5687 },
5688 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5689 }, {
5690 .name = "xsr.configid0",
5691 .op_flags = XTENSA_OP_ILL,
5692 }, {
5693 .name = "xsr.configid1",
5694 .op_flags = XTENSA_OP_ILL,
5695 }, {
5696 .name = "xsr.cpenable",
5697 .translate = translate_xsr_mask,
5698 .test_exceptions = test_exceptions_sr,
5699 .par = (const uint32_t[]){
5700 CPENABLE,
5701 XTENSA_OPTION_COPROCESSOR,
5702 0xff,
5703 },
5704 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
5705 }, {
5706 .name = "xsr.dbreaka0",
5707 .translate = translate_xsr_dbreaka,
5708 .test_exceptions = test_exceptions_dbreak,
5709 .par = (const uint32_t[]){
5710 DBREAKA,
5711 XTENSA_OPTION_DEBUG,
5712 },
5713 .op_flags = XTENSA_OP_PRIVILEGED,
5714 }, {
5715 .name = "xsr.dbreaka1",
5716 .translate = translate_xsr_dbreaka,
5717 .test_exceptions = test_exceptions_dbreak,
5718 .par = (const uint32_t[]){
5719 DBREAKA + 1,
5720 XTENSA_OPTION_DEBUG,
5721 },
5722 .op_flags = XTENSA_OP_PRIVILEGED,
5723 }, {
5724 .name = "xsr.dbreakc0",
5725 .translate = translate_xsr_dbreakc,
5726 .test_exceptions = test_exceptions_dbreak,
5727 .par = (const uint32_t[]){
5728 DBREAKC,
5729 XTENSA_OPTION_DEBUG,
5730 },
5731 .op_flags = XTENSA_OP_PRIVILEGED,
5732 }, {
5733 .name = "xsr.dbreakc1",
5734 .translate = translate_xsr_dbreakc,
5735 .test_exceptions = test_exceptions_dbreak,
5736 .par = (const uint32_t[]){
5737 DBREAKC + 1,
5738 XTENSA_OPTION_DEBUG,
5739 },
5740 .op_flags = XTENSA_OP_PRIVILEGED,
5741 }, {
5742 .name = "xsr.ddr",
5743 .translate = translate_xsr,
5744 .test_exceptions = test_exceptions_sr,
5745 .par = (const uint32_t[]){
5746 DDR,
5747 XTENSA_OPTION_DEBUG,
5748 },
5749 .op_flags = XTENSA_OP_PRIVILEGED,
5750 }, {
5751 .name = "xsr.debugcause",
5752 .op_flags = XTENSA_OP_ILL,
5753 }, {
5754 .name = "xsr.depc",
5755 .translate = translate_xsr,
5756 .test_exceptions = test_exceptions_sr,
5757 .par = (const uint32_t[]){
5758 DEPC,
5759 XTENSA_OPTION_EXCEPTION,
5760 },
5761 .op_flags = XTENSA_OP_PRIVILEGED,
5762 }, {
5763 .name = "xsr.dtlbcfg",
5764 .translate = translate_xsr_mask,
5765 .test_exceptions = test_exceptions_sr,
5766 .par = (const uint32_t[]){
5767 DTLBCFG,
5768 XTENSA_OPTION_MMU,
5769 0x01130000,
5770 },
5771 .op_flags = XTENSA_OP_PRIVILEGED,
5772 }, {
5773 .name = "xsr.epc1",
5774 .translate = translate_xsr,
5775 .test_exceptions = test_exceptions_sr,
5776 .par = (const uint32_t[]){
5777 EPC1,
5778 XTENSA_OPTION_EXCEPTION,
5779 },
5780 .op_flags = XTENSA_OP_PRIVILEGED,
5781 }, {
5782 .name = "xsr.epc2",
5783 .translate = translate_xsr,
5784 .test_exceptions = test_exceptions_hpi,
5785 .par = (const uint32_t[]){
5786 EPC1 + 1,
5787 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5788 },
5789 .op_flags = XTENSA_OP_PRIVILEGED,
5790 }, {
5791 .name = "xsr.epc3",
5792 .translate = translate_xsr,
5793 .test_exceptions = test_exceptions_hpi,
5794 .par = (const uint32_t[]){
5795 EPC1 + 2,
5796 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5797 },
5798 .op_flags = XTENSA_OP_PRIVILEGED,
5799 }, {
5800 .name = "xsr.epc4",
5801 .translate = translate_xsr,
5802 .test_exceptions = test_exceptions_hpi,
5803 .par = (const uint32_t[]){
5804 EPC1 + 3,
5805 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5806 },
5807 .op_flags = XTENSA_OP_PRIVILEGED,
5808 }, {
5809 .name = "xsr.epc5",
5810 .translate = translate_xsr,
5811 .test_exceptions = test_exceptions_hpi,
5812 .par = (const uint32_t[]){
5813 EPC1 + 4,
5814 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5815 },
5816 .op_flags = XTENSA_OP_PRIVILEGED,
5817 }, {
5818 .name = "xsr.epc6",
5819 .translate = translate_xsr,
5820 .test_exceptions = test_exceptions_hpi,
5821 .par = (const uint32_t[]){
5822 EPC1 + 5,
5823 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5824 },
5825 .op_flags = XTENSA_OP_PRIVILEGED,
5826 }, {
5827 .name = "xsr.epc7",
5828 .translate = translate_xsr,
5829 .test_exceptions = test_exceptions_hpi,
5830 .par = (const uint32_t[]){
5831 EPC1 + 6,
5832 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5833 },
5834 .op_flags = XTENSA_OP_PRIVILEGED,
5835 }, {
5836 .name = "xsr.eps2",
5837 .translate = translate_xsr,
5838 .test_exceptions = test_exceptions_hpi,
5839 .par = (const uint32_t[]){
5840 EPS2,
5841 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5842 },
5843 .op_flags = XTENSA_OP_PRIVILEGED,
5844 }, {
5845 .name = "xsr.eps3",
5846 .translate = translate_xsr,
5847 .test_exceptions = test_exceptions_hpi,
5848 .par = (const uint32_t[]){
5849 EPS2 + 1,
5850 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5851 },
5852 .op_flags = XTENSA_OP_PRIVILEGED,
5853 }, {
5854 .name = "xsr.eps4",
5855 .translate = translate_xsr,
5856 .test_exceptions = test_exceptions_hpi,
5857 .par = (const uint32_t[]){
5858 EPS2 + 2,
5859 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5860 },
5861 .op_flags = XTENSA_OP_PRIVILEGED,
5862 }, {
5863 .name = "xsr.eps5",
5864 .translate = translate_xsr,
5865 .test_exceptions = test_exceptions_hpi,
5866 .par = (const uint32_t[]){
5867 EPS2 + 3,
5868 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5869 },
5870 .op_flags = XTENSA_OP_PRIVILEGED,
5871 }, {
5872 .name = "xsr.eps6",
5873 .translate = translate_xsr,
5874 .test_exceptions = test_exceptions_hpi,
5875 .par = (const uint32_t[]){
5876 EPS2 + 4,
5877 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5878 },
5879 .op_flags = XTENSA_OP_PRIVILEGED,
5880 }, {
5881 .name = "xsr.eps7",
5882 .translate = translate_xsr,
5883 .test_exceptions = test_exceptions_hpi,
5884 .par = (const uint32_t[]){
5885 EPS2 + 5,
5886 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5887 },
5888 .op_flags = XTENSA_OP_PRIVILEGED,
5889 }, {
5890 .name = "xsr.eraccess",
5891 .translate = translate_xsr_mask,
5892 .par = (const uint32_t[]){
5893 ERACCESS,
5894 0,
5895 0xffff,
5896 },
5897 .op_flags = XTENSA_OP_PRIVILEGED,
5898 }, {
5899 .name = "xsr.exccause",
5900 .translate = translate_xsr,
5901 .test_exceptions = test_exceptions_sr,
5902 .par = (const uint32_t[]){
5903 EXCCAUSE,
5904 XTENSA_OPTION_EXCEPTION,
5905 },
5906 .op_flags = XTENSA_OP_PRIVILEGED,
5907 }, {
5908 .name = "xsr.excsave1",
5909 .translate = translate_xsr,
5910 .test_exceptions = test_exceptions_sr,
5911 .par = (const uint32_t[]){
5912 EXCSAVE1,
5913 XTENSA_OPTION_EXCEPTION,
5914 },
5915 .op_flags = XTENSA_OP_PRIVILEGED,
5916 }, {
5917 .name = "xsr.excsave2",
5918 .translate = translate_xsr,
5919 .test_exceptions = test_exceptions_hpi,
5920 .par = (const uint32_t[]){
5921 EXCSAVE1 + 1,
5922 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5923 },
5924 .op_flags = XTENSA_OP_PRIVILEGED,
5925 }, {
5926 .name = "xsr.excsave3",
5927 .translate = translate_xsr,
5928 .test_exceptions = test_exceptions_hpi,
5929 .par = (const uint32_t[]){
5930 EXCSAVE1 + 2,
5931 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5932 },
5933 .op_flags = XTENSA_OP_PRIVILEGED,
5934 }, {
5935 .name = "xsr.excsave4",
5936 .translate = translate_xsr,
5937 .test_exceptions = test_exceptions_hpi,
5938 .par = (const uint32_t[]){
5939 EXCSAVE1 + 3,
5940 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5941 },
5942 .op_flags = XTENSA_OP_PRIVILEGED,
5943 }, {
5944 .name = "xsr.excsave5",
5945 .translate = translate_xsr,
5946 .test_exceptions = test_exceptions_hpi,
5947 .par = (const uint32_t[]){
5948 EXCSAVE1 + 4,
5949 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5950 },
5951 .op_flags = XTENSA_OP_PRIVILEGED,
5952 }, {
5953 .name = "xsr.excsave6",
5954 .translate = translate_xsr,
5955 .test_exceptions = test_exceptions_hpi,
5956 .par = (const uint32_t[]){
5957 EXCSAVE1 + 5,
5958 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5959 },
5960 .op_flags = XTENSA_OP_PRIVILEGED,
5961 }, {
5962 .name = "xsr.excsave7",
5963 .translate = translate_xsr,
5964 .test_exceptions = test_exceptions_hpi,
5965 .par = (const uint32_t[]){
5966 EXCSAVE1 + 6,
5967 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
5968 },
5969 .op_flags = XTENSA_OP_PRIVILEGED,
5970 }, {
5971 .name = "xsr.excvaddr",
5972 .translate = translate_xsr,
5973 .test_exceptions = test_exceptions_sr,
5974 .par = (const uint32_t[]){
5975 EXCVADDR,
5976 XTENSA_OPTION_EXCEPTION,
5977 },
5978 .op_flags = XTENSA_OP_PRIVILEGED,
5979 }, {
5980 .name = "xsr.ibreaka0",
5981 .translate = translate_xsr_ibreaka,
5982 .test_exceptions = test_exceptions_ibreak,
5983 .par = (const uint32_t[]){
5984 IBREAKA,
5985 XTENSA_OPTION_DEBUG,
5986 },
5987 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5988 }, {
5989 .name = "xsr.ibreaka1",
5990 .translate = translate_xsr_ibreaka,
5991 .test_exceptions = test_exceptions_ibreak,
5992 .par = (const uint32_t[]){
5993 IBREAKA + 1,
5994 XTENSA_OPTION_DEBUG,
5995 },
5996 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
5997 }, {
5998 .name = "xsr.ibreakenable",
5999 .translate = translate_xsr_ibreakenable,
6000 .test_exceptions = test_exceptions_sr,
6001 .par = (const uint32_t[]){
6002 IBREAKENABLE,
6003 XTENSA_OPTION_DEBUG,
6004 },
6005 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0,
6006 }, {
6007 .name = "xsr.icount",
6008 .translate = translate_xsr_icount,
6009 .test_exceptions = test_exceptions_sr,
6010 .par = (const uint32_t[]){
6011 ICOUNT,
6012 XTENSA_OPTION_DEBUG,
6013 },
6014 .op_flags = XTENSA_OP_PRIVILEGED,
6015 }, {
6016 .name = "xsr.icountlevel",
6017 .translate = translate_xsr_mask,
6018 .test_exceptions = test_exceptions_sr,
6019 .par = (const uint32_t[]){
6020 ICOUNTLEVEL,
6021 XTENSA_OPTION_DEBUG,
6022 0xf,
6023 },
6024 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6025 }, {
6026 .name = "xsr.intclear",
6027 .op_flags = XTENSA_OP_ILL,
6028 }, {
6029 .name = "xsr.intenable",
6030 .translate = translate_xsr,
6031 .test_exceptions = test_exceptions_sr,
6032 .par = (const uint32_t[]){
6033 INTENABLE,
6034 XTENSA_OPTION_INTERRUPT,
6035 },
6036 .op_flags =
6037 XTENSA_OP_PRIVILEGED |
6038 XTENSA_OP_EXIT_TB_0 |
6039 XTENSA_OP_CHECK_INTERRUPTS,
6040 }, {
6041 .name = "xsr.interrupt",
6042 .op_flags = XTENSA_OP_ILL,
6043 }, {
6044 .name = "xsr.intset",
6045 .op_flags = XTENSA_OP_ILL,
6046 }, {
6047 .name = "xsr.itlbcfg",
6048 .translate = translate_xsr_mask,
6049 .test_exceptions = test_exceptions_sr,
6050 .par = (const uint32_t[]){
6051 ITLBCFG,
6052 XTENSA_OPTION_MMU,
6053 0x01130000,
6054 },
6055 .op_flags = XTENSA_OP_PRIVILEGED,
6056 }, {
6057 .name = "xsr.lbeg",
6058 .translate = translate_xsr,
6059 .test_exceptions = test_exceptions_sr,
6060 .par = (const uint32_t[]){
6061 LBEG,
6062 XTENSA_OPTION_LOOP,
6063 },
6064 .op_flags = XTENSA_OP_EXIT_TB_M1,
6065 }, {
6066 .name = "xsr.lcount",
6067 .translate = translate_xsr,
6068 .test_exceptions = test_exceptions_sr,
6069 .par = (const uint32_t[]){
6070 LCOUNT,
6071 XTENSA_OPTION_LOOP,
6072 },
6073 }, {
6074 .name = "xsr.lend",
6075 .translate = translate_xsr,
6076 .test_exceptions = test_exceptions_sr,
6077 .par = (const uint32_t[]){
6078 LEND,
6079 XTENSA_OPTION_LOOP,
6080 },
6081 .op_flags = XTENSA_OP_EXIT_TB_M1,
6082 }, {
6083 .name = "xsr.litbase",
6084 .translate = translate_xsr_mask,
6085 .test_exceptions = test_exceptions_sr,
6086 .par = (const uint32_t[]){
6087 LITBASE,
6088 XTENSA_OPTION_EXTENDED_L32R,
6089 0xfffff001,
6090 },
6091 .op_flags = XTENSA_OP_EXIT_TB_M1,
6092 }, {
6093 .name = "xsr.m0",
6094 .translate = translate_xsr,
6095 .test_exceptions = test_exceptions_sr,
6096 .par = (const uint32_t[]){
6097 MR,
6098 XTENSA_OPTION_MAC16,
6099 },
6100 }, {
6101 .name = "xsr.m1",
6102 .translate = translate_xsr,
6103 .test_exceptions = test_exceptions_sr,
6104 .par = (const uint32_t[]){
6105 MR + 1,
6106 XTENSA_OPTION_MAC16,
6107 },
6108 }, {
6109 .name = "xsr.m2",
6110 .translate = translate_xsr,
6111 .test_exceptions = test_exceptions_sr,
6112 .par = (const uint32_t[]){
6113 MR + 2,
6114 XTENSA_OPTION_MAC16,
6115 },
6116 }, {
6117 .name = "xsr.m3",
6118 .translate = translate_xsr,
6119 .test_exceptions = test_exceptions_sr,
6120 .par = (const uint32_t[]){
6121 MR + 3,
6122 XTENSA_OPTION_MAC16,
6123 },
6124 }, {
6125 .name = "xsr.memctl",
6126 .translate = translate_xsr_memctl,
6127 .par = (const uint32_t[]){MEMCTL},
6128 .op_flags = XTENSA_OP_PRIVILEGED,
6129 }, {
6130 .name = "xsr.mecr",
6131 .translate = translate_xsr,
6132 .test_exceptions = test_exceptions_sr,
6133 .par = (const uint32_t[]){
6134 MECR,
6135 XTENSA_OPTION_MEMORY_ECC_PARITY,
6136 },
6137 .op_flags = XTENSA_OP_PRIVILEGED,
6138 }, {
6139 .name = "xsr.mepc",
6140 .translate = translate_xsr,
6141 .test_exceptions = test_exceptions_sr,
6142 .par = (const uint32_t[]){
6143 MEPC,
6144 XTENSA_OPTION_MEMORY_ECC_PARITY,
6145 },
6146 .op_flags = XTENSA_OP_PRIVILEGED,
6147 }, {
6148 .name = "xsr.meps",
6149 .translate = translate_xsr,
6150 .test_exceptions = test_exceptions_sr,
6151 .par = (const uint32_t[]){
6152 MEPS,
6153 XTENSA_OPTION_MEMORY_ECC_PARITY,
6154 },
6155 .op_flags = XTENSA_OP_PRIVILEGED,
6156 }, {
6157 .name = "xsr.mesave",
6158 .translate = translate_xsr,
6159 .test_exceptions = test_exceptions_sr,
6160 .par = (const uint32_t[]){
6161 MESAVE,
6162 XTENSA_OPTION_MEMORY_ECC_PARITY,
6163 },
6164 .op_flags = XTENSA_OP_PRIVILEGED,
6165 }, {
6166 .name = "xsr.mesr",
6167 .translate = translate_xsr,
6168 .test_exceptions = test_exceptions_sr,
6169 .par = (const uint32_t[]){
6170 MESR,
6171 XTENSA_OPTION_MEMORY_ECC_PARITY,
6172 },
6173 .op_flags = XTENSA_OP_PRIVILEGED,
6174 }, {
6175 .name = "xsr.mevaddr",
6176 .translate = translate_xsr,
6177 .test_exceptions = test_exceptions_sr,
6178 .par = (const uint32_t[]){
6179 MESR,
6180 XTENSA_OPTION_MEMORY_ECC_PARITY,
6181 },
6182 .op_flags = XTENSA_OP_PRIVILEGED,
6183 }, {
6184 .name = "xsr.misc0",
6185 .translate = translate_xsr,
6186 .test_exceptions = test_exceptions_sr,
6187 .par = (const uint32_t[]){
6188 MISC,
6189 XTENSA_OPTION_MISC_SR,
6190 },
6191 .op_flags = XTENSA_OP_PRIVILEGED,
6192 }, {
6193 .name = "xsr.misc1",
6194 .translate = translate_xsr,
6195 .test_exceptions = test_exceptions_sr,
6196 .par = (const uint32_t[]){
6197 MISC + 1,
6198 XTENSA_OPTION_MISC_SR,
6199 },
6200 .op_flags = XTENSA_OP_PRIVILEGED,
6201 }, {
6202 .name = "xsr.misc2",
6203 .translate = translate_xsr,
6204 .test_exceptions = test_exceptions_sr,
6205 .par = (const uint32_t[]){
6206 MISC + 2,
6207 XTENSA_OPTION_MISC_SR,
6208 },
6209 .op_flags = XTENSA_OP_PRIVILEGED,
6210 }, {
6211 .name = "xsr.misc3",
6212 .translate = translate_xsr,
6213 .test_exceptions = test_exceptions_sr,
6214 .par = (const uint32_t[]){
6215 MISC + 3,
6216 XTENSA_OPTION_MISC_SR,
6217 },
6218 .op_flags = XTENSA_OP_PRIVILEGED,
6219 }, {
6220 .name = "xsr.mpuenb",
6221 .translate = translate_xsr_mpuenb,
6222 .test_exceptions = test_exceptions_sr,
6223 .par = (const uint32_t[]){
6224 MPUENB,
6225 XTENSA_OPTION_MPU,
6226 },
6227 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6228 }, {
6229 .name = "xsr.prefctl",
6230 .translate = translate_xsr,
6231 .par = (const uint32_t[]){PREFCTL},
6232 }, {
6233 .name = "xsr.prid",
6234 .op_flags = XTENSA_OP_ILL,
6235 }, {
6236 .name = "xsr.ps",
6237 .translate = translate_xsr_ps,
6238 .test_exceptions = test_exceptions_sr,
6239 .par = (const uint32_t[]){
6240 PS,
6241 XTENSA_OPTION_EXCEPTION,
6242 },
6243 .op_flags =
6244 XTENSA_OP_PRIVILEGED |
6245 XTENSA_OP_EXIT_TB_M1 |
6246 XTENSA_OP_CHECK_INTERRUPTS,
6247 }, {
6248 .name = "xsr.ptevaddr",
6249 .translate = translate_xsr_mask,
6250 .test_exceptions = test_exceptions_sr,
6251 .par = (const uint32_t[]){
6252 PTEVADDR,
6253 XTENSA_OPTION_MMU,
6254 0xffc00000,
6255 },
6256 .op_flags = XTENSA_OP_PRIVILEGED,
6257 }, {
6258 .name = "xsr.rasid",
6259 .translate = translate_xsr_rasid,
6260 .test_exceptions = test_exceptions_sr,
6261 .par = (const uint32_t[]){
6262 RASID,
6263 XTENSA_OPTION_MMU,
6264 },
6265 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6266 }, {
6267 .name = "xsr.sar",
6268 .translate = translate_xsr_sar,
6269 .par = (const uint32_t[]){SAR},
6270 }, {
6271 .name = "xsr.scompare1",
6272 .translate = translate_xsr,
6273 .test_exceptions = test_exceptions_sr,
6274 .par = (const uint32_t[]){
6275 SCOMPARE1,
6276 XTENSA_OPTION_CONDITIONAL_STORE,
6277 },
6278 }, {
6279 .name = "xsr.vecbase",
6280 .translate = translate_xsr,
6281 .test_exceptions = test_exceptions_sr,
6282 .par = (const uint32_t[]){
6283 VECBASE,
6284 XTENSA_OPTION_RELOCATABLE_VECTOR,
6285 },
6286 .op_flags = XTENSA_OP_PRIVILEGED,
6287 }, {
6288 .name = "xsr.windowbase",
6289 .translate = translate_xsr_windowbase,
6290 .test_exceptions = test_exceptions_sr,
6291 .par = (const uint32_t[]){
6292 WINDOW_BASE,
6293 XTENSA_OPTION_WINDOWED_REGISTER,
6294 },
6295 .op_flags = XTENSA_OP_PRIVILEGED |
6296 XTENSA_OP_EXIT_TB_M1 |
6297 XTENSA_OP_SYNC_REGISTER_WINDOW,
6298 }, {
6299 .name = "xsr.windowstart",
6300 .translate = translate_xsr_windowstart,
6301 .test_exceptions = test_exceptions_sr,
6302 .par = (const uint32_t[]){
6303 WINDOW_START,
6304 XTENSA_OPTION_WINDOWED_REGISTER,
6305 },
6306 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
6307 },
6308 };
6309
6310 const XtensaOpcodeTranslators xtensa_core_opcodes = {
6311 .num_opcodes = ARRAY_SIZE(core_ops),
6312 .opcode = core_ops,
6313 };
6314
6315
6316 static inline void get_f32_o1_i3(const OpcodeArg *arg, OpcodeArg *arg32,
6317 int o0, int i0, int i1, int i2)
6318 {
6319 if ((i0 >= 0 && arg[i0].num_bits == 64) ||
6320 (o0 >= 0 && arg[o0].num_bits == 64)) {
6321 if (o0 >= 0) {
6322 arg32[o0].out = tcg_temp_new_i32();
6323 }
6324 if (i0 >= 0) {
6325 arg32[i0].in = tcg_temp_new_i32();
6326 tcg_gen_extrl_i64_i32(arg32[i0].in, arg[i0].in);
6327 }
6328 if (i1 >= 0) {
6329 arg32[i1].in = tcg_temp_new_i32();
6330 tcg_gen_extrl_i64_i32(arg32[i1].in, arg[i1].in);
6331 }
6332 if (i2 >= 0) {
6333 arg32[i2].in = tcg_temp_new_i32();
6334 tcg_gen_extrl_i64_i32(arg32[i2].in, arg[i2].in);
6335 }
6336 } else {
6337 if (o0 >= 0) {
6338 arg32[o0].out = arg[o0].out;
6339 }
6340 if (i0 >= 0) {
6341 arg32[i0].in = arg[i0].in;
6342 }
6343 if (i1 >= 0) {
6344 arg32[i1].in = arg[i1].in;
6345 }
6346 if (i2 >= 0) {
6347 arg32[i2].in = arg[i2].in;
6348 }
6349 }
6350 }
6351
6352 static inline void put_f32_o1_i3(const OpcodeArg *arg, const OpcodeArg *arg32,
6353 int o0, int i0, int i1, int i2)
6354 {
6355 if ((i0 >= 0 && arg[i0].num_bits == 64) ||
6356 (o0 >= 0 && arg[o0].num_bits == 64)) {
6357 if (o0 >= 0) {
6358 tcg_gen_extu_i32_i64(arg[o0].out, arg32[o0].out);
6359 tcg_temp_free_i32(arg32[o0].out);
6360 }
6361 if (i0 >= 0) {
6362 tcg_temp_free_i32(arg32[i0].in);
6363 }
6364 if (i1 >= 0) {
6365 tcg_temp_free_i32(arg32[i1].in);
6366 }
6367 if (i2 >= 0) {
6368 tcg_temp_free_i32(arg32[i2].in);
6369 }
6370 }
6371 }
6372
6373 static inline void get_f32_o1_i2(const OpcodeArg *arg, OpcodeArg *arg32,
6374 int o0, int i0, int i1)
6375 {
6376 get_f32_o1_i3(arg, arg32, o0, i0, i1, -1);
6377 }
6378
6379 static inline void put_f32_o1_i2(const OpcodeArg *arg, const OpcodeArg *arg32,
6380 int o0, int i0, int i1)
6381 {
6382 put_f32_o1_i3(arg, arg32, o0, i0, i1, -1);
6383 }
6384
6385 static inline void get_f32_o1_i1(const OpcodeArg *arg, OpcodeArg *arg32,
6386 int o0, int i0)
6387 {
6388 get_f32_o1_i2(arg, arg32, o0, i0, -1);
6389 }
6390
6391 static inline void put_f32_o1_i1(const OpcodeArg *arg, const OpcodeArg *arg32,
6392 int o0, int i0)
6393 {
6394 put_f32_o1_i2(arg, arg32, o0, i0, -1);
6395 }
6396
6397 static inline void get_f32_o1(const OpcodeArg *arg, OpcodeArg *arg32,
6398 int o0)
6399 {
6400 get_f32_o1_i1(arg, arg32, o0, -1);
6401 }
6402
6403 static inline void put_f32_o1(const OpcodeArg *arg, const OpcodeArg *arg32,
6404 int o0)
6405 {
6406 put_f32_o1_i1(arg, arg32, o0, -1);
6407 }
6408
6409 static inline void get_f32_i2(const OpcodeArg *arg, OpcodeArg *arg32,
6410 int i0, int i1)
6411 {
6412 get_f32_o1_i2(arg, arg32, -1, i0, i1);
6413 }
6414
6415 static inline void put_f32_i2(const OpcodeArg *arg, const OpcodeArg *arg32,
6416 int i0, int i1)
6417 {
6418 put_f32_o1_i2(arg, arg32, -1, i0, i1);
6419 }
6420
6421 static inline void get_f32_i1(const OpcodeArg *arg, OpcodeArg *arg32,
6422 int i0)
6423 {
6424 get_f32_i2(arg, arg32, i0, -1);
6425 }
6426
6427 static inline void put_f32_i1(const OpcodeArg *arg, const OpcodeArg *arg32,
6428 int i0)
6429 {
6430 put_f32_i2(arg, arg32, i0, -1);
6431 }
6432
6433
6434 static void translate_abs_d(DisasContext *dc, const OpcodeArg arg[],
6435 const uint32_t par[])
6436 {
6437 gen_helper_abs_d(arg[0].out, arg[1].in);
6438 }
6439
6440 static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[],
6441 const uint32_t par[])
6442 {
6443 OpcodeArg arg32[2];
6444
6445 get_f32_o1_i1(arg, arg32, 0, 1);
6446 gen_helper_abs_s(arg32[0].out, arg32[1].in);
6447 put_f32_o1_i1(arg, arg32, 0, 1);
6448 }
6449
6450 static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[],
6451 const uint32_t par[])
6452 {
6453 gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
6454 arg[1].in, arg[2].in);
6455 }
6456
6457 enum {
6458 COMPARE_UN,
6459 COMPARE_OEQ,
6460 COMPARE_UEQ,
6461 COMPARE_OLT,
6462 COMPARE_ULT,
6463 COMPARE_OLE,
6464 COMPARE_ULE,
6465 };
6466
6467 static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[],
6468 const uint32_t par[])
6469 {
6470 static void (* const helper[])(TCGv_i32 res, TCGv_env env,
6471 TCGv_i64 s, TCGv_i64 t) = {
6472 [COMPARE_UN] = gen_helper_un_d,
6473 [COMPARE_OEQ] = gen_helper_oeq_d,
6474 [COMPARE_UEQ] = gen_helper_ueq_d,
6475 [COMPARE_OLT] = gen_helper_olt_d,
6476 [COMPARE_ULT] = gen_helper_ult_d,
6477 [COMPARE_OLE] = gen_helper_ole_d,
6478 [COMPARE_ULE] = gen_helper_ule_d,
6479 };
6480 TCGv_i32 zero = tcg_const_i32(0);
6481 TCGv_i32 res = tcg_temp_new_i32();
6482 TCGv_i32 set_br = tcg_temp_new_i32();
6483 TCGv_i32 clr_br = tcg_temp_new_i32();
6484
6485 tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm);
6486 tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
6487
6488 helper[par[0]](res, cpu_env, arg[1].in, arg[2].in);
6489 tcg_gen_movcond_i32(TCG_COND_NE,
6490 arg[0].out, res, zero,
6491 set_br, clr_br);
6492 tcg_temp_free(zero);
6493 tcg_temp_free(res);
6494 tcg_temp_free(set_br);
6495 tcg_temp_free(clr_br);
6496 }
6497
6498 static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[],
6499 const uint32_t par[])
6500 {
6501 static void (* const helper[])(TCGv_i32 res, TCGv_env env,
6502 TCGv_i32 s, TCGv_i32 t) = {
6503 [COMPARE_UN] = gen_helper_un_s,
6504 [COMPARE_OEQ] = gen_helper_oeq_s,
6505 [COMPARE_UEQ] = gen_helper_ueq_s,
6506 [COMPARE_OLT] = gen_helper_olt_s,
6507 [COMPARE_ULT] = gen_helper_ult_s,
6508 [COMPARE_OLE] = gen_helper_ole_s,
6509 [COMPARE_ULE] = gen_helper_ule_s,
6510 };
6511 OpcodeArg arg32[3];
6512 TCGv_i32 zero = tcg_const_i32(0);
6513 TCGv_i32 res = tcg_temp_new_i32();
6514 TCGv_i32 set_br = tcg_temp_new_i32();
6515 TCGv_i32 clr_br = tcg_temp_new_i32();
6516
6517 tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm);
6518 tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm));
6519
6520 get_f32_i2(arg, arg32, 1, 2);
6521 helper[par[0]](res, cpu_env, arg32[1].in, arg32[2].in);
6522 tcg_gen_movcond_i32(TCG_COND_NE,
6523 arg[0].out, res, zero,
6524 set_br, clr_br);
6525 put_f32_i2(arg, arg32, 1, 2);
6526 tcg_temp_free(zero);
6527 tcg_temp_free(res);
6528 tcg_temp_free(set_br);
6529 tcg_temp_free(clr_br);
6530 }
6531
6532 static void translate_const_d(DisasContext *dc, const OpcodeArg arg[],
6533 const uint32_t par[])
6534 {
6535 static const uint64_t v[] = {
6536 UINT64_C(0x0000000000000000),
6537 UINT64_C(0x3ff0000000000000),
6538 UINT64_C(0x4000000000000000),
6539 UINT64_C(0x3fe0000000000000),
6540 };
6541
6542 tcg_gen_movi_i64(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]);
6543 if (arg[1].imm >= ARRAY_SIZE(v)) {
6544 qemu_log_mask(LOG_GUEST_ERROR,
6545 "const.d f%d, #%d, immediate value is reserved\n",
6546 arg[0].imm, arg[1].imm);
6547 }
6548 }
6549
6550 static void translate_const_s(DisasContext *dc, const OpcodeArg arg[],
6551 const uint32_t par[])
6552 {
6553 static const uint32_t v[] = {
6554 0x00000000,
6555 0x3f800000,
6556 0x40000000,
6557 0x3f000000,
6558 };
6559
6560 if (arg[0].num_bits == 32) {
6561 tcg_gen_movi_i32(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]);
6562 } else {
6563 tcg_gen_movi_i64(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]);
6564 }
6565 if (arg[1].imm >= ARRAY_SIZE(v)) {
6566 qemu_log_mask(LOG_GUEST_ERROR,
6567 "const.s f%d, #%d, immediate value is reserved\n",
6568 arg[0].imm, arg[1].imm);
6569 }
6570 }
6571
6572 static void translate_float_d(DisasContext *dc, const OpcodeArg arg[],
6573 const uint32_t par[])
6574 {
6575 TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
6576
6577 if (par[0]) {
6578 gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale);
6579 } else {
6580 gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale);
6581 }
6582 tcg_temp_free(scale);
6583 }
6584
6585 static void translate_float_s(DisasContext *dc, const OpcodeArg arg[],
6586 const uint32_t par[])
6587 {
6588 TCGv_i32 scale = tcg_const_i32(-arg[2].imm);
6589 OpcodeArg arg32[1];
6590
6591 get_f32_o1(arg, arg32, 0);
6592 if (par[0]) {
6593 gen_helper_uitof_s(arg32[0].out, cpu_env, arg[1].in, scale);
6594 } else {
6595 gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale);
6596 }
6597 put_f32_o1(arg, arg32, 0);
6598 tcg_temp_free(scale);
6599 }
6600
6601 static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[],
6602 const uint32_t par[])
6603 {
6604 TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
6605 TCGv_i32 scale = tcg_const_i32(arg[2].imm);
6606
6607 if (par[1]) {
6608 gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in,
6609 rounding_mode, scale);
6610 } else {
6611 gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in,
6612 rounding_mode, scale);
6613 }
6614 tcg_temp_free(rounding_mode);
6615 tcg_temp_free(scale);
6616 }
6617
6618 static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[],
6619 const uint32_t par[])
6620 {
6621 TCGv_i32 rounding_mode = tcg_const_i32(par[0]);
6622 TCGv_i32 scale = tcg_const_i32(arg[2].imm);
6623 OpcodeArg arg32[2];
6624
6625 get_f32_i1(arg, arg32, 1);
6626 if (par[1]) {
6627 gen_helper_ftoui_s(arg[0].out, cpu_env, arg32[1].in,
6628 rounding_mode, scale);
6629 } else {
6630 gen_helper_ftoi_s(arg[0].out, cpu_env, arg32[1].in,
6631 rounding_mode, scale);
6632 }
6633 put_f32_i1(arg, arg32, 1);
6634 tcg_temp_free(rounding_mode);
6635 tcg_temp_free(scale);
6636 }
6637
6638 static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[],
6639 const uint32_t par[])
6640 {
6641 TCGv_i32 addr = tcg_temp_new_i32();
6642
6643 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
6644 gen_load_store_alignment(dc, 2, addr, false);
6645 if (par[0]) {
6646 tcg_gen_qemu_st32(arg[0].in, addr, dc->cring);
6647 } else {
6648 tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring);
6649 }
6650 if (par[1]) {
6651 tcg_gen_mov_i32(arg[1].out, addr);
6652 }
6653 tcg_temp_free(addr);
6654 }
6655
6656 static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[],
6657 const uint32_t par[])
6658 {
6659 TCGv_i32 addr = tcg_temp_new_i32();
6660
6661 tcg_gen_add_i32(addr, arg[1].in, arg[2].in);
6662 gen_load_store_alignment(dc, 2, addr, false);
6663 if (par[0]) {
6664 tcg_gen_qemu_st32(arg[0].in, addr, dc->cring);
6665 } else {
6666 tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring);
6667 }
6668 if (par[1]) {
6669 tcg_gen_mov_i32(arg[1].out, addr);
6670 }
6671 tcg_temp_free(addr);
6672 }
6673
6674 static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[],
6675 const uint32_t par[])
6676 {
6677 gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
6678 arg[0].in, arg[1].in, arg[2].in);
6679 }
6680
6681 static void translate_mov_d(DisasContext *dc, const OpcodeArg arg[],
6682 const uint32_t par[])
6683 {
6684 tcg_gen_mov_i64(arg[0].out, arg[1].in);
6685 }
6686
6687 static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[],
6688 const uint32_t par[])
6689 {
6690 if (arg[0].num_bits == 32) {
6691 tcg_gen_mov_i32(arg[0].out, arg[1].in);
6692 } else {
6693 tcg_gen_mov_i64(arg[0].out, arg[1].in);
6694 }
6695 }
6696
6697 static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[],
6698 const uint32_t par[])
6699 {
6700 TCGv_i64 zero = tcg_const_i64(0);
6701 TCGv_i64 arg2 = tcg_temp_new_i64();
6702
6703 tcg_gen_ext_i32_i64(arg2, arg[2].in);
6704 tcg_gen_movcond_i64(par[0], arg[0].out,
6705 arg2, zero,
6706 arg[1].in, arg[0].in);
6707 tcg_temp_free_i64(zero);
6708 tcg_temp_free_i64(arg2);
6709 }
6710
6711 static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[],
6712 const uint32_t par[])
6713 {
6714 if (arg[0].num_bits == 32) {
6715 TCGv_i32 zero = tcg_const_i32(0);
6716
6717 tcg_gen_movcond_i32(par[0], arg[0].out,
6718 arg[2].in, zero,
6719 arg[1].in, arg[0].in);
6720 tcg_temp_free(zero);
6721 } else {
6722 translate_movcond_d(dc, arg, par);
6723 }
6724 }
6725
6726 static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[],
6727 const uint32_t par[])
6728 {
6729 TCGv_i64 zero = tcg_const_i64(0);
6730 TCGv_i32 tmp1 = tcg_temp_new_i32();
6731 TCGv_i64 tmp2 = tcg_temp_new_i64();
6732
6733 tcg_gen_andi_i32(tmp1, arg[2].in, 1 << arg[2].imm);
6734 tcg_gen_extu_i32_i64(tmp2, tmp1);
6735 tcg_gen_movcond_i64(par[0],
6736 arg[0].out, tmp2, zero,
6737 arg[1].in, arg[0].in);
6738 tcg_temp_free_i64(zero);
6739 tcg_temp_free_i32(tmp1);
6740 tcg_temp_free_i64(tmp2);
6741 }
6742
6743 static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[],
6744 const uint32_t par[])
6745 {
6746 if (arg[0].num_bits == 32) {
6747 TCGv_i32 zero = tcg_const_i32(0);
6748 TCGv_i32 tmp = tcg_temp_new_i32();
6749
6750 tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm);
6751 tcg_gen_movcond_i32(par[0],
6752 arg[0].out, tmp, zero,
6753 arg[1].in, arg[0].in);
6754 tcg_temp_free(tmp);
6755 tcg_temp_free(zero);
6756 } else {
6757 translate_movp_d(dc, arg, par);
6758 }
6759 }
6760
6761 static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[],
6762 const uint32_t par[])
6763 {
6764 gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
6765 arg[1].in, arg[2].in);
6766 }
6767
6768 static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[],
6769 const uint32_t par[])
6770 {
6771 gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
6772 arg[0].in, arg[1].in, arg[2].in);
6773 }
6774
6775 static void translate_neg_d(DisasContext *dc, const OpcodeArg arg[],
6776 const uint32_t par[])
6777 {
6778 gen_helper_neg_d(arg[0].out, arg[1].in);
6779 }
6780
6781 static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[],
6782 const uint32_t par[])
6783 {
6784 OpcodeArg arg32[2];
6785
6786 get_f32_o1_i1(arg, arg32, 0, 1);
6787 gen_helper_neg_s(arg32[0].out, arg32[1].in);
6788 put_f32_o1_i1(arg, arg32, 0, 1);
6789 }
6790
6791 static void translate_rfr_d(DisasContext *dc, const OpcodeArg arg[],
6792 const uint32_t par[])
6793 {
6794 tcg_gen_extrh_i64_i32(arg[0].out, arg[1].in);
6795 }
6796
6797 static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[],
6798 const uint32_t par[])
6799 {
6800 if (arg[1].num_bits == 32) {
6801 tcg_gen_mov_i32(arg[0].out, arg[1].in);
6802 } else {
6803 tcg_gen_extrl_i64_i32(arg[0].out, arg[1].in);
6804 }
6805 }
6806
6807 static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[],
6808 const uint32_t par[])
6809 {
6810 gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
6811 arg[1].in, arg[2].in);
6812 }
6813
6814 static void translate_wfr_d(DisasContext *dc, const OpcodeArg arg[],
6815 const uint32_t par[])
6816 {
6817 tcg_gen_concat_i32_i64(arg[0].out, arg[2].in, arg[1].in);
6818 }
6819
6820 static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[],
6821 const uint32_t par[])
6822 {
6823 if (arg[0].num_bits == 32) {
6824 tcg_gen_mov_i32(arg[0].out, arg[1].in);
6825 } else {
6826 tcg_gen_ext_i32_i64(arg[0].out, arg[1].in);
6827 }
6828 }
6829
6830 static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[],
6831 const uint32_t par[])
6832 {
6833 gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in);
6834 }
6835
6836 static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[],
6837 const uint32_t par[])
6838 {
6839 tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80);
6840 }
6841
6842 static const XtensaOpcodeOps fpu2000_ops[] = {
6843 {
6844 .name = "abs.s",
6845 .translate = translate_abs_s,
6846 .coprocessor = 0x1,
6847 }, {
6848 .name = "add.s",
6849 .translate = translate_fpu2k_add_s,
6850 .coprocessor = 0x1,
6851 }, {
6852 .name = "ceil.s",
6853 .translate = translate_ftoi_s,
6854 .par = (const uint32_t[]){float_round_up, false},
6855 .coprocessor = 0x1,
6856 }, {
6857 .name = "float.s",
6858 .translate = translate_float_s,
6859 .par = (const uint32_t[]){false},
6860 .coprocessor = 0x1,
6861 }, {
6862 .name = "floor.s",
6863 .translate = translate_ftoi_s,
6864 .par = (const uint32_t[]){float_round_down, false},
6865 .coprocessor = 0x1,
6866 }, {
6867 .name = "lsi",
6868 .translate = translate_ldsti,
6869 .par = (const uint32_t[]){false, false},
6870 .op_flags = XTENSA_OP_LOAD,
6871 .coprocessor = 0x1,
6872 }, {
6873 .name = "lsiu",
6874 .translate = translate_ldsti,
6875 .par = (const uint32_t[]){false, true},
6876 .op_flags = XTENSA_OP_LOAD,
6877 .coprocessor = 0x1,
6878 }, {
6879 .name = "lsx",
6880 .translate = translate_ldstx,
6881 .par = (const uint32_t[]){false, false},
6882 .op_flags = XTENSA_OP_LOAD,
6883 .coprocessor = 0x1,
6884 }, {
6885 .name = "lsxu",
6886 .translate = translate_ldstx,
6887 .par = (const uint32_t[]){false, true},
6888 .op_flags = XTENSA_OP_LOAD,
6889 .coprocessor = 0x1,
6890 }, {
6891 .name = "madd.s",
6892 .translate = translate_fpu2k_madd_s,
6893 .coprocessor = 0x1,
6894 }, {
6895 .name = "mov.s",
6896 .translate = translate_mov_s,
6897 .coprocessor = 0x1,
6898 }, {
6899 .name = "moveqz.s",
6900 .translate = translate_movcond_s,
6901 .par = (const uint32_t[]){TCG_COND_EQ},
6902 .coprocessor = 0x1,
6903 }, {
6904 .name = "movf.s",
6905 .translate = translate_movp_s,
6906 .par = (const uint32_t[]){TCG_COND_EQ},
6907 .coprocessor = 0x1,
6908 }, {
6909 .name = "movgez.s",
6910 .translate = translate_movcond_s,
6911 .par = (const uint32_t[]){TCG_COND_GE},
6912 .coprocessor = 0x1,
6913 }, {
6914 .name = "movltz.s",
6915 .translate = translate_movcond_s,
6916 .par = (const uint32_t[]){TCG_COND_LT},
6917 .coprocessor = 0x1,
6918 }, {
6919 .name = "movnez.s",
6920 .translate = translate_movcond_s,
6921 .par = (const uint32_t[]){TCG_COND_NE},
6922 .coprocessor = 0x1,
6923 }, {
6924 .name = "movt.s",
6925 .translate = translate_movp_s,
6926 .par = (const uint32_t[]){TCG_COND_NE},
6927 .coprocessor = 0x1,
6928 }, {
6929 .name = "msub.s",
6930 .translate = translate_fpu2k_msub_s,
6931 .coprocessor = 0x1,
6932 }, {
6933 .name = "mul.s",
6934 .translate = translate_fpu2k_mul_s,
6935 .coprocessor = 0x1,
6936 }, {
6937 .name = "neg.s",
6938 .translate = translate_neg_s,
6939 .coprocessor = 0x1,
6940 }, {
6941 .name = "oeq.s",
6942 .translate = translate_compare_s,
6943 .par = (const uint32_t[]){COMPARE_OEQ},
6944 .coprocessor = 0x1,
6945 }, {
6946 .name = "ole.s",
6947 .translate = translate_compare_s,
6948 .par = (const uint32_t[]){COMPARE_OLE},
6949 .coprocessor = 0x1,
6950 }, {
6951 .name = "olt.s",
6952 .translate = translate_compare_s,
6953 .par = (const uint32_t[]){COMPARE_OLT},
6954 .coprocessor = 0x1,
6955 }, {
6956 .name = "rfr",
6957 .translate = translate_rfr_s,
6958 .coprocessor = 0x1,
6959 }, {
6960 .name = "round.s",
6961 .translate = translate_ftoi_s,
6962 .par = (const uint32_t[]){float_round_nearest_even, false},
6963 .coprocessor = 0x1,
6964 }, {
6965 .name = "rur.fcr",
6966 .translate = translate_rur,
6967 .par = (const uint32_t[]){FCR},
6968 .coprocessor = 0x1,
6969 }, {
6970 .name = "rur.fsr",
6971 .translate = translate_rur,
6972 .par = (const uint32_t[]){FSR},
6973 .coprocessor = 0x1,
6974 }, {
6975 .name = "ssi",
6976 .translate = translate_ldsti,
6977 .par = (const uint32_t[]){true, false},
6978 .op_flags = XTENSA_OP_STORE,
6979 .coprocessor = 0x1,
6980 }, {
6981 .name = "ssiu",
6982 .translate = translate_ldsti,
6983 .par = (const uint32_t[]){true, true},
6984 .op_flags = XTENSA_OP_STORE,
6985 .coprocessor = 0x1,
6986 }, {
6987 .name = "ssx",
6988 .translate = translate_ldstx,
6989 .par = (const uint32_t[]){true, false},
6990 .op_flags = XTENSA_OP_STORE,
6991 .coprocessor = 0x1,
6992 }, {
6993 .name = "ssxu",
6994 .translate = translate_ldstx,
6995 .par = (const uint32_t[]){true, true},
6996 .op_flags = XTENSA_OP_STORE,
6997 .coprocessor = 0x1,
6998 }, {
6999 .name = "sub.s",
7000 .translate = translate_fpu2k_sub_s,
7001 .coprocessor = 0x1,
7002 }, {
7003 .name = "trunc.s",
7004 .translate = translate_ftoi_s,
7005 .par = (const uint32_t[]){float_round_to_zero, false},
7006 .coprocessor = 0x1,
7007 }, {
7008 .name = "ueq.s",
7009 .translate = translate_compare_s,
7010 .par = (const uint32_t[]){COMPARE_UEQ},
7011 .coprocessor = 0x1,
7012 }, {
7013 .name = "ufloat.s",
7014 .translate = translate_float_s,
7015 .par = (const uint32_t[]){true},
7016 .coprocessor = 0x1,
7017 }, {
7018 .name = "ule.s",
7019 .translate = translate_compare_s,
7020 .par = (const uint32_t[]){COMPARE_ULE},
7021 .coprocessor = 0x1,
7022 }, {
7023 .name = "ult.s",
7024 .translate = translate_compare_s,
7025 .par = (const uint32_t[]){COMPARE_ULT},
7026 .coprocessor = 0x1,
7027 }, {
7028 .name = "un.s",
7029 .translate = translate_compare_s,
7030 .par = (const uint32_t[]){COMPARE_UN},
7031 .coprocessor = 0x1,
7032 }, {
7033 .name = "utrunc.s",
7034 .translate = translate_ftoi_s,
7035 .par = (const uint32_t[]){float_round_to_zero, true},
7036 .coprocessor = 0x1,
7037 }, {
7038 .name = "wfr",
7039 .translate = translate_wfr_s,
7040 .coprocessor = 0x1,
7041 }, {
7042 .name = "wur.fcr",
7043 .translate = translate_wur_fpu2k_fcr,
7044 .par = (const uint32_t[]){FCR},
7045 .coprocessor = 0x1,
7046 }, {
7047 .name = "wur.fsr",
7048 .translate = translate_wur_fpu2k_fsr,
7049 .par = (const uint32_t[]){FSR},
7050 .coprocessor = 0x1,
7051 },
7052 };
7053
7054 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = {
7055 .num_opcodes = ARRAY_SIZE(fpu2000_ops),
7056 .opcode = fpu2000_ops,
7057 };
7058
7059 static void translate_add_d(DisasContext *dc, const OpcodeArg arg[],
7060 const uint32_t par[])
7061 {
7062 gen_helper_add_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
7063 }
7064
7065 static void translate_add_s(DisasContext *dc, const OpcodeArg arg[],
7066 const uint32_t par[])
7067 {
7068 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7069 gen_helper_fpu2k_add_s(arg[0].out, cpu_env,
7070 arg[1].in, arg[2].in);
7071 } else {
7072 OpcodeArg arg32[3];
7073
7074 get_f32_o1_i2(arg, arg32, 0, 1, 2);
7075 gen_helper_add_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
7076 put_f32_o1_i2(arg, arg32, 0, 1, 2);
7077 }
7078 }
7079
7080 static void translate_cvtd_s(DisasContext *dc, const OpcodeArg arg[],
7081 const uint32_t par[])
7082 {
7083 TCGv_i32 v = tcg_temp_new_i32();
7084
7085 tcg_gen_extrl_i64_i32(v, arg[1].in);
7086 gen_helper_cvtd_s(arg[0].out, cpu_env, v);
7087 tcg_temp_free_i32(v);
7088 }
7089
7090 static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[],
7091 const uint32_t par[])
7092 {
7093 TCGv_i32 v = tcg_temp_new_i32();
7094
7095 gen_helper_cvts_d(v, cpu_env, arg[1].in);
7096 tcg_gen_extu_i32_i64(arg[0].out, v);
7097 tcg_temp_free_i32(v);
7098 }
7099
7100 static void translate_ldsti_d(DisasContext *dc, const OpcodeArg arg[],
7101 const uint32_t par[])
7102 {
7103 TCGv_i32 addr;
7104
7105 if (par[1]) {
7106 addr = tcg_temp_new_i32();
7107 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
7108 } else {
7109 addr = arg[1].in;
7110 }
7111 gen_load_store_alignment(dc, 3, addr, false);
7112 if (par[0]) {
7113 tcg_gen_qemu_st64(arg[0].in, addr, dc->cring);
7114 } else {
7115 tcg_gen_qemu_ld64(arg[0].out, addr, dc->cring);
7116 }
7117 if (par[2]) {
7118 if (par[1]) {
7119 tcg_gen_mov_i32(arg[1].out, addr);
7120 } else {
7121 tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm);
7122 }
7123 }
7124 if (par[1]) {
7125 tcg_temp_free(addr);
7126 }
7127 }
7128
7129 static void translate_ldsti_s(DisasContext *dc, const OpcodeArg arg[],
7130 const uint32_t par[])
7131 {
7132 TCGv_i32 addr;
7133 OpcodeArg arg32[1];
7134
7135 if (par[1]) {
7136 addr = tcg_temp_new_i32();
7137 tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm);
7138 } else {
7139 addr = arg[1].in;
7140 }
7141 gen_load_store_alignment(dc, 2, addr, false);
7142 if (par[0]) {
7143 get_f32_i1(arg, arg32, 0);
7144 tcg_gen_qemu_st32(arg32[0].in, addr, dc->cring);
7145 put_f32_i1(arg, arg32, 0);
7146 } else {
7147 get_f32_o1(arg, arg32, 0);
7148 tcg_gen_qemu_ld32u(arg32[0].out, addr, dc->cring);
7149 put_f32_o1(arg, arg32, 0);
7150 }
7151 if (par[2]) {
7152 if (par[1]) {
7153 tcg_gen_mov_i32(arg[1].out, addr);
7154 } else {
7155 tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm);
7156 }
7157 }
7158 if (par[1]) {
7159 tcg_temp_free(addr);
7160 }
7161 }
7162
7163 static void translate_ldstx_d(DisasContext *dc, const OpcodeArg arg[],
7164 const uint32_t par[])
7165 {
7166 TCGv_i32 addr;
7167
7168 if (par[1]) {
7169 addr = tcg_temp_new_i32();
7170 tcg_gen_add_i32(addr, arg[1].in, arg[2].in);
7171 } else {
7172 addr = arg[1].in;
7173 }
7174 gen_load_store_alignment(dc, 3, addr, false);
7175 if (par[0]) {
7176 tcg_gen_qemu_st64(arg[0].in, addr, dc->cring);
7177 } else {
7178 tcg_gen_qemu_ld64(arg[0].out, addr, dc->cring);
7179 }
7180 if (par[2]) {
7181 if (par[1]) {
7182 tcg_gen_mov_i32(arg[1].out, addr);
7183 } else {
7184 tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in);
7185 }
7186 }
7187 if (par[1]) {
7188 tcg_temp_free(addr);
7189 }
7190 }
7191
7192 static void translate_ldstx_s(DisasContext *dc, const OpcodeArg arg[],
7193 const uint32_t par[])
7194 {
7195 TCGv_i32 addr;
7196 OpcodeArg arg32[1];
7197
7198 if (par[1]) {
7199 addr = tcg_temp_new_i32();
7200 tcg_gen_add_i32(addr, arg[1].in, arg[2].in);
7201 } else {
7202 addr = arg[1].in;
7203 }
7204 gen_load_store_alignment(dc, 2, addr, false);
7205 if (par[0]) {
7206 get_f32_i1(arg, arg32, 0);
7207 tcg_gen_qemu_st32(arg32[0].in, addr, dc->cring);
7208 put_f32_i1(arg, arg32, 0);
7209 } else {
7210 get_f32_o1(arg, arg32, 0);
7211 tcg_gen_qemu_ld32u(arg32[0].out, addr, dc->cring);
7212 put_f32_o1(arg, arg32, 0);
7213 }
7214 if (par[2]) {
7215 if (par[1]) {
7216 tcg_gen_mov_i32(arg[1].out, addr);
7217 } else {
7218 tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in);
7219 }
7220 }
7221 if (par[1]) {
7222 tcg_temp_free(addr);
7223 }
7224 }
7225
7226 static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[],
7227 const uint32_t par[])
7228 {
7229 gen_helper_madd_d(arg[0].out, cpu_env,
7230 arg[0].in, arg[1].in, arg[2].in);
7231 }
7232
7233 static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[],
7234 const uint32_t par[])
7235 {
7236 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7237 gen_helper_fpu2k_madd_s(arg[0].out, cpu_env,
7238 arg[0].in, arg[1].in, arg[2].in);
7239 } else {
7240 OpcodeArg arg32[3];
7241
7242 get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
7243 gen_helper_madd_s(arg32[0].out, cpu_env,
7244 arg32[0].in, arg32[1].in, arg32[2].in);
7245 put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
7246 }
7247 }
7248
7249 static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[],
7250 const uint32_t par[])
7251 {
7252 gen_helper_mul_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
7253 }
7254
7255 static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[],
7256 const uint32_t par[])
7257 {
7258 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7259 gen_helper_fpu2k_mul_s(arg[0].out, cpu_env,
7260 arg[1].in, arg[2].in);
7261 } else {
7262 OpcodeArg arg32[3];
7263
7264 get_f32_o1_i2(arg, arg32, 0, 1, 2);
7265 gen_helper_mul_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
7266 put_f32_o1_i2(arg, arg32, 0, 1, 2);
7267 }
7268 }
7269
7270 static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[],
7271 const uint32_t par[])
7272 {
7273 gen_helper_msub_d(arg[0].out, cpu_env,
7274 arg[0].in, arg[1].in, arg[2].in);
7275 }
7276
7277 static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[],
7278 const uint32_t par[])
7279 {
7280 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7281 gen_helper_fpu2k_msub_s(arg[0].out, cpu_env,
7282 arg[0].in, arg[1].in, arg[2].in);
7283 } else {
7284 OpcodeArg arg32[3];
7285
7286 get_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
7287 gen_helper_msub_s(arg32[0].out, cpu_env,
7288 arg32[0].in, arg32[1].in, arg32[2].in);
7289 put_f32_o1_i3(arg, arg32, 0, 0, 1, 2);
7290 }
7291 }
7292
7293 static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[],
7294 const uint32_t par[])
7295 {
7296 gen_helper_sub_d(arg[0].out, cpu_env, arg[1].in, arg[2].in);
7297 }
7298
7299 static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[],
7300 const uint32_t par[])
7301 {
7302 if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) {
7303 gen_helper_fpu2k_sub_s(arg[0].out, cpu_env,
7304 arg[1].in, arg[2].in);
7305 } else {
7306 OpcodeArg arg32[3];
7307
7308 get_f32_o1_i2(arg, arg32, 0, 1, 2);
7309 gen_helper_sub_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in);
7310 put_f32_o1_i2(arg, arg32, 0, 1, 2);
7311 }
7312 }
7313
7314 static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[],
7315 const uint32_t par[])
7316 {
7317 gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in);
7318 }
7319
7320 static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[],
7321 const uint32_t par[])
7322 {
7323 OpcodeArg arg32[2];
7324
7325 get_f32_o1_i2(arg, arg32, 0, 0, 1);
7326 gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in);
7327 put_f32_o1_i2(arg, arg32, 0, 0, 1);
7328 }
7329
7330 static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[],
7331 const uint32_t par[])
7332 {
7333 gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in);
7334 }
7335
7336 static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[],
7337 const uint32_t par[])
7338 {
7339 OpcodeArg arg32[2];
7340
7341 get_f32_o1_i1(arg, arg32, 0, 1);
7342 gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in);
7343 put_f32_o1_i1(arg, arg32, 0, 1);
7344 }
7345
7346 static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[],
7347 const uint32_t par[])
7348 {
7349 gen_helper_wur_fpu_fcr(cpu_env, arg[0].in);
7350 }
7351
7352 static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
7353 const uint32_t par[])
7354 {
7355 gen_helper_rur_fpu_fsr(arg[0].out, cpu_env);
7356 }
7357
7358 static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[],
7359 const uint32_t par[])
7360 {
7361 gen_helper_wur_fpu_fsr(cpu_env, arg[0].in);
7362 }
7363
7364 static const XtensaOpcodeOps fpu_ops[] = {
7365 {
7366 .name = "abs.d",
7367 .translate = translate_abs_d,
7368 .coprocessor = 0x1,
7369 }, {
7370 .name = "abs.s",
7371 .translate = translate_abs_s,
7372 .coprocessor = 0x1,
7373 }, {
7374 .name = "add.d",
7375 .translate = translate_add_d,
7376 .coprocessor = 0x1,
7377 }, {
7378 .name = "add.s",
7379 .translate = translate_add_s,
7380 .coprocessor = 0x1,
7381 }, {
7382 .name = "addexp.d",
7383 .translate = translate_nop,
7384 .coprocessor = 0x1,
7385 }, {
7386 .name = "addexp.s",
7387 .translate = translate_nop,
7388 .coprocessor = 0x1,
7389 }, {
7390 .name = "addexpm.d",
7391 .translate = translate_mov_s,
7392 .coprocessor = 0x1,
7393 }, {
7394 .name = "addexpm.s",
7395 .translate = translate_mov_s,
7396 .coprocessor = 0x1,
7397 }, {
7398 .name = "ceil.d",
7399 .translate = translate_ftoi_d,
7400 .par = (const uint32_t[]){float_round_up, false},
7401 .coprocessor = 0x1,
7402 }, {
7403 .name = "ceil.s",
7404 .translate = translate_ftoi_s,
7405 .par = (const uint32_t[]){float_round_up, false},
7406 .coprocessor = 0x1,
7407 }, {
7408 .name = "const.d",
7409 .translate = translate_const_d,
7410 .coprocessor = 0x1,
7411 }, {
7412 .name = "const.s",
7413 .translate = translate_const_s,
7414 .coprocessor = 0x1,
7415 }, {
7416 .name = "cvtd.s",
7417 .translate = translate_cvtd_s,
7418 .coprocessor = 0x1,
7419 }, {
7420 .name = "cvts.d",
7421 .translate = translate_cvts_d,
7422 .coprocessor = 0x1,
7423 }, {
7424 .name = "div0.d",
7425 .translate = translate_nop,
7426 .coprocessor = 0x1,
7427 }, {
7428 .name = "div0.s",
7429 .translate = translate_nop,
7430 .coprocessor = 0x1,
7431 }, {
7432 .name = "divn.d",
7433 .translate = translate_nop,
7434 .coprocessor = 0x1,
7435 }, {
7436 .name = "divn.s",
7437 .translate = translate_nop,
7438 .coprocessor = 0x1,
7439 }, {
7440 .name = "float.d",
7441 .translate = translate_float_d,
7442 .par = (const uint32_t[]){false},
7443 .coprocessor = 0x1,
7444 }, {
7445 .name = "float.s",
7446 .translate = translate_float_s,
7447 .par = (const uint32_t[]){false},
7448 .coprocessor = 0x1,
7449 }, {
7450 .name = "floor.d",
7451 .translate = translate_ftoi_d,
7452 .par = (const uint32_t[]){float_round_down, false},
7453 .coprocessor = 0x1,
7454 }, {
7455 .name = "floor.s",
7456 .translate = translate_ftoi_s,
7457 .par = (const uint32_t[]){float_round_down, false},
7458 .coprocessor = 0x1,
7459 }, {
7460 .name = "ldi",
7461 .translate = translate_ldsti_d,
7462 .par = (const uint32_t[]){false, true, false},
7463 .op_flags = XTENSA_OP_LOAD,
7464 .coprocessor = 0x1,
7465 }, {
7466 .name = "ldip",
7467 .translate = translate_ldsti_d,
7468 .par = (const uint32_t[]){false, false, true},
7469 .op_flags = XTENSA_OP_LOAD,
7470 .coprocessor = 0x1,
7471 }, {
7472 .name = "ldiu",
7473 .translate = translate_ldsti_d,
7474 .par = (const uint32_t[]){false, true, true},
7475 .op_flags = XTENSA_OP_LOAD,
7476 .coprocessor = 0x1,
7477 }, {
7478 .name = "ldx",
7479 .translate = translate_ldstx_d,
7480 .par = (const uint32_t[]){false, true, false},
7481 .op_flags = XTENSA_OP_LOAD,
7482 .coprocessor = 0x1,
7483 }, {
7484 .name = "ldxp",
7485 .translate = translate_ldstx_d,
7486 .par = (const uint32_t[]){false, false, true},
7487 .op_flags = XTENSA_OP_LOAD,
7488 .coprocessor = 0x1,
7489 }, {
7490 .name = "ldxu",
7491 .translate = translate_ldstx_d,
7492 .par = (const uint32_t[]){false, true, true},
7493 .op_flags = XTENSA_OP_LOAD,
7494 .coprocessor = 0x1,
7495 }, {
7496 .name = "lsi",
7497 .translate = translate_ldsti_s,
7498 .par = (const uint32_t[]){false, true, false},
7499 .op_flags = XTENSA_OP_LOAD,
7500 .coprocessor = 0x1,
7501 }, {
7502 .name = "lsip",
7503 .translate = translate_ldsti_s,
7504 .par = (const uint32_t[]){false, false, true},
7505 .op_flags = XTENSA_OP_LOAD,
7506 .coprocessor = 0x1,
7507 }, {
7508 .name = "lsiu",
7509 .translate = translate_ldsti_s,
7510 .par = (const uint32_t[]){false, true, true},
7511 .op_flags = XTENSA_OP_LOAD,
7512 .coprocessor = 0x1,
7513 }, {
7514 .name = "lsx",
7515 .translate = translate_ldstx_s,
7516 .par = (const uint32_t[]){false, true, false},
7517 .op_flags = XTENSA_OP_LOAD,
7518 .coprocessor = 0x1,
7519 }, {
7520 .name = "lsxp",
7521 .translate = translate_ldstx_s,
7522 .par = (const uint32_t[]){false, false, true},
7523 .op_flags = XTENSA_OP_LOAD,
7524 .coprocessor = 0x1,
7525 }, {
7526 .name = "lsxu",
7527 .translate = translate_ldstx_s,
7528 .par = (const uint32_t[]){false, true, true},
7529 .op_flags = XTENSA_OP_LOAD,
7530 .coprocessor = 0x1,
7531 }, {
7532 .name = "madd.d",
7533 .translate = translate_madd_d,
7534 .coprocessor = 0x1,
7535 }, {
7536 .name = "madd.s",
7537 .translate = translate_madd_s,
7538 .coprocessor = 0x1,
7539 }, {
7540 .name = "maddn.d",
7541 .translate = translate_nop,
7542 .coprocessor = 0x1,
7543 }, {
7544 .name = "maddn.s",
7545 .translate = translate_nop,
7546 .coprocessor = 0x1,
7547 }, {
7548 .name = "mkdadj.d",
7549 .translate = translate_mkdadj_d,
7550 .coprocessor = 0x1,
7551 }, {
7552 .name = "mkdadj.s",
7553 .translate = translate_mkdadj_s,
7554 .coprocessor = 0x1,
7555 }, {
7556 .name = "mksadj.d",
7557 .translate = translate_mksadj_d,
7558 .coprocessor = 0x1,
7559 }, {
7560 .name = "mksadj.s",
7561 .translate = translate_mksadj_s,
7562 .coprocessor = 0x1,
7563 }, {
7564 .name = "mov.d",
7565 .translate = translate_mov_d,
7566 .coprocessor = 0x1,
7567 }, {
7568 .name = "mov.s",
7569 .translate = translate_mov_s,
7570 .coprocessor = 0x1,
7571 }, {
7572 .name = "moveqz.d",
7573 .translate = translate_movcond_d,
7574 .par = (const uint32_t[]){TCG_COND_EQ},
7575 .coprocessor = 0x1,
7576 }, {
7577 .name = "moveqz.s",
7578 .translate = translate_movcond_s,
7579 .par = (const uint32_t[]){TCG_COND_EQ},
7580 .coprocessor = 0x1,
7581 }, {
7582 .name = "movf.d",
7583 .translate = translate_movp_d,
7584 .par = (const uint32_t[]){TCG_COND_EQ},
7585 .coprocessor = 0x1,
7586 }, {
7587 .name = "movf.s",
7588 .translate = translate_movp_s,
7589 .par = (const uint32_t[]){TCG_COND_EQ},
7590 .coprocessor = 0x1,
7591 }, {
7592 .name = "movgez.d",
7593 .translate = translate_movcond_d,
7594 .par = (const uint32_t[]){TCG_COND_GE},
7595 .coprocessor = 0x1,
7596 }, {
7597 .name = "movgez.s",
7598 .translate = translate_movcond_s,
7599 .par = (const uint32_t[]){TCG_COND_GE},
7600 .coprocessor = 0x1,
7601 }, {
7602 .name = "movltz.d",
7603 .translate = translate_movcond_d,
7604 .par = (const uint32_t[]){TCG_COND_LT},
7605 .coprocessor = 0x1,
7606 }, {
7607 .name = "movltz.s",
7608 .translate = translate_movcond_s,
7609 .par = (const uint32_t[]){TCG_COND_LT},
7610 .coprocessor = 0x1,
7611 }, {
7612 .name = "movnez.d",
7613 .translate = translate_movcond_d,
7614 .par = (const uint32_t[]){TCG_COND_NE},
7615 .coprocessor = 0x1,
7616 }, {
7617 .name = "movnez.s",
7618 .translate = translate_movcond_s,
7619 .par = (const uint32_t[]){TCG_COND_NE},
7620 .coprocessor = 0x1,
7621 }, {
7622 .name = "movt.d",
7623 .translate = translate_movp_d,
7624 .par = (const uint32_t[]){TCG_COND_NE},
7625 .coprocessor = 0x1,
7626 }, {
7627 .name = "movt.s",
7628 .translate = translate_movp_s,
7629 .par = (const uint32_t[]){TCG_COND_NE},
7630 .coprocessor = 0x1,
7631 }, {
7632 .name = "msub.d",
7633 .translate = translate_msub_d,
7634 .coprocessor = 0x1,
7635 }, {
7636 .name = "msub.s",
7637 .translate = translate_msub_s,
7638 .coprocessor = 0x1,
7639 }, {
7640 .name = "mul.d",
7641 .translate = translate_mul_d,
7642 .coprocessor = 0x1,
7643 }, {
7644 .name = "mul.s",
7645 .translate = translate_mul_s,
7646 .coprocessor = 0x1,
7647 }, {
7648 .name = "neg.d",
7649 .translate = translate_neg_d,
7650 .coprocessor = 0x1,
7651 }, {
7652 .name = "neg.s",
7653 .translate = translate_neg_s,
7654 .coprocessor = 0x1,
7655 }, {
7656 .name = "nexp01.d",
7657 .translate = translate_nop,
7658 .coprocessor = 0x1,
7659 }, {
7660 .name = "nexp01.s",
7661 .translate = translate_nop,
7662 .coprocessor = 0x1,
7663 }, {
7664 .name = "oeq.d",
7665 .translate = translate_compare_d,
7666 .par = (const uint32_t[]){COMPARE_OEQ},
7667 .coprocessor = 0x1,
7668 }, {
7669 .name = "oeq.s",
7670 .translate = translate_compare_s,
7671 .par = (const uint32_t[]){COMPARE_OEQ},
7672 .coprocessor = 0x1,
7673 }, {
7674 .name = "ole.d",
7675 .translate = translate_compare_d,
7676 .par = (const uint32_t[]){COMPARE_OLE},
7677 .coprocessor = 0x1,
7678 }, {
7679 .name = "ole.s",
7680 .translate = translate_compare_s,
7681 .par = (const uint32_t[]){COMPARE_OLE},
7682 .coprocessor = 0x1,
7683 }, {
7684 .name = "olt.d",
7685 .translate = translate_compare_d,
7686 .par = (const uint32_t[]){COMPARE_OLT},
7687 .coprocessor = 0x1,
7688 }, {
7689 .name = "olt.s",
7690 .translate = translate_compare_s,
7691 .par = (const uint32_t[]){COMPARE_OLT},
7692 .coprocessor = 0x1,
7693 }, {
7694 .name = "rfr",
7695 .translate = translate_rfr_s,
7696 .coprocessor = 0x1,
7697 }, {
7698 .name = "rfrd",
7699 .translate = translate_rfr_d,
7700 .coprocessor = 0x1,
7701 }, {
7702 .name = "round.d",
7703 .translate = translate_ftoi_d,
7704 .par = (const uint32_t[]){float_round_nearest_even, false},
7705 .coprocessor = 0x1,
7706 }, {
7707 .name = "round.s",
7708 .translate = translate_ftoi_s,
7709 .par = (const uint32_t[]){float_round_nearest_even, false},
7710 .coprocessor = 0x1,
7711 }, {
7712 .name = "rur.fcr",
7713 .translate = translate_rur,
7714 .par = (const uint32_t[]){FCR},
7715 .coprocessor = 0x1,
7716 }, {
7717 .name = "rur.fsr",
7718 .translate = translate_rur_fpu_fsr,
7719 .coprocessor = 0x1,
7720 }, {
7721 .name = "sdi",
7722 .translate = translate_ldsti_d,
7723 .par = (const uint32_t[]){true, true, false},
7724 .op_flags = XTENSA_OP_STORE,
7725 .coprocessor = 0x1,
7726 }, {
7727 .name = "sdip",
7728 .translate = translate_ldsti_d,
7729 .par = (const uint32_t[]){true, false, true},
7730 .op_flags = XTENSA_OP_STORE,
7731 .coprocessor = 0x1,
7732 }, {
7733 .name = "sdiu",
7734 .translate = translate_ldsti_d,
7735 .par = (const uint32_t[]){true, true, true},
7736 .op_flags = XTENSA_OP_STORE,
7737 .coprocessor = 0x1,
7738 }, {
7739 .name = "sdx",
7740 .translate = translate_ldstx_d,
7741 .par = (const uint32_t[]){true, true, false},
7742 .op_flags = XTENSA_OP_STORE,
7743 .coprocessor = 0x1,
7744 }, {
7745 .name = "sdxp",
7746 .translate = translate_ldstx_d,
7747 .par = (const uint32_t[]){true, false, true},
7748 .op_flags = XTENSA_OP_STORE,
7749 .coprocessor = 0x1,
7750 }, {
7751 .name = "sdxu",
7752 .translate = translate_ldstx_d,
7753 .par = (const uint32_t[]){true, true, true},
7754 .op_flags = XTENSA_OP_STORE,
7755 .coprocessor = 0x1,
7756 }, {
7757 .name = "sqrt0.d",
7758 .translate = translate_nop,
7759 .coprocessor = 0x1,
7760 }, {
7761 .name = "sqrt0.s",
7762 .translate = translate_nop,
7763 .coprocessor = 0x1,
7764 }, {
7765 .name = "ssi",
7766 .translate = translate_ldsti_s,
7767 .par = (const uint32_t[]){true, true, false},
7768 .op_flags = XTENSA_OP_STORE,
7769 .coprocessor = 0x1,
7770 }, {
7771 .name = "ssip",
7772 .translate = translate_ldsti_s,
7773 .par = (const uint32_t[]){true, false, true},
7774 .op_flags = XTENSA_OP_STORE,
7775 .coprocessor = 0x1,
7776 }, {
7777 .name = "ssiu",
7778 .translate = translate_ldsti_s,
7779 .par = (const uint32_t[]){true, true, true},
7780 .op_flags = XTENSA_OP_STORE,
7781 .coprocessor = 0x1,
7782 }, {
7783 .name = "ssx",
7784 .translate = translate_ldstx_s,
7785 .par = (const uint32_t[]){true, true, false},
7786 .op_flags = XTENSA_OP_STORE,
7787 .coprocessor = 0x1,
7788 }, {
7789 .name = "ssxp",
7790 .translate = translate_ldstx_s,
7791 .par = (const uint32_t[]){true, false, true},
7792 .op_flags = XTENSA_OP_STORE,
7793 .coprocessor = 0x1,
7794 }, {
7795 .name = "ssxu",
7796 .translate = translate_ldstx_s,
7797 .par = (const uint32_t[]){true, true, true},
7798 .op_flags = XTENSA_OP_STORE,
7799 .coprocessor = 0x1,
7800 }, {
7801 .name = "sub.d",
7802 .translate = translate_sub_d,
7803 .coprocessor = 0x1,
7804 }, {
7805 .name = "sub.s",
7806 .translate = translate_sub_s,
7807 .coprocessor = 0x1,
7808 }, {
7809 .name = "trunc.d",
7810 .translate = translate_ftoi_d,
7811 .par = (const uint32_t[]){float_round_to_zero, false},
7812 .coprocessor = 0x1,
7813 }, {
7814 .name = "trunc.s",
7815 .translate = translate_ftoi_s,
7816 .par = (const uint32_t[]){float_round_to_zero, false},
7817 .coprocessor = 0x1,
7818 }, {
7819 .name = "ueq.d",
7820 .translate = translate_compare_d,
7821 .par = (const uint32_t[]){COMPARE_UEQ},
7822 .coprocessor = 0x1,
7823 }, {
7824 .name = "ueq.s",
7825 .translate = translate_compare_s,
7826 .par = (const uint32_t[]){COMPARE_UEQ},
7827 .coprocessor = 0x1,
7828 }, {
7829 .name = "ufloat.d",
7830 .translate = translate_float_d,
7831 .par = (const uint32_t[]){true},
7832 .coprocessor = 0x1,
7833 }, {
7834 .name = "ufloat.s",
7835 .translate = translate_float_s,
7836 .par = (const uint32_t[]){true},
7837 .coprocessor = 0x1,
7838 }, {
7839 .name = "ule.d",
7840 .translate = translate_compare_d,
7841 .par = (const uint32_t[]){COMPARE_ULE},
7842 .coprocessor = 0x1,
7843 }, {
7844 .name = "ule.s",
7845 .translate = translate_compare_s,
7846 .par = (const uint32_t[]){COMPARE_ULE},
7847 .coprocessor = 0x1,
7848 }, {
7849 .name = "ult.d",
7850 .translate = translate_compare_d,
7851 .par = (const uint32_t[]){COMPARE_ULT},
7852 .coprocessor = 0x1,
7853 }, {
7854 .name = "ult.s",
7855 .translate = translate_compare_s,
7856 .par = (const uint32_t[]){COMPARE_ULT},
7857 .coprocessor = 0x1,
7858 }, {
7859 .name = "un.d",
7860 .translate = translate_compare_d,
7861 .par = (const uint32_t[]){COMPARE_UN},
7862 .coprocessor = 0x1,
7863 }, {
7864 .name = "un.s",
7865 .translate = translate_compare_s,
7866 .par = (const uint32_t[]){COMPARE_UN},
7867 .coprocessor = 0x1,
7868 }, {
7869 .name = "utrunc.d",
7870 .translate = translate_ftoi_d,
7871 .par = (const uint32_t[]){float_round_to_zero, true},
7872 .coprocessor = 0x1,
7873 }, {
7874 .name = "utrunc.s",
7875 .translate = translate_ftoi_s,
7876 .par = (const uint32_t[]){float_round_to_zero, true},
7877 .coprocessor = 0x1,
7878 }, {
7879 .name = "wfr",
7880 .translate = translate_wfr_s,
7881 .coprocessor = 0x1,
7882 }, {
7883 .name = "wfrd",
7884 .translate = translate_wfr_d,
7885 .coprocessor = 0x1,
7886 }, {
7887 .name = "wur.fcr",
7888 .translate = translate_wur_fpu_fcr,
7889 .par = (const uint32_t[]){FCR},
7890 .coprocessor = 0x1,
7891 }, {
7892 .name = "wur.fsr",
7893 .translate = translate_wur_fpu_fsr,
7894 .coprocessor = 0x1,
7895 },
7896 };
7897
7898 const XtensaOpcodeTranslators xtensa_fpu_opcodes = {
7899 .num_opcodes = ARRAY_SIZE(fpu_ops),
7900 .opcode = fpu_ops,
7901 };
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