3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/cpu_ldst.h"
40 #include "exec/semihost.h"
41 #include "exec/translator.h"
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
46 #include "trace-tcg.h"
50 /* is_jmp field values */
51 #define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */
54 const XtensaConfig
*config
;
63 int singlestep_enabled
;
67 bool sar_m32_allocated
;
79 xtensa_insnbuf insnbuf
;
80 xtensa_insnbuf slotbuf
;
83 static TCGv_i32 cpu_pc
;
84 static TCGv_i32 cpu_R
[16];
85 static TCGv_i32 cpu_FR
[16];
86 static TCGv_i32 cpu_SR
[256];
87 static TCGv_i32 cpu_UR
[256];
89 #include "exec/gen-icount.h"
91 typedef struct XtensaReg
{
103 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
105 .opt_bits = XTENSA_OPTION_BIT(opt), \
109 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
111 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
117 #define XTENSA_REG_BITS(regname, opt) \
118 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
120 static const XtensaReg sregnames
[256] = {
121 [LBEG
] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP
),
122 [LEND
] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP
),
123 [LCOUNT
] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP
),
124 [SAR
] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL
),
125 [BR
] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN
),
126 [LITBASE
] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R
),
127 [SCOMPARE1
] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE
),
128 [ACCLO
] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16
),
129 [ACCHI
] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16
),
130 [MR
] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16
),
131 [MR
+ 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16
),
132 [MR
+ 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16
),
133 [MR
+ 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16
),
134 [WINDOW_BASE
] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER
),
135 [WINDOW_START
] = XTENSA_REG("WINDOW_START",
136 XTENSA_OPTION_WINDOWED_REGISTER
),
137 [PTEVADDR
] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU
),
138 [MMID
] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL
),
139 [RASID
] = XTENSA_REG("RASID", XTENSA_OPTION_MMU
),
140 [ITLBCFG
] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU
),
141 [DTLBCFG
] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU
),
142 [IBREAKENABLE
] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG
),
143 [MEMCTL
] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL
),
144 [CACHEATTR
] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR
),
145 [ATOMCTL
] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL
),
146 [DDR
] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG
),
147 [IBREAKA
] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG
),
148 [IBREAKA
+ 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG
),
149 [DBREAKA
] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG
),
150 [DBREAKA
+ 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG
),
151 [DBREAKC
] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG
),
152 [DBREAKC
+ 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG
),
153 [CONFIGID0
] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL
, SR_R
),
154 [EPC1
] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION
),
155 [EPC1
+ 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
156 [EPC1
+ 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
157 [EPC1
+ 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
158 [EPC1
+ 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
159 [EPC1
+ 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
160 [EPC1
+ 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
161 [DEPC
] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION
),
162 [EPS2
] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
163 [EPS2
+ 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
164 [EPS2
+ 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
165 [EPS2
+ 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
166 [EPS2
+ 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
167 [EPS2
+ 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
168 [CONFIGID1
] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL
, SR_R
),
169 [EXCSAVE1
] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION
),
170 [EXCSAVE1
+ 1] = XTENSA_REG("EXCSAVE2",
171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
172 [EXCSAVE1
+ 2] = XTENSA_REG("EXCSAVE3",
173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
174 [EXCSAVE1
+ 3] = XTENSA_REG("EXCSAVE4",
175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
176 [EXCSAVE1
+ 4] = XTENSA_REG("EXCSAVE5",
177 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
178 [EXCSAVE1
+ 5] = XTENSA_REG("EXCSAVE6",
179 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
180 [EXCSAVE1
+ 6] = XTENSA_REG("EXCSAVE7",
181 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
182 [CPENABLE
] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR
),
183 [INTSET
] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT
, SR_RW
),
184 [INTCLEAR
] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT
, SR_W
),
185 [INTENABLE
] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT
),
186 [PS
] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL
),
187 [VECBASE
] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR
),
188 [EXCCAUSE
] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION
),
189 [DEBUGCAUSE
] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG
, SR_R
),
190 [CCOUNT
] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT
),
191 [PRID
] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID
, SR_R
),
192 [ICOUNT
] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG
),
193 [ICOUNTLEVEL
] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG
),
194 [EXCVADDR
] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION
),
195 [CCOMPARE
] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT
),
196 [CCOMPARE
+ 1] = XTENSA_REG("CCOMPARE1",
197 XTENSA_OPTION_TIMER_INTERRUPT
),
198 [CCOMPARE
+ 2] = XTENSA_REG("CCOMPARE2",
199 XTENSA_OPTION_TIMER_INTERRUPT
),
200 [MISC
] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR
),
201 [MISC
+ 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR
),
202 [MISC
+ 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR
),
203 [MISC
+ 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR
),
206 static const XtensaReg uregnames
[256] = {
207 [EXPSTATE
] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL
),
208 [THREADPTR
] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER
),
209 [FCR
] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR
),
210 [FSR
] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR
),
213 void xtensa_translate_init(void)
215 static const char * const regnames
[] = {
216 "ar0", "ar1", "ar2", "ar3",
217 "ar4", "ar5", "ar6", "ar7",
218 "ar8", "ar9", "ar10", "ar11",
219 "ar12", "ar13", "ar14", "ar15",
221 static const char * const fregnames
[] = {
222 "f0", "f1", "f2", "f3",
223 "f4", "f5", "f6", "f7",
224 "f8", "f9", "f10", "f11",
225 "f12", "f13", "f14", "f15",
229 cpu_pc
= tcg_global_mem_new_i32(cpu_env
,
230 offsetof(CPUXtensaState
, pc
), "pc");
232 for (i
= 0; i
< 16; i
++) {
233 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
234 offsetof(CPUXtensaState
, regs
[i
]),
238 for (i
= 0; i
< 16; i
++) {
239 cpu_FR
[i
] = tcg_global_mem_new_i32(cpu_env
,
240 offsetof(CPUXtensaState
, fregs
[i
].f32
[FP_F32_LOW
]),
244 for (i
= 0; i
< 256; ++i
) {
245 if (sregnames
[i
].name
) {
246 cpu_SR
[i
] = tcg_global_mem_new_i32(cpu_env
,
247 offsetof(CPUXtensaState
, sregs
[i
]),
252 for (i
= 0; i
< 256; ++i
) {
253 if (uregnames
[i
].name
) {
254 cpu_UR
[i
] = tcg_global_mem_new_i32(cpu_env
,
255 offsetof(CPUXtensaState
, uregs
[i
]),
261 static inline bool option_enabled(DisasContext
*dc
, int opt
)
263 return xtensa_option_enabled(dc
->config
, opt
);
266 static void init_sar_tracker(DisasContext
*dc
)
268 dc
->sar_5bit
= false;
269 dc
->sar_m32_5bit
= false;
270 dc
->sar_m32_allocated
= false;
273 static void reset_sar_tracker(DisasContext
*dc
)
275 if (dc
->sar_m32_allocated
) {
276 tcg_temp_free(dc
->sar_m32
);
280 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
282 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
283 if (dc
->sar_m32_5bit
) {
284 tcg_gen_discard_i32(dc
->sar_m32
);
287 dc
->sar_m32_5bit
= false;
290 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
292 TCGv_i32 tmp
= tcg_const_i32(32);
293 if (!dc
->sar_m32_allocated
) {
294 dc
->sar_m32
= tcg_temp_local_new_i32();
295 dc
->sar_m32_allocated
= true;
297 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
298 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
299 dc
->sar_5bit
= false;
300 dc
->sar_m32_5bit
= true;
304 static void gen_exception(DisasContext
*dc
, int excp
)
306 TCGv_i32 tmp
= tcg_const_i32(excp
);
307 gen_helper_exception(cpu_env
, tmp
);
311 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
313 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
314 TCGv_i32 tcause
= tcg_const_i32(cause
);
315 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
317 tcg_temp_free(tcause
);
318 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
319 cause
== SYSCALL_CAUSE
) {
320 dc
->is_jmp
= DISAS_UPDATE
;
324 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
327 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
328 TCGv_i32 tcause
= tcg_const_i32(cause
);
329 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
331 tcg_temp_free(tcause
);
334 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
336 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
337 TCGv_i32 tcause
= tcg_const_i32(cause
);
338 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
340 tcg_temp_free(tcause
);
341 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
342 dc
->is_jmp
= DISAS_UPDATE
;
346 static bool gen_check_privilege(DisasContext
*dc
)
348 #ifndef CONFIG_USER_ONLY
353 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
354 dc
->is_jmp
= DISAS_UPDATE
;
358 static bool gen_check_cpenable(DisasContext
*dc
, unsigned cp
)
360 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) &&
361 !(dc
->cpenable
& (1 << cp
))) {
362 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ cp
);
363 dc
->is_jmp
= DISAS_UPDATE
;
369 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
371 tcg_gen_mov_i32(cpu_pc
, dest
);
373 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
375 if (dc
->singlestep_enabled
) {
376 gen_exception(dc
, EXCP_DEBUG
);
379 tcg_gen_goto_tb(slot
);
380 tcg_gen_exit_tb(dc
->tb
, slot
);
382 tcg_gen_exit_tb(NULL
, 0);
385 dc
->is_jmp
= DISAS_UPDATE
;
388 static void gen_jump(DisasContext
*dc
, TCGv dest
)
390 gen_jump_slot(dc
, dest
, -1);
393 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
395 TCGv_i32 tmp
= tcg_const_i32(dest
);
396 #ifndef CONFIG_USER_ONLY
397 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
401 gen_jump_slot(dc
, tmp
, slot
);
405 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
408 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
410 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
411 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
412 tcg_temp_free(tcallinc
);
413 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
414 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
415 gen_jump_slot(dc
, dest
, slot
);
418 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
420 gen_callw_slot(dc
, callinc
, dest
, -1);
423 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
425 TCGv_i32 tmp
= tcg_const_i32(dest
);
426 #ifndef CONFIG_USER_ONLY
427 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
431 gen_callw_slot(dc
, callinc
, tmp
, slot
);
435 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
437 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
438 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
439 dc
->next_pc
== dc
->lend
) {
440 TCGLabel
*label
= gen_new_label();
442 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
443 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
444 gen_jumpi(dc
, dc
->lbeg
, slot
);
445 gen_set_label(label
);
446 gen_jumpi(dc
, dc
->next_pc
, -1);
452 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
454 if (!gen_check_loop_end(dc
, slot
)) {
455 gen_jumpi(dc
, dc
->next_pc
, slot
);
459 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
460 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t addr
)
462 TCGLabel
*label
= gen_new_label();
464 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
465 gen_jumpi_check_loop_end(dc
, 0);
466 gen_set_label(label
);
467 gen_jumpi(dc
, addr
, 1);
470 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
471 TCGv_i32 t0
, uint32_t t1
, uint32_t addr
)
473 TCGv_i32 tmp
= tcg_const_i32(t1
);
474 gen_brcond(dc
, cond
, t0
, tmp
, addr
);
478 static bool gen_check_sr(DisasContext
*dc
, uint32_t sr
, unsigned access
)
480 if (!xtensa_option_bits_enabled(dc
->config
, sregnames
[sr
].opt_bits
)) {
481 if (sregnames
[sr
].name
) {
482 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not configured\n", sregnames
[sr
].name
);
484 qemu_log_mask(LOG_UNIMP
, "SR %d is not implemented\n", sr
);
486 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
488 } else if (!(sregnames
[sr
].access
& access
)) {
489 static const char * const access_text
[] = {
494 assert(access
< ARRAY_SIZE(access_text
) && access_text
[access
]);
495 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not available for %s\n", sregnames
[sr
].name
,
496 access_text
[access
]);
497 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
503 #ifndef CONFIG_USER_ONLY
504 static bool gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
506 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
509 gen_helper_update_ccount(cpu_env
);
510 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
511 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
518 static bool gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
520 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
521 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
522 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
527 static bool gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
529 static bool (* const rsr_handler
[256])(DisasContext
*dc
,
530 TCGv_i32 d
, uint32_t sr
) = {
531 #ifndef CONFIG_USER_ONLY
532 [CCOUNT
] = gen_rsr_ccount
,
533 [INTSET
] = gen_rsr_ccount
,
534 [PTEVADDR
] = gen_rsr_ptevaddr
,
538 if (rsr_handler
[sr
]) {
539 return rsr_handler
[sr
](dc
, d
, sr
);
541 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
546 static bool gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
548 gen_helper_wsr_lbeg(cpu_env
, s
);
549 gen_jumpi_check_loop_end(dc
, 0);
553 static bool gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
555 gen_helper_wsr_lend(cpu_env
, s
);
556 gen_jumpi_check_loop_end(dc
, 0);
560 static bool gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
562 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
563 if (dc
->sar_m32_5bit
) {
564 tcg_gen_discard_i32(dc
->sar_m32
);
566 dc
->sar_5bit
= false;
567 dc
->sar_m32_5bit
= false;
571 static bool gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
573 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
577 static bool gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
579 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
580 /* This can change tb->flags, so exit tb */
581 gen_jumpi_check_loop_end(dc
, -1);
585 static bool gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
587 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
591 #ifndef CONFIG_USER_ONLY
592 static bool gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
594 gen_helper_wsr_windowbase(cpu_env
, v
);
595 /* This can change tb->flags, so exit tb */
596 gen_jumpi_check_loop_end(dc
, -1);
600 static bool gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
602 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
603 /* This can change tb->flags, so exit tb */
604 gen_jumpi_check_loop_end(dc
, -1);
608 static bool gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
610 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
614 static bool gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
616 gen_helper_wsr_rasid(cpu_env
, v
);
617 /* This can change tb->flags, so exit tb */
618 gen_jumpi_check_loop_end(dc
, -1);
622 static bool gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
624 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
628 static bool gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
630 gen_helper_wsr_ibreakenable(cpu_env
, v
);
631 gen_jumpi_check_loop_end(dc
, 0);
635 static bool gen_wsr_memctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
637 gen_helper_wsr_memctl(cpu_env
, v
);
641 static bool gen_wsr_atomctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
643 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x3f);
647 static bool gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
649 unsigned id
= sr
- IBREAKA
;
651 if (id
< dc
->config
->nibreak
) {
652 TCGv_i32 tmp
= tcg_const_i32(id
);
653 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
655 gen_jumpi_check_loop_end(dc
, 0);
661 static bool gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
663 unsigned id
= sr
- DBREAKA
;
665 if (id
< dc
->config
->ndbreak
) {
666 TCGv_i32 tmp
= tcg_const_i32(id
);
667 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
673 static bool gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
675 unsigned id
= sr
- DBREAKC
;
677 if (id
< dc
->config
->ndbreak
) {
678 TCGv_i32 tmp
= tcg_const_i32(id
);
679 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
685 static bool gen_wsr_cpenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
687 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xff);
688 /* This can change tb->flags, so exit tb */
689 gen_jumpi_check_loop_end(dc
, -1);
693 static void gen_check_interrupts(DisasContext
*dc
)
695 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
698 gen_helper_check_interrupts(cpu_env
);
699 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
704 static bool gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
706 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
707 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
708 gen_check_interrupts(dc
);
709 gen_jumpi_check_loop_end(dc
, 0);
713 static bool gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
715 TCGv_i32 tmp
= tcg_temp_new_i32();
717 tcg_gen_andi_i32(tmp
, v
,
718 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
719 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
720 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
721 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
723 gen_check_interrupts(dc
);
724 gen_jumpi_check_loop_end(dc
, 0);
728 static bool gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
730 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
731 gen_check_interrupts(dc
);
732 gen_jumpi_check_loop_end(dc
, 0);
736 static bool gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
738 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
739 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
741 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
744 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
745 gen_check_interrupts(dc
);
746 /* This can change mmu index and tb->flags, so exit tb */
747 gen_jumpi_check_loop_end(dc
, -1);
751 static bool gen_wsr_ccount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
753 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
756 gen_helper_wsr_ccount(cpu_env
, v
);
757 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
759 gen_jumpi_check_loop_end(dc
, 0);
765 static bool gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
768 tcg_gen_mov_i32(dc
->next_icount
, v
);
770 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
775 static bool gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
777 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
778 /* This can change tb->flags, so exit tb */
779 gen_jumpi_check_loop_end(dc
, -1);
783 static bool gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
785 uint32_t id
= sr
- CCOMPARE
;
788 if (id
< dc
->config
->nccompare
) {
789 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
790 TCGv_i32 tmp
= tcg_const_i32(id
);
792 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
793 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
794 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
797 gen_helper_update_ccompare(cpu_env
, tmp
);
798 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
800 gen_jumpi_check_loop_end(dc
, 0);
808 static void gen_check_interrupts(DisasContext
*dc
)
813 static bool gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
815 static bool (* const wsr_handler
[256])(DisasContext
*dc
,
816 uint32_t sr
, TCGv_i32 v
) = {
817 [LBEG
] = gen_wsr_lbeg
,
818 [LEND
] = gen_wsr_lend
,
821 [LITBASE
] = gen_wsr_litbase
,
822 [ACCHI
] = gen_wsr_acchi
,
823 #ifndef CONFIG_USER_ONLY
824 [WINDOW_BASE
] = gen_wsr_windowbase
,
825 [WINDOW_START
] = gen_wsr_windowstart
,
826 [PTEVADDR
] = gen_wsr_ptevaddr
,
827 [RASID
] = gen_wsr_rasid
,
828 [ITLBCFG
] = gen_wsr_tlbcfg
,
829 [DTLBCFG
] = gen_wsr_tlbcfg
,
830 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
831 [MEMCTL
] = gen_wsr_memctl
,
832 [ATOMCTL
] = gen_wsr_atomctl
,
833 [IBREAKA
] = gen_wsr_ibreaka
,
834 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
835 [DBREAKA
] = gen_wsr_dbreaka
,
836 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
837 [DBREAKC
] = gen_wsr_dbreakc
,
838 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
839 [CPENABLE
] = gen_wsr_cpenable
,
840 [INTSET
] = gen_wsr_intset
,
841 [INTCLEAR
] = gen_wsr_intclear
,
842 [INTENABLE
] = gen_wsr_intenable
,
844 [CCOUNT
] = gen_wsr_ccount
,
845 [ICOUNT
] = gen_wsr_icount
,
846 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
847 [CCOMPARE
] = gen_wsr_ccompare
,
848 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
849 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
853 if (wsr_handler
[sr
]) {
854 return wsr_handler
[sr
](dc
, sr
, s
);
856 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
861 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
865 gen_helper_wur_fcr(cpu_env
, s
);
869 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
873 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
878 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
879 TCGv_i32 addr
, bool no_hw_alignment
)
881 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
882 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
883 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
885 TCGLabel
*label
= gen_new_label();
886 TCGv_i32 tmp
= tcg_temp_new_i32();
887 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
888 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
889 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
890 gen_set_label(label
);
895 #ifndef CONFIG_USER_ONLY
896 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
898 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
899 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
901 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
904 gen_helper_waiti(cpu_env
, pc
, intlevel
);
905 if (tb_cflags(dc
->tb
) & CF_USE_ICOUNT
) {
909 tcg_temp_free(intlevel
);
910 gen_jumpi_check_loop_end(dc
, 0);
914 static bool gen_window_check1(DisasContext
*dc
, unsigned r1
)
916 if (r1
/ 4 > dc
->window
) {
917 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
918 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
920 gen_helper_window_check(cpu_env
, pc
, w
);
921 dc
->is_jmp
= DISAS_UPDATE
;
927 static bool gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
929 return gen_window_check1(dc
, r1
> r2
? r1
: r2
);
932 static bool gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
935 return gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
938 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
940 TCGv_i32 m
= tcg_temp_new_i32();
943 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
945 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
950 static inline unsigned xtensa_op0_insn_len(DisasContext
*dc
, uint8_t op0
)
952 return xtensa_isa_length_from_chars(dc
->config
->isa
, &op0
);
955 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
957 xtensa_isa isa
= dc
->config
->isa
;
958 unsigned char b
[MAX_INSN_LENGTH
] = {cpu_ldub_code(env
, dc
->pc
)};
959 unsigned len
= xtensa_op0_insn_len(dc
, b
[0]);
964 if (len
== XTENSA_UNDEFINED
) {
965 qemu_log_mask(LOG_GUEST_ERROR
,
966 "unknown instruction length (pc = %08x)\n",
968 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
972 dc
->next_pc
= dc
->pc
+ len
;
973 for (i
= 1; i
< len
; ++i
) {
974 b
[i
] = cpu_ldub_code(env
, dc
->pc
+ i
);
976 xtensa_insnbuf_from_chars(isa
, dc
->insnbuf
, b
, len
);
977 fmt
= xtensa_format_decode(isa
, dc
->insnbuf
);
978 if (fmt
== XTENSA_UNDEFINED
) {
979 qemu_log_mask(LOG_GUEST_ERROR
,
980 "unrecognized instruction format (pc = %08x)\n",
982 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
985 slots
= xtensa_format_num_slots(isa
, fmt
);
986 for (slot
= 0; slot
< slots
; ++slot
) {
988 int opnd
, vopnd
, opnds
;
989 uint32_t raw_arg
[MAX_OPCODE_ARGS
];
990 uint32_t arg
[MAX_OPCODE_ARGS
];
991 XtensaOpcodeOps
*ops
;
993 dc
->raw_arg
= raw_arg
;
995 xtensa_format_get_slot(isa
, fmt
, slot
, dc
->insnbuf
, dc
->slotbuf
);
996 opc
= xtensa_opcode_decode(isa
, fmt
, slot
, dc
->slotbuf
);
997 if (opc
== XTENSA_UNDEFINED
) {
998 qemu_log_mask(LOG_GUEST_ERROR
,
999 "unrecognized opcode in slot %d (pc = %08x)\n",
1001 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1004 opnds
= xtensa_opcode_num_operands(isa
, opc
);
1006 for (opnd
= vopnd
= 0; opnd
< opnds
; ++opnd
) {
1007 if (xtensa_operand_is_visible(isa
, opc
, opnd
)) {
1010 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
1012 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
1014 if (xtensa_operand_is_PCrelative(isa
, opc
, opnd
)) {
1015 xtensa_operand_undo_reloc(isa
, opc
, opnd
, &v
, dc
->pc
);
1021 ops
= dc
->config
->opcode_ops
[opc
];
1023 ops
->translate(dc
, arg
, ops
->par
);
1025 qemu_log_mask(LOG_GUEST_ERROR
,
1026 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
1027 xtensa_opcode_name(isa
, opc
), slot
, dc
->pc
);
1028 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1032 if (dc
->is_jmp
== DISAS_NEXT
) {
1033 gen_check_loop_end(dc
, 0);
1035 dc
->pc
= dc
->next_pc
;
1038 static inline unsigned xtensa_insn_len(CPUXtensaState
*env
, DisasContext
*dc
)
1040 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
1041 return xtensa_op0_insn_len(dc
, b0
);
1044 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
1048 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
1049 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
1050 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
1051 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
1057 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
)
1059 CPUXtensaState
*env
= cs
->env_ptr
;
1062 int max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
1063 uint32_t pc_start
= tb
->pc
;
1064 uint32_t page_start
= pc_start
& TARGET_PAGE_MASK
;
1066 if (max_insns
== 0) {
1067 max_insns
= CF_COUNT_MASK
;
1069 if (max_insns
> TCG_MAX_INSNS
) {
1070 max_insns
= TCG_MAX_INSNS
;
1073 dc
.config
= env
->config
;
1074 dc
.singlestep_enabled
= cs
->singlestep_enabled
;
1077 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
1078 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
1079 dc
.lbeg
= env
->sregs
[LBEG
];
1080 dc
.lend
= env
->sregs
[LEND
];
1081 dc
.is_jmp
= DISAS_NEXT
;
1082 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
1083 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
1084 dc
.cpenable
= (tb
->flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
1085 XTENSA_TBFLAG_CPENABLE_SHIFT
;
1086 dc
.window
= ((tb
->flags
& XTENSA_TBFLAG_WINDOW_MASK
) >>
1087 XTENSA_TBFLAG_WINDOW_SHIFT
);
1089 if (dc
.config
->isa
) {
1090 dc
.insnbuf
= xtensa_insnbuf_alloc(dc
.config
->isa
);
1091 dc
.slotbuf
= xtensa_insnbuf_alloc(dc
.config
->isa
);
1094 init_sar_tracker(&dc
);
1096 dc
.next_icount
= tcg_temp_local_new_i32();
1101 if ((tb_cflags(tb
) & CF_USE_ICOUNT
) &&
1102 (tb
->flags
& XTENSA_TBFLAG_YIELD
)) {
1103 tcg_gen_insn_start(dc
.pc
);
1105 gen_exception(&dc
, EXCP_YIELD
);
1106 dc
.is_jmp
= DISAS_UPDATE
;
1109 if (tb
->flags
& XTENSA_TBFLAG_EXCEPTION
) {
1110 tcg_gen_insn_start(dc
.pc
);
1112 gen_exception(&dc
, EXCP_DEBUG
);
1113 dc
.is_jmp
= DISAS_UPDATE
;
1118 tcg_gen_insn_start(dc
.pc
);
1121 if (unlikely(cpu_breakpoint_test(cs
, dc
.pc
, BP_ANY
))) {
1122 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1123 gen_exception(&dc
, EXCP_DEBUG
);
1124 dc
.is_jmp
= DISAS_UPDATE
;
1125 /* The address covered by the breakpoint must be included in
1126 [tb->pc, tb->pc + tb->size) in order to for it to be
1127 properly cleared -- thus we increment the PC here so that
1128 the logic setting tb->size below does the right thing. */
1133 if (insn_count
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
1138 TCGLabel
*label
= gen_new_label();
1140 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
1141 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
1142 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
1144 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
1146 gen_set_label(label
);
1150 gen_ibreak_check(env
, &dc
);
1153 disas_xtensa_insn(env
, &dc
);
1155 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
1157 if (cs
->singlestep_enabled
) {
1158 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1159 gen_exception(&dc
, EXCP_DEBUG
);
1162 } while (dc
.is_jmp
== DISAS_NEXT
&&
1163 insn_count
< max_insns
&&
1164 dc
.pc
- page_start
< TARGET_PAGE_SIZE
&&
1165 dc
.pc
- page_start
+ xtensa_insn_len(env
, &dc
) <= TARGET_PAGE_SIZE
1166 && !tcg_op_buf_full());
1168 reset_sar_tracker(&dc
);
1170 tcg_temp_free(dc
.next_icount
);
1172 if (dc
.config
->isa
) {
1173 xtensa_insnbuf_free(dc
.config
->isa
, dc
.insnbuf
);
1174 xtensa_insnbuf_free(dc
.config
->isa
, dc
.slotbuf
);
1177 if (tb_cflags(tb
) & CF_LAST_IO
) {
1181 if (dc
.is_jmp
== DISAS_NEXT
) {
1182 gen_jumpi(&dc
, dc
.pc
, 0);
1184 gen_tb_end(tb
, insn_count
);
1187 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
1188 && qemu_log_in_addr_range(pc_start
)) {
1190 qemu_log("----------------\n");
1191 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
1192 log_target_disas(cs
, pc_start
, dc
.pc
- pc_start
);
1197 tb
->size
= dc
.pc
- pc_start
;
1198 tb
->icount
= insn_count
;
1201 void xtensa_cpu_dump_state(CPUState
*cs
, FILE *f
,
1202 fprintf_function cpu_fprintf
, int flags
)
1204 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
1205 CPUXtensaState
*env
= &cpu
->env
;
1208 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
1210 for (i
= j
= 0; i
< 256; ++i
) {
1211 if (xtensa_option_bits_enabled(env
->config
, sregnames
[i
].opt_bits
)) {
1212 cpu_fprintf(f
, "%12s=%08x%c", sregnames
[i
].name
, env
->sregs
[i
],
1213 (j
++ % 4) == 3 ? '\n' : ' ');
1217 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1219 for (i
= j
= 0; i
< 256; ++i
) {
1220 if (xtensa_option_bits_enabled(env
->config
, uregnames
[i
].opt_bits
)) {
1221 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
].name
, env
->uregs
[i
],
1222 (j
++ % 4) == 3 ? '\n' : ' ');
1226 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1228 for (i
= 0; i
< 16; ++i
) {
1229 cpu_fprintf(f
, " A%02d=%08x%c", i
, env
->regs
[i
],
1230 (i
% 4) == 3 ? '\n' : ' ');
1233 xtensa_sync_phys_from_window(env
);
1234 cpu_fprintf(f
, "\n");
1236 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
1237 cpu_fprintf(f
, "AR%02d=%08x ", i
, env
->phys_regs
[i
]);
1239 bool ws
= (env
->sregs
[WINDOW_START
] & (1 << (i
/ 4))) != 0;
1240 bool cw
= env
->sregs
[WINDOW_BASE
] == i
/ 4;
1242 cpu_fprintf(f
, "%c%c\n", ws
? '<' : ' ', cw
? '=' : ' ');
1246 if ((flags
& CPU_DUMP_FPU
) &&
1247 xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
1248 cpu_fprintf(f
, "\n");
1250 for (i
= 0; i
< 16; ++i
) {
1251 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
1252 float32_val(env
->fregs
[i
].f32
[FP_F32_LOW
]),
1253 *(float *)(env
->fregs
[i
].f32
+ FP_F32_LOW
),
1254 (i
% 2) == 1 ? '\n' : ' ');
1259 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
,
1265 static int compare_opcode_ops(const void *a
, const void *b
)
1267 return strcmp((const char *)a
,
1268 ((const XtensaOpcodeOps
*)b
)->name
);
1272 xtensa_find_opcode_ops(const XtensaOpcodeTranslators
*t
,
1275 return bsearch(name
, t
->opcode
, t
->num_opcodes
,
1276 sizeof(XtensaOpcodeOps
), compare_opcode_ops
);
1279 static void translate_abs(DisasContext
*dc
, const uint32_t arg
[],
1280 const uint32_t par
[])
1282 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1283 TCGv_i32 zero
= tcg_const_i32(0);
1284 TCGv_i32 neg
= tcg_temp_new_i32();
1286 tcg_gen_neg_i32(neg
, cpu_R
[arg
[1]]);
1287 tcg_gen_movcond_i32(TCG_COND_GE
, cpu_R
[arg
[0]],
1288 cpu_R
[arg
[1]], zero
, cpu_R
[arg
[1]], neg
);
1290 tcg_temp_free(zero
);
1294 static void translate_add(DisasContext
*dc
, const uint32_t arg
[],
1295 const uint32_t par
[])
1297 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1298 tcg_gen_add_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1302 static void translate_addi(DisasContext
*dc
, const uint32_t arg
[],
1303 const uint32_t par
[])
1305 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1306 tcg_gen_addi_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
1310 static void translate_addx(DisasContext
*dc
, const uint32_t arg
[],
1311 const uint32_t par
[])
1313 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1314 TCGv_i32 tmp
= tcg_temp_new_i32();
1315 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], par
[0]);
1316 tcg_gen_add_i32(cpu_R
[arg
[0]], tmp
, cpu_R
[arg
[2]]);
1321 static void translate_all(DisasContext
*dc
, const uint32_t arg
[],
1322 const uint32_t par
[])
1324 uint32_t shift
= par
[1];
1325 TCGv_i32 mask
= tcg_const_i32(((1 << shift
) - 1) << arg
[1]);
1326 TCGv_i32 tmp
= tcg_temp_new_i32();
1328 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1330 tcg_gen_addi_i32(tmp
, tmp
, 1 << arg
[1]);
1332 tcg_gen_add_i32(tmp
, tmp
, mask
);
1334 tcg_gen_shri_i32(tmp
, tmp
, arg
[1] + shift
);
1335 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1337 tcg_temp_free(mask
);
1341 static void translate_and(DisasContext
*dc
, const uint32_t arg
[],
1342 const uint32_t par
[])
1344 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1345 tcg_gen_and_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1349 static void translate_ball(DisasContext
*dc
, const uint32_t arg
[],
1350 const uint32_t par
[])
1352 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1353 TCGv_i32 tmp
= tcg_temp_new_i32();
1354 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1355 gen_brcond(dc
, par
[0], tmp
, cpu_R
[arg
[1]], arg
[2]);
1360 static void translate_bany(DisasContext
*dc
, const uint32_t arg
[],
1361 const uint32_t par
[])
1363 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1364 TCGv_i32 tmp
= tcg_temp_new_i32();
1365 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1366 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1371 static void translate_b(DisasContext
*dc
, const uint32_t arg
[],
1372 const uint32_t par
[])
1374 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1375 gen_brcond(dc
, par
[0], cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
1379 static void translate_bb(DisasContext
*dc
, const uint32_t arg
[],
1380 const uint32_t par
[])
1382 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1383 #ifdef TARGET_WORDS_BIGENDIAN
1384 TCGv_i32 bit
= tcg_const_i32(0x80000000u
);
1386 TCGv_i32 bit
= tcg_const_i32(0x00000001u
);
1388 TCGv_i32 tmp
= tcg_temp_new_i32();
1389 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[1]], 0x1f);
1390 #ifdef TARGET_WORDS_BIGENDIAN
1391 tcg_gen_shr_i32(bit
, bit
, tmp
);
1393 tcg_gen_shl_i32(bit
, bit
, tmp
);
1395 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], bit
);
1396 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1402 static void translate_bbi(DisasContext
*dc
, const uint32_t arg
[],
1403 const uint32_t par
[])
1405 if (gen_window_check1(dc
, arg
[0])) {
1406 TCGv_i32 tmp
= tcg_temp_new_i32();
1407 #ifdef TARGET_WORDS_BIGENDIAN
1408 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[0]], 0x80000000u
>> arg
[1]);
1410 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[0]], 0x00000001u
<< arg
[1]);
1412 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1417 static void translate_bi(DisasContext
*dc
, const uint32_t arg
[],
1418 const uint32_t par
[])
1420 if (gen_window_check1(dc
, arg
[0])) {
1421 gen_brcondi(dc
, par
[0], cpu_R
[arg
[0]], arg
[1], arg
[2]);
1425 static void translate_bz(DisasContext
*dc
, const uint32_t arg
[],
1426 const uint32_t par
[])
1428 if (gen_window_check1(dc
, arg
[0])) {
1429 gen_brcondi(dc
, par
[0], cpu_R
[arg
[0]], 0, arg
[1]);
1441 static void translate_boolean(DisasContext
*dc
, const uint32_t arg
[],
1442 const uint32_t par
[])
1444 static void (* const op
[])(TCGv_i32
, TCGv_i32
, TCGv_i32
) = {
1445 [BOOLEAN_AND
] = tcg_gen_and_i32
,
1446 [BOOLEAN_ANDC
] = tcg_gen_andc_i32
,
1447 [BOOLEAN_OR
] = tcg_gen_or_i32
,
1448 [BOOLEAN_ORC
] = tcg_gen_orc_i32
,
1449 [BOOLEAN_XOR
] = tcg_gen_xor_i32
,
1452 TCGv_i32 tmp1
= tcg_temp_new_i32();
1453 TCGv_i32 tmp2
= tcg_temp_new_i32();
1455 tcg_gen_shri_i32(tmp1
, cpu_SR
[BR
], arg
[1]);
1456 tcg_gen_shri_i32(tmp2
, cpu_SR
[BR
], arg
[2]);
1457 op
[par
[0]](tmp1
, tmp1
, tmp2
);
1458 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
], tmp1
, arg
[0], 1);
1459 tcg_temp_free(tmp1
);
1460 tcg_temp_free(tmp2
);
1463 static void translate_bp(DisasContext
*dc
, const uint32_t arg
[],
1464 const uint32_t par
[])
1466 TCGv_i32 tmp
= tcg_temp_new_i32();
1468 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[0]);
1469 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[1]);
1473 static void translate_break(DisasContext
*dc
, const uint32_t arg
[],
1474 const uint32_t par
[])
1477 gen_debug_exception(dc
, par
[0]);
1481 static void translate_call0(DisasContext
*dc
, const uint32_t arg
[],
1482 const uint32_t par
[])
1484 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1485 gen_jumpi(dc
, arg
[0], 0);
1488 static void translate_callw(DisasContext
*dc
, const uint32_t arg
[],
1489 const uint32_t par
[])
1491 if (gen_window_check1(dc
, par
[0] << 2)) {
1492 gen_callwi(dc
, par
[0], arg
[0], 0);
1496 static void translate_callx0(DisasContext
*dc
, const uint32_t arg
[],
1497 const uint32_t par
[])
1499 if (gen_window_check1(dc
, arg
[0])) {
1500 TCGv_i32 tmp
= tcg_temp_new_i32();
1501 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
1502 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1508 static void translate_callxw(DisasContext
*dc
, const uint32_t arg
[],
1509 const uint32_t par
[])
1511 if (gen_window_check2(dc
, arg
[0], par
[0] << 2)) {
1512 TCGv_i32 tmp
= tcg_temp_new_i32();
1514 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
1515 gen_callw(dc
, par
[0], tmp
);
1520 static void translate_clamps(DisasContext
*dc
, const uint32_t arg
[],
1521 const uint32_t par
[])
1523 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1524 TCGv_i32 tmp1
= tcg_const_i32(-1u << arg
[2]);
1525 TCGv_i32 tmp2
= tcg_const_i32((1 << arg
[2]) - 1);
1527 tcg_gen_smax_i32(tmp1
, tmp1
, cpu_R
[arg
[1]]);
1528 tcg_gen_smin_i32(cpu_R
[arg
[0]], tmp1
, tmp2
);
1529 tcg_temp_free(tmp1
);
1530 tcg_temp_free(tmp2
);
1534 static void translate_clrb_expstate(DisasContext
*dc
, const uint32_t arg
[],
1535 const uint32_t par
[])
1537 /* TODO: GPIO32 may be a part of coprocessor */
1538 tcg_gen_andi_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], ~(1u << arg
[0]));
1541 static void translate_const16(DisasContext
*dc
, const uint32_t arg
[],
1542 const uint32_t par
[])
1544 if (gen_window_check1(dc
, arg
[0])) {
1545 TCGv_i32 c
= tcg_const_i32(arg
[1]);
1547 tcg_gen_deposit_i32(cpu_R
[arg
[0]], c
, cpu_R
[arg
[0]], 16, 16);
1552 /* par[0]: privileged, par[1]: check memory access */
1553 static void translate_dcache(DisasContext
*dc
, const uint32_t arg
[],
1554 const uint32_t par
[])
1556 if ((!par
[0] || gen_check_privilege(dc
)) &&
1557 gen_window_check1(dc
, arg
[0]) && par
[1]) {
1558 TCGv_i32 addr
= tcg_temp_new_i32();
1559 TCGv_i32 res
= tcg_temp_new_i32();
1561 tcg_gen_addi_i32(addr
, cpu_R
[arg
[0]], arg
[1]);
1562 tcg_gen_qemu_ld8u(res
, addr
, dc
->cring
);
1563 tcg_temp_free(addr
);
1568 static void translate_depbits(DisasContext
*dc
, const uint32_t arg
[],
1569 const uint32_t par
[])
1571 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1572 tcg_gen_deposit_i32(cpu_R
[arg
[1]], cpu_R
[arg
[1]], cpu_R
[arg
[0]],
1577 static void translate_entry(DisasContext
*dc
, const uint32_t arg
[],
1578 const uint32_t par
[])
1580 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1581 TCGv_i32 s
= tcg_const_i32(arg
[0]);
1582 TCGv_i32 imm
= tcg_const_i32(arg
[1]);
1583 gen_helper_entry(cpu_env
, pc
, s
, imm
);
1587 /* This can change tb->flags, so exit tb */
1588 gen_jumpi_check_loop_end(dc
, -1);
1591 static void translate_extui(DisasContext
*dc
, const uint32_t arg
[],
1592 const uint32_t par
[])
1594 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1595 int maskimm
= (1 << arg
[3]) - 1;
1597 TCGv_i32 tmp
= tcg_temp_new_i32();
1598 tcg_gen_shri_i32(tmp
, cpu_R
[arg
[1]], arg
[2]);
1599 tcg_gen_andi_i32(cpu_R
[arg
[0]], tmp
, maskimm
);
1604 /* par[0]: privileged, par[1]: check memory access */
1605 static void translate_icache(DisasContext
*dc
, const uint32_t arg
[],
1606 const uint32_t par
[])
1608 if ((!par
[0] || gen_check_privilege(dc
)) &&
1609 gen_window_check1(dc
, arg
[0]) && par
[1]) {
1610 #ifndef CONFIG_USER_ONLY
1611 TCGv_i32 addr
= tcg_temp_new_i32();
1613 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1614 tcg_gen_addi_i32(addr
, cpu_R
[arg
[0]], arg
[1]);
1615 gen_helper_itlb_hit_test(cpu_env
, addr
);
1616 tcg_temp_free(addr
);
1621 static void translate_itlb(DisasContext
*dc
, const uint32_t arg
[],
1622 const uint32_t par
[])
1624 if (gen_check_privilege(dc
) &&
1625 gen_window_check1(dc
, arg
[0])) {
1626 #ifndef CONFIG_USER_ONLY
1627 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
1629 gen_helper_itlb(cpu_env
, cpu_R
[arg
[0]], dtlb
);
1630 /* This could change memory mapping, so exit tb */
1631 gen_jumpi_check_loop_end(dc
, -1);
1632 tcg_temp_free(dtlb
);
1637 static void translate_ill(DisasContext
*dc
, const uint32_t arg
[],
1638 const uint32_t par
[])
1640 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1643 static void translate_j(DisasContext
*dc
, const uint32_t arg
[],
1644 const uint32_t par
[])
1646 gen_jumpi(dc
, arg
[0], 0);
1649 static void translate_jx(DisasContext
*dc
, const uint32_t arg
[],
1650 const uint32_t par
[])
1652 if (gen_window_check1(dc
, arg
[0])) {
1653 gen_jump(dc
, cpu_R
[arg
[0]]);
1657 static void translate_l32e(DisasContext
*dc
, const uint32_t arg
[],
1658 const uint32_t par
[])
1660 if (gen_check_privilege(dc
) &&
1661 gen_window_check2(dc
, arg
[0], arg
[1])) {
1662 TCGv_i32 addr
= tcg_temp_new_i32();
1664 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
1665 gen_load_store_alignment(dc
, 2, addr
, false);
1666 tcg_gen_qemu_ld_tl(cpu_R
[arg
[0]], addr
, dc
->ring
, MO_TEUL
);
1667 tcg_temp_free(addr
);
1671 static void translate_ldst(DisasContext
*dc
, const uint32_t arg
[],
1672 const uint32_t par
[])
1674 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1675 TCGv_i32 addr
= tcg_temp_new_i32();
1677 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
1678 if (par
[0] & MO_SIZE
) {
1679 gen_load_store_alignment(dc
, par
[0] & MO_SIZE
, addr
, par
[1]);
1683 tcg_gen_mb(TCG_BAR_STRL
| TCG_MO_ALL
);
1685 tcg_gen_qemu_st_tl(cpu_R
[arg
[0]], addr
, dc
->cring
, par
[0]);
1687 tcg_gen_qemu_ld_tl(cpu_R
[arg
[0]], addr
, dc
->cring
, par
[0]);
1689 tcg_gen_mb(TCG_BAR_LDAQ
| TCG_MO_ALL
);
1692 tcg_temp_free(addr
);
1696 static void translate_l32r(DisasContext
*dc
, const uint32_t arg
[],
1697 const uint32_t par
[])
1699 if (gen_window_check1(dc
, arg
[0])) {
1702 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1703 tmp
= tcg_const_i32(dc
->raw_arg
[1] - 1);
1704 tcg_gen_add_i32(tmp
, cpu_SR
[LITBASE
], tmp
);
1706 tmp
= tcg_const_i32(arg
[1]);
1708 tcg_gen_qemu_ld32u(cpu_R
[arg
[0]], tmp
, dc
->cring
);
1713 static void translate_loop(DisasContext
*dc
, const uint32_t arg
[],
1714 const uint32_t par
[])
1716 if (gen_window_check1(dc
, arg
[0])) {
1717 uint32_t lend
= arg
[1];
1718 TCGv_i32 tmp
= tcg_const_i32(lend
);
1720 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[arg
[0]], 1);
1721 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
1722 gen_helper_wsr_lend(cpu_env
, tmp
);
1725 if (par
[0] != TCG_COND_NEVER
) {
1726 TCGLabel
*label
= gen_new_label();
1727 tcg_gen_brcondi_i32(par
[0], cpu_R
[arg
[0]], 0, label
);
1728 gen_jumpi(dc
, lend
, 1);
1729 gen_set_label(label
);
1732 gen_jumpi(dc
, dc
->next_pc
, 0);
1764 static void translate_mac16(DisasContext
*dc
, const uint32_t arg
[],
1765 const uint32_t par
[])
1768 bool is_m1_sr
= par
[1] & MAC16_DX
;
1769 bool is_m2_sr
= par
[1] & MAC16_XD
;
1770 unsigned half
= par
[2];
1771 uint32_t ld_offset
= par
[3];
1772 unsigned off
= ld_offset
? 2 : 0;
1773 uint32_t ar
[3] = {0};
1776 if (op
!= MAC16_NONE
) {
1778 ar
[n_ar
++] = arg
[off
];
1781 ar
[n_ar
++] = arg
[off
+ 1];
1786 ar
[n_ar
++] = arg
[1];
1789 if (gen_window_check3(dc
, ar
[0], ar
[1], ar
[2])) {
1790 TCGv_i32 vaddr
= tcg_temp_new_i32();
1791 TCGv_i32 mem32
= tcg_temp_new_i32();
1794 tcg_gen_addi_i32(vaddr
, cpu_R
[arg
[1]], ld_offset
);
1795 gen_load_store_alignment(dc
, 2, vaddr
, false);
1796 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
1798 if (op
!= MAC16_NONE
) {
1799 TCGv_i32 m1
= gen_mac16_m(is_m1_sr
?
1800 cpu_SR
[MR
+ arg
[off
]] :
1802 half
& MAC16_HX
, op
== MAC16_UMUL
);
1803 TCGv_i32 m2
= gen_mac16_m(is_m2_sr
?
1804 cpu_SR
[MR
+ arg
[off
+ 1]] :
1805 cpu_R
[arg
[off
+ 1]],
1806 half
& MAC16_XH
, op
== MAC16_UMUL
);
1808 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
1809 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
1810 if (op
== MAC16_UMUL
) {
1811 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
1813 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
1816 TCGv_i32 lo
= tcg_temp_new_i32();
1817 TCGv_i32 hi
= tcg_temp_new_i32();
1819 tcg_gen_mul_i32(lo
, m1
, m2
);
1820 tcg_gen_sari_i32(hi
, lo
, 31);
1821 if (op
== MAC16_MULA
) {
1822 tcg_gen_add2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1823 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1826 tcg_gen_sub2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1827 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1830 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
1832 tcg_temp_free_i32(lo
);
1833 tcg_temp_free_i32(hi
);
1839 tcg_gen_mov_i32(cpu_R
[arg
[1]], vaddr
);
1840 tcg_gen_mov_i32(cpu_SR
[MR
+ arg
[0]], mem32
);
1842 tcg_temp_free(vaddr
);
1843 tcg_temp_free(mem32
);
1847 static void translate_memw(DisasContext
*dc
, const uint32_t arg
[],
1848 const uint32_t par
[])
1850 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
1853 static void translate_smin(DisasContext
*dc
, const uint32_t arg
[],
1854 const uint32_t par
[])
1856 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1857 tcg_gen_smin_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1861 static void translate_umin(DisasContext
*dc
, const uint32_t arg
[],
1862 const uint32_t par
[])
1864 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1865 tcg_gen_umin_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1869 static void translate_smax(DisasContext
*dc
, const uint32_t arg
[],
1870 const uint32_t par
[])
1872 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1873 tcg_gen_smax_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1877 static void translate_umax(DisasContext
*dc
, const uint32_t arg
[],
1878 const uint32_t par
[])
1880 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1881 tcg_gen_umax_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1885 static void translate_mov(DisasContext
*dc
, const uint32_t arg
[],
1886 const uint32_t par
[])
1888 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1889 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1893 static void translate_movcond(DisasContext
*dc
, const uint32_t arg
[],
1894 const uint32_t par
[])
1896 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1897 TCGv_i32 zero
= tcg_const_i32(0);
1899 tcg_gen_movcond_i32(par
[0], cpu_R
[arg
[0]],
1900 cpu_R
[arg
[2]], zero
, cpu_R
[arg
[1]], cpu_R
[arg
[0]]);
1901 tcg_temp_free(zero
);
1905 static void translate_movi(DisasContext
*dc
, const uint32_t arg
[],
1906 const uint32_t par
[])
1908 if (gen_window_check1(dc
, arg
[0])) {
1909 tcg_gen_movi_i32(cpu_R
[arg
[0]], arg
[1]);
1913 static void translate_movp(DisasContext
*dc
, const uint32_t arg
[],
1914 const uint32_t par
[])
1916 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1917 TCGv_i32 zero
= tcg_const_i32(0);
1918 TCGv_i32 tmp
= tcg_temp_new_i32();
1920 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[2]);
1921 tcg_gen_movcond_i32(par
[0],
1922 cpu_R
[arg
[0]], tmp
, zero
,
1923 cpu_R
[arg
[1]], cpu_R
[arg
[0]]);
1925 tcg_temp_free(zero
);
1929 static void translate_movsp(DisasContext
*dc
, const uint32_t arg
[],
1930 const uint32_t par
[])
1932 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1933 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1934 gen_helper_movsp(cpu_env
, pc
);
1935 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1940 static void translate_mul16(DisasContext
*dc
, const uint32_t arg
[],
1941 const uint32_t par
[])
1943 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1944 TCGv_i32 v1
= tcg_temp_new_i32();
1945 TCGv_i32 v2
= tcg_temp_new_i32();
1948 tcg_gen_ext16s_i32(v1
, cpu_R
[arg
[1]]);
1949 tcg_gen_ext16s_i32(v2
, cpu_R
[arg
[2]]);
1951 tcg_gen_ext16u_i32(v1
, cpu_R
[arg
[1]]);
1952 tcg_gen_ext16u_i32(v2
, cpu_R
[arg
[2]]);
1954 tcg_gen_mul_i32(cpu_R
[arg
[0]], v1
, v2
);
1960 static void translate_mull(DisasContext
*dc
, const uint32_t arg
[],
1961 const uint32_t par
[])
1963 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1964 tcg_gen_mul_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1968 static void translate_mulh(DisasContext
*dc
, const uint32_t arg
[],
1969 const uint32_t par
[])
1971 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1972 TCGv_i32 lo
= tcg_temp_new();
1975 tcg_gen_muls2_i32(lo
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1977 tcg_gen_mulu2_i32(lo
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1983 static void translate_neg(DisasContext
*dc
, const uint32_t arg
[],
1984 const uint32_t par
[])
1986 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1987 tcg_gen_neg_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1991 static void translate_nop(DisasContext
*dc
, const uint32_t arg
[],
1992 const uint32_t par
[])
1996 static void translate_nsa(DisasContext
*dc
, const uint32_t arg
[],
1997 const uint32_t par
[])
1999 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2000 tcg_gen_clrsb_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2004 static void translate_nsau(DisasContext
*dc
, const uint32_t arg
[],
2005 const uint32_t par
[])
2007 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2008 tcg_gen_clzi_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], 32);
2012 static void translate_or(DisasContext
*dc
, const uint32_t arg
[],
2013 const uint32_t par
[])
2015 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2016 tcg_gen_or_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2020 static void translate_ptlb(DisasContext
*dc
, const uint32_t arg
[],
2021 const uint32_t par
[])
2023 if (gen_check_privilege(dc
) &&
2024 gen_window_check2(dc
, arg
[0], arg
[1])) {
2025 #ifndef CONFIG_USER_ONLY
2026 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2028 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2029 gen_helper_ptlb(cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], dtlb
);
2030 tcg_temp_free(dtlb
);
2035 static void gen_zero_check(DisasContext
*dc
, const uint32_t arg
[])
2037 TCGLabel
*label
= gen_new_label();
2039 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[2]], 0, label
);
2040 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
2041 gen_set_label(label
);
2044 static void translate_quos(DisasContext
*dc
, const uint32_t arg
[],
2045 const uint32_t par
[])
2047 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2048 TCGLabel
*label1
= gen_new_label();
2049 TCGLabel
*label2
= gen_new_label();
2051 gen_zero_check(dc
, arg
);
2053 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[1]], 0x80000000,
2055 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[2]], 0xffffffff,
2057 tcg_gen_movi_i32(cpu_R
[arg
[0]],
2058 par
[0] ? 0x80000000 : 0);
2060 gen_set_label(label1
);
2062 tcg_gen_div_i32(cpu_R
[arg
[0]],
2063 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2065 tcg_gen_rem_i32(cpu_R
[arg
[0]],
2066 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2068 gen_set_label(label2
);
2072 static void translate_quou(DisasContext
*dc
, const uint32_t arg
[],
2073 const uint32_t par
[])
2075 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2076 gen_zero_check(dc
, arg
);
2078 tcg_gen_divu_i32(cpu_R
[arg
[0]],
2079 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2081 tcg_gen_remu_i32(cpu_R
[arg
[0]],
2082 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2087 static void translate_read_impwire(DisasContext
*dc
, const uint32_t arg
[],
2088 const uint32_t par
[])
2090 if (gen_window_check1(dc
, arg
[0])) {
2091 /* TODO: GPIO32 may be a part of coprocessor */
2092 tcg_gen_movi_i32(cpu_R
[arg
[0]], 0);
2096 static void translate_rer(DisasContext
*dc
, const uint32_t arg
[],
2097 const uint32_t par
[])
2099 if (gen_check_privilege(dc
) &&
2100 gen_window_check2(dc
, arg
[0], arg
[1])) {
2101 gen_helper_rer(cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]]);
2105 static void translate_ret(DisasContext
*dc
, const uint32_t arg
[],
2106 const uint32_t par
[])
2108 gen_jump(dc
, cpu_R
[0]);
2111 static void translate_retw(DisasContext
*dc
, const uint32_t arg
[],
2112 const uint32_t par
[])
2114 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2115 gen_helper_retw(tmp
, cpu_env
, tmp
);
2120 static void translate_rfde(DisasContext
*dc
, const uint32_t arg
[],
2121 const uint32_t par
[])
2123 if (gen_check_privilege(dc
)) {
2124 gen_jump(dc
, cpu_SR
[dc
->config
->ndepc
? DEPC
: EPC1
]);
2128 static void translate_rfe(DisasContext
*dc
, const uint32_t arg
[],
2129 const uint32_t par
[])
2131 if (gen_check_privilege(dc
)) {
2132 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2133 gen_check_interrupts(dc
);
2134 gen_jump(dc
, cpu_SR
[EPC1
]);
2138 static void translate_rfi(DisasContext
*dc
, const uint32_t arg
[],
2139 const uint32_t par
[])
2141 if (gen_check_privilege(dc
)) {
2142 tcg_gen_mov_i32(cpu_SR
[PS
], cpu_SR
[EPS2
+ arg
[0] - 2]);
2143 gen_check_interrupts(dc
);
2144 gen_jump(dc
, cpu_SR
[EPC1
+ arg
[0] - 1]);
2148 static void translate_rfw(DisasContext
*dc
, const uint32_t arg
[],
2149 const uint32_t par
[])
2151 if (gen_check_privilege(dc
)) {
2152 TCGv_i32 tmp
= tcg_const_i32(1);
2154 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2155 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
2158 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
2159 cpu_SR
[WINDOW_START
], tmp
);
2161 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
2162 cpu_SR
[WINDOW_START
], tmp
);
2165 gen_helper_restore_owb(cpu_env
);
2166 gen_check_interrupts(dc
);
2167 gen_jump(dc
, cpu_SR
[EPC1
]);
2173 static void translate_rotw(DisasContext
*dc
, const uint32_t arg
[],
2174 const uint32_t par
[])
2176 if (gen_check_privilege(dc
)) {
2177 TCGv_i32 tmp
= tcg_const_i32(arg
[0]);
2178 gen_helper_rotw(cpu_env
, tmp
);
2180 /* This can change tb->flags, so exit tb */
2181 gen_jumpi_check_loop_end(dc
, -1);
2185 static void translate_rsil(DisasContext
*dc
, const uint32_t arg
[],
2186 const uint32_t par
[])
2188 if (gen_check_privilege(dc
) &&
2189 gen_window_check1(dc
, arg
[0])) {
2190 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_SR
[PS
]);
2191 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
2192 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], arg
[1]);
2193 gen_check_interrupts(dc
);
2194 gen_jumpi_check_loop_end(dc
, 0);
2198 static void translate_rsr(DisasContext
*dc
, const uint32_t arg
[],
2199 const uint32_t par
[])
2201 if (gen_check_sr(dc
, par
[0], SR_R
) &&
2202 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2203 gen_window_check1(dc
, arg
[0])) {
2204 if (gen_rsr(dc
, cpu_R
[arg
[0]], par
[0])) {
2205 gen_jumpi_check_loop_end(dc
, 0);
2210 static void translate_rtlb(DisasContext
*dc
, const uint32_t arg
[],
2211 const uint32_t par
[])
2213 static void (* const helper
[])(TCGv_i32 r
, TCGv_env env
, TCGv_i32 a1
,
2215 #ifndef CONFIG_USER_ONLY
2221 if (gen_check_privilege(dc
) &&
2222 gen_window_check2(dc
, arg
[0], arg
[1])) {
2223 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2225 helper
[par
[1]](cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], dtlb
);
2226 tcg_temp_free(dtlb
);
2230 static void translate_rur(DisasContext
*dc
, const uint32_t arg
[],
2231 const uint32_t par
[])
2233 if (gen_window_check1(dc
, arg
[0])) {
2234 if (uregnames
[par
[0]].name
) {
2235 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_UR
[par
[0]]);
2237 qemu_log_mask(LOG_UNIMP
, "RUR %d not implemented\n", par
[0]);
2242 static void translate_setb_expstate(DisasContext
*dc
, const uint32_t arg
[],
2243 const uint32_t par
[])
2245 /* TODO: GPIO32 may be a part of coprocessor */
2246 tcg_gen_ori_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], 1u << arg
[0]);
2249 #ifdef CONFIG_USER_ONLY
2250 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2254 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2256 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
2258 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2263 static void translate_s32c1i(DisasContext
*dc
, const uint32_t arg
[],
2264 const uint32_t par
[])
2266 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2267 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2268 TCGv_i32 addr
= tcg_temp_local_new_i32();
2270 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
2271 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
2272 gen_load_store_alignment(dc
, 2, addr
, true);
2273 gen_check_atomctl(dc
, addr
);
2274 tcg_gen_atomic_cmpxchg_i32(cpu_R
[arg
[0]], addr
, cpu_SR
[SCOMPARE1
],
2275 tmp
, dc
->cring
, MO_32
);
2276 tcg_temp_free(addr
);
2281 static void translate_s32e(DisasContext
*dc
, const uint32_t arg
[],
2282 const uint32_t par
[])
2284 if (gen_check_privilege(dc
) &&
2285 gen_window_check2(dc
, arg
[0], arg
[1])) {
2286 TCGv_i32 addr
= tcg_temp_new_i32();
2288 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
2289 gen_load_store_alignment(dc
, 2, addr
, false);
2290 tcg_gen_qemu_st_tl(cpu_R
[arg
[0]], addr
, dc
->ring
, MO_TEUL
);
2291 tcg_temp_free(addr
);
2295 static void translate_salt(DisasContext
*dc
, const uint32_t arg
[],
2296 const uint32_t par
[])
2298 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2299 tcg_gen_setcond_i32(par
[0],
2301 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2305 static void translate_sext(DisasContext
*dc
, const uint32_t arg
[],
2306 const uint32_t par
[])
2308 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2309 int shift
= 31 - arg
[2];
2312 tcg_gen_ext8s_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2313 } else if (shift
== 16) {
2314 tcg_gen_ext16s_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2316 TCGv_i32 tmp
= tcg_temp_new_i32();
2317 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], shift
);
2318 tcg_gen_sari_i32(cpu_R
[arg
[0]], tmp
, shift
);
2324 static void translate_simcall(DisasContext
*dc
, const uint32_t arg
[],
2325 const uint32_t par
[])
2327 #ifndef CONFIG_USER_ONLY
2328 if (semihosting_enabled()) {
2329 if (gen_check_privilege(dc
)) {
2330 gen_helper_simcall(cpu_env
);
2335 qemu_log_mask(LOG_GUEST_ERROR
, "SIMCALL but semihosting is disabled\n");
2336 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2341 * Note: 64 bit ops are used here solely because SAR values
2344 #define gen_shift_reg(cmd, reg) do { \
2345 TCGv_i64 tmp = tcg_temp_new_i64(); \
2346 tcg_gen_extu_i32_i64(tmp, reg); \
2347 tcg_gen_##cmd##_i64(v, v, tmp); \
2348 tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \
2349 tcg_temp_free_i64(v); \
2350 tcg_temp_free_i64(tmp); \
2353 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2355 static void translate_sll(DisasContext
*dc
, const uint32_t arg
[],
2356 const uint32_t par
[])
2358 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2359 if (dc
->sar_m32_5bit
) {
2360 tcg_gen_shl_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], dc
->sar_m32
);
2362 TCGv_i64 v
= tcg_temp_new_i64();
2363 TCGv_i32 s
= tcg_const_i32(32);
2364 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
2365 tcg_gen_andi_i32(s
, s
, 0x3f);
2366 tcg_gen_extu_i32_i64(v
, cpu_R
[arg
[1]]);
2367 gen_shift_reg(shl
, s
);
2373 static void translate_slli(DisasContext
*dc
, const uint32_t arg
[],
2374 const uint32_t par
[])
2376 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2378 qemu_log_mask(LOG_GUEST_ERROR
, "slli a%d, a%d, 32 is undefined\n",
2381 tcg_gen_shli_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2] & 0x1f);
2385 static void translate_sra(DisasContext
*dc
, const uint32_t arg
[],
2386 const uint32_t par
[])
2388 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2389 if (dc
->sar_m32_5bit
) {
2390 tcg_gen_sar_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_SR
[SAR
]);
2392 TCGv_i64 v
= tcg_temp_new_i64();
2393 tcg_gen_ext_i32_i64(v
, cpu_R
[arg
[1]]);
2399 static void translate_srai(DisasContext
*dc
, const uint32_t arg
[],
2400 const uint32_t par
[])
2402 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2403 tcg_gen_sari_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
2407 static void translate_src(DisasContext
*dc
, const uint32_t arg
[],
2408 const uint32_t par
[])
2410 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2411 TCGv_i64 v
= tcg_temp_new_i64();
2412 tcg_gen_concat_i32_i64(v
, cpu_R
[arg
[2]], cpu_R
[arg
[1]]);
2417 static void translate_srl(DisasContext
*dc
, const uint32_t arg
[],
2418 const uint32_t par
[])
2420 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2421 if (dc
->sar_m32_5bit
) {
2422 tcg_gen_shr_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_SR
[SAR
]);
2424 TCGv_i64 v
= tcg_temp_new_i64();
2425 tcg_gen_extu_i32_i64(v
, cpu_R
[arg
[1]]);
2432 #undef gen_shift_reg
2434 static void translate_srli(DisasContext
*dc
, const uint32_t arg
[],
2435 const uint32_t par
[])
2437 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2438 tcg_gen_shri_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
2442 static void translate_ssa8b(DisasContext
*dc
, const uint32_t arg
[],
2443 const uint32_t par
[])
2445 if (gen_window_check1(dc
, arg
[0])) {
2446 TCGv_i32 tmp
= tcg_temp_new_i32();
2447 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[0]], 3);
2448 gen_left_shift_sar(dc
, tmp
);
2453 static void translate_ssa8l(DisasContext
*dc
, const uint32_t arg
[],
2454 const uint32_t par
[])
2456 if (gen_window_check1(dc
, arg
[0])) {
2457 TCGv_i32 tmp
= tcg_temp_new_i32();
2458 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[0]], 3);
2459 gen_right_shift_sar(dc
, tmp
);
2464 static void translate_ssai(DisasContext
*dc
, const uint32_t arg
[],
2465 const uint32_t par
[])
2467 TCGv_i32 tmp
= tcg_const_i32(arg
[0]);
2468 gen_right_shift_sar(dc
, tmp
);
2472 static void translate_ssl(DisasContext
*dc
, const uint32_t arg
[],
2473 const uint32_t par
[])
2475 if (gen_window_check1(dc
, arg
[0])) {
2476 gen_left_shift_sar(dc
, cpu_R
[arg
[0]]);
2480 static void translate_ssr(DisasContext
*dc
, const uint32_t arg
[],
2481 const uint32_t par
[])
2483 if (gen_window_check1(dc
, arg
[0])) {
2484 gen_right_shift_sar(dc
, cpu_R
[arg
[0]]);
2488 static void translate_sub(DisasContext
*dc
, const uint32_t arg
[],
2489 const uint32_t par
[])
2491 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2492 tcg_gen_sub_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2496 static void translate_subx(DisasContext
*dc
, const uint32_t arg
[],
2497 const uint32_t par
[])
2499 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2500 TCGv_i32 tmp
= tcg_temp_new_i32();
2501 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], par
[0]);
2502 tcg_gen_sub_i32(cpu_R
[arg
[0]], tmp
, cpu_R
[arg
[2]]);
2507 static void translate_syscall(DisasContext
*dc
, const uint32_t arg
[],
2508 const uint32_t par
[])
2510 gen_exception_cause(dc
, SYSCALL_CAUSE
);
2513 static void translate_waiti(DisasContext
*dc
, const uint32_t arg
[],
2514 const uint32_t par
[])
2516 if (gen_check_privilege(dc
)) {
2517 #ifndef CONFIG_USER_ONLY
2518 gen_waiti(dc
, arg
[0]);
2523 static void translate_wtlb(DisasContext
*dc
, const uint32_t arg
[],
2524 const uint32_t par
[])
2526 if (gen_check_privilege(dc
) &&
2527 gen_window_check2(dc
, arg
[0], arg
[1])) {
2528 #ifndef CONFIG_USER_ONLY
2529 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2531 gen_helper_wtlb(cpu_env
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], dtlb
);
2532 /* This could change memory mapping, so exit tb */
2533 gen_jumpi_check_loop_end(dc
, -1);
2534 tcg_temp_free(dtlb
);
2539 static void translate_wer(DisasContext
*dc
, const uint32_t arg
[],
2540 const uint32_t par
[])
2542 if (gen_check_privilege(dc
) &&
2543 gen_window_check2(dc
, arg
[0], arg
[1])) {
2544 gen_helper_wer(cpu_env
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2548 static void translate_wrmsk_expstate(DisasContext
*dc
, const uint32_t arg
[],
2549 const uint32_t par
[])
2551 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2552 /* TODO: GPIO32 may be a part of coprocessor */
2553 tcg_gen_and_i32(cpu_UR
[EXPSTATE
], cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2557 static void translate_wsr(DisasContext
*dc
, const uint32_t arg
[],
2558 const uint32_t par
[])
2560 if (gen_check_sr(dc
, par
[0], SR_W
) &&
2561 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2562 gen_window_check1(dc
, arg
[0])) {
2563 gen_wsr(dc
, par
[0], cpu_R
[arg
[0]]);
2567 static void translate_wur(DisasContext
*dc
, const uint32_t arg
[],
2568 const uint32_t par
[])
2570 if (gen_window_check1(dc
, arg
[0])) {
2571 if (uregnames
[par
[0]].name
) {
2572 gen_wur(par
[0], cpu_R
[arg
[0]]);
2574 qemu_log_mask(LOG_UNIMP
, "WUR %d not implemented\n", par
[0]);
2579 static void translate_xor(DisasContext
*dc
, const uint32_t arg
[],
2580 const uint32_t par
[])
2582 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2583 tcg_gen_xor_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2587 static void translate_xsr(DisasContext
*dc
, const uint32_t arg
[],
2588 const uint32_t par
[])
2590 if (gen_check_sr(dc
, par
[0], SR_X
) &&
2591 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2592 gen_window_check1(dc
, arg
[0])) {
2593 TCGv_i32 tmp
= tcg_temp_new_i32();
2594 bool rsr_end
, wsr_end
;
2596 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
2597 rsr_end
= gen_rsr(dc
, cpu_R
[arg
[0]], par
[0]);
2598 wsr_end
= gen_wsr(dc
, par
[0], tmp
);
2600 if (rsr_end
&& !wsr_end
) {
2601 gen_jumpi_check_loop_end(dc
, 0);
2606 static const XtensaOpcodeOps core_ops
[] = {
2609 .translate
= translate_abs
,
2612 .translate
= translate_add
,
2615 .translate
= translate_add
,
2618 .translate
= translate_addi
,
2621 .translate
= translate_addi
,
2624 .translate
= translate_addi
,
2627 .translate
= translate_addx
,
2628 .par
= (const uint32_t[]){1},
2631 .translate
= translate_addx
,
2632 .par
= (const uint32_t[]){2},
2635 .translate
= translate_addx
,
2636 .par
= (const uint32_t[]){3},
2639 .translate
= translate_all
,
2640 .par
= (const uint32_t[]){true, 4},
2643 .translate
= translate_all
,
2644 .par
= (const uint32_t[]){true, 8},
2647 .translate
= translate_and
,
2650 .translate
= translate_boolean
,
2651 .par
= (const uint32_t[]){BOOLEAN_AND
},
2654 .translate
= translate_boolean
,
2655 .par
= (const uint32_t[]){BOOLEAN_ANDC
},
2658 .translate
= translate_all
,
2659 .par
= (const uint32_t[]){false, 4},
2662 .translate
= translate_all
,
2663 .par
= (const uint32_t[]){false, 8},
2666 .translate
= translate_ball
,
2667 .par
= (const uint32_t[]){TCG_COND_EQ
},
2670 .translate
= translate_bany
,
2671 .par
= (const uint32_t[]){TCG_COND_NE
},
2674 .translate
= translate_bb
,
2675 .par
= (const uint32_t[]){TCG_COND_EQ
},
2678 .translate
= translate_bbi
,
2679 .par
= (const uint32_t[]){TCG_COND_EQ
},
2682 .translate
= translate_bb
,
2683 .par
= (const uint32_t[]){TCG_COND_NE
},
2686 .translate
= translate_bbi
,
2687 .par
= (const uint32_t[]){TCG_COND_NE
},
2690 .translate
= translate_b
,
2691 .par
= (const uint32_t[]){TCG_COND_EQ
},
2694 .translate
= translate_bi
,
2695 .par
= (const uint32_t[]){TCG_COND_EQ
},
2698 .translate
= translate_bz
,
2699 .par
= (const uint32_t[]){TCG_COND_EQ
},
2702 .translate
= translate_bz
,
2703 .par
= (const uint32_t[]){TCG_COND_EQ
},
2706 .translate
= translate_bp
,
2707 .par
= (const uint32_t[]){TCG_COND_EQ
},
2710 .translate
= translate_b
,
2711 .par
= (const uint32_t[]){TCG_COND_GE
},
2714 .translate
= translate_bi
,
2715 .par
= (const uint32_t[]){TCG_COND_GE
},
2718 .translate
= translate_b
,
2719 .par
= (const uint32_t[]){TCG_COND_GEU
},
2722 .translate
= translate_bi
,
2723 .par
= (const uint32_t[]){TCG_COND_GEU
},
2726 .translate
= translate_bz
,
2727 .par
= (const uint32_t[]){TCG_COND_GE
},
2730 .translate
= translate_b
,
2731 .par
= (const uint32_t[]){TCG_COND_LT
},
2734 .translate
= translate_bi
,
2735 .par
= (const uint32_t[]){TCG_COND_LT
},
2738 .translate
= translate_b
,
2739 .par
= (const uint32_t[]){TCG_COND_LTU
},
2742 .translate
= translate_bi
,
2743 .par
= (const uint32_t[]){TCG_COND_LTU
},
2746 .translate
= translate_bz
,
2747 .par
= (const uint32_t[]){TCG_COND_LT
},
2750 .translate
= translate_ball
,
2751 .par
= (const uint32_t[]){TCG_COND_NE
},
2754 .translate
= translate_b
,
2755 .par
= (const uint32_t[]){TCG_COND_NE
},
2758 .translate
= translate_bi
,
2759 .par
= (const uint32_t[]){TCG_COND_NE
},
2762 .translate
= translate_bz
,
2763 .par
= (const uint32_t[]){TCG_COND_NE
},
2766 .translate
= translate_bz
,
2767 .par
= (const uint32_t[]){TCG_COND_NE
},
2770 .translate
= translate_bany
,
2771 .par
= (const uint32_t[]){TCG_COND_EQ
},
2774 .translate
= translate_break
,
2775 .par
= (const uint32_t[]){DEBUGCAUSE_BI
},
2778 .translate
= translate_break
,
2779 .par
= (const uint32_t[]){DEBUGCAUSE_BN
},
2782 .translate
= translate_bp
,
2783 .par
= (const uint32_t[]){TCG_COND_NE
},
2786 .translate
= translate_call0
,
2789 .translate
= translate_callw
,
2790 .par
= (const uint32_t[]){3},
2793 .translate
= translate_callw
,
2794 .par
= (const uint32_t[]){1},
2797 .translate
= translate_callw
,
2798 .par
= (const uint32_t[]){2},
2801 .translate
= translate_callx0
,
2804 .translate
= translate_callxw
,
2805 .par
= (const uint32_t[]){3},
2808 .translate
= translate_callxw
,
2809 .par
= (const uint32_t[]){1},
2812 .translate
= translate_callxw
,
2813 .par
= (const uint32_t[]){2},
2816 .translate
= translate_clamps
,
2818 .name
= "clrb_expstate",
2819 .translate
= translate_clrb_expstate
,
2822 .translate
= translate_const16
,
2825 .translate
= translate_depbits
,
2828 .translate
= translate_dcache
,
2829 .par
= (const uint32_t[]){true, true},
2832 .translate
= translate_dcache
,
2833 .par
= (const uint32_t[]){true, true},
2836 .translate
= translate_dcache
,
2837 .par
= (const uint32_t[]){false, true},
2840 .translate
= translate_dcache
,
2841 .par
= (const uint32_t[]){false, true},
2844 .translate
= translate_dcache
,
2845 .par
= (const uint32_t[]){true, false},
2848 .translate
= translate_dcache
,
2849 .par
= (const uint32_t[]){true, false},
2852 .translate
= translate_dcache
,
2853 .par
= (const uint32_t[]){true, false},
2856 .translate
= translate_dcache
,
2857 .par
= (const uint32_t[]){true, false},
2860 .translate
= translate_dcache
,
2861 .par
= (const uint32_t[]){true, true},
2864 .translate
= translate_dcache
,
2865 .par
= (const uint32_t[]){false, false},
2868 .translate
= translate_dcache
,
2869 .par
= (const uint32_t[]){false, false},
2872 .translate
= translate_dcache
,
2873 .par
= (const uint32_t[]){false, false},
2876 .translate
= translate_dcache
,
2877 .par
= (const uint32_t[]){false, false},
2880 .translate
= translate_nop
,
2883 .translate
= translate_entry
,
2886 .translate
= translate_nop
,
2889 .translate
= translate_nop
,
2892 .translate
= translate_extui
,
2895 .translate
= translate_memw
,
2898 .translate
= translate_ill
,
2901 .translate
= translate_ill
,
2904 .translate
= translate_itlb
,
2905 .par
= (const uint32_t[]){true},
2908 .translate
= translate_icache
,
2909 .par
= (const uint32_t[]){false, true},
2912 .translate
= translate_icache
,
2913 .par
= (const uint32_t[]){true, true},
2916 .translate
= translate_icache
,
2917 .par
= (const uint32_t[]){true, false},
2920 .translate
= translate_itlb
,
2921 .par
= (const uint32_t[]){false},
2924 .translate
= translate_icache
,
2925 .par
= (const uint32_t[]){true, false},
2928 .translate
= translate_ill
,
2931 .translate
= translate_ill
,
2934 .translate
= translate_icache
,
2935 .par
= (const uint32_t[]){false, false},
2938 .translate
= translate_icache
,
2939 .par
= (const uint32_t[]){true, true},
2942 .translate
= translate_nop
,
2945 .translate
= translate_j
,
2948 .translate
= translate_jx
,
2951 .translate
= translate_ldst
,
2952 .par
= (const uint32_t[]){MO_TESW
, false, false},
2955 .translate
= translate_ldst
,
2956 .par
= (const uint32_t[]){MO_TEUW
, false, false},
2959 .translate
= translate_ldst
,
2960 .par
= (const uint32_t[]){MO_TEUL
, true, false},
2963 .translate
= translate_l32e
,
2966 .translate
= translate_ldst
,
2967 .par
= (const uint32_t[]){MO_TEUL
, false, false},
2970 .translate
= translate_ldst
,
2971 .par
= (const uint32_t[]){MO_TEUL
, false, false},
2974 .translate
= translate_l32r
,
2977 .translate
= translate_ldst
,
2978 .par
= (const uint32_t[]){MO_UB
, false, false},
2981 .translate
= translate_mac16
,
2982 .par
= (const uint32_t[]){MAC16_NONE
, 0, 0, -4},
2985 .translate
= translate_mac16
,
2986 .par
= (const uint32_t[]){MAC16_NONE
, 0, 0, 4},
2989 .translate
= translate_ill
,
2992 .translate
= translate_loop
,
2993 .par
= (const uint32_t[]){TCG_COND_NEVER
},
2996 .translate
= translate_loop
,
2997 .par
= (const uint32_t[]){TCG_COND_GT
},
3000 .translate
= translate_loop
,
3001 .par
= (const uint32_t[]){TCG_COND_NE
},
3004 .translate
= translate_smax
,
3007 .translate
= translate_umax
,
3010 .translate
= translate_memw
,
3013 .translate
= translate_smin
,
3016 .translate
= translate_umin
,
3019 .translate
= translate_mov
,
3022 .translate
= translate_mov
,
3025 .translate
= translate_movcond
,
3026 .par
= (const uint32_t[]){TCG_COND_EQ
},
3029 .translate
= translate_movp
,
3030 .par
= (const uint32_t[]){TCG_COND_EQ
},
3033 .translate
= translate_movcond
,
3034 .par
= (const uint32_t[]){TCG_COND_GE
},
3037 .translate
= translate_movi
,
3040 .translate
= translate_movi
,
3043 .translate
= translate_movcond
,
3044 .par
= (const uint32_t[]){TCG_COND_LT
},
3047 .translate
= translate_movcond
,
3048 .par
= (const uint32_t[]){TCG_COND_NE
},
3051 .translate
= translate_movsp
,
3054 .translate
= translate_movp
,
3055 .par
= (const uint32_t[]){TCG_COND_NE
},
3057 .name
= "mul.aa.hh",
3058 .translate
= translate_mac16
,
3059 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_HH
, 0},
3061 .name
= "mul.aa.hl",
3062 .translate
= translate_mac16
,
3063 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_HL
, 0},
3065 .name
= "mul.aa.lh",
3066 .translate
= translate_mac16
,
3067 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_LH
, 0},
3069 .name
= "mul.aa.ll",
3070 .translate
= translate_mac16
,
3071 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_LL
, 0},
3073 .name
= "mul.ad.hh",
3074 .translate
= translate_mac16
,
3075 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_HH
, 0},
3077 .name
= "mul.ad.hl",
3078 .translate
= translate_mac16
,
3079 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_HL
, 0},
3081 .name
= "mul.ad.lh",
3082 .translate
= translate_mac16
,
3083 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_LH
, 0},
3085 .name
= "mul.ad.ll",
3086 .translate
= translate_mac16
,
3087 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_LL
, 0},
3089 .name
= "mul.da.hh",
3090 .translate
= translate_mac16
,
3091 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_HH
, 0},
3093 .name
= "mul.da.hl",
3094 .translate
= translate_mac16
,
3095 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_HL
, 0},
3097 .name
= "mul.da.lh",
3098 .translate
= translate_mac16
,
3099 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_LH
, 0},
3101 .name
= "mul.da.ll",
3102 .translate
= translate_mac16
,
3103 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_LL
, 0},
3105 .name
= "mul.dd.hh",
3106 .translate
= translate_mac16
,
3107 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_HH
, 0},
3109 .name
= "mul.dd.hl",
3110 .translate
= translate_mac16
,
3111 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_HL
, 0},
3113 .name
= "mul.dd.lh",
3114 .translate
= translate_mac16
,
3115 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_LH
, 0},
3117 .name
= "mul.dd.ll",
3118 .translate
= translate_mac16
,
3119 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_LL
, 0},
3122 .translate
= translate_mul16
,
3123 .par
= (const uint32_t[]){true},
3126 .translate
= translate_mul16
,
3127 .par
= (const uint32_t[]){false},
3129 .name
= "mula.aa.hh",
3130 .translate
= translate_mac16
,
3131 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_HH
, 0},
3133 .name
= "mula.aa.hl",
3134 .translate
= translate_mac16
,
3135 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_HL
, 0},
3137 .name
= "mula.aa.lh",
3138 .translate
= translate_mac16
,
3139 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_LH
, 0},
3141 .name
= "mula.aa.ll",
3142 .translate
= translate_mac16
,
3143 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_LL
, 0},
3145 .name
= "mula.ad.hh",
3146 .translate
= translate_mac16
,
3147 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_HH
, 0},
3149 .name
= "mula.ad.hl",
3150 .translate
= translate_mac16
,
3151 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_HL
, 0},
3153 .name
= "mula.ad.lh",
3154 .translate
= translate_mac16
,
3155 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_LH
, 0},
3157 .name
= "mula.ad.ll",
3158 .translate
= translate_mac16
,
3159 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_LL
, 0},
3161 .name
= "mula.da.hh",
3162 .translate
= translate_mac16
,
3163 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, 0},
3165 .name
= "mula.da.hh.lddec",
3166 .translate
= translate_mac16
,
3167 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, -4},
3169 .name
= "mula.da.hh.ldinc",
3170 .translate
= translate_mac16
,
3171 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, 4},
3173 .name
= "mula.da.hl",
3174 .translate
= translate_mac16
,
3175 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, 0},
3177 .name
= "mula.da.hl.lddec",
3178 .translate
= translate_mac16
,
3179 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, -4},
3181 .name
= "mula.da.hl.ldinc",
3182 .translate
= translate_mac16
,
3183 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, 4},
3185 .name
= "mula.da.lh",
3186 .translate
= translate_mac16
,
3187 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, 0},
3189 .name
= "mula.da.lh.lddec",
3190 .translate
= translate_mac16
,
3191 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, -4},
3193 .name
= "mula.da.lh.ldinc",
3194 .translate
= translate_mac16
,
3195 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, 4},
3197 .name
= "mula.da.ll",
3198 .translate
= translate_mac16
,
3199 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, 0},
3201 .name
= "mula.da.ll.lddec",
3202 .translate
= translate_mac16
,
3203 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, -4},
3205 .name
= "mula.da.ll.ldinc",
3206 .translate
= translate_mac16
,
3207 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, 4},
3209 .name
= "mula.dd.hh",
3210 .translate
= translate_mac16
,
3211 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, 0},
3213 .name
= "mula.dd.hh.lddec",
3214 .translate
= translate_mac16
,
3215 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, -4},
3217 .name
= "mula.dd.hh.ldinc",
3218 .translate
= translate_mac16
,
3219 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, 4},
3221 .name
= "mula.dd.hl",
3222 .translate
= translate_mac16
,
3223 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, 0},
3225 .name
= "mula.dd.hl.lddec",
3226 .translate
= translate_mac16
,
3227 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, -4},
3229 .name
= "mula.dd.hl.ldinc",
3230 .translate
= translate_mac16
,
3231 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, 4},
3233 .name
= "mula.dd.lh",
3234 .translate
= translate_mac16
,
3235 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, 0},
3237 .name
= "mula.dd.lh.lddec",
3238 .translate
= translate_mac16
,
3239 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, -4},
3241 .name
= "mula.dd.lh.ldinc",
3242 .translate
= translate_mac16
,
3243 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, 4},
3245 .name
= "mula.dd.ll",
3246 .translate
= translate_mac16
,
3247 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, 0},
3249 .name
= "mula.dd.ll.lddec",
3250 .translate
= translate_mac16
,
3251 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, -4},
3253 .name
= "mula.dd.ll.ldinc",
3254 .translate
= translate_mac16
,
3255 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, 4},
3258 .translate
= translate_mull
,
3260 .name
= "muls.aa.hh",
3261 .translate
= translate_mac16
,
3262 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_HH
, 0},
3264 .name
= "muls.aa.hl",
3265 .translate
= translate_mac16
,
3266 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_HL
, 0},
3268 .name
= "muls.aa.lh",
3269 .translate
= translate_mac16
,
3270 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_LH
, 0},
3272 .name
= "muls.aa.ll",
3273 .translate
= translate_mac16
,
3274 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_LL
, 0},
3276 .name
= "muls.ad.hh",
3277 .translate
= translate_mac16
,
3278 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_HH
, 0},
3280 .name
= "muls.ad.hl",
3281 .translate
= translate_mac16
,
3282 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_HL
, 0},
3284 .name
= "muls.ad.lh",
3285 .translate
= translate_mac16
,
3286 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_LH
, 0},
3288 .name
= "muls.ad.ll",
3289 .translate
= translate_mac16
,
3290 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_LL
, 0},
3292 .name
= "muls.da.hh",
3293 .translate
= translate_mac16
,
3294 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_HH
, 0},
3296 .name
= "muls.da.hl",
3297 .translate
= translate_mac16
,
3298 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_HL
, 0},
3300 .name
= "muls.da.lh",
3301 .translate
= translate_mac16
,
3302 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_LH
, 0},
3304 .name
= "muls.da.ll",
3305 .translate
= translate_mac16
,
3306 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_LL
, 0},
3308 .name
= "muls.dd.hh",
3309 .translate
= translate_mac16
,
3310 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_HH
, 0},
3312 .name
= "muls.dd.hl",
3313 .translate
= translate_mac16
,
3314 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_HL
, 0},
3316 .name
= "muls.dd.lh",
3317 .translate
= translate_mac16
,
3318 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_LH
, 0},
3320 .name
= "muls.dd.ll",
3321 .translate
= translate_mac16
,
3322 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_LL
, 0},
3325 .translate
= translate_mulh
,
3326 .par
= (const uint32_t[]){true},
3329 .translate
= translate_mulh
,
3330 .par
= (const uint32_t[]){false},
3333 .translate
= translate_neg
,
3336 .translate
= translate_nop
,
3339 .translate
= translate_nop
,
3342 .translate
= translate_nsa
,
3345 .translate
= translate_nsau
,
3348 .translate
= translate_or
,
3351 .translate
= translate_boolean
,
3352 .par
= (const uint32_t[]){BOOLEAN_OR
},
3355 .translate
= translate_boolean
,
3356 .par
= (const uint32_t[]){BOOLEAN_ORC
},
3359 .translate
= translate_ptlb
,
3360 .par
= (const uint32_t[]){true},
3363 .translate
= translate_ptlb
,
3364 .par
= (const uint32_t[]){false},
3367 .translate
= translate_quos
,
3368 .par
= (const uint32_t[]){true},
3371 .translate
= translate_quou
,
3372 .par
= (const uint32_t[]){true},
3375 .translate
= translate_rtlb
,
3376 .par
= (const uint32_t[]){true, 0},
3379 .translate
= translate_rtlb
,
3380 .par
= (const uint32_t[]){true, 1},
3382 .name
= "read_impwire",
3383 .translate
= translate_read_impwire
,
3386 .translate
= translate_quos
,
3387 .par
= (const uint32_t[]){false},
3390 .translate
= translate_quou
,
3391 .par
= (const uint32_t[]){false},
3394 .translate
= translate_rer
,
3397 .translate
= translate_ret
,
3400 .translate
= translate_ret
,
3403 .translate
= translate_retw
,
3406 .translate
= translate_retw
,
3409 .translate
= translate_ill
,
3412 .translate
= translate_rfde
,
3415 .translate
= translate_ill
,
3418 .translate
= translate_rfe
,
3421 .translate
= translate_rfi
,
3424 .translate
= translate_rfw
,
3425 .par
= (const uint32_t[]){true},
3428 .translate
= translate_rfw
,
3429 .par
= (const uint32_t[]){false},
3432 .translate
= translate_rtlb
,
3433 .par
= (const uint32_t[]){false, 0},
3436 .translate
= translate_rtlb
,
3437 .par
= (const uint32_t[]){false, 1},
3440 .translate
= translate_rotw
,
3443 .translate
= translate_rsil
,
3446 .translate
= translate_rsr
,
3447 .par
= (const uint32_t[]){176},
3450 .translate
= translate_rsr
,
3451 .par
= (const uint32_t[]){208},
3453 .name
= "rsr.acchi",
3454 .translate
= translate_rsr
,
3455 .par
= (const uint32_t[]){ACCHI
},
3457 .name
= "rsr.acclo",
3458 .translate
= translate_rsr
,
3459 .par
= (const uint32_t[]){ACCLO
},
3461 .name
= "rsr.atomctl",
3462 .translate
= translate_rsr
,
3463 .par
= (const uint32_t[]){ATOMCTL
},
3466 .translate
= translate_rsr
,
3467 .par
= (const uint32_t[]){BR
},
3469 .name
= "rsr.cacheattr",
3470 .translate
= translate_rsr
,
3471 .par
= (const uint32_t[]){CACHEATTR
},
3473 .name
= "rsr.ccompare0",
3474 .translate
= translate_rsr
,
3475 .par
= (const uint32_t[]){CCOMPARE
},
3477 .name
= "rsr.ccompare1",
3478 .translate
= translate_rsr
,
3479 .par
= (const uint32_t[]){CCOMPARE
+ 1},
3481 .name
= "rsr.ccompare2",
3482 .translate
= translate_rsr
,
3483 .par
= (const uint32_t[]){CCOMPARE
+ 2},
3485 .name
= "rsr.ccount",
3486 .translate
= translate_rsr
,
3487 .par
= (const uint32_t[]){CCOUNT
},
3489 .name
= "rsr.configid0",
3490 .translate
= translate_rsr
,
3491 .par
= (const uint32_t[]){CONFIGID0
},
3493 .name
= "rsr.configid1",
3494 .translate
= translate_rsr
,
3495 .par
= (const uint32_t[]){CONFIGID1
},
3497 .name
= "rsr.cpenable",
3498 .translate
= translate_rsr
,
3499 .par
= (const uint32_t[]){CPENABLE
},
3501 .name
= "rsr.dbreaka0",
3502 .translate
= translate_rsr
,
3503 .par
= (const uint32_t[]){DBREAKA
},
3505 .name
= "rsr.dbreaka1",
3506 .translate
= translate_rsr
,
3507 .par
= (const uint32_t[]){DBREAKA
+ 1},
3509 .name
= "rsr.dbreakc0",
3510 .translate
= translate_rsr
,
3511 .par
= (const uint32_t[]){DBREAKC
},
3513 .name
= "rsr.dbreakc1",
3514 .translate
= translate_rsr
,
3515 .par
= (const uint32_t[]){DBREAKC
+ 1},
3518 .translate
= translate_rsr
,
3519 .par
= (const uint32_t[]){DDR
},
3521 .name
= "rsr.debugcause",
3522 .translate
= translate_rsr
,
3523 .par
= (const uint32_t[]){DEBUGCAUSE
},
3526 .translate
= translate_rsr
,
3527 .par
= (const uint32_t[]){DEPC
},
3529 .name
= "rsr.dtlbcfg",
3530 .translate
= translate_rsr
,
3531 .par
= (const uint32_t[]){DTLBCFG
},
3534 .translate
= translate_rsr
,
3535 .par
= (const uint32_t[]){EPC1
},
3538 .translate
= translate_rsr
,
3539 .par
= (const uint32_t[]){EPC1
+ 1},
3542 .translate
= translate_rsr
,
3543 .par
= (const uint32_t[]){EPC1
+ 2},
3546 .translate
= translate_rsr
,
3547 .par
= (const uint32_t[]){EPC1
+ 3},
3550 .translate
= translate_rsr
,
3551 .par
= (const uint32_t[]){EPC1
+ 4},
3554 .translate
= translate_rsr
,
3555 .par
= (const uint32_t[]){EPC1
+ 5},
3558 .translate
= translate_rsr
,
3559 .par
= (const uint32_t[]){EPC1
+ 6},
3562 .translate
= translate_rsr
,
3563 .par
= (const uint32_t[]){EPS2
},
3566 .translate
= translate_rsr
,
3567 .par
= (const uint32_t[]){EPS2
+ 1},
3570 .translate
= translate_rsr
,
3571 .par
= (const uint32_t[]){EPS2
+ 2},
3574 .translate
= translate_rsr
,
3575 .par
= (const uint32_t[]){EPS2
+ 3},
3578 .translate
= translate_rsr
,
3579 .par
= (const uint32_t[]){EPS2
+ 4},
3582 .translate
= translate_rsr
,
3583 .par
= (const uint32_t[]){EPS2
+ 5},
3585 .name
= "rsr.exccause",
3586 .translate
= translate_rsr
,
3587 .par
= (const uint32_t[]){EXCCAUSE
},
3589 .name
= "rsr.excsave1",
3590 .translate
= translate_rsr
,
3591 .par
= (const uint32_t[]){EXCSAVE1
},
3593 .name
= "rsr.excsave2",
3594 .translate
= translate_rsr
,
3595 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
3597 .name
= "rsr.excsave3",
3598 .translate
= translate_rsr
,
3599 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
3601 .name
= "rsr.excsave4",
3602 .translate
= translate_rsr
,
3603 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
3605 .name
= "rsr.excsave5",
3606 .translate
= translate_rsr
,
3607 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
3609 .name
= "rsr.excsave6",
3610 .translate
= translate_rsr
,
3611 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
3613 .name
= "rsr.excsave7",
3614 .translate
= translate_rsr
,
3615 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
3617 .name
= "rsr.excvaddr",
3618 .translate
= translate_rsr
,
3619 .par
= (const uint32_t[]){EXCVADDR
},
3621 .name
= "rsr.ibreaka0",
3622 .translate
= translate_rsr
,
3623 .par
= (const uint32_t[]){IBREAKA
},
3625 .name
= "rsr.ibreaka1",
3626 .translate
= translate_rsr
,
3627 .par
= (const uint32_t[]){IBREAKA
+ 1},
3629 .name
= "rsr.ibreakenable",
3630 .translate
= translate_rsr
,
3631 .par
= (const uint32_t[]){IBREAKENABLE
},
3633 .name
= "rsr.icount",
3634 .translate
= translate_rsr
,
3635 .par
= (const uint32_t[]){ICOUNT
},
3637 .name
= "rsr.icountlevel",
3638 .translate
= translate_rsr
,
3639 .par
= (const uint32_t[]){ICOUNTLEVEL
},
3641 .name
= "rsr.intclear",
3642 .translate
= translate_rsr
,
3643 .par
= (const uint32_t[]){INTCLEAR
},
3645 .name
= "rsr.intenable",
3646 .translate
= translate_rsr
,
3647 .par
= (const uint32_t[]){INTENABLE
},
3649 .name
= "rsr.interrupt",
3650 .translate
= translate_rsr
,
3651 .par
= (const uint32_t[]){INTSET
},
3653 .name
= "rsr.intset",
3654 .translate
= translate_rsr
,
3655 .par
= (const uint32_t[]){INTSET
},
3657 .name
= "rsr.itlbcfg",
3658 .translate
= translate_rsr
,
3659 .par
= (const uint32_t[]){ITLBCFG
},
3662 .translate
= translate_rsr
,
3663 .par
= (const uint32_t[]){LBEG
},
3665 .name
= "rsr.lcount",
3666 .translate
= translate_rsr
,
3667 .par
= (const uint32_t[]){LCOUNT
},
3670 .translate
= translate_rsr
,
3671 .par
= (const uint32_t[]){LEND
},
3673 .name
= "rsr.litbase",
3674 .translate
= translate_rsr
,
3675 .par
= (const uint32_t[]){LITBASE
},
3678 .translate
= translate_rsr
,
3679 .par
= (const uint32_t[]){MR
},
3682 .translate
= translate_rsr
,
3683 .par
= (const uint32_t[]){MR
+ 1},
3686 .translate
= translate_rsr
,
3687 .par
= (const uint32_t[]){MR
+ 2},
3690 .translate
= translate_rsr
,
3691 .par
= (const uint32_t[]){MR
+ 3},
3693 .name
= "rsr.memctl",
3694 .translate
= translate_rsr
,
3695 .par
= (const uint32_t[]){MEMCTL
},
3697 .name
= "rsr.misc0",
3698 .translate
= translate_rsr
,
3699 .par
= (const uint32_t[]){MISC
},
3701 .name
= "rsr.misc1",
3702 .translate
= translate_rsr
,
3703 .par
= (const uint32_t[]){MISC
+ 1},
3705 .name
= "rsr.misc2",
3706 .translate
= translate_rsr
,
3707 .par
= (const uint32_t[]){MISC
+ 2},
3709 .name
= "rsr.misc3",
3710 .translate
= translate_rsr
,
3711 .par
= (const uint32_t[]){MISC
+ 3},
3714 .translate
= translate_rsr
,
3715 .par
= (const uint32_t[]){PRID
},
3718 .translate
= translate_rsr
,
3719 .par
= (const uint32_t[]){PS
},
3721 .name
= "rsr.ptevaddr",
3722 .translate
= translate_rsr
,
3723 .par
= (const uint32_t[]){PTEVADDR
},
3725 .name
= "rsr.rasid",
3726 .translate
= translate_rsr
,
3727 .par
= (const uint32_t[]){RASID
},
3730 .translate
= translate_rsr
,
3731 .par
= (const uint32_t[]){SAR
},
3733 .name
= "rsr.scompare1",
3734 .translate
= translate_rsr
,
3735 .par
= (const uint32_t[]){SCOMPARE1
},
3737 .name
= "rsr.vecbase",
3738 .translate
= translate_rsr
,
3739 .par
= (const uint32_t[]){VECBASE
},
3741 .name
= "rsr.windowbase",
3742 .translate
= translate_rsr
,
3743 .par
= (const uint32_t[]){WINDOW_BASE
},
3745 .name
= "rsr.windowstart",
3746 .translate
= translate_rsr
,
3747 .par
= (const uint32_t[]){WINDOW_START
},
3750 .translate
= translate_nop
,
3752 .name
= "rur.expstate",
3753 .translate
= translate_rur
,
3754 .par
= (const uint32_t[]){EXPSTATE
},
3757 .translate
= translate_rur
,
3758 .par
= (const uint32_t[]){FCR
},
3761 .translate
= translate_rur
,
3762 .par
= (const uint32_t[]){FSR
},
3764 .name
= "rur.threadptr",
3765 .translate
= translate_rur
,
3766 .par
= (const uint32_t[]){THREADPTR
},
3769 .translate
= translate_ldst
,
3770 .par
= (const uint32_t[]){MO_TEUW
, false, true},
3773 .translate
= translate_s32c1i
,
3776 .translate
= translate_s32e
,
3779 .translate
= translate_ldst
,
3780 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3783 .translate
= translate_ldst
,
3784 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3787 .translate
= translate_ldst
,
3788 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3791 .translate
= translate_ldst
,
3792 .par
= (const uint32_t[]){MO_TEUL
, true, true},
3795 .translate
= translate_ldst
,
3796 .par
= (const uint32_t[]){MO_UB
, false, true},
3799 .translate
= translate_salt
,
3800 .par
= (const uint32_t[]){TCG_COND_LT
},
3803 .translate
= translate_salt
,
3804 .par
= (const uint32_t[]){TCG_COND_LTU
},
3806 .name
= "setb_expstate",
3807 .translate
= translate_setb_expstate
,
3810 .translate
= translate_sext
,
3813 .translate
= translate_simcall
,
3816 .translate
= translate_sll
,
3819 .translate
= translate_slli
,
3822 .translate
= translate_sra
,
3825 .translate
= translate_srai
,
3828 .translate
= translate_src
,
3831 .translate
= translate_srl
,
3834 .translate
= translate_srli
,
3837 .translate
= translate_ssa8b
,
3840 .translate
= translate_ssa8l
,
3843 .translate
= translate_ssai
,
3846 .translate
= translate_ssl
,
3849 .translate
= translate_ssr
,
3852 .translate
= translate_sub
,
3855 .translate
= translate_subx
,
3856 .par
= (const uint32_t[]){1},
3859 .translate
= translate_subx
,
3860 .par
= (const uint32_t[]){2},
3863 .translate
= translate_subx
,
3864 .par
= (const uint32_t[]){3},
3867 .translate
= translate_syscall
,
3869 .name
= "umul.aa.hh",
3870 .translate
= translate_mac16
,
3871 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_HH
, 0},
3873 .name
= "umul.aa.hl",
3874 .translate
= translate_mac16
,
3875 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_HL
, 0},
3877 .name
= "umul.aa.lh",
3878 .translate
= translate_mac16
,
3879 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_LH
, 0},
3881 .name
= "umul.aa.ll",
3882 .translate
= translate_mac16
,
3883 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_LL
, 0},
3886 .translate
= translate_waiti
,
3889 .translate
= translate_wtlb
,
3890 .par
= (const uint32_t[]){true},
3893 .translate
= translate_wer
,
3896 .translate
= translate_wtlb
,
3897 .par
= (const uint32_t[]){false},
3899 .name
= "wrmsk_expstate",
3900 .translate
= translate_wrmsk_expstate
,
3903 .translate
= translate_wsr
,
3904 .par
= (const uint32_t[]){176},
3907 .translate
= translate_wsr
,
3908 .par
= (const uint32_t[]){208},
3910 .name
= "wsr.acchi",
3911 .translate
= translate_wsr
,
3912 .par
= (const uint32_t[]){ACCHI
},
3914 .name
= "wsr.acclo",
3915 .translate
= translate_wsr
,
3916 .par
= (const uint32_t[]){ACCLO
},
3918 .name
= "wsr.atomctl",
3919 .translate
= translate_wsr
,
3920 .par
= (const uint32_t[]){ATOMCTL
},
3923 .translate
= translate_wsr
,
3924 .par
= (const uint32_t[]){BR
},
3926 .name
= "wsr.cacheattr",
3927 .translate
= translate_wsr
,
3928 .par
= (const uint32_t[]){CACHEATTR
},
3930 .name
= "wsr.ccompare0",
3931 .translate
= translate_wsr
,
3932 .par
= (const uint32_t[]){CCOMPARE
},
3934 .name
= "wsr.ccompare1",
3935 .translate
= translate_wsr
,
3936 .par
= (const uint32_t[]){CCOMPARE
+ 1},
3938 .name
= "wsr.ccompare2",
3939 .translate
= translate_wsr
,
3940 .par
= (const uint32_t[]){CCOMPARE
+ 2},
3942 .name
= "wsr.ccount",
3943 .translate
= translate_wsr
,
3944 .par
= (const uint32_t[]){CCOUNT
},
3946 .name
= "wsr.configid0",
3947 .translate
= translate_wsr
,
3948 .par
= (const uint32_t[]){CONFIGID0
},
3950 .name
= "wsr.configid1",
3951 .translate
= translate_wsr
,
3952 .par
= (const uint32_t[]){CONFIGID1
},
3954 .name
= "wsr.cpenable",
3955 .translate
= translate_wsr
,
3956 .par
= (const uint32_t[]){CPENABLE
},
3958 .name
= "wsr.dbreaka0",
3959 .translate
= translate_wsr
,
3960 .par
= (const uint32_t[]){DBREAKA
},
3962 .name
= "wsr.dbreaka1",
3963 .translate
= translate_wsr
,
3964 .par
= (const uint32_t[]){DBREAKA
+ 1},
3966 .name
= "wsr.dbreakc0",
3967 .translate
= translate_wsr
,
3968 .par
= (const uint32_t[]){DBREAKC
},
3970 .name
= "wsr.dbreakc1",
3971 .translate
= translate_wsr
,
3972 .par
= (const uint32_t[]){DBREAKC
+ 1},
3975 .translate
= translate_wsr
,
3976 .par
= (const uint32_t[]){DDR
},
3978 .name
= "wsr.debugcause",
3979 .translate
= translate_wsr
,
3980 .par
= (const uint32_t[]){DEBUGCAUSE
},
3983 .translate
= translate_wsr
,
3984 .par
= (const uint32_t[]){DEPC
},
3986 .name
= "wsr.dtlbcfg",
3987 .translate
= translate_wsr
,
3988 .par
= (const uint32_t[]){DTLBCFG
},
3991 .translate
= translate_wsr
,
3992 .par
= (const uint32_t[]){EPC1
},
3995 .translate
= translate_wsr
,
3996 .par
= (const uint32_t[]){EPC1
+ 1},
3999 .translate
= translate_wsr
,
4000 .par
= (const uint32_t[]){EPC1
+ 2},
4003 .translate
= translate_wsr
,
4004 .par
= (const uint32_t[]){EPC1
+ 3},
4007 .translate
= translate_wsr
,
4008 .par
= (const uint32_t[]){EPC1
+ 4},
4011 .translate
= translate_wsr
,
4012 .par
= (const uint32_t[]){EPC1
+ 5},
4015 .translate
= translate_wsr
,
4016 .par
= (const uint32_t[]){EPC1
+ 6},
4019 .translate
= translate_wsr
,
4020 .par
= (const uint32_t[]){EPS2
},
4023 .translate
= translate_wsr
,
4024 .par
= (const uint32_t[]){EPS2
+ 1},
4027 .translate
= translate_wsr
,
4028 .par
= (const uint32_t[]){EPS2
+ 2},
4031 .translate
= translate_wsr
,
4032 .par
= (const uint32_t[]){EPS2
+ 3},
4035 .translate
= translate_wsr
,
4036 .par
= (const uint32_t[]){EPS2
+ 4},
4039 .translate
= translate_wsr
,
4040 .par
= (const uint32_t[]){EPS2
+ 5},
4042 .name
= "wsr.exccause",
4043 .translate
= translate_wsr
,
4044 .par
= (const uint32_t[]){EXCCAUSE
},
4046 .name
= "wsr.excsave1",
4047 .translate
= translate_wsr
,
4048 .par
= (const uint32_t[]){EXCSAVE1
},
4050 .name
= "wsr.excsave2",
4051 .translate
= translate_wsr
,
4052 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
4054 .name
= "wsr.excsave3",
4055 .translate
= translate_wsr
,
4056 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
4058 .name
= "wsr.excsave4",
4059 .translate
= translate_wsr
,
4060 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
4062 .name
= "wsr.excsave5",
4063 .translate
= translate_wsr
,
4064 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
4066 .name
= "wsr.excsave6",
4067 .translate
= translate_wsr
,
4068 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
4070 .name
= "wsr.excsave7",
4071 .translate
= translate_wsr
,
4072 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
4074 .name
= "wsr.excvaddr",
4075 .translate
= translate_wsr
,
4076 .par
= (const uint32_t[]){EXCVADDR
},
4078 .name
= "wsr.ibreaka0",
4079 .translate
= translate_wsr
,
4080 .par
= (const uint32_t[]){IBREAKA
},
4082 .name
= "wsr.ibreaka1",
4083 .translate
= translate_wsr
,
4084 .par
= (const uint32_t[]){IBREAKA
+ 1},
4086 .name
= "wsr.ibreakenable",
4087 .translate
= translate_wsr
,
4088 .par
= (const uint32_t[]){IBREAKENABLE
},
4090 .name
= "wsr.icount",
4091 .translate
= translate_wsr
,
4092 .par
= (const uint32_t[]){ICOUNT
},
4094 .name
= "wsr.icountlevel",
4095 .translate
= translate_wsr
,
4096 .par
= (const uint32_t[]){ICOUNTLEVEL
},
4098 .name
= "wsr.intclear",
4099 .translate
= translate_wsr
,
4100 .par
= (const uint32_t[]){INTCLEAR
},
4102 .name
= "wsr.intenable",
4103 .translate
= translate_wsr
,
4104 .par
= (const uint32_t[]){INTENABLE
},
4106 .name
= "wsr.interrupt",
4107 .translate
= translate_wsr
,
4108 .par
= (const uint32_t[]){INTSET
},
4110 .name
= "wsr.intset",
4111 .translate
= translate_wsr
,
4112 .par
= (const uint32_t[]){INTSET
},
4114 .name
= "wsr.itlbcfg",
4115 .translate
= translate_wsr
,
4116 .par
= (const uint32_t[]){ITLBCFG
},
4119 .translate
= translate_wsr
,
4120 .par
= (const uint32_t[]){LBEG
},
4122 .name
= "wsr.lcount",
4123 .translate
= translate_wsr
,
4124 .par
= (const uint32_t[]){LCOUNT
},
4127 .translate
= translate_wsr
,
4128 .par
= (const uint32_t[]){LEND
},
4130 .name
= "wsr.litbase",
4131 .translate
= translate_wsr
,
4132 .par
= (const uint32_t[]){LITBASE
},
4135 .translate
= translate_wsr
,
4136 .par
= (const uint32_t[]){MR
},
4139 .translate
= translate_wsr
,
4140 .par
= (const uint32_t[]){MR
+ 1},
4143 .translate
= translate_wsr
,
4144 .par
= (const uint32_t[]){MR
+ 2},
4147 .translate
= translate_wsr
,
4148 .par
= (const uint32_t[]){MR
+ 3},
4150 .name
= "wsr.memctl",
4151 .translate
= translate_wsr
,
4152 .par
= (const uint32_t[]){MEMCTL
},
4154 .name
= "wsr.misc0",
4155 .translate
= translate_wsr
,
4156 .par
= (const uint32_t[]){MISC
},
4158 .name
= "wsr.misc1",
4159 .translate
= translate_wsr
,
4160 .par
= (const uint32_t[]){MISC
+ 1},
4162 .name
= "wsr.misc2",
4163 .translate
= translate_wsr
,
4164 .par
= (const uint32_t[]){MISC
+ 2},
4166 .name
= "wsr.misc3",
4167 .translate
= translate_wsr
,
4168 .par
= (const uint32_t[]){MISC
+ 3},
4171 .translate
= translate_wsr
,
4172 .par
= (const uint32_t[]){MMID
},
4175 .translate
= translate_wsr
,
4176 .par
= (const uint32_t[]){PRID
},
4179 .translate
= translate_wsr
,
4180 .par
= (const uint32_t[]){PS
},
4182 .name
= "wsr.ptevaddr",
4183 .translate
= translate_wsr
,
4184 .par
= (const uint32_t[]){PTEVADDR
},
4186 .name
= "wsr.rasid",
4187 .translate
= translate_wsr
,
4188 .par
= (const uint32_t[]){RASID
},
4191 .translate
= translate_wsr
,
4192 .par
= (const uint32_t[]){SAR
},
4194 .name
= "wsr.scompare1",
4195 .translate
= translate_wsr
,
4196 .par
= (const uint32_t[]){SCOMPARE1
},
4198 .name
= "wsr.vecbase",
4199 .translate
= translate_wsr
,
4200 .par
= (const uint32_t[]){VECBASE
},
4202 .name
= "wsr.windowbase",
4203 .translate
= translate_wsr
,
4204 .par
= (const uint32_t[]){WINDOW_BASE
},
4206 .name
= "wsr.windowstart",
4207 .translate
= translate_wsr
,
4208 .par
= (const uint32_t[]){WINDOW_START
},
4210 .name
= "wur.expstate",
4211 .translate
= translate_wur
,
4212 .par
= (const uint32_t[]){EXPSTATE
},
4215 .translate
= translate_wur
,
4216 .par
= (const uint32_t[]){FCR
},
4219 .translate
= translate_wur
,
4220 .par
= (const uint32_t[]){FSR
},
4222 .name
= "wur.threadptr",
4223 .translate
= translate_wur
,
4224 .par
= (const uint32_t[]){THREADPTR
},
4227 .translate
= translate_xor
,
4230 .translate
= translate_boolean
,
4231 .par
= (const uint32_t[]){BOOLEAN_XOR
},
4234 .translate
= translate_xsr
,
4235 .par
= (const uint32_t[]){176},
4238 .translate
= translate_xsr
,
4239 .par
= (const uint32_t[]){208},
4241 .name
= "xsr.acchi",
4242 .translate
= translate_xsr
,
4243 .par
= (const uint32_t[]){ACCHI
},
4245 .name
= "xsr.acclo",
4246 .translate
= translate_xsr
,
4247 .par
= (const uint32_t[]){ACCLO
},
4249 .name
= "xsr.atomctl",
4250 .translate
= translate_xsr
,
4251 .par
= (const uint32_t[]){ATOMCTL
},
4254 .translate
= translate_xsr
,
4255 .par
= (const uint32_t[]){BR
},
4257 .name
= "xsr.cacheattr",
4258 .translate
= translate_xsr
,
4259 .par
= (const uint32_t[]){CACHEATTR
},
4261 .name
= "xsr.ccompare0",
4262 .translate
= translate_xsr
,
4263 .par
= (const uint32_t[]){CCOMPARE
},
4265 .name
= "xsr.ccompare1",
4266 .translate
= translate_xsr
,
4267 .par
= (const uint32_t[]){CCOMPARE
+ 1},
4269 .name
= "xsr.ccompare2",
4270 .translate
= translate_xsr
,
4271 .par
= (const uint32_t[]){CCOMPARE
+ 2},
4273 .name
= "xsr.ccount",
4274 .translate
= translate_xsr
,
4275 .par
= (const uint32_t[]){CCOUNT
},
4277 .name
= "xsr.configid0",
4278 .translate
= translate_xsr
,
4279 .par
= (const uint32_t[]){CONFIGID0
},
4281 .name
= "xsr.configid1",
4282 .translate
= translate_xsr
,
4283 .par
= (const uint32_t[]){CONFIGID1
},
4285 .name
= "xsr.cpenable",
4286 .translate
= translate_xsr
,
4287 .par
= (const uint32_t[]){CPENABLE
},
4289 .name
= "xsr.dbreaka0",
4290 .translate
= translate_xsr
,
4291 .par
= (const uint32_t[]){DBREAKA
},
4293 .name
= "xsr.dbreaka1",
4294 .translate
= translate_xsr
,
4295 .par
= (const uint32_t[]){DBREAKA
+ 1},
4297 .name
= "xsr.dbreakc0",
4298 .translate
= translate_xsr
,
4299 .par
= (const uint32_t[]){DBREAKC
},
4301 .name
= "xsr.dbreakc1",
4302 .translate
= translate_xsr
,
4303 .par
= (const uint32_t[]){DBREAKC
+ 1},
4306 .translate
= translate_xsr
,
4307 .par
= (const uint32_t[]){DDR
},
4309 .name
= "xsr.debugcause",
4310 .translate
= translate_xsr
,
4311 .par
= (const uint32_t[]){DEBUGCAUSE
},
4314 .translate
= translate_xsr
,
4315 .par
= (const uint32_t[]){DEPC
},
4317 .name
= "xsr.dtlbcfg",
4318 .translate
= translate_xsr
,
4319 .par
= (const uint32_t[]){DTLBCFG
},
4322 .translate
= translate_xsr
,
4323 .par
= (const uint32_t[]){EPC1
},
4326 .translate
= translate_xsr
,
4327 .par
= (const uint32_t[]){EPC1
+ 1},
4330 .translate
= translate_xsr
,
4331 .par
= (const uint32_t[]){EPC1
+ 2},
4334 .translate
= translate_xsr
,
4335 .par
= (const uint32_t[]){EPC1
+ 3},
4338 .translate
= translate_xsr
,
4339 .par
= (const uint32_t[]){EPC1
+ 4},
4342 .translate
= translate_xsr
,
4343 .par
= (const uint32_t[]){EPC1
+ 5},
4346 .translate
= translate_xsr
,
4347 .par
= (const uint32_t[]){EPC1
+ 6},
4350 .translate
= translate_xsr
,
4351 .par
= (const uint32_t[]){EPS2
},
4354 .translate
= translate_xsr
,
4355 .par
= (const uint32_t[]){EPS2
+ 1},
4358 .translate
= translate_xsr
,
4359 .par
= (const uint32_t[]){EPS2
+ 2},
4362 .translate
= translate_xsr
,
4363 .par
= (const uint32_t[]){EPS2
+ 3},
4366 .translate
= translate_xsr
,
4367 .par
= (const uint32_t[]){EPS2
+ 4},
4370 .translate
= translate_xsr
,
4371 .par
= (const uint32_t[]){EPS2
+ 5},
4373 .name
= "xsr.exccause",
4374 .translate
= translate_xsr
,
4375 .par
= (const uint32_t[]){EXCCAUSE
},
4377 .name
= "xsr.excsave1",
4378 .translate
= translate_xsr
,
4379 .par
= (const uint32_t[]){EXCSAVE1
},
4381 .name
= "xsr.excsave2",
4382 .translate
= translate_xsr
,
4383 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
4385 .name
= "xsr.excsave3",
4386 .translate
= translate_xsr
,
4387 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
4389 .name
= "xsr.excsave4",
4390 .translate
= translate_xsr
,
4391 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
4393 .name
= "xsr.excsave5",
4394 .translate
= translate_xsr
,
4395 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
4397 .name
= "xsr.excsave6",
4398 .translate
= translate_xsr
,
4399 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
4401 .name
= "xsr.excsave7",
4402 .translate
= translate_xsr
,
4403 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
4405 .name
= "xsr.excvaddr",
4406 .translate
= translate_xsr
,
4407 .par
= (const uint32_t[]){EXCVADDR
},
4409 .name
= "xsr.ibreaka0",
4410 .translate
= translate_xsr
,
4411 .par
= (const uint32_t[]){IBREAKA
},
4413 .name
= "xsr.ibreaka1",
4414 .translate
= translate_xsr
,
4415 .par
= (const uint32_t[]){IBREAKA
+ 1},
4417 .name
= "xsr.ibreakenable",
4418 .translate
= translate_xsr
,
4419 .par
= (const uint32_t[]){IBREAKENABLE
},
4421 .name
= "xsr.icount",
4422 .translate
= translate_xsr
,
4423 .par
= (const uint32_t[]){ICOUNT
},
4425 .name
= "xsr.icountlevel",
4426 .translate
= translate_xsr
,
4427 .par
= (const uint32_t[]){ICOUNTLEVEL
},
4429 .name
= "xsr.intclear",
4430 .translate
= translate_xsr
,
4431 .par
= (const uint32_t[]){INTCLEAR
},
4433 .name
= "xsr.intenable",
4434 .translate
= translate_xsr
,
4435 .par
= (const uint32_t[]){INTENABLE
},
4437 .name
= "xsr.interrupt",
4438 .translate
= translate_xsr
,
4439 .par
= (const uint32_t[]){INTSET
},
4441 .name
= "xsr.intset",
4442 .translate
= translate_xsr
,
4443 .par
= (const uint32_t[]){INTSET
},
4445 .name
= "xsr.itlbcfg",
4446 .translate
= translate_xsr
,
4447 .par
= (const uint32_t[]){ITLBCFG
},
4450 .translate
= translate_xsr
,
4451 .par
= (const uint32_t[]){LBEG
},
4453 .name
= "xsr.lcount",
4454 .translate
= translate_xsr
,
4455 .par
= (const uint32_t[]){LCOUNT
},
4458 .translate
= translate_xsr
,
4459 .par
= (const uint32_t[]){LEND
},
4461 .name
= "xsr.litbase",
4462 .translate
= translate_xsr
,
4463 .par
= (const uint32_t[]){LITBASE
},
4466 .translate
= translate_xsr
,
4467 .par
= (const uint32_t[]){MR
},
4470 .translate
= translate_xsr
,
4471 .par
= (const uint32_t[]){MR
+ 1},
4474 .translate
= translate_xsr
,
4475 .par
= (const uint32_t[]){MR
+ 2},
4478 .translate
= translate_xsr
,
4479 .par
= (const uint32_t[]){MR
+ 3},
4481 .name
= "xsr.memctl",
4482 .translate
= translate_xsr
,
4483 .par
= (const uint32_t[]){MEMCTL
},
4485 .name
= "xsr.misc0",
4486 .translate
= translate_xsr
,
4487 .par
= (const uint32_t[]){MISC
},
4489 .name
= "xsr.misc1",
4490 .translate
= translate_xsr
,
4491 .par
= (const uint32_t[]){MISC
+ 1},
4493 .name
= "xsr.misc2",
4494 .translate
= translate_xsr
,
4495 .par
= (const uint32_t[]){MISC
+ 2},
4497 .name
= "xsr.misc3",
4498 .translate
= translate_xsr
,
4499 .par
= (const uint32_t[]){MISC
+ 3},
4502 .translate
= translate_xsr
,
4503 .par
= (const uint32_t[]){PRID
},
4506 .translate
= translate_xsr
,
4507 .par
= (const uint32_t[]){PS
},
4509 .name
= "xsr.ptevaddr",
4510 .translate
= translate_xsr
,
4511 .par
= (const uint32_t[]){PTEVADDR
},
4513 .name
= "xsr.rasid",
4514 .translate
= translate_xsr
,
4515 .par
= (const uint32_t[]){RASID
},
4518 .translate
= translate_xsr
,
4519 .par
= (const uint32_t[]){SAR
},
4521 .name
= "xsr.scompare1",
4522 .translate
= translate_xsr
,
4523 .par
= (const uint32_t[]){SCOMPARE1
},
4525 .name
= "xsr.vecbase",
4526 .translate
= translate_xsr
,
4527 .par
= (const uint32_t[]){VECBASE
},
4529 .name
= "xsr.windowbase",
4530 .translate
= translate_xsr
,
4531 .par
= (const uint32_t[]){WINDOW_BASE
},
4533 .name
= "xsr.windowstart",
4534 .translate
= translate_xsr
,
4535 .par
= (const uint32_t[]){WINDOW_START
},
4539 const XtensaOpcodeTranslators xtensa_core_opcodes
= {
4540 .num_opcodes
= ARRAY_SIZE(core_ops
),
4545 static void translate_abs_s(DisasContext
*dc
, const uint32_t arg
[],
4546 const uint32_t par
[])
4548 if (gen_check_cpenable(dc
, 0)) {
4549 gen_helper_abs_s(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4553 static void translate_add_s(DisasContext
*dc
, const uint32_t arg
[],
4554 const uint32_t par
[])
4556 if (gen_check_cpenable(dc
, 0)) {
4557 gen_helper_add_s(cpu_FR
[arg
[0]], cpu_env
,
4558 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4572 static void translate_compare_s(DisasContext
*dc
, const uint32_t arg
[],
4573 const uint32_t par
[])
4575 static void (* const helper
[])(TCGv_env env
, TCGv_i32 bit
,
4576 TCGv_i32 s
, TCGv_i32 t
) = {
4577 [COMPARE_UN
] = gen_helper_un_s
,
4578 [COMPARE_OEQ
] = gen_helper_oeq_s
,
4579 [COMPARE_UEQ
] = gen_helper_ueq_s
,
4580 [COMPARE_OLT
] = gen_helper_olt_s
,
4581 [COMPARE_ULT
] = gen_helper_ult_s
,
4582 [COMPARE_OLE
] = gen_helper_ole_s
,
4583 [COMPARE_ULE
] = gen_helper_ule_s
,
4586 if (gen_check_cpenable(dc
, 0)) {
4587 TCGv_i32 bit
= tcg_const_i32(1 << arg
[0]);
4589 helper
[par
[0]](cpu_env
, bit
, cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4594 static void translate_float_s(DisasContext
*dc
, const uint32_t arg
[],
4595 const uint32_t par
[])
4597 if (gen_window_check1(dc
, arg
[1]) && gen_check_cpenable(dc
, 0)) {
4598 TCGv_i32 scale
= tcg_const_i32(-arg
[2]);
4601 gen_helper_uitof(cpu_FR
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], scale
);
4603 gen_helper_itof(cpu_FR
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], scale
);
4605 tcg_temp_free(scale
);
4609 static void translate_ftoi_s(DisasContext
*dc
, const uint32_t arg
[],
4610 const uint32_t par
[])
4612 if (gen_window_check1(dc
, arg
[0]) && gen_check_cpenable(dc
, 0)) {
4613 TCGv_i32 rounding_mode
= tcg_const_i32(par
[0]);
4614 TCGv_i32 scale
= tcg_const_i32(arg
[2]);
4617 gen_helper_ftoui(cpu_R
[arg
[0]], cpu_FR
[arg
[1]],
4618 rounding_mode
, scale
);
4620 gen_helper_ftoi(cpu_R
[arg
[0]], cpu_FR
[arg
[1]],
4621 rounding_mode
, scale
);
4623 tcg_temp_free(rounding_mode
);
4624 tcg_temp_free(scale
);
4628 static void translate_ldsti(DisasContext
*dc
, const uint32_t arg
[],
4629 const uint32_t par
[])
4631 if (gen_window_check1(dc
, arg
[1]) && gen_check_cpenable(dc
, 0)) {
4632 TCGv_i32 addr
= tcg_temp_new_i32();
4634 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
4635 gen_load_store_alignment(dc
, 2, addr
, false);
4637 tcg_gen_qemu_st32(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4639 tcg_gen_qemu_ld32u(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4642 tcg_gen_mov_i32(cpu_R
[arg
[1]], addr
);
4644 tcg_temp_free(addr
);
4648 static void translate_ldstx(DisasContext
*dc
, const uint32_t arg
[],
4649 const uint32_t par
[])
4651 if (gen_window_check2(dc
, arg
[1], arg
[2]) && gen_check_cpenable(dc
, 0)) {
4652 TCGv_i32 addr
= tcg_temp_new_i32();
4654 tcg_gen_add_i32(addr
, cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
4655 gen_load_store_alignment(dc
, 2, addr
, false);
4657 tcg_gen_qemu_st32(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4659 tcg_gen_qemu_ld32u(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4662 tcg_gen_mov_i32(cpu_R
[arg
[1]], addr
);
4664 tcg_temp_free(addr
);
4668 static void translate_madd_s(DisasContext
*dc
, const uint32_t arg
[],
4669 const uint32_t par
[])
4671 if (gen_check_cpenable(dc
, 0)) {
4672 gen_helper_madd_s(cpu_FR
[arg
[0]], cpu_env
,
4673 cpu_FR
[arg
[0]], cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4677 static void translate_mov_s(DisasContext
*dc
, const uint32_t arg
[],
4678 const uint32_t par
[])
4680 if (gen_check_cpenable(dc
, 0)) {
4681 tcg_gen_mov_i32(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4685 static void translate_movcond_s(DisasContext
*dc
, const uint32_t arg
[],
4686 const uint32_t par
[])
4688 if (gen_window_check1(dc
, arg
[2]) && gen_check_cpenable(dc
, 0)) {
4689 TCGv_i32 zero
= tcg_const_i32(0);
4691 tcg_gen_movcond_i32(par
[0], cpu_FR
[arg
[0]],
4692 cpu_R
[arg
[2]], zero
,
4693 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4694 tcg_temp_free(zero
);
4698 static void translate_movp_s(DisasContext
*dc
, const uint32_t arg
[],
4699 const uint32_t par
[])
4701 if (gen_check_cpenable(dc
, 0)) {
4702 TCGv_i32 zero
= tcg_const_i32(0);
4703 TCGv_i32 tmp
= tcg_temp_new_i32();
4705 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[2]);
4706 tcg_gen_movcond_i32(par
[0],
4707 cpu_FR
[arg
[0]], tmp
, zero
,
4708 cpu_FR
[arg
[1]], cpu_FR
[arg
[0]]);
4710 tcg_temp_free(zero
);
4714 static void translate_mul_s(DisasContext
*dc
, const uint32_t arg
[],
4715 const uint32_t par
[])
4717 if (gen_check_cpenable(dc
, 0)) {
4718 gen_helper_mul_s(cpu_FR
[arg
[0]], cpu_env
,
4719 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4723 static void translate_msub_s(DisasContext
*dc
, const uint32_t arg
[],
4724 const uint32_t par
[])
4726 if (gen_check_cpenable(dc
, 0)) {
4727 gen_helper_msub_s(cpu_FR
[arg
[0]], cpu_env
,
4728 cpu_FR
[arg
[0]], cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4732 static void translate_neg_s(DisasContext
*dc
, const uint32_t arg
[],
4733 const uint32_t par
[])
4735 if (gen_check_cpenable(dc
, 0)) {
4736 gen_helper_neg_s(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4740 static void translate_rfr_s(DisasContext
*dc
, const uint32_t arg
[],
4741 const uint32_t par
[])
4743 if (gen_window_check1(dc
, arg
[0]) &&
4744 gen_check_cpenable(dc
, 0)) {
4745 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_FR
[arg
[1]]);
4749 static void translate_sub_s(DisasContext
*dc
, const uint32_t arg
[],
4750 const uint32_t par
[])
4752 if (gen_check_cpenable(dc
, 0)) {
4753 gen_helper_sub_s(cpu_FR
[arg
[0]], cpu_env
,
4754 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4758 static void translate_wfr_s(DisasContext
*dc
, const uint32_t arg
[],
4759 const uint32_t par
[])
4761 if (gen_window_check1(dc
, arg
[1]) &&
4762 gen_check_cpenable(dc
, 0)) {
4763 tcg_gen_mov_i32(cpu_FR
[arg
[0]], cpu_R
[arg
[1]]);
4767 static const XtensaOpcodeOps fpu2000_ops
[] = {
4770 .translate
= translate_abs_s
,
4773 .translate
= translate_add_s
,
4776 .translate
= translate_ftoi_s
,
4777 .par
= (const uint32_t[]){float_round_up
, false},
4780 .translate
= translate_float_s
,
4781 .par
= (const uint32_t[]){false},
4784 .translate
= translate_ftoi_s
,
4785 .par
= (const uint32_t[]){float_round_down
, false},
4788 .translate
= translate_ldsti
,
4789 .par
= (const uint32_t[]){false, false},
4792 .translate
= translate_ldsti
,
4793 .par
= (const uint32_t[]){false, true},
4796 .translate
= translate_ldstx
,
4797 .par
= (const uint32_t[]){false, false},
4800 .translate
= translate_ldstx
,
4801 .par
= (const uint32_t[]){false, true},
4804 .translate
= translate_madd_s
,
4807 .translate
= translate_mov_s
,
4810 .translate
= translate_movcond_s
,
4811 .par
= (const uint32_t[]){TCG_COND_EQ
},
4814 .translate
= translate_movp_s
,
4815 .par
= (const uint32_t[]){TCG_COND_EQ
},
4818 .translate
= translate_movcond_s
,
4819 .par
= (const uint32_t[]){TCG_COND_GE
},
4822 .translate
= translate_movcond_s
,
4823 .par
= (const uint32_t[]){TCG_COND_LT
},
4826 .translate
= translate_movcond_s
,
4827 .par
= (const uint32_t[]){TCG_COND_NE
},
4830 .translate
= translate_movp_s
,
4831 .par
= (const uint32_t[]){TCG_COND_NE
},
4834 .translate
= translate_msub_s
,
4837 .translate
= translate_mul_s
,
4840 .translate
= translate_neg_s
,
4843 .translate
= translate_compare_s
,
4844 .par
= (const uint32_t[]){COMPARE_OEQ
},
4847 .translate
= translate_compare_s
,
4848 .par
= (const uint32_t[]){COMPARE_OLE
},
4851 .translate
= translate_compare_s
,
4852 .par
= (const uint32_t[]){COMPARE_OLT
},
4855 .translate
= translate_rfr_s
,
4858 .translate
= translate_ftoi_s
,
4859 .par
= (const uint32_t[]){float_round_nearest_even
, false},
4862 .translate
= translate_ldsti
,
4863 .par
= (const uint32_t[]){true, false},
4866 .translate
= translate_ldsti
,
4867 .par
= (const uint32_t[]){true, true},
4870 .translate
= translate_ldstx
,
4871 .par
= (const uint32_t[]){true, false},
4874 .translate
= translate_ldstx
,
4875 .par
= (const uint32_t[]){true, true},
4878 .translate
= translate_sub_s
,
4881 .translate
= translate_ftoi_s
,
4882 .par
= (const uint32_t[]){float_round_to_zero
, false},
4885 .translate
= translate_compare_s
,
4886 .par
= (const uint32_t[]){COMPARE_UEQ
},
4889 .translate
= translate_float_s
,
4890 .par
= (const uint32_t[]){true},
4893 .translate
= translate_compare_s
,
4894 .par
= (const uint32_t[]){COMPARE_ULE
},
4897 .translate
= translate_compare_s
,
4898 .par
= (const uint32_t[]){COMPARE_ULT
},
4901 .translate
= translate_compare_s
,
4902 .par
= (const uint32_t[]){COMPARE_UN
},
4905 .translate
= translate_ftoi_s
,
4906 .par
= (const uint32_t[]){float_round_to_zero
, true},
4909 .translate
= translate_wfr_s
,
4913 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
= {
4914 .num_opcodes
= ARRAY_SIZE(fpu2000_ops
),
4915 .opcode
= fpu2000_ops
,