3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/cpu_ldst.h"
40 #include "exec/semihost.h"
41 #include "exec/translator.h"
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
46 #include "trace-tcg.h"
51 DisasContextBase base
;
52 const XtensaConfig
*config
;
61 bool sar_m32_allocated
;
73 xtensa_insnbuf insnbuf
;
74 xtensa_insnbuf slotbuf
;
77 static TCGv_i32 cpu_pc
;
78 static TCGv_i32 cpu_R
[16];
79 static TCGv_i32 cpu_FR
[16];
80 static TCGv_i32 cpu_SR
[256];
81 static TCGv_i32 cpu_UR
[256];
83 #include "exec/gen-icount.h"
85 typedef struct XtensaReg
{
97 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
99 .opt_bits = XTENSA_OPTION_BIT(opt), \
103 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
105 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
111 #define XTENSA_REG_BITS(regname, opt) \
112 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
114 static const XtensaReg sregnames
[256] = {
115 [LBEG
] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP
),
116 [LEND
] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP
),
117 [LCOUNT
] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP
),
118 [SAR
] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL
),
119 [BR
] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN
),
120 [LITBASE
] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R
),
121 [SCOMPARE1
] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE
),
122 [ACCLO
] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16
),
123 [ACCHI
] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16
),
124 [MR
] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16
),
125 [MR
+ 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16
),
126 [MR
+ 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16
),
127 [MR
+ 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16
),
128 [WINDOW_BASE
] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER
),
129 [WINDOW_START
] = XTENSA_REG("WINDOW_START",
130 XTENSA_OPTION_WINDOWED_REGISTER
),
131 [PTEVADDR
] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU
),
132 [MMID
] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL
),
133 [RASID
] = XTENSA_REG("RASID", XTENSA_OPTION_MMU
),
134 [ITLBCFG
] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU
),
135 [DTLBCFG
] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU
),
136 [IBREAKENABLE
] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG
),
137 [MEMCTL
] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL
),
138 [CACHEATTR
] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR
),
139 [ATOMCTL
] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL
),
140 [DDR
] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG
),
141 [IBREAKA
] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG
),
142 [IBREAKA
+ 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG
),
143 [DBREAKA
] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG
),
144 [DBREAKA
+ 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG
),
145 [DBREAKC
] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG
),
146 [DBREAKC
+ 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG
),
147 [CONFIGID0
] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL
, SR_R
),
148 [EPC1
] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION
),
149 [EPC1
+ 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
150 [EPC1
+ 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
151 [EPC1
+ 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
152 [EPC1
+ 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
153 [EPC1
+ 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
154 [EPC1
+ 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
155 [DEPC
] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION
),
156 [EPS2
] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
157 [EPS2
+ 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
158 [EPS2
+ 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
159 [EPS2
+ 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
160 [EPS2
+ 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
161 [EPS2
+ 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
162 [CONFIGID1
] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL
, SR_R
),
163 [EXCSAVE1
] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION
),
164 [EXCSAVE1
+ 1] = XTENSA_REG("EXCSAVE2",
165 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
166 [EXCSAVE1
+ 2] = XTENSA_REG("EXCSAVE3",
167 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
168 [EXCSAVE1
+ 3] = XTENSA_REG("EXCSAVE4",
169 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
170 [EXCSAVE1
+ 4] = XTENSA_REG("EXCSAVE5",
171 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
172 [EXCSAVE1
+ 5] = XTENSA_REG("EXCSAVE6",
173 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
174 [EXCSAVE1
+ 6] = XTENSA_REG("EXCSAVE7",
175 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
176 [CPENABLE
] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR
),
177 [INTSET
] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT
, SR_RW
),
178 [INTCLEAR
] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT
, SR_W
),
179 [INTENABLE
] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT
),
180 [PS
] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL
),
181 [VECBASE
] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR
),
182 [EXCCAUSE
] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION
),
183 [DEBUGCAUSE
] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG
, SR_R
),
184 [CCOUNT
] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT
),
185 [PRID
] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID
, SR_R
),
186 [ICOUNT
] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG
),
187 [ICOUNTLEVEL
] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG
),
188 [EXCVADDR
] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION
),
189 [CCOMPARE
] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT
),
190 [CCOMPARE
+ 1] = XTENSA_REG("CCOMPARE1",
191 XTENSA_OPTION_TIMER_INTERRUPT
),
192 [CCOMPARE
+ 2] = XTENSA_REG("CCOMPARE2",
193 XTENSA_OPTION_TIMER_INTERRUPT
),
194 [MISC
] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR
),
195 [MISC
+ 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR
),
196 [MISC
+ 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR
),
197 [MISC
+ 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR
),
200 static const XtensaReg uregnames
[256] = {
201 [EXPSTATE
] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL
),
202 [THREADPTR
] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER
),
203 [FCR
] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR
),
204 [FSR
] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR
),
207 void xtensa_translate_init(void)
209 static const char * const regnames
[] = {
210 "ar0", "ar1", "ar2", "ar3",
211 "ar4", "ar5", "ar6", "ar7",
212 "ar8", "ar9", "ar10", "ar11",
213 "ar12", "ar13", "ar14", "ar15",
215 static const char * const fregnames
[] = {
216 "f0", "f1", "f2", "f3",
217 "f4", "f5", "f6", "f7",
218 "f8", "f9", "f10", "f11",
219 "f12", "f13", "f14", "f15",
223 cpu_pc
= tcg_global_mem_new_i32(cpu_env
,
224 offsetof(CPUXtensaState
, pc
), "pc");
226 for (i
= 0; i
< 16; i
++) {
227 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
228 offsetof(CPUXtensaState
, regs
[i
]),
232 for (i
= 0; i
< 16; i
++) {
233 cpu_FR
[i
] = tcg_global_mem_new_i32(cpu_env
,
234 offsetof(CPUXtensaState
, fregs
[i
].f32
[FP_F32_LOW
]),
238 for (i
= 0; i
< 256; ++i
) {
239 if (sregnames
[i
].name
) {
240 cpu_SR
[i
] = tcg_global_mem_new_i32(cpu_env
,
241 offsetof(CPUXtensaState
, sregs
[i
]),
246 for (i
= 0; i
< 256; ++i
) {
247 if (uregnames
[i
].name
) {
248 cpu_UR
[i
] = tcg_global_mem_new_i32(cpu_env
,
249 offsetof(CPUXtensaState
, uregs
[i
]),
255 static inline bool option_enabled(DisasContext
*dc
, int opt
)
257 return xtensa_option_enabled(dc
->config
, opt
);
260 static void init_sar_tracker(DisasContext
*dc
)
262 dc
->sar_5bit
= false;
263 dc
->sar_m32_5bit
= false;
264 dc
->sar_m32_allocated
= false;
267 static void reset_sar_tracker(DisasContext
*dc
)
269 if (dc
->sar_m32_allocated
) {
270 tcg_temp_free(dc
->sar_m32
);
274 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
276 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
277 if (dc
->sar_m32_5bit
) {
278 tcg_gen_discard_i32(dc
->sar_m32
);
281 dc
->sar_m32_5bit
= false;
284 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
286 TCGv_i32 tmp
= tcg_const_i32(32);
287 if (!dc
->sar_m32_allocated
) {
288 dc
->sar_m32
= tcg_temp_local_new_i32();
289 dc
->sar_m32_allocated
= true;
291 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
292 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
293 dc
->sar_5bit
= false;
294 dc
->sar_m32_5bit
= true;
298 static void gen_exception(DisasContext
*dc
, int excp
)
300 TCGv_i32 tmp
= tcg_const_i32(excp
);
301 gen_helper_exception(cpu_env
, tmp
);
305 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
307 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
308 TCGv_i32 tcause
= tcg_const_i32(cause
);
309 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
311 tcg_temp_free(tcause
);
312 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
313 cause
== SYSCALL_CAUSE
) {
314 dc
->base
.is_jmp
= DISAS_NORETURN
;
318 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
321 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
322 TCGv_i32 tcause
= tcg_const_i32(cause
);
323 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
325 tcg_temp_free(tcause
);
328 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
330 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
331 TCGv_i32 tcause
= tcg_const_i32(cause
);
332 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
334 tcg_temp_free(tcause
);
335 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
336 dc
->base
.is_jmp
= DISAS_NORETURN
;
340 static bool gen_check_privilege(DisasContext
*dc
)
342 #ifndef CONFIG_USER_ONLY
347 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
348 dc
->base
.is_jmp
= DISAS_NORETURN
;
352 static bool gen_check_cpenable(DisasContext
*dc
, unsigned cp
)
354 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) &&
355 !(dc
->cpenable
& (1 << cp
))) {
356 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ cp
);
357 dc
->base
.is_jmp
= DISAS_NORETURN
;
363 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
365 tcg_gen_mov_i32(cpu_pc
, dest
);
367 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
369 if (dc
->base
.singlestep_enabled
) {
370 gen_exception(dc
, EXCP_DEBUG
);
373 tcg_gen_goto_tb(slot
);
374 tcg_gen_exit_tb(dc
->base
.tb
, slot
);
376 tcg_gen_exit_tb(NULL
, 0);
379 dc
->base
.is_jmp
= DISAS_NORETURN
;
382 static void gen_jump(DisasContext
*dc
, TCGv dest
)
384 gen_jump_slot(dc
, dest
, -1);
387 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
389 TCGv_i32 tmp
= tcg_const_i32(dest
);
390 #ifndef CONFIG_USER_ONLY
391 if (((dc
->base
.pc_first
^ dest
) & TARGET_PAGE_MASK
) != 0) {
395 gen_jump_slot(dc
, tmp
, slot
);
399 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
402 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
404 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
405 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
406 tcg_temp_free(tcallinc
);
407 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
408 (callinc
<< 30) | (dc
->base
.pc_next
& 0x3fffffff));
409 gen_jump_slot(dc
, dest
, slot
);
412 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
414 gen_callw_slot(dc
, callinc
, dest
, -1);
417 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
419 TCGv_i32 tmp
= tcg_const_i32(dest
);
420 #ifndef CONFIG_USER_ONLY
421 if (((dc
->base
.pc_first
^ dest
) & TARGET_PAGE_MASK
) != 0) {
425 gen_callw_slot(dc
, callinc
, tmp
, slot
);
429 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
431 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
432 !(dc
->base
.tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
433 dc
->base
.pc_next
== dc
->lend
) {
434 TCGLabel
*label
= gen_new_label();
436 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
437 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
438 gen_jumpi(dc
, dc
->lbeg
, slot
);
439 gen_set_label(label
);
440 gen_jumpi(dc
, dc
->base
.pc_next
, -1);
446 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
448 if (!gen_check_loop_end(dc
, slot
)) {
449 gen_jumpi(dc
, dc
->base
.pc_next
, slot
);
453 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
454 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t addr
)
456 TCGLabel
*label
= gen_new_label();
458 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
459 gen_jumpi_check_loop_end(dc
, 0);
460 gen_set_label(label
);
461 gen_jumpi(dc
, addr
, 1);
464 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
465 TCGv_i32 t0
, uint32_t t1
, uint32_t addr
)
467 TCGv_i32 tmp
= tcg_const_i32(t1
);
468 gen_brcond(dc
, cond
, t0
, tmp
, addr
);
472 static bool gen_check_sr(DisasContext
*dc
, uint32_t sr
, unsigned access
)
474 if (!xtensa_option_bits_enabled(dc
->config
, sregnames
[sr
].opt_bits
)) {
475 if (sregnames
[sr
].name
) {
476 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not configured\n", sregnames
[sr
].name
);
478 qemu_log_mask(LOG_UNIMP
, "SR %d is not implemented\n", sr
);
480 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
482 } else if (!(sregnames
[sr
].access
& access
)) {
483 static const char * const access_text
[] = {
488 assert(access
< ARRAY_SIZE(access_text
) && access_text
[access
]);
489 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not available for %s\n", sregnames
[sr
].name
,
490 access_text
[access
]);
491 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
497 #ifndef CONFIG_USER_ONLY
498 static bool gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
500 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
503 gen_helper_update_ccount(cpu_env
);
504 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
505 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
512 static bool gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
514 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
515 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
516 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
521 static bool gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
523 static bool (* const rsr_handler
[256])(DisasContext
*dc
,
524 TCGv_i32 d
, uint32_t sr
) = {
525 #ifndef CONFIG_USER_ONLY
526 [CCOUNT
] = gen_rsr_ccount
,
527 [INTSET
] = gen_rsr_ccount
,
528 [PTEVADDR
] = gen_rsr_ptevaddr
,
532 if (rsr_handler
[sr
]) {
533 return rsr_handler
[sr
](dc
, d
, sr
);
535 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
540 static bool gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
542 gen_helper_wsr_lbeg(cpu_env
, s
);
543 gen_jumpi_check_loop_end(dc
, 0);
547 static bool gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
549 gen_helper_wsr_lend(cpu_env
, s
);
550 gen_jumpi_check_loop_end(dc
, 0);
554 static bool gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
556 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
557 if (dc
->sar_m32_5bit
) {
558 tcg_gen_discard_i32(dc
->sar_m32
);
560 dc
->sar_5bit
= false;
561 dc
->sar_m32_5bit
= false;
565 static bool gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
567 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
571 static bool gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
573 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
574 /* This can change tb->flags, so exit tb */
575 gen_jumpi_check_loop_end(dc
, -1);
579 static bool gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
581 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
585 #ifndef CONFIG_USER_ONLY
586 static bool gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
588 gen_helper_wsr_windowbase(cpu_env
, v
);
589 /* This can change tb->flags, so exit tb */
590 gen_jumpi_check_loop_end(dc
, -1);
594 static bool gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
596 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
597 /* This can change tb->flags, so exit tb */
598 gen_jumpi_check_loop_end(dc
, -1);
602 static bool gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
604 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
608 static bool gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
610 gen_helper_wsr_rasid(cpu_env
, v
);
611 /* This can change tb->flags, so exit tb */
612 gen_jumpi_check_loop_end(dc
, -1);
616 static bool gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
618 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
622 static bool gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
624 gen_helper_wsr_ibreakenable(cpu_env
, v
);
625 gen_jumpi_check_loop_end(dc
, 0);
629 static bool gen_wsr_memctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
631 gen_helper_wsr_memctl(cpu_env
, v
);
635 static bool gen_wsr_atomctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
637 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x3f);
641 static bool gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
643 unsigned id
= sr
- IBREAKA
;
645 if (id
< dc
->config
->nibreak
) {
646 TCGv_i32 tmp
= tcg_const_i32(id
);
647 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
649 gen_jumpi_check_loop_end(dc
, 0);
655 static bool gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
657 unsigned id
= sr
- DBREAKA
;
659 if (id
< dc
->config
->ndbreak
) {
660 TCGv_i32 tmp
= tcg_const_i32(id
);
661 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
667 static bool gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
669 unsigned id
= sr
- DBREAKC
;
671 if (id
< dc
->config
->ndbreak
) {
672 TCGv_i32 tmp
= tcg_const_i32(id
);
673 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
679 static bool gen_wsr_cpenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
681 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xff);
682 /* This can change tb->flags, so exit tb */
683 gen_jumpi_check_loop_end(dc
, -1);
687 static void gen_check_interrupts(DisasContext
*dc
)
689 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
692 gen_helper_check_interrupts(cpu_env
);
693 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
698 static bool gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
700 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
701 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
702 gen_check_interrupts(dc
);
703 gen_jumpi_check_loop_end(dc
, 0);
707 static bool gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
709 TCGv_i32 tmp
= tcg_temp_new_i32();
711 tcg_gen_andi_i32(tmp
, v
,
712 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
713 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
714 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
715 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
717 gen_check_interrupts(dc
);
718 gen_jumpi_check_loop_end(dc
, 0);
722 static bool gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
724 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
725 gen_check_interrupts(dc
);
726 gen_jumpi_check_loop_end(dc
, 0);
730 static bool gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
732 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
733 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
735 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
738 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
739 gen_check_interrupts(dc
);
740 /* This can change mmu index and tb->flags, so exit tb */
741 gen_jumpi_check_loop_end(dc
, -1);
745 static bool gen_wsr_ccount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
747 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
750 gen_helper_wsr_ccount(cpu_env
, v
);
751 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
753 gen_jumpi_check_loop_end(dc
, 0);
759 static bool gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
762 tcg_gen_mov_i32(dc
->next_icount
, v
);
764 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
769 static bool gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
771 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
772 /* This can change tb->flags, so exit tb */
773 gen_jumpi_check_loop_end(dc
, -1);
777 static bool gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
779 uint32_t id
= sr
- CCOMPARE
;
782 if (id
< dc
->config
->nccompare
) {
783 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
784 TCGv_i32 tmp
= tcg_const_i32(id
);
786 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
787 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
788 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
791 gen_helper_update_ccompare(cpu_env
, tmp
);
792 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
794 gen_jumpi_check_loop_end(dc
, 0);
802 static void gen_check_interrupts(DisasContext
*dc
)
807 static bool gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
809 static bool (* const wsr_handler
[256])(DisasContext
*dc
,
810 uint32_t sr
, TCGv_i32 v
) = {
811 [LBEG
] = gen_wsr_lbeg
,
812 [LEND
] = gen_wsr_lend
,
815 [LITBASE
] = gen_wsr_litbase
,
816 [ACCHI
] = gen_wsr_acchi
,
817 #ifndef CONFIG_USER_ONLY
818 [WINDOW_BASE
] = gen_wsr_windowbase
,
819 [WINDOW_START
] = gen_wsr_windowstart
,
820 [PTEVADDR
] = gen_wsr_ptevaddr
,
821 [RASID
] = gen_wsr_rasid
,
822 [ITLBCFG
] = gen_wsr_tlbcfg
,
823 [DTLBCFG
] = gen_wsr_tlbcfg
,
824 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
825 [MEMCTL
] = gen_wsr_memctl
,
826 [ATOMCTL
] = gen_wsr_atomctl
,
827 [IBREAKA
] = gen_wsr_ibreaka
,
828 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
829 [DBREAKA
] = gen_wsr_dbreaka
,
830 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
831 [DBREAKC
] = gen_wsr_dbreakc
,
832 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
833 [CPENABLE
] = gen_wsr_cpenable
,
834 [INTSET
] = gen_wsr_intset
,
835 [INTCLEAR
] = gen_wsr_intclear
,
836 [INTENABLE
] = gen_wsr_intenable
,
838 [CCOUNT
] = gen_wsr_ccount
,
839 [ICOUNT
] = gen_wsr_icount
,
840 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
841 [CCOMPARE
] = gen_wsr_ccompare
,
842 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
843 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
847 if (wsr_handler
[sr
]) {
848 return wsr_handler
[sr
](dc
, sr
, s
);
850 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
855 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
859 gen_helper_wur_fcr(cpu_env
, s
);
863 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
867 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
872 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
873 TCGv_i32 addr
, bool no_hw_alignment
)
875 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
876 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
877 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
879 TCGLabel
*label
= gen_new_label();
880 TCGv_i32 tmp
= tcg_temp_new_i32();
881 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
882 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
883 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
884 gen_set_label(label
);
889 #ifndef CONFIG_USER_ONLY
890 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
892 TCGv_i32 pc
= tcg_const_i32(dc
->base
.pc_next
);
893 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
895 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
898 gen_helper_waiti(cpu_env
, pc
, intlevel
);
899 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
903 tcg_temp_free(intlevel
);
904 gen_jumpi_check_loop_end(dc
, 0);
908 static bool gen_window_check1(DisasContext
*dc
, unsigned r1
)
910 if (r1
/ 4 > dc
->window
) {
911 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
912 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
914 gen_helper_window_check(cpu_env
, pc
, w
);
915 dc
->base
.is_jmp
= DISAS_NORETURN
;
921 static bool gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
923 return gen_window_check1(dc
, r1
> r2
? r1
: r2
);
926 static bool gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
929 return gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
932 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
934 TCGv_i32 m
= tcg_temp_new_i32();
937 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
939 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
944 static inline unsigned xtensa_op0_insn_len(DisasContext
*dc
, uint8_t op0
)
946 return xtensa_isa_length_from_chars(dc
->config
->isa
, &op0
);
949 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
951 xtensa_isa isa
= dc
->config
->isa
;
952 unsigned char b
[MAX_INSN_LENGTH
] = {cpu_ldub_code(env
, dc
->pc
)};
953 unsigned len
= xtensa_op0_insn_len(dc
, b
[0]);
958 if (len
== XTENSA_UNDEFINED
) {
959 qemu_log_mask(LOG_GUEST_ERROR
,
960 "unknown instruction length (pc = %08x)\n",
962 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
966 dc
->base
.pc_next
= dc
->pc
+ len
;
967 if (xtensa_option_enabled(dc
->config
, XTENSA_OPTION_LOOP
) &&
968 dc
->lbeg
== dc
->pc
&&
969 ((dc
->pc
^ (dc
->base
.pc_next
- 1)) & -dc
->config
->inst_fetch_width
)) {
970 qemu_log_mask(LOG_GUEST_ERROR
,
971 "unaligned first instruction of a loop (pc = %08x)\n",
974 for (i
= 1; i
< len
; ++i
) {
975 b
[i
] = cpu_ldub_code(env
, dc
->pc
+ i
);
977 xtensa_insnbuf_from_chars(isa
, dc
->insnbuf
, b
, len
);
978 fmt
= xtensa_format_decode(isa
, dc
->insnbuf
);
979 if (fmt
== XTENSA_UNDEFINED
) {
980 qemu_log_mask(LOG_GUEST_ERROR
,
981 "unrecognized instruction format (pc = %08x)\n",
983 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
986 slots
= xtensa_format_num_slots(isa
, fmt
);
987 for (slot
= 0; slot
< slots
; ++slot
) {
989 int opnd
, vopnd
, opnds
;
990 uint32_t raw_arg
[MAX_OPCODE_ARGS
];
991 uint32_t arg
[MAX_OPCODE_ARGS
];
992 XtensaOpcodeOps
*ops
;
994 dc
->raw_arg
= raw_arg
;
996 xtensa_format_get_slot(isa
, fmt
, slot
, dc
->insnbuf
, dc
->slotbuf
);
997 opc
= xtensa_opcode_decode(isa
, fmt
, slot
, dc
->slotbuf
);
998 if (opc
== XTENSA_UNDEFINED
) {
999 qemu_log_mask(LOG_GUEST_ERROR
,
1000 "unrecognized opcode in slot %d (pc = %08x)\n",
1002 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1005 opnds
= xtensa_opcode_num_operands(isa
, opc
);
1007 for (opnd
= vopnd
= 0; opnd
< opnds
; ++opnd
) {
1008 if (xtensa_operand_is_visible(isa
, opc
, opnd
)) {
1011 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
1013 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
1015 if (xtensa_operand_is_PCrelative(isa
, opc
, opnd
)) {
1016 xtensa_operand_undo_reloc(isa
, opc
, opnd
, &v
, dc
->pc
);
1022 ops
= dc
->config
->opcode_ops
[opc
];
1024 ops
->translate(dc
, arg
, ops
->par
);
1026 qemu_log_mask(LOG_GUEST_ERROR
,
1027 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
1028 xtensa_opcode_name(isa
, opc
), slot
, dc
->pc
);
1029 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1033 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
1034 gen_check_loop_end(dc
, 0);
1036 dc
->pc
= dc
->base
.pc_next
;
1039 static inline unsigned xtensa_insn_len(CPUXtensaState
*env
, DisasContext
*dc
)
1041 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
1042 return xtensa_op0_insn_len(dc
, b0
);
1045 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
1049 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
1050 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
1051 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
1052 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
1058 static void xtensa_tr_init_disas_context(DisasContextBase
*dcbase
,
1061 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1062 CPUXtensaState
*env
= cpu
->env_ptr
;
1063 uint32_t tb_flags
= dc
->base
.tb
->flags
;
1065 dc
->config
= env
->config
;
1066 dc
->pc
= dc
->base
.pc_first
;
1067 dc
->ring
= tb_flags
& XTENSA_TBFLAG_RING_MASK
;
1068 dc
->cring
= (tb_flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
->ring
;
1069 dc
->lbeg
= env
->sregs
[LBEG
];
1070 dc
->lend
= env
->sregs
[LEND
];
1071 dc
->debug
= tb_flags
& XTENSA_TBFLAG_DEBUG
;
1072 dc
->icount
= tb_flags
& XTENSA_TBFLAG_ICOUNT
;
1073 dc
->cpenable
= (tb_flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
1074 XTENSA_TBFLAG_CPENABLE_SHIFT
;
1075 dc
->window
= ((tb_flags
& XTENSA_TBFLAG_WINDOW_MASK
) >>
1076 XTENSA_TBFLAG_WINDOW_SHIFT
);
1078 if (dc
->config
->isa
) {
1079 dc
->insnbuf
= xtensa_insnbuf_alloc(dc
->config
->isa
);
1080 dc
->slotbuf
= xtensa_insnbuf_alloc(dc
->config
->isa
);
1082 init_sar_tracker(dc
);
1085 static void xtensa_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1087 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1090 dc
->next_icount
= tcg_temp_local_new_i32();
1094 static void xtensa_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1096 tcg_gen_insn_start(dcbase
->pc_next
);
1099 static bool xtensa_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
1100 const CPUBreakpoint
*bp
)
1102 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1104 tcg_gen_movi_i32(cpu_pc
, dc
->base
.pc_next
);
1105 gen_exception(dc
, EXCP_DEBUG
);
1106 dc
->base
.is_jmp
= DISAS_NORETURN
;
1107 /* The address covered by the breakpoint must be included in
1108 [tb->pc, tb->pc + tb->size) in order to for it to be
1109 properly cleared -- thus we increment the PC here so that
1110 the logic setting tb->size below does the right thing. */
1111 dc
->base
.pc_next
+= 2;
1115 static void xtensa_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1117 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1118 CPUXtensaState
*env
= cpu
->env_ptr
;
1119 target_ulong page_start
;
1121 /* These two conditions only apply to the first insn in the TB,
1122 but this is the first TranslateOps hook that allows exiting. */
1123 if ((tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
)
1124 && (dc
->base
.tb
->flags
& XTENSA_TBFLAG_YIELD
)) {
1125 gen_exception(dc
, EXCP_YIELD
);
1126 dc
->base
.is_jmp
= DISAS_NORETURN
;
1129 if (dc
->base
.tb
->flags
& XTENSA_TBFLAG_EXCEPTION
) {
1130 gen_exception(dc
, EXCP_DEBUG
);
1131 dc
->base
.is_jmp
= DISAS_NORETURN
;
1136 TCGLabel
*label
= gen_new_label();
1138 tcg_gen_addi_i32(dc
->next_icount
, cpu_SR
[ICOUNT
], 1);
1139 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
->next_icount
, 0, label
);
1140 tcg_gen_mov_i32(dc
->next_icount
, cpu_SR
[ICOUNT
]);
1142 gen_debug_exception(dc
, DEBUGCAUSE_IC
);
1144 gen_set_label(label
);
1148 gen_ibreak_check(env
, dc
);
1151 disas_xtensa_insn(env
, dc
);
1154 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
1157 /* End the TB if the next insn will cross into the next page. */
1158 page_start
= dc
->base
.pc_first
& TARGET_PAGE_MASK
;
1159 if (dc
->base
.is_jmp
== DISAS_NEXT
&&
1160 (dc
->pc
- page_start
>= TARGET_PAGE_SIZE
||
1161 dc
->pc
- page_start
+ xtensa_insn_len(env
, dc
) > TARGET_PAGE_SIZE
)) {
1162 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
1166 static void xtensa_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1168 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1170 reset_sar_tracker(dc
);
1171 if (dc
->config
->isa
) {
1172 xtensa_insnbuf_free(dc
->config
->isa
, dc
->insnbuf
);
1173 xtensa_insnbuf_free(dc
->config
->isa
, dc
->slotbuf
);
1176 tcg_temp_free(dc
->next_icount
);
1179 switch (dc
->base
.is_jmp
) {
1180 case DISAS_NORETURN
:
1182 case DISAS_TOO_MANY
:
1183 if (dc
->base
.singlestep_enabled
) {
1184 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1185 gen_exception(dc
, EXCP_DEBUG
);
1187 gen_jumpi(dc
, dc
->pc
, 0);
1191 g_assert_not_reached();
1195 static void xtensa_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
1197 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1198 log_target_disas(cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1201 static const TranslatorOps xtensa_translator_ops
= {
1202 .init_disas_context
= xtensa_tr_init_disas_context
,
1203 .tb_start
= xtensa_tr_tb_start
,
1204 .insn_start
= xtensa_tr_insn_start
,
1205 .breakpoint_check
= xtensa_tr_breakpoint_check
,
1206 .translate_insn
= xtensa_tr_translate_insn
,
1207 .tb_stop
= xtensa_tr_tb_stop
,
1208 .disas_log
= xtensa_tr_disas_log
,
1211 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
)
1213 DisasContext dc
= {};
1214 translator_loop(&xtensa_translator_ops
, &dc
.base
, cpu
, tb
);
1217 void xtensa_cpu_dump_state(CPUState
*cs
, FILE *f
,
1218 fprintf_function cpu_fprintf
, int flags
)
1220 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
1221 CPUXtensaState
*env
= &cpu
->env
;
1224 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
1226 for (i
= j
= 0; i
< 256; ++i
) {
1227 if (xtensa_option_bits_enabled(env
->config
, sregnames
[i
].opt_bits
)) {
1228 cpu_fprintf(f
, "%12s=%08x%c", sregnames
[i
].name
, env
->sregs
[i
],
1229 (j
++ % 4) == 3 ? '\n' : ' ');
1233 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1235 for (i
= j
= 0; i
< 256; ++i
) {
1236 if (xtensa_option_bits_enabled(env
->config
, uregnames
[i
].opt_bits
)) {
1237 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
].name
, env
->uregs
[i
],
1238 (j
++ % 4) == 3 ? '\n' : ' ');
1242 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1244 for (i
= 0; i
< 16; ++i
) {
1245 cpu_fprintf(f
, " A%02d=%08x%c", i
, env
->regs
[i
],
1246 (i
% 4) == 3 ? '\n' : ' ');
1249 xtensa_sync_phys_from_window(env
);
1250 cpu_fprintf(f
, "\n");
1252 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
1253 cpu_fprintf(f
, "AR%02d=%08x ", i
, env
->phys_regs
[i
]);
1255 bool ws
= (env
->sregs
[WINDOW_START
] & (1 << (i
/ 4))) != 0;
1256 bool cw
= env
->sregs
[WINDOW_BASE
] == i
/ 4;
1258 cpu_fprintf(f
, "%c%c\n", ws
? '<' : ' ', cw
? '=' : ' ');
1262 if ((flags
& CPU_DUMP_FPU
) &&
1263 xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
1264 cpu_fprintf(f
, "\n");
1266 for (i
= 0; i
< 16; ++i
) {
1267 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
1268 float32_val(env
->fregs
[i
].f32
[FP_F32_LOW
]),
1269 *(float *)(env
->fregs
[i
].f32
+ FP_F32_LOW
),
1270 (i
% 2) == 1 ? '\n' : ' ');
1275 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
,
1281 static int compare_opcode_ops(const void *a
, const void *b
)
1283 return strcmp((const char *)a
,
1284 ((const XtensaOpcodeOps
*)b
)->name
);
1288 xtensa_find_opcode_ops(const XtensaOpcodeTranslators
*t
,
1291 return bsearch(name
, t
->opcode
, t
->num_opcodes
,
1292 sizeof(XtensaOpcodeOps
), compare_opcode_ops
);
1295 static void translate_abs(DisasContext
*dc
, const uint32_t arg
[],
1296 const uint32_t par
[])
1298 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1299 TCGv_i32 zero
= tcg_const_i32(0);
1300 TCGv_i32 neg
= tcg_temp_new_i32();
1302 tcg_gen_neg_i32(neg
, cpu_R
[arg
[1]]);
1303 tcg_gen_movcond_i32(TCG_COND_GE
, cpu_R
[arg
[0]],
1304 cpu_R
[arg
[1]], zero
, cpu_R
[arg
[1]], neg
);
1306 tcg_temp_free(zero
);
1310 static void translate_add(DisasContext
*dc
, const uint32_t arg
[],
1311 const uint32_t par
[])
1313 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1314 tcg_gen_add_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1318 static void translate_addi(DisasContext
*dc
, const uint32_t arg
[],
1319 const uint32_t par
[])
1321 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1322 tcg_gen_addi_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
1326 static void translate_addx(DisasContext
*dc
, const uint32_t arg
[],
1327 const uint32_t par
[])
1329 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1330 TCGv_i32 tmp
= tcg_temp_new_i32();
1331 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], par
[0]);
1332 tcg_gen_add_i32(cpu_R
[arg
[0]], tmp
, cpu_R
[arg
[2]]);
1337 static void translate_all(DisasContext
*dc
, const uint32_t arg
[],
1338 const uint32_t par
[])
1340 uint32_t shift
= par
[1];
1341 TCGv_i32 mask
= tcg_const_i32(((1 << shift
) - 1) << arg
[1]);
1342 TCGv_i32 tmp
= tcg_temp_new_i32();
1344 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1346 tcg_gen_addi_i32(tmp
, tmp
, 1 << arg
[1]);
1348 tcg_gen_add_i32(tmp
, tmp
, mask
);
1350 tcg_gen_shri_i32(tmp
, tmp
, arg
[1] + shift
);
1351 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1353 tcg_temp_free(mask
);
1357 static void translate_and(DisasContext
*dc
, const uint32_t arg
[],
1358 const uint32_t par
[])
1360 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1361 tcg_gen_and_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1365 static void translate_ball(DisasContext
*dc
, const uint32_t arg
[],
1366 const uint32_t par
[])
1368 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1369 TCGv_i32 tmp
= tcg_temp_new_i32();
1370 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1371 gen_brcond(dc
, par
[0], tmp
, cpu_R
[arg
[1]], arg
[2]);
1376 static void translate_bany(DisasContext
*dc
, const uint32_t arg
[],
1377 const uint32_t par
[])
1379 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1380 TCGv_i32 tmp
= tcg_temp_new_i32();
1381 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1382 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1387 static void translate_b(DisasContext
*dc
, const uint32_t arg
[],
1388 const uint32_t par
[])
1390 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1391 gen_brcond(dc
, par
[0], cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
1395 static void translate_bb(DisasContext
*dc
, const uint32_t arg
[],
1396 const uint32_t par
[])
1398 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1399 #ifdef TARGET_WORDS_BIGENDIAN
1400 TCGv_i32 bit
= tcg_const_i32(0x80000000u
);
1402 TCGv_i32 bit
= tcg_const_i32(0x00000001u
);
1404 TCGv_i32 tmp
= tcg_temp_new_i32();
1405 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[1]], 0x1f);
1406 #ifdef TARGET_WORDS_BIGENDIAN
1407 tcg_gen_shr_i32(bit
, bit
, tmp
);
1409 tcg_gen_shl_i32(bit
, bit
, tmp
);
1411 tcg_gen_and_i32(tmp
, cpu_R
[arg
[0]], bit
);
1412 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1418 static void translate_bbi(DisasContext
*dc
, const uint32_t arg
[],
1419 const uint32_t par
[])
1421 if (gen_window_check1(dc
, arg
[0])) {
1422 TCGv_i32 tmp
= tcg_temp_new_i32();
1423 #ifdef TARGET_WORDS_BIGENDIAN
1424 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[0]], 0x80000000u
>> arg
[1]);
1426 tcg_gen_andi_i32(tmp
, cpu_R
[arg
[0]], 0x00000001u
<< arg
[1]);
1428 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2]);
1433 static void translate_bi(DisasContext
*dc
, const uint32_t arg
[],
1434 const uint32_t par
[])
1436 if (gen_window_check1(dc
, arg
[0])) {
1437 gen_brcondi(dc
, par
[0], cpu_R
[arg
[0]], arg
[1], arg
[2]);
1441 static void translate_bz(DisasContext
*dc
, const uint32_t arg
[],
1442 const uint32_t par
[])
1444 if (gen_window_check1(dc
, arg
[0])) {
1445 gen_brcondi(dc
, par
[0], cpu_R
[arg
[0]], 0, arg
[1]);
1457 static void translate_boolean(DisasContext
*dc
, const uint32_t arg
[],
1458 const uint32_t par
[])
1460 static void (* const op
[])(TCGv_i32
, TCGv_i32
, TCGv_i32
) = {
1461 [BOOLEAN_AND
] = tcg_gen_and_i32
,
1462 [BOOLEAN_ANDC
] = tcg_gen_andc_i32
,
1463 [BOOLEAN_OR
] = tcg_gen_or_i32
,
1464 [BOOLEAN_ORC
] = tcg_gen_orc_i32
,
1465 [BOOLEAN_XOR
] = tcg_gen_xor_i32
,
1468 TCGv_i32 tmp1
= tcg_temp_new_i32();
1469 TCGv_i32 tmp2
= tcg_temp_new_i32();
1471 tcg_gen_shri_i32(tmp1
, cpu_SR
[BR
], arg
[1]);
1472 tcg_gen_shri_i32(tmp2
, cpu_SR
[BR
], arg
[2]);
1473 op
[par
[0]](tmp1
, tmp1
, tmp2
);
1474 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
], tmp1
, arg
[0], 1);
1475 tcg_temp_free(tmp1
);
1476 tcg_temp_free(tmp2
);
1479 static void translate_bp(DisasContext
*dc
, const uint32_t arg
[],
1480 const uint32_t par
[])
1482 TCGv_i32 tmp
= tcg_temp_new_i32();
1484 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[0]);
1485 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[1]);
1489 static void translate_break(DisasContext
*dc
, const uint32_t arg
[],
1490 const uint32_t par
[])
1493 gen_debug_exception(dc
, par
[0]);
1497 static void translate_call0(DisasContext
*dc
, const uint32_t arg
[],
1498 const uint32_t par
[])
1500 tcg_gen_movi_i32(cpu_R
[0], dc
->base
.pc_next
);
1501 gen_jumpi(dc
, arg
[0], 0);
1504 static void translate_callw(DisasContext
*dc
, const uint32_t arg
[],
1505 const uint32_t par
[])
1507 if (gen_window_check1(dc
, par
[0] << 2)) {
1508 gen_callwi(dc
, par
[0], arg
[0], 0);
1512 static void translate_callx0(DisasContext
*dc
, const uint32_t arg
[],
1513 const uint32_t par
[])
1515 if (gen_window_check1(dc
, arg
[0])) {
1516 TCGv_i32 tmp
= tcg_temp_new_i32();
1517 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
1518 tcg_gen_movi_i32(cpu_R
[0], dc
->base
.pc_next
);
1524 static void translate_callxw(DisasContext
*dc
, const uint32_t arg
[],
1525 const uint32_t par
[])
1527 if (gen_window_check2(dc
, arg
[0], par
[0] << 2)) {
1528 TCGv_i32 tmp
= tcg_temp_new_i32();
1530 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
1531 gen_callw(dc
, par
[0], tmp
);
1536 static void translate_clamps(DisasContext
*dc
, const uint32_t arg
[],
1537 const uint32_t par
[])
1539 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1540 TCGv_i32 tmp1
= tcg_const_i32(-1u << arg
[2]);
1541 TCGv_i32 tmp2
= tcg_const_i32((1 << arg
[2]) - 1);
1543 tcg_gen_smax_i32(tmp1
, tmp1
, cpu_R
[arg
[1]]);
1544 tcg_gen_smin_i32(cpu_R
[arg
[0]], tmp1
, tmp2
);
1545 tcg_temp_free(tmp1
);
1546 tcg_temp_free(tmp2
);
1550 static void translate_clrb_expstate(DisasContext
*dc
, const uint32_t arg
[],
1551 const uint32_t par
[])
1553 /* TODO: GPIO32 may be a part of coprocessor */
1554 tcg_gen_andi_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], ~(1u << arg
[0]));
1557 static void translate_const16(DisasContext
*dc
, const uint32_t arg
[],
1558 const uint32_t par
[])
1560 if (gen_window_check1(dc
, arg
[0])) {
1561 TCGv_i32 c
= tcg_const_i32(arg
[1]);
1563 tcg_gen_deposit_i32(cpu_R
[arg
[0]], c
, cpu_R
[arg
[0]], 16, 16);
1568 /* par[0]: privileged, par[1]: check memory access */
1569 static void translate_dcache(DisasContext
*dc
, const uint32_t arg
[],
1570 const uint32_t par
[])
1572 if ((!par
[0] || gen_check_privilege(dc
)) &&
1573 gen_window_check1(dc
, arg
[0]) && par
[1]) {
1574 TCGv_i32 addr
= tcg_temp_new_i32();
1575 TCGv_i32 res
= tcg_temp_new_i32();
1577 tcg_gen_addi_i32(addr
, cpu_R
[arg
[0]], arg
[1]);
1578 tcg_gen_qemu_ld8u(res
, addr
, dc
->cring
);
1579 tcg_temp_free(addr
);
1584 static void translate_depbits(DisasContext
*dc
, const uint32_t arg
[],
1585 const uint32_t par
[])
1587 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1588 tcg_gen_deposit_i32(cpu_R
[arg
[1]], cpu_R
[arg
[1]], cpu_R
[arg
[0]],
1593 static void translate_entry(DisasContext
*dc
, const uint32_t arg
[],
1594 const uint32_t par
[])
1596 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1597 TCGv_i32 s
= tcg_const_i32(arg
[0]);
1598 TCGv_i32 imm
= tcg_const_i32(arg
[1]);
1599 gen_helper_entry(cpu_env
, pc
, s
, imm
);
1603 /* This can change tb->flags, so exit tb */
1604 gen_jumpi_check_loop_end(dc
, -1);
1607 static void translate_extui(DisasContext
*dc
, const uint32_t arg
[],
1608 const uint32_t par
[])
1610 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1611 int maskimm
= (1 << arg
[3]) - 1;
1613 TCGv_i32 tmp
= tcg_temp_new_i32();
1614 tcg_gen_shri_i32(tmp
, cpu_R
[arg
[1]], arg
[2]);
1615 tcg_gen_andi_i32(cpu_R
[arg
[0]], tmp
, maskimm
);
1620 /* par[0]: privileged, par[1]: check memory access */
1621 static void translate_icache(DisasContext
*dc
, const uint32_t arg
[],
1622 const uint32_t par
[])
1624 if ((!par
[0] || gen_check_privilege(dc
)) &&
1625 gen_window_check1(dc
, arg
[0]) && par
[1]) {
1626 #ifndef CONFIG_USER_ONLY
1627 TCGv_i32 addr
= tcg_temp_new_i32();
1629 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1630 tcg_gen_addi_i32(addr
, cpu_R
[arg
[0]], arg
[1]);
1631 gen_helper_itlb_hit_test(cpu_env
, addr
);
1632 tcg_temp_free(addr
);
1637 static void translate_itlb(DisasContext
*dc
, const uint32_t arg
[],
1638 const uint32_t par
[])
1640 if (gen_check_privilege(dc
) &&
1641 gen_window_check1(dc
, arg
[0])) {
1642 #ifndef CONFIG_USER_ONLY
1643 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
1645 gen_helper_itlb(cpu_env
, cpu_R
[arg
[0]], dtlb
);
1646 /* This could change memory mapping, so exit tb */
1647 gen_jumpi_check_loop_end(dc
, -1);
1648 tcg_temp_free(dtlb
);
1653 static void translate_ill(DisasContext
*dc
, const uint32_t arg
[],
1654 const uint32_t par
[])
1656 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1659 static void translate_j(DisasContext
*dc
, const uint32_t arg
[],
1660 const uint32_t par
[])
1662 gen_jumpi(dc
, arg
[0], 0);
1665 static void translate_jx(DisasContext
*dc
, const uint32_t arg
[],
1666 const uint32_t par
[])
1668 if (gen_window_check1(dc
, arg
[0])) {
1669 gen_jump(dc
, cpu_R
[arg
[0]]);
1673 static void translate_l32e(DisasContext
*dc
, const uint32_t arg
[],
1674 const uint32_t par
[])
1676 if (gen_check_privilege(dc
) &&
1677 gen_window_check2(dc
, arg
[0], arg
[1])) {
1678 TCGv_i32 addr
= tcg_temp_new_i32();
1680 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
1681 gen_load_store_alignment(dc
, 2, addr
, false);
1682 tcg_gen_qemu_ld_tl(cpu_R
[arg
[0]], addr
, dc
->ring
, MO_TEUL
);
1683 tcg_temp_free(addr
);
1687 static void translate_ldst(DisasContext
*dc
, const uint32_t arg
[],
1688 const uint32_t par
[])
1690 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1691 TCGv_i32 addr
= tcg_temp_new_i32();
1693 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
1694 if (par
[0] & MO_SIZE
) {
1695 gen_load_store_alignment(dc
, par
[0] & MO_SIZE
, addr
, par
[1]);
1699 tcg_gen_mb(TCG_BAR_STRL
| TCG_MO_ALL
);
1701 tcg_gen_qemu_st_tl(cpu_R
[arg
[0]], addr
, dc
->cring
, par
[0]);
1703 tcg_gen_qemu_ld_tl(cpu_R
[arg
[0]], addr
, dc
->cring
, par
[0]);
1705 tcg_gen_mb(TCG_BAR_LDAQ
| TCG_MO_ALL
);
1708 tcg_temp_free(addr
);
1712 static void translate_l32r(DisasContext
*dc
, const uint32_t arg
[],
1713 const uint32_t par
[])
1715 if (gen_window_check1(dc
, arg
[0])) {
1718 if (dc
->base
.tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1719 tmp
= tcg_const_i32(dc
->raw_arg
[1] - 1);
1720 tcg_gen_add_i32(tmp
, cpu_SR
[LITBASE
], tmp
);
1722 tmp
= tcg_const_i32(arg
[1]);
1724 tcg_gen_qemu_ld32u(cpu_R
[arg
[0]], tmp
, dc
->cring
);
1729 static void translate_loop(DisasContext
*dc
, const uint32_t arg
[],
1730 const uint32_t par
[])
1732 if (gen_window_check1(dc
, arg
[0])) {
1733 uint32_t lend
= arg
[1];
1734 TCGv_i32 tmp
= tcg_const_i32(lend
);
1736 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[arg
[0]], 1);
1737 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->base
.pc_next
);
1738 gen_helper_wsr_lend(cpu_env
, tmp
);
1741 if (par
[0] != TCG_COND_NEVER
) {
1742 TCGLabel
*label
= gen_new_label();
1743 tcg_gen_brcondi_i32(par
[0], cpu_R
[arg
[0]], 0, label
);
1744 gen_jumpi(dc
, lend
, 1);
1745 gen_set_label(label
);
1748 gen_jumpi(dc
, dc
->base
.pc_next
, 0);
1780 static void translate_mac16(DisasContext
*dc
, const uint32_t arg
[],
1781 const uint32_t par
[])
1784 bool is_m1_sr
= par
[1] & MAC16_DX
;
1785 bool is_m2_sr
= par
[1] & MAC16_XD
;
1786 unsigned half
= par
[2];
1787 uint32_t ld_offset
= par
[3];
1788 unsigned off
= ld_offset
? 2 : 0;
1789 uint32_t ar
[3] = {0};
1792 if (op
!= MAC16_NONE
) {
1794 ar
[n_ar
++] = arg
[off
];
1797 ar
[n_ar
++] = arg
[off
+ 1];
1802 ar
[n_ar
++] = arg
[1];
1805 if (gen_window_check3(dc
, ar
[0], ar
[1], ar
[2])) {
1806 TCGv_i32 vaddr
= tcg_temp_new_i32();
1807 TCGv_i32 mem32
= tcg_temp_new_i32();
1810 tcg_gen_addi_i32(vaddr
, cpu_R
[arg
[1]], ld_offset
);
1811 gen_load_store_alignment(dc
, 2, vaddr
, false);
1812 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
1814 if (op
!= MAC16_NONE
) {
1815 TCGv_i32 m1
= gen_mac16_m(is_m1_sr
?
1816 cpu_SR
[MR
+ arg
[off
]] :
1818 half
& MAC16_HX
, op
== MAC16_UMUL
);
1819 TCGv_i32 m2
= gen_mac16_m(is_m2_sr
?
1820 cpu_SR
[MR
+ arg
[off
+ 1]] :
1821 cpu_R
[arg
[off
+ 1]],
1822 half
& MAC16_XH
, op
== MAC16_UMUL
);
1824 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
1825 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
1826 if (op
== MAC16_UMUL
) {
1827 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
1829 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
1832 TCGv_i32 lo
= tcg_temp_new_i32();
1833 TCGv_i32 hi
= tcg_temp_new_i32();
1835 tcg_gen_mul_i32(lo
, m1
, m2
);
1836 tcg_gen_sari_i32(hi
, lo
, 31);
1837 if (op
== MAC16_MULA
) {
1838 tcg_gen_add2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1839 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1842 tcg_gen_sub2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1843 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1846 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
1848 tcg_temp_free_i32(lo
);
1849 tcg_temp_free_i32(hi
);
1855 tcg_gen_mov_i32(cpu_R
[arg
[1]], vaddr
);
1856 tcg_gen_mov_i32(cpu_SR
[MR
+ arg
[0]], mem32
);
1858 tcg_temp_free(vaddr
);
1859 tcg_temp_free(mem32
);
1863 static void translate_memw(DisasContext
*dc
, const uint32_t arg
[],
1864 const uint32_t par
[])
1866 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
1869 static void translate_smin(DisasContext
*dc
, const uint32_t arg
[],
1870 const uint32_t par
[])
1872 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1873 tcg_gen_smin_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1877 static void translate_umin(DisasContext
*dc
, const uint32_t arg
[],
1878 const uint32_t par
[])
1880 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1881 tcg_gen_umin_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1885 static void translate_smax(DisasContext
*dc
, const uint32_t arg
[],
1886 const uint32_t par
[])
1888 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1889 tcg_gen_smax_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1893 static void translate_umax(DisasContext
*dc
, const uint32_t arg
[],
1894 const uint32_t par
[])
1896 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1897 tcg_gen_umax_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1901 static void translate_mov(DisasContext
*dc
, const uint32_t arg
[],
1902 const uint32_t par
[])
1904 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1905 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1909 static void translate_movcond(DisasContext
*dc
, const uint32_t arg
[],
1910 const uint32_t par
[])
1912 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1913 TCGv_i32 zero
= tcg_const_i32(0);
1915 tcg_gen_movcond_i32(par
[0], cpu_R
[arg
[0]],
1916 cpu_R
[arg
[2]], zero
, cpu_R
[arg
[1]], cpu_R
[arg
[0]]);
1917 tcg_temp_free(zero
);
1921 static void translate_movi(DisasContext
*dc
, const uint32_t arg
[],
1922 const uint32_t par
[])
1924 if (gen_window_check1(dc
, arg
[0])) {
1925 tcg_gen_movi_i32(cpu_R
[arg
[0]], arg
[1]);
1929 static void translate_movp(DisasContext
*dc
, const uint32_t arg
[],
1930 const uint32_t par
[])
1932 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1933 TCGv_i32 zero
= tcg_const_i32(0);
1934 TCGv_i32 tmp
= tcg_temp_new_i32();
1936 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[2]);
1937 tcg_gen_movcond_i32(par
[0],
1938 cpu_R
[arg
[0]], tmp
, zero
,
1939 cpu_R
[arg
[1]], cpu_R
[arg
[0]]);
1941 tcg_temp_free(zero
);
1945 static void translate_movsp(DisasContext
*dc
, const uint32_t arg
[],
1946 const uint32_t par
[])
1948 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
1949 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1950 gen_helper_movsp(cpu_env
, pc
);
1951 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
1956 static void translate_mul16(DisasContext
*dc
, const uint32_t arg
[],
1957 const uint32_t par
[])
1959 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1960 TCGv_i32 v1
= tcg_temp_new_i32();
1961 TCGv_i32 v2
= tcg_temp_new_i32();
1964 tcg_gen_ext16s_i32(v1
, cpu_R
[arg
[1]]);
1965 tcg_gen_ext16s_i32(v2
, cpu_R
[arg
[2]]);
1967 tcg_gen_ext16u_i32(v1
, cpu_R
[arg
[1]]);
1968 tcg_gen_ext16u_i32(v2
, cpu_R
[arg
[2]]);
1970 tcg_gen_mul_i32(cpu_R
[arg
[0]], v1
, v2
);
1976 static void translate_mull(DisasContext
*dc
, const uint32_t arg
[],
1977 const uint32_t par
[])
1979 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1980 tcg_gen_mul_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1984 static void translate_mulh(DisasContext
*dc
, const uint32_t arg
[],
1985 const uint32_t par
[])
1987 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
1988 TCGv_i32 lo
= tcg_temp_new();
1991 tcg_gen_muls2_i32(lo
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1993 tcg_gen_mulu2_i32(lo
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
1999 static void translate_neg(DisasContext
*dc
, const uint32_t arg
[],
2000 const uint32_t par
[])
2002 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2003 tcg_gen_neg_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2007 static void translate_nop(DisasContext
*dc
, const uint32_t arg
[],
2008 const uint32_t par
[])
2012 static void translate_nsa(DisasContext
*dc
, const uint32_t arg
[],
2013 const uint32_t par
[])
2015 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2016 tcg_gen_clrsb_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2020 static void translate_nsau(DisasContext
*dc
, const uint32_t arg
[],
2021 const uint32_t par
[])
2023 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2024 tcg_gen_clzi_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], 32);
2028 static void translate_or(DisasContext
*dc
, const uint32_t arg
[],
2029 const uint32_t par
[])
2031 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2032 tcg_gen_or_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2036 static void translate_ptlb(DisasContext
*dc
, const uint32_t arg
[],
2037 const uint32_t par
[])
2039 if (gen_check_privilege(dc
) &&
2040 gen_window_check2(dc
, arg
[0], arg
[1])) {
2041 #ifndef CONFIG_USER_ONLY
2042 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2044 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2045 gen_helper_ptlb(cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], dtlb
);
2046 tcg_temp_free(dtlb
);
2051 static void gen_zero_check(DisasContext
*dc
, const uint32_t arg
[])
2053 TCGLabel
*label
= gen_new_label();
2055 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[2]], 0, label
);
2056 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
2057 gen_set_label(label
);
2060 static void translate_quos(DisasContext
*dc
, const uint32_t arg
[],
2061 const uint32_t par
[])
2063 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2064 TCGLabel
*label1
= gen_new_label();
2065 TCGLabel
*label2
= gen_new_label();
2067 gen_zero_check(dc
, arg
);
2069 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[1]], 0x80000000,
2071 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[arg
[2]], 0xffffffff,
2073 tcg_gen_movi_i32(cpu_R
[arg
[0]],
2074 par
[0] ? 0x80000000 : 0);
2076 gen_set_label(label1
);
2078 tcg_gen_div_i32(cpu_R
[arg
[0]],
2079 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2081 tcg_gen_rem_i32(cpu_R
[arg
[0]],
2082 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2084 gen_set_label(label2
);
2088 static void translate_quou(DisasContext
*dc
, const uint32_t arg
[],
2089 const uint32_t par
[])
2091 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2092 gen_zero_check(dc
, arg
);
2094 tcg_gen_divu_i32(cpu_R
[arg
[0]],
2095 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2097 tcg_gen_remu_i32(cpu_R
[arg
[0]],
2098 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2103 static void translate_read_impwire(DisasContext
*dc
, const uint32_t arg
[],
2104 const uint32_t par
[])
2106 if (gen_window_check1(dc
, arg
[0])) {
2107 /* TODO: GPIO32 may be a part of coprocessor */
2108 tcg_gen_movi_i32(cpu_R
[arg
[0]], 0);
2112 static void translate_rer(DisasContext
*dc
, const uint32_t arg
[],
2113 const uint32_t par
[])
2115 if (gen_check_privilege(dc
) &&
2116 gen_window_check2(dc
, arg
[0], arg
[1])) {
2117 gen_helper_rer(cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]]);
2121 static void translate_ret(DisasContext
*dc
, const uint32_t arg
[],
2122 const uint32_t par
[])
2124 gen_jump(dc
, cpu_R
[0]);
2127 static void translate_retw(DisasContext
*dc
, const uint32_t arg
[],
2128 const uint32_t par
[])
2130 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2131 gen_helper_retw(tmp
, cpu_env
, tmp
);
2136 static void translate_rfde(DisasContext
*dc
, const uint32_t arg
[],
2137 const uint32_t par
[])
2139 if (gen_check_privilege(dc
)) {
2140 gen_jump(dc
, cpu_SR
[dc
->config
->ndepc
? DEPC
: EPC1
]);
2144 static void translate_rfe(DisasContext
*dc
, const uint32_t arg
[],
2145 const uint32_t par
[])
2147 if (gen_check_privilege(dc
)) {
2148 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2149 gen_check_interrupts(dc
);
2150 gen_jump(dc
, cpu_SR
[EPC1
]);
2154 static void translate_rfi(DisasContext
*dc
, const uint32_t arg
[],
2155 const uint32_t par
[])
2157 if (gen_check_privilege(dc
)) {
2158 tcg_gen_mov_i32(cpu_SR
[PS
], cpu_SR
[EPS2
+ arg
[0] - 2]);
2159 gen_check_interrupts(dc
);
2160 gen_jump(dc
, cpu_SR
[EPC1
+ arg
[0] - 1]);
2164 static void translate_rfw(DisasContext
*dc
, const uint32_t arg
[],
2165 const uint32_t par
[])
2167 if (gen_check_privilege(dc
)) {
2168 TCGv_i32 tmp
= tcg_const_i32(1);
2170 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2171 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
2174 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
2175 cpu_SR
[WINDOW_START
], tmp
);
2177 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
2178 cpu_SR
[WINDOW_START
], tmp
);
2181 gen_helper_restore_owb(cpu_env
);
2182 gen_check_interrupts(dc
);
2183 gen_jump(dc
, cpu_SR
[EPC1
]);
2189 static void translate_rotw(DisasContext
*dc
, const uint32_t arg
[],
2190 const uint32_t par
[])
2192 if (gen_check_privilege(dc
)) {
2193 TCGv_i32 tmp
= tcg_const_i32(arg
[0]);
2194 gen_helper_rotw(cpu_env
, tmp
);
2196 /* This can change tb->flags, so exit tb */
2197 gen_jumpi_check_loop_end(dc
, -1);
2201 static void translate_rsil(DisasContext
*dc
, const uint32_t arg
[],
2202 const uint32_t par
[])
2204 if (gen_check_privilege(dc
) &&
2205 gen_window_check1(dc
, arg
[0])) {
2206 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_SR
[PS
]);
2207 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
2208 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], arg
[1]);
2209 gen_check_interrupts(dc
);
2210 gen_jumpi_check_loop_end(dc
, 0);
2214 static void translate_rsr(DisasContext
*dc
, const uint32_t arg
[],
2215 const uint32_t par
[])
2217 if (gen_check_sr(dc
, par
[0], SR_R
) &&
2218 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2219 gen_window_check1(dc
, arg
[0])) {
2220 if (gen_rsr(dc
, cpu_R
[arg
[0]], par
[0])) {
2221 gen_jumpi_check_loop_end(dc
, 0);
2226 static void translate_rtlb(DisasContext
*dc
, const uint32_t arg
[],
2227 const uint32_t par
[])
2229 static void (* const helper
[])(TCGv_i32 r
, TCGv_env env
, TCGv_i32 a1
,
2231 #ifndef CONFIG_USER_ONLY
2237 if (gen_check_privilege(dc
) &&
2238 gen_window_check2(dc
, arg
[0], arg
[1])) {
2239 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2241 helper
[par
[1]](cpu_R
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], dtlb
);
2242 tcg_temp_free(dtlb
);
2246 static void translate_rur(DisasContext
*dc
, const uint32_t arg
[],
2247 const uint32_t par
[])
2249 if (gen_window_check1(dc
, arg
[0])) {
2250 if (uregnames
[par
[0]].name
) {
2251 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_UR
[par
[0]]);
2253 qemu_log_mask(LOG_UNIMP
, "RUR %d not implemented\n", par
[0]);
2258 static void translate_setb_expstate(DisasContext
*dc
, const uint32_t arg
[],
2259 const uint32_t par
[])
2261 /* TODO: GPIO32 may be a part of coprocessor */
2262 tcg_gen_ori_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], 1u << arg
[0]);
2265 #ifdef CONFIG_USER_ONLY
2266 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2270 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2272 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
2274 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2279 static void translate_s32c1i(DisasContext
*dc
, const uint32_t arg
[],
2280 const uint32_t par
[])
2282 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2283 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2284 TCGv_i32 addr
= tcg_temp_local_new_i32();
2286 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
2287 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
2288 gen_load_store_alignment(dc
, 2, addr
, true);
2289 gen_check_atomctl(dc
, addr
);
2290 tcg_gen_atomic_cmpxchg_i32(cpu_R
[arg
[0]], addr
, cpu_SR
[SCOMPARE1
],
2291 tmp
, dc
->cring
, MO_32
);
2292 tcg_temp_free(addr
);
2297 static void translate_s32e(DisasContext
*dc
, const uint32_t arg
[],
2298 const uint32_t par
[])
2300 if (gen_check_privilege(dc
) &&
2301 gen_window_check2(dc
, arg
[0], arg
[1])) {
2302 TCGv_i32 addr
= tcg_temp_new_i32();
2304 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
2305 gen_load_store_alignment(dc
, 2, addr
, false);
2306 tcg_gen_qemu_st_tl(cpu_R
[arg
[0]], addr
, dc
->ring
, MO_TEUL
);
2307 tcg_temp_free(addr
);
2311 static void translate_salt(DisasContext
*dc
, const uint32_t arg
[],
2312 const uint32_t par
[])
2314 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2315 tcg_gen_setcond_i32(par
[0],
2317 cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2321 static void translate_sext(DisasContext
*dc
, const uint32_t arg
[],
2322 const uint32_t par
[])
2324 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2325 int shift
= 31 - arg
[2];
2328 tcg_gen_ext8s_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2329 } else if (shift
== 16) {
2330 tcg_gen_ext16s_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2332 TCGv_i32 tmp
= tcg_temp_new_i32();
2333 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], shift
);
2334 tcg_gen_sari_i32(cpu_R
[arg
[0]], tmp
, shift
);
2340 static void translate_simcall(DisasContext
*dc
, const uint32_t arg
[],
2341 const uint32_t par
[])
2343 #ifndef CONFIG_USER_ONLY
2344 if (semihosting_enabled()) {
2345 if (gen_check_privilege(dc
)) {
2346 gen_helper_simcall(cpu_env
);
2351 qemu_log_mask(LOG_GUEST_ERROR
, "SIMCALL but semihosting is disabled\n");
2352 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2357 * Note: 64 bit ops are used here solely because SAR values
2360 #define gen_shift_reg(cmd, reg) do { \
2361 TCGv_i64 tmp = tcg_temp_new_i64(); \
2362 tcg_gen_extu_i32_i64(tmp, reg); \
2363 tcg_gen_##cmd##_i64(v, v, tmp); \
2364 tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \
2365 tcg_temp_free_i64(v); \
2366 tcg_temp_free_i64(tmp); \
2369 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2371 static void translate_sll(DisasContext
*dc
, const uint32_t arg
[],
2372 const uint32_t par
[])
2374 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2375 if (dc
->sar_m32_5bit
) {
2376 tcg_gen_shl_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], dc
->sar_m32
);
2378 TCGv_i64 v
= tcg_temp_new_i64();
2379 TCGv_i32 s
= tcg_const_i32(32);
2380 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
2381 tcg_gen_andi_i32(s
, s
, 0x3f);
2382 tcg_gen_extu_i32_i64(v
, cpu_R
[arg
[1]]);
2383 gen_shift_reg(shl
, s
);
2389 static void translate_slli(DisasContext
*dc
, const uint32_t arg
[],
2390 const uint32_t par
[])
2392 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2394 qemu_log_mask(LOG_GUEST_ERROR
, "slli a%d, a%d, 32 is undefined\n",
2397 tcg_gen_shli_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2] & 0x1f);
2401 static void translate_sra(DisasContext
*dc
, const uint32_t arg
[],
2402 const uint32_t par
[])
2404 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2405 if (dc
->sar_m32_5bit
) {
2406 tcg_gen_sar_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_SR
[SAR
]);
2408 TCGv_i64 v
= tcg_temp_new_i64();
2409 tcg_gen_ext_i32_i64(v
, cpu_R
[arg
[1]]);
2415 static void translate_srai(DisasContext
*dc
, const uint32_t arg
[],
2416 const uint32_t par
[])
2418 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2419 tcg_gen_sari_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
2423 static void translate_src(DisasContext
*dc
, const uint32_t arg
[],
2424 const uint32_t par
[])
2426 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2427 TCGv_i64 v
= tcg_temp_new_i64();
2428 tcg_gen_concat_i32_i64(v
, cpu_R
[arg
[2]], cpu_R
[arg
[1]]);
2433 static void translate_srl(DisasContext
*dc
, const uint32_t arg
[],
2434 const uint32_t par
[])
2436 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2437 if (dc
->sar_m32_5bit
) {
2438 tcg_gen_shr_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_SR
[SAR
]);
2440 TCGv_i64 v
= tcg_temp_new_i64();
2441 tcg_gen_extu_i32_i64(v
, cpu_R
[arg
[1]]);
2448 #undef gen_shift_reg
2450 static void translate_srli(DisasContext
*dc
, const uint32_t arg
[],
2451 const uint32_t par
[])
2453 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2454 tcg_gen_shri_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], arg
[2]);
2458 static void translate_ssa8b(DisasContext
*dc
, const uint32_t arg
[],
2459 const uint32_t par
[])
2461 if (gen_window_check1(dc
, arg
[0])) {
2462 TCGv_i32 tmp
= tcg_temp_new_i32();
2463 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[0]], 3);
2464 gen_left_shift_sar(dc
, tmp
);
2469 static void translate_ssa8l(DisasContext
*dc
, const uint32_t arg
[],
2470 const uint32_t par
[])
2472 if (gen_window_check1(dc
, arg
[0])) {
2473 TCGv_i32 tmp
= tcg_temp_new_i32();
2474 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[0]], 3);
2475 gen_right_shift_sar(dc
, tmp
);
2480 static void translate_ssai(DisasContext
*dc
, const uint32_t arg
[],
2481 const uint32_t par
[])
2483 TCGv_i32 tmp
= tcg_const_i32(arg
[0]);
2484 gen_right_shift_sar(dc
, tmp
);
2488 static void translate_ssl(DisasContext
*dc
, const uint32_t arg
[],
2489 const uint32_t par
[])
2491 if (gen_window_check1(dc
, arg
[0])) {
2492 gen_left_shift_sar(dc
, cpu_R
[arg
[0]]);
2496 static void translate_ssr(DisasContext
*dc
, const uint32_t arg
[],
2497 const uint32_t par
[])
2499 if (gen_window_check1(dc
, arg
[0])) {
2500 gen_right_shift_sar(dc
, cpu_R
[arg
[0]]);
2504 static void translate_sub(DisasContext
*dc
, const uint32_t arg
[],
2505 const uint32_t par
[])
2507 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2508 tcg_gen_sub_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2512 static void translate_subx(DisasContext
*dc
, const uint32_t arg
[],
2513 const uint32_t par
[])
2515 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2516 TCGv_i32 tmp
= tcg_temp_new_i32();
2517 tcg_gen_shli_i32(tmp
, cpu_R
[arg
[1]], par
[0]);
2518 tcg_gen_sub_i32(cpu_R
[arg
[0]], tmp
, cpu_R
[arg
[2]]);
2523 static void translate_syscall(DisasContext
*dc
, const uint32_t arg
[],
2524 const uint32_t par
[])
2526 gen_exception_cause(dc
, SYSCALL_CAUSE
);
2529 static void translate_waiti(DisasContext
*dc
, const uint32_t arg
[],
2530 const uint32_t par
[])
2532 if (gen_check_privilege(dc
)) {
2533 #ifndef CONFIG_USER_ONLY
2534 gen_waiti(dc
, arg
[0]);
2539 static void translate_wtlb(DisasContext
*dc
, const uint32_t arg
[],
2540 const uint32_t par
[])
2542 if (gen_check_privilege(dc
) &&
2543 gen_window_check2(dc
, arg
[0], arg
[1])) {
2544 #ifndef CONFIG_USER_ONLY
2545 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2547 gen_helper_wtlb(cpu_env
, cpu_R
[arg
[0]], cpu_R
[arg
[1]], dtlb
);
2548 /* This could change memory mapping, so exit tb */
2549 gen_jumpi_check_loop_end(dc
, -1);
2550 tcg_temp_free(dtlb
);
2555 static void translate_wer(DisasContext
*dc
, const uint32_t arg
[],
2556 const uint32_t par
[])
2558 if (gen_check_privilege(dc
) &&
2559 gen_window_check2(dc
, arg
[0], arg
[1])) {
2560 gen_helper_wer(cpu_env
, cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2564 static void translate_wrmsk_expstate(DisasContext
*dc
, const uint32_t arg
[],
2565 const uint32_t par
[])
2567 if (gen_window_check2(dc
, arg
[0], arg
[1])) {
2568 /* TODO: GPIO32 may be a part of coprocessor */
2569 tcg_gen_and_i32(cpu_UR
[EXPSTATE
], cpu_R
[arg
[0]], cpu_R
[arg
[1]]);
2573 static void translate_wsr(DisasContext
*dc
, const uint32_t arg
[],
2574 const uint32_t par
[])
2576 if (gen_check_sr(dc
, par
[0], SR_W
) &&
2577 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2578 gen_window_check1(dc
, arg
[0])) {
2579 gen_wsr(dc
, par
[0], cpu_R
[arg
[0]]);
2583 static void translate_wur(DisasContext
*dc
, const uint32_t arg
[],
2584 const uint32_t par
[])
2586 if (gen_window_check1(dc
, arg
[0])) {
2587 if (uregnames
[par
[0]].name
) {
2588 gen_wur(par
[0], cpu_R
[arg
[0]]);
2590 qemu_log_mask(LOG_UNIMP
, "WUR %d not implemented\n", par
[0]);
2595 static void translate_xor(DisasContext
*dc
, const uint32_t arg
[],
2596 const uint32_t par
[])
2598 if (gen_window_check3(dc
, arg
[0], arg
[1], arg
[2])) {
2599 tcg_gen_xor_i32(cpu_R
[arg
[0]], cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
2603 static void translate_xsr(DisasContext
*dc
, const uint32_t arg
[],
2604 const uint32_t par
[])
2606 if (gen_check_sr(dc
, par
[0], SR_X
) &&
2607 (par
[0] < 64 || gen_check_privilege(dc
)) &&
2608 gen_window_check1(dc
, arg
[0])) {
2609 TCGv_i32 tmp
= tcg_temp_new_i32();
2610 bool rsr_end
, wsr_end
;
2612 tcg_gen_mov_i32(tmp
, cpu_R
[arg
[0]]);
2613 rsr_end
= gen_rsr(dc
, cpu_R
[arg
[0]], par
[0]);
2614 wsr_end
= gen_wsr(dc
, par
[0], tmp
);
2616 if (rsr_end
&& !wsr_end
) {
2617 gen_jumpi_check_loop_end(dc
, 0);
2622 static const XtensaOpcodeOps core_ops
[] = {
2625 .translate
= translate_abs
,
2628 .translate
= translate_add
,
2631 .translate
= translate_add
,
2634 .translate
= translate_addi
,
2637 .translate
= translate_addi
,
2640 .translate
= translate_addi
,
2643 .translate
= translate_addx
,
2644 .par
= (const uint32_t[]){1},
2647 .translate
= translate_addx
,
2648 .par
= (const uint32_t[]){2},
2651 .translate
= translate_addx
,
2652 .par
= (const uint32_t[]){3},
2655 .translate
= translate_all
,
2656 .par
= (const uint32_t[]){true, 4},
2659 .translate
= translate_all
,
2660 .par
= (const uint32_t[]){true, 8},
2663 .translate
= translate_and
,
2666 .translate
= translate_boolean
,
2667 .par
= (const uint32_t[]){BOOLEAN_AND
},
2670 .translate
= translate_boolean
,
2671 .par
= (const uint32_t[]){BOOLEAN_ANDC
},
2674 .translate
= translate_all
,
2675 .par
= (const uint32_t[]){false, 4},
2678 .translate
= translate_all
,
2679 .par
= (const uint32_t[]){false, 8},
2682 .translate
= translate_ball
,
2683 .par
= (const uint32_t[]){TCG_COND_EQ
},
2686 .translate
= translate_bany
,
2687 .par
= (const uint32_t[]){TCG_COND_NE
},
2690 .translate
= translate_bb
,
2691 .par
= (const uint32_t[]){TCG_COND_EQ
},
2694 .translate
= translate_bbi
,
2695 .par
= (const uint32_t[]){TCG_COND_EQ
},
2698 .translate
= translate_bb
,
2699 .par
= (const uint32_t[]){TCG_COND_NE
},
2702 .translate
= translate_bbi
,
2703 .par
= (const uint32_t[]){TCG_COND_NE
},
2706 .translate
= translate_b
,
2707 .par
= (const uint32_t[]){TCG_COND_EQ
},
2710 .translate
= translate_bi
,
2711 .par
= (const uint32_t[]){TCG_COND_EQ
},
2714 .translate
= translate_bz
,
2715 .par
= (const uint32_t[]){TCG_COND_EQ
},
2718 .translate
= translate_bz
,
2719 .par
= (const uint32_t[]){TCG_COND_EQ
},
2722 .translate
= translate_bp
,
2723 .par
= (const uint32_t[]){TCG_COND_EQ
},
2726 .translate
= translate_b
,
2727 .par
= (const uint32_t[]){TCG_COND_GE
},
2730 .translate
= translate_bi
,
2731 .par
= (const uint32_t[]){TCG_COND_GE
},
2734 .translate
= translate_b
,
2735 .par
= (const uint32_t[]){TCG_COND_GEU
},
2738 .translate
= translate_bi
,
2739 .par
= (const uint32_t[]){TCG_COND_GEU
},
2742 .translate
= translate_bz
,
2743 .par
= (const uint32_t[]){TCG_COND_GE
},
2746 .translate
= translate_b
,
2747 .par
= (const uint32_t[]){TCG_COND_LT
},
2750 .translate
= translate_bi
,
2751 .par
= (const uint32_t[]){TCG_COND_LT
},
2754 .translate
= translate_b
,
2755 .par
= (const uint32_t[]){TCG_COND_LTU
},
2758 .translate
= translate_bi
,
2759 .par
= (const uint32_t[]){TCG_COND_LTU
},
2762 .translate
= translate_bz
,
2763 .par
= (const uint32_t[]){TCG_COND_LT
},
2766 .translate
= translate_ball
,
2767 .par
= (const uint32_t[]){TCG_COND_NE
},
2770 .translate
= translate_b
,
2771 .par
= (const uint32_t[]){TCG_COND_NE
},
2774 .translate
= translate_bi
,
2775 .par
= (const uint32_t[]){TCG_COND_NE
},
2778 .translate
= translate_bz
,
2779 .par
= (const uint32_t[]){TCG_COND_NE
},
2782 .translate
= translate_bz
,
2783 .par
= (const uint32_t[]){TCG_COND_NE
},
2786 .translate
= translate_bany
,
2787 .par
= (const uint32_t[]){TCG_COND_EQ
},
2790 .translate
= translate_break
,
2791 .par
= (const uint32_t[]){DEBUGCAUSE_BI
},
2794 .translate
= translate_break
,
2795 .par
= (const uint32_t[]){DEBUGCAUSE_BN
},
2798 .translate
= translate_bp
,
2799 .par
= (const uint32_t[]){TCG_COND_NE
},
2802 .translate
= translate_call0
,
2805 .translate
= translate_callw
,
2806 .par
= (const uint32_t[]){3},
2809 .translate
= translate_callw
,
2810 .par
= (const uint32_t[]){1},
2813 .translate
= translate_callw
,
2814 .par
= (const uint32_t[]){2},
2817 .translate
= translate_callx0
,
2820 .translate
= translate_callxw
,
2821 .par
= (const uint32_t[]){3},
2824 .translate
= translate_callxw
,
2825 .par
= (const uint32_t[]){1},
2828 .translate
= translate_callxw
,
2829 .par
= (const uint32_t[]){2},
2832 .translate
= translate_clamps
,
2834 .name
= "clrb_expstate",
2835 .translate
= translate_clrb_expstate
,
2838 .translate
= translate_const16
,
2841 .translate
= translate_depbits
,
2844 .translate
= translate_dcache
,
2845 .par
= (const uint32_t[]){true, true},
2848 .translate
= translate_dcache
,
2849 .par
= (const uint32_t[]){true, true},
2852 .translate
= translate_dcache
,
2853 .par
= (const uint32_t[]){false, true},
2856 .translate
= translate_dcache
,
2857 .par
= (const uint32_t[]){false, true},
2860 .translate
= translate_dcache
,
2861 .par
= (const uint32_t[]){true, false},
2864 .translate
= translate_dcache
,
2865 .par
= (const uint32_t[]){true, false},
2868 .translate
= translate_dcache
,
2869 .par
= (const uint32_t[]){true, false},
2872 .translate
= translate_dcache
,
2873 .par
= (const uint32_t[]){true, false},
2876 .translate
= translate_dcache
,
2877 .par
= (const uint32_t[]){true, true},
2880 .translate
= translate_dcache
,
2881 .par
= (const uint32_t[]){false, false},
2884 .translate
= translate_dcache
,
2885 .par
= (const uint32_t[]){false, false},
2888 .translate
= translate_dcache
,
2889 .par
= (const uint32_t[]){false, false},
2892 .translate
= translate_dcache
,
2893 .par
= (const uint32_t[]){false, false},
2896 .translate
= translate_nop
,
2899 .translate
= translate_entry
,
2902 .translate
= translate_nop
,
2905 .translate
= translate_nop
,
2908 .translate
= translate_extui
,
2911 .translate
= translate_memw
,
2914 .translate
= translate_ill
,
2917 .translate
= translate_ill
,
2920 .translate
= translate_itlb
,
2921 .par
= (const uint32_t[]){true},
2924 .translate
= translate_icache
,
2925 .par
= (const uint32_t[]){false, true},
2928 .translate
= translate_icache
,
2929 .par
= (const uint32_t[]){true, true},
2932 .translate
= translate_icache
,
2933 .par
= (const uint32_t[]){true, false},
2936 .translate
= translate_itlb
,
2937 .par
= (const uint32_t[]){false},
2940 .translate
= translate_icache
,
2941 .par
= (const uint32_t[]){true, false},
2944 .translate
= translate_ill
,
2947 .translate
= translate_ill
,
2950 .translate
= translate_icache
,
2951 .par
= (const uint32_t[]){false, false},
2954 .translate
= translate_icache
,
2955 .par
= (const uint32_t[]){true, true},
2958 .translate
= translate_nop
,
2961 .translate
= translate_j
,
2964 .translate
= translate_jx
,
2967 .translate
= translate_ldst
,
2968 .par
= (const uint32_t[]){MO_TESW
, false, false},
2971 .translate
= translate_ldst
,
2972 .par
= (const uint32_t[]){MO_TEUW
, false, false},
2975 .translate
= translate_ldst
,
2976 .par
= (const uint32_t[]){MO_TEUL
, true, false},
2979 .translate
= translate_l32e
,
2982 .translate
= translate_ldst
,
2983 .par
= (const uint32_t[]){MO_TEUL
, false, false},
2986 .translate
= translate_ldst
,
2987 .par
= (const uint32_t[]){MO_TEUL
, false, false},
2990 .translate
= translate_l32r
,
2993 .translate
= translate_ldst
,
2994 .par
= (const uint32_t[]){MO_UB
, false, false},
2997 .translate
= translate_mac16
,
2998 .par
= (const uint32_t[]){MAC16_NONE
, 0, 0, -4},
3001 .translate
= translate_mac16
,
3002 .par
= (const uint32_t[]){MAC16_NONE
, 0, 0, 4},
3005 .translate
= translate_ill
,
3008 .translate
= translate_loop
,
3009 .par
= (const uint32_t[]){TCG_COND_NEVER
},
3012 .translate
= translate_loop
,
3013 .par
= (const uint32_t[]){TCG_COND_GT
},
3016 .translate
= translate_loop
,
3017 .par
= (const uint32_t[]){TCG_COND_NE
},
3020 .translate
= translate_smax
,
3023 .translate
= translate_umax
,
3026 .translate
= translate_memw
,
3029 .translate
= translate_smin
,
3032 .translate
= translate_umin
,
3035 .translate
= translate_mov
,
3038 .translate
= translate_mov
,
3041 .translate
= translate_movcond
,
3042 .par
= (const uint32_t[]){TCG_COND_EQ
},
3045 .translate
= translate_movp
,
3046 .par
= (const uint32_t[]){TCG_COND_EQ
},
3049 .translate
= translate_movcond
,
3050 .par
= (const uint32_t[]){TCG_COND_GE
},
3053 .translate
= translate_movi
,
3056 .translate
= translate_movi
,
3059 .translate
= translate_movcond
,
3060 .par
= (const uint32_t[]){TCG_COND_LT
},
3063 .translate
= translate_movcond
,
3064 .par
= (const uint32_t[]){TCG_COND_NE
},
3067 .translate
= translate_movsp
,
3070 .translate
= translate_movp
,
3071 .par
= (const uint32_t[]){TCG_COND_NE
},
3073 .name
= "mul.aa.hh",
3074 .translate
= translate_mac16
,
3075 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_HH
, 0},
3077 .name
= "mul.aa.hl",
3078 .translate
= translate_mac16
,
3079 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_HL
, 0},
3081 .name
= "mul.aa.lh",
3082 .translate
= translate_mac16
,
3083 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_LH
, 0},
3085 .name
= "mul.aa.ll",
3086 .translate
= translate_mac16
,
3087 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AA
, MAC16_LL
, 0},
3089 .name
= "mul.ad.hh",
3090 .translate
= translate_mac16
,
3091 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_HH
, 0},
3093 .name
= "mul.ad.hl",
3094 .translate
= translate_mac16
,
3095 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_HL
, 0},
3097 .name
= "mul.ad.lh",
3098 .translate
= translate_mac16
,
3099 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_LH
, 0},
3101 .name
= "mul.ad.ll",
3102 .translate
= translate_mac16
,
3103 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_AD
, MAC16_LL
, 0},
3105 .name
= "mul.da.hh",
3106 .translate
= translate_mac16
,
3107 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_HH
, 0},
3109 .name
= "mul.da.hl",
3110 .translate
= translate_mac16
,
3111 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_HL
, 0},
3113 .name
= "mul.da.lh",
3114 .translate
= translate_mac16
,
3115 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_LH
, 0},
3117 .name
= "mul.da.ll",
3118 .translate
= translate_mac16
,
3119 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DA
, MAC16_LL
, 0},
3121 .name
= "mul.dd.hh",
3122 .translate
= translate_mac16
,
3123 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_HH
, 0},
3125 .name
= "mul.dd.hl",
3126 .translate
= translate_mac16
,
3127 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_HL
, 0},
3129 .name
= "mul.dd.lh",
3130 .translate
= translate_mac16
,
3131 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_LH
, 0},
3133 .name
= "mul.dd.ll",
3134 .translate
= translate_mac16
,
3135 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_DD
, MAC16_LL
, 0},
3138 .translate
= translate_mul16
,
3139 .par
= (const uint32_t[]){true},
3142 .translate
= translate_mul16
,
3143 .par
= (const uint32_t[]){false},
3145 .name
= "mula.aa.hh",
3146 .translate
= translate_mac16
,
3147 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_HH
, 0},
3149 .name
= "mula.aa.hl",
3150 .translate
= translate_mac16
,
3151 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_HL
, 0},
3153 .name
= "mula.aa.lh",
3154 .translate
= translate_mac16
,
3155 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_LH
, 0},
3157 .name
= "mula.aa.ll",
3158 .translate
= translate_mac16
,
3159 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AA
, MAC16_LL
, 0},
3161 .name
= "mula.ad.hh",
3162 .translate
= translate_mac16
,
3163 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_HH
, 0},
3165 .name
= "mula.ad.hl",
3166 .translate
= translate_mac16
,
3167 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_HL
, 0},
3169 .name
= "mula.ad.lh",
3170 .translate
= translate_mac16
,
3171 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_LH
, 0},
3173 .name
= "mula.ad.ll",
3174 .translate
= translate_mac16
,
3175 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_AD
, MAC16_LL
, 0},
3177 .name
= "mula.da.hh",
3178 .translate
= translate_mac16
,
3179 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, 0},
3181 .name
= "mula.da.hh.lddec",
3182 .translate
= translate_mac16
,
3183 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, -4},
3185 .name
= "mula.da.hh.ldinc",
3186 .translate
= translate_mac16
,
3187 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HH
, 4},
3189 .name
= "mula.da.hl",
3190 .translate
= translate_mac16
,
3191 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, 0},
3193 .name
= "mula.da.hl.lddec",
3194 .translate
= translate_mac16
,
3195 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, -4},
3197 .name
= "mula.da.hl.ldinc",
3198 .translate
= translate_mac16
,
3199 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_HL
, 4},
3201 .name
= "mula.da.lh",
3202 .translate
= translate_mac16
,
3203 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, 0},
3205 .name
= "mula.da.lh.lddec",
3206 .translate
= translate_mac16
,
3207 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, -4},
3209 .name
= "mula.da.lh.ldinc",
3210 .translate
= translate_mac16
,
3211 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LH
, 4},
3213 .name
= "mula.da.ll",
3214 .translate
= translate_mac16
,
3215 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, 0},
3217 .name
= "mula.da.ll.lddec",
3218 .translate
= translate_mac16
,
3219 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, -4},
3221 .name
= "mula.da.ll.ldinc",
3222 .translate
= translate_mac16
,
3223 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DA
, MAC16_LL
, 4},
3225 .name
= "mula.dd.hh",
3226 .translate
= translate_mac16
,
3227 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, 0},
3229 .name
= "mula.dd.hh.lddec",
3230 .translate
= translate_mac16
,
3231 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, -4},
3233 .name
= "mula.dd.hh.ldinc",
3234 .translate
= translate_mac16
,
3235 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HH
, 4},
3237 .name
= "mula.dd.hl",
3238 .translate
= translate_mac16
,
3239 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, 0},
3241 .name
= "mula.dd.hl.lddec",
3242 .translate
= translate_mac16
,
3243 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, -4},
3245 .name
= "mula.dd.hl.ldinc",
3246 .translate
= translate_mac16
,
3247 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_HL
, 4},
3249 .name
= "mula.dd.lh",
3250 .translate
= translate_mac16
,
3251 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, 0},
3253 .name
= "mula.dd.lh.lddec",
3254 .translate
= translate_mac16
,
3255 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, -4},
3257 .name
= "mula.dd.lh.ldinc",
3258 .translate
= translate_mac16
,
3259 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LH
, 4},
3261 .name
= "mula.dd.ll",
3262 .translate
= translate_mac16
,
3263 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, 0},
3265 .name
= "mula.dd.ll.lddec",
3266 .translate
= translate_mac16
,
3267 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, -4},
3269 .name
= "mula.dd.ll.ldinc",
3270 .translate
= translate_mac16
,
3271 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_DD
, MAC16_LL
, 4},
3274 .translate
= translate_mull
,
3276 .name
= "muls.aa.hh",
3277 .translate
= translate_mac16
,
3278 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_HH
, 0},
3280 .name
= "muls.aa.hl",
3281 .translate
= translate_mac16
,
3282 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_HL
, 0},
3284 .name
= "muls.aa.lh",
3285 .translate
= translate_mac16
,
3286 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_LH
, 0},
3288 .name
= "muls.aa.ll",
3289 .translate
= translate_mac16
,
3290 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AA
, MAC16_LL
, 0},
3292 .name
= "muls.ad.hh",
3293 .translate
= translate_mac16
,
3294 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_HH
, 0},
3296 .name
= "muls.ad.hl",
3297 .translate
= translate_mac16
,
3298 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_HL
, 0},
3300 .name
= "muls.ad.lh",
3301 .translate
= translate_mac16
,
3302 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_LH
, 0},
3304 .name
= "muls.ad.ll",
3305 .translate
= translate_mac16
,
3306 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_AD
, MAC16_LL
, 0},
3308 .name
= "muls.da.hh",
3309 .translate
= translate_mac16
,
3310 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_HH
, 0},
3312 .name
= "muls.da.hl",
3313 .translate
= translate_mac16
,
3314 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_HL
, 0},
3316 .name
= "muls.da.lh",
3317 .translate
= translate_mac16
,
3318 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_LH
, 0},
3320 .name
= "muls.da.ll",
3321 .translate
= translate_mac16
,
3322 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DA
, MAC16_LL
, 0},
3324 .name
= "muls.dd.hh",
3325 .translate
= translate_mac16
,
3326 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_HH
, 0},
3328 .name
= "muls.dd.hl",
3329 .translate
= translate_mac16
,
3330 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_HL
, 0},
3332 .name
= "muls.dd.lh",
3333 .translate
= translate_mac16
,
3334 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_LH
, 0},
3336 .name
= "muls.dd.ll",
3337 .translate
= translate_mac16
,
3338 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_DD
, MAC16_LL
, 0},
3341 .translate
= translate_mulh
,
3342 .par
= (const uint32_t[]){true},
3345 .translate
= translate_mulh
,
3346 .par
= (const uint32_t[]){false},
3349 .translate
= translate_neg
,
3352 .translate
= translate_nop
,
3355 .translate
= translate_nop
,
3358 .translate
= translate_nsa
,
3361 .translate
= translate_nsau
,
3364 .translate
= translate_or
,
3367 .translate
= translate_boolean
,
3368 .par
= (const uint32_t[]){BOOLEAN_OR
},
3371 .translate
= translate_boolean
,
3372 .par
= (const uint32_t[]){BOOLEAN_ORC
},
3375 .translate
= translate_ptlb
,
3376 .par
= (const uint32_t[]){true},
3379 .translate
= translate_ptlb
,
3380 .par
= (const uint32_t[]){false},
3383 .translate
= translate_quos
,
3384 .par
= (const uint32_t[]){true},
3387 .translate
= translate_quou
,
3388 .par
= (const uint32_t[]){true},
3391 .translate
= translate_rtlb
,
3392 .par
= (const uint32_t[]){true, 0},
3395 .translate
= translate_rtlb
,
3396 .par
= (const uint32_t[]){true, 1},
3398 .name
= "read_impwire",
3399 .translate
= translate_read_impwire
,
3402 .translate
= translate_quos
,
3403 .par
= (const uint32_t[]){false},
3406 .translate
= translate_quou
,
3407 .par
= (const uint32_t[]){false},
3410 .translate
= translate_rer
,
3413 .translate
= translate_ret
,
3416 .translate
= translate_ret
,
3419 .translate
= translate_retw
,
3422 .translate
= translate_retw
,
3425 .translate
= translate_ill
,
3428 .translate
= translate_rfde
,
3431 .translate
= translate_ill
,
3434 .translate
= translate_rfe
,
3437 .translate
= translate_rfi
,
3440 .translate
= translate_rfw
,
3441 .par
= (const uint32_t[]){true},
3444 .translate
= translate_rfw
,
3445 .par
= (const uint32_t[]){false},
3448 .translate
= translate_rtlb
,
3449 .par
= (const uint32_t[]){false, 0},
3452 .translate
= translate_rtlb
,
3453 .par
= (const uint32_t[]){false, 1},
3456 .translate
= translate_rotw
,
3459 .translate
= translate_rsil
,
3462 .translate
= translate_rsr
,
3463 .par
= (const uint32_t[]){176},
3466 .translate
= translate_rsr
,
3467 .par
= (const uint32_t[]){208},
3469 .name
= "rsr.acchi",
3470 .translate
= translate_rsr
,
3471 .par
= (const uint32_t[]){ACCHI
},
3473 .name
= "rsr.acclo",
3474 .translate
= translate_rsr
,
3475 .par
= (const uint32_t[]){ACCLO
},
3477 .name
= "rsr.atomctl",
3478 .translate
= translate_rsr
,
3479 .par
= (const uint32_t[]){ATOMCTL
},
3482 .translate
= translate_rsr
,
3483 .par
= (const uint32_t[]){BR
},
3485 .name
= "rsr.cacheattr",
3486 .translate
= translate_rsr
,
3487 .par
= (const uint32_t[]){CACHEATTR
},
3489 .name
= "rsr.ccompare0",
3490 .translate
= translate_rsr
,
3491 .par
= (const uint32_t[]){CCOMPARE
},
3493 .name
= "rsr.ccompare1",
3494 .translate
= translate_rsr
,
3495 .par
= (const uint32_t[]){CCOMPARE
+ 1},
3497 .name
= "rsr.ccompare2",
3498 .translate
= translate_rsr
,
3499 .par
= (const uint32_t[]){CCOMPARE
+ 2},
3501 .name
= "rsr.ccount",
3502 .translate
= translate_rsr
,
3503 .par
= (const uint32_t[]){CCOUNT
},
3505 .name
= "rsr.configid0",
3506 .translate
= translate_rsr
,
3507 .par
= (const uint32_t[]){CONFIGID0
},
3509 .name
= "rsr.configid1",
3510 .translate
= translate_rsr
,
3511 .par
= (const uint32_t[]){CONFIGID1
},
3513 .name
= "rsr.cpenable",
3514 .translate
= translate_rsr
,
3515 .par
= (const uint32_t[]){CPENABLE
},
3517 .name
= "rsr.dbreaka0",
3518 .translate
= translate_rsr
,
3519 .par
= (const uint32_t[]){DBREAKA
},
3521 .name
= "rsr.dbreaka1",
3522 .translate
= translate_rsr
,
3523 .par
= (const uint32_t[]){DBREAKA
+ 1},
3525 .name
= "rsr.dbreakc0",
3526 .translate
= translate_rsr
,
3527 .par
= (const uint32_t[]){DBREAKC
},
3529 .name
= "rsr.dbreakc1",
3530 .translate
= translate_rsr
,
3531 .par
= (const uint32_t[]){DBREAKC
+ 1},
3534 .translate
= translate_rsr
,
3535 .par
= (const uint32_t[]){DDR
},
3537 .name
= "rsr.debugcause",
3538 .translate
= translate_rsr
,
3539 .par
= (const uint32_t[]){DEBUGCAUSE
},
3542 .translate
= translate_rsr
,
3543 .par
= (const uint32_t[]){DEPC
},
3545 .name
= "rsr.dtlbcfg",
3546 .translate
= translate_rsr
,
3547 .par
= (const uint32_t[]){DTLBCFG
},
3550 .translate
= translate_rsr
,
3551 .par
= (const uint32_t[]){EPC1
},
3554 .translate
= translate_rsr
,
3555 .par
= (const uint32_t[]){EPC1
+ 1},
3558 .translate
= translate_rsr
,
3559 .par
= (const uint32_t[]){EPC1
+ 2},
3562 .translate
= translate_rsr
,
3563 .par
= (const uint32_t[]){EPC1
+ 3},
3566 .translate
= translate_rsr
,
3567 .par
= (const uint32_t[]){EPC1
+ 4},
3570 .translate
= translate_rsr
,
3571 .par
= (const uint32_t[]){EPC1
+ 5},
3574 .translate
= translate_rsr
,
3575 .par
= (const uint32_t[]){EPC1
+ 6},
3578 .translate
= translate_rsr
,
3579 .par
= (const uint32_t[]){EPS2
},
3582 .translate
= translate_rsr
,
3583 .par
= (const uint32_t[]){EPS2
+ 1},
3586 .translate
= translate_rsr
,
3587 .par
= (const uint32_t[]){EPS2
+ 2},
3590 .translate
= translate_rsr
,
3591 .par
= (const uint32_t[]){EPS2
+ 3},
3594 .translate
= translate_rsr
,
3595 .par
= (const uint32_t[]){EPS2
+ 4},
3598 .translate
= translate_rsr
,
3599 .par
= (const uint32_t[]){EPS2
+ 5},
3601 .name
= "rsr.exccause",
3602 .translate
= translate_rsr
,
3603 .par
= (const uint32_t[]){EXCCAUSE
},
3605 .name
= "rsr.excsave1",
3606 .translate
= translate_rsr
,
3607 .par
= (const uint32_t[]){EXCSAVE1
},
3609 .name
= "rsr.excsave2",
3610 .translate
= translate_rsr
,
3611 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
3613 .name
= "rsr.excsave3",
3614 .translate
= translate_rsr
,
3615 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
3617 .name
= "rsr.excsave4",
3618 .translate
= translate_rsr
,
3619 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
3621 .name
= "rsr.excsave5",
3622 .translate
= translate_rsr
,
3623 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
3625 .name
= "rsr.excsave6",
3626 .translate
= translate_rsr
,
3627 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
3629 .name
= "rsr.excsave7",
3630 .translate
= translate_rsr
,
3631 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
3633 .name
= "rsr.excvaddr",
3634 .translate
= translate_rsr
,
3635 .par
= (const uint32_t[]){EXCVADDR
},
3637 .name
= "rsr.ibreaka0",
3638 .translate
= translate_rsr
,
3639 .par
= (const uint32_t[]){IBREAKA
},
3641 .name
= "rsr.ibreaka1",
3642 .translate
= translate_rsr
,
3643 .par
= (const uint32_t[]){IBREAKA
+ 1},
3645 .name
= "rsr.ibreakenable",
3646 .translate
= translate_rsr
,
3647 .par
= (const uint32_t[]){IBREAKENABLE
},
3649 .name
= "rsr.icount",
3650 .translate
= translate_rsr
,
3651 .par
= (const uint32_t[]){ICOUNT
},
3653 .name
= "rsr.icountlevel",
3654 .translate
= translate_rsr
,
3655 .par
= (const uint32_t[]){ICOUNTLEVEL
},
3657 .name
= "rsr.intclear",
3658 .translate
= translate_rsr
,
3659 .par
= (const uint32_t[]){INTCLEAR
},
3661 .name
= "rsr.intenable",
3662 .translate
= translate_rsr
,
3663 .par
= (const uint32_t[]){INTENABLE
},
3665 .name
= "rsr.interrupt",
3666 .translate
= translate_rsr
,
3667 .par
= (const uint32_t[]){INTSET
},
3669 .name
= "rsr.intset",
3670 .translate
= translate_rsr
,
3671 .par
= (const uint32_t[]){INTSET
},
3673 .name
= "rsr.itlbcfg",
3674 .translate
= translate_rsr
,
3675 .par
= (const uint32_t[]){ITLBCFG
},
3678 .translate
= translate_rsr
,
3679 .par
= (const uint32_t[]){LBEG
},
3681 .name
= "rsr.lcount",
3682 .translate
= translate_rsr
,
3683 .par
= (const uint32_t[]){LCOUNT
},
3686 .translate
= translate_rsr
,
3687 .par
= (const uint32_t[]){LEND
},
3689 .name
= "rsr.litbase",
3690 .translate
= translate_rsr
,
3691 .par
= (const uint32_t[]){LITBASE
},
3694 .translate
= translate_rsr
,
3695 .par
= (const uint32_t[]){MR
},
3698 .translate
= translate_rsr
,
3699 .par
= (const uint32_t[]){MR
+ 1},
3702 .translate
= translate_rsr
,
3703 .par
= (const uint32_t[]){MR
+ 2},
3706 .translate
= translate_rsr
,
3707 .par
= (const uint32_t[]){MR
+ 3},
3709 .name
= "rsr.memctl",
3710 .translate
= translate_rsr
,
3711 .par
= (const uint32_t[]){MEMCTL
},
3713 .name
= "rsr.misc0",
3714 .translate
= translate_rsr
,
3715 .par
= (const uint32_t[]){MISC
},
3717 .name
= "rsr.misc1",
3718 .translate
= translate_rsr
,
3719 .par
= (const uint32_t[]){MISC
+ 1},
3721 .name
= "rsr.misc2",
3722 .translate
= translate_rsr
,
3723 .par
= (const uint32_t[]){MISC
+ 2},
3725 .name
= "rsr.misc3",
3726 .translate
= translate_rsr
,
3727 .par
= (const uint32_t[]){MISC
+ 3},
3730 .translate
= translate_rsr
,
3731 .par
= (const uint32_t[]){PRID
},
3734 .translate
= translate_rsr
,
3735 .par
= (const uint32_t[]){PS
},
3737 .name
= "rsr.ptevaddr",
3738 .translate
= translate_rsr
,
3739 .par
= (const uint32_t[]){PTEVADDR
},
3741 .name
= "rsr.rasid",
3742 .translate
= translate_rsr
,
3743 .par
= (const uint32_t[]){RASID
},
3746 .translate
= translate_rsr
,
3747 .par
= (const uint32_t[]){SAR
},
3749 .name
= "rsr.scompare1",
3750 .translate
= translate_rsr
,
3751 .par
= (const uint32_t[]){SCOMPARE1
},
3753 .name
= "rsr.vecbase",
3754 .translate
= translate_rsr
,
3755 .par
= (const uint32_t[]){VECBASE
},
3757 .name
= "rsr.windowbase",
3758 .translate
= translate_rsr
,
3759 .par
= (const uint32_t[]){WINDOW_BASE
},
3761 .name
= "rsr.windowstart",
3762 .translate
= translate_rsr
,
3763 .par
= (const uint32_t[]){WINDOW_START
},
3766 .translate
= translate_nop
,
3768 .name
= "rur.expstate",
3769 .translate
= translate_rur
,
3770 .par
= (const uint32_t[]){EXPSTATE
},
3773 .translate
= translate_rur
,
3774 .par
= (const uint32_t[]){FCR
},
3777 .translate
= translate_rur
,
3778 .par
= (const uint32_t[]){FSR
},
3780 .name
= "rur.threadptr",
3781 .translate
= translate_rur
,
3782 .par
= (const uint32_t[]){THREADPTR
},
3785 .translate
= translate_ldst
,
3786 .par
= (const uint32_t[]){MO_TEUW
, false, true},
3789 .translate
= translate_s32c1i
,
3792 .translate
= translate_s32e
,
3795 .translate
= translate_ldst
,
3796 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3799 .translate
= translate_ldst
,
3800 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3803 .translate
= translate_ldst
,
3804 .par
= (const uint32_t[]){MO_TEUL
, false, true},
3807 .translate
= translate_ldst
,
3808 .par
= (const uint32_t[]){MO_TEUL
, true, true},
3811 .translate
= translate_ldst
,
3812 .par
= (const uint32_t[]){MO_UB
, false, true},
3815 .translate
= translate_salt
,
3816 .par
= (const uint32_t[]){TCG_COND_LT
},
3819 .translate
= translate_salt
,
3820 .par
= (const uint32_t[]){TCG_COND_LTU
},
3822 .name
= "setb_expstate",
3823 .translate
= translate_setb_expstate
,
3826 .translate
= translate_sext
,
3829 .translate
= translate_simcall
,
3832 .translate
= translate_sll
,
3835 .translate
= translate_slli
,
3838 .translate
= translate_sra
,
3841 .translate
= translate_srai
,
3844 .translate
= translate_src
,
3847 .translate
= translate_srl
,
3850 .translate
= translate_srli
,
3853 .translate
= translate_ssa8b
,
3856 .translate
= translate_ssa8l
,
3859 .translate
= translate_ssai
,
3862 .translate
= translate_ssl
,
3865 .translate
= translate_ssr
,
3868 .translate
= translate_sub
,
3871 .translate
= translate_subx
,
3872 .par
= (const uint32_t[]){1},
3875 .translate
= translate_subx
,
3876 .par
= (const uint32_t[]){2},
3879 .translate
= translate_subx
,
3880 .par
= (const uint32_t[]){3},
3883 .translate
= translate_syscall
,
3885 .name
= "umul.aa.hh",
3886 .translate
= translate_mac16
,
3887 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_HH
, 0},
3889 .name
= "umul.aa.hl",
3890 .translate
= translate_mac16
,
3891 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_HL
, 0},
3893 .name
= "umul.aa.lh",
3894 .translate
= translate_mac16
,
3895 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_LH
, 0},
3897 .name
= "umul.aa.ll",
3898 .translate
= translate_mac16
,
3899 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_AA
, MAC16_LL
, 0},
3902 .translate
= translate_waiti
,
3905 .translate
= translate_wtlb
,
3906 .par
= (const uint32_t[]){true},
3909 .translate
= translate_wer
,
3912 .translate
= translate_wtlb
,
3913 .par
= (const uint32_t[]){false},
3915 .name
= "wrmsk_expstate",
3916 .translate
= translate_wrmsk_expstate
,
3919 .translate
= translate_wsr
,
3920 .par
= (const uint32_t[]){176},
3923 .translate
= translate_wsr
,
3924 .par
= (const uint32_t[]){208},
3926 .name
= "wsr.acchi",
3927 .translate
= translate_wsr
,
3928 .par
= (const uint32_t[]){ACCHI
},
3930 .name
= "wsr.acclo",
3931 .translate
= translate_wsr
,
3932 .par
= (const uint32_t[]){ACCLO
},
3934 .name
= "wsr.atomctl",
3935 .translate
= translate_wsr
,
3936 .par
= (const uint32_t[]){ATOMCTL
},
3939 .translate
= translate_wsr
,
3940 .par
= (const uint32_t[]){BR
},
3942 .name
= "wsr.cacheattr",
3943 .translate
= translate_wsr
,
3944 .par
= (const uint32_t[]){CACHEATTR
},
3946 .name
= "wsr.ccompare0",
3947 .translate
= translate_wsr
,
3948 .par
= (const uint32_t[]){CCOMPARE
},
3950 .name
= "wsr.ccompare1",
3951 .translate
= translate_wsr
,
3952 .par
= (const uint32_t[]){CCOMPARE
+ 1},
3954 .name
= "wsr.ccompare2",
3955 .translate
= translate_wsr
,
3956 .par
= (const uint32_t[]){CCOMPARE
+ 2},
3958 .name
= "wsr.ccount",
3959 .translate
= translate_wsr
,
3960 .par
= (const uint32_t[]){CCOUNT
},
3962 .name
= "wsr.configid0",
3963 .translate
= translate_wsr
,
3964 .par
= (const uint32_t[]){CONFIGID0
},
3966 .name
= "wsr.configid1",
3967 .translate
= translate_wsr
,
3968 .par
= (const uint32_t[]){CONFIGID1
},
3970 .name
= "wsr.cpenable",
3971 .translate
= translate_wsr
,
3972 .par
= (const uint32_t[]){CPENABLE
},
3974 .name
= "wsr.dbreaka0",
3975 .translate
= translate_wsr
,
3976 .par
= (const uint32_t[]){DBREAKA
},
3978 .name
= "wsr.dbreaka1",
3979 .translate
= translate_wsr
,
3980 .par
= (const uint32_t[]){DBREAKA
+ 1},
3982 .name
= "wsr.dbreakc0",
3983 .translate
= translate_wsr
,
3984 .par
= (const uint32_t[]){DBREAKC
},
3986 .name
= "wsr.dbreakc1",
3987 .translate
= translate_wsr
,
3988 .par
= (const uint32_t[]){DBREAKC
+ 1},
3991 .translate
= translate_wsr
,
3992 .par
= (const uint32_t[]){DDR
},
3994 .name
= "wsr.debugcause",
3995 .translate
= translate_wsr
,
3996 .par
= (const uint32_t[]){DEBUGCAUSE
},
3999 .translate
= translate_wsr
,
4000 .par
= (const uint32_t[]){DEPC
},
4002 .name
= "wsr.dtlbcfg",
4003 .translate
= translate_wsr
,
4004 .par
= (const uint32_t[]){DTLBCFG
},
4007 .translate
= translate_wsr
,
4008 .par
= (const uint32_t[]){EPC1
},
4011 .translate
= translate_wsr
,
4012 .par
= (const uint32_t[]){EPC1
+ 1},
4015 .translate
= translate_wsr
,
4016 .par
= (const uint32_t[]){EPC1
+ 2},
4019 .translate
= translate_wsr
,
4020 .par
= (const uint32_t[]){EPC1
+ 3},
4023 .translate
= translate_wsr
,
4024 .par
= (const uint32_t[]){EPC1
+ 4},
4027 .translate
= translate_wsr
,
4028 .par
= (const uint32_t[]){EPC1
+ 5},
4031 .translate
= translate_wsr
,
4032 .par
= (const uint32_t[]){EPC1
+ 6},
4035 .translate
= translate_wsr
,
4036 .par
= (const uint32_t[]){EPS2
},
4039 .translate
= translate_wsr
,
4040 .par
= (const uint32_t[]){EPS2
+ 1},
4043 .translate
= translate_wsr
,
4044 .par
= (const uint32_t[]){EPS2
+ 2},
4047 .translate
= translate_wsr
,
4048 .par
= (const uint32_t[]){EPS2
+ 3},
4051 .translate
= translate_wsr
,
4052 .par
= (const uint32_t[]){EPS2
+ 4},
4055 .translate
= translate_wsr
,
4056 .par
= (const uint32_t[]){EPS2
+ 5},
4058 .name
= "wsr.exccause",
4059 .translate
= translate_wsr
,
4060 .par
= (const uint32_t[]){EXCCAUSE
},
4062 .name
= "wsr.excsave1",
4063 .translate
= translate_wsr
,
4064 .par
= (const uint32_t[]){EXCSAVE1
},
4066 .name
= "wsr.excsave2",
4067 .translate
= translate_wsr
,
4068 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
4070 .name
= "wsr.excsave3",
4071 .translate
= translate_wsr
,
4072 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
4074 .name
= "wsr.excsave4",
4075 .translate
= translate_wsr
,
4076 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
4078 .name
= "wsr.excsave5",
4079 .translate
= translate_wsr
,
4080 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
4082 .name
= "wsr.excsave6",
4083 .translate
= translate_wsr
,
4084 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
4086 .name
= "wsr.excsave7",
4087 .translate
= translate_wsr
,
4088 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
4090 .name
= "wsr.excvaddr",
4091 .translate
= translate_wsr
,
4092 .par
= (const uint32_t[]){EXCVADDR
},
4094 .name
= "wsr.ibreaka0",
4095 .translate
= translate_wsr
,
4096 .par
= (const uint32_t[]){IBREAKA
},
4098 .name
= "wsr.ibreaka1",
4099 .translate
= translate_wsr
,
4100 .par
= (const uint32_t[]){IBREAKA
+ 1},
4102 .name
= "wsr.ibreakenable",
4103 .translate
= translate_wsr
,
4104 .par
= (const uint32_t[]){IBREAKENABLE
},
4106 .name
= "wsr.icount",
4107 .translate
= translate_wsr
,
4108 .par
= (const uint32_t[]){ICOUNT
},
4110 .name
= "wsr.icountlevel",
4111 .translate
= translate_wsr
,
4112 .par
= (const uint32_t[]){ICOUNTLEVEL
},
4114 .name
= "wsr.intclear",
4115 .translate
= translate_wsr
,
4116 .par
= (const uint32_t[]){INTCLEAR
},
4118 .name
= "wsr.intenable",
4119 .translate
= translate_wsr
,
4120 .par
= (const uint32_t[]){INTENABLE
},
4122 .name
= "wsr.interrupt",
4123 .translate
= translate_wsr
,
4124 .par
= (const uint32_t[]){INTSET
},
4126 .name
= "wsr.intset",
4127 .translate
= translate_wsr
,
4128 .par
= (const uint32_t[]){INTSET
},
4130 .name
= "wsr.itlbcfg",
4131 .translate
= translate_wsr
,
4132 .par
= (const uint32_t[]){ITLBCFG
},
4135 .translate
= translate_wsr
,
4136 .par
= (const uint32_t[]){LBEG
},
4138 .name
= "wsr.lcount",
4139 .translate
= translate_wsr
,
4140 .par
= (const uint32_t[]){LCOUNT
},
4143 .translate
= translate_wsr
,
4144 .par
= (const uint32_t[]){LEND
},
4146 .name
= "wsr.litbase",
4147 .translate
= translate_wsr
,
4148 .par
= (const uint32_t[]){LITBASE
},
4151 .translate
= translate_wsr
,
4152 .par
= (const uint32_t[]){MR
},
4155 .translate
= translate_wsr
,
4156 .par
= (const uint32_t[]){MR
+ 1},
4159 .translate
= translate_wsr
,
4160 .par
= (const uint32_t[]){MR
+ 2},
4163 .translate
= translate_wsr
,
4164 .par
= (const uint32_t[]){MR
+ 3},
4166 .name
= "wsr.memctl",
4167 .translate
= translate_wsr
,
4168 .par
= (const uint32_t[]){MEMCTL
},
4170 .name
= "wsr.misc0",
4171 .translate
= translate_wsr
,
4172 .par
= (const uint32_t[]){MISC
},
4174 .name
= "wsr.misc1",
4175 .translate
= translate_wsr
,
4176 .par
= (const uint32_t[]){MISC
+ 1},
4178 .name
= "wsr.misc2",
4179 .translate
= translate_wsr
,
4180 .par
= (const uint32_t[]){MISC
+ 2},
4182 .name
= "wsr.misc3",
4183 .translate
= translate_wsr
,
4184 .par
= (const uint32_t[]){MISC
+ 3},
4187 .translate
= translate_wsr
,
4188 .par
= (const uint32_t[]){MMID
},
4191 .translate
= translate_wsr
,
4192 .par
= (const uint32_t[]){PRID
},
4195 .translate
= translate_wsr
,
4196 .par
= (const uint32_t[]){PS
},
4198 .name
= "wsr.ptevaddr",
4199 .translate
= translate_wsr
,
4200 .par
= (const uint32_t[]){PTEVADDR
},
4202 .name
= "wsr.rasid",
4203 .translate
= translate_wsr
,
4204 .par
= (const uint32_t[]){RASID
},
4207 .translate
= translate_wsr
,
4208 .par
= (const uint32_t[]){SAR
},
4210 .name
= "wsr.scompare1",
4211 .translate
= translate_wsr
,
4212 .par
= (const uint32_t[]){SCOMPARE1
},
4214 .name
= "wsr.vecbase",
4215 .translate
= translate_wsr
,
4216 .par
= (const uint32_t[]){VECBASE
},
4218 .name
= "wsr.windowbase",
4219 .translate
= translate_wsr
,
4220 .par
= (const uint32_t[]){WINDOW_BASE
},
4222 .name
= "wsr.windowstart",
4223 .translate
= translate_wsr
,
4224 .par
= (const uint32_t[]){WINDOW_START
},
4226 .name
= "wur.expstate",
4227 .translate
= translate_wur
,
4228 .par
= (const uint32_t[]){EXPSTATE
},
4231 .translate
= translate_wur
,
4232 .par
= (const uint32_t[]){FCR
},
4235 .translate
= translate_wur
,
4236 .par
= (const uint32_t[]){FSR
},
4238 .name
= "wur.threadptr",
4239 .translate
= translate_wur
,
4240 .par
= (const uint32_t[]){THREADPTR
},
4243 .translate
= translate_xor
,
4246 .translate
= translate_boolean
,
4247 .par
= (const uint32_t[]){BOOLEAN_XOR
},
4250 .translate
= translate_xsr
,
4251 .par
= (const uint32_t[]){176},
4254 .translate
= translate_xsr
,
4255 .par
= (const uint32_t[]){208},
4257 .name
= "xsr.acchi",
4258 .translate
= translate_xsr
,
4259 .par
= (const uint32_t[]){ACCHI
},
4261 .name
= "xsr.acclo",
4262 .translate
= translate_xsr
,
4263 .par
= (const uint32_t[]){ACCLO
},
4265 .name
= "xsr.atomctl",
4266 .translate
= translate_xsr
,
4267 .par
= (const uint32_t[]){ATOMCTL
},
4270 .translate
= translate_xsr
,
4271 .par
= (const uint32_t[]){BR
},
4273 .name
= "xsr.cacheattr",
4274 .translate
= translate_xsr
,
4275 .par
= (const uint32_t[]){CACHEATTR
},
4277 .name
= "xsr.ccompare0",
4278 .translate
= translate_xsr
,
4279 .par
= (const uint32_t[]){CCOMPARE
},
4281 .name
= "xsr.ccompare1",
4282 .translate
= translate_xsr
,
4283 .par
= (const uint32_t[]){CCOMPARE
+ 1},
4285 .name
= "xsr.ccompare2",
4286 .translate
= translate_xsr
,
4287 .par
= (const uint32_t[]){CCOMPARE
+ 2},
4289 .name
= "xsr.ccount",
4290 .translate
= translate_xsr
,
4291 .par
= (const uint32_t[]){CCOUNT
},
4293 .name
= "xsr.configid0",
4294 .translate
= translate_xsr
,
4295 .par
= (const uint32_t[]){CONFIGID0
},
4297 .name
= "xsr.configid1",
4298 .translate
= translate_xsr
,
4299 .par
= (const uint32_t[]){CONFIGID1
},
4301 .name
= "xsr.cpenable",
4302 .translate
= translate_xsr
,
4303 .par
= (const uint32_t[]){CPENABLE
},
4305 .name
= "xsr.dbreaka0",
4306 .translate
= translate_xsr
,
4307 .par
= (const uint32_t[]){DBREAKA
},
4309 .name
= "xsr.dbreaka1",
4310 .translate
= translate_xsr
,
4311 .par
= (const uint32_t[]){DBREAKA
+ 1},
4313 .name
= "xsr.dbreakc0",
4314 .translate
= translate_xsr
,
4315 .par
= (const uint32_t[]){DBREAKC
},
4317 .name
= "xsr.dbreakc1",
4318 .translate
= translate_xsr
,
4319 .par
= (const uint32_t[]){DBREAKC
+ 1},
4322 .translate
= translate_xsr
,
4323 .par
= (const uint32_t[]){DDR
},
4325 .name
= "xsr.debugcause",
4326 .translate
= translate_xsr
,
4327 .par
= (const uint32_t[]){DEBUGCAUSE
},
4330 .translate
= translate_xsr
,
4331 .par
= (const uint32_t[]){DEPC
},
4333 .name
= "xsr.dtlbcfg",
4334 .translate
= translate_xsr
,
4335 .par
= (const uint32_t[]){DTLBCFG
},
4338 .translate
= translate_xsr
,
4339 .par
= (const uint32_t[]){EPC1
},
4342 .translate
= translate_xsr
,
4343 .par
= (const uint32_t[]){EPC1
+ 1},
4346 .translate
= translate_xsr
,
4347 .par
= (const uint32_t[]){EPC1
+ 2},
4350 .translate
= translate_xsr
,
4351 .par
= (const uint32_t[]){EPC1
+ 3},
4354 .translate
= translate_xsr
,
4355 .par
= (const uint32_t[]){EPC1
+ 4},
4358 .translate
= translate_xsr
,
4359 .par
= (const uint32_t[]){EPC1
+ 5},
4362 .translate
= translate_xsr
,
4363 .par
= (const uint32_t[]){EPC1
+ 6},
4366 .translate
= translate_xsr
,
4367 .par
= (const uint32_t[]){EPS2
},
4370 .translate
= translate_xsr
,
4371 .par
= (const uint32_t[]){EPS2
+ 1},
4374 .translate
= translate_xsr
,
4375 .par
= (const uint32_t[]){EPS2
+ 2},
4378 .translate
= translate_xsr
,
4379 .par
= (const uint32_t[]){EPS2
+ 3},
4382 .translate
= translate_xsr
,
4383 .par
= (const uint32_t[]){EPS2
+ 4},
4386 .translate
= translate_xsr
,
4387 .par
= (const uint32_t[]){EPS2
+ 5},
4389 .name
= "xsr.exccause",
4390 .translate
= translate_xsr
,
4391 .par
= (const uint32_t[]){EXCCAUSE
},
4393 .name
= "xsr.excsave1",
4394 .translate
= translate_xsr
,
4395 .par
= (const uint32_t[]){EXCSAVE1
},
4397 .name
= "xsr.excsave2",
4398 .translate
= translate_xsr
,
4399 .par
= (const uint32_t[]){EXCSAVE1
+ 1},
4401 .name
= "xsr.excsave3",
4402 .translate
= translate_xsr
,
4403 .par
= (const uint32_t[]){EXCSAVE1
+ 2},
4405 .name
= "xsr.excsave4",
4406 .translate
= translate_xsr
,
4407 .par
= (const uint32_t[]){EXCSAVE1
+ 3},
4409 .name
= "xsr.excsave5",
4410 .translate
= translate_xsr
,
4411 .par
= (const uint32_t[]){EXCSAVE1
+ 4},
4413 .name
= "xsr.excsave6",
4414 .translate
= translate_xsr
,
4415 .par
= (const uint32_t[]){EXCSAVE1
+ 5},
4417 .name
= "xsr.excsave7",
4418 .translate
= translate_xsr
,
4419 .par
= (const uint32_t[]){EXCSAVE1
+ 6},
4421 .name
= "xsr.excvaddr",
4422 .translate
= translate_xsr
,
4423 .par
= (const uint32_t[]){EXCVADDR
},
4425 .name
= "xsr.ibreaka0",
4426 .translate
= translate_xsr
,
4427 .par
= (const uint32_t[]){IBREAKA
},
4429 .name
= "xsr.ibreaka1",
4430 .translate
= translate_xsr
,
4431 .par
= (const uint32_t[]){IBREAKA
+ 1},
4433 .name
= "xsr.ibreakenable",
4434 .translate
= translate_xsr
,
4435 .par
= (const uint32_t[]){IBREAKENABLE
},
4437 .name
= "xsr.icount",
4438 .translate
= translate_xsr
,
4439 .par
= (const uint32_t[]){ICOUNT
},
4441 .name
= "xsr.icountlevel",
4442 .translate
= translate_xsr
,
4443 .par
= (const uint32_t[]){ICOUNTLEVEL
},
4445 .name
= "xsr.intclear",
4446 .translate
= translate_xsr
,
4447 .par
= (const uint32_t[]){INTCLEAR
},
4449 .name
= "xsr.intenable",
4450 .translate
= translate_xsr
,
4451 .par
= (const uint32_t[]){INTENABLE
},
4453 .name
= "xsr.interrupt",
4454 .translate
= translate_xsr
,
4455 .par
= (const uint32_t[]){INTSET
},
4457 .name
= "xsr.intset",
4458 .translate
= translate_xsr
,
4459 .par
= (const uint32_t[]){INTSET
},
4461 .name
= "xsr.itlbcfg",
4462 .translate
= translate_xsr
,
4463 .par
= (const uint32_t[]){ITLBCFG
},
4466 .translate
= translate_xsr
,
4467 .par
= (const uint32_t[]){LBEG
},
4469 .name
= "xsr.lcount",
4470 .translate
= translate_xsr
,
4471 .par
= (const uint32_t[]){LCOUNT
},
4474 .translate
= translate_xsr
,
4475 .par
= (const uint32_t[]){LEND
},
4477 .name
= "xsr.litbase",
4478 .translate
= translate_xsr
,
4479 .par
= (const uint32_t[]){LITBASE
},
4482 .translate
= translate_xsr
,
4483 .par
= (const uint32_t[]){MR
},
4486 .translate
= translate_xsr
,
4487 .par
= (const uint32_t[]){MR
+ 1},
4490 .translate
= translate_xsr
,
4491 .par
= (const uint32_t[]){MR
+ 2},
4494 .translate
= translate_xsr
,
4495 .par
= (const uint32_t[]){MR
+ 3},
4497 .name
= "xsr.memctl",
4498 .translate
= translate_xsr
,
4499 .par
= (const uint32_t[]){MEMCTL
},
4501 .name
= "xsr.misc0",
4502 .translate
= translate_xsr
,
4503 .par
= (const uint32_t[]){MISC
},
4505 .name
= "xsr.misc1",
4506 .translate
= translate_xsr
,
4507 .par
= (const uint32_t[]){MISC
+ 1},
4509 .name
= "xsr.misc2",
4510 .translate
= translate_xsr
,
4511 .par
= (const uint32_t[]){MISC
+ 2},
4513 .name
= "xsr.misc3",
4514 .translate
= translate_xsr
,
4515 .par
= (const uint32_t[]){MISC
+ 3},
4518 .translate
= translate_xsr
,
4519 .par
= (const uint32_t[]){PRID
},
4522 .translate
= translate_xsr
,
4523 .par
= (const uint32_t[]){PS
},
4525 .name
= "xsr.ptevaddr",
4526 .translate
= translate_xsr
,
4527 .par
= (const uint32_t[]){PTEVADDR
},
4529 .name
= "xsr.rasid",
4530 .translate
= translate_xsr
,
4531 .par
= (const uint32_t[]){RASID
},
4534 .translate
= translate_xsr
,
4535 .par
= (const uint32_t[]){SAR
},
4537 .name
= "xsr.scompare1",
4538 .translate
= translate_xsr
,
4539 .par
= (const uint32_t[]){SCOMPARE1
},
4541 .name
= "xsr.vecbase",
4542 .translate
= translate_xsr
,
4543 .par
= (const uint32_t[]){VECBASE
},
4545 .name
= "xsr.windowbase",
4546 .translate
= translate_xsr
,
4547 .par
= (const uint32_t[]){WINDOW_BASE
},
4549 .name
= "xsr.windowstart",
4550 .translate
= translate_xsr
,
4551 .par
= (const uint32_t[]){WINDOW_START
},
4555 const XtensaOpcodeTranslators xtensa_core_opcodes
= {
4556 .num_opcodes
= ARRAY_SIZE(core_ops
),
4561 static void translate_abs_s(DisasContext
*dc
, const uint32_t arg
[],
4562 const uint32_t par
[])
4564 if (gen_check_cpenable(dc
, 0)) {
4565 gen_helper_abs_s(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4569 static void translate_add_s(DisasContext
*dc
, const uint32_t arg
[],
4570 const uint32_t par
[])
4572 if (gen_check_cpenable(dc
, 0)) {
4573 gen_helper_add_s(cpu_FR
[arg
[0]], cpu_env
,
4574 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4588 static void translate_compare_s(DisasContext
*dc
, const uint32_t arg
[],
4589 const uint32_t par
[])
4591 static void (* const helper
[])(TCGv_env env
, TCGv_i32 bit
,
4592 TCGv_i32 s
, TCGv_i32 t
) = {
4593 [COMPARE_UN
] = gen_helper_un_s
,
4594 [COMPARE_OEQ
] = gen_helper_oeq_s
,
4595 [COMPARE_UEQ
] = gen_helper_ueq_s
,
4596 [COMPARE_OLT
] = gen_helper_olt_s
,
4597 [COMPARE_ULT
] = gen_helper_ult_s
,
4598 [COMPARE_OLE
] = gen_helper_ole_s
,
4599 [COMPARE_ULE
] = gen_helper_ule_s
,
4602 if (gen_check_cpenable(dc
, 0)) {
4603 TCGv_i32 bit
= tcg_const_i32(1 << arg
[0]);
4605 helper
[par
[0]](cpu_env
, bit
, cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4610 static void translate_float_s(DisasContext
*dc
, const uint32_t arg
[],
4611 const uint32_t par
[])
4613 if (gen_window_check1(dc
, arg
[1]) && gen_check_cpenable(dc
, 0)) {
4614 TCGv_i32 scale
= tcg_const_i32(-arg
[2]);
4617 gen_helper_uitof(cpu_FR
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], scale
);
4619 gen_helper_itof(cpu_FR
[arg
[0]], cpu_env
, cpu_R
[arg
[1]], scale
);
4621 tcg_temp_free(scale
);
4625 static void translate_ftoi_s(DisasContext
*dc
, const uint32_t arg
[],
4626 const uint32_t par
[])
4628 if (gen_window_check1(dc
, arg
[0]) && gen_check_cpenable(dc
, 0)) {
4629 TCGv_i32 rounding_mode
= tcg_const_i32(par
[0]);
4630 TCGv_i32 scale
= tcg_const_i32(arg
[2]);
4633 gen_helper_ftoui(cpu_R
[arg
[0]], cpu_FR
[arg
[1]],
4634 rounding_mode
, scale
);
4636 gen_helper_ftoi(cpu_R
[arg
[0]], cpu_FR
[arg
[1]],
4637 rounding_mode
, scale
);
4639 tcg_temp_free(rounding_mode
);
4640 tcg_temp_free(scale
);
4644 static void translate_ldsti(DisasContext
*dc
, const uint32_t arg
[],
4645 const uint32_t par
[])
4647 if (gen_window_check1(dc
, arg
[1]) && gen_check_cpenable(dc
, 0)) {
4648 TCGv_i32 addr
= tcg_temp_new_i32();
4650 tcg_gen_addi_i32(addr
, cpu_R
[arg
[1]], arg
[2]);
4651 gen_load_store_alignment(dc
, 2, addr
, false);
4653 tcg_gen_qemu_st32(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4655 tcg_gen_qemu_ld32u(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4658 tcg_gen_mov_i32(cpu_R
[arg
[1]], addr
);
4660 tcg_temp_free(addr
);
4664 static void translate_ldstx(DisasContext
*dc
, const uint32_t arg
[],
4665 const uint32_t par
[])
4667 if (gen_window_check2(dc
, arg
[1], arg
[2]) && gen_check_cpenable(dc
, 0)) {
4668 TCGv_i32 addr
= tcg_temp_new_i32();
4670 tcg_gen_add_i32(addr
, cpu_R
[arg
[1]], cpu_R
[arg
[2]]);
4671 gen_load_store_alignment(dc
, 2, addr
, false);
4673 tcg_gen_qemu_st32(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4675 tcg_gen_qemu_ld32u(cpu_FR
[arg
[0]], addr
, dc
->cring
);
4678 tcg_gen_mov_i32(cpu_R
[arg
[1]], addr
);
4680 tcg_temp_free(addr
);
4684 static void translate_madd_s(DisasContext
*dc
, const uint32_t arg
[],
4685 const uint32_t par
[])
4687 if (gen_check_cpenable(dc
, 0)) {
4688 gen_helper_madd_s(cpu_FR
[arg
[0]], cpu_env
,
4689 cpu_FR
[arg
[0]], cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4693 static void translate_mov_s(DisasContext
*dc
, const uint32_t arg
[],
4694 const uint32_t par
[])
4696 if (gen_check_cpenable(dc
, 0)) {
4697 tcg_gen_mov_i32(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4701 static void translate_movcond_s(DisasContext
*dc
, const uint32_t arg
[],
4702 const uint32_t par
[])
4704 if (gen_window_check1(dc
, arg
[2]) && gen_check_cpenable(dc
, 0)) {
4705 TCGv_i32 zero
= tcg_const_i32(0);
4707 tcg_gen_movcond_i32(par
[0], cpu_FR
[arg
[0]],
4708 cpu_R
[arg
[2]], zero
,
4709 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4710 tcg_temp_free(zero
);
4714 static void translate_movp_s(DisasContext
*dc
, const uint32_t arg
[],
4715 const uint32_t par
[])
4717 if (gen_check_cpenable(dc
, 0)) {
4718 TCGv_i32 zero
= tcg_const_i32(0);
4719 TCGv_i32 tmp
= tcg_temp_new_i32();
4721 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << arg
[2]);
4722 tcg_gen_movcond_i32(par
[0],
4723 cpu_FR
[arg
[0]], tmp
, zero
,
4724 cpu_FR
[arg
[1]], cpu_FR
[arg
[0]]);
4726 tcg_temp_free(zero
);
4730 static void translate_mul_s(DisasContext
*dc
, const uint32_t arg
[],
4731 const uint32_t par
[])
4733 if (gen_check_cpenable(dc
, 0)) {
4734 gen_helper_mul_s(cpu_FR
[arg
[0]], cpu_env
,
4735 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4739 static void translate_msub_s(DisasContext
*dc
, const uint32_t arg
[],
4740 const uint32_t par
[])
4742 if (gen_check_cpenable(dc
, 0)) {
4743 gen_helper_msub_s(cpu_FR
[arg
[0]], cpu_env
,
4744 cpu_FR
[arg
[0]], cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4748 static void translate_neg_s(DisasContext
*dc
, const uint32_t arg
[],
4749 const uint32_t par
[])
4751 if (gen_check_cpenable(dc
, 0)) {
4752 gen_helper_neg_s(cpu_FR
[arg
[0]], cpu_FR
[arg
[1]]);
4756 static void translate_rfr_s(DisasContext
*dc
, const uint32_t arg
[],
4757 const uint32_t par
[])
4759 if (gen_window_check1(dc
, arg
[0]) &&
4760 gen_check_cpenable(dc
, 0)) {
4761 tcg_gen_mov_i32(cpu_R
[arg
[0]], cpu_FR
[arg
[1]]);
4765 static void translate_sub_s(DisasContext
*dc
, const uint32_t arg
[],
4766 const uint32_t par
[])
4768 if (gen_check_cpenable(dc
, 0)) {
4769 gen_helper_sub_s(cpu_FR
[arg
[0]], cpu_env
,
4770 cpu_FR
[arg
[1]], cpu_FR
[arg
[2]]);
4774 static void translate_wfr_s(DisasContext
*dc
, const uint32_t arg
[],
4775 const uint32_t par
[])
4777 if (gen_window_check1(dc
, arg
[1]) &&
4778 gen_check_cpenable(dc
, 0)) {
4779 tcg_gen_mov_i32(cpu_FR
[arg
[0]], cpu_R
[arg
[1]]);
4783 static const XtensaOpcodeOps fpu2000_ops
[] = {
4786 .translate
= translate_abs_s
,
4789 .translate
= translate_add_s
,
4792 .translate
= translate_ftoi_s
,
4793 .par
= (const uint32_t[]){float_round_up
, false},
4796 .translate
= translate_float_s
,
4797 .par
= (const uint32_t[]){false},
4800 .translate
= translate_ftoi_s
,
4801 .par
= (const uint32_t[]){float_round_down
, false},
4804 .translate
= translate_ldsti
,
4805 .par
= (const uint32_t[]){false, false},
4808 .translate
= translate_ldsti
,
4809 .par
= (const uint32_t[]){false, true},
4812 .translate
= translate_ldstx
,
4813 .par
= (const uint32_t[]){false, false},
4816 .translate
= translate_ldstx
,
4817 .par
= (const uint32_t[]){false, true},
4820 .translate
= translate_madd_s
,
4823 .translate
= translate_mov_s
,
4826 .translate
= translate_movcond_s
,
4827 .par
= (const uint32_t[]){TCG_COND_EQ
},
4830 .translate
= translate_movp_s
,
4831 .par
= (const uint32_t[]){TCG_COND_EQ
},
4834 .translate
= translate_movcond_s
,
4835 .par
= (const uint32_t[]){TCG_COND_GE
},
4838 .translate
= translate_movcond_s
,
4839 .par
= (const uint32_t[]){TCG_COND_LT
},
4842 .translate
= translate_movcond_s
,
4843 .par
= (const uint32_t[]){TCG_COND_NE
},
4846 .translate
= translate_movp_s
,
4847 .par
= (const uint32_t[]){TCG_COND_NE
},
4850 .translate
= translate_msub_s
,
4853 .translate
= translate_mul_s
,
4856 .translate
= translate_neg_s
,
4859 .translate
= translate_compare_s
,
4860 .par
= (const uint32_t[]){COMPARE_OEQ
},
4863 .translate
= translate_compare_s
,
4864 .par
= (const uint32_t[]){COMPARE_OLE
},
4867 .translate
= translate_compare_s
,
4868 .par
= (const uint32_t[]){COMPARE_OLT
},
4871 .translate
= translate_rfr_s
,
4874 .translate
= translate_ftoi_s
,
4875 .par
= (const uint32_t[]){float_round_nearest_even
, false},
4878 .translate
= translate_ldsti
,
4879 .par
= (const uint32_t[]){true, false},
4882 .translate
= translate_ldsti
,
4883 .par
= (const uint32_t[]){true, true},
4886 .translate
= translate_ldstx
,
4887 .par
= (const uint32_t[]){true, false},
4890 .translate
= translate_ldstx
,
4891 .par
= (const uint32_t[]){true, true},
4894 .translate
= translate_sub_s
,
4897 .translate
= translate_ftoi_s
,
4898 .par
= (const uint32_t[]){float_round_to_zero
, false},
4901 .translate
= translate_compare_s
,
4902 .par
= (const uint32_t[]){COMPARE_UEQ
},
4905 .translate
= translate_float_s
,
4906 .par
= (const uint32_t[]){true},
4909 .translate
= translate_compare_s
,
4910 .par
= (const uint32_t[]){COMPARE_ULE
},
4913 .translate
= translate_compare_s
,
4914 .par
= (const uint32_t[]){COMPARE_ULT
},
4917 .translate
= translate_compare_s
,
4918 .par
= (const uint32_t[]){COMPARE_UN
},
4921 .translate
= translate_ftoi_s
,
4922 .par
= (const uint32_t[]){float_round_to_zero
, true},
4925 .translate
= translate_wfr_s
,
4929 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
= {
4930 .num_opcodes
= ARRAY_SIZE(fpu2000_ops
),
4931 .opcode
= fpu2000_ops
,