2 * Alpha emulation cpu definitions for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #if !defined (__CPU_ALPHA_H__)
21 #define __CPU_ALPHA_H__
25 #define TARGET_LONG_BITS 64
27 #define CPUState struct CPUAlphaState
33 #include "softfloat.h"
35 #define TARGET_HAS_ICE 1
37 #define ELF_MACHINE EM_ALPHA
39 #define ICACHE_LINE_SIZE 32
40 #define DCACHE_LINE_SIZE 32
42 #define TARGET_PAGE_BITS 13
44 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
45 #define TARGET_PHYS_ADDR_SPACE_BITS 44
46 #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
48 /* Alpha major type */
54 ALPHA_EV5
= 5, /* 21164 */
55 ALPHA_EV45
= 6, /* 21064A */
56 ALPHA_EV56
= 7, /* 21164A */
67 ALPHA_LCA_1
= 1, /* 21066 */
68 ALPHA_LCA_2
= 2, /* 20166 */
69 ALPHA_LCA_3
= 3, /* 21068 */
70 ALPHA_LCA_4
= 4, /* 21068 */
71 ALPHA_LCA_5
= 5, /* 21066A */
72 ALPHA_LCA_6
= 6, /* 21068A */
77 ALPHA_EV5_1
= 1, /* Rev BA, CA */
78 ALPHA_EV5_2
= 2, /* Rev DA, EA */
79 ALPHA_EV5_3
= 3, /* Pass 3 */
80 ALPHA_EV5_4
= 4, /* Pass 3.2 */
81 ALPHA_EV5_5
= 5, /* Pass 4 */
86 ALPHA_EV45_1
= 1, /* Pass 1 */
87 ALPHA_EV45_2
= 2, /* Pass 1.1 */
88 ALPHA_EV45_3
= 3, /* Pass 2 */
93 ALPHA_EV56_1
= 1, /* Pass 1 */
94 ALPHA_EV56_2
= 2, /* Pass 2 */
98 IMPLVER_2106x
= 0, /* EV4, EV45 & LCA45 */
99 IMPLVER_21164
= 1, /* EV5, EV56 & PCA45 */
100 IMPLVER_21264
= 2, /* EV6, EV67 & EV68x */
101 IMPLVER_21364
= 3, /* EV7 & EV79 */
105 AMASK_BWX
= 0x00000001,
106 AMASK_FIX
= 0x00000002,
107 AMASK_CIX
= 0x00000004,
108 AMASK_MVI
= 0x00000100,
109 AMASK_TRAP
= 0x00000200,
110 AMASK_PREFETCH
= 0x00001000,
114 VAX_ROUND_NORMAL
= 0,
119 IEEE_ROUND_NORMAL
= 0,
126 /* IEEE floating-point operations encoding */
138 FP_ROUND_CHOPPED
= 0x0,
139 FP_ROUND_MINUS
= 0x1,
140 FP_ROUND_NORMAL
= 0x2,
141 FP_ROUND_DYNAMIC
= 0x3,
145 #define FPCR_SUM (1ULL << 63)
146 #define FPCR_INED (1ULL << 62)
147 #define FPCR_UNFD (1ULL << 61)
148 #define FPCR_UNDZ (1ULL << 60)
149 #define FPCR_DYN_SHIFT 58
150 #define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT)
151 #define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT)
152 #define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT)
153 #define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT)
154 #define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT)
155 #define FPCR_IOV (1ULL << 57)
156 #define FPCR_INE (1ULL << 56)
157 #define FPCR_UNF (1ULL << 55)
158 #define FPCR_OVF (1ULL << 54)
159 #define FPCR_DZE (1ULL << 53)
160 #define FPCR_INV (1ULL << 52)
161 #define FPCR_OVFD (1ULL << 51)
162 #define FPCR_DZED (1ULL << 50)
163 #define FPCR_INVD (1ULL << 49)
164 #define FPCR_DNZ (1ULL << 48)
165 #define FPCR_DNOD (1ULL << 47)
166 #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
167 | FPCR_OVF | FPCR_DZE | FPCR_INV)
169 /* The silly software trap enables implemented by the kernel emulation.
170 These are more or less architecturally required, since the real hardware
171 has read-as-zero bits in the FPCR when the features aren't implemented.
172 For the purposes of QEMU, we pretend the FPCR can hold everything. */
173 #define SWCR_TRAP_ENABLE_INV (1ULL << 1)
174 #define SWCR_TRAP_ENABLE_DZE (1ULL << 2)
175 #define SWCR_TRAP_ENABLE_OVF (1ULL << 3)
176 #define SWCR_TRAP_ENABLE_UNF (1ULL << 4)
177 #define SWCR_TRAP_ENABLE_INE (1ULL << 5)
178 #define SWCR_TRAP_ENABLE_DNO (1ULL << 6)
179 #define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1))
181 #define SWCR_MAP_DMZ (1ULL << 12)
182 #define SWCR_MAP_UMZ (1ULL << 13)
183 #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
185 #define SWCR_STATUS_INV (1ULL << 17)
186 #define SWCR_STATUS_DZE (1ULL << 18)
187 #define SWCR_STATUS_OVF (1ULL << 19)
188 #define SWCR_STATUS_UNF (1ULL << 20)
189 #define SWCR_STATUS_INE (1ULL << 21)
190 #define SWCR_STATUS_DNO (1ULL << 22)
191 #define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17))
193 #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
195 /* Internal processor registers */
196 /* XXX: TOFIX: most of those registers are implementation dependant */
198 #if defined(CONFIG_USER_ONLY)
204 IPR_CC
= 0xC0, /* 21264 */
205 IPR_CC_CTL
= 0xC1, /* 21264 */
206 #define IPR_CC_CTL_ENA_SHIFT 32
207 #define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL
208 IPR_VA
= 0xC2, /* 21264 */
209 IPR_VA_CTL
= 0xC4, /* 21264 */
210 #define IPR_VA_CTL_VA_48_SHIFT 1
211 #define IPR_VA_CTL_VPTB_SHIFT 30
212 IPR_VA_FORM
= 0xC3, /* 21264 */
214 IPR_ITB_TAG
= 0x00, /* 21264 */
215 IPR_ITB_PTE
= 0x01, /* 21264 */
217 IPR_ITB_IA
= 0x03, /* 21264 */
218 IPR_ITB_IS
= 0x04, /* 21264 */
220 IPR_EXC_ADDR
= 0x06, /* 21264 */
221 IPR_IVA_FORM
= 0x07, /* 21264 */
222 IPR_CM
= 0x09, /* 21264 */
223 #define IPR_CM_SHIFT 3
224 #define IPR_CM_MASK (3ULL << IPR_CM_SHIFT) /* 21264 */
225 IPR_IER
= 0x0A, /* 21264 */
226 #define IPR_IER_MASK 0x0000007fffffe000ULL
227 IPR_IER_CM
= 0x0B, /* 21264: = CM | IER */
228 IPR_SIRR
= 0x0C, /* 21264 */
229 #define IPR_SIRR_SHIFT 14
230 #define IPR_SIRR_MASK 0x7fff
231 IPR_ISUM
= 0x0D, /* 21264 */
232 IPR_HW_INT_CLR
= 0x0E, /* 21264 */
236 #define IPR_I_CTL_CHIP_ID_SHIFT 24 /* 21264 */
237 #define IPR_I_CTL_BIST_FAIL (1 << 23) /* 21264 */
238 #define IPR_I_CTL_IC_EN_SHIFT 2 /* 21264 */
239 #define IPR_I_CTL_SDE1_SHIFT 7 /* 21264 */
240 #define IPR_I_CTL_HWE_SHIFT 12 /* 21264 */
241 #define IPR_I_CTL_VA_48_SHIFT 15 /* 21264 */
242 #define IPR_I_CTL_SPE_SHIFT 3 /* 21264 */
243 #define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */
244 IPR_I_STAT
= 0x16, /* 21264 */
245 IPR_IC_FLUSH
= 0x13, /* 21264 */
246 IPR_IC_FLUSH_ASM
= 0x12, /* 21264 */
250 IPR_PCTX_ASN
= 0x01, /* field */
251 #define IPR_PCTX_ASN_SHIFT 39
252 IPR_PCTX_ASTER
= 0x02, /* field */
253 #define IPR_PCTX_ASTER_SHIFT 5
254 IPR_PCTX_ASTRR
= 0x04, /* field */
255 #define IPR_PCTX_ASTRR_SHIFT 9
256 IPR_PCTX_PPCE
= 0x08, /* field */
257 #define IPR_PCTX_PPCE_SHIFT 1
258 IPR_PCTX_FPE
= 0x10, /* field */
259 #define IPR_PCTX_FPE_SHIFT 2
260 IPR_PCTX_ALL
= 0x5f, /* all fields */
261 IPR_PCTR_CTL
= 0x14, /* 21264 */
263 IPR_DTB_TAG0
= 0x20, /* 21264 */
264 IPR_DTB_TAG1
= 0xA0, /* 21264 */
265 IPR_DTB_PTE0
= 0x21, /* 21264 */
266 IPR_DTB_PTE1
= 0xA1, /* 21264 */
267 IPR_DTB_ALTMODE
= 0xA6,
268 IPR_DTB_ALTMODE0
= 0x26, /* 21264 */
269 #define IPR_DTB_ALTMODE_MASK 3
271 IPR_DTB_IA
= 0xA3, /* 21264 */
274 IPR_DTB_ASN0
= 0x25, /* 21264 */
275 IPR_DTB_ASN1
= 0xA5, /* 21264 */
276 #define IPR_DTB_ASN_SHIFT 56
277 IPR_MM_STAT
= 0x27, /* 21264 */
278 IPR_M_CTL
= 0x28, /* 21264 */
279 #define IPR_M_CTL_SPE_SHIFT 1
280 #define IPR_M_CTL_SPE_MASK 7
281 IPR_DC_CTL
= 0x29, /* 21264 */
282 IPR_DC_STAT
= 0x2A, /* 21264 */
320 /* MMU modes definitions */
322 /* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
323 The Unix PALcode only exposes the kernel and user modes; presumably
324 executive and supervisor are used by VMS.
326 PALcode itself uses physical mode for code and kernel mode for data;
327 there are PALmode instructions that can access data via physical mode
328 or via an os-installed "alternate mode", which is one of the 4 above.
330 QEMU does not currently properly distinguish between code/data when
331 looking up addresses. To avoid having to address this issue, our
332 emulated PALcode will cheat and use the KSEG mapping for its code+data
333 rather than physical addresses.
335 Moreover, we're only emulating Unix PALcode, and not attempting VMS.
337 All of which allows us to drop all but kernel and user modes.
338 Elide the unused MMU modes to save space. */
340 #define NB_MMU_MODES 2
342 #define MMU_MODE0_SUFFIX _kernel
343 #define MMU_MODE1_SUFFIX _user
344 #define MMU_KERNEL_IDX 0
345 #define MMU_USER_IDX 1
347 typedef struct CPUAlphaState CPUAlphaState
;
349 struct CPUAlphaState
{
353 uint64_t ipr
[IPR_LAST
];
357 uint64_t lock_st_addr
;
359 float_status fp_status
;
360 /* The following fields make up the FPCR, but in FP_STATUS format. */
361 uint8_t fpcr_exc_status
;
362 uint8_t fpcr_exc_mask
;
363 uint8_t fpcr_dyn_round
;
364 uint8_t fpcr_flush_to_zero
;
369 /* Used for HW_LD / HW_ST */
374 #if TARGET_LONG_BITS > HOST_LONG_BITS
375 /* temporary fixed-point registers
376 * used to emulate 64 bits target on 32 bits hosts
381 /* Those resources are used only in Qemu core */
393 #define cpu_init cpu_alpha_init
394 #define cpu_exec cpu_alpha_exec
395 #define cpu_gen_code cpu_alpha_gen_code
396 #define cpu_signal_handler cpu_alpha_signal_handler
398 static inline int cpu_mmu_index (CPUState
*env
)
400 return (env
->ps
>> 3) & 1;
406 FEATURE_ASN
= 0x00000001,
407 FEATURE_SPS
= 0x00000002,
408 FEATURE_VIRBND
= 0x00000004,
409 FEATURE_TBCHK
= 0x00000008,
416 EXCP_HW_INTERRUPT
= 0x00E0,
417 EXCP_DFAULT
= 0x01E0,
418 EXCP_DTB_MISS_PAL
= 0x09E0,
419 EXCP_ITB_MISS
= 0x03E0,
420 EXCP_ITB_ACV
= 0x07E0,
421 EXCP_DTB_MISS_NATIVE
= 0x08E0,
422 EXCP_UNALIGN
= 0x11E0,
423 EXCP_OPCDEC
= 0x13E0,
425 EXCP_CALL_PAL
= 0x2000,
426 EXCP_CALL_PALP
= 0x3000,
427 EXCP_CALL_PALE
= 0x4000,
428 /* Pseudo exception for console */
429 EXCP_CONSOLE_DISPATCH
= 0x4001,
430 EXCP_CONSOLE_FIXUP
= 0x4002,
435 /* Arithmetic exception */
436 #define EXC_M_IOV (1<<16) /* Integer Overflow */
437 #define EXC_M_INE (1<<15) /* Inexact result */
438 #define EXC_M_UNF (1<<14) /* Underflow */
439 #define EXC_M_FOV (1<<13) /* Overflow */
440 #define EXC_M_DZE (1<<12) /* Division by zero */
441 #define EXC_M_INV (1<<11) /* Invalid operation */
442 #define EXC_M_SWC (1<<10) /* Software completion */
481 CPUAlphaState
* cpu_alpha_init (const char *cpu_model
);
482 int cpu_alpha_exec(CPUAlphaState
*s
);
483 /* you can call this signal handler from your SIGBUS and SIGSEGV
484 signal handlers to inform the virtual CPU of exceptions. non zero
485 is returned if the signal was handled by the virtual CPU. */
486 int cpu_alpha_signal_handler(int host_signum
, void *pinfo
,
488 int cpu_alpha_handle_mmu_fault (CPUState
*env
, uint64_t address
, int rw
,
489 int mmu_idx
, int is_softmmu
);
490 #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
491 void do_interrupt (CPUState
*env
);
493 uint64_t cpu_alpha_load_fpcr (CPUState
*env
);
494 void cpu_alpha_store_fpcr (CPUState
*env
, uint64_t val
);
495 int cpu_alpha_mfpr (CPUState
*env
, int iprn
, uint64_t *valp
);
496 int cpu_alpha_mtpr (CPUState
*env
, int iprn
, uint64_t val
, uint64_t *oldvalp
);
498 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
499 target_ulong
*cs_base
, int *flags
)
506 #if defined(CONFIG_USER_ONLY)
507 static inline void cpu_clone_regs(CPUState
*env
, target_ulong newsp
)
510 env
->ir
[IR_SP
] = newsp
;
516 static inline void cpu_set_tls(CPUState
*env
, target_ulong newtls
)
518 env
->unique
= newtls
;
522 #endif /* !defined (__CPU_ALPHA_H__) */