2 * Alpha emulation cpu definitions for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #if !defined (__CPU_ALPHA_H__)
21 #define __CPU_ALPHA_H__
25 #define TARGET_LONG_BITS 64
27 #define CPUState struct CPUAlphaState
33 #include "softfloat.h"
35 #define TARGET_HAS_ICE 1
37 #define ELF_MACHINE EM_ALPHA
39 #define ICACHE_LINE_SIZE 32
40 #define DCACHE_LINE_SIZE 32
42 #define TARGET_PAGE_BITS 13
44 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
45 #define TARGET_PHYS_ADDR_SPACE_BITS 44
46 #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
48 /* Alpha major type */
54 ALPHA_EV5
= 5, /* 21164 */
55 ALPHA_EV45
= 6, /* 21064A */
56 ALPHA_EV56
= 7, /* 21164A */
67 ALPHA_LCA_1
= 1, /* 21066 */
68 ALPHA_LCA_2
= 2, /* 20166 */
69 ALPHA_LCA_3
= 3, /* 21068 */
70 ALPHA_LCA_4
= 4, /* 21068 */
71 ALPHA_LCA_5
= 5, /* 21066A */
72 ALPHA_LCA_6
= 6, /* 21068A */
77 ALPHA_EV5_1
= 1, /* Rev BA, CA */
78 ALPHA_EV5_2
= 2, /* Rev DA, EA */
79 ALPHA_EV5_3
= 3, /* Pass 3 */
80 ALPHA_EV5_4
= 4, /* Pass 3.2 */
81 ALPHA_EV5_5
= 5, /* Pass 4 */
86 ALPHA_EV45_1
= 1, /* Pass 1 */
87 ALPHA_EV45_2
= 2, /* Pass 1.1 */
88 ALPHA_EV45_3
= 3, /* Pass 2 */
93 ALPHA_EV56_1
= 1, /* Pass 1 */
94 ALPHA_EV56_2
= 2, /* Pass 2 */
98 IMPLVER_2106x
= 0, /* EV4, EV45 & LCA45 */
99 IMPLVER_21164
= 1, /* EV5, EV56 & PCA45 */
100 IMPLVER_21264
= 2, /* EV6, EV67 & EV68x */
101 IMPLVER_21364
= 3, /* EV7 & EV79 */
105 AMASK_BWX
= 0x00000001,
106 AMASK_FIX
= 0x00000002,
107 AMASK_CIX
= 0x00000004,
108 AMASK_MVI
= 0x00000100,
109 AMASK_TRAP
= 0x00000200,
110 AMASK_PREFETCH
= 0x00001000,
114 VAX_ROUND_NORMAL
= 0,
119 IEEE_ROUND_NORMAL
= 0,
126 /* IEEE floating-point operations encoding */
138 FP_ROUND_CHOPPED
= 0x0,
139 FP_ROUND_MINUS
= 0x1,
140 FP_ROUND_NORMAL
= 0x2,
141 FP_ROUND_DYNAMIC
= 0x3,
145 #define FPCR_SUM (1ULL << 63)
146 #define FPCR_INED (1ULL << 62)
147 #define FPCR_UNFD (1ULL << 61)
148 #define FPCR_UNDZ (1ULL << 60)
149 #define FPCR_DYN_SHIFT 58
150 #define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT)
151 #define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT)
152 #define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT)
153 #define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT)
154 #define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT)
155 #define FPCR_IOV (1ULL << 57)
156 #define FPCR_INE (1ULL << 56)
157 #define FPCR_UNF (1ULL << 55)
158 #define FPCR_OVF (1ULL << 54)
159 #define FPCR_DZE (1ULL << 53)
160 #define FPCR_INV (1ULL << 52)
161 #define FPCR_OVFD (1ULL << 51)
162 #define FPCR_DZED (1ULL << 50)
163 #define FPCR_INVD (1ULL << 49)
164 #define FPCR_DNZ (1ULL << 48)
165 #define FPCR_DNOD (1ULL << 47)
166 #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
167 | FPCR_OVF | FPCR_DZE | FPCR_INV)
169 /* The silly software trap enables implemented by the kernel emulation.
170 These are more or less architecturally required, since the real hardware
171 has read-as-zero bits in the FPCR when the features aren't implemented.
172 For the purposes of QEMU, we pretend the FPCR can hold everything. */
173 #define SWCR_TRAP_ENABLE_INV (1ULL << 1)
174 #define SWCR_TRAP_ENABLE_DZE (1ULL << 2)
175 #define SWCR_TRAP_ENABLE_OVF (1ULL << 3)
176 #define SWCR_TRAP_ENABLE_UNF (1ULL << 4)
177 #define SWCR_TRAP_ENABLE_INE (1ULL << 5)
178 #define SWCR_TRAP_ENABLE_DNO (1ULL << 6)
179 #define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1))
181 #define SWCR_MAP_DMZ (1ULL << 12)
182 #define SWCR_MAP_UMZ (1ULL << 13)
183 #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
185 #define SWCR_STATUS_INV (1ULL << 17)
186 #define SWCR_STATUS_DZE (1ULL << 18)
187 #define SWCR_STATUS_OVF (1ULL << 19)
188 #define SWCR_STATUS_UNF (1ULL << 20)
189 #define SWCR_STATUS_INE (1ULL << 21)
190 #define SWCR_STATUS_DNO (1ULL << 22)
191 #define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17))
193 #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
195 /* MMU modes definitions */
197 /* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
198 The Unix PALcode only exposes the kernel and user modes; presumably
199 executive and supervisor are used by VMS.
201 PALcode itself uses physical mode for code and kernel mode for data;
202 there are PALmode instructions that can access data via physical mode
203 or via an os-installed "alternate mode", which is one of the 4 above.
205 QEMU does not currently properly distinguish between code/data when
206 looking up addresses. To avoid having to address this issue, our
207 emulated PALcode will cheat and use the KSEG mapping for its code+data
208 rather than physical addresses.
210 Moreover, we're only emulating Unix PALcode, and not attempting VMS.
212 All of which allows us to drop all but kernel and user modes.
213 Elide the unused MMU modes to save space. */
215 #define NB_MMU_MODES 2
217 #define MMU_MODE0_SUFFIX _kernel
218 #define MMU_MODE1_SUFFIX _user
219 #define MMU_KERNEL_IDX 0
220 #define MMU_USER_IDX 1
222 typedef struct CPUAlphaState CPUAlphaState
;
224 struct CPUAlphaState
{
230 uint64_t lock_st_addr
;
232 float_status fp_status
;
233 /* The following fields make up the FPCR, but in FP_STATUS format. */
234 uint8_t fpcr_exc_status
;
235 uint8_t fpcr_exc_mask
;
236 uint8_t fpcr_dyn_round
;
237 uint8_t fpcr_flush_to_zero
;
242 /* The Internal Processor Registers. Some of these we assume always
243 exist for use in user-mode. */
248 /* These pass data from the exception logic in the translator and
249 helpers to the OS entry point. This is used for both system
250 emulation and user-mode. */
255 #if TARGET_LONG_BITS > HOST_LONG_BITS
256 /* temporary fixed-point registers
257 * used to emulate 64 bits target on 32 bits hosts
262 /* Those resources are used only in Qemu core */
272 #define cpu_init cpu_alpha_init
273 #define cpu_exec cpu_alpha_exec
274 #define cpu_gen_code cpu_alpha_gen_code
275 #define cpu_signal_handler cpu_alpha_signal_handler
280 FEATURE_ASN
= 0x00000001,
281 FEATURE_SPS
= 0x00000002,
282 FEATURE_VIRBND
= 0x00000004,
283 FEATURE_TBCHK
= 0x00000008,
298 /* For Usermode emulation. */
303 /* Hardware interrupt (entInt) constants. */
312 /* Memory management (entMM) constants. */
321 /* Arithmetic exception (entArith) constants. */
323 EXC_M_SWC
= 1, /* Software completion */
324 EXC_M_INV
= 2, /* Invalid operation */
325 EXC_M_DZE
= 4, /* Division by zero */
326 EXC_M_FOV
= 8, /* Overflow */
327 EXC_M_UNF
= 16, /* Underflow */
328 EXC_M_INE
= 32, /* Inexact result */
329 EXC_M_IOV
= 64 /* Integer Overflow */
332 /* Processor status constants. */
334 /* Low 3 bits are interrupt mask level. */
337 /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
338 The Unix PALcode only uses bit 4. */
342 static inline int cpu_mmu_index(CPUState
*env
)
345 return MMU_KERNEL_IDX
;
346 } else if (env
->ps
& PS_USER_MODE
) {
349 return MMU_KERNEL_IDX
;
390 CPUAlphaState
* cpu_alpha_init (const char *cpu_model
);
391 int cpu_alpha_exec(CPUAlphaState
*s
);
392 /* you can call this signal handler from your SIGBUS and SIGSEGV
393 signal handlers to inform the virtual CPU of exceptions. non zero
394 is returned if the signal was handled by the virtual CPU. */
395 int cpu_alpha_signal_handler(int host_signum
, void *pinfo
,
397 int cpu_alpha_handle_mmu_fault (CPUState
*env
, uint64_t address
, int rw
,
398 int mmu_idx
, int is_softmmu
);
399 #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
400 void do_interrupt (CPUState
*env
);
402 uint64_t cpu_alpha_load_fpcr (CPUState
*env
);
403 void cpu_alpha_store_fpcr (CPUState
*env
, uint64_t val
);
405 static inline void cpu_get_tb_cpu_state(CPUState
*env
, target_ulong
*pc
,
406 target_ulong
*cs_base
, int *flags
)
413 #if defined(CONFIG_USER_ONLY)
414 static inline void cpu_clone_regs(CPUState
*env
, target_ulong newsp
)
417 env
->ir
[IR_SP
] = newsp
;
423 static inline void cpu_set_tls(CPUState
*env
, target_ulong newtls
)
425 env
->unique
= newtls
;
429 #endif /* !defined (__CPU_ALPHA_H__) */