2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define DO_SINGLE_STEP
31 #define ALPHA_DEBUG_DISAS
34 typedef struct DisasContext DisasContext
;
38 #if !defined (CONFIG_USER_ONLY)
44 #ifdef USE_DIRECT_JUMP
47 #define TBPARAM(x) (long)(x)
51 #define DEF(s, n, copy_size) INDEX_op_ ## s,
57 static uint16_t *gen_opc_ptr
;
58 static uint32_t *gen_opparam_ptr
;
62 static always_inline
void gen_op_nop (void)
64 #if defined(GENERATE_NOP)
69 #define GEN32(func, NAME) \
70 static GenOpFunc *NAME ## _table [32] = { \
71 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
72 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
73 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
74 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
75 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
76 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
77 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
78 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
80 static always_inline void func (int n) \
82 NAME ## _table[n](); \
86 /* Special hacks for ir31 */
87 #define gen_op_load_T0_ir31 gen_op_reset_T0
88 #define gen_op_load_T1_ir31 gen_op_reset_T1
89 #define gen_op_load_T2_ir31 gen_op_reset_T2
90 #define gen_op_store_T0_ir31 gen_op_nop
91 #define gen_op_store_T1_ir31 gen_op_nop
92 #define gen_op_store_T2_ir31 gen_op_nop
93 #define gen_op_cmov_ir31 gen_op_nop
94 GEN32(gen_op_load_T0_ir
, gen_op_load_T0_ir
);
95 GEN32(gen_op_load_T1_ir
, gen_op_load_T1_ir
);
96 GEN32(gen_op_load_T2_ir
, gen_op_load_T2_ir
);
97 GEN32(gen_op_store_T0_ir
, gen_op_store_T0_ir
);
98 GEN32(gen_op_store_T1_ir
, gen_op_store_T1_ir
);
99 GEN32(gen_op_store_T2_ir
, gen_op_store_T2_ir
);
100 GEN32(gen_op_cmov_ir
, gen_op_cmov_ir
);
102 static always_inline
void gen_load_ir (DisasContext
*ctx
, int irn
, int Tn
)
106 gen_op_load_T0_ir(irn
);
109 gen_op_load_T1_ir(irn
);
112 gen_op_load_T2_ir(irn
);
117 static always_inline
void gen_store_ir (DisasContext
*ctx
, int irn
, int Tn
)
121 gen_op_store_T0_ir(irn
);
124 gen_op_store_T1_ir(irn
);
127 gen_op_store_T2_ir(irn
);
133 /* Special hacks for fir31 */
134 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
135 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
136 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
137 #define gen_op_store_FT0_fir31 gen_op_nop
138 #define gen_op_store_FT1_fir31 gen_op_nop
139 #define gen_op_store_FT2_fir31 gen_op_nop
140 #define gen_op_cmov_fir31 gen_op_nop
141 GEN32(gen_op_load_FT0_fir
, gen_op_load_FT0_fir
);
142 GEN32(gen_op_load_FT1_fir
, gen_op_load_FT1_fir
);
143 GEN32(gen_op_load_FT2_fir
, gen_op_load_FT2_fir
);
144 GEN32(gen_op_store_FT0_fir
, gen_op_store_FT0_fir
);
145 GEN32(gen_op_store_FT1_fir
, gen_op_store_FT1_fir
);
146 GEN32(gen_op_store_FT2_fir
, gen_op_store_FT2_fir
);
147 GEN32(gen_op_cmov_fir
, gen_op_cmov_fir
);
149 static always_inline
void gen_load_fir (DisasContext
*ctx
, int firn
, int Tn
)
153 gen_op_load_FT0_fir(firn
);
156 gen_op_load_FT1_fir(firn
);
159 gen_op_load_FT2_fir(firn
);
164 static always_inline
void gen_store_fir (DisasContext
*ctx
, int firn
, int Tn
)
168 gen_op_store_FT0_fir(firn
);
171 gen_op_store_FT1_fir(firn
);
174 gen_op_store_FT2_fir(firn
);
180 #if defined(CONFIG_USER_ONLY)
181 #define OP_LD_TABLE(width) \
182 static GenOpFunc *gen_op_ld##width[] = { \
183 &gen_op_ld##width##_raw, \
185 #define OP_ST_TABLE(width) \
186 static GenOpFunc *gen_op_st##width[] = { \
187 &gen_op_st##width##_raw, \
190 #define OP_LD_TABLE(width) \
191 static GenOpFunc *gen_op_ld##width[] = { \
192 &gen_op_ld##width##_kernel, \
193 &gen_op_ld##width##_executive, \
194 &gen_op_ld##width##_supervisor, \
195 &gen_op_ld##width##_user, \
197 #define OP_ST_TABLE(width) \
198 static GenOpFunc *gen_op_st##width[] = { \
199 &gen_op_st##width##_kernel, \
200 &gen_op_st##width##_executive, \
201 &gen_op_st##width##_supervisor, \
202 &gen_op_st##width##_user, \
206 #define GEN_LD(width) \
207 OP_LD_TABLE(width); \
208 static always_inline void gen_ld##width (DisasContext *ctx) \
210 (*gen_op_ld##width[ctx->mem_idx])(); \
213 #define GEN_ST(width) \
214 OP_ST_TABLE(width); \
215 static always_inline void gen_st##width (DisasContext *ctx) \
217 (*gen_op_st##width[ctx->mem_idx])(); \
235 #if 0 /* currently unused */
246 #if defined(__i386__) || defined(__x86_64__)
247 static always_inline
void gen_op_set_s16_T0 (int16_t imm
)
249 gen_op_set_s32_T0((int32_t)imm
);
252 static always_inline
void gen_op_set_s16_T1 (int16_t imm
)
254 gen_op_set_s32_T1((int32_t)imm
);
257 static always_inline
void gen_op_set_u16_T0 (uint16_t imm
)
259 gen_op_set_s32_T0((uint32_t)imm
);
262 static always_inline
void gen_op_set_u16_T1 (uint16_t imm
)
264 gen_op_set_s32_T1((uint32_t)imm
);
268 static always_inline
void gen_set_sT0 (DisasContext
*ctx
, int64_t imm
)
280 gen_op_set_s16_T0(imm16
);
283 gen_op_set_s32_T0(imm32
);
286 #if 0 // Qemu does not know how to do this...
287 gen_op_set_64_T0(imm
);
289 gen_op_set_64_T0(imm
>> 32, imm
);
294 static always_inline
void gen_set_sT1 (DisasContext
*ctx
, int64_t imm
)
306 gen_op_set_s16_T1(imm16
);
309 gen_op_set_s32_T1(imm32
);
312 #if 0 // Qemu does not know how to do this...
313 gen_op_set_64_T1(imm
);
315 gen_op_set_64_T1(imm
>> 32, imm
);
320 static always_inline
void gen_set_uT0 (DisasContext
*ctx
, uint64_t imm
)
327 gen_op_set_u16_T0(imm
);
329 gen_op_set_u32_T0(imm
);
332 #if 0 // Qemu does not know how to do this...
333 gen_op_set_64_T0(imm
);
335 gen_op_set_64_T0(imm
>> 32, imm
);
340 static always_inline
void gen_set_uT1 (DisasContext
*ctx
, uint64_t imm
)
347 gen_op_set_u16_T1(imm
);
349 gen_op_set_u32_T1(imm
);
352 #if 0 // Qemu does not know how to do this...
353 gen_op_set_64_T1(imm
);
355 gen_op_set_64_T1(imm
>> 32, imm
);
360 static always_inline
void gen_update_pc (DisasContext
*ctx
)
362 if (!(ctx
->pc
>> 32)) {
363 gen_op_update_pc32(ctx
->pc
);
365 #if 0 // Qemu does not know how to do this...
366 gen_op_update_pc(ctx
->pc
);
368 gen_op_update_pc(ctx
->pc
>> 32, ctx
->pc
);
373 static always_inline
void _gen_op_bcond (DisasContext
*ctx
)
375 #if 0 // Qemu does not know how to do this...
376 gen_op_bcond(ctx
->pc
);
378 gen_op_bcond(ctx
->pc
>> 32, ctx
->pc
);
382 static always_inline
void gen_excp (DisasContext
*ctx
,
383 int exception
, int error_code
)
386 gen_op_excp(exception
, error_code
);
389 static always_inline
void gen_invalid (DisasContext
*ctx
)
391 gen_excp(ctx
, EXCP_OPCDEC
, 0);
394 static always_inline
void gen_load_mem (DisasContext
*ctx
,
395 void (*gen_load_op
)(DisasContext
*ctx
),
396 int ra
, int rb
, int32_t disp16
,
399 if (ra
== 31 && disp16
== 0) {
403 gen_load_ir(ctx
, rb
, 0);
405 gen_set_sT1(ctx
, disp16
);
411 gen_store_ir(ctx
, ra
, 1);
415 static always_inline
void gen_store_mem (DisasContext
*ctx
,
416 void (*gen_store_op
)(DisasContext
*ctx
),
417 int ra
, int rb
, int32_t disp16
,
420 gen_load_ir(ctx
, rb
, 0);
422 gen_set_sT1(ctx
, disp16
);
427 gen_load_ir(ctx
, ra
, 1);
428 (*gen_store_op
)(ctx
);
431 static always_inline
void gen_load_fmem (DisasContext
*ctx
,
432 void (*gen_load_fop
)(DisasContext
*ctx
),
433 int ra
, int rb
, int32_t disp16
)
435 gen_load_ir(ctx
, rb
, 0);
437 gen_set_sT1(ctx
, disp16
);
440 (*gen_load_fop
)(ctx
);
441 gen_store_fir(ctx
, ra
, 1);
444 static always_inline
void gen_store_fmem (DisasContext
*ctx
,
445 void (*gen_store_fop
)(DisasContext
*ctx
),
446 int ra
, int rb
, int32_t disp16
)
448 gen_load_ir(ctx
, rb
, 0);
450 gen_set_sT1(ctx
, disp16
);
453 gen_load_fir(ctx
, ra
, 1);
454 (*gen_store_fop
)(ctx
);
457 static always_inline
void gen_bcond (DisasContext
*ctx
,
458 void (*gen_test_op
)(void),
459 int ra
, int32_t disp16
)
462 gen_set_uT0(ctx
, ctx
->pc
);
463 gen_set_sT1(ctx
, disp16
<< 2);
466 gen_set_uT1(ctx
, ctx
->pc
);
468 gen_load_ir(ctx
, ra
, 0);
473 static always_inline
void gen_fbcond (DisasContext
*ctx
,
474 void (*gen_test_op
)(void),
475 int ra
, int32_t disp16
)
478 gen_set_uT0(ctx
, ctx
->pc
);
479 gen_set_sT1(ctx
, disp16
<< 2);
482 gen_set_uT1(ctx
, ctx
->pc
);
484 gen_load_fir(ctx
, ra
, 0);
489 static always_inline
void gen_arith2 (DisasContext
*ctx
,
490 void (*gen_arith_op
)(void),
491 int rb
, int rc
, int islit
, int8_t lit
)
494 gen_set_sT0(ctx
, lit
);
496 gen_load_ir(ctx
, rb
, 0);
498 gen_store_ir(ctx
, rc
, 0);
501 static always_inline
void gen_arith3 (DisasContext
*ctx
,
502 void (*gen_arith_op
)(void),
503 int ra
, int rb
, int rc
,
504 int islit
, int8_t lit
)
506 gen_load_ir(ctx
, ra
, 0);
508 gen_set_sT1(ctx
, lit
);
510 gen_load_ir(ctx
, rb
, 1);
512 gen_store_ir(ctx
, rc
, 0);
515 static always_inline
void gen_cmov (DisasContext
*ctx
,
516 void (*gen_test_op
)(void),
517 int ra
, int rb
, int rc
,
518 int islit
, int8_t lit
)
520 gen_load_ir(ctx
, ra
, 1);
522 gen_set_sT0(ctx
, lit
);
524 gen_load_ir(ctx
, rb
, 0);
529 static always_inline
void gen_farith2 (DisasContext
*ctx
,
530 void (*gen_arith_fop
)(void),
533 gen_load_fir(ctx
, rb
, 0);
535 gen_store_fir(ctx
, rc
, 0);
538 static always_inline
void gen_farith3 (DisasContext
*ctx
,
539 void (*gen_arith_fop
)(void),
540 int ra
, int rb
, int rc
)
542 gen_load_fir(ctx
, ra
, 0);
543 gen_load_fir(ctx
, rb
, 1);
545 gen_store_fir(ctx
, rc
, 0);
548 static always_inline
void gen_fcmov (DisasContext
*ctx
,
549 void (*gen_test_fop
)(void),
550 int ra
, int rb
, int rc
)
552 gen_load_fir(ctx
, ra
, 0);
553 gen_load_fir(ctx
, rb
, 1);
558 static always_inline
void gen_fti (DisasContext
*ctx
,
559 void (*gen_move_fop
)(void),
562 gen_load_fir(ctx
, rc
, 0);
564 gen_store_ir(ctx
, ra
, 0);
567 static always_inline
void gen_itf (DisasContext
*ctx
,
568 void (*gen_move_fop
)(void),
571 gen_load_ir(ctx
, ra
, 0);
573 gen_store_fir(ctx
, rc
, 0);
576 static always_inline
void gen_s4addl (void)
582 static always_inline
void gen_s4subl (void)
588 static always_inline
void gen_s8addl (void)
594 static always_inline
void gen_s8subl (void)
600 static always_inline
void gen_s4addq (void)
606 static always_inline
void gen_s4subq (void)
612 static always_inline
void gen_s8addq (void)
618 static always_inline
void gen_s8subq (void)
624 static always_inline
void gen_amask (void)
630 static always_inline
int translate_one (DisasContext
*ctx
, uint32_t insn
)
633 int32_t disp21
, disp16
, disp12
;
635 uint8_t opc
, ra
, rb
, rc
, sbz
, fpfn
, fn7
, fn2
, islit
;
639 /* Decode all instruction fields */
641 ra
= (insn
>> 21) & 0x1F;
642 rb
= (insn
>> 16) & 0x1F;
644 sbz
= (insn
>> 13) & 0x07;
645 islit
= (insn
>> 12) & 1;
646 lit
= (insn
>> 13) & 0xFF;
647 palcode
= insn
& 0x03FFFFFF;
648 disp21
= ((int32_t)((insn
& 0x001FFFFF) << 11)) >> 11;
649 disp16
= (int16_t)(insn
& 0x0000FFFF);
650 disp12
= (int32_t)((insn
& 0x00000FFF) << 20) >> 20;
651 fn16
= insn
& 0x0000FFFF;
652 fn11
= (insn
>> 5) & 0x000007FF;
654 fn7
= (insn
>> 5) & 0x0000007F;
655 fn2
= (insn
>> 5) & 0x00000003;
657 #if defined ALPHA_DEBUG_DISAS
658 if (logfile
!= NULL
) {
659 fprintf(logfile
, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
660 opc
, ra
, rb
, rc
, disp16
);
666 if (palcode
>= 0x80 && palcode
< 0xC0) {
667 /* Unprivileged PAL call */
668 gen_excp(ctx
, EXCP_CALL_PAL
+ ((palcode
& 0x1F) << 6), 0);
669 #if !defined (CONFIG_USER_ONLY)
670 } else if (palcode
< 0x40) {
671 /* Privileged PAL code */
672 if (ctx
->mem_idx
& 1)
675 gen_excp(ctx
, EXCP_CALL_PALP
+ ((palcode
& 0x1F) << 6), 0);
678 /* Invalid PAL call */
706 gen_load_ir(ctx
, rb
, 0);
707 gen_set_sT1(ctx
, disp16
);
709 gen_store_ir(ctx
, ra
, 0);
713 gen_load_ir(ctx
, rb
, 0);
714 gen_set_sT1(ctx
, disp16
<< 16);
716 gen_store_ir(ctx
, ra
, 0);
720 if (!(ctx
->amask
& AMASK_BWX
))
722 gen_load_mem(ctx
, &gen_ldbu
, ra
, rb
, disp16
, 0);
726 gen_load_mem(ctx
, &gen_ldq_u
, ra
, rb
, disp16
, 1);
730 if (!(ctx
->amask
& AMASK_BWX
))
732 gen_load_mem(ctx
, &gen_ldwu
, ra
, rb
, disp16
, 0);
736 if (!(ctx
->amask
& AMASK_BWX
))
738 gen_store_mem(ctx
, &gen_stw
, ra
, rb
, disp16
, 0);
742 if (!(ctx
->amask
& AMASK_BWX
))
744 gen_store_mem(ctx
, &gen_stb
, ra
, rb
, disp16
, 0);
748 gen_store_mem(ctx
, &gen_stq_u
, ra
, rb
, disp16
, 1);
754 gen_arith3(ctx
, &gen_op_addl
, ra
, rb
, rc
, islit
, lit
);
758 gen_arith3(ctx
, &gen_s4addl
, ra
, rb
, rc
, islit
, lit
);
762 gen_arith3(ctx
, &gen_op_subl
, ra
, rb
, rc
, islit
, lit
);
766 gen_arith3(ctx
, &gen_s4subl
, ra
, rb
, rc
, islit
, lit
);
770 gen_arith3(ctx
, &gen_op_cmpbge
, ra
, rb
, rc
, islit
, lit
);
774 gen_arith3(ctx
, &gen_s8addl
, ra
, rb
, rc
, islit
, lit
);
778 gen_arith3(ctx
, &gen_s8subl
, ra
, rb
, rc
, islit
, lit
);
782 gen_arith3(ctx
, &gen_op_cmpult
, ra
, rb
, rc
, islit
, lit
);
786 gen_arith3(ctx
, &gen_op_addq
, ra
, rb
, rc
, islit
, lit
);
790 gen_arith3(ctx
, &gen_s4addq
, ra
, rb
, rc
, islit
, lit
);
794 gen_arith3(ctx
, &gen_op_subq
, ra
, rb
, rc
, islit
, lit
);
798 gen_arith3(ctx
, &gen_s4subq
, ra
, rb
, rc
, islit
, lit
);
802 gen_arith3(ctx
, &gen_op_cmpeq
, ra
, rb
, rc
, islit
, lit
);
806 gen_arith3(ctx
, &gen_s8addq
, ra
, rb
, rc
, islit
, lit
);
810 gen_arith3(ctx
, &gen_s8subq
, ra
, rb
, rc
, islit
, lit
);
814 gen_arith3(ctx
, &gen_op_cmpule
, ra
, rb
, rc
, islit
, lit
);
818 gen_arith3(ctx
, &gen_op_addlv
, ra
, rb
, rc
, islit
, lit
);
822 gen_arith3(ctx
, &gen_op_sublv
, ra
, rb
, rc
, islit
, lit
);
826 gen_arith3(ctx
, &gen_op_cmplt
, ra
, rb
, rc
, islit
, lit
);
830 gen_arith3(ctx
, &gen_op_addqv
, ra
, rb
, rc
, islit
, lit
);
834 gen_arith3(ctx
, &gen_op_subqv
, ra
, rb
, rc
, islit
, lit
);
838 gen_arith3(ctx
, &gen_op_cmple
, ra
, rb
, rc
, islit
, lit
);
848 gen_arith3(ctx
, &gen_op_and
, ra
, rb
, rc
, islit
, lit
);
852 gen_arith3(ctx
, &gen_op_bic
, ra
, rb
, rc
, islit
, lit
);
856 gen_cmov(ctx
, &gen_op_cmplbs
, ra
, rb
, rc
, islit
, lit
);
860 gen_cmov(ctx
, &gen_op_cmplbc
, ra
, rb
, rc
, islit
, lit
);
864 if (ra
== rb
|| ra
== 31 || rb
== 31) {
865 if (ra
== 31 && rc
== 31) {
870 gen_load_ir(ctx
, rb
, 0);
871 gen_store_ir(ctx
, rc
, 0);
874 gen_arith3(ctx
, &gen_op_bis
, ra
, rb
, rc
, islit
, lit
);
879 gen_cmov(ctx
, &gen_op_cmpeqz
, ra
, rb
, rc
, islit
, lit
);
883 gen_cmov(ctx
, &gen_op_cmpnez
, ra
, rb
, rc
, islit
, lit
);
887 gen_arith3(ctx
, &gen_op_ornot
, ra
, rb
, rc
, islit
, lit
);
891 gen_arith3(ctx
, &gen_op_xor
, ra
, rb
, rc
, islit
, lit
);
895 gen_cmov(ctx
, &gen_op_cmpltz
, ra
, rb
, rc
, islit
, lit
);
899 gen_cmov(ctx
, &gen_op_cmpgez
, ra
, rb
, rc
, islit
, lit
);
903 gen_arith3(ctx
, &gen_op_eqv
, ra
, rb
, rc
, islit
, lit
);
907 gen_arith2(ctx
, &gen_amask
, rb
, rc
, islit
, lit
);
911 gen_cmov(ctx
, &gen_op_cmplez
, ra
, rb
, rc
, islit
, lit
);
915 gen_cmov(ctx
, &gen_op_cmpgtz
, ra
, rb
, rc
, islit
, lit
);
919 gen_op_load_implver();
920 gen_store_ir(ctx
, rc
, 0);
930 gen_arith3(ctx
, &gen_op_mskbl
, ra
, rb
, rc
, islit
, lit
);
934 gen_arith3(ctx
, &gen_op_extbl
, ra
, rb
, rc
, islit
, lit
);
938 gen_arith3(ctx
, &gen_op_insbl
, ra
, rb
, rc
, islit
, lit
);
942 gen_arith3(ctx
, &gen_op_mskwl
, ra
, rb
, rc
, islit
, lit
);
946 gen_arith3(ctx
, &gen_op_extwl
, ra
, rb
, rc
, islit
, lit
);
950 gen_arith3(ctx
, &gen_op_inswl
, ra
, rb
, rc
, islit
, lit
);
954 gen_arith3(ctx
, &gen_op_mskll
, ra
, rb
, rc
, islit
, lit
);
958 gen_arith3(ctx
, &gen_op_extll
, ra
, rb
, rc
, islit
, lit
);
962 gen_arith3(ctx
, &gen_op_insll
, ra
, rb
, rc
, islit
, lit
);
966 gen_arith3(ctx
, &gen_op_zap
, ra
, rb
, rc
, islit
, lit
);
970 gen_arith3(ctx
, &gen_op_zapnot
, ra
, rb
, rc
, islit
, lit
);
974 gen_arith3(ctx
, &gen_op_mskql
, ra
, rb
, rc
, islit
, lit
);
978 gen_arith3(ctx
, &gen_op_srl
, ra
, rb
, rc
, islit
, lit
);
982 gen_arith3(ctx
, &gen_op_extql
, ra
, rb
, rc
, islit
, lit
);
986 gen_arith3(ctx
, &gen_op_sll
, ra
, rb
, rc
, islit
, lit
);
990 gen_arith3(ctx
, &gen_op_insql
, ra
, rb
, rc
, islit
, lit
);
994 gen_arith3(ctx
, &gen_op_sra
, ra
, rb
, rc
, islit
, lit
);
998 gen_arith3(ctx
, &gen_op_mskwh
, ra
, rb
, rc
, islit
, lit
);
1002 gen_arith3(ctx
, &gen_op_inswh
, ra
, rb
, rc
, islit
, lit
);
1006 gen_arith3(ctx
, &gen_op_extwh
, ra
, rb
, rc
, islit
, lit
);
1010 gen_arith3(ctx
, &gen_op_msklh
, ra
, rb
, rc
, islit
, lit
);
1014 gen_arith3(ctx
, &gen_op_inslh
, ra
, rb
, rc
, islit
, lit
);
1018 gen_arith3(ctx
, &gen_op_extlh
, ra
, rb
, rc
, islit
, lit
);
1022 gen_arith3(ctx
, &gen_op_mskqh
, ra
, rb
, rc
, islit
, lit
);
1026 gen_arith3(ctx
, &gen_op_insqh
, ra
, rb
, rc
, islit
, lit
);
1030 gen_arith3(ctx
, &gen_op_extqh
, ra
, rb
, rc
, islit
, lit
);
1040 gen_arith3(ctx
, &gen_op_mull
, ra
, rb
, rc
, islit
, lit
);
1044 gen_arith3(ctx
, &gen_op_mulq
, ra
, rb
, rc
, islit
, lit
);
1048 gen_arith3(ctx
, &gen_op_umulh
, ra
, rb
, rc
, islit
, lit
);
1052 gen_arith3(ctx
, &gen_op_mullv
, ra
, rb
, rc
, islit
, lit
);
1056 gen_arith3(ctx
, &gen_op_mulqv
, ra
, rb
, rc
, islit
, lit
);
1063 switch (fpfn
) { /* f11 & 0x3F */
1066 if (!(ctx
->amask
& AMASK_FIX
))
1068 gen_itf(ctx
, &gen_op_itofs
, ra
, rc
);
1072 if (!(ctx
->amask
& AMASK_FIX
))
1074 gen_farith2(ctx
, &gen_op_sqrtf
, rb
, rc
);
1078 if (!(ctx
->amask
& AMASK_FIX
))
1080 gen_farith2(ctx
, &gen_op_sqrts
, rb
, rc
);
1084 if (!(ctx
->amask
& AMASK_FIX
))
1087 gen_itf(ctx
, &gen_op_itoff
, ra
, rc
);
1094 if (!(ctx
->amask
& AMASK_FIX
))
1096 gen_itf(ctx
, &gen_op_itoft
, ra
, rc
);
1100 if (!(ctx
->amask
& AMASK_FIX
))
1102 gen_farith2(ctx
, &gen_op_sqrtg
, rb
, rc
);
1106 if (!(ctx
->amask
& AMASK_FIX
))
1108 gen_farith2(ctx
, &gen_op_sqrtt
, rb
, rc
);
1115 /* VAX floating point */
1116 /* XXX: rounding mode and trap are ignored (!) */
1117 switch (fpfn
) { /* f11 & 0x3F */
1120 gen_farith3(ctx
, &gen_op_addf
, ra
, rb
, rc
);
1124 gen_farith3(ctx
, &gen_op_subf
, ra
, rb
, rc
);
1128 gen_farith3(ctx
, &gen_op_mulf
, ra
, rb
, rc
);
1132 gen_farith3(ctx
, &gen_op_divf
, ra
, rb
, rc
);
1137 gen_farith2(ctx
, &gen_op_cvtdg
, rb
, rc
);
1144 gen_farith3(ctx
, &gen_op_addg
, ra
, rb
, rc
);
1148 gen_farith3(ctx
, &gen_op_subg
, ra
, rb
, rc
);
1152 gen_farith3(ctx
, &gen_op_mulg
, ra
, rb
, rc
);
1156 gen_farith3(ctx
, &gen_op_divg
, ra
, rb
, rc
);
1160 gen_farith3(ctx
, &gen_op_cmpgeq
, ra
, rb
, rc
);
1164 gen_farith3(ctx
, &gen_op_cmpglt
, ra
, rb
, rc
);
1168 gen_farith3(ctx
, &gen_op_cmpgle
, ra
, rb
, rc
);
1172 gen_farith2(ctx
, &gen_op_cvtgf
, rb
, rc
);
1177 gen_farith2(ctx
, &gen_op_cvtgd
, rb
, rc
);
1184 gen_farith2(ctx
, &gen_op_cvtgq
, rb
, rc
);
1188 gen_farith2(ctx
, &gen_op_cvtqf
, rb
, rc
);
1192 gen_farith2(ctx
, &gen_op_cvtqg
, rb
, rc
);
1199 /* IEEE floating-point */
1200 /* XXX: rounding mode and traps are ignored (!) */
1201 switch (fpfn
) { /* f11 & 0x3F */
1204 gen_farith3(ctx
, &gen_op_adds
, ra
, rb
, rc
);
1208 gen_farith3(ctx
, &gen_op_subs
, ra
, rb
, rc
);
1212 gen_farith3(ctx
, &gen_op_muls
, ra
, rb
, rc
);
1216 gen_farith3(ctx
, &gen_op_divs
, ra
, rb
, rc
);
1220 gen_farith3(ctx
, &gen_op_addt
, ra
, rb
, rc
);
1224 gen_farith3(ctx
, &gen_op_subt
, ra
, rb
, rc
);
1228 gen_farith3(ctx
, &gen_op_mult
, ra
, rb
, rc
);
1232 gen_farith3(ctx
, &gen_op_divt
, ra
, rb
, rc
);
1236 gen_farith3(ctx
, &gen_op_cmptun
, ra
, rb
, rc
);
1240 gen_farith3(ctx
, &gen_op_cmpteq
, ra
, rb
, rc
);
1244 gen_farith3(ctx
, &gen_op_cmptlt
, ra
, rb
, rc
);
1248 gen_farith3(ctx
, &gen_op_cmptle
, ra
, rb
, rc
);
1251 /* XXX: incorrect */
1252 if (fn11
== 0x2AC) {
1254 gen_farith2(ctx
, &gen_op_cvtst
, rb
, rc
);
1257 gen_farith2(ctx
, &gen_op_cvtts
, rb
, rc
);
1262 gen_farith2(ctx
, &gen_op_cvttq
, rb
, rc
);
1266 gen_farith2(ctx
, &gen_op_cvtqs
, rb
, rc
);
1270 gen_farith2(ctx
, &gen_op_cvtqt
, rb
, rc
);
1280 gen_farith2(ctx
, &gen_op_cvtlq
, rb
, rc
);
1285 if (ra
== 31 && rc
== 31) {
1290 gen_load_fir(ctx
, rb
, 0);
1291 gen_store_fir(ctx
, rc
, 0);
1294 gen_farith3(ctx
, &gen_op_cpys
, ra
, rb
, rc
);
1299 gen_farith2(ctx
, &gen_op_cpysn
, rb
, rc
);
1303 gen_farith2(ctx
, &gen_op_cpyse
, rb
, rc
);
1307 gen_load_fir(ctx
, ra
, 0);
1308 gen_op_store_fpcr();
1313 gen_store_fir(ctx
, ra
, 0);
1317 gen_fcmov(ctx
, &gen_op_cmpfeq
, ra
, rb
, rc
);
1321 gen_fcmov(ctx
, &gen_op_cmpfne
, ra
, rb
, rc
);
1325 gen_fcmov(ctx
, &gen_op_cmpflt
, ra
, rb
, rc
);
1329 gen_fcmov(ctx
, &gen_op_cmpfge
, ra
, rb
, rc
);
1333 gen_fcmov(ctx
, &gen_op_cmpfle
, ra
, rb
, rc
);
1337 gen_fcmov(ctx
, &gen_op_cmpfgt
, ra
, rb
, rc
);
1341 gen_farith2(ctx
, &gen_op_cvtql
, rb
, rc
);
1345 gen_farith2(ctx
, &gen_op_cvtqlv
, rb
, rc
);
1349 gen_farith2(ctx
, &gen_op_cvtqlsv
, rb
, rc
);
1356 switch ((uint16_t)disp16
) {
1359 /* No-op. Just exit from the current tb */
1364 /* No-op. Just exit from the current tb */
1386 gen_store_ir(ctx
, ra
, 0);
1391 gen_store_ir(ctx
, ra
, 0);
1396 /* XXX: TODO: evict tb cache at address rb */
1406 gen_store_ir(ctx
, ra
, 0);
1418 /* HW_MFPR (PALcode) */
1419 #if defined (CONFIG_USER_ONLY)
1424 gen_op_mfpr(insn
& 0xFF);
1425 gen_store_ir(ctx
, ra
, 0);
1429 gen_load_ir(ctx
, rb
, 0);
1431 gen_set_uT1(ctx
, ctx
->pc
);
1432 gen_store_ir(ctx
, ra
, 1);
1435 /* Those four jumps only differ by the branch prediction hint */
1453 /* HW_LD (PALcode) */
1454 #if defined (CONFIG_USER_ONLY)
1459 gen_load_ir(ctx
, rb
, 0);
1460 gen_set_sT1(ctx
, disp12
);
1462 switch ((insn
>> 12) & 0xF) {
1464 /* Longword physical access */
1468 /* Quadword physical access */
1472 /* Longword physical access with lock */
1476 /* Quadword physical access with lock */
1480 /* Longword virtual PTE fetch */
1481 gen_op_ldl_kernel();
1484 /* Quadword virtual PTE fetch */
1485 gen_op_ldq_kernel();
1494 /* Longword virtual access */
1495 gen_op_ld_phys_to_virt();
1499 /* Quadword virtual access */
1500 gen_op_ld_phys_to_virt();
1504 /* Longword virtual access with protection check */
1508 /* Quadword virtual access with protection check */
1512 /* Longword virtual access with altenate access mode */
1513 gen_op_set_alt_mode();
1514 gen_op_ld_phys_to_virt();
1516 gen_op_restore_mode();
1519 /* Quadword virtual access with altenate access mode */
1520 gen_op_set_alt_mode();
1521 gen_op_ld_phys_to_virt();
1523 gen_op_restore_mode();
1526 /* Longword virtual access with alternate access mode and
1529 gen_op_set_alt_mode();
1531 gen_op_restore_mode();
1534 /* Quadword virtual access with alternate access mode and
1537 gen_op_set_alt_mode();
1539 gen_op_restore_mode();
1542 gen_store_ir(ctx
, ra
, 1);
1549 if (!(ctx
->amask
& AMASK_BWX
))
1551 gen_arith2(ctx
, &gen_op_sextb
, rb
, rc
, islit
, lit
);
1555 if (!(ctx
->amask
& AMASK_BWX
))
1557 gen_arith2(ctx
, &gen_op_sextw
, rb
, rc
, islit
, lit
);
1561 if (!(ctx
->amask
& AMASK_CIX
))
1563 gen_arith2(ctx
, &gen_op_ctpop
, rb
, rc
, 0, 0);
1567 if (!(ctx
->amask
& AMASK_MVI
))
1574 if (!(ctx
->amask
& AMASK_CIX
))
1576 gen_arith2(ctx
, &gen_op_ctlz
, rb
, rc
, 0, 0);
1580 if (!(ctx
->amask
& AMASK_CIX
))
1582 gen_arith2(ctx
, &gen_op_cttz
, rb
, rc
, 0, 0);
1586 if (!(ctx
->amask
& AMASK_MVI
))
1593 if (!(ctx
->amask
& AMASK_MVI
))
1600 if (!(ctx
->amask
& AMASK_MVI
))
1607 if (!(ctx
->amask
& AMASK_MVI
))
1614 if (!(ctx
->amask
& AMASK_MVI
))
1621 if (!(ctx
->amask
& AMASK_MVI
))
1628 if (!(ctx
->amask
& AMASK_MVI
))
1635 if (!(ctx
->amask
& AMASK_MVI
))
1642 if (!(ctx
->amask
& AMASK_MVI
))
1649 if (!(ctx
->amask
& AMASK_MVI
))
1656 if (!(ctx
->amask
& AMASK_MVI
))
1663 if (!(ctx
->amask
& AMASK_MVI
))
1670 if (!(ctx
->amask
& AMASK_FIX
))
1672 gen_fti(ctx
, &gen_op_ftoit
, ra
, rb
);
1676 if (!(ctx
->amask
& AMASK_FIX
))
1678 gen_fti(ctx
, &gen_op_ftois
, ra
, rb
);
1685 /* HW_MTPR (PALcode) */
1686 #if defined (CONFIG_USER_ONLY)
1691 gen_load_ir(ctx
, ra
, 0);
1692 gen_op_mtpr(insn
& 0xFF);
1697 /* HW_REI (PALcode) */
1698 #if defined (CONFIG_USER_ONLY)
1707 gen_load_ir(ctx
, rb
, 0);
1708 gen_set_uT1(ctx
, (((int64_t)insn
<< 51) >> 51));
1716 /* HW_ST (PALcode) */
1717 #if defined (CONFIG_USER_ONLY)
1722 gen_load_ir(ctx
, rb
, 0);
1723 gen_set_sT1(ctx
, disp12
);
1725 gen_load_ir(ctx
, ra
, 1);
1726 switch ((insn
>> 12) & 0xF) {
1728 /* Longword physical access */
1732 /* Quadword physical access */
1736 /* Longword physical access with lock */
1740 /* Quadword physical access with lock */
1744 /* Longword virtual access */
1745 gen_op_st_phys_to_virt();
1749 /* Quadword virtual access */
1750 gen_op_st_phys_to_virt();
1772 /* Longword virtual access with alternate access mode */
1773 gen_op_set_alt_mode();
1774 gen_op_st_phys_to_virt();
1776 gen_op_restore_mode();
1779 /* Quadword virtual access with alternate access mode */
1780 gen_op_set_alt_mode();
1781 gen_op_st_phys_to_virt();
1783 gen_op_restore_mode();
1798 gen_load_fmem(ctx
, &gen_ldf
, ra
, rb
, disp16
);
1806 gen_load_fmem(ctx
, &gen_ldg
, ra
, rb
, disp16
);
1813 gen_load_fmem(ctx
, &gen_lds
, ra
, rb
, disp16
);
1817 gen_load_fmem(ctx
, &gen_ldt
, ra
, rb
, disp16
);
1822 gen_store_fmem(ctx
, &gen_stf
, ra
, rb
, disp16
);
1830 gen_store_fmem(ctx
, &gen_stg
, ra
, rb
, disp16
);
1837 gen_store_fmem(ctx
, &gen_sts
, ra
, rb
, disp16
);
1841 gen_store_fmem(ctx
, &gen_stt
, ra
, rb
, disp16
);
1845 gen_load_mem(ctx
, &gen_ldl
, ra
, rb
, disp16
, 0);
1849 gen_load_mem(ctx
, &gen_ldq
, ra
, rb
, disp16
, 0);
1853 gen_load_mem(ctx
, &gen_ldl_l
, ra
, rb
, disp16
, 0);
1857 gen_load_mem(ctx
, &gen_ldq_l
, ra
, rb
, disp16
, 0);
1861 gen_store_mem(ctx
, &gen_stl
, ra
, rb
, disp16
, 0);
1865 gen_store_mem(ctx
, &gen_stq
, ra
, rb
, disp16
, 0);
1869 gen_store_mem(ctx
, &gen_stl_c
, ra
, rb
, disp16
, 0);
1873 gen_store_mem(ctx
, &gen_stq_c
, ra
, rb
, disp16
, 0);
1877 gen_set_uT0(ctx
, ctx
->pc
);
1878 gen_store_ir(ctx
, ra
, 0);
1880 gen_set_sT1(ctx
, disp21
<< 2);
1888 gen_fbcond(ctx
, &gen_op_cmpfeq
, ra
, disp16
);
1893 gen_fbcond(ctx
, &gen_op_cmpflt
, ra
, disp16
);
1898 gen_fbcond(ctx
, &gen_op_cmpfle
, ra
, disp16
);
1903 gen_set_uT0(ctx
, ctx
->pc
);
1904 gen_store_ir(ctx
, ra
, 0);
1906 gen_set_sT1(ctx
, disp21
<< 2);
1914 gen_fbcond(ctx
, &gen_op_cmpfne
, ra
, disp16
);
1919 gen_fbcond(ctx
, &gen_op_cmpfge
, ra
, disp16
);
1924 gen_fbcond(ctx
, &gen_op_cmpfgt
, ra
, disp16
);
1929 gen_bcond(ctx
, &gen_op_cmplbc
, ra
, disp16
);
1934 gen_bcond(ctx
, &gen_op_cmpeqz
, ra
, disp16
);
1939 gen_bcond(ctx
, &gen_op_cmpltz
, ra
, disp16
);
1944 gen_bcond(ctx
, &gen_op_cmplez
, ra
, disp16
);
1949 gen_bcond(ctx
, &gen_op_cmplbs
, ra
, disp16
);
1954 gen_bcond(ctx
, &gen_op_cmpnez
, ra
, disp16
);
1959 gen_bcond(ctx
, &gen_op_cmpgez
, ra
, disp16
);
1964 gen_bcond(ctx
, &gen_op_cmpgtz
, ra
, disp16
);
1976 static always_inline
int gen_intermediate_code_internal (CPUState
*env
,
1977 TranslationBlock
*tb
,
1980 #if defined ALPHA_DEBUG_DISAS
1981 static int insn_count
;
1983 DisasContext ctx
, *ctxp
= &ctx
;
1984 target_ulong pc_start
;
1986 uint16_t *gen_opc_end
;
1991 gen_opc_ptr
= gen_opc_buf
;
1992 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1993 gen_opparam_ptr
= gen_opparam_buf
;
1996 ctx
.amask
= env
->amask
;
1997 #if defined (CONFIG_USER_ONLY)
2000 ctx
.mem_idx
= ((env
->ps
>> 3) & 3);
2001 ctx
.pal_mode
= env
->ipr
[IPR_EXC_ADDR
] & 1;
2003 for (ret
= 0; ret
== 0;) {
2004 if (env
->nb_breakpoints
> 0) {
2005 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
2006 if (env
->breakpoints
[j
] == ctx
.pc
) {
2007 gen_excp(&ctx
, EXCP_DEBUG
, 0);
2013 j
= gen_opc_ptr
- gen_opc_buf
;
2017 gen_opc_instr_start
[lj
++] = 0;
2018 gen_opc_pc
[lj
] = ctx
.pc
;
2019 gen_opc_instr_start
[lj
] = 1;
2022 #if defined ALPHA_DEBUG_DISAS
2024 if (logfile
!= NULL
) {
2025 fprintf(logfile
, "pc " TARGET_FMT_lx
" mem_idx %d\n",
2026 ctx
.pc
, ctx
.mem_idx
);
2029 insn
= ldl_code(ctx
.pc
);
2030 #if defined ALPHA_DEBUG_DISAS
2032 if (logfile
!= NULL
) {
2033 fprintf(logfile
, "opcode %08x %d\n", insn
, insn_count
);
2037 ret
= translate_one(ctxp
, insn
);
2040 /* if we reach a page boundary or are single stepping, stop
2043 if (((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
2044 (env
->singlestep_enabled
)) {
2047 #if defined (DO_SINGLE_STEP)
2051 if (ret
!= 1 && ret
!= 3) {
2052 gen_update_pc(&ctx
);
2055 #if defined (DO_TB_FLUSH)
2058 /* Generate the return instruction */
2060 *gen_opc_ptr
= INDEX_op_end
;
2062 j
= gen_opc_ptr
- gen_opc_buf
;
2065 gen_opc_instr_start
[lj
++] = 0;
2067 tb
->size
= ctx
.pc
- pc_start
;
2069 #if defined ALPHA_DEBUG_DISAS
2070 if (loglevel
& CPU_LOG_TB_CPU
) {
2071 cpu_dump_state(env
, logfile
, fprintf
, 0);
2073 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2074 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2075 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 1);
2076 fprintf(logfile
, "\n");
2078 if (loglevel
& CPU_LOG_TB_OP
) {
2079 fprintf(logfile
, "OP:\n");
2080 dump_ops(gen_opc_buf
, gen_opparam_buf
);
2081 fprintf(logfile
, "\n");
2088 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2090 return gen_intermediate_code_internal(env
, tb
, 0);
2093 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2095 return gen_intermediate_code_internal(env
, tb
, 1);
2098 CPUAlphaState
* cpu_alpha_init (const char *cpu_model
)
2103 env
= qemu_mallocz(sizeof(CPUAlphaState
));
2108 /* XXX: should not be hardcoded */
2109 env
->implver
= IMPLVER_2106x
;
2111 #if defined (CONFIG_USER_ONLY)
2115 /* Initialize IPR */
2116 hwpcb
= env
->ipr
[IPR_PCBB
];
2117 env
->ipr
[IPR_ASN
] = 0;
2118 env
->ipr
[IPR_ASTEN
] = 0;
2119 env
->ipr
[IPR_ASTSR
] = 0;
2120 env
->ipr
[IPR_DATFX
] = 0;
2122 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2123 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2124 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2125 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2126 env
->ipr
[IPR_FEN
] = 0;
2127 env
->ipr
[IPR_IPL
] = 31;
2128 env
->ipr
[IPR_MCES
] = 0;
2129 env
->ipr
[IPR_PERFMON
] = 0; /* Implementation specific */
2130 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2131 env
->ipr
[IPR_SISR
] = 0;
2132 env
->ipr
[IPR_VIRBND
] = -1ULL;