target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #include "hw/qdev-properties.h"
  24 #if !defined(CONFIG_USER_ONLY)
  25 #include "hw/loader.h"
  26 #endif
  27 #include "hw/arm/arm.h"
  28 #include "sysemu/sysemu.h"
  29 #include "sysemu/kvm.h"
  30
  31 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  32 {
  33     ARMCPU *cpu = ARM_CPU(cs);
  34
  35     cpu->env.regs[15] = value;
  36 }
  37
  38 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  39 {
  40     /* Reset a single ARMCPRegInfo register */
  41     ARMCPRegInfo *ri = value;
  42     ARMCPU *cpu = opaque;
  43
  44     if (ri->type & ARM_CP_SPECIAL) {
  45         return;
  46     }
  47
  48     if (ri->resetfn) {
  49         ri->resetfn(&cpu->env, ri);
  50         return;
  51     }
  52
  53     /* A zero offset is never possible as it would be regs[0]
  54      * so we use it to indicate that reset is being handled elsewhere.
  55      * This is basically only used for fields in non-core coprocessors
  56      * (like the pxa2xx ones).
  57      */
  58     if (!ri->fieldoffset) {
  59         return;
  60     }
  61
  62     if (ri->type & ARM_CP_64BIT) {
  63         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  64     } else {
  65         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  66     }
  67 }
  68
  69 /* CPUClass::reset() */
  70 static void arm_cpu_reset(CPUState *s)
  71 {
  72     ARMCPU *cpu = ARM_CPU(s);
  73     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  74     CPUARMState *env = &cpu->env;
  75
  76     acc->parent_reset(s);
  77
  78     memset(env, 0, offsetof(CPUARMState, breakpoints));
  79     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  80     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  81     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  82     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  83
  84     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  85         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  86     }
  87
  88     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  89         /* 64 bit CPUs always start in 64 bit mode */
  90         env->aarch64 = 1;
  91     }
  92
  93 #if defined(CONFIG_USER_ONLY)
  94     env->uncached_cpsr = ARM_CPU_MODE_USR;
  95     /* For user mode we must enable access to coprocessors */
  96     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
  97     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  98         env->cp15.c15_cpar = 3;
  99     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 100         env->cp15.c15_cpar = 1;
 101     }
 102 #else
 103     /* SVC mode with interrupts disabled.  */
 104     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
 105     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 106        clear at reset.  Initial SP and PC are loaded from ROM.  */
 107     if (IS_M(env)) {
 108         uint32_t pc;
 109         uint8_t *rom;
 110         env->uncached_cpsr &= ~CPSR_I;
 111         rom = rom_ptr(0);
 112         if (rom) {
 113             /* We should really use ldl_phys here, in case the guest
 114                modified flash and reset itself.  However images
 115                loaded via -kernel have not been copied yet, so load the
 116                values directly from there.  */
 117             env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
 118             pc = ldl_p(rom + 4);
 119             env->thumb = pc & 1;
 120             env->regs[15] = pc & ~1;
 121         }
 122     }
 123     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 124 #endif
 125     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 126     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 127     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 128     set_float_detect_tininess(float_tininess_before_rounding,
 129                               &env->vfp.fp_status);
 130     set_float_detect_tininess(float_tininess_before_rounding,
 131                               &env->vfp.standard_fp_status);
 132     tlb_flush(env, 1);
 133     /* Reset is a state change for some CPUARMState fields which we
 134      * bake assumptions about into translated code, so we need to
 135      * tb_flush().
 136      */
 137     tb_flush(env);
 138 }
 139
 140 #ifndef CONFIG_USER_ONLY
 141 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 142 {
 143     ARMCPU *cpu = opaque;
 144     CPUState *cs = CPU(cpu);
 145
 146     switch (irq) {
 147     case ARM_CPU_IRQ:
 148         if (level) {
 149             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 150         } else {
 151             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 152         }
 153         break;
 154     case ARM_CPU_FIQ:
 155         if (level) {
 156             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 157         } else {
 158             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 159         }
 160         break;
 161     default:
 162         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 163     }
 164 }
 165
 166 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 167 {
 168 #ifdef CONFIG_KVM
 169     ARMCPU *cpu = opaque;
 170     CPUState *cs = CPU(cpu);
 171     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 172
 173     switch (irq) {
 174     case ARM_CPU_IRQ:
 175         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 176         break;
 177     case ARM_CPU_FIQ:
 178         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 179         break;
 180     default:
 181         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 182     }
 183     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 184     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 185 #endif
 186 }
 187 #endif
 188
 189 static inline void set_feature(CPUARMState *env, int feature)
 190 {
 191     env->features |= 1ULL << feature;
 192 }
 193
 194 static void arm_cpu_initfn(Object *obj)
 195 {
 196     CPUState *cs = CPU(obj);
 197     ARMCPU *cpu = ARM_CPU(obj);
 198     static bool inited;
 199
 200     cs->env_ptr = &cpu->env;
 201     cpu_exec_init(&cpu->env);
 202     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 203                                          g_free, g_free);
 204
 205 #ifndef CONFIG_USER_ONLY
 206     /* Our inbound IRQ and FIQ lines */
 207     if (kvm_enabled()) {
 208         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 209     } else {
 210         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 211     }
 212
 213     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 214                                                 arm_gt_ptimer_cb, cpu);
 215     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 216                                                 arm_gt_vtimer_cb, cpu);
 217     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 218                        ARRAY_SIZE(cpu->gt_timer_outputs));
 219 #endif
 220
 221     /* DTB consumers generally don't in fact care what the 'compatible'
 222      * string is, so always provide some string and trust that a hypothetical
 223      * picky DTB consumer will also provide a helpful error message.
 224      */
 225     cpu->dtb_compatible = "qemu,unknown";
 226     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 227
 228     if (tcg_enabled() && !inited) {
 229         inited = true;
 230         arm_translate_init();
 231     }
 232 }
 233
 234 static void arm_cpu_finalizefn(Object *obj)
 235 {
 236     ARMCPU *cpu = ARM_CPU(obj);
 237     g_hash_table_destroy(cpu->cp_regs);
 238 }
 239
 240 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 241 {
 242     CPUState *cs = CPU(dev);
 243     ARMCPU *cpu = ARM_CPU(dev);
 244     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 245     CPUARMState *env = &cpu->env;
 246
 247     /* Some features automatically imply others: */
 248     if (arm_feature(env, ARM_FEATURE_V8)) {
 249         set_feature(env, ARM_FEATURE_V7);
 250         set_feature(env, ARM_FEATURE_ARM_DIV);
 251         set_feature(env, ARM_FEATURE_LPAE);
 252         set_feature(env, ARM_FEATURE_V8_AES);
 253     }
 254     if (arm_feature(env, ARM_FEATURE_V7)) {
 255         set_feature(env, ARM_FEATURE_VAPA);
 256         set_feature(env, ARM_FEATURE_THUMB2);
 257         set_feature(env, ARM_FEATURE_MPIDR);
 258         if (!arm_feature(env, ARM_FEATURE_M)) {
 259             set_feature(env, ARM_FEATURE_V6K);
 260         } else {
 261             set_feature(env, ARM_FEATURE_V6);
 262         }
 263     }
 264     if (arm_feature(env, ARM_FEATURE_V6K)) {
 265         set_feature(env, ARM_FEATURE_V6);
 266         set_feature(env, ARM_FEATURE_MVFR);
 267     }
 268     if (arm_feature(env, ARM_FEATURE_V6)) {
 269         set_feature(env, ARM_FEATURE_V5);
 270         if (!arm_feature(env, ARM_FEATURE_M)) {
 271             set_feature(env, ARM_FEATURE_AUXCR);
 272         }
 273     }
 274     if (arm_feature(env, ARM_FEATURE_V5)) {
 275         set_feature(env, ARM_FEATURE_V4T);
 276     }
 277     if (arm_feature(env, ARM_FEATURE_M)) {
 278         set_feature(env, ARM_FEATURE_THUMB_DIV);
 279     }
 280     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 281         set_feature(env, ARM_FEATURE_THUMB_DIV);
 282     }
 283     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 284         set_feature(env, ARM_FEATURE_VFP3);
 285     }
 286     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 287         set_feature(env, ARM_FEATURE_VFP);
 288     }
 289     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 290         set_feature(env, ARM_FEATURE_V7MP);
 291         set_feature(env, ARM_FEATURE_PXN);
 292     }
 293
 294     register_cp_regs_for_features(cpu);
 295     arm_cpu_register_gdb_regs_for_features(cpu);
 296
 297     init_cpreg_list(cpu);
 298
 299     cpu_reset(cs);
 300     qemu_init_vcpu(cs);
 301
 302     acc->parent_realize(dev, errp);
 303 }
 304
 305 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 306 {
 307     ObjectClass *oc;
 308     char *typename;
 309
 310     if (!cpu_model) {
 311         return NULL;
 312     }
 313
 314     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 315     oc = object_class_by_name(typename);
 316     g_free(typename);
 317     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 318         object_class_is_abstract(oc)) {
 319         return NULL;
 320     }
 321     return oc;
 322 }
 323
 324 /* CPU models. These are not needed for the AArch64 linux-user build. */
 325 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 326
 327 static void arm926_initfn(Object *obj)
 328 {
 329     ARMCPU *cpu = ARM_CPU(obj);
 330
 331     cpu->dtb_compatible = "arm,arm926";
 332     set_feature(&cpu->env, ARM_FEATURE_V5);
 333     set_feature(&cpu->env, ARM_FEATURE_VFP);
 334     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 335     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 336     cpu->midr = 0x41069265;
 337     cpu->reset_fpsid = 0x41011090;
 338     cpu->ctr = 0x1dd20d2;
 339     cpu->reset_sctlr = 0x00090078;
 340 }
 341
 342 static void arm946_initfn(Object *obj)
 343 {
 344     ARMCPU *cpu = ARM_CPU(obj);
 345
 346     cpu->dtb_compatible = "arm,arm946";
 347     set_feature(&cpu->env, ARM_FEATURE_V5);
 348     set_feature(&cpu->env, ARM_FEATURE_MPU);
 349     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 350     cpu->midr = 0x41059461;
 351     cpu->ctr = 0x0f004006;
 352     cpu->reset_sctlr = 0x00000078;
 353 }
 354
 355 static void arm1026_initfn(Object *obj)
 356 {
 357     ARMCPU *cpu = ARM_CPU(obj);
 358
 359     cpu->dtb_compatible = "arm,arm1026";
 360     set_feature(&cpu->env, ARM_FEATURE_V5);
 361     set_feature(&cpu->env, ARM_FEATURE_VFP);
 362     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 363     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 364     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 365     cpu->midr = 0x4106a262;
 366     cpu->reset_fpsid = 0x410110a0;
 367     cpu->ctr = 0x1dd20d2;
 368     cpu->reset_sctlr = 0x00090078;
 369     cpu->reset_auxcr = 1;
 370     {
 371         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 372         ARMCPRegInfo ifar = {
 373             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 374             .access = PL1_RW,
 375             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 376             .resetvalue = 0
 377         };
 378         define_one_arm_cp_reg(cpu, &ifar);
 379     }
 380 }
 381
 382 static void arm1136_r2_initfn(Object *obj)
 383 {
 384     ARMCPU *cpu = ARM_CPU(obj);
 385     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 386      * older core than plain "arm1136". In particular this does not
 387      * have the v6K features.
 388      * These ID register values are correct for 1136 but may be wrong
 389      * for 1136_r2 (in particular r0p2 does not actually implement most
 390      * of the ID registers).
 391      */
 392
 393     cpu->dtb_compatible = "arm,arm1136";
 394     set_feature(&cpu->env, ARM_FEATURE_V6);
 395     set_feature(&cpu->env, ARM_FEATURE_VFP);
 396     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 397     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 398     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 399     cpu->midr = 0x4107b362;
 400     cpu->reset_fpsid = 0x410120b4;
 401     cpu->mvfr0 = 0x11111111;
 402     cpu->mvfr1 = 0x00000000;
 403     cpu->ctr = 0x1dd20d2;
 404     cpu->reset_sctlr = 0x00050078;
 405     cpu->id_pfr0 = 0x111;
 406     cpu->id_pfr1 = 0x1;
 407     cpu->id_dfr0 = 0x2;
 408     cpu->id_afr0 = 0x3;
 409     cpu->id_mmfr0 = 0x01130003;
 410     cpu->id_mmfr1 = 0x10030302;
 411     cpu->id_mmfr2 = 0x01222110;
 412     cpu->id_isar0 = 0x00140011;
 413     cpu->id_isar1 = 0x12002111;
 414     cpu->id_isar2 = 0x11231111;
 415     cpu->id_isar3 = 0x01102131;
 416     cpu->id_isar4 = 0x141;
 417     cpu->reset_auxcr = 7;
 418 }
 419
 420 static void arm1136_initfn(Object *obj)
 421 {
 422     ARMCPU *cpu = ARM_CPU(obj);
 423
 424     cpu->dtb_compatible = "arm,arm1136";
 425     set_feature(&cpu->env, ARM_FEATURE_V6K);
 426     set_feature(&cpu->env, ARM_FEATURE_V6);
 427     set_feature(&cpu->env, ARM_FEATURE_VFP);
 428     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 429     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 430     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 431     cpu->midr = 0x4117b363;
 432     cpu->reset_fpsid = 0x410120b4;
 433     cpu->mvfr0 = 0x11111111;
 434     cpu->mvfr1 = 0x00000000;
 435     cpu->ctr = 0x1dd20d2;
 436     cpu->reset_sctlr = 0x00050078;
 437     cpu->id_pfr0 = 0x111;
 438     cpu->id_pfr1 = 0x1;
 439     cpu->id_dfr0 = 0x2;
 440     cpu->id_afr0 = 0x3;
 441     cpu->id_mmfr0 = 0x01130003;
 442     cpu->id_mmfr1 = 0x10030302;
 443     cpu->id_mmfr2 = 0x01222110;
 444     cpu->id_isar0 = 0x00140011;
 445     cpu->id_isar1 = 0x12002111;
 446     cpu->id_isar2 = 0x11231111;
 447     cpu->id_isar3 = 0x01102131;
 448     cpu->id_isar4 = 0x141;
 449     cpu->reset_auxcr = 7;
 450 }
 451
 452 static void arm1176_initfn(Object *obj)
 453 {
 454     ARMCPU *cpu = ARM_CPU(obj);
 455
 456     cpu->dtb_compatible = "arm,arm1176";
 457     set_feature(&cpu->env, ARM_FEATURE_V6K);
 458     set_feature(&cpu->env, ARM_FEATURE_VFP);
 459     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 460     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 461     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 462     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 463     cpu->midr = 0x410fb767;
 464     cpu->reset_fpsid = 0x410120b5;
 465     cpu->mvfr0 = 0x11111111;
 466     cpu->mvfr1 = 0x00000000;
 467     cpu->ctr = 0x1dd20d2;
 468     cpu->reset_sctlr = 0x00050078;
 469     cpu->id_pfr0 = 0x111;
 470     cpu->id_pfr1 = 0x11;
 471     cpu->id_dfr0 = 0x33;
 472     cpu->id_afr0 = 0;
 473     cpu->id_mmfr0 = 0x01130003;
 474     cpu->id_mmfr1 = 0x10030302;
 475     cpu->id_mmfr2 = 0x01222100;
 476     cpu->id_isar0 = 0x0140011;
 477     cpu->id_isar1 = 0x12002111;
 478     cpu->id_isar2 = 0x11231121;
 479     cpu->id_isar3 = 0x01102131;
 480     cpu->id_isar4 = 0x01141;
 481     cpu->reset_auxcr = 7;
 482 }
 483
 484 static void arm11mpcore_initfn(Object *obj)
 485 {
 486     ARMCPU *cpu = ARM_CPU(obj);
 487
 488     cpu->dtb_compatible = "arm,arm11mpcore";
 489     set_feature(&cpu->env, ARM_FEATURE_V6K);
 490     set_feature(&cpu->env, ARM_FEATURE_VFP);
 491     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 492     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 493     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 494     cpu->midr = 0x410fb022;
 495     cpu->reset_fpsid = 0x410120b4;
 496     cpu->mvfr0 = 0x11111111;
 497     cpu->mvfr1 = 0x00000000;
 498     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 499     cpu->id_pfr0 = 0x111;
 500     cpu->id_pfr1 = 0x1;
 501     cpu->id_dfr0 = 0;
 502     cpu->id_afr0 = 0x2;
 503     cpu->id_mmfr0 = 0x01100103;
 504     cpu->id_mmfr1 = 0x10020302;
 505     cpu->id_mmfr2 = 0x01222000;
 506     cpu->id_isar0 = 0x00100011;
 507     cpu->id_isar1 = 0x12002111;
 508     cpu->id_isar2 = 0x11221011;
 509     cpu->id_isar3 = 0x01102131;
 510     cpu->id_isar4 = 0x141;
 511     cpu->reset_auxcr = 1;
 512 }
 513
 514 static void cortex_m3_initfn(Object *obj)
 515 {
 516     ARMCPU *cpu = ARM_CPU(obj);
 517     set_feature(&cpu->env, ARM_FEATURE_V7);
 518     set_feature(&cpu->env, ARM_FEATURE_M);
 519     cpu->midr = 0x410fc231;
 520 }
 521
 522 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 523 {
 524 #ifndef CONFIG_USER_ONLY
 525     CPUClass *cc = CPU_CLASS(oc);
 526
 527     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 528 #endif
 529 }
 530
 531 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 532     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 533       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 534     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 535       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 536     REGINFO_SENTINEL
 537 };
 538
 539 static void cortex_a8_initfn(Object *obj)
 540 {
 541     ARMCPU *cpu = ARM_CPU(obj);
 542
 543     cpu->dtb_compatible = "arm,cortex-a8";
 544     set_feature(&cpu->env, ARM_FEATURE_V7);
 545     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 546     set_feature(&cpu->env, ARM_FEATURE_NEON);
 547     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 548     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 549     cpu->midr = 0x410fc080;
 550     cpu->reset_fpsid = 0x410330c0;
 551     cpu->mvfr0 = 0x11110222;
 552     cpu->mvfr1 = 0x00011100;
 553     cpu->ctr = 0x82048004;
 554     cpu->reset_sctlr = 0x00c50078;
 555     cpu->id_pfr0 = 0x1031;
 556     cpu->id_pfr1 = 0x11;
 557     cpu->id_dfr0 = 0x400;
 558     cpu->id_afr0 = 0;
 559     cpu->id_mmfr0 = 0x31100003;
 560     cpu->id_mmfr1 = 0x20000000;
 561     cpu->id_mmfr2 = 0x01202000;
 562     cpu->id_mmfr3 = 0x11;
 563     cpu->id_isar0 = 0x00101111;
 564     cpu->id_isar1 = 0x12112111;
 565     cpu->id_isar2 = 0x21232031;
 566     cpu->id_isar3 = 0x11112131;
 567     cpu->id_isar4 = 0x00111142;
 568     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 569     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 570     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 571     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 572     cpu->reset_auxcr = 2;
 573     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 574 }
 575
 576 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 577     /* power_control should be set to maximum latency. Again,
 578      * default to 0 and set by private hook
 579      */
 580     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 581       .access = PL1_RW, .resetvalue = 0,
 582       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 583     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 584       .access = PL1_RW, .resetvalue = 0,
 585       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 586     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 587       .access = PL1_RW, .resetvalue = 0,
 588       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 589     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 590       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 591     /* TLB lockdown control */
 592     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 593       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 594     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 595       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 596     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 597       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 598     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 599       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 600     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 601       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 602     REGINFO_SENTINEL
 603 };
 604
 605 static void cortex_a9_initfn(Object *obj)
 606 {
 607     ARMCPU *cpu = ARM_CPU(obj);
 608
 609     cpu->dtb_compatible = "arm,cortex-a9";
 610     set_feature(&cpu->env, ARM_FEATURE_V7);
 611     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 612     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 613     set_feature(&cpu->env, ARM_FEATURE_NEON);
 614     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 615     /* Note that A9 supports the MP extensions even for
 616      * A9UP and single-core A9MP (which are both different
 617      * and valid configurations; we don't model A9UP).
 618      */
 619     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 620     cpu->midr = 0x410fc090;
 621     cpu->reset_fpsid = 0x41033090;
 622     cpu->mvfr0 = 0x11110222;
 623     cpu->mvfr1 = 0x01111111;
 624     cpu->ctr = 0x80038003;
 625     cpu->reset_sctlr = 0x00c50078;
 626     cpu->id_pfr0 = 0x1031;
 627     cpu->id_pfr1 = 0x11;
 628     cpu->id_dfr0 = 0x000;
 629     cpu->id_afr0 = 0;
 630     cpu->id_mmfr0 = 0x00100103;
 631     cpu->id_mmfr1 = 0x20000000;
 632     cpu->id_mmfr2 = 0x01230000;
 633     cpu->id_mmfr3 = 0x00002111;
 634     cpu->id_isar0 = 0x00101111;
 635     cpu->id_isar1 = 0x13112111;
 636     cpu->id_isar2 = 0x21232041;
 637     cpu->id_isar3 = 0x11112131;
 638     cpu->id_isar4 = 0x00111142;
 639     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 640     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 641     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 642     {
 643         ARMCPRegInfo cbar = {
 644             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
 645             .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
 646             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
 647         };
 648         define_one_arm_cp_reg(cpu, &cbar);
 649         define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 650     }
 651 }
 652
 653 #ifndef CONFIG_USER_ONLY
 654 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 655                            uint64_t *value)
 656 {
 657     /* Linux wants the number of processors from here.
 658      * Might as well set the interrupt-controller bit too.
 659      */
 660     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 661     return 0;
 662 }
 663 #endif
 664
 665 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 666 #ifndef CONFIG_USER_ONLY
 667     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 668       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 669       .writefn = arm_cp_write_ignore, },
 670 #endif
 671     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 672       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 673     REGINFO_SENTINEL
 674 };
 675
 676 static void cortex_a15_initfn(Object *obj)
 677 {
 678     ARMCPU *cpu = ARM_CPU(obj);
 679
 680     cpu->dtb_compatible = "arm,cortex-a15";
 681     set_feature(&cpu->env, ARM_FEATURE_V7);
 682     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 683     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 684     set_feature(&cpu->env, ARM_FEATURE_NEON);
 685     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 686     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 687     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 688     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 689     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 690     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 691     cpu->midr = 0x412fc0f1;
 692     cpu->reset_fpsid = 0x410430f0;
 693     cpu->mvfr0 = 0x10110222;
 694     cpu->mvfr1 = 0x11111111;
 695     cpu->ctr = 0x8444c004;
 696     cpu->reset_sctlr = 0x00c50078;
 697     cpu->id_pfr0 = 0x00001131;
 698     cpu->id_pfr1 = 0x00011011;
 699     cpu->id_dfr0 = 0x02010555;
 700     cpu->id_afr0 = 0x00000000;
 701     cpu->id_mmfr0 = 0x10201105;
 702     cpu->id_mmfr1 = 0x20000000;
 703     cpu->id_mmfr2 = 0x01240000;
 704     cpu->id_mmfr3 = 0x02102211;
 705     cpu->id_isar0 = 0x02101110;
 706     cpu->id_isar1 = 0x13112111;
 707     cpu->id_isar2 = 0x21232041;
 708     cpu->id_isar3 = 0x11112131;
 709     cpu->id_isar4 = 0x10011142;
 710     cpu->clidr = 0x0a200023;
 711     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 712     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 713     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 714     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 715 }
 716
 717 static void ti925t_initfn(Object *obj)
 718 {
 719     ARMCPU *cpu = ARM_CPU(obj);
 720     set_feature(&cpu->env, ARM_FEATURE_V4T);
 721     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 722     cpu->midr = ARM_CPUID_TI925T;
 723     cpu->ctr = 0x5109149;
 724     cpu->reset_sctlr = 0x00000070;
 725 }
 726
 727 static void sa1100_initfn(Object *obj)
 728 {
 729     ARMCPU *cpu = ARM_CPU(obj);
 730
 731     cpu->dtb_compatible = "intel,sa1100";
 732     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 733     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 734     cpu->midr = 0x4401A11B;
 735     cpu->reset_sctlr = 0x00000070;
 736 }
 737
 738 static void sa1110_initfn(Object *obj)
 739 {
 740     ARMCPU *cpu = ARM_CPU(obj);
 741     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 742     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 743     cpu->midr = 0x6901B119;
 744     cpu->reset_sctlr = 0x00000070;
 745 }
 746
 747 static void pxa250_initfn(Object *obj)
 748 {
 749     ARMCPU *cpu = ARM_CPU(obj);
 750
 751     cpu->dtb_compatible = "marvell,xscale";
 752     set_feature(&cpu->env, ARM_FEATURE_V5);
 753     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 754     cpu->midr = 0x69052100;
 755     cpu->ctr = 0xd172172;
 756     cpu->reset_sctlr = 0x00000078;
 757 }
 758
 759 static void pxa255_initfn(Object *obj)
 760 {
 761     ARMCPU *cpu = ARM_CPU(obj);
 762
 763     cpu->dtb_compatible = "marvell,xscale";
 764     set_feature(&cpu->env, ARM_FEATURE_V5);
 765     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 766     cpu->midr = 0x69052d00;
 767     cpu->ctr = 0xd172172;
 768     cpu->reset_sctlr = 0x00000078;
 769 }
 770
 771 static void pxa260_initfn(Object *obj)
 772 {
 773     ARMCPU *cpu = ARM_CPU(obj);
 774
 775     cpu->dtb_compatible = "marvell,xscale";
 776     set_feature(&cpu->env, ARM_FEATURE_V5);
 777     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 778     cpu->midr = 0x69052903;
 779     cpu->ctr = 0xd172172;
 780     cpu->reset_sctlr = 0x00000078;
 781 }
 782
 783 static void pxa261_initfn(Object *obj)
 784 {
 785     ARMCPU *cpu = ARM_CPU(obj);
 786
 787     cpu->dtb_compatible = "marvell,xscale";
 788     set_feature(&cpu->env, ARM_FEATURE_V5);
 789     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 790     cpu->midr = 0x69052d05;
 791     cpu->ctr = 0xd172172;
 792     cpu->reset_sctlr = 0x00000078;
 793 }
 794
 795 static void pxa262_initfn(Object *obj)
 796 {
 797     ARMCPU *cpu = ARM_CPU(obj);
 798
 799     cpu->dtb_compatible = "marvell,xscale";
 800     set_feature(&cpu->env, ARM_FEATURE_V5);
 801     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 802     cpu->midr = 0x69052d06;
 803     cpu->ctr = 0xd172172;
 804     cpu->reset_sctlr = 0x00000078;
 805 }
 806
 807 static void pxa270a0_initfn(Object *obj)
 808 {
 809     ARMCPU *cpu = ARM_CPU(obj);
 810
 811     cpu->dtb_compatible = "marvell,xscale";
 812     set_feature(&cpu->env, ARM_FEATURE_V5);
 813     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 814     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 815     cpu->midr = 0x69054110;
 816     cpu->ctr = 0xd172172;
 817     cpu->reset_sctlr = 0x00000078;
 818 }
 819
 820 static void pxa270a1_initfn(Object *obj)
 821 {
 822     ARMCPU *cpu = ARM_CPU(obj);
 823
 824     cpu->dtb_compatible = "marvell,xscale";
 825     set_feature(&cpu->env, ARM_FEATURE_V5);
 826     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 827     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 828     cpu->midr = 0x69054111;
 829     cpu->ctr = 0xd172172;
 830     cpu->reset_sctlr = 0x00000078;
 831 }
 832
 833 static void pxa270b0_initfn(Object *obj)
 834 {
 835     ARMCPU *cpu = ARM_CPU(obj);
 836
 837     cpu->dtb_compatible = "marvell,xscale";
 838     set_feature(&cpu->env, ARM_FEATURE_V5);
 839     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 840     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 841     cpu->midr = 0x69054112;
 842     cpu->ctr = 0xd172172;
 843     cpu->reset_sctlr = 0x00000078;
 844 }
 845
 846 static void pxa270b1_initfn(Object *obj)
 847 {
 848     ARMCPU *cpu = ARM_CPU(obj);
 849
 850     cpu->dtb_compatible = "marvell,xscale";
 851     set_feature(&cpu->env, ARM_FEATURE_V5);
 852     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 853     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 854     cpu->midr = 0x69054113;
 855     cpu->ctr = 0xd172172;
 856     cpu->reset_sctlr = 0x00000078;
 857 }
 858
 859 static void pxa270c0_initfn(Object *obj)
 860 {
 861     ARMCPU *cpu = ARM_CPU(obj);
 862
 863     cpu->dtb_compatible = "marvell,xscale";
 864     set_feature(&cpu->env, ARM_FEATURE_V5);
 865     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 866     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 867     cpu->midr = 0x69054114;
 868     cpu->ctr = 0xd172172;
 869     cpu->reset_sctlr = 0x00000078;
 870 }
 871
 872 static void pxa270c5_initfn(Object *obj)
 873 {
 874     ARMCPU *cpu = ARM_CPU(obj);
 875
 876     cpu->dtb_compatible = "marvell,xscale";
 877     set_feature(&cpu->env, ARM_FEATURE_V5);
 878     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 879     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 880     cpu->midr = 0x69054117;
 881     cpu->ctr = 0xd172172;
 882     cpu->reset_sctlr = 0x00000078;
 883 }
 884
 885 #ifdef CONFIG_USER_ONLY
 886 static void arm_any_initfn(Object *obj)
 887 {
 888     ARMCPU *cpu = ARM_CPU(obj);
 889     set_feature(&cpu->env, ARM_FEATURE_V8);
 890     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 891     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 892     set_feature(&cpu->env, ARM_FEATURE_NEON);
 893     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 894     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 895     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 896 #ifdef TARGET_AARCH64
 897     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 898 #endif
 899     cpu->midr = 0xffffffff;
 900 }
 901 #endif
 902
 903 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 904
 905 typedef struct ARMCPUInfo {
 906     const char *name;
 907     void (*initfn)(Object *obj);
 908     void (*class_init)(ObjectClass *oc, void *data);
 909 } ARMCPUInfo;
 910
 911 static const ARMCPUInfo arm_cpus[] = {
 912 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 913     { .name = "arm926",      .initfn = arm926_initfn },
 914     { .name = "arm946",      .initfn = arm946_initfn },
 915     { .name = "arm1026",     .initfn = arm1026_initfn },
 916     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 917      * older core than plain "arm1136". In particular this does not
 918      * have the v6K features.
 919      */
 920     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 921     { .name = "arm1136",     .initfn = arm1136_initfn },
 922     { .name = "arm1176",     .initfn = arm1176_initfn },
 923     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 924     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 925                              .class_init = arm_v7m_class_init },
 926     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 927     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 928     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 929     { .name = "ti925t",      .initfn = ti925t_initfn },
 930     { .name = "sa1100",      .initfn = sa1100_initfn },
 931     { .name = "sa1110",      .initfn = sa1110_initfn },
 932     { .name = "pxa250",      .initfn = pxa250_initfn },
 933     { .name = "pxa255",      .initfn = pxa255_initfn },
 934     { .name = "pxa260",      .initfn = pxa260_initfn },
 935     { .name = "pxa261",      .initfn = pxa261_initfn },
 936     { .name = "pxa262",      .initfn = pxa262_initfn },
 937     /* "pxa270" is an alias for "pxa270-a0" */
 938     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 939     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 940     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 941     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 942     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 943     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 944     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 945 #ifdef CONFIG_USER_ONLY
 946     { .name = "any",         .initfn = arm_any_initfn },
 947 #endif
 948 #endif
 949 };
 950
 951 static Property arm_cpu_properties[] = {
 952     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
 953     DEFINE_PROP_END_OF_LIST()
 954 };
 955
 956 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 957 {
 958     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 959     CPUClass *cc = CPU_CLASS(acc);
 960     DeviceClass *dc = DEVICE_CLASS(oc);
 961
 962     acc->parent_realize = dc->realize;
 963     dc->realize = arm_cpu_realizefn;
 964     dc->props = arm_cpu_properties;
 965
 966     acc->parent_reset = cc->reset;
 967     cc->reset = arm_cpu_reset;
 968
 969     cc->class_by_name = arm_cpu_class_by_name;
 970     cc->do_interrupt = arm_cpu_do_interrupt;
 971     cc->dump_state = arm_cpu_dump_state;
 972     cc->set_pc = arm_cpu_set_pc;
 973     cc->gdb_read_register = arm_cpu_gdb_read_register;
 974     cc->gdb_write_register = arm_cpu_gdb_write_register;
 975 #ifndef CONFIG_USER_ONLY
 976     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
 977     cc->vmsd = &vmstate_arm_cpu;
 978 #endif
 979     cc->gdb_num_core_regs = 26;
 980     cc->gdb_core_xml_file = "arm-core.xml";
 981 }
 982
 983 static void cpu_register(const ARMCPUInfo *info)
 984 {
 985     TypeInfo type_info = {
 986         .parent = TYPE_ARM_CPU,
 987         .instance_size = sizeof(ARMCPU),
 988         .instance_init = info->initfn,
 989         .class_size = sizeof(ARMCPUClass),
 990         .class_init = info->class_init,
 991     };
 992
 993     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 994     type_register(&type_info);
 995     g_free((void *)type_info.name);
 996 }
 997
 998 static const TypeInfo arm_cpu_type_info = {
 999     .name = TYPE_ARM_CPU,
1000     .parent = TYPE_CPU,
1001     .instance_size = sizeof(ARMCPU),
1002     .instance_init = arm_cpu_initfn,
1003     .instance_finalize = arm_cpu_finalizefn,
1004     .abstract = true,
1005     .class_size = sizeof(ARMCPUClass),
1006     .class_init = arm_cpu_class_init,
1007 };
1008
1009 static void arm_cpu_register_types(void)
1010 {
1011     int i;
1012
1013     type_register_static(&arm_cpu_type_info);
1014     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
1015         cpu_register(&arm_cpus[i]);
1016     }
1017 }
1018
1019 type_init(arm_cpu_register_types)