target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/loader.h"
  25 #endif
  26 #include "sysemu/sysemu.h"
  27
  28 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  29 {
  30     /* Reset a single ARMCPRegInfo register */
  31     ARMCPRegInfo *ri = value;
  32     ARMCPU *cpu = opaque;
  33
  34     if (ri->type & ARM_CP_SPECIAL) {
  35         return;
  36     }
  37
  38     if (ri->resetfn) {
  39         ri->resetfn(&cpu->env, ri);
  40         return;
  41     }
  42
  43     /* A zero offset is never possible as it would be regs[0]
  44      * so we use it to indicate that reset is being handled elsewhere.
  45      * This is basically only used for fields in non-core coprocessors
  46      * (like the pxa2xx ones).
  47      */
  48     if (!ri->fieldoffset) {
  49         return;
  50     }
  51
  52     if (ri->type & ARM_CP_64BIT) {
  53         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  54     } else {
  55         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  56     }
  57 }
  58
  59 /* CPUClass::reset() */
  60 static void arm_cpu_reset(CPUState *s)
  61 {
  62     ARMCPU *cpu = ARM_CPU(s);
  63     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  64     CPUARMState *env = &cpu->env;
  65
  66     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  67         qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
  68         log_cpu_state(env, 0);
  69     }
  70
  71     acc->parent_reset(s);
  72
  73     memset(env, 0, offsetof(CPUARMState, breakpoints));
  74     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  75     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  76     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  77     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  78
  79     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  80         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  81     }
  82
  83 #if defined(CONFIG_USER_ONLY)
  84     env->uncached_cpsr = ARM_CPU_MODE_USR;
  85     /* For user mode we must enable access to coprocessors */
  86     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
  87     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  88         env->cp15.c15_cpar = 3;
  89     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
  90         env->cp15.c15_cpar = 1;
  91     }
  92 #else
  93     /* SVC mode with interrupts disabled.  */
  94     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
  95     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
  96        clear at reset.  Initial SP and PC are loaded from ROM.  */
  97     if (IS_M(env)) {
  98         uint32_t pc;
  99         uint8_t *rom;
 100         env->uncached_cpsr &= ~CPSR_I;
 101         rom = rom_ptr(0);
 102         if (rom) {
 103             /* We should really use ldl_phys here, in case the guest
 104                modified flash and reset itself.  However images
 105                loaded via -kernel have not been copied yet, so load the
 106                values directly from there.  */
 107             env->regs[13] = ldl_p(rom);
 108             pc = ldl_p(rom + 4);
 109             env->thumb = pc & 1;
 110             env->regs[15] = pc & ~1;
 111         }
 112     }
 113     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 114 #endif
 115     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 116     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 117     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 118     set_float_detect_tininess(float_tininess_before_rounding,
 119                               &env->vfp.fp_status);
 120     set_float_detect_tininess(float_tininess_before_rounding,
 121                               &env->vfp.standard_fp_status);
 122     tlb_flush(env, 1);
 123     /* Reset is a state change for some CPUARMState fields which we
 124      * bake assumptions about into translated code, so we need to
 125      * tb_flush().
 126      */
 127     tb_flush(env);
 128 }
 129
 130 static inline void set_feature(CPUARMState *env, int feature)
 131 {
 132     env->features |= 1ULL << feature;
 133 }
 134
 135 static void arm_cpu_initfn(Object *obj)
 136 {
 137     ARMCPU *cpu = ARM_CPU(obj);
 138
 139     cpu_exec_init(&cpu->env);
 140     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 141                                          g_free, g_free);
 142 }
 143
 144 static void arm_cpu_finalizefn(Object *obj)
 145 {
 146     ARMCPU *cpu = ARM_CPU(obj);
 147     g_hash_table_destroy(cpu->cp_regs);
 148 }
 149
 150 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 151 {
 152     ARMCPU *cpu = ARM_CPU(dev);
 153     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 154     CPUARMState *env = &cpu->env;
 155
 156     /* Some features automatically imply others: */
 157     if (arm_feature(env, ARM_FEATURE_V7)) {
 158         set_feature(env, ARM_FEATURE_VAPA);
 159         set_feature(env, ARM_FEATURE_THUMB2);
 160         set_feature(env, ARM_FEATURE_MPIDR);
 161         if (!arm_feature(env, ARM_FEATURE_M)) {
 162             set_feature(env, ARM_FEATURE_V6K);
 163         } else {
 164             set_feature(env, ARM_FEATURE_V6);
 165         }
 166     }
 167     if (arm_feature(env, ARM_FEATURE_V6K)) {
 168         set_feature(env, ARM_FEATURE_V6);
 169         set_feature(env, ARM_FEATURE_MVFR);
 170     }
 171     if (arm_feature(env, ARM_FEATURE_V6)) {
 172         set_feature(env, ARM_FEATURE_V5);
 173         if (!arm_feature(env, ARM_FEATURE_M)) {
 174             set_feature(env, ARM_FEATURE_AUXCR);
 175         }
 176     }
 177     if (arm_feature(env, ARM_FEATURE_V5)) {
 178         set_feature(env, ARM_FEATURE_V4T);
 179     }
 180     if (arm_feature(env, ARM_FEATURE_M)) {
 181         set_feature(env, ARM_FEATURE_THUMB_DIV);
 182     }
 183     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 184         set_feature(env, ARM_FEATURE_THUMB_DIV);
 185     }
 186     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 187         set_feature(env, ARM_FEATURE_VFP3);
 188     }
 189     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 190         set_feature(env, ARM_FEATURE_VFP);
 191     }
 192     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 193         set_feature(env, ARM_FEATURE_PXN);
 194     }
 195
 196     register_cp_regs_for_features(cpu);
 197     arm_cpu_register_gdb_regs_for_features(cpu);
 198
 199     cpu_reset(CPU(cpu));
 200     qemu_init_vcpu(env);
 201
 202     acc->parent_realize(dev, errp);
 203 }
 204
 205 /* CPU models */
 206
 207 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 208 {
 209     ObjectClass *oc;
 210     char *typename;
 211
 212     if (!cpu_model) {
 213         return NULL;
 214     }
 215
 216     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 217     oc = object_class_by_name(typename);
 218     g_free(typename);
 219     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 220         object_class_is_abstract(oc)) {
 221         return NULL;
 222     }
 223     return oc;
 224 }
 225
 226 static void arm926_initfn(Object *obj)
 227 {
 228     ARMCPU *cpu = ARM_CPU(obj);
 229     set_feature(&cpu->env, ARM_FEATURE_V5);
 230     set_feature(&cpu->env, ARM_FEATURE_VFP);
 231     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 232     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 233     cpu->midr = 0x41069265;
 234     cpu->reset_fpsid = 0x41011090;
 235     cpu->ctr = 0x1dd20d2;
 236     cpu->reset_sctlr = 0x00090078;
 237 }
 238
 239 static void arm946_initfn(Object *obj)
 240 {
 241     ARMCPU *cpu = ARM_CPU(obj);
 242     set_feature(&cpu->env, ARM_FEATURE_V5);
 243     set_feature(&cpu->env, ARM_FEATURE_MPU);
 244     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 245     cpu->midr = 0x41059461;
 246     cpu->ctr = 0x0f004006;
 247     cpu->reset_sctlr = 0x00000078;
 248 }
 249
 250 static void arm1026_initfn(Object *obj)
 251 {
 252     ARMCPU *cpu = ARM_CPU(obj);
 253     set_feature(&cpu->env, ARM_FEATURE_V5);
 254     set_feature(&cpu->env, ARM_FEATURE_VFP);
 255     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 256     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 257     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 258     cpu->midr = 0x4106a262;
 259     cpu->reset_fpsid = 0x410110a0;
 260     cpu->ctr = 0x1dd20d2;
 261     cpu->reset_sctlr = 0x00090078;
 262     cpu->reset_auxcr = 1;
 263     {
 264         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 265         ARMCPRegInfo ifar = {
 266             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 267             .access = PL1_RW,
 268             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 269             .resetvalue = 0
 270         };
 271         define_one_arm_cp_reg(cpu, &ifar);
 272     }
 273 }
 274
 275 static void arm1136_r2_initfn(Object *obj)
 276 {
 277     ARMCPU *cpu = ARM_CPU(obj);
 278     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 279      * older core than plain "arm1136". In particular this does not
 280      * have the v6K features.
 281      * These ID register values are correct for 1136 but may be wrong
 282      * for 1136_r2 (in particular r0p2 does not actually implement most
 283      * of the ID registers).
 284      */
 285     set_feature(&cpu->env, ARM_FEATURE_V6);
 286     set_feature(&cpu->env, ARM_FEATURE_VFP);
 287     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 288     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 289     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 290     cpu->midr = 0x4107b362;
 291     cpu->reset_fpsid = 0x410120b4;
 292     cpu->mvfr0 = 0x11111111;
 293     cpu->mvfr1 = 0x00000000;
 294     cpu->ctr = 0x1dd20d2;
 295     cpu->reset_sctlr = 0x00050078;
 296     cpu->id_pfr0 = 0x111;
 297     cpu->id_pfr1 = 0x1;
 298     cpu->id_dfr0 = 0x2;
 299     cpu->id_afr0 = 0x3;
 300     cpu->id_mmfr0 = 0x01130003;
 301     cpu->id_mmfr1 = 0x10030302;
 302     cpu->id_mmfr2 = 0x01222110;
 303     cpu->id_isar0 = 0x00140011;
 304     cpu->id_isar1 = 0x12002111;
 305     cpu->id_isar2 = 0x11231111;
 306     cpu->id_isar3 = 0x01102131;
 307     cpu->id_isar4 = 0x141;
 308     cpu->reset_auxcr = 7;
 309 }
 310
 311 static void arm1136_initfn(Object *obj)
 312 {
 313     ARMCPU *cpu = ARM_CPU(obj);
 314     set_feature(&cpu->env, ARM_FEATURE_V6K);
 315     set_feature(&cpu->env, ARM_FEATURE_V6);
 316     set_feature(&cpu->env, ARM_FEATURE_VFP);
 317     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 318     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 319     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 320     cpu->midr = 0x4117b363;
 321     cpu->reset_fpsid = 0x410120b4;
 322     cpu->mvfr0 = 0x11111111;
 323     cpu->mvfr1 = 0x00000000;
 324     cpu->ctr = 0x1dd20d2;
 325     cpu->reset_sctlr = 0x00050078;
 326     cpu->id_pfr0 = 0x111;
 327     cpu->id_pfr1 = 0x1;
 328     cpu->id_dfr0 = 0x2;
 329     cpu->id_afr0 = 0x3;
 330     cpu->id_mmfr0 = 0x01130003;
 331     cpu->id_mmfr1 = 0x10030302;
 332     cpu->id_mmfr2 = 0x01222110;
 333     cpu->id_isar0 = 0x00140011;
 334     cpu->id_isar1 = 0x12002111;
 335     cpu->id_isar2 = 0x11231111;
 336     cpu->id_isar3 = 0x01102131;
 337     cpu->id_isar4 = 0x141;
 338     cpu->reset_auxcr = 7;
 339 }
 340
 341 static void arm1176_initfn(Object *obj)
 342 {
 343     ARMCPU *cpu = ARM_CPU(obj);
 344     set_feature(&cpu->env, ARM_FEATURE_V6K);
 345     set_feature(&cpu->env, ARM_FEATURE_VFP);
 346     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 347     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 348     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 349     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 350     cpu->midr = 0x410fb767;
 351     cpu->reset_fpsid = 0x410120b5;
 352     cpu->mvfr0 = 0x11111111;
 353     cpu->mvfr1 = 0x00000000;
 354     cpu->ctr = 0x1dd20d2;
 355     cpu->reset_sctlr = 0x00050078;
 356     cpu->id_pfr0 = 0x111;
 357     cpu->id_pfr1 = 0x11;
 358     cpu->id_dfr0 = 0x33;
 359     cpu->id_afr0 = 0;
 360     cpu->id_mmfr0 = 0x01130003;
 361     cpu->id_mmfr1 = 0x10030302;
 362     cpu->id_mmfr2 = 0x01222100;
 363     cpu->id_isar0 = 0x0140011;
 364     cpu->id_isar1 = 0x12002111;
 365     cpu->id_isar2 = 0x11231121;
 366     cpu->id_isar3 = 0x01102131;
 367     cpu->id_isar4 = 0x01141;
 368     cpu->reset_auxcr = 7;
 369 }
 370
 371 static void arm11mpcore_initfn(Object *obj)
 372 {
 373     ARMCPU *cpu = ARM_CPU(obj);
 374     set_feature(&cpu->env, ARM_FEATURE_V6K);
 375     set_feature(&cpu->env, ARM_FEATURE_VFP);
 376     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 377     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 378     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 379     cpu->midr = 0x410fb022;
 380     cpu->reset_fpsid = 0x410120b4;
 381     cpu->mvfr0 = 0x11111111;
 382     cpu->mvfr1 = 0x00000000;
 383     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 384     cpu->id_pfr0 = 0x111;
 385     cpu->id_pfr1 = 0x1;
 386     cpu->id_dfr0 = 0;
 387     cpu->id_afr0 = 0x2;
 388     cpu->id_mmfr0 = 0x01100103;
 389     cpu->id_mmfr1 = 0x10020302;
 390     cpu->id_mmfr2 = 0x01222000;
 391     cpu->id_isar0 = 0x00100011;
 392     cpu->id_isar1 = 0x12002111;
 393     cpu->id_isar2 = 0x11221011;
 394     cpu->id_isar3 = 0x01102131;
 395     cpu->id_isar4 = 0x141;
 396     cpu->reset_auxcr = 1;
 397 }
 398
 399 static void cortex_m3_initfn(Object *obj)
 400 {
 401     ARMCPU *cpu = ARM_CPU(obj);
 402     set_feature(&cpu->env, ARM_FEATURE_V7);
 403     set_feature(&cpu->env, ARM_FEATURE_M);
 404     cpu->midr = 0x410fc231;
 405 }
 406
 407 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 408     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 409       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 410     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 411       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 412     REGINFO_SENTINEL
 413 };
 414
 415 static void cortex_a8_initfn(Object *obj)
 416 {
 417     ARMCPU *cpu = ARM_CPU(obj);
 418     set_feature(&cpu->env, ARM_FEATURE_V7);
 419     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 420     set_feature(&cpu->env, ARM_FEATURE_NEON);
 421     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 422     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 423     cpu->midr = 0x410fc080;
 424     cpu->reset_fpsid = 0x410330c0;
 425     cpu->mvfr0 = 0x11110222;
 426     cpu->mvfr1 = 0x00011100;
 427     cpu->ctr = 0x82048004;
 428     cpu->reset_sctlr = 0x00c50078;
 429     cpu->id_pfr0 = 0x1031;
 430     cpu->id_pfr1 = 0x11;
 431     cpu->id_dfr0 = 0x400;
 432     cpu->id_afr0 = 0;
 433     cpu->id_mmfr0 = 0x31100003;
 434     cpu->id_mmfr1 = 0x20000000;
 435     cpu->id_mmfr2 = 0x01202000;
 436     cpu->id_mmfr3 = 0x11;
 437     cpu->id_isar0 = 0x00101111;
 438     cpu->id_isar1 = 0x12112111;
 439     cpu->id_isar2 = 0x21232031;
 440     cpu->id_isar3 = 0x11112131;
 441     cpu->id_isar4 = 0x00111142;
 442     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 443     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 444     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 445     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 446     cpu->reset_auxcr = 2;
 447     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 448 }
 449
 450 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 451     /* power_control should be set to maximum latency. Again,
 452      * default to 0 and set by private hook
 453      */
 454     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 455       .access = PL1_RW, .resetvalue = 0,
 456       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 457     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 458       .access = PL1_RW, .resetvalue = 0,
 459       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 460     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 461       .access = PL1_RW, .resetvalue = 0,
 462       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 463     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 464       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 465     /* TLB lockdown control */
 466     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 467       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 468     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 469       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 470     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 471       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 472     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 473       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 474     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 475       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 476     REGINFO_SENTINEL
 477 };
 478
 479 static void cortex_a9_initfn(Object *obj)
 480 {
 481     ARMCPU *cpu = ARM_CPU(obj);
 482     set_feature(&cpu->env, ARM_FEATURE_V7);
 483     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 484     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 485     set_feature(&cpu->env, ARM_FEATURE_NEON);
 486     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 487     /* Note that A9 supports the MP extensions even for
 488      * A9UP and single-core A9MP (which are both different
 489      * and valid configurations; we don't model A9UP).
 490      */
 491     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 492     cpu->midr = 0x410fc090;
 493     cpu->reset_fpsid = 0x41033090;
 494     cpu->mvfr0 = 0x11110222;
 495     cpu->mvfr1 = 0x01111111;
 496     cpu->ctr = 0x80038003;
 497     cpu->reset_sctlr = 0x00c50078;
 498     cpu->id_pfr0 = 0x1031;
 499     cpu->id_pfr1 = 0x11;
 500     cpu->id_dfr0 = 0x000;
 501     cpu->id_afr0 = 0;
 502     cpu->id_mmfr0 = 0x00100103;
 503     cpu->id_mmfr1 = 0x20000000;
 504     cpu->id_mmfr2 = 0x01230000;
 505     cpu->id_mmfr3 = 0x00002111;
 506     cpu->id_isar0 = 0x00101111;
 507     cpu->id_isar1 = 0x13112111;
 508     cpu->id_isar2 = 0x21232041;
 509     cpu->id_isar3 = 0x11112131;
 510     cpu->id_isar4 = 0x00111142;
 511     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 512     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 513     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 514     {
 515         ARMCPRegInfo cbar = {
 516             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
 517             .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
 518             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
 519         };
 520         define_one_arm_cp_reg(cpu, &cbar);
 521         define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 522     }
 523 }
 524
 525 #ifndef CONFIG_USER_ONLY
 526 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 527                            uint64_t *value)
 528 {
 529     /* Linux wants the number of processors from here.
 530      * Might as well set the interrupt-controller bit too.
 531      */
 532     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 533     return 0;
 534 }
 535 #endif
 536
 537 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 538 #ifndef CONFIG_USER_ONLY
 539     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 540       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 541       .writefn = arm_cp_write_ignore, },
 542 #endif
 543     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 544       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 545     REGINFO_SENTINEL
 546 };
 547
 548 static void cortex_a15_initfn(Object *obj)
 549 {
 550     ARMCPU *cpu = ARM_CPU(obj);
 551     set_feature(&cpu->env, ARM_FEATURE_V7);
 552     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 553     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 554     set_feature(&cpu->env, ARM_FEATURE_NEON);
 555     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 556     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 557     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 558     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 559     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 560     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 561     cpu->midr = 0x412fc0f1;
 562     cpu->reset_fpsid = 0x410430f0;
 563     cpu->mvfr0 = 0x10110222;
 564     cpu->mvfr1 = 0x11111111;
 565     cpu->ctr = 0x8444c004;
 566     cpu->reset_sctlr = 0x00c50078;
 567     cpu->id_pfr0 = 0x00001131;
 568     cpu->id_pfr1 = 0x00011011;
 569     cpu->id_dfr0 = 0x02010555;
 570     cpu->id_afr0 = 0x00000000;
 571     cpu->id_mmfr0 = 0x10201105;
 572     cpu->id_mmfr1 = 0x20000000;
 573     cpu->id_mmfr2 = 0x01240000;
 574     cpu->id_mmfr3 = 0x02102211;
 575     cpu->id_isar0 = 0x02101110;
 576     cpu->id_isar1 = 0x13112111;
 577     cpu->id_isar2 = 0x21232041;
 578     cpu->id_isar3 = 0x11112131;
 579     cpu->id_isar4 = 0x10011142;
 580     cpu->clidr = 0x0a200023;
 581     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 582     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 583     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 584     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 585 }
 586
 587 static void ti925t_initfn(Object *obj)
 588 {
 589     ARMCPU *cpu = ARM_CPU(obj);
 590     set_feature(&cpu->env, ARM_FEATURE_V4T);
 591     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 592     cpu->midr = ARM_CPUID_TI925T;
 593     cpu->ctr = 0x5109149;
 594     cpu->reset_sctlr = 0x00000070;
 595 }
 596
 597 static void sa1100_initfn(Object *obj)
 598 {
 599     ARMCPU *cpu = ARM_CPU(obj);
 600     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 601     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 602     cpu->midr = 0x4401A11B;
 603     cpu->reset_sctlr = 0x00000070;
 604 }
 605
 606 static void sa1110_initfn(Object *obj)
 607 {
 608     ARMCPU *cpu = ARM_CPU(obj);
 609     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 610     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 611     cpu->midr = 0x6901B119;
 612     cpu->reset_sctlr = 0x00000070;
 613 }
 614
 615 static void pxa250_initfn(Object *obj)
 616 {
 617     ARMCPU *cpu = ARM_CPU(obj);
 618     set_feature(&cpu->env, ARM_FEATURE_V5);
 619     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 620     cpu->midr = 0x69052100;
 621     cpu->ctr = 0xd172172;
 622     cpu->reset_sctlr = 0x00000078;
 623 }
 624
 625 static void pxa255_initfn(Object *obj)
 626 {
 627     ARMCPU *cpu = ARM_CPU(obj);
 628     set_feature(&cpu->env, ARM_FEATURE_V5);
 629     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 630     cpu->midr = 0x69052d00;
 631     cpu->ctr = 0xd172172;
 632     cpu->reset_sctlr = 0x00000078;
 633 }
 634
 635 static void pxa260_initfn(Object *obj)
 636 {
 637     ARMCPU *cpu = ARM_CPU(obj);
 638     set_feature(&cpu->env, ARM_FEATURE_V5);
 639     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 640     cpu->midr = 0x69052903;
 641     cpu->ctr = 0xd172172;
 642     cpu->reset_sctlr = 0x00000078;
 643 }
 644
 645 static void pxa261_initfn(Object *obj)
 646 {
 647     ARMCPU *cpu = ARM_CPU(obj);
 648     set_feature(&cpu->env, ARM_FEATURE_V5);
 649     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 650     cpu->midr = 0x69052d05;
 651     cpu->ctr = 0xd172172;
 652     cpu->reset_sctlr = 0x00000078;
 653 }
 654
 655 static void pxa262_initfn(Object *obj)
 656 {
 657     ARMCPU *cpu = ARM_CPU(obj);
 658     set_feature(&cpu->env, ARM_FEATURE_V5);
 659     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 660     cpu->midr = 0x69052d06;
 661     cpu->ctr = 0xd172172;
 662     cpu->reset_sctlr = 0x00000078;
 663 }
 664
 665 static void pxa270a0_initfn(Object *obj)
 666 {
 667     ARMCPU *cpu = ARM_CPU(obj);
 668     set_feature(&cpu->env, ARM_FEATURE_V5);
 669     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 670     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 671     cpu->midr = 0x69054110;
 672     cpu->ctr = 0xd172172;
 673     cpu->reset_sctlr = 0x00000078;
 674 }
 675
 676 static void pxa270a1_initfn(Object *obj)
 677 {
 678     ARMCPU *cpu = ARM_CPU(obj);
 679     set_feature(&cpu->env, ARM_FEATURE_V5);
 680     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 681     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 682     cpu->midr = 0x69054111;
 683     cpu->ctr = 0xd172172;
 684     cpu->reset_sctlr = 0x00000078;
 685 }
 686
 687 static void pxa270b0_initfn(Object *obj)
 688 {
 689     ARMCPU *cpu = ARM_CPU(obj);
 690     set_feature(&cpu->env, ARM_FEATURE_V5);
 691     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 692     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 693     cpu->midr = 0x69054112;
 694     cpu->ctr = 0xd172172;
 695     cpu->reset_sctlr = 0x00000078;
 696 }
 697
 698 static void pxa270b1_initfn(Object *obj)
 699 {
 700     ARMCPU *cpu = ARM_CPU(obj);
 701     set_feature(&cpu->env, ARM_FEATURE_V5);
 702     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 703     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 704     cpu->midr = 0x69054113;
 705     cpu->ctr = 0xd172172;
 706     cpu->reset_sctlr = 0x00000078;
 707 }
 708
 709 static void pxa270c0_initfn(Object *obj)
 710 {
 711     ARMCPU *cpu = ARM_CPU(obj);
 712     set_feature(&cpu->env, ARM_FEATURE_V5);
 713     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 714     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 715     cpu->midr = 0x69054114;
 716     cpu->ctr = 0xd172172;
 717     cpu->reset_sctlr = 0x00000078;
 718 }
 719
 720 static void pxa270c5_initfn(Object *obj)
 721 {
 722     ARMCPU *cpu = ARM_CPU(obj);
 723     set_feature(&cpu->env, ARM_FEATURE_V5);
 724     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 725     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 726     cpu->midr = 0x69054117;
 727     cpu->ctr = 0xd172172;
 728     cpu->reset_sctlr = 0x00000078;
 729 }
 730
 731 static void arm_any_initfn(Object *obj)
 732 {
 733     ARMCPU *cpu = ARM_CPU(obj);
 734     set_feature(&cpu->env, ARM_FEATURE_V7);
 735     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 736     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 737     set_feature(&cpu->env, ARM_FEATURE_NEON);
 738     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 739     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 740     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 741     cpu->midr = 0xffffffff;
 742 }
 743
 744 typedef struct ARMCPUInfo {
 745     const char *name;
 746     void (*initfn)(Object *obj);
 747 } ARMCPUInfo;
 748
 749 static const ARMCPUInfo arm_cpus[] = {
 750     { .name = "arm926",      .initfn = arm926_initfn },
 751     { .name = "arm946",      .initfn = arm946_initfn },
 752     { .name = "arm1026",     .initfn = arm1026_initfn },
 753     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 754      * older core than plain "arm1136". In particular this does not
 755      * have the v6K features.
 756      */
 757     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 758     { .name = "arm1136",     .initfn = arm1136_initfn },
 759     { .name = "arm1176",     .initfn = arm1176_initfn },
 760     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 761     { .name = "cortex-m3",   .initfn = cortex_m3_initfn },
 762     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 763     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 764     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 765     { .name = "ti925t",      .initfn = ti925t_initfn },
 766     { .name = "sa1100",      .initfn = sa1100_initfn },
 767     { .name = "sa1110",      .initfn = sa1110_initfn },
 768     { .name = "pxa250",      .initfn = pxa250_initfn },
 769     { .name = "pxa255",      .initfn = pxa255_initfn },
 770     { .name = "pxa260",      .initfn = pxa260_initfn },
 771     { .name = "pxa261",      .initfn = pxa261_initfn },
 772     { .name = "pxa262",      .initfn = pxa262_initfn },
 773     /* "pxa270" is an alias for "pxa270-a0" */
 774     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 775     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 776     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 777     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 778     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 779     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 780     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 781     { .name = "any",         .initfn = arm_any_initfn },
 782 };
 783
 784 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 785 {
 786     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 787     CPUClass *cc = CPU_CLASS(acc);
 788     DeviceClass *dc = DEVICE_CLASS(oc);
 789
 790     acc->parent_realize = dc->realize;
 791     dc->realize = arm_cpu_realizefn;
 792
 793     acc->parent_reset = cc->reset;
 794     cc->reset = arm_cpu_reset;
 795
 796     cc->class_by_name = arm_cpu_class_by_name;
 797 }
 798
 799 static void cpu_register(const ARMCPUInfo *info)
 800 {
 801     TypeInfo type_info = {
 802         .parent = TYPE_ARM_CPU,
 803         .instance_size = sizeof(ARMCPU),
 804         .instance_init = info->initfn,
 805         .class_size = sizeof(ARMCPUClass),
 806     };
 807
 808     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 809     type_register(&type_info);
 810     g_free((void *)type_info.name);
 811 }
 812
 813 static const TypeInfo arm_cpu_type_info = {
 814     .name = TYPE_ARM_CPU,
 815     .parent = TYPE_CPU,
 816     .instance_size = sizeof(ARMCPU),
 817     .instance_init = arm_cpu_initfn,
 818     .instance_finalize = arm_cpu_finalizefn,
 819     .abstract = true,
 820     .class_size = sizeof(ARMCPUClass),
 821     .class_init = arm_cpu_class_init,
 822 };
 823
 824 static void arm_cpu_register_types(void)
 825 {
 826     int i;
 827
 828     type_register_static(&arm_cpu_type_info);
 829     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
 830         cpu_register(&arm_cpus[i]);
 831     }
 832 }
 833
 834 type_init(arm_cpu_register_types)