target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define ELF_MACHINE     EM_ARM
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #define EXCP_UDEF            1   /* undefined instruction */
  34 #define EXCP_SWI             2   /* software interrupt */
  35 #define EXCP_PREFETCH_ABORT  3
  36 #define EXCP_DATA_ABORT      4
  37 #define EXCP_IRQ             5
  38 #define EXCP_FIQ             6
  39 #define EXCP_BKPT            7
  40
  41 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  42                             int srcreg, int operand, uint32_t value);
  43 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  44                                int dstreg, int operand);
  45
  46 /* We currently assume float and double are IEEE single and double
  47    precision respectively.
  48    Doing runtime conversions is tricky because VFP registers may contain
  49    integer values (eg. as the result of a FTOSI instruction).
  50    s<2n> maps to the least significant half of d<n>
  51    s<2n+1> maps to the most significant half of d<n>
  52  */
  53
  54 typedef struct CPUARMState {
  55     /* Regs for current mode.  */
  56     uint32_t regs[16];
  57     /* Frequently accessed CPSR bits are stored separately for efficiently.
  58        This contains all the other bits.  Use cpsr_{read,write} to access
  59        the whole CPSR.  */
  60     uint32_t uncached_cpsr;
  61     uint32_t spsr;
  62
  63     /* Banked registers.  */
  64     uint32_t banked_spsr[6];
  65     uint32_t banked_r13[6];
  66     uint32_t banked_r14[6];
  67
  68     /* These hold r8-r12.  */
  69     uint32_t usr_regs[5];
  70     uint32_t fiq_regs[5];
  71
  72     /* cpsr flag cache for faster execution */
  73     uint32_t CF; /* 0 or 1 */
  74     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  75     uint32_t NZF; /* N is bit 31. Z is computed from NZF */
  76     uint32_t QF; /* 0 or 1 */
  77
  78     int thumb; /* 0 = arm mode, 1 = thumb mode */
  79
  80     /* System control coprocessor (cp15) */
  81     struct {
  82         uint32_t c0_cpuid;
  83         uint32_t c0_cachetype;
  84         uint32_t c1_sys; /* System control register.  */
  85         uint32_t c1_coproc; /* Coprocessor access register.  */
  86         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
  87         uint32_t c2_base; /* MMU translation table base.  */
  88         uint32_t c2_data; /* MPU data cachable bits.  */
  89         uint32_t c2_insn; /* MPU instruction cachable bits.  */
  90         uint32_t c3; /* MMU domain access control register
  91                         MPU write buffer control.  */
  92         uint32_t c5_insn; /* Fault status registers.  */
  93         uint32_t c5_data;
  94         uint32_t c6_region[8]; /* MPU base/size registers.  */
  95         uint32_t c6_insn; /* Fault address registers.  */
  96         uint32_t c6_data;
  97         uint32_t c9_insn; /* Cache lockdown registers.  */
  98         uint32_t c9_data;
  99         uint32_t c13_fcse; /* FCSE PID.  */
 100         uint32_t c13_context; /* Context ID.  */
 101         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 102         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 103         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 104         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 105         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 106     } cp15;
 107
 108     /* Coprocessor IO used by peripherals */
 109     struct {
 110         ARMReadCPFunc *cp_read;
 111         ARMWriteCPFunc *cp_write;
 112         void *opaque;
 113     } cp[15];
 114
 115     /* Internal CPU feature flags.  */
 116     uint32_t features;
 117
 118     /* exception/interrupt handling */
 119     jmp_buf jmp_env;
 120     int exception_index;
 121     int interrupt_request;
 122     int user_mode_only;
 123     int halted;
 124
 125     /* VFP coprocessor state.  */
 126     struct {
 127         float64 regs[16];
 128
 129         uint32_t xregs[16];
 130         /* We store these fpcsr fields separately for convenience.  */
 131         int vec_len;
 132         int vec_stride;
 133
 134         /* Temporary variables if we don't have spare fp regs.  */
 135         float32 tmp0s, tmp1s;
 136         float64 tmp0d, tmp1d;
 137
 138         float_status fp_status;
 139     } vfp;
 140
 141     /* iwMMXt coprocessor state.  */
 142     struct {
 143         uint64_t regs[16];
 144         uint64_t val;
 145
 146         uint32_t cregs[16];
 147     } iwmmxt;
 148
 149 #if defined(CONFIG_USER_ONLY)
 150     /* For usermode syscall translation.  */
 151     int eabi;
 152 #endif
 153
 154     CPU_COMMON
 155
 156     /* These fields after the common ones so they are preserved on reset.  */
 157     int ram_size;
 158     const char *kernel_filename;
 159     const char *kernel_cmdline;
 160     const char *initrd_filename;
 161     int board_id;
 162     target_phys_addr_t loader_start;
 163 } CPUARMState;
 164
 165 CPUARMState *cpu_arm_init(void);
 166 int cpu_arm_exec(CPUARMState *s);
 167 void cpu_arm_close(CPUARMState *s);
 168 void do_interrupt(CPUARMState *);
 169 void switch_mode(CPUARMState *, int);
 170
 171 /* you can call this signal handler from your SIGBUS and SIGSEGV
 172    signal handlers to inform the virtual CPU of exceptions. non zero
 173    is returned if the signal was handled by the virtual CPU.  */
 174 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 175                            void *puc);
 176
 177 #define CPSR_M (0x1f)
 178 #define CPSR_T (1 << 5)
 179 #define CPSR_F (1 << 6)
 180 #define CPSR_I (1 << 7)
 181 #define CPSR_A (1 << 8)
 182 #define CPSR_E (1 << 9)
 183 #define CPSR_IT_2_7 (0xfc00)
 184 /* Bits 20-23 reserved.  */
 185 #define CPSR_J (1 << 24)
 186 #define CPSR_IT_0_1 (3 << 25)
 187 #define CPSR_Q (1 << 27)
 188 #define CPSR_NZCV (0xf << 28)
 189
 190 #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
 191 /* Return the current CPSR value.  */
 192 static inline uint32_t cpsr_read(CPUARMState *env)
 193 {
 194     int ZF;
 195     ZF = (env->NZF == 0);
 196     return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
 197         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 198         | (env->thumb << 5);
 199 }
 200
 201 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 202 static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 203 {
 204     /* NOTE: N = 1 and Z = 1 cannot be stored currently */
 205     if (mask & CPSR_NZCV) {
 206         env->NZF = (val & 0xc0000000) ^ 0x40000000;
 207         env->CF = (val >> 29) & 1;
 208         env->VF = (val << 3) & 0x80000000;
 209     }
 210     if (mask & CPSR_Q)
 211         env->QF = ((val & CPSR_Q) != 0);
 212     if (mask & CPSR_T)
 213         env->thumb = ((val & CPSR_T) != 0);
 214
 215     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
 216         switch_mode(env, val & CPSR_M);
 217     }
 218     mask &= ~CACHED_CPSR_BITS;
 219     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
 220 }
 221
 222 enum arm_cpu_mode {
 223   ARM_CPU_MODE_USR = 0x10,
 224   ARM_CPU_MODE_FIQ = 0x11,
 225   ARM_CPU_MODE_IRQ = 0x12,
 226   ARM_CPU_MODE_SVC = 0x13,
 227   ARM_CPU_MODE_ABT = 0x17,
 228   ARM_CPU_MODE_UND = 0x1b,
 229   ARM_CPU_MODE_SYS = 0x1f
 230 };
 231
 232 /* VFP system registers.  */
 233 #define ARM_VFP_FPSID   0
 234 #define ARM_VFP_FPSCR   1
 235 #define ARM_VFP_FPEXC   8
 236 #define ARM_VFP_FPINST  9
 237 #define ARM_VFP_FPINST2 10
 238
 239 /* iwMMXt coprocessor control registers.  */
 240 #define ARM_IWMMXT_wCID         0
 241 #define ARM_IWMMXT_wCon         1
 242 #define ARM_IWMMXT_wCSSF        2
 243 #define ARM_IWMMXT_wCASF        3
 244 #define ARM_IWMMXT_wCGR0        8
 245 #define ARM_IWMMXT_wCGR1        9
 246 #define ARM_IWMMXT_wCGR2        10
 247 #define ARM_IWMMXT_wCGR3        11
 248
 249 enum arm_features {
 250     ARM_FEATURE_VFP,
 251     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 252     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 253     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 254     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 255     ARM_FEATURE_OMAPCP  /* OMAP specific CP15 ops handling.  */
 256 };
 257
 258 static inline int arm_feature(CPUARMState *env, int feature)
 259 {
 260     return (env->features & (1u << feature)) != 0;
 261 }
 262
 263 void arm_cpu_list(void);
 264 void cpu_arm_set_model(CPUARMState *env, const char *name);
 265
 266 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 267                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 268                        void *opaque);
 269
 270 #define ARM_CPUID_ARM1026   0x4106a262
 271 #define ARM_CPUID_ARM926    0x41069265
 272 #define ARM_CPUID_ARM946    0x41059461
 273 #define ARM_CPUID_TI915T    0x54029152
 274 #define ARM_CPUID_TI925T    0x54029252
 275 #define ARM_CPUID_PXA250    0x69052100
 276 #define ARM_CPUID_PXA255    0x69052d00
 277 #define ARM_CPUID_PXA260    0x69052903
 278 #define ARM_CPUID_PXA261    0x69052d05
 279 #define ARM_CPUID_PXA262    0x69052d06
 280 #define ARM_CPUID_PXA270    0x69054110
 281 #define ARM_CPUID_PXA270_A0 0x69054110
 282 #define ARM_CPUID_PXA270_A1 0x69054111
 283 #define ARM_CPUID_PXA270_B0 0x69054112
 284 #define ARM_CPUID_PXA270_B1 0x69054113
 285 #define ARM_CPUID_PXA270_C0 0x69054114
 286 #define ARM_CPUID_PXA270_C5 0x69054117
 287
 288 #if defined(CONFIG_USER_ONLY)
 289 #define TARGET_PAGE_BITS 12
 290 #else
 291 /* The ARM MMU allows 1k pages.  */
 292 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 293    architecture revisions.  Maybe a configure option to disable them.  */
 294 #define TARGET_PAGE_BITS 10
 295 #endif
 296
 297 #define CPUState CPUARMState
 298 #define cpu_init cpu_arm_init
 299 #define cpu_exec cpu_arm_exec
 300 #define cpu_gen_code cpu_arm_gen_code
 301 #define cpu_signal_handler cpu_arm_signal_handler
 302
 303 #include "cpu-all.h"
 304
 305 #endif