target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define ELF_MACHINE     EM_ARM
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #define EXCP_UDEF            1   /* undefined instruction */
  34 #define EXCP_SWI             2   /* software interrupt */
  35 #define EXCP_PREFETCH_ABORT  3
  36 #define EXCP_DATA_ABORT      4
  37 #define EXCP_IRQ             5
  38 #define EXCP_FIQ             6
  39 #define EXCP_BKPT            7
  40 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  41
  42 #define ARMV7M_EXCP_RESET   1
  43 #define ARMV7M_EXCP_NMI     2
  44 #define ARMV7M_EXCP_HARD    3
  45 #define ARMV7M_EXCP_MEM     4
  46 #define ARMV7M_EXCP_BUS     5
  47 #define ARMV7M_EXCP_USAGE   6
  48 #define ARMV7M_EXCP_SVC     11
  49 #define ARMV7M_EXCP_DEBUG   12
  50 #define ARMV7M_EXCP_PENDSV  14
  51 #define ARMV7M_EXCP_SYSTICK 15
  52
  53 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  54                             int srcreg, int operand, uint32_t value);
  55 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  56                                int dstreg, int operand);
  57
  58 struct arm_boot_info;
  59
  60 #define NB_MMU_MODES 2
  61
  62 /* We currently assume float and double are IEEE single and double
  63    precision respectively.
  64    Doing runtime conversions is tricky because VFP registers may contain
  65    integer values (eg. as the result of a FTOSI instruction).
  66    s<2n> maps to the least significant half of d<n>
  67    s<2n+1> maps to the most significant half of d<n>
  68  */
  69
  70 typedef struct CPUARMState {
  71     /* Regs for current mode.  */
  72     uint32_t regs[16];
  73     /* Frequently accessed CPSR bits are stored separately for efficiently.
  74        This contains all the other bits.  Use cpsr_{read,write} to access
  75        the whole CPSR.  */
  76     uint32_t uncached_cpsr;
  77     uint32_t spsr;
  78
  79     /* Banked registers.  */
  80     uint32_t banked_spsr[6];
  81     uint32_t banked_r13[6];
  82     uint32_t banked_r14[6];
  83
  84     /* These hold r8-r12.  */
  85     uint32_t usr_regs[5];
  86     uint32_t fiq_regs[5];
  87
  88     /* cpsr flag cache for faster execution */
  89     uint32_t CF; /* 0 or 1 */
  90     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  91     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
  92     uint32_t ZF; /* Z set if zero.  */
  93     uint32_t QF; /* 0 or 1 */
  94     uint32_t GE; /* cpsr[19:16] */
  95     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
  96     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
  97
  98     /* System control coprocessor (cp15) */
  99     struct {
 100         uint32_t c0_cpuid;
 101         uint32_t c0_cachetype;
 102         uint32_t c0_c1[8]; /* Feature registers.  */
 103         uint32_t c0_c2[8]; /* Instruction set registers.  */
 104         uint32_t c1_sys; /* System control register.  */
 105         uint32_t c1_coproc; /* Coprocessor access register.  */
 106         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 107         uint32_t c2_base0; /* MMU translation table base 0.  */
 108         uint32_t c2_base1; /* MMU translation table base 1.  */
 109         uint32_t c2_mask; /* MMU translation table base mask.  */
 110         uint32_t c2_data; /* MPU data cachable bits.  */
 111         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 112         uint32_t c3; /* MMU domain access control register
 113                         MPU write buffer control.  */
 114         uint32_t c5_insn; /* Fault status registers.  */
 115         uint32_t c5_data;
 116         uint32_t c6_region[8]; /* MPU base/size registers.  */
 117         uint32_t c6_insn; /* Fault address registers.  */
 118         uint32_t c6_data;
 119         uint32_t c9_insn; /* Cache lockdown registers.  */
 120         uint32_t c9_data;
 121         uint32_t c13_fcse; /* FCSE PID.  */
 122         uint32_t c13_context; /* Context ID.  */
 123         uint32_t c13_tls1; /* User RW Thread register.  */
 124         uint32_t c13_tls2; /* User RO Thread register.  */
 125         uint32_t c13_tls3; /* Privileged Thread register.  */
 126         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 127         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 128         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 129         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 130         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 131     } cp15;
 132
 133     struct {
 134         uint32_t other_sp;
 135         uint32_t vecbase;
 136         uint32_t basepri;
 137         uint32_t control;
 138         int current_sp;
 139         int exception;
 140         int pending_exception;
 141         void *nvic;
 142     } v7m;
 143
 144     /* Coprocessor IO used by peripherals */
 145     struct {
 146         ARMReadCPFunc *cp_read;
 147         ARMWriteCPFunc *cp_write;
 148         void *opaque;
 149     } cp[15];
 150
 151     /* Internal CPU feature flags.  */
 152     uint32_t features;
 153
 154     /* Callback for vectored interrupt controller.  */
 155     int (*get_irq_vector)(struct CPUARMState *);
 156     void *irq_opaque;
 157
 158     /* exception/interrupt handling */
 159     jmp_buf jmp_env;
 160     int exception_index;
 161     int interrupt_request;
 162     int user_mode_only;
 163     int halted;
 164
 165     /* VFP coprocessor state.  */
 166     struct {
 167         float64 regs[32];
 168
 169         uint32_t xregs[16];
 170         /* We store these fpcsr fields separately for convenience.  */
 171         int vec_len;
 172         int vec_stride;
 173
 174         /* scratch space when Tn are not sufficient.  */
 175         uint32_t scratch[8];
 176
 177         float_status fp_status;
 178     } vfp;
 179 #if defined(CONFIG_USER_ONLY)
 180     struct mmon_state *mmon_entry;
 181 #else
 182     uint32_t mmon_addr;
 183 #endif
 184
 185     /* iwMMXt coprocessor state.  */
 186     struct {
 187         uint64_t regs[16];
 188         uint64_t val;
 189
 190         uint32_t cregs[16];
 191     } iwmmxt;
 192
 193 #if defined(CONFIG_USER_ONLY)
 194     /* For usermode syscall translation.  */
 195     int eabi;
 196 #endif
 197
 198     CPU_COMMON
 199
 200     /* These fields after the common ones so they are preserved on reset.  */
 201     struct arm_boot_info *boot_info;
 202 } CPUARMState;
 203
 204 CPUARMState *cpu_arm_init(const char *cpu_model);
 205 void arm_translate_init(void);
 206 int cpu_arm_exec(CPUARMState *s);
 207 void cpu_arm_close(CPUARMState *s);
 208 void do_interrupt(CPUARMState *);
 209 void switch_mode(CPUARMState *, int);
 210 uint32_t do_arm_semihosting(CPUARMState *env);
 211
 212 /* you can call this signal handler from your SIGBUS and SIGSEGV
 213    signal handlers to inform the virtual CPU of exceptions. non zero
 214    is returned if the signal was handled by the virtual CPU.  */
 215 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 216                            void *puc);
 217
 218 void cpu_lock(void);
 219 void cpu_unlock(void);
 220
 221 #define CPSR_M (0x1f)
 222 #define CPSR_T (1 << 5)
 223 #define CPSR_F (1 << 6)
 224 #define CPSR_I (1 << 7)
 225 #define CPSR_A (1 << 8)
 226 #define CPSR_E (1 << 9)
 227 #define CPSR_IT_2_7 (0xfc00)
 228 #define CPSR_GE (0xf << 16)
 229 #define CPSR_RESERVED (0xf << 20)
 230 #define CPSR_J (1 << 24)
 231 #define CPSR_IT_0_1 (3 << 25)
 232 #define CPSR_Q (1 << 27)
 233 #define CPSR_V (1 << 28)
 234 #define CPSR_C (1 << 29)
 235 #define CPSR_Z (1 << 30)
 236 #define CPSR_N (1 << 31)
 237 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 238
 239 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 240 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 241 /* Bits writable in user mode.  */
 242 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 243 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 244 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 245
 246 /* Return the current CPSR value.  */
 247 uint32_t cpsr_read(CPUARMState *env);
 248 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 249 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 250
 251 /* Return the current xPSR value.  */
 252 static inline uint32_t xpsr_read(CPUARMState *env)
 253 {
 254     int ZF;
 255     ZF = (env->ZF == 0);
 256     return (env->NF & 0x80000000) | (ZF << 30)
 257         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 258         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 259         | ((env->condexec_bits & 0xfc) << 8)
 260         | env->v7m.exception;
 261 }
 262
 263 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 264 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 265 {
 266     if (mask & CPSR_NZCV) {
 267         env->ZF = (~val) & CPSR_Z;
 268         env->NF = val;
 269         env->CF = (val >> 29) & 1;
 270         env->VF = (val << 3) & 0x80000000;
 271     }
 272     if (mask & CPSR_Q)
 273         env->QF = ((val & CPSR_Q) != 0);
 274     if (mask & (1 << 24))
 275         env->thumb = ((val & (1 << 24)) != 0);
 276     if (mask & CPSR_IT_0_1) {
 277         env->condexec_bits &= ~3;
 278         env->condexec_bits |= (val >> 25) & 3;
 279     }
 280     if (mask & CPSR_IT_2_7) {
 281         env->condexec_bits &= 3;
 282         env->condexec_bits |= (val >> 8) & 0xfc;
 283     }
 284     if (mask & 0x1ff) {
 285         env->v7m.exception = val & 0x1ff;
 286     }
 287 }
 288
 289 enum arm_cpu_mode {
 290   ARM_CPU_MODE_USR = 0x10,
 291   ARM_CPU_MODE_FIQ = 0x11,
 292   ARM_CPU_MODE_IRQ = 0x12,
 293   ARM_CPU_MODE_SVC = 0x13,
 294   ARM_CPU_MODE_ABT = 0x17,
 295   ARM_CPU_MODE_UND = 0x1b,
 296   ARM_CPU_MODE_SYS = 0x1f
 297 };
 298
 299 /* VFP system registers.  */
 300 #define ARM_VFP_FPSID   0
 301 #define ARM_VFP_FPSCR   1
 302 #define ARM_VFP_MVFR1   6
 303 #define ARM_VFP_MVFR0   7
 304 #define ARM_VFP_FPEXC   8
 305 #define ARM_VFP_FPINST  9
 306 #define ARM_VFP_FPINST2 10
 307
 308 /* iwMMXt coprocessor control registers.  */
 309 #define ARM_IWMMXT_wCID         0
 310 #define ARM_IWMMXT_wCon         1
 311 #define ARM_IWMMXT_wCSSF        2
 312 #define ARM_IWMMXT_wCASF        3
 313 #define ARM_IWMMXT_wCGR0        8
 314 #define ARM_IWMMXT_wCGR1        9
 315 #define ARM_IWMMXT_wCGR2        10
 316 #define ARM_IWMMXT_wCGR3        11
 317
 318 enum arm_features {
 319     ARM_FEATURE_VFP,
 320     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 321     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 322     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 323     ARM_FEATURE_V6,
 324     ARM_FEATURE_V6K,
 325     ARM_FEATURE_V7,
 326     ARM_FEATURE_THUMB2,
 327     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 328     ARM_FEATURE_VFP3,
 329     ARM_FEATURE_NEON,
 330     ARM_FEATURE_DIV,
 331     ARM_FEATURE_M, /* Microcontroller profile.  */
 332     ARM_FEATURE_OMAPCP  /* OMAP specific CP15 ops handling.  */
 333 };
 334
 335 static inline int arm_feature(CPUARMState *env, int feature)
 336 {
 337     return (env->features & (1u << feature)) != 0;
 338 }
 339
 340 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 341
 342 /* Interface between CPU and Interrupt controller.  */
 343 void armv7m_nvic_set_pending(void *opaque, int irq);
 344 int armv7m_nvic_acknowledge_irq(void *opaque);
 345 void armv7m_nvic_complete_irq(void *opaque, int irq);
 346
 347 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 348                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 349                        void *opaque);
 350
 351 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 352    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 353    conventional cores (ie. Application or Realtime profile).  */
 354
 355 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 356 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 357
 358 #define ARM_CPUID_ARM1026     0x4106a262
 359 #define ARM_CPUID_ARM926      0x41069265
 360 #define ARM_CPUID_ARM946      0x41059461
 361 #define ARM_CPUID_TI915T      0x54029152
 362 #define ARM_CPUID_TI925T      0x54029252
 363 #define ARM_CPUID_PXA250      0x69052100
 364 #define ARM_CPUID_PXA255      0x69052d00
 365 #define ARM_CPUID_PXA260      0x69052903
 366 #define ARM_CPUID_PXA261      0x69052d05
 367 #define ARM_CPUID_PXA262      0x69052d06
 368 #define ARM_CPUID_PXA270      0x69054110
 369 #define ARM_CPUID_PXA270_A0   0x69054110
 370 #define ARM_CPUID_PXA270_A1   0x69054111
 371 #define ARM_CPUID_PXA270_B0   0x69054112
 372 #define ARM_CPUID_PXA270_B1   0x69054113
 373 #define ARM_CPUID_PXA270_C0   0x69054114
 374 #define ARM_CPUID_PXA270_C5   0x69054117
 375 #define ARM_CPUID_ARM1136     0x4117b363
 376 #define ARM_CPUID_ARM1136_R2  0x4107b362
 377 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 378 #define ARM_CPUID_CORTEXA8    0x410fc080
 379 #define ARM_CPUID_CORTEXM3    0x410fc231
 380 #define ARM_CPUID_ANY         0xffffffff
 381
 382 #if defined(CONFIG_USER_ONLY)
 383 #define TARGET_PAGE_BITS 12
 384 #else
 385 /* The ARM MMU allows 1k pages.  */
 386 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 387    architecture revisions.  Maybe a configure option to disable them.  */
 388 #define TARGET_PAGE_BITS 10
 389 #endif
 390
 391 #define CPUState CPUARMState
 392 #define cpu_init cpu_arm_init
 393 #define cpu_exec cpu_arm_exec
 394 #define cpu_gen_code cpu_arm_gen_code
 395 #define cpu_signal_handler cpu_arm_signal_handler
 396 #define cpu_list arm_cpu_list
 397
 398 #define ARM_CPU_SAVE_VERSION 1
 399
 400 /* MMU modes definitions */
 401 #define MMU_MODE0_SUFFIX _kernel
 402 #define MMU_MODE1_SUFFIX _user
 403 #define MMU_USER_IDX 1
 404 static inline int cpu_mmu_index (CPUState *env)
 405 {
 406     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 407 }
 408
 409 #include "cpu-all.h"
 410
 411 #endif