target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define ELF_MACHINE     EM_ARM
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #define EXCP_UDEF            1   /* undefined instruction */
  34 #define EXCP_SWI             2   /* software interrupt */
  35 #define EXCP_PREFETCH_ABORT  3
  36 #define EXCP_DATA_ABORT      4
  37 #define EXCP_IRQ             5
  38 #define EXCP_FIQ             6
  39 #define EXCP_BKPT            7
  40
  41 /* We currently assume float and double are IEEE single and double
  42    precision respectively.
  43    Doing runtime conversions is tricky because VFP registers may contain
  44    integer values (eg. as the result of a FTOSI instruction).
  45    s<2n> maps to the least significant half of d<n>
  46    s<2n+1> maps to the most significant half of d<n>
  47  */
  48
  49 typedef struct CPUARMState {
  50     /* Regs for current mode.  */
  51     uint32_t regs[16];
  52     /* Frequently accessed CPSR bits are stored separately for efficiently.
  53        This contains all the other bits.  Use cpsr_{read,write} to access
  54        the whole CPSR.  */
  55     uint32_t uncached_cpsr;
  56     uint32_t spsr;
  57
  58     /* Banked registers.  */
  59     uint32_t banked_spsr[6];
  60     uint32_t banked_r13[6];
  61     uint32_t banked_r14[6];
  62
  63     /* These hold r8-r12.  */
  64     uint32_t usr_regs[5];
  65     uint32_t fiq_regs[5];
  66
  67     /* cpsr flag cache for faster execution */
  68     uint32_t CF; /* 0 or 1 */
  69     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  70     uint32_t NZF; /* N is bit 31. Z is computed from NZF */
  71     uint32_t QF; /* 0 or 1 */
  72
  73     int thumb; /* 0 = arm mode, 1 = thumb mode */
  74
  75     /* System control coprocessor (cp15) */
  76     struct {
  77         uint32_t c0_cpuid;
  78         uint32_t c1_sys; /* System control register.  */
  79         uint32_t c1_coproc; /* Coprocessor access register.  */
  80         uint32_t c2; /* MMU translation table base.  */
  81         uint32_t c3; /* MMU domain access control register.  */
  82         uint32_t c5_insn; /* Fault status registers.  */
  83         uint32_t c5_data;
  84         uint32_t c6_insn; /* Fault address registers.  */
  85         uint32_t c6_data;
  86         uint32_t c9_insn; /* Cache lockdown registers.  */
  87         uint32_t c9_data;
  88         uint32_t c13_fcse; /* FCSE PID.  */
  89         uint32_t c13_context; /* Context ID.  */
  90     } cp15;
  91
  92     /* Internal CPU feature flags.  */
  93     uint32_t features;
  94
  95     /* exception/interrupt handling */
  96     jmp_buf jmp_env;
  97     int exception_index;
  98     int interrupt_request;
  99     int user_mode_only;
 100     int halted;
 101
 102     /* VFP coprocessor state.  */
 103     struct {
 104         float64 regs[16];
 105
 106         uint32_t xregs[16];
 107         /* We store these fpcsr fields separately for convenience.  */
 108         int vec_len;
 109         int vec_stride;
 110
 111         /* Temporary variables if we don't have spare fp regs.  */
 112         float32 tmp0s, tmp1s;
 113         float64 tmp0d, tmp1d;
 114
 115         float_status fp_status;
 116     } vfp;
 117
 118 #if defined(CONFIG_USER_ONLY)
 119     /* For usermode syscall translation.  */
 120     int eabi;
 121 #endif
 122
 123     CPU_COMMON
 124
 125 } CPUARMState;
 126
 127 CPUARMState *cpu_arm_init(void);
 128 int cpu_arm_exec(CPUARMState *s);
 129 void cpu_arm_close(CPUARMState *s);
 130 void do_interrupt(CPUARMState *);
 131 void switch_mode(CPUARMState *, int);
 132
 133 /* you can call this signal handler from your SIGBUS and SIGSEGV
 134    signal handlers to inform the virtual CPU of exceptions. non zero
 135    is returned if the signal was handled by the virtual CPU.  */
 136 struct siginfo;
 137 int cpu_arm_signal_handler(int host_signum, struct siginfo *info,
 138                            void *puc);
 139
 140 #define CPSR_M (0x1f)
 141 #define CPSR_T (1 << 5)
 142 #define CPSR_F (1 << 6)
 143 #define CPSR_I (1 << 7)
 144 #define CPSR_A (1 << 8)
 145 #define CPSR_E (1 << 9)
 146 #define CPSR_IT_2_7 (0xfc00)
 147 /* Bits 20-23 reserved.  */
 148 #define CPSR_J (1 << 24)
 149 #define CPSR_IT_0_1 (3 << 25)
 150 #define CPSR_Q (1 << 27)
 151 #define CPSR_NZCV (0xf << 28)
 152
 153 #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
 154 /* Return the current CPSR value.  */
 155 static inline uint32_t cpsr_read(CPUARMState *env)
 156 {
 157     int ZF;
 158     ZF = (env->NZF == 0);
 159     return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
 160         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 161         | (env->thumb << 5);
 162 }
 163
 164 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 165 static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 166 {
 167     /* NOTE: N = 1 and Z = 1 cannot be stored currently */
 168     if (mask & CPSR_NZCV) {
 169         env->NZF = (val & 0xc0000000) ^ 0x40000000;
 170         env->CF = (val >> 29) & 1;
 171         env->VF = (val << 3) & 0x80000000;
 172     }
 173     if (mask & CPSR_Q)
 174         env->QF = ((val & CPSR_Q) != 0);
 175     if (mask & CPSR_T)
 176         env->thumb = ((val & CPSR_T) != 0);
 177
 178     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
 179         switch_mode(env, val & CPSR_M);
 180     }
 181     mask &= ~CACHED_CPSR_BITS;
 182     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
 183 }
 184
 185 enum arm_cpu_mode {
 186   ARM_CPU_MODE_USR = 0x10,
 187   ARM_CPU_MODE_FIQ = 0x11,
 188   ARM_CPU_MODE_IRQ = 0x12,
 189   ARM_CPU_MODE_SVC = 0x13,
 190   ARM_CPU_MODE_ABT = 0x17,
 191   ARM_CPU_MODE_UND = 0x1b,
 192   ARM_CPU_MODE_SYS = 0x1f
 193 };
 194
 195 /* VFP system registers.  */
 196 #define ARM_VFP_FPSID   0
 197 #define ARM_VFP_FPSCR   1
 198 #define ARM_VFP_FPEXC   8
 199 #define ARM_VFP_FPINST  9
 200 #define ARM_VFP_FPINST2 10
 201
 202
 203 enum arm_features {
 204     ARM_FEATURE_VFP,
 205     ARM_FEATURE_AUXCR /* ARM1026 Auxiliary control register.  */
 206 };
 207
 208 static inline int arm_feature(CPUARMState *env, int feature)
 209 {
 210     return (env->features & (1u << feature)) != 0;
 211 }
 212
 213 void cpu_arm_set_model(CPUARMState *env, uint32_t id);
 214
 215 #define ARM_CPUID_ARM1026 0x4106a262
 216 #define ARM_CPUID_ARM926  0x41069265
 217
 218 #if defined(CONFIG_USER_ONLY)
 219 #define TARGET_PAGE_BITS 12
 220 #else
 221 /* The ARM MMU allows 1k pages.  */
 222 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 223    architecture revisions.  Maybe an a configure option to disable them.  */
 224 #define TARGET_PAGE_BITS 10
 225 #endif
 226 #include "cpu-all.h"
 227
 228 #endif