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1 #include "cpu.h"
2 #include "internals.h"
3 #include "exec/gdbstub.h"
4 #include "exec/helper-proto.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include "exec/cpu_ldst.h"
11 #include "arm_ldst.h"
12 #include <zlib.h> /* For crc32 */
13
14 #ifndef CONFIG_USER_ONLY
15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
16 int access_type, int is_user,
17 hwaddr *phys_ptr, int *prot,
18 target_ulong *page_size);
19
20 /* Definitions for the PMCCNTR and PMCR registers */
21 #define PMCRD 0x8
22 #define PMCRC 0x4
23 #define PMCRE 0x1
24 #endif
25
26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
27 {
28 int nregs;
29
30 /* VFP data registers are always little-endian. */
31 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
32 if (reg < nregs) {
33 stfq_le_p(buf, env->vfp.regs[reg]);
34 return 8;
35 }
36 if (arm_feature(env, ARM_FEATURE_NEON)) {
37 /* Aliases for Q regs. */
38 nregs += 16;
39 if (reg < nregs) {
40 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
41 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
42 return 16;
43 }
44 }
45 switch (reg - nregs) {
46 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
47 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
48 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
49 }
50 return 0;
51 }
52
53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
54 {
55 int nregs;
56
57 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
58 if (reg < nregs) {
59 env->vfp.regs[reg] = ldfq_le_p(buf);
60 return 8;
61 }
62 if (arm_feature(env, ARM_FEATURE_NEON)) {
63 nregs += 16;
64 if (reg < nregs) {
65 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
66 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
67 return 16;
68 }
69 }
70 switch (reg - nregs) {
71 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
72 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
73 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
74 }
75 return 0;
76 }
77
78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
79 {
80 switch (reg) {
81 case 0 ... 31:
82 /* 128 bit FP register */
83 stfq_le_p(buf, env->vfp.regs[reg * 2]);
84 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
85 return 16;
86 case 32:
87 /* FPSR */
88 stl_p(buf, vfp_get_fpsr(env));
89 return 4;
90 case 33:
91 /* FPCR */
92 stl_p(buf, vfp_get_fpcr(env));
93 return 4;
94 default:
95 return 0;
96 }
97 }
98
99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
100 {
101 switch (reg) {
102 case 0 ... 31:
103 /* 128 bit FP register */
104 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
105 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
106 return 16;
107 case 32:
108 /* FPSR */
109 vfp_set_fpsr(env, ldl_p(buf));
110 return 4;
111 case 33:
112 /* FPCR */
113 vfp_set_fpcr(env, ldl_p(buf));
114 return 4;
115 default:
116 return 0;
117 }
118 }
119
120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
121 {
122 if (cpreg_field_is_64bit(ri)) {
123 return CPREG_FIELD64(env, ri);
124 } else {
125 return CPREG_FIELD32(env, ri);
126 }
127 }
128
129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
130 uint64_t value)
131 {
132 if (cpreg_field_is_64bit(ri)) {
133 CPREG_FIELD64(env, ri) = value;
134 } else {
135 CPREG_FIELD32(env, ri) = value;
136 }
137 }
138
139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
140 {
141 /* Raw read of a coprocessor register (as needed for migration, etc). */
142 if (ri->type & ARM_CP_CONST) {
143 return ri->resetvalue;
144 } else if (ri->raw_readfn) {
145 return ri->raw_readfn(env, ri);
146 } else if (ri->readfn) {
147 return ri->readfn(env, ri);
148 } else {
149 return raw_read(env, ri);
150 }
151 }
152
153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
154 uint64_t v)
155 {
156 /* Raw write of a coprocessor register (as needed for migration, etc).
157 * Note that constant registers are treated as write-ignored; the
158 * caller should check for success by whether a readback gives the
159 * value written.
160 */
161 if (ri->type & ARM_CP_CONST) {
162 return;
163 } else if (ri->raw_writefn) {
164 ri->raw_writefn(env, ri, v);
165 } else if (ri->writefn) {
166 ri->writefn(env, ri, v);
167 } else {
168 raw_write(env, ri, v);
169 }
170 }
171
172 bool write_cpustate_to_list(ARMCPU *cpu)
173 {
174 /* Write the coprocessor state from cpu->env to the (index,value) list. */
175 int i;
176 bool ok = true;
177
178 for (i = 0; i < cpu->cpreg_array_len; i++) {
179 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
180 const ARMCPRegInfo *ri;
181
182 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
183 if (!ri) {
184 ok = false;
185 continue;
186 }
187 if (ri->type & ARM_CP_NO_MIGRATE) {
188 continue;
189 }
190 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
191 }
192 return ok;
193 }
194
195 bool write_list_to_cpustate(ARMCPU *cpu)
196 {
197 int i;
198 bool ok = true;
199
200 for (i = 0; i < cpu->cpreg_array_len; i++) {
201 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
202 uint64_t v = cpu->cpreg_values[i];
203 const ARMCPRegInfo *ri;
204
205 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
206 if (!ri) {
207 ok = false;
208 continue;
209 }
210 if (ri->type & ARM_CP_NO_MIGRATE) {
211 continue;
212 }
213 /* Write value and confirm it reads back as written
214 * (to catch read-only registers and partially read-only
215 * registers where the incoming migration value doesn't match)
216 */
217 write_raw_cp_reg(&cpu->env, ri, v);
218 if (read_raw_cp_reg(&cpu->env, ri) != v) {
219 ok = false;
220 }
221 }
222 return ok;
223 }
224
225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
226 {
227 ARMCPU *cpu = opaque;
228 uint64_t regidx;
229 const ARMCPRegInfo *ri;
230
231 regidx = *(uint32_t *)key;
232 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
233
234 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
235 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
236 /* The value array need not be initialized at this point */
237 cpu->cpreg_array_len++;
238 }
239 }
240
241 static void count_cpreg(gpointer key, gpointer opaque)
242 {
243 ARMCPU *cpu = opaque;
244 uint64_t regidx;
245 const ARMCPRegInfo *ri;
246
247 regidx = *(uint32_t *)key;
248 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
249
250 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
251 cpu->cpreg_array_len++;
252 }
253 }
254
255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
256 {
257 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
258 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
259
260 if (aidx > bidx) {
261 return 1;
262 }
263 if (aidx < bidx) {
264 return -1;
265 }
266 return 0;
267 }
268
269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
270 {
271 GList **plist = udata;
272
273 *plist = g_list_prepend(*plist, key);
274 }
275
276 void init_cpreg_list(ARMCPU *cpu)
277 {
278 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
279 * Note that we require cpreg_tuples[] to be sorted by key ID.
280 */
281 GList *keys = NULL;
282 int arraylen;
283
284 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
285
286 keys = g_list_sort(keys, cpreg_key_compare);
287
288 cpu->cpreg_array_len = 0;
289
290 g_list_foreach(keys, count_cpreg, cpu);
291
292 arraylen = cpu->cpreg_array_len;
293 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
294 cpu->cpreg_values = g_new(uint64_t, arraylen);
295 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
296 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
297 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
298 cpu->cpreg_array_len = 0;
299
300 g_list_foreach(keys, add_cpreg_to_list, cpu);
301
302 assert(cpu->cpreg_array_len == arraylen);
303
304 g_list_free(keys);
305 }
306
307 /* Return true if extended addresses are enabled.
308 * This is always the case if our translation regime is 64 bit,
309 * but depends on TTBCR.EAE for 32 bit.
310 */
311 static inline bool extended_addresses_enabled(CPUARMState *env)
312 {
313 return arm_el_is_aa64(env, 1)
314 || ((arm_feature(env, ARM_FEATURE_LPAE)
315 && (env->cp15.c2_control & (1U << 31))));
316 }
317
318 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
319 {
320 ARMCPU *cpu = arm_env_get_cpu(env);
321
322 env->cp15.c3 = value;
323 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
324 }
325
326 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
327 {
328 ARMCPU *cpu = arm_env_get_cpu(env);
329
330 if (env->cp15.c13_fcse != value) {
331 /* Unlike real hardware the qemu TLB uses virtual addresses,
332 * not modified virtual addresses, so this causes a TLB flush.
333 */
334 tlb_flush(CPU(cpu), 1);
335 env->cp15.c13_fcse = value;
336 }
337 }
338
339 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
340 uint64_t value)
341 {
342 ARMCPU *cpu = arm_env_get_cpu(env);
343
344 if (env->cp15.contextidr_el1 != value && !arm_feature(env, ARM_FEATURE_MPU)
345 && !extended_addresses_enabled(env)) {
346 /* For VMSA (when not using the LPAE long descriptor page table
347 * format) this register includes the ASID, so do a TLB flush.
348 * For PMSA it is purely a process ID and no action is needed.
349 */
350 tlb_flush(CPU(cpu), 1);
351 }
352 env->cp15.contextidr_el1 = value;
353 }
354
355 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
356 uint64_t value)
357 {
358 /* Invalidate all (TLBIALL) */
359 ARMCPU *cpu = arm_env_get_cpu(env);
360
361 tlb_flush(CPU(cpu), 1);
362 }
363
364 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
365 uint64_t value)
366 {
367 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
368 ARMCPU *cpu = arm_env_get_cpu(env);
369
370 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
371 }
372
373 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
374 uint64_t value)
375 {
376 /* Invalidate by ASID (TLBIASID) */
377 ARMCPU *cpu = arm_env_get_cpu(env);
378
379 tlb_flush(CPU(cpu), value == 0);
380 }
381
382 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
383 uint64_t value)
384 {
385 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
386 ARMCPU *cpu = arm_env_get_cpu(env);
387
388 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
389 }
390
391 static const ARMCPRegInfo cp_reginfo[] = {
392 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
393 * version" bits will read as a reserved value, which should cause
394 * Linux to not try to use the debug hardware.
395 */
396 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
397 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
398 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
399 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
400 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
401 { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
402 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
403 .access = PL1_RW,
404 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
405 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
406 REGINFO_SENTINEL
407 };
408
409 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
410 /* NB: Some of these registers exist in v8 but with more precise
411 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
412 */
413 /* MMU Domain access control / MPU write buffer control */
414 { .name = "DACR", .cp = 15,
415 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
416 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
417 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
418 /* ??? This covers not just the impdef TLB lockdown registers but also
419 * some v7VMSA registers relating to TEX remap, so it is overly broad.
420 */
421 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
422 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
423 /* MMU TLB control. Note that the wildcarding means we cover not just
424 * the unified TLB ops but also the dside/iside/inner-shareable variants.
425 */
426 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
427 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
428 .type = ARM_CP_NO_MIGRATE },
429 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
430 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
431 .type = ARM_CP_NO_MIGRATE },
432 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
433 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
434 .type = ARM_CP_NO_MIGRATE },
435 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
436 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
437 .type = ARM_CP_NO_MIGRATE },
438 /* Cache maintenance ops; some of this space may be overridden later. */
439 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
440 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
441 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
442 REGINFO_SENTINEL
443 };
444
445 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
446 /* Not all pre-v6 cores implemented this WFI, so this is slightly
447 * over-broad.
448 */
449 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
450 .access = PL1_W, .type = ARM_CP_WFI },
451 REGINFO_SENTINEL
452 };
453
454 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
455 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
456 * is UNPREDICTABLE; we choose to NOP as most implementations do).
457 */
458 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
459 .access = PL1_W, .type = ARM_CP_WFI },
460 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
461 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
462 * OMAPCP will override this space.
463 */
464 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
465 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
466 .resetvalue = 0 },
467 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
468 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
469 .resetvalue = 0 },
470 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
471 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
472 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
473 .resetvalue = 0 },
474 REGINFO_SENTINEL
475 };
476
477 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
478 uint64_t value)
479 {
480 uint32_t mask = 0;
481
482 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
483 if (!arm_feature(env, ARM_FEATURE_V8)) {
484 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
485 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
486 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
487 */
488 if (arm_feature(env, ARM_FEATURE_VFP)) {
489 /* VFP coprocessor: cp10 & cp11 [23:20] */
490 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
491
492 if (!arm_feature(env, ARM_FEATURE_NEON)) {
493 /* ASEDIS [31] bit is RAO/WI */
494 value |= (1 << 31);
495 }
496
497 /* VFPv3 and upwards with NEON implement 32 double precision
498 * registers (D0-D31).
499 */
500 if (!arm_feature(env, ARM_FEATURE_NEON) ||
501 !arm_feature(env, ARM_FEATURE_VFP3)) {
502 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
503 value |= (1 << 30);
504 }
505 }
506 value &= mask;
507 }
508 env->cp15.c1_coproc = value;
509 }
510
511 static const ARMCPRegInfo v6_cp_reginfo[] = {
512 /* prefetch by MVA in v6, NOP in v7 */
513 { .name = "MVA_prefetch",
514 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
515 .access = PL1_W, .type = ARM_CP_NOP },
516 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
517 .access = PL0_W, .type = ARM_CP_NOP },
518 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
519 .access = PL0_W, .type = ARM_CP_NOP },
520 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
521 .access = PL0_W, .type = ARM_CP_NOP },
522 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
523 .access = PL1_RW,
524 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),
525 .resetvalue = 0, },
526 /* Watchpoint Fault Address Register : should actually only be present
527 * for 1136, 1176, 11MPCore.
528 */
529 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
530 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
531 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
532 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
533 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
534 .resetvalue = 0, .writefn = cpacr_write },
535 REGINFO_SENTINEL
536 };
537
538 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
539 {
540 /* Performance monitor registers user accessibility is controlled
541 * by PMUSERENR.
542 */
543 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
544 return CP_ACCESS_TRAP;
545 }
546 return CP_ACCESS_OK;
547 }
548
549 #ifndef CONFIG_USER_ONLY
550 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
551 uint64_t value)
552 {
553 /* Don't computer the number of ticks in user mode */
554 uint32_t temp_ticks;
555
556 temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
557 get_ticks_per_sec() / 1000000;
558
559 if (env->cp15.c9_pmcr & PMCRE) {
560 /* If the counter is enabled */
561 if (env->cp15.c9_pmcr & PMCRD) {
562 /* Increment once every 64 processor clock cycles */
563 env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
564 } else {
565 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
566 }
567 }
568
569 if (value & PMCRC) {
570 /* The counter has been reset */
571 env->cp15.c15_ccnt = 0;
572 }
573
574 /* only the DP, X, D and E bits are writable */
575 env->cp15.c9_pmcr &= ~0x39;
576 env->cp15.c9_pmcr |= (value & 0x39);
577
578 if (env->cp15.c9_pmcr & PMCRE) {
579 if (env->cp15.c9_pmcr & PMCRD) {
580 /* Increment once every 64 processor clock cycles */
581 temp_ticks /= 64;
582 }
583 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
584 }
585 }
586
587 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
588 {
589 uint32_t total_ticks;
590
591 if (!(env->cp15.c9_pmcr & PMCRE)) {
592 /* Counter is disabled, do not change value */
593 return env->cp15.c15_ccnt;
594 }
595
596 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
597 get_ticks_per_sec() / 1000000;
598
599 if (env->cp15.c9_pmcr & PMCRD) {
600 /* Increment once every 64 processor clock cycles */
601 total_ticks /= 64;
602 }
603 return total_ticks - env->cp15.c15_ccnt;
604 }
605
606 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
607 uint64_t value)
608 {
609 uint32_t total_ticks;
610
611 if (!(env->cp15.c9_pmcr & PMCRE)) {
612 /* Counter is disabled, set the absolute value */
613 env->cp15.c15_ccnt = value;
614 return;
615 }
616
617 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
618 get_ticks_per_sec() / 1000000;
619
620 if (env->cp15.c9_pmcr & PMCRD) {
621 /* Increment once every 64 processor clock cycles */
622 total_ticks /= 64;
623 }
624 env->cp15.c15_ccnt = total_ticks - value;
625 }
626 #endif
627
628 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
629 uint64_t value)
630 {
631 value &= (1 << 31);
632 env->cp15.c9_pmcnten |= value;
633 }
634
635 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
636 uint64_t value)
637 {
638 value &= (1 << 31);
639 env->cp15.c9_pmcnten &= ~value;
640 }
641
642 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
643 uint64_t value)
644 {
645 env->cp15.c9_pmovsr &= ~value;
646 }
647
648 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
649 uint64_t value)
650 {
651 env->cp15.c9_pmxevtyper = value & 0xff;
652 }
653
654 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
655 uint64_t value)
656 {
657 env->cp15.c9_pmuserenr = value & 1;
658 }
659
660 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
661 uint64_t value)
662 {
663 /* We have no event counters so only the C bit can be changed */
664 value &= (1 << 31);
665 env->cp15.c9_pminten |= value;
666 }
667
668 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
669 uint64_t value)
670 {
671 value &= (1 << 31);
672 env->cp15.c9_pminten &= ~value;
673 }
674
675 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
676 uint64_t value)
677 {
678 /* Note that even though the AArch64 view of this register has bits
679 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
680 * architectural requirements for bits which are RES0 only in some
681 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
682 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
683 */
684 raw_write(env, ri, value & ~0x1FULL);
685 }
686
687 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
688 {
689 ARMCPU *cpu = arm_env_get_cpu(env);
690 return cpu->ccsidr[env->cp15.c0_cssel];
691 }
692
693 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
694 uint64_t value)
695 {
696 env->cp15.c0_cssel = value & 0xf;
697 }
698
699 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
700 {
701 CPUState *cs = ENV_GET_CPU(env);
702 uint64_t ret = 0;
703
704 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
705 ret |= CPSR_I;
706 }
707 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
708 ret |= CPSR_F;
709 }
710 /* External aborts are not possible in QEMU so A bit is always clear */
711 return ret;
712 }
713
714 static const ARMCPRegInfo v7_cp_reginfo[] = {
715 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
716 * debug components
717 */
718 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
719 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
720 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
721 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
722 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
723 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
724 .access = PL1_W, .type = ARM_CP_NOP },
725 /* Performance monitors are implementation defined in v7,
726 * but with an ARM recommended set of registers, which we
727 * follow (although we don't actually implement any counters)
728 *
729 * Performance registers fall into three categories:
730 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
731 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
732 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
733 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
734 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
735 */
736 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
737 .access = PL0_RW, .resetvalue = 0,
738 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
739 .writefn = pmcntenset_write,
740 .accessfn = pmreg_access,
741 .raw_writefn = raw_write },
742 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
743 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
744 .accessfn = pmreg_access,
745 .writefn = pmcntenclr_write,
746 .type = ARM_CP_NO_MIGRATE },
747 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
748 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
749 .accessfn = pmreg_access,
750 .writefn = pmovsr_write,
751 .raw_writefn = raw_write },
752 /* Unimplemented so WI. */
753 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
754 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
755 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
756 * We choose to RAZ/WI.
757 */
758 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
759 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
760 .accessfn = pmreg_access },
761 #ifndef CONFIG_USER_ONLY
762 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
763 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
764 .readfn = pmccntr_read, .writefn = pmccntr_write,
765 .accessfn = pmreg_access },
766 #endif
767 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
768 .access = PL0_RW,
769 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
770 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
771 .raw_writefn = raw_write },
772 /* Unimplemented, RAZ/WI. */
773 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
774 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
775 .accessfn = pmreg_access },
776 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
777 .access = PL0_R | PL1_RW,
778 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
779 .resetvalue = 0,
780 .writefn = pmuserenr_write, .raw_writefn = raw_write },
781 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
782 .access = PL1_RW,
783 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
784 .resetvalue = 0,
785 .writefn = pmintenset_write, .raw_writefn = raw_write },
786 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
787 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
788 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
789 .resetvalue = 0, .writefn = pmintenclr_write, },
790 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
791 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
792 .access = PL1_RW, .writefn = vbar_write,
793 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
794 .resetvalue = 0 },
795 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
796 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
797 .resetvalue = 0, },
798 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
799 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
800 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
801 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
802 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
803 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
804 .writefn = csselr_write, .resetvalue = 0 },
805 /* Auxiliary ID register: this actually has an IMPDEF value but for now
806 * just RAZ for all cores:
807 */
808 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
809 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
810 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
811 /* Auxiliary fault status registers: these also are IMPDEF, and we
812 * choose to RAZ/WI for all cores.
813 */
814 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
815 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
816 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
817 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
818 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
819 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
820 /* MAIR can just read-as-written because we don't implement caches
821 * and so don't need to care about memory attributes.
822 */
823 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
824 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
825 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
826 .resetvalue = 0 },
827 /* For non-long-descriptor page tables these are PRRR and NMRR;
828 * regardless they still act as reads-as-written for QEMU.
829 * The override is necessary because of the overly-broad TLB_LOCKDOWN
830 * definition.
831 */
832 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
833 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
834 .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
835 .resetfn = arm_cp_reset_ignore },
836 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
837 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
838 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
839 .resetfn = arm_cp_reset_ignore },
840 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
841 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
842 .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
843 REGINFO_SENTINEL
844 };
845
846 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
847 uint64_t value)
848 {
849 value &= 1;
850 env->teecr = value;
851 }
852
853 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
854 {
855 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
856 return CP_ACCESS_TRAP;
857 }
858 return CP_ACCESS_OK;
859 }
860
861 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
862 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
863 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
864 .resetvalue = 0,
865 .writefn = teecr_write },
866 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
867 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
868 .accessfn = teehbr_access, .resetvalue = 0 },
869 REGINFO_SENTINEL
870 };
871
872 static const ARMCPRegInfo v6k_cp_reginfo[] = {
873 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
874 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
875 .access = PL0_RW,
876 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
877 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
878 .access = PL0_RW,
879 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
880 .resetfn = arm_cp_reset_ignore },
881 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
882 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
883 .access = PL0_R|PL1_W,
884 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
885 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
886 .access = PL0_R|PL1_W,
887 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
888 .resetfn = arm_cp_reset_ignore },
889 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
890 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
891 .access = PL1_RW,
892 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
893 REGINFO_SENTINEL
894 };
895
896 #ifndef CONFIG_USER_ONLY
897
898 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
899 {
900 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
901 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
902 return CP_ACCESS_TRAP;
903 }
904 return CP_ACCESS_OK;
905 }
906
907 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
908 {
909 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
910 if (arm_current_pl(env) == 0 &&
911 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
912 return CP_ACCESS_TRAP;
913 }
914 return CP_ACCESS_OK;
915 }
916
917 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
918 {
919 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
920 * EL0[PV]TEN is zero.
921 */
922 if (arm_current_pl(env) == 0 &&
923 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
924 return CP_ACCESS_TRAP;
925 }
926 return CP_ACCESS_OK;
927 }
928
929 static CPAccessResult gt_pct_access(CPUARMState *env,
930 const ARMCPRegInfo *ri)
931 {
932 return gt_counter_access(env, GTIMER_PHYS);
933 }
934
935 static CPAccessResult gt_vct_access(CPUARMState *env,
936 const ARMCPRegInfo *ri)
937 {
938 return gt_counter_access(env, GTIMER_VIRT);
939 }
940
941 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
942 {
943 return gt_timer_access(env, GTIMER_PHYS);
944 }
945
946 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
947 {
948 return gt_timer_access(env, GTIMER_VIRT);
949 }
950
951 static uint64_t gt_get_countervalue(CPUARMState *env)
952 {
953 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
954 }
955
956 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
957 {
958 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
959
960 if (gt->ctl & 1) {
961 /* Timer enabled: calculate and set current ISTATUS, irq, and
962 * reset timer to when ISTATUS next has to change
963 */
964 uint64_t count = gt_get_countervalue(&cpu->env);
965 /* Note that this must be unsigned 64 bit arithmetic: */
966 int istatus = count >= gt->cval;
967 uint64_t nexttick;
968
969 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
970 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
971 (istatus && !(gt->ctl & 2)));
972 if (istatus) {
973 /* Next transition is when count rolls back over to zero */
974 nexttick = UINT64_MAX;
975 } else {
976 /* Next transition is when we hit cval */
977 nexttick = gt->cval;
978 }
979 /* Note that the desired next expiry time might be beyond the
980 * signed-64-bit range of a QEMUTimer -- in this case we just
981 * set the timer for as far in the future as possible. When the
982 * timer expires we will reset the timer for any remaining period.
983 */
984 if (nexttick > INT64_MAX / GTIMER_SCALE) {
985 nexttick = INT64_MAX / GTIMER_SCALE;
986 }
987 timer_mod(cpu->gt_timer[timeridx], nexttick);
988 } else {
989 /* Timer disabled: ISTATUS and timer output always clear */
990 gt->ctl &= ~4;
991 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
992 timer_del(cpu->gt_timer[timeridx]);
993 }
994 }
995
996 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
997 {
998 ARMCPU *cpu = arm_env_get_cpu(env);
999 int timeridx = ri->opc1 & 1;
1000
1001 timer_del(cpu->gt_timer[timeridx]);
1002 }
1003
1004 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1005 {
1006 return gt_get_countervalue(env);
1007 }
1008
1009 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1010 uint64_t value)
1011 {
1012 int timeridx = ri->opc1 & 1;
1013
1014 env->cp15.c14_timer[timeridx].cval = value;
1015 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1016 }
1017
1018 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1019 {
1020 int timeridx = ri->crm & 1;
1021
1022 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1023 gt_get_countervalue(env));
1024 }
1025
1026 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1027 uint64_t value)
1028 {
1029 int timeridx = ri->crm & 1;
1030
1031 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1032 + sextract64(value, 0, 32);
1033 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1034 }
1035
1036 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1037 uint64_t value)
1038 {
1039 ARMCPU *cpu = arm_env_get_cpu(env);
1040 int timeridx = ri->crm & 1;
1041 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1042
1043 env->cp15.c14_timer[timeridx].ctl = value & 3;
1044 if ((oldval ^ value) & 1) {
1045 /* Enable toggled */
1046 gt_recalc_timer(cpu, timeridx);
1047 } else if ((oldval & value) & 2) {
1048 /* IMASK toggled: don't need to recalculate,
1049 * just set the interrupt line based on ISTATUS
1050 */
1051 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1052 (oldval & 4) && (value & 2));
1053 }
1054 }
1055
1056 void arm_gt_ptimer_cb(void *opaque)
1057 {
1058 ARMCPU *cpu = opaque;
1059
1060 gt_recalc_timer(cpu, GTIMER_PHYS);
1061 }
1062
1063 void arm_gt_vtimer_cb(void *opaque)
1064 {
1065 ARMCPU *cpu = opaque;
1066
1067 gt_recalc_timer(cpu, GTIMER_VIRT);
1068 }
1069
1070 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1071 /* Note that CNTFRQ is purely reads-as-written for the benefit
1072 * of software; writing it doesn't actually change the timer frequency.
1073 * Our reset value matches the fixed frequency we implement the timer at.
1074 */
1075 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1076 .type = ARM_CP_NO_MIGRATE,
1077 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1078 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1079 .resetfn = arm_cp_reset_ignore,
1080 },
1081 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1082 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1083 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1084 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1085 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1086 },
1087 /* overall control: mostly access permissions */
1088 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1089 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1090 .access = PL1_RW,
1091 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1092 .resetvalue = 0,
1093 },
1094 /* per-timer control */
1095 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1096 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1097 .accessfn = gt_ptimer_access,
1098 .fieldoffset = offsetoflow32(CPUARMState,
1099 cp15.c14_timer[GTIMER_PHYS].ctl),
1100 .resetfn = arm_cp_reset_ignore,
1101 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1102 },
1103 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1104 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1105 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1106 .accessfn = gt_ptimer_access,
1107 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1108 .resetvalue = 0,
1109 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1110 },
1111 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1112 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1113 .accessfn = gt_vtimer_access,
1114 .fieldoffset = offsetoflow32(CPUARMState,
1115 cp15.c14_timer[GTIMER_VIRT].ctl),
1116 .resetfn = arm_cp_reset_ignore,
1117 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1118 },
1119 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1120 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1121 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1122 .accessfn = gt_vtimer_access,
1123 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1124 .resetvalue = 0,
1125 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1126 },
1127 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1128 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1129 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1130 .accessfn = gt_ptimer_access,
1131 .readfn = gt_tval_read, .writefn = gt_tval_write,
1132 },
1133 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1134 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1135 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1136 .readfn = gt_tval_read, .writefn = gt_tval_write,
1137 },
1138 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1139 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1140 .accessfn = gt_vtimer_access,
1141 .readfn = gt_tval_read, .writefn = gt_tval_write,
1142 },
1143 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1144 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1145 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1146 .readfn = gt_tval_read, .writefn = gt_tval_write,
1147 },
1148 /* The counter itself */
1149 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1150 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1151 .accessfn = gt_pct_access,
1152 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1153 },
1154 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1155 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1156 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1157 .accessfn = gt_pct_access,
1158 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1159 },
1160 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1161 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1162 .accessfn = gt_vct_access,
1163 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1164 },
1165 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1166 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1167 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1168 .accessfn = gt_vct_access,
1169 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1170 },
1171 /* Comparison value, indicating when the timer goes off */
1172 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1173 .access = PL1_RW | PL0_R,
1174 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1175 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1176 .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1177 .writefn = gt_cval_write, .raw_writefn = raw_write,
1178 },
1179 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1180 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1181 .access = PL1_RW | PL0_R,
1182 .type = ARM_CP_IO,
1183 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1184 .resetvalue = 0, .accessfn = gt_vtimer_access,
1185 .writefn = gt_cval_write, .raw_writefn = raw_write,
1186 },
1187 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1188 .access = PL1_RW | PL0_R,
1189 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1190 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1191 .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1192 .writefn = gt_cval_write, .raw_writefn = raw_write,
1193 },
1194 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1195 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1196 .access = PL1_RW | PL0_R,
1197 .type = ARM_CP_IO,
1198 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1199 .resetvalue = 0, .accessfn = gt_vtimer_access,
1200 .writefn = gt_cval_write, .raw_writefn = raw_write,
1201 },
1202 REGINFO_SENTINEL
1203 };
1204
1205 #else
1206 /* In user-mode none of the generic timer registers are accessible,
1207 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1208 * so instead just don't register any of them.
1209 */
1210 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1211 REGINFO_SENTINEL
1212 };
1213
1214 #endif
1215
1216 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1217 {
1218 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1219 env->cp15.par_el1 = value;
1220 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1221 env->cp15.par_el1 = value & 0xfffff6ff;
1222 } else {
1223 env->cp15.par_el1 = value & 0xfffff1ff;
1224 }
1225 }
1226
1227 #ifndef CONFIG_USER_ONLY
1228 /* get_phys_addr() isn't present for user-mode-only targets */
1229
1230 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1231 {
1232 if (ri->opc2 & 4) {
1233 /* Other states are only available with TrustZone; in
1234 * a non-TZ implementation these registers don't exist
1235 * at all, which is an Uncategorized trap. This underdecoding
1236 * is safe because the reginfo is NO_MIGRATE.
1237 */
1238 return CP_ACCESS_TRAP_UNCATEGORIZED;
1239 }
1240 return CP_ACCESS_OK;
1241 }
1242
1243 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1244 {
1245 hwaddr phys_addr;
1246 target_ulong page_size;
1247 int prot;
1248 int ret, is_user = ri->opc2 & 2;
1249 int access_type = ri->opc2 & 1;
1250
1251 ret = get_phys_addr(env, value, access_type, is_user,
1252 &phys_addr, &prot, &page_size);
1253 if (extended_addresses_enabled(env)) {
1254 /* ret is a DFSR/IFSR value for the long descriptor
1255 * translation table format, but with WnR always clear.
1256 * Convert it to a 64-bit PAR.
1257 */
1258 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1259 if (ret == 0) {
1260 par64 |= phys_addr & ~0xfffULL;
1261 /* We don't set the ATTR or SH fields in the PAR. */
1262 } else {
1263 par64 |= 1; /* F */
1264 par64 |= (ret & 0x3f) << 1; /* FS */
1265 /* Note that S2WLK and FSTAGE are always zero, because we don't
1266 * implement virtualization and therefore there can't be a stage 2
1267 * fault.
1268 */
1269 }
1270 env->cp15.par_el1 = par64;
1271 } else {
1272 /* ret is a DFSR/IFSR value for the short descriptor
1273 * translation table format (with WnR always clear).
1274 * Convert it to a 32-bit PAR.
1275 */
1276 if (ret == 0) {
1277 /* We do not set any attribute bits in the PAR */
1278 if (page_size == (1 << 24)
1279 && arm_feature(env, ARM_FEATURE_V7)) {
1280 env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
1281 } else {
1282 env->cp15.par_el1 = phys_addr & 0xfffff000;
1283 }
1284 } else {
1285 env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
1286 ((ret & (1 << 12)) >> 6) |
1287 ((ret & 0xf) << 1) | 1;
1288 }
1289 }
1290 }
1291 #endif
1292
1293 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1294 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1295 .access = PL1_RW, .resetvalue = 0,
1296 .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
1297 .writefn = par_write },
1298 #ifndef CONFIG_USER_ONLY
1299 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1300 .access = PL1_W, .accessfn = ats_access,
1301 .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1302 #endif
1303 REGINFO_SENTINEL
1304 };
1305
1306 /* Return basic MPU access permission bits. */
1307 static uint32_t simple_mpu_ap_bits(uint32_t val)
1308 {
1309 uint32_t ret;
1310 uint32_t mask;
1311 int i;
1312 ret = 0;
1313 mask = 3;
1314 for (i = 0; i < 16; i += 2) {
1315 ret |= (val >> i) & mask;
1316 mask <<= 2;
1317 }
1318 return ret;
1319 }
1320
1321 /* Pad basic MPU access permission bits to extended format. */
1322 static uint32_t extended_mpu_ap_bits(uint32_t val)
1323 {
1324 uint32_t ret;
1325 uint32_t mask;
1326 int i;
1327 ret = 0;
1328 mask = 3;
1329 for (i = 0; i < 16; i += 2) {
1330 ret |= (val & mask) << i;
1331 mask <<= 2;
1332 }
1333 return ret;
1334 }
1335
1336 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1337 uint64_t value)
1338 {
1339 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1340 }
1341
1342 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1343 {
1344 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1345 }
1346
1347 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1348 uint64_t value)
1349 {
1350 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1351 }
1352
1353 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1354 {
1355 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1356 }
1357
1358 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1359 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1360 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1361 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1362 .resetvalue = 0,
1363 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1364 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1365 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1366 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1367 .resetvalue = 0,
1368 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1369 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1370 .access = PL1_RW,
1371 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1372 .resetvalue = 0, },
1373 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1374 .access = PL1_RW,
1375 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1376 .resetvalue = 0, },
1377 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1378 .access = PL1_RW,
1379 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1380 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1381 .access = PL1_RW,
1382 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1383 /* Protection region base and size registers */
1384 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1385 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1386 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1387 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1388 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1389 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1390 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1391 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1392 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1393 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1394 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1395 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1396 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1397 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1398 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1399 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1400 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1401 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1402 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1403 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1404 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1405 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1406 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1407 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1408 REGINFO_SENTINEL
1409 };
1410
1411 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1412 uint64_t value)
1413 {
1414 int maskshift = extract32(value, 0, 3);
1415
1416 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1417 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1418 } else {
1419 value &= 7;
1420 }
1421 /* Note that we always calculate c2_mask and c2_base_mask, but
1422 * they are only used for short-descriptor tables (ie if EAE is 0);
1423 * for long-descriptor tables the TTBCR fields are used differently
1424 * and the c2_mask and c2_base_mask values are meaningless.
1425 */
1426 env->cp15.c2_control = value;
1427 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1428 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1429 }
1430
1431 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1432 uint64_t value)
1433 {
1434 ARMCPU *cpu = arm_env_get_cpu(env);
1435
1436 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1437 /* With LPAE the TTBCR could result in a change of ASID
1438 * via the TTBCR.A1 bit, so do a TLB flush.
1439 */
1440 tlb_flush(CPU(cpu), 1);
1441 }
1442 vmsa_ttbcr_raw_write(env, ri, value);
1443 }
1444
1445 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1446 {
1447 env->cp15.c2_base_mask = 0xffffc000u;
1448 env->cp15.c2_control = 0;
1449 env->cp15.c2_mask = 0;
1450 }
1451
1452 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1453 uint64_t value)
1454 {
1455 ARMCPU *cpu = arm_env_get_cpu(env);
1456
1457 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1458 tlb_flush(CPU(cpu), 1);
1459 env->cp15.c2_control = value;
1460 }
1461
1462 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1463 uint64_t value)
1464 {
1465 /* 64 bit accesses to the TTBRs can change the ASID and so we
1466 * must flush the TLB.
1467 */
1468 if (cpreg_field_is_64bit(ri)) {
1469 ARMCPU *cpu = arm_env_get_cpu(env);
1470
1471 tlb_flush(CPU(cpu), 1);
1472 }
1473 raw_write(env, ri, value);
1474 }
1475
1476 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1477 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1478 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1479 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1480 .resetfn = arm_cp_reset_ignore, },
1481 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1482 .access = PL1_RW,
1483 .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1484 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1485 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1486 .access = PL1_RW,
1487 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1488 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1489 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1490 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1491 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1492 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1493 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1494 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1495 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1496 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1497 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1498 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1499 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1500 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1501 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1502 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1503 .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1504 .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1505 /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1506 { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1507 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1508 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el1),
1509 .resetvalue = 0, },
1510 REGINFO_SENTINEL
1511 };
1512
1513 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1514 uint64_t value)
1515 {
1516 env->cp15.c15_ticonfig = value & 0xe7;
1517 /* The OS_TYPE bit in this register changes the reported CPUID! */
1518 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1519 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1520 }
1521
1522 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1523 uint64_t value)
1524 {
1525 env->cp15.c15_threadid = value & 0xffff;
1526 }
1527
1528 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1529 uint64_t value)
1530 {
1531 /* Wait-for-interrupt (deprecated) */
1532 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1533 }
1534
1535 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1536 uint64_t value)
1537 {
1538 /* On OMAP there are registers indicating the max/min index of dcache lines
1539 * containing a dirty line; cache flush operations have to reset these.
1540 */
1541 env->cp15.c15_i_max = 0x000;
1542 env->cp15.c15_i_min = 0xff0;
1543 }
1544
1545 static const ARMCPRegInfo omap_cp_reginfo[] = {
1546 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1547 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1548 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1549 .resetvalue = 0, },
1550 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1551 .access = PL1_RW, .type = ARM_CP_NOP },
1552 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1553 .access = PL1_RW,
1554 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1555 .writefn = omap_ticonfig_write },
1556 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1557 .access = PL1_RW,
1558 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1559 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1560 .access = PL1_RW, .resetvalue = 0xff0,
1561 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1562 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1563 .access = PL1_RW,
1564 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1565 .writefn = omap_threadid_write },
1566 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1567 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1568 .type = ARM_CP_NO_MIGRATE,
1569 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1570 /* TODO: Peripheral port remap register:
1571 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1572 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1573 * when MMU is off.
1574 */
1575 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1576 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1577 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1578 .writefn = omap_cachemaint_write },
1579 { .name = "C9", .cp = 15, .crn = 9,
1580 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1581 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1582 REGINFO_SENTINEL
1583 };
1584
1585 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1586 uint64_t value)
1587 {
1588 value &= 0x3fff;
1589 if (env->cp15.c15_cpar != value) {
1590 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1591 tb_flush(env);
1592 env->cp15.c15_cpar = value;
1593 }
1594 }
1595
1596 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1597 { .name = "XSCALE_CPAR",
1598 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1599 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1600 .writefn = xscale_cpar_write, },
1601 { .name = "XSCALE_AUXCR",
1602 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1603 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1604 .resetvalue = 0, },
1605 /* XScale specific cache-lockdown: since we have no cache we NOP these
1606 * and hope the guest does not really rely on cache behaviour.
1607 */
1608 { .name = "XSCALE_LOCK_ICACHE_LINE",
1609 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1610 .access = PL1_W, .type = ARM_CP_NOP },
1611 { .name = "XSCALE_UNLOCK_ICACHE",
1612 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1613 .access = PL1_W, .type = ARM_CP_NOP },
1614 { .name = "XSCALE_DCACHE_LOCK",
1615 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1616 .access = PL1_RW, .type = ARM_CP_NOP },
1617 { .name = "XSCALE_UNLOCK_DCACHE",
1618 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1619 .access = PL1_W, .type = ARM_CP_NOP },
1620 REGINFO_SENTINEL
1621 };
1622
1623 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1624 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1625 * implementation of this implementation-defined space.
1626 * Ideally this should eventually disappear in favour of actually
1627 * implementing the correct behaviour for all cores.
1628 */
1629 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1630 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1631 .access = PL1_RW,
1632 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1633 .resetvalue = 0 },
1634 REGINFO_SENTINEL
1635 };
1636
1637 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1638 /* Cache status: RAZ because we have no cache so it's always clean */
1639 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1640 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1641 .resetvalue = 0 },
1642 REGINFO_SENTINEL
1643 };
1644
1645 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1646 /* We never have a a block transfer operation in progress */
1647 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1648 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1649 .resetvalue = 0 },
1650 /* The cache ops themselves: these all NOP for QEMU */
1651 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1652 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1653 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1654 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1655 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1656 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1657 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1658 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1659 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1660 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1661 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1662 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1663 REGINFO_SENTINEL
1664 };
1665
1666 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1667 /* The cache test-and-clean instructions always return (1 << 30)
1668 * to indicate that there are no dirty cache lines.
1669 */
1670 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1671 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1672 .resetvalue = (1 << 30) },
1673 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1674 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1675 .resetvalue = (1 << 30) },
1676 REGINFO_SENTINEL
1677 };
1678
1679 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1680 /* Ignore ReadBuffer accesses */
1681 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1682 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1683 .access = PL1_RW, .resetvalue = 0,
1684 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1685 REGINFO_SENTINEL
1686 };
1687
1688 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1689 {
1690 CPUState *cs = CPU(arm_env_get_cpu(env));
1691 uint32_t mpidr = cs->cpu_index;
1692 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1693 * in later ARM ARM versions), or any of the higher affinity level fields,
1694 * so these bits always RAZ.
1695 */
1696 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1697 mpidr |= (1U << 31);
1698 /* Cores which are uniprocessor (non-coherent)
1699 * but still implement the MP extensions set
1700 * bit 30. (For instance, A9UP.) However we do
1701 * not currently model any of those cores.
1702 */
1703 }
1704 return mpidr;
1705 }
1706
1707 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1708 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1709 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1710 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1711 REGINFO_SENTINEL
1712 };
1713
1714 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1715 /* NOP AMAIR0/1: the override is because these clash with the rather
1716 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1717 */
1718 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1719 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1720 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1721 .resetvalue = 0 },
1722 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1723 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1724 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1725 .resetvalue = 0 },
1726 /* 64 bit access versions of the (dummy) debug registers */
1727 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1728 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1729 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1730 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1731 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1732 .access = PL1_RW, .type = ARM_CP_64BIT,
1733 .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
1734 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1735 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1736 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1737 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1738 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1739 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1740 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1741 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1742 REGINFO_SENTINEL
1743 };
1744
1745 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1746 {
1747 return vfp_get_fpcr(env);
1748 }
1749
1750 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1751 uint64_t value)
1752 {
1753 vfp_set_fpcr(env, value);
1754 }
1755
1756 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1757 {
1758 return vfp_get_fpsr(env);
1759 }
1760
1761 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1762 uint64_t value)
1763 {
1764 vfp_set_fpsr(env, value);
1765 }
1766
1767 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1768 {
1769 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1770 return CP_ACCESS_TRAP;
1771 }
1772 return CP_ACCESS_OK;
1773 }
1774
1775 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1776 uint64_t value)
1777 {
1778 env->daif = value & PSTATE_DAIF;
1779 }
1780
1781 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1782 const ARMCPRegInfo *ri)
1783 {
1784 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1785 * SCTLR_EL1.UCI is set.
1786 */
1787 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1788 return CP_ACCESS_TRAP;
1789 }
1790 return CP_ACCESS_OK;
1791 }
1792
1793 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1794 uint64_t value)
1795 {
1796 /* Invalidate by VA (AArch64 version) */
1797 ARMCPU *cpu = arm_env_get_cpu(env);
1798 uint64_t pageaddr = value << 12;
1799 tlb_flush_page(CPU(cpu), pageaddr);
1800 }
1801
1802 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1803 uint64_t value)
1804 {
1805 /* Invalidate by VA, all ASIDs (AArch64 version) */
1806 ARMCPU *cpu = arm_env_get_cpu(env);
1807 uint64_t pageaddr = value << 12;
1808 tlb_flush_page(CPU(cpu), pageaddr);
1809 }
1810
1811 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1812 uint64_t value)
1813 {
1814 /* Invalidate by ASID (AArch64 version) */
1815 ARMCPU *cpu = arm_env_get_cpu(env);
1816 int asid = extract64(value, 48, 16);
1817 tlb_flush(CPU(cpu), asid == 0);
1818 }
1819
1820 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
1821 {
1822 /* We don't implement EL2, so the only control on DC ZVA is the
1823 * bit in the SCTLR which can prohibit access for EL0.
1824 */
1825 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
1826 return CP_ACCESS_TRAP;
1827 }
1828 return CP_ACCESS_OK;
1829 }
1830
1831 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
1832 {
1833 ARMCPU *cpu = arm_env_get_cpu(env);
1834 int dzp_bit = 1 << 4;
1835
1836 /* DZP indicates whether DC ZVA access is allowed */
1837 if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
1838 dzp_bit = 0;
1839 }
1840 return cpu->dcz_blocksize | dzp_bit;
1841 }
1842
1843 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1844 {
1845 if (!env->pstate & PSTATE_SP) {
1846 /* Access to SP_EL0 is undefined if it's being used as
1847 * the stack pointer.
1848 */
1849 return CP_ACCESS_TRAP_UNCATEGORIZED;
1850 }
1851 return CP_ACCESS_OK;
1852 }
1853
1854 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
1855 {
1856 return env->pstate & PSTATE_SP;
1857 }
1858
1859 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
1860 {
1861 update_spsel(env, val);
1862 }
1863
1864 static const ARMCPRegInfo v8_cp_reginfo[] = {
1865 /* Minimal set of EL0-visible registers. This will need to be expanded
1866 * significantly for system emulation of AArch64 CPUs.
1867 */
1868 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1869 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1870 .access = PL0_RW, .type = ARM_CP_NZCV },
1871 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
1872 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
1873 .type = ARM_CP_NO_MIGRATE,
1874 .access = PL0_RW, .accessfn = aa64_daif_access,
1875 .fieldoffset = offsetof(CPUARMState, daif),
1876 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1877 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1878 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1879 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1880 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1881 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1882 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1883 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1884 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1885 .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
1886 .readfn = aa64_dczid_read },
1887 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
1888 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
1889 .access = PL0_W, .type = ARM_CP_DC_ZVA,
1890 #ifndef CONFIG_USER_ONLY
1891 /* Avoid overhead of an access check that always passes in user-mode */
1892 .accessfn = aa64_zva_access,
1893 #endif
1894 },
1895 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1896 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1897 .access = PL1_R, .type = ARM_CP_CURRENTEL },
1898 /* Cache ops: all NOPs since we don't emulate caches */
1899 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1900 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1901 .access = PL1_W, .type = ARM_CP_NOP },
1902 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1903 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1904 .access = PL1_W, .type = ARM_CP_NOP },
1905 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1906 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1907 .access = PL0_W, .type = ARM_CP_NOP,
1908 .accessfn = aa64_cacheop_access },
1909 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1910 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1911 .access = PL1_W, .type = ARM_CP_NOP },
1912 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1913 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1914 .access = PL1_W, .type = ARM_CP_NOP },
1915 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1916 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1917 .access = PL0_W, .type = ARM_CP_NOP,
1918 .accessfn = aa64_cacheop_access },
1919 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1920 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1921 .access = PL1_W, .type = ARM_CP_NOP },
1922 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1923 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1924 .access = PL0_W, .type = ARM_CP_NOP,
1925 .accessfn = aa64_cacheop_access },
1926 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1927 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1928 .access = PL0_W, .type = ARM_CP_NOP,
1929 .accessfn = aa64_cacheop_access },
1930 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1931 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1932 .access = PL1_W, .type = ARM_CP_NOP },
1933 /* TLBI operations */
1934 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1935 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1936 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1937 .writefn = tlbiall_write },
1938 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1939 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1940 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1941 .writefn = tlbi_aa64_va_write },
1942 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1943 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1944 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1945 .writefn = tlbi_aa64_asid_write },
1946 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1947 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1948 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1949 .writefn = tlbi_aa64_vaa_write },
1950 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
1951 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1952 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1953 .writefn = tlbi_aa64_va_write },
1954 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
1955 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1956 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1957 .writefn = tlbi_aa64_vaa_write },
1958 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
1959 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1960 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1961 .writefn = tlbiall_write },
1962 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
1963 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1964 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1965 .writefn = tlbi_aa64_va_write },
1966 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
1967 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1968 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1969 .writefn = tlbi_aa64_asid_write },
1970 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
1971 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1972 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1973 .writefn = tlbi_aa64_vaa_write },
1974 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
1975 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
1976 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1977 .writefn = tlbi_aa64_va_write },
1978 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
1979 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
1980 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1981 .writefn = tlbi_aa64_vaa_write },
1982 #ifndef CONFIG_USER_ONLY
1983 /* 64 bit address translation operations */
1984 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
1985 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
1986 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1987 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
1988 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
1989 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1990 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
1991 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
1992 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1993 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
1994 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
1995 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1996 #endif
1997 /* 32 bit TLB invalidates, Inner Shareable */
1998 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1999 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2000 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2001 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2002 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2003 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2004 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2005 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2006 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2007 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2008 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2009 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2010 /* 32 bit ITLB invalidates */
2011 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
2012 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2013 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
2014 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2015 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
2016 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2017 /* 32 bit DTLB invalidates */
2018 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
2019 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2020 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
2021 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2022 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
2023 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2024 /* 32 bit TLB invalidates */
2025 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2026 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2027 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2028 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2029 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2030 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2031 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2032 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2033 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2034 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2035 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2036 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2037 /* 32 bit cache operations */
2038 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2039 .type = ARM_CP_NOP, .access = PL1_W },
2040 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2041 .type = ARM_CP_NOP, .access = PL1_W },
2042 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2043 .type = ARM_CP_NOP, .access = PL1_W },
2044 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2045 .type = ARM_CP_NOP, .access = PL1_W },
2046 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2047 .type = ARM_CP_NOP, .access = PL1_W },
2048 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2049 .type = ARM_CP_NOP, .access = PL1_W },
2050 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2051 .type = ARM_CP_NOP, .access = PL1_W },
2052 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2053 .type = ARM_CP_NOP, .access = PL1_W },
2054 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2055 .type = ARM_CP_NOP, .access = PL1_W },
2056 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2057 .type = ARM_CP_NOP, .access = PL1_W },
2058 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2059 .type = ARM_CP_NOP, .access = PL1_W },
2060 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2061 .type = ARM_CP_NOP, .access = PL1_W },
2062 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2063 .type = ARM_CP_NOP, .access = PL1_W },
2064 /* MMU Domain access control / MPU write buffer control */
2065 { .name = "DACR", .cp = 15,
2066 .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2067 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
2068 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
2069 /* Dummy implementation of monitor debug system control register:
2070 * we don't support debug.
2071 */
2072 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
2073 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2074 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2075 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2076 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
2077 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2078 .access = PL1_W, .type = ARM_CP_NOP },
2079 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2080 .type = ARM_CP_NO_MIGRATE,
2081 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2082 .access = PL1_RW,
2083 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2084 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2085 .type = ARM_CP_NO_MIGRATE,
2086 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2087 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2088 /* We rely on the access checks not allowing the guest to write to the
2089 * state field when SPSel indicates that it's being used as the stack
2090 * pointer.
2091 */
2092 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2093 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2094 .access = PL1_RW, .accessfn = sp_el0_access,
2095 .type = ARM_CP_NO_MIGRATE,
2096 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2097 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2098 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2099 .type = ARM_CP_NO_MIGRATE,
2100 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2101 REGINFO_SENTINEL
2102 };
2103
2104 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
2105 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2106 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2107 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2108 .access = PL2_RW,
2109 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2110 REGINFO_SENTINEL
2111 };
2112
2113 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2114 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2115 .type = ARM_CP_NO_MIGRATE,
2116 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2117 .access = PL2_RW,
2118 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2119 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2120 .type = ARM_CP_NO_MIGRATE,
2121 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2122 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2123 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2124 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2125 .access = PL2_RW, .writefn = vbar_write,
2126 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2127 .resetvalue = 0 },
2128 REGINFO_SENTINEL
2129 };
2130
2131 static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
2132 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2133 .type = ARM_CP_NO_MIGRATE,
2134 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2135 .access = PL3_RW,
2136 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2137 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2138 .type = ARM_CP_NO_MIGRATE,
2139 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2140 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2141 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2142 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2143 .access = PL3_RW, .writefn = vbar_write,
2144 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2145 .resetvalue = 0 },
2146 REGINFO_SENTINEL
2147 };
2148
2149 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2150 uint64_t value)
2151 {
2152 ARMCPU *cpu = arm_env_get_cpu(env);
2153
2154 if (env->cp15.c1_sys == value) {
2155 /* Skip the TLB flush if nothing actually changed; Linux likes
2156 * to do a lot of pointless SCTLR writes.
2157 */
2158 return;
2159 }
2160
2161 env->cp15.c1_sys = value;
2162 /* ??? Lots of these bits are not implemented. */
2163 /* This may enable/disable the MMU, so do a TLB flush. */
2164 tlb_flush(CPU(cpu), 1);
2165 }
2166
2167 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2168 {
2169 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2170 * but the AArch32 CTR has its own reginfo struct)
2171 */
2172 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
2173 return CP_ACCESS_TRAP;
2174 }
2175 return CP_ACCESS_OK;
2176 }
2177
2178 static void define_aarch64_debug_regs(ARMCPU *cpu)
2179 {
2180 /* Define breakpoint and watchpoint registers. These do nothing
2181 * but read as written, for now.
2182 */
2183 int i;
2184
2185 for (i = 0; i < 16; i++) {
2186 ARMCPRegInfo dbgregs[] = {
2187 { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
2188 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2189 .access = PL1_RW,
2190 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
2191 { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
2192 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2193 .access = PL1_RW,
2194 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
2195 { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
2196 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2197 .access = PL1_RW,
2198 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
2199 { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
2200 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2201 .access = PL1_RW,
2202 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
2203 REGINFO_SENTINEL
2204 };
2205 define_arm_cp_regs(cpu, dbgregs);
2206 }
2207 }
2208
2209 void register_cp_regs_for_features(ARMCPU *cpu)
2210 {
2211 /* Register all the coprocessor registers based on feature bits */
2212 CPUARMState *env = &cpu->env;
2213 if (arm_feature(env, ARM_FEATURE_M)) {
2214 /* M profile has no coprocessor registers */
2215 return;
2216 }
2217
2218 define_arm_cp_regs(cpu, cp_reginfo);
2219 if (!arm_feature(env, ARM_FEATURE_V8)) {
2220 /* Must go early as it is full of wildcards that may be
2221 * overridden by later definitions.
2222 */
2223 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2224 }
2225
2226 if (arm_feature(env, ARM_FEATURE_V6)) {
2227 /* The ID registers all have impdef reset values */
2228 ARMCPRegInfo v6_idregs[] = {
2229 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2230 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2231 .access = PL1_R, .type = ARM_CP_CONST,
2232 .resetvalue = cpu->id_pfr0 },
2233 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2234 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2235 .access = PL1_R, .type = ARM_CP_CONST,
2236 .resetvalue = cpu->id_pfr1 },
2237 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2238 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2239 .access = PL1_R, .type = ARM_CP_CONST,
2240 .resetvalue = cpu->id_dfr0 },
2241 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2242 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2243 .access = PL1_R, .type = ARM_CP_CONST,
2244 .resetvalue = cpu->id_afr0 },
2245 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2246 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2247 .access = PL1_R, .type = ARM_CP_CONST,
2248 .resetvalue = cpu->id_mmfr0 },
2249 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2250 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2251 .access = PL1_R, .type = ARM_CP_CONST,
2252 .resetvalue = cpu->id_mmfr1 },
2253 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2254 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2255 .access = PL1_R, .type = ARM_CP_CONST,
2256 .resetvalue = cpu->id_mmfr2 },
2257 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2258 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2259 .access = PL1_R, .type = ARM_CP_CONST,
2260 .resetvalue = cpu->id_mmfr3 },
2261 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2262 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2263 .access = PL1_R, .type = ARM_CP_CONST,
2264 .resetvalue = cpu->id_isar0 },
2265 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2266 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2267 .access = PL1_R, .type = ARM_CP_CONST,
2268 .resetvalue = cpu->id_isar1 },
2269 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2270 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2271 .access = PL1_R, .type = ARM_CP_CONST,
2272 .resetvalue = cpu->id_isar2 },
2273 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2274 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2275 .access = PL1_R, .type = ARM_CP_CONST,
2276 .resetvalue = cpu->id_isar3 },
2277 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2278 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2279 .access = PL1_R, .type = ARM_CP_CONST,
2280 .resetvalue = cpu->id_isar4 },
2281 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2282 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2283 .access = PL1_R, .type = ARM_CP_CONST,
2284 .resetvalue = cpu->id_isar5 },
2285 /* 6..7 are as yet unallocated and must RAZ */
2286 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2287 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2288 .resetvalue = 0 },
2289 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2290 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2291 .resetvalue = 0 },
2292 REGINFO_SENTINEL
2293 };
2294 define_arm_cp_regs(cpu, v6_idregs);
2295 define_arm_cp_regs(cpu, v6_cp_reginfo);
2296 } else {
2297 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2298 }
2299 if (arm_feature(env, ARM_FEATURE_V6K)) {
2300 define_arm_cp_regs(cpu, v6k_cp_reginfo);
2301 }
2302 if (arm_feature(env, ARM_FEATURE_V7)) {
2303 /* v7 performance monitor control register: same implementor
2304 * field as main ID register, and we implement only the cycle
2305 * count register.
2306 */
2307 #ifndef CONFIG_USER_ONLY
2308 ARMCPRegInfo pmcr = {
2309 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2310 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
2311 .type = ARM_CP_IO,
2312 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2313 .accessfn = pmreg_access, .writefn = pmcr_write,
2314 .raw_writefn = raw_write,
2315 };
2316 define_one_arm_cp_reg(cpu, &pmcr);
2317 #endif
2318 ARMCPRegInfo clidr = {
2319 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2320 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2321 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2322 };
2323 define_one_arm_cp_reg(cpu, &clidr);
2324 define_arm_cp_regs(cpu, v7_cp_reginfo);
2325 } else {
2326 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2327 }
2328 if (arm_feature(env, ARM_FEATURE_V8)) {
2329 /* AArch64 ID registers, which all have impdef reset values */
2330 ARMCPRegInfo v8_idregs[] = {
2331 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2332 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2333 .access = PL1_R, .type = ARM_CP_CONST,
2334 .resetvalue = cpu->id_aa64pfr0 },
2335 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2336 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2337 .access = PL1_R, .type = ARM_CP_CONST,
2338 .resetvalue = cpu->id_aa64pfr1},
2339 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2340 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2341 .access = PL1_R, .type = ARM_CP_CONST,
2342 /* We mask out the PMUVer field, beacuse we don't currently
2343 * implement the PMU. Not advertising it prevents the guest
2344 * from trying to use it and getting UNDEFs on registers we
2345 * don't implement.
2346 */
2347 .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
2348 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2349 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2350 .access = PL1_R, .type = ARM_CP_CONST,
2351 .resetvalue = cpu->id_aa64dfr1 },
2352 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2353 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2354 .access = PL1_R, .type = ARM_CP_CONST,
2355 .resetvalue = cpu->id_aa64afr0 },
2356 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2357 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2358 .access = PL1_R, .type = ARM_CP_CONST,
2359 .resetvalue = cpu->id_aa64afr1 },
2360 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2361 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2362 .access = PL1_R, .type = ARM_CP_CONST,
2363 .resetvalue = cpu->id_aa64isar0 },
2364 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2365 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2366 .access = PL1_R, .type = ARM_CP_CONST,
2367 .resetvalue = cpu->id_aa64isar1 },
2368 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2369 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2370 .access = PL1_R, .type = ARM_CP_CONST,
2371 .resetvalue = cpu->id_aa64mmfr0 },
2372 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2373 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2374 .access = PL1_R, .type = ARM_CP_CONST,
2375 .resetvalue = cpu->id_aa64mmfr1 },
2376 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
2377 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
2378 .access = PL1_R, .type = ARM_CP_CONST,
2379 .resetvalue = cpu->mvfr0 },
2380 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
2381 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
2382 .access = PL1_R, .type = ARM_CP_CONST,
2383 .resetvalue = cpu->mvfr1 },
2384 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
2385 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
2386 .access = PL1_R, .type = ARM_CP_CONST,
2387 .resetvalue = cpu->mvfr2 },
2388 REGINFO_SENTINEL
2389 };
2390 ARMCPRegInfo rvbar = {
2391 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
2392 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
2393 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
2394 };
2395 define_one_arm_cp_reg(cpu, &rvbar);
2396 define_arm_cp_regs(cpu, v8_idregs);
2397 define_arm_cp_regs(cpu, v8_cp_reginfo);
2398 define_aarch64_debug_regs(cpu);
2399 }
2400 if (arm_feature(env, ARM_FEATURE_EL2)) {
2401 define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
2402 } else {
2403 /* If EL2 is missing but higher ELs are enabled, we need to
2404 * register the no_el2 reginfos.
2405 */
2406 if (arm_feature(env, ARM_FEATURE_EL3)) {
2407 define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
2408 }
2409 }
2410 if (arm_feature(env, ARM_FEATURE_EL3)) {
2411 define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
2412 }
2413 if (arm_feature(env, ARM_FEATURE_MPU)) {
2414 /* These are the MPU registers prior to PMSAv6. Any new
2415 * PMSA core later than the ARM946 will require that we
2416 * implement the PMSAv6 or PMSAv7 registers, which are
2417 * completely different.
2418 */
2419 assert(!arm_feature(env, ARM_FEATURE_V6));
2420 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2421 } else {
2422 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2423 }
2424 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2425 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2426 }
2427 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2428 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2429 }
2430 if (arm_feature(env, ARM_FEATURE_VAPA)) {
2431 define_arm_cp_regs(cpu, vapa_cp_reginfo);
2432 }
2433 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2434 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2435 }
2436 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2437 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2438 }
2439 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2440 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2441 }
2442 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2443 define_arm_cp_regs(cpu, omap_cp_reginfo);
2444 }
2445 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2446 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2447 }
2448 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2449 define_arm_cp_regs(cpu, xscale_cp_reginfo);
2450 }
2451 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2452 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2453 }
2454 if (arm_feature(env, ARM_FEATURE_LPAE)) {
2455 define_arm_cp_regs(cpu, lpae_cp_reginfo);
2456 }
2457 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2458 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2459 * be read-only (ie write causes UNDEF exception).
2460 */
2461 {
2462 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
2463 /* Pre-v8 MIDR space.
2464 * Note that the MIDR isn't a simple constant register because
2465 * of the TI925 behaviour where writes to another register can
2466 * cause the MIDR value to change.
2467 *
2468 * Unimplemented registers in the c15 0 0 0 space default to
2469 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2470 * and friends override accordingly.
2471 */
2472 { .name = "MIDR",
2473 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2474 .access = PL1_R, .resetvalue = cpu->midr,
2475 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2476 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2477 .type = ARM_CP_OVERRIDE },
2478 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2479 { .name = "DUMMY",
2480 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2481 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2482 { .name = "DUMMY",
2483 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2484 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2485 { .name = "DUMMY",
2486 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2487 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2488 { .name = "DUMMY",
2489 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2490 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2491 { .name = "DUMMY",
2492 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2493 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2494 REGINFO_SENTINEL
2495 };
2496 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
2497 /* v8 MIDR -- the wildcard isn't necessary, and nor is the
2498 * variable-MIDR TI925 behaviour. Instead we have a single
2499 * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
2500 */
2501 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
2502 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
2503 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2504 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
2505 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
2506 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2507 REGINFO_SENTINEL
2508 };
2509 ARMCPRegInfo id_cp_reginfo[] = {
2510 /* These are common to v8 and pre-v8 */
2511 { .name = "CTR",
2512 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2513 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2514 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2515 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2516 .access = PL0_R, .accessfn = ctr_el0_access,
2517 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2518 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
2519 { .name = "TCMTR",
2520 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2521 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2522 { .name = "TLBTR",
2523 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2524 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2525 REGINFO_SENTINEL
2526 };
2527 ARMCPRegInfo crn0_wi_reginfo = {
2528 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2529 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2530 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2531 };
2532 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2533 arm_feature(env, ARM_FEATURE_STRONGARM)) {
2534 ARMCPRegInfo *r;
2535 /* Register the blanket "writes ignored" value first to cover the
2536 * whole space. Then update the specific ID registers to allow write
2537 * access, so that they ignore writes rather than causing them to
2538 * UNDEF.
2539 */
2540 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2541 for (r = id_pre_v8_midr_cp_reginfo;
2542 r->type != ARM_CP_SENTINEL; r++) {
2543 r->access = PL1_RW;
2544 }
2545 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2546 r->access = PL1_RW;
2547 }
2548 }
2549 if (arm_feature(env, ARM_FEATURE_V8)) {
2550 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
2551 } else {
2552 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
2553 }
2554 define_arm_cp_regs(cpu, id_cp_reginfo);
2555 }
2556
2557 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2558 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2559 }
2560
2561 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2562 ARMCPRegInfo auxcr = {
2563 .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
2564 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
2565 .access = PL1_RW, .type = ARM_CP_CONST,
2566 .resetvalue = cpu->reset_auxcr
2567 };
2568 define_one_arm_cp_reg(cpu, &auxcr);
2569 }
2570
2571 if (arm_feature(env, ARM_FEATURE_CBAR)) {
2572 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2573 /* 32 bit view is [31:18] 0...0 [43:32]. */
2574 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
2575 | extract64(cpu->reset_cbar, 32, 12);
2576 ARMCPRegInfo cbar_reginfo[] = {
2577 { .name = "CBAR",
2578 .type = ARM_CP_CONST,
2579 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2580 .access = PL1_R, .resetvalue = cpu->reset_cbar },
2581 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
2582 .type = ARM_CP_CONST,
2583 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
2584 .access = PL1_R, .resetvalue = cbar32 },
2585 REGINFO_SENTINEL
2586 };
2587 /* We don't implement a r/w 64 bit CBAR currently */
2588 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
2589 define_arm_cp_regs(cpu, cbar_reginfo);
2590 } else {
2591 ARMCPRegInfo cbar = {
2592 .name = "CBAR",
2593 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2594 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2595 .fieldoffset = offsetof(CPUARMState,
2596 cp15.c15_config_base_address)
2597 };
2598 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
2599 cbar.access = PL1_R;
2600 cbar.fieldoffset = 0;
2601 cbar.type = ARM_CP_CONST;
2602 }
2603 define_one_arm_cp_reg(cpu, &cbar);
2604 }
2605 }
2606
2607 /* Generic registers whose values depend on the implementation */
2608 {
2609 ARMCPRegInfo sctlr = {
2610 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2611 .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2612 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2613 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2614 .raw_writefn = raw_write,
2615 };
2616 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2617 /* Normally we would always end the TB on an SCTLR write, but Linux
2618 * arch/arm/mach-pxa/sleep.S expects two instructions following
2619 * an MMU enable to execute from cache. Imitate this behaviour.
2620 */
2621 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2622 }
2623 define_one_arm_cp_reg(cpu, &sctlr);
2624 }
2625 }
2626
2627 ARMCPU *cpu_arm_init(const char *cpu_model)
2628 {
2629 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2630 }
2631
2632 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2633 {
2634 CPUState *cs = CPU(cpu);
2635 CPUARMState *env = &cpu->env;
2636
2637 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2638 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2639 aarch64_fpu_gdb_set_reg,
2640 34, "aarch64-fpu.xml", 0);
2641 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2642 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2643 51, "arm-neon.xml", 0);
2644 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2645 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2646 35, "arm-vfp3.xml", 0);
2647 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2648 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2649 19, "arm-vfp.xml", 0);
2650 }
2651 }
2652
2653 /* Sort alphabetically by type name, except for "any". */
2654 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2655 {
2656 ObjectClass *class_a = (ObjectClass *)a;
2657 ObjectClass *class_b = (ObjectClass *)b;
2658 const char *name_a, *name_b;
2659
2660 name_a = object_class_get_name(class_a);
2661 name_b = object_class_get_name(class_b);
2662 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2663 return 1;
2664 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2665 return -1;
2666 } else {
2667 return strcmp(name_a, name_b);
2668 }
2669 }
2670
2671 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2672 {
2673 ObjectClass *oc = data;
2674 CPUListState *s = user_data;
2675 const char *typename;
2676 char *name;
2677
2678 typename = object_class_get_name(oc);
2679 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2680 (*s->cpu_fprintf)(s->file, " %s\n",
2681 name);
2682 g_free(name);
2683 }
2684
2685 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2686 {
2687 CPUListState s = {
2688 .file = f,
2689 .cpu_fprintf = cpu_fprintf,
2690 };
2691 GSList *list;
2692
2693 list = object_class_get_list(TYPE_ARM_CPU, false);
2694 list = g_slist_sort(list, arm_cpu_list_compare);
2695 (*cpu_fprintf)(f, "Available CPUs:\n");
2696 g_slist_foreach(list, arm_cpu_list_entry, &s);
2697 g_slist_free(list);
2698 #ifdef CONFIG_KVM
2699 /* The 'host' CPU type is dynamically registered only if KVM is
2700 * enabled, so we have to special-case it here:
2701 */
2702 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
2703 #endif
2704 }
2705
2706 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2707 {
2708 ObjectClass *oc = data;
2709 CpuDefinitionInfoList **cpu_list = user_data;
2710 CpuDefinitionInfoList *entry;
2711 CpuDefinitionInfo *info;
2712 const char *typename;
2713
2714 typename = object_class_get_name(oc);
2715 info = g_malloc0(sizeof(*info));
2716 info->name = g_strndup(typename,
2717 strlen(typename) - strlen("-" TYPE_ARM_CPU));
2718
2719 entry = g_malloc0(sizeof(*entry));
2720 entry->value = info;
2721 entry->next = *cpu_list;
2722 *cpu_list = entry;
2723 }
2724
2725 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2726 {
2727 CpuDefinitionInfoList *cpu_list = NULL;
2728 GSList *list;
2729
2730 list = object_class_get_list(TYPE_ARM_CPU, false);
2731 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2732 g_slist_free(list);
2733
2734 return cpu_list;
2735 }
2736
2737 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2738 void *opaque, int state,
2739 int crm, int opc1, int opc2)
2740 {
2741 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2742 * add a single reginfo struct to the hash table.
2743 */
2744 uint32_t *key = g_new(uint32_t, 1);
2745 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2746 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2747 if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2748 /* The AArch32 view of a shared register sees the lower 32 bits
2749 * of a 64 bit backing field. It is not migratable as the AArch64
2750 * view handles that. AArch64 also handles reset.
2751 * We assume it is a cp15 register.
2752 */
2753 r2->cp = 15;
2754 r2->type |= ARM_CP_NO_MIGRATE;
2755 r2->resetfn = arm_cp_reset_ignore;
2756 #ifdef HOST_WORDS_BIGENDIAN
2757 if (r2->fieldoffset) {
2758 r2->fieldoffset += sizeof(uint32_t);
2759 }
2760 #endif
2761 }
2762 if (state == ARM_CP_STATE_AA64) {
2763 /* To allow abbreviation of ARMCPRegInfo
2764 * definitions, we treat cp == 0 as equivalent to
2765 * the value for "standard guest-visible sysreg".
2766 */
2767 if (r->cp == 0) {
2768 r2->cp = CP_REG_ARM64_SYSREG_CP;
2769 }
2770 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2771 r2->opc0, opc1, opc2);
2772 } else {
2773 *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2774 }
2775 if (opaque) {
2776 r2->opaque = opaque;
2777 }
2778 /* reginfo passed to helpers is correct for the actual access,
2779 * and is never ARM_CP_STATE_BOTH:
2780 */
2781 r2->state = state;
2782 /* Make sure reginfo passed to helpers for wildcarded regs
2783 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2784 */
2785 r2->crm = crm;
2786 r2->opc1 = opc1;
2787 r2->opc2 = opc2;
2788 /* By convention, for wildcarded registers only the first
2789 * entry is used for migration; the others are marked as
2790 * NO_MIGRATE so we don't try to transfer the register
2791 * multiple times. Special registers (ie NOP/WFI) are
2792 * never migratable.
2793 */
2794 if ((r->type & ARM_CP_SPECIAL) ||
2795 ((r->crm == CP_ANY) && crm != 0) ||
2796 ((r->opc1 == CP_ANY) && opc1 != 0) ||
2797 ((r->opc2 == CP_ANY) && opc2 != 0)) {
2798 r2->type |= ARM_CP_NO_MIGRATE;
2799 }
2800
2801 /* Overriding of an existing definition must be explicitly
2802 * requested.
2803 */
2804 if (!(r->type & ARM_CP_OVERRIDE)) {
2805 ARMCPRegInfo *oldreg;
2806 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2807 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2808 fprintf(stderr, "Register redefined: cp=%d %d bit "
2809 "crn=%d crm=%d opc1=%d opc2=%d, "
2810 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2811 r2->crn, r2->crm, r2->opc1, r2->opc2,
2812 oldreg->name, r2->name);
2813 g_assert_not_reached();
2814 }
2815 }
2816 g_hash_table_insert(cpu->cp_regs, key, r2);
2817 }
2818
2819
2820 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2821 const ARMCPRegInfo *r, void *opaque)
2822 {
2823 /* Define implementations of coprocessor registers.
2824 * We store these in a hashtable because typically
2825 * there are less than 150 registers in a space which
2826 * is 16*16*16*8*8 = 262144 in size.
2827 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2828 * If a register is defined twice then the second definition is
2829 * used, so this can be used to define some generic registers and
2830 * then override them with implementation specific variations.
2831 * At least one of the original and the second definition should
2832 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2833 * against accidental use.
2834 *
2835 * The state field defines whether the register is to be
2836 * visible in the AArch32 or AArch64 execution state. If the
2837 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2838 * reginfo structure for the AArch32 view, which sees the lower
2839 * 32 bits of the 64 bit register.
2840 *
2841 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2842 * be wildcarded. AArch64 registers are always considered to be 64
2843 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2844 * the register, if any.
2845 */
2846 int crm, opc1, opc2, state;
2847 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2848 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2849 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2850 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2851 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2852 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2853 /* 64 bit registers have only CRm and Opc1 fields */
2854 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2855 /* op0 only exists in the AArch64 encodings */
2856 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2857 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2858 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2859 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2860 * encodes a minimum access level for the register. We roll this
2861 * runtime check into our general permission check code, so check
2862 * here that the reginfo's specified permissions are strict enough
2863 * to encompass the generic architectural permission check.
2864 */
2865 if (r->state != ARM_CP_STATE_AA32) {
2866 int mask = 0;
2867 switch (r->opc1) {
2868 case 0: case 1: case 2:
2869 /* min_EL EL1 */
2870 mask = PL1_RW;
2871 break;
2872 case 3:
2873 /* min_EL EL0 */
2874 mask = PL0_RW;
2875 break;
2876 case 4:
2877 /* min_EL EL2 */
2878 mask = PL2_RW;
2879 break;
2880 case 5:
2881 /* unallocated encoding, so not possible */
2882 assert(false);
2883 break;
2884 case 6:
2885 /* min_EL EL3 */
2886 mask = PL3_RW;
2887 break;
2888 case 7:
2889 /* min_EL EL1, secure mode only (we don't check the latter) */
2890 mask = PL1_RW;
2891 break;
2892 default:
2893 /* broken reginfo with out-of-range opc1 */
2894 assert(false);
2895 break;
2896 }
2897 /* assert our permissions are not too lax (stricter is fine) */
2898 assert((r->access & ~mask) == 0);
2899 }
2900
2901 /* Check that the register definition has enough info to handle
2902 * reads and writes if they are permitted.
2903 */
2904 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2905 if (r->access & PL3_R) {
2906 assert(r->fieldoffset || r->readfn);
2907 }
2908 if (r->access & PL3_W) {
2909 assert(r->fieldoffset || r->writefn);
2910 }
2911 }
2912 /* Bad type field probably means missing sentinel at end of reg list */
2913 assert(cptype_valid(r->type));
2914 for (crm = crmmin; crm <= crmmax; crm++) {
2915 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2916 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2917 for (state = ARM_CP_STATE_AA32;
2918 state <= ARM_CP_STATE_AA64; state++) {
2919 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2920 continue;
2921 }
2922 add_cpreg_to_hashtable(cpu, r, opaque, state,
2923 crm, opc1, opc2);
2924 }
2925 }
2926 }
2927 }
2928 }
2929
2930 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2931 const ARMCPRegInfo *regs, void *opaque)
2932 {
2933 /* Define a whole list of registers */
2934 const ARMCPRegInfo *r;
2935 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2936 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2937 }
2938 }
2939
2940 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2941 {
2942 return g_hash_table_lookup(cpregs, &encoded_cp);
2943 }
2944
2945 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2946 uint64_t value)
2947 {
2948 /* Helper coprocessor write function for write-ignore registers */
2949 }
2950
2951 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
2952 {
2953 /* Helper coprocessor write function for read-as-zero registers */
2954 return 0;
2955 }
2956
2957 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2958 {
2959 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2960 }
2961
2962 static int bad_mode_switch(CPUARMState *env, int mode)
2963 {
2964 /* Return true if it is not valid for us to switch to
2965 * this CPU mode (ie all the UNPREDICTABLE cases in
2966 * the ARM ARM CPSRWriteByInstr pseudocode).
2967 */
2968 switch (mode) {
2969 case ARM_CPU_MODE_USR:
2970 case ARM_CPU_MODE_SYS:
2971 case ARM_CPU_MODE_SVC:
2972 case ARM_CPU_MODE_ABT:
2973 case ARM_CPU_MODE_UND:
2974 case ARM_CPU_MODE_IRQ:
2975 case ARM_CPU_MODE_FIQ:
2976 return 0;
2977 default:
2978 return 1;
2979 }
2980 }
2981
2982 uint32_t cpsr_read(CPUARMState *env)
2983 {
2984 int ZF;
2985 ZF = (env->ZF == 0);
2986 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2987 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2988 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2989 | ((env->condexec_bits & 0xfc) << 8)
2990 | (env->GE << 16) | (env->daif & CPSR_AIF);
2991 }
2992
2993 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2994 {
2995 if (mask & CPSR_NZCV) {
2996 env->ZF = (~val) & CPSR_Z;
2997 env->NF = val;
2998 env->CF = (val >> 29) & 1;
2999 env->VF = (val << 3) & 0x80000000;
3000 }
3001 if (mask & CPSR_Q)
3002 env->QF = ((val & CPSR_Q) != 0);
3003 if (mask & CPSR_T)
3004 env->thumb = ((val & CPSR_T) != 0);
3005 if (mask & CPSR_IT_0_1) {
3006 env->condexec_bits &= ~3;
3007 env->condexec_bits |= (val >> 25) & 3;
3008 }
3009 if (mask & CPSR_IT_2_7) {
3010 env->condexec_bits &= 3;
3011 env->condexec_bits |= (val >> 8) & 0xfc;
3012 }
3013 if (mask & CPSR_GE) {
3014 env->GE = (val >> 16) & 0xf;
3015 }
3016
3017 env->daif &= ~(CPSR_AIF & mask);
3018 env->daif |= val & CPSR_AIF & mask;
3019
3020 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
3021 if (bad_mode_switch(env, val & CPSR_M)) {
3022 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3023 * We choose to ignore the attempt and leave the CPSR M field
3024 * untouched.
3025 */
3026 mask &= ~CPSR_M;
3027 } else {
3028 switch_mode(env, val & CPSR_M);
3029 }
3030 }
3031 mask &= ~CACHED_CPSR_BITS;
3032 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
3033 }
3034
3035 /* Sign/zero extend */
3036 uint32_t HELPER(sxtb16)(uint32_t x)
3037 {
3038 uint32_t res;
3039 res = (uint16_t)(int8_t)x;
3040 res |= (uint32_t)(int8_t)(x >> 16) << 16;
3041 return res;
3042 }
3043
3044 uint32_t HELPER(uxtb16)(uint32_t x)
3045 {
3046 uint32_t res;
3047 res = (uint16_t)(uint8_t)x;
3048 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
3049 return res;
3050 }
3051
3052 uint32_t HELPER(clz)(uint32_t x)
3053 {
3054 return clz32(x);
3055 }
3056
3057 int32_t HELPER(sdiv)(int32_t num, int32_t den)
3058 {
3059 if (den == 0)
3060 return 0;
3061 if (num == INT_MIN && den == -1)
3062 return INT_MIN;
3063 return num / den;
3064 }
3065
3066 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
3067 {
3068 if (den == 0)
3069 return 0;
3070 return num / den;
3071 }
3072
3073 uint32_t HELPER(rbit)(uint32_t x)
3074 {
3075 x = ((x & 0xff000000) >> 24)
3076 | ((x & 0x00ff0000) >> 8)
3077 | ((x & 0x0000ff00) << 8)
3078 | ((x & 0x000000ff) << 24);
3079 x = ((x & 0xf0f0f0f0) >> 4)
3080 | ((x & 0x0f0f0f0f) << 4);
3081 x = ((x & 0x88888888) >> 3)
3082 | ((x & 0x44444444) >> 1)
3083 | ((x & 0x22222222) << 1)
3084 | ((x & 0x11111111) << 3);
3085 return x;
3086 }
3087
3088 #if defined(CONFIG_USER_ONLY)
3089
3090 void arm_cpu_do_interrupt(CPUState *cs)
3091 {
3092 cs->exception_index = -1;
3093 }
3094
3095 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
3096 int mmu_idx)
3097 {
3098 ARMCPU *cpu = ARM_CPU(cs);
3099 CPUARMState *env = &cpu->env;
3100
3101 env->exception.vaddress = address;
3102 if (rw == 2) {
3103 cs->exception_index = EXCP_PREFETCH_ABORT;
3104 } else {
3105 cs->exception_index = EXCP_DATA_ABORT;
3106 }
3107 return 1;
3108 }
3109
3110 /* These should probably raise undefined insn exceptions. */
3111 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3112 {
3113 ARMCPU *cpu = arm_env_get_cpu(env);
3114
3115 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
3116 }
3117
3118 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3119 {
3120 ARMCPU *cpu = arm_env_get_cpu(env);
3121
3122 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
3123 return 0;
3124 }
3125
3126 void switch_mode(CPUARMState *env, int mode)
3127 {
3128 ARMCPU *cpu = arm_env_get_cpu(env);
3129
3130 if (mode != ARM_CPU_MODE_USR) {
3131 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
3132 }
3133 }
3134
3135 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3136 {
3137 ARMCPU *cpu = arm_env_get_cpu(env);
3138
3139 cpu_abort(CPU(cpu), "banked r13 write\n");
3140 }
3141
3142 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3143 {
3144 ARMCPU *cpu = arm_env_get_cpu(env);
3145
3146 cpu_abort(CPU(cpu), "banked r13 read\n");
3147 return 0;
3148 }
3149
3150 #else
3151
3152 /* Map CPU modes onto saved register banks. */
3153 int bank_number(int mode)
3154 {
3155 switch (mode) {
3156 case ARM_CPU_MODE_USR:
3157 case ARM_CPU_MODE_SYS:
3158 return 0;
3159 case ARM_CPU_MODE_SVC:
3160 return 1;
3161 case ARM_CPU_MODE_ABT:
3162 return 2;
3163 case ARM_CPU_MODE_UND:
3164 return 3;
3165 case ARM_CPU_MODE_IRQ:
3166 return 4;
3167 case ARM_CPU_MODE_FIQ:
3168 return 5;
3169 case ARM_CPU_MODE_HYP:
3170 return 6;
3171 case ARM_CPU_MODE_MON:
3172 return 7;
3173 }
3174 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
3175 }
3176
3177 void switch_mode(CPUARMState *env, int mode)
3178 {
3179 int old_mode;
3180 int i;
3181
3182 old_mode = env->uncached_cpsr & CPSR_M;
3183 if (mode == old_mode)
3184 return;
3185
3186 if (old_mode == ARM_CPU_MODE_FIQ) {
3187 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
3188 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
3189 } else if (mode == ARM_CPU_MODE_FIQ) {
3190 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
3191 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
3192 }
3193
3194 i = bank_number(old_mode);
3195 env->banked_r13[i] = env->regs[13];
3196 env->banked_r14[i] = env->regs[14];
3197 env->banked_spsr[i] = env->spsr;
3198
3199 i = bank_number(mode);
3200 env->regs[13] = env->banked_r13[i];
3201 env->regs[14] = env->banked_r14[i];
3202 env->spsr = env->banked_spsr[i];
3203 }
3204
3205 static void v7m_push(CPUARMState *env, uint32_t val)
3206 {
3207 CPUState *cs = CPU(arm_env_get_cpu(env));
3208
3209 env->regs[13] -= 4;
3210 stl_phys(cs->as, env->regs[13], val);
3211 }
3212
3213 static uint32_t v7m_pop(CPUARMState *env)
3214 {
3215 CPUState *cs = CPU(arm_env_get_cpu(env));
3216 uint32_t val;
3217
3218 val = ldl_phys(cs->as, env->regs[13]);
3219 env->regs[13] += 4;
3220 return val;
3221 }
3222
3223 /* Switch to V7M main or process stack pointer. */
3224 static void switch_v7m_sp(CPUARMState *env, int process)
3225 {
3226 uint32_t tmp;
3227 if (env->v7m.current_sp != process) {
3228 tmp = env->v7m.other_sp;
3229 env->v7m.other_sp = env->regs[13];
3230 env->regs[13] = tmp;
3231 env->v7m.current_sp = process;
3232 }
3233 }
3234
3235 static void do_v7m_exception_exit(CPUARMState *env)
3236 {
3237 uint32_t type;
3238 uint32_t xpsr;
3239
3240 type = env->regs[15];
3241 if (env->v7m.exception != 0)
3242 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
3243
3244 /* Switch to the target stack. */
3245 switch_v7m_sp(env, (type & 4) != 0);
3246 /* Pop registers. */
3247 env->regs[0] = v7m_pop(env);
3248 env->regs[1] = v7m_pop(env);
3249 env->regs[2] = v7m_pop(env);
3250 env->regs[3] = v7m_pop(env);
3251 env->regs[12] = v7m_pop(env);
3252 env->regs[14] = v7m_pop(env);
3253 env->regs[15] = v7m_pop(env);
3254 xpsr = v7m_pop(env);
3255 xpsr_write(env, xpsr, 0xfffffdff);
3256 /* Undo stack alignment. */
3257 if (xpsr & 0x200)
3258 env->regs[13] |= 4;
3259 /* ??? The exception return type specifies Thread/Handler mode. However
3260 this is also implied by the xPSR value. Not sure what to do
3261 if there is a mismatch. */
3262 /* ??? Likewise for mismatches between the CONTROL register and the stack
3263 pointer. */
3264 }
3265
3266 void arm_v7m_cpu_do_interrupt(CPUState *cs)
3267 {
3268 ARMCPU *cpu = ARM_CPU(cs);
3269 CPUARMState *env = &cpu->env;
3270 uint32_t xpsr = xpsr_read(env);
3271 uint32_t lr;
3272 uint32_t addr;
3273
3274 arm_log_exception(cs->exception_index);
3275
3276 lr = 0xfffffff1;
3277 if (env->v7m.current_sp)
3278 lr |= 4;
3279 if (env->v7m.exception == 0)
3280 lr |= 8;
3281
3282 /* For exceptions we just mark as pending on the NVIC, and let that
3283 handle it. */
3284 /* TODO: Need to escalate if the current priority is higher than the
3285 one we're raising. */
3286 switch (cs->exception_index) {
3287 case EXCP_UDEF:
3288 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
3289 return;
3290 case EXCP_SWI:
3291 /* The PC already points to the next instruction. */
3292 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
3293 return;
3294 case EXCP_PREFETCH_ABORT:
3295 case EXCP_DATA_ABORT:
3296 /* TODO: if we implemented the MPU registers, this is where we
3297 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3298 */
3299 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
3300 return;
3301 case EXCP_BKPT:
3302 if (semihosting_enabled) {
3303 int nr;
3304 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3305 if (nr == 0xab) {
3306 env->regs[15] += 2;
3307 env->regs[0] = do_arm_semihosting(env);
3308 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3309 return;
3310 }
3311 }
3312 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
3313 return;
3314 case EXCP_IRQ:
3315 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
3316 break;
3317 case EXCP_EXCEPTION_EXIT:
3318 do_v7m_exception_exit(env);
3319 return;
3320 default:
3321 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3322 return; /* Never happens. Keep compiler happy. */
3323 }
3324
3325 /* Align stack pointer. */
3326 /* ??? Should only do this if Configuration Control Register
3327 STACKALIGN bit is set. */
3328 if (env->regs[13] & 4) {
3329 env->regs[13] -= 4;
3330 xpsr |= 0x200;
3331 }
3332 /* Switch to the handler mode. */
3333 v7m_push(env, xpsr);
3334 v7m_push(env, env->regs[15]);
3335 v7m_push(env, env->regs[14]);
3336 v7m_push(env, env->regs[12]);
3337 v7m_push(env, env->regs[3]);
3338 v7m_push(env, env->regs[2]);
3339 v7m_push(env, env->regs[1]);
3340 v7m_push(env, env->regs[0]);
3341 switch_v7m_sp(env, 0);
3342 /* Clear IT bits */
3343 env->condexec_bits = 0;
3344 env->regs[14] = lr;
3345 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
3346 env->regs[15] = addr & 0xfffffffe;
3347 env->thumb = addr & 1;
3348 }
3349
3350 /* Handle a CPU exception. */
3351 void arm_cpu_do_interrupt(CPUState *cs)
3352 {
3353 ARMCPU *cpu = ARM_CPU(cs);
3354 CPUARMState *env = &cpu->env;
3355 uint32_t addr;
3356 uint32_t mask;
3357 int new_mode;
3358 uint32_t offset;
3359
3360 assert(!IS_M(env));
3361
3362 arm_log_exception(cs->exception_index);
3363
3364 /* TODO: Vectored interrupt controller. */
3365 switch (cs->exception_index) {
3366 case EXCP_UDEF:
3367 new_mode = ARM_CPU_MODE_UND;
3368 addr = 0x04;
3369 mask = CPSR_I;
3370 if (env->thumb)
3371 offset = 2;
3372 else
3373 offset = 4;
3374 break;
3375 case EXCP_SWI:
3376 if (semihosting_enabled) {
3377 /* Check for semihosting interrupt. */
3378 if (env->thumb) {
3379 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
3380 & 0xff;
3381 } else {
3382 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
3383 & 0xffffff;
3384 }
3385 /* Only intercept calls from privileged modes, to provide some
3386 semblance of security. */
3387 if (((mask == 0x123456 && !env->thumb)
3388 || (mask == 0xab && env->thumb))
3389 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3390 env->regs[0] = do_arm_semihosting(env);
3391 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3392 return;
3393 }
3394 }
3395 new_mode = ARM_CPU_MODE_SVC;
3396 addr = 0x08;
3397 mask = CPSR_I;
3398 /* The PC already points to the next instruction. */
3399 offset = 0;
3400 break;
3401 case EXCP_BKPT:
3402 /* See if this is a semihosting syscall. */
3403 if (env->thumb && semihosting_enabled) {
3404 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3405 if (mask == 0xab
3406 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3407 env->regs[15] += 2;
3408 env->regs[0] = do_arm_semihosting(env);
3409 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3410 return;
3411 }
3412 }
3413 env->exception.fsr = 2;
3414 /* Fall through to prefetch abort. */
3415 case EXCP_PREFETCH_ABORT:
3416 env->cp15.ifsr_el2 = env->exception.fsr;
3417 env->cp15.far_el1 = deposit64(env->cp15.far_el1, 32, 32,
3418 env->exception.vaddress);
3419 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
3420 env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
3421 new_mode = ARM_CPU_MODE_ABT;
3422 addr = 0x0c;
3423 mask = CPSR_A | CPSR_I;
3424 offset = 4;
3425 break;
3426 case EXCP_DATA_ABORT:
3427 env->cp15.esr_el[1] = env->exception.fsr;
3428 env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32,
3429 env->exception.vaddress);
3430 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
3431 (uint32_t)env->cp15.esr_el[1],
3432 (uint32_t)env->exception.vaddress);
3433 new_mode = ARM_CPU_MODE_ABT;
3434 addr = 0x10;
3435 mask = CPSR_A | CPSR_I;
3436 offset = 8;
3437 break;
3438 case EXCP_IRQ:
3439 new_mode = ARM_CPU_MODE_IRQ;
3440 addr = 0x18;
3441 /* Disable IRQ and imprecise data aborts. */
3442 mask = CPSR_A | CPSR_I;
3443 offset = 4;
3444 break;
3445 case EXCP_FIQ:
3446 new_mode = ARM_CPU_MODE_FIQ;
3447 addr = 0x1c;
3448 /* Disable FIQ, IRQ and imprecise data aborts. */
3449 mask = CPSR_A | CPSR_I | CPSR_F;
3450 offset = 4;
3451 break;
3452 default:
3453 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3454 return; /* Never happens. Keep compiler happy. */
3455 }
3456 /* High vectors. */
3457 if (env->cp15.c1_sys & SCTLR_V) {
3458 /* when enabled, base address cannot be remapped. */
3459 addr += 0xffff0000;
3460 } else {
3461 /* ARM v7 architectures provide a vector base address register to remap
3462 * the interrupt vector table.
3463 * This register is only followed in non-monitor mode, and has a secure
3464 * and un-secure copy. Since the cpu is always in a un-secure operation
3465 * and is never in monitor mode this feature is always active.
3466 * Note: only bits 31:5 are valid.
3467 */
3468 addr += env->cp15.vbar_el[1];
3469 }
3470 switch_mode (env, new_mode);
3471 env->spsr = cpsr_read(env);
3472 /* Clear IT bits. */
3473 env->condexec_bits = 0;
3474 /* Switch to the new mode, and to the correct instruction set. */
3475 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3476 env->daif |= mask;
3477 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3478 * and we should just guard the thumb mode on V4 */
3479 if (arm_feature(env, ARM_FEATURE_V4T)) {
3480 env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3481 }
3482 env->regs[14] = env->regs[15] + offset;
3483 env->regs[15] = addr;
3484 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
3485 }
3486
3487 /* Check section/page access permissions.
3488 Returns the page protection flags, or zero if the access is not
3489 permitted. */
3490 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3491 int access_type, int is_user)
3492 {
3493 int prot_ro;
3494
3495 if (domain_prot == 3) {
3496 return PAGE_READ | PAGE_WRITE;
3497 }
3498
3499 if (access_type == 1)
3500 prot_ro = 0;
3501 else
3502 prot_ro = PAGE_READ;
3503
3504 switch (ap) {
3505 case 0:
3506 if (arm_feature(env, ARM_FEATURE_V7)) {
3507 return 0;
3508 }
3509 if (access_type == 1)
3510 return 0;
3511 switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3512 case SCTLR_S:
3513 return is_user ? 0 : PAGE_READ;
3514 case SCTLR_R:
3515 return PAGE_READ;
3516 default:
3517 return 0;
3518 }
3519 case 1:
3520 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3521 case 2:
3522 if (is_user)
3523 return prot_ro;
3524 else
3525 return PAGE_READ | PAGE_WRITE;
3526 case 3:
3527 return PAGE_READ | PAGE_WRITE;
3528 case 4: /* Reserved. */
3529 return 0;
3530 case 5:
3531 return is_user ? 0 : prot_ro;
3532 case 6:
3533 return prot_ro;
3534 case 7:
3535 if (!arm_feature (env, ARM_FEATURE_V6K))
3536 return 0;
3537 return prot_ro;
3538 default:
3539 abort();
3540 }
3541 }
3542
3543 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
3544 {
3545 uint32_t table;
3546
3547 if (address & env->cp15.c2_mask)
3548 table = env->cp15.ttbr1_el1 & 0xffffc000;
3549 else
3550 table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3551
3552 table |= (address >> 18) & 0x3ffc;
3553 return table;
3554 }
3555
3556 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3557 int is_user, hwaddr *phys_ptr,
3558 int *prot, target_ulong *page_size)
3559 {
3560 CPUState *cs = CPU(arm_env_get_cpu(env));
3561 int code;
3562 uint32_t table;
3563 uint32_t desc;
3564 int type;
3565 int ap;
3566 int domain;
3567 int domain_prot;
3568 hwaddr phys_addr;
3569
3570 /* Pagetable walk. */
3571 /* Lookup l1 descriptor. */
3572 table = get_level1_table_address(env, address);
3573 desc = ldl_phys(cs->as, table);
3574 type = (desc & 3);
3575 domain = (desc >> 5) & 0x0f;
3576 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3577 if (type == 0) {
3578 /* Section translation fault. */
3579 code = 5;
3580 goto do_fault;
3581 }
3582 if (domain_prot == 0 || domain_prot == 2) {
3583 if (type == 2)
3584 code = 9; /* Section domain fault. */
3585 else
3586 code = 11; /* Page domain fault. */
3587 goto do_fault;
3588 }
3589 if (type == 2) {
3590 /* 1Mb section. */
3591 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3592 ap = (desc >> 10) & 3;
3593 code = 13;
3594 *page_size = 1024 * 1024;
3595 } else {
3596 /* Lookup l2 entry. */
3597 if (type == 1) {
3598 /* Coarse pagetable. */
3599 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3600 } else {
3601 /* Fine pagetable. */
3602 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3603 }
3604 desc = ldl_phys(cs->as, table);
3605 switch (desc & 3) {
3606 case 0: /* Page translation fault. */
3607 code = 7;
3608 goto do_fault;
3609 case 1: /* 64k page. */
3610 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3611 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3612 *page_size = 0x10000;
3613 break;
3614 case 2: /* 4k page. */
3615 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3616 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3617 *page_size = 0x1000;
3618 break;
3619 case 3: /* 1k page. */
3620 if (type == 1) {
3621 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3622 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3623 } else {
3624 /* Page translation fault. */
3625 code = 7;
3626 goto do_fault;
3627 }
3628 } else {
3629 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3630 }
3631 ap = (desc >> 4) & 3;
3632 *page_size = 0x400;
3633 break;
3634 default:
3635 /* Never happens, but compiler isn't smart enough to tell. */
3636 abort();
3637 }
3638 code = 15;
3639 }
3640 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3641 if (!*prot) {
3642 /* Access permission fault. */
3643 goto do_fault;
3644 }
3645 *prot |= PAGE_EXEC;
3646 *phys_ptr = phys_addr;
3647 return 0;
3648 do_fault:
3649 return code | (domain << 4);
3650 }
3651
3652 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3653 int is_user, hwaddr *phys_ptr,
3654 int *prot, target_ulong *page_size)
3655 {
3656 CPUState *cs = CPU(arm_env_get_cpu(env));
3657 int code;
3658 uint32_t table;
3659 uint32_t desc;
3660 uint32_t xn;
3661 uint32_t pxn = 0;
3662 int type;
3663 int ap;
3664 int domain = 0;
3665 int domain_prot;
3666 hwaddr phys_addr;
3667
3668 /* Pagetable walk. */
3669 /* Lookup l1 descriptor. */
3670 table = get_level1_table_address(env, address);
3671 desc = ldl_phys(cs->as, table);
3672 type = (desc & 3);
3673 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3674 /* Section translation fault, or attempt to use the encoding
3675 * which is Reserved on implementations without PXN.
3676 */
3677 code = 5;
3678 goto do_fault;
3679 }
3680 if ((type == 1) || !(desc & (1 << 18))) {
3681 /* Page or Section. */
3682 domain = (desc >> 5) & 0x0f;
3683 }
3684 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3685 if (domain_prot == 0 || domain_prot == 2) {
3686 if (type != 1) {
3687 code = 9; /* Section domain fault. */
3688 } else {
3689 code = 11; /* Page domain fault. */
3690 }
3691 goto do_fault;
3692 }
3693 if (type != 1) {
3694 if (desc & (1 << 18)) {
3695 /* Supersection. */
3696 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3697 *page_size = 0x1000000;
3698 } else {
3699 /* Section. */
3700 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3701 *page_size = 0x100000;
3702 }
3703 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3704 xn = desc & (1 << 4);
3705 pxn = desc & 1;
3706 code = 13;
3707 } else {
3708 if (arm_feature(env, ARM_FEATURE_PXN)) {
3709 pxn = (desc >> 2) & 1;
3710 }
3711 /* Lookup l2 entry. */
3712 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3713 desc = ldl_phys(cs->as, table);
3714 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3715 switch (desc & 3) {
3716 case 0: /* Page translation fault. */
3717 code = 7;
3718 goto do_fault;
3719 case 1: /* 64k page. */
3720 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3721 xn = desc & (1 << 15);
3722 *page_size = 0x10000;
3723 break;
3724 case 2: case 3: /* 4k page. */
3725 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3726 xn = desc & 1;
3727 *page_size = 0x1000;
3728 break;
3729 default:
3730 /* Never happens, but compiler isn't smart enough to tell. */
3731 abort();
3732 }
3733 code = 15;
3734 }
3735 if (domain_prot == 3) {
3736 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3737 } else {
3738 if (pxn && !is_user) {
3739 xn = 1;
3740 }
3741 if (xn && access_type == 2)
3742 goto do_fault;
3743
3744 /* The simplified model uses AP[0] as an access control bit. */
3745 if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3746 /* Access flag fault. */
3747 code = (code == 15) ? 6 : 3;
3748 goto do_fault;
3749 }
3750 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3751 if (!*prot) {
3752 /* Access permission fault. */
3753 goto do_fault;
3754 }
3755 if (!xn) {
3756 *prot |= PAGE_EXEC;
3757 }
3758 }
3759 *phys_ptr = phys_addr;
3760 return 0;
3761 do_fault:
3762 return code | (domain << 4);
3763 }
3764
3765 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3766 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3767 */
3768 typedef enum {
3769 translation_fault = 1,
3770 access_fault = 2,
3771 permission_fault = 3,
3772 } MMUFaultType;
3773
3774 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
3775 int access_type, int is_user,
3776 hwaddr *phys_ptr, int *prot,
3777 target_ulong *page_size_ptr)
3778 {
3779 CPUState *cs = CPU(arm_env_get_cpu(env));
3780 /* Read an LPAE long-descriptor translation table. */
3781 MMUFaultType fault_type = translation_fault;
3782 uint32_t level = 1;
3783 uint32_t epd;
3784 int32_t tsz;
3785 uint32_t tg;
3786 uint64_t ttbr;
3787 int ttbr_select;
3788 hwaddr descaddr, descmask;
3789 uint32_t tableattrs;
3790 target_ulong page_size;
3791 uint32_t attrs;
3792 int32_t granule_sz = 9;
3793 int32_t va_size = 32;
3794 int32_t tbi = 0;
3795
3796 if (arm_el_is_aa64(env, 1)) {
3797 va_size = 64;
3798 if (extract64(address, 55, 1))
3799 tbi = extract64(env->cp15.c2_control, 38, 1);
3800 else
3801 tbi = extract64(env->cp15.c2_control, 37, 1);
3802 tbi *= 8;
3803 }
3804
3805 /* Determine whether this address is in the region controlled by
3806 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3807 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3808 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3809 */
3810 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
3811 if (arm_el_is_aa64(env, 1)) {
3812 t0sz = MIN(t0sz, 39);
3813 t0sz = MAX(t0sz, 16);
3814 }
3815 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
3816 if (arm_el_is_aa64(env, 1)) {
3817 t1sz = MIN(t1sz, 39);
3818 t1sz = MAX(t1sz, 16);
3819 }
3820 if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
3821 /* there is a ttbr0 region and we are in it (high bits all zero) */
3822 ttbr_select = 0;
3823 } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
3824 /* there is a ttbr1 region and we are in it (high bits all one) */
3825 ttbr_select = 1;
3826 } else if (!t0sz) {
3827 /* ttbr0 region is "everything not in the ttbr1 region" */
3828 ttbr_select = 0;
3829 } else if (!t1sz) {
3830 /* ttbr1 region is "everything not in the ttbr0 region" */
3831 ttbr_select = 1;
3832 } else {
3833 /* in the gap between the two regions, this is a Translation fault */
3834 fault_type = translation_fault;
3835 goto do_fault;
3836 }
3837
3838 /* Note that QEMU ignores shareability and cacheability attributes,
3839 * so we don't need to do anything with the SH, ORGN, IRGN fields
3840 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3841 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3842 * implement any ASID-like capability so we can ignore it (instead
3843 * we will always flush the TLB any time the ASID is changed).
3844 */
3845 if (ttbr_select == 0) {
3846 ttbr = env->cp15.ttbr0_el1;
3847 epd = extract32(env->cp15.c2_control, 7, 1);
3848 tsz = t0sz;
3849
3850 tg = extract32(env->cp15.c2_control, 14, 2);
3851 if (tg == 1) { /* 64KB pages */
3852 granule_sz = 13;
3853 }
3854 if (tg == 2) { /* 16KB pages */
3855 granule_sz = 11;
3856 }
3857 } else {
3858 ttbr = env->cp15.ttbr1_el1;
3859 epd = extract32(env->cp15.c2_control, 23, 1);
3860 tsz = t1sz;
3861
3862 tg = extract32(env->cp15.c2_control, 30, 2);
3863 if (tg == 3) { /* 64KB pages */
3864 granule_sz = 13;
3865 }
3866 if (tg == 1) { /* 16KB pages */
3867 granule_sz = 11;
3868 }
3869 }
3870
3871 if (epd) {
3872 /* Translation table walk disabled => Translation fault on TLB miss */
3873 goto do_fault;
3874 }
3875
3876 /* The starting level depends on the virtual address size which can be
3877 * up to 48-bits and the translation granule size.
3878 */
3879 if ((va_size - tsz) > (granule_sz * 4 + 3)) {
3880 level = 0;
3881 } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
3882 level = 1;
3883 } else {
3884 level = 2;
3885 }
3886
3887 /* Clear the vaddr bits which aren't part of the within-region address,
3888 * so that we don't have to special case things when calculating the
3889 * first descriptor address.
3890 */
3891 if (tsz) {
3892 address &= (1ULL << (va_size - tsz)) - 1;
3893 }
3894
3895 descmask = (1ULL << (granule_sz + 3)) - 1;
3896
3897 /* Now we can extract the actual base address from the TTBR */
3898 descaddr = extract64(ttbr, 0, 48);
3899 descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
3900
3901 tableattrs = 0;
3902 for (;;) {
3903 uint64_t descriptor;
3904
3905 descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
3906 descaddr &= ~7ULL;
3907 descriptor = ldq_phys(cs->as, descaddr);
3908 if (!(descriptor & 1) ||
3909 (!(descriptor & 2) && (level == 3))) {
3910 /* Invalid, or the Reserved level 3 encoding */
3911 goto do_fault;
3912 }
3913 descaddr = descriptor & 0xfffffff000ULL;
3914
3915 if ((descriptor & 2) && (level < 3)) {
3916 /* Table entry. The top five bits are attributes which may
3917 * propagate down through lower levels of the table (and
3918 * which are all arranged so that 0 means "no effect", so
3919 * we can gather them up by ORing in the bits at each level).
3920 */
3921 tableattrs |= extract64(descriptor, 59, 5);
3922 level++;
3923 continue;
3924 }
3925 /* Block entry at level 1 or 2, or page entry at level 3.
3926 * These are basically the same thing, although the number
3927 * of bits we pull in from the vaddr varies.
3928 */
3929 page_size = (1 << ((granule_sz * (4 - level)) + 3));
3930 descaddr |= (address & (page_size - 1));
3931 /* Extract attributes from the descriptor and merge with table attrs */
3932 if (arm_feature(env, ARM_FEATURE_V8)) {
3933 attrs = extract64(descriptor, 2, 10)
3934 | (extract64(descriptor, 53, 11) << 10);
3935 } else {
3936 attrs = extract64(descriptor, 2, 10)
3937 | (extract64(descriptor, 52, 12) << 10);
3938 }
3939 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3940 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3941 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3942 * means "force PL1 access only", which means forcing AP[1] to 0.
3943 */
3944 if (extract32(tableattrs, 2, 1)) {
3945 attrs &= ~(1 << 4);
3946 }
3947 /* Since we're always in the Non-secure state, NSTable is ignored. */
3948 break;
3949 }
3950 /* Here descaddr is the final physical address, and attributes
3951 * are all in attrs.
3952 */
3953 fault_type = access_fault;
3954 if ((attrs & (1 << 8)) == 0) {
3955 /* Access flag */
3956 goto do_fault;
3957 }
3958 fault_type = permission_fault;
3959 if (is_user && !(attrs & (1 << 4))) {
3960 /* Unprivileged access not enabled */
3961 goto do_fault;
3962 }
3963 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3964 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3965 /* XN or PXN */
3966 if (access_type == 2) {
3967 goto do_fault;
3968 }
3969 *prot &= ~PAGE_EXEC;
3970 }
3971 if (attrs & (1 << 5)) {
3972 /* Write access forbidden */
3973 if (access_type == 1) {
3974 goto do_fault;
3975 }
3976 *prot &= ~PAGE_WRITE;
3977 }
3978
3979 *phys_ptr = descaddr;
3980 *page_size_ptr = page_size;
3981 return 0;
3982
3983 do_fault:
3984 /* Long-descriptor format IFSR/DFSR value */
3985 return (1 << 9) | (fault_type << 2) | level;
3986 }
3987
3988 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3989 int access_type, int is_user,
3990 hwaddr *phys_ptr, int *prot)
3991 {
3992 int n;
3993 uint32_t mask;
3994 uint32_t base;
3995
3996 *phys_ptr = address;
3997 for (n = 7; n >= 0; n--) {
3998 base = env->cp15.c6_region[n];
3999 if ((base & 1) == 0)
4000 continue;
4001 mask = 1 << ((base >> 1) & 0x1f);
4002 /* Keep this shift separate from the above to avoid an
4003 (undefined) << 32. */
4004 mask = (mask << 1) - 1;
4005 if (((base ^ address) & ~mask) == 0)
4006 break;
4007 }
4008 if (n < 0)
4009 return 2;
4010
4011 if (access_type == 2) {
4012 mask = env->cp15.pmsav5_insn_ap;
4013 } else {
4014 mask = env->cp15.pmsav5_data_ap;
4015 }
4016 mask = (mask >> (n * 4)) & 0xf;
4017 switch (mask) {
4018 case 0:
4019 return 1;
4020 case 1:
4021 if (is_user)
4022 return 1;
4023 *prot = PAGE_READ | PAGE_WRITE;
4024 break;
4025 case 2:
4026 *prot = PAGE_READ;
4027 if (!is_user)
4028 *prot |= PAGE_WRITE;
4029 break;
4030 case 3:
4031 *prot = PAGE_READ | PAGE_WRITE;
4032 break;
4033 case 5:
4034 if (is_user)
4035 return 1;
4036 *prot = PAGE_READ;
4037 break;
4038 case 6:
4039 *prot = PAGE_READ;
4040 break;
4041 default:
4042 /* Bad permission. */
4043 return 1;
4044 }
4045 *prot |= PAGE_EXEC;
4046 return 0;
4047 }
4048
4049 /* get_phys_addr - get the physical address for this virtual address
4050 *
4051 * Find the physical address corresponding to the given virtual address,
4052 * by doing a translation table walk on MMU based systems or using the
4053 * MPU state on MPU based systems.
4054 *
4055 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
4056 * prot and page_size are not filled in, and the return value provides
4057 * information on why the translation aborted, in the format of a
4058 * DFSR/IFSR fault register, with the following caveats:
4059 * * we honour the short vs long DFSR format differences.
4060 * * the WnR bit is never set (the caller must do this).
4061 * * for MPU based systems we don't bother to return a full FSR format
4062 * value.
4063 *
4064 * @env: CPUARMState
4065 * @address: virtual address to get physical address for
4066 * @access_type: 0 for read, 1 for write, 2 for execute
4067 * @is_user: 0 for privileged access, 1 for user
4068 * @phys_ptr: set to the physical address corresponding to the virtual address
4069 * @prot: set to the permissions for the page containing phys_ptr
4070 * @page_size: set to the size of the page containing phys_ptr
4071 */
4072 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
4073 int access_type, int is_user,
4074 hwaddr *phys_ptr, int *prot,
4075 target_ulong *page_size)
4076 {
4077 /* Fast Context Switch Extension. */
4078 if (address < 0x02000000)
4079 address += env->cp15.c13_fcse;
4080
4081 if ((env->cp15.c1_sys & SCTLR_M) == 0) {
4082 /* MMU/MPU disabled. */
4083 *phys_ptr = address;
4084 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4085 *page_size = TARGET_PAGE_SIZE;
4086 return 0;
4087 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
4088 *page_size = TARGET_PAGE_SIZE;
4089 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
4090 prot);
4091 } else if (extended_addresses_enabled(env)) {
4092 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
4093 prot, page_size);
4094 } else if (env->cp15.c1_sys & SCTLR_XP) {
4095 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
4096 prot, page_size);
4097 } else {
4098 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
4099 prot, page_size);
4100 }
4101 }
4102
4103 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
4104 int access_type, int mmu_idx)
4105 {
4106 ARMCPU *cpu = ARM_CPU(cs);
4107 CPUARMState *env = &cpu->env;
4108 hwaddr phys_addr;
4109 target_ulong page_size;
4110 int prot;
4111 int ret, is_user;
4112 uint32_t syn;
4113 bool same_el = (arm_current_pl(env) != 0);
4114
4115 is_user = mmu_idx == MMU_USER_IDX;
4116 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
4117 &page_size);
4118 if (ret == 0) {
4119 /* Map a single [sub]page. */
4120 phys_addr &= ~(hwaddr)0x3ff;
4121 address &= ~(target_ulong)0x3ff;
4122 tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
4123 return 0;
4124 }
4125
4126 /* AArch64 syndrome does not have an LPAE bit */
4127 syn = ret & ~(1 << 9);
4128
4129 /* For insn and data aborts we assume there is no instruction syndrome
4130 * information; this is always true for exceptions reported to EL1.
4131 */
4132 if (access_type == 2) {
4133 syn = syn_insn_abort(same_el, 0, 0, syn);
4134 cs->exception_index = EXCP_PREFETCH_ABORT;
4135 } else {
4136 syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
4137 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
4138 ret |= (1 << 11);
4139 }
4140 cs->exception_index = EXCP_DATA_ABORT;
4141 }
4142
4143 env->exception.syndrome = syn;
4144 env->exception.vaddress = address;
4145 env->exception.fsr = ret;
4146 return 1;
4147 }
4148
4149 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4150 {
4151 ARMCPU *cpu = ARM_CPU(cs);
4152 hwaddr phys_addr;
4153 target_ulong page_size;
4154 int prot;
4155 int ret;
4156
4157 ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
4158
4159 if (ret != 0) {
4160 return -1;
4161 }
4162
4163 return phys_addr;
4164 }
4165
4166 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4167 {
4168 if ((env->uncached_cpsr & CPSR_M) == mode) {
4169 env->regs[13] = val;
4170 } else {
4171 env->banked_r13[bank_number(mode)] = val;
4172 }
4173 }
4174
4175 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4176 {
4177 if ((env->uncached_cpsr & CPSR_M) == mode) {
4178 return env->regs[13];
4179 } else {
4180 return env->banked_r13[bank_number(mode)];
4181 }
4182 }
4183
4184 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4185 {
4186 ARMCPU *cpu = arm_env_get_cpu(env);
4187
4188 switch (reg) {
4189 case 0: /* APSR */
4190 return xpsr_read(env) & 0xf8000000;
4191 case 1: /* IAPSR */
4192 return xpsr_read(env) & 0xf80001ff;
4193 case 2: /* EAPSR */
4194 return xpsr_read(env) & 0xff00fc00;
4195 case 3: /* xPSR */
4196 return xpsr_read(env) & 0xff00fdff;
4197 case 5: /* IPSR */
4198 return xpsr_read(env) & 0x000001ff;
4199 case 6: /* EPSR */
4200 return xpsr_read(env) & 0x0700fc00;
4201 case 7: /* IEPSR */
4202 return xpsr_read(env) & 0x0700edff;
4203 case 8: /* MSP */
4204 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
4205 case 9: /* PSP */
4206 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
4207 case 16: /* PRIMASK */
4208 return (env->daif & PSTATE_I) != 0;
4209 case 17: /* BASEPRI */
4210 case 18: /* BASEPRI_MAX */
4211 return env->v7m.basepri;
4212 case 19: /* FAULTMASK */
4213 return (env->daif & PSTATE_F) != 0;
4214 case 20: /* CONTROL */
4215 return env->v7m.control;
4216 default:
4217 /* ??? For debugging only. */
4218 cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
4219 return 0;
4220 }
4221 }
4222
4223 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4224 {
4225 ARMCPU *cpu = arm_env_get_cpu(env);
4226
4227 switch (reg) {
4228 case 0: /* APSR */
4229 xpsr_write(env, val, 0xf8000000);
4230 break;
4231 case 1: /* IAPSR */
4232 xpsr_write(env, val, 0xf8000000);
4233 break;
4234 case 2: /* EAPSR */
4235 xpsr_write(env, val, 0xfe00fc00);
4236 break;
4237 case 3: /* xPSR */
4238 xpsr_write(env, val, 0xfe00fc00);
4239 break;
4240 case 5: /* IPSR */
4241 /* IPSR bits are readonly. */
4242 break;
4243 case 6: /* EPSR */
4244 xpsr_write(env, val, 0x0600fc00);
4245 break;
4246 case 7: /* IEPSR */
4247 xpsr_write(env, val, 0x0600fc00);
4248 break;
4249 case 8: /* MSP */
4250 if (env->v7m.current_sp)
4251 env->v7m.other_sp = val;
4252 else
4253 env->regs[13] = val;
4254 break;
4255 case 9: /* PSP */
4256 if (env->v7m.current_sp)
4257 env->regs[13] = val;
4258 else
4259 env->v7m.other_sp = val;
4260 break;
4261 case 16: /* PRIMASK */
4262 if (val & 1) {
4263 env->daif |= PSTATE_I;
4264 } else {
4265 env->daif &= ~PSTATE_I;
4266 }
4267 break;
4268 case 17: /* BASEPRI */
4269 env->v7m.basepri = val & 0xff;
4270 break;
4271 case 18: /* BASEPRI_MAX */
4272 val &= 0xff;
4273 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
4274 env->v7m.basepri = val;
4275 break;
4276 case 19: /* FAULTMASK */
4277 if (val & 1) {
4278 env->daif |= PSTATE_F;
4279 } else {
4280 env->daif &= ~PSTATE_F;
4281 }
4282 break;
4283 case 20: /* CONTROL */
4284 env->v7m.control = val & 3;
4285 switch_v7m_sp(env, (val & 2) != 0);
4286 break;
4287 default:
4288 /* ??? For debugging only. */
4289 cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
4290 return;
4291 }
4292 }
4293
4294 #endif
4295
4296 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
4297 {
4298 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4299 * Note that we do not implement the (architecturally mandated)
4300 * alignment fault for attempts to use this on Device memory
4301 * (which matches the usual QEMU behaviour of not implementing either
4302 * alignment faults or any memory attribute handling).
4303 */
4304
4305 ARMCPU *cpu = arm_env_get_cpu(env);
4306 uint64_t blocklen = 4 << cpu->dcz_blocksize;
4307 uint64_t vaddr = vaddr_in & ~(blocklen - 1);
4308
4309 #ifndef CONFIG_USER_ONLY
4310 {
4311 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4312 * the block size so we might have to do more than one TLB lookup.
4313 * We know that in fact for any v8 CPU the page size is at least 4K
4314 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4315 * 1K as an artefact of legacy v5 subpage support being present in the
4316 * same QEMU executable.
4317 */
4318 int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
4319 void *hostaddr[maxidx];
4320 int try, i;
4321
4322 for (try = 0; try < 2; try++) {
4323
4324 for (i = 0; i < maxidx; i++) {
4325 hostaddr[i] = tlb_vaddr_to_host(env,
4326 vaddr + TARGET_PAGE_SIZE * i,
4327 1, cpu_mmu_index(env));
4328 if (!hostaddr[i]) {
4329 break;
4330 }
4331 }
4332 if (i == maxidx) {
4333 /* If it's all in the TLB it's fair game for just writing to;
4334 * we know we don't need to update dirty status, etc.
4335 */
4336 for (i = 0; i < maxidx - 1; i++) {
4337 memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
4338 }
4339 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
4340 return;
4341 }
4342 /* OK, try a store and see if we can populate the tlb. This
4343 * might cause an exception if the memory isn't writable,
4344 * in which case we will longjmp out of here. We must for
4345 * this purpose use the actual register value passed to us
4346 * so that we get the fault address right.
4347 */
4348 helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
4349 /* Now we can populate the other TLB entries, if any */
4350 for (i = 0; i < maxidx; i++) {
4351 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
4352 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
4353 helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
4354 }
4355 }
4356 }
4357
4358 /* Slow path (probably attempt to do this to an I/O device or
4359 * similar, or clearing of a block of code we have translations
4360 * cached for). Just do a series of byte writes as the architecture
4361 * demands. It's not worth trying to use a cpu_physical_memory_map(),
4362 * memset(), unmap() sequence here because:
4363 * + we'd need to account for the blocksize being larger than a page
4364 * + the direct-RAM access case is almost always going to be dealt
4365 * with in the fastpath code above, so there's no speed benefit
4366 * + we would have to deal with the map returning NULL because the
4367 * bounce buffer was in use
4368 */
4369 for (i = 0; i < blocklen; i++) {
4370 helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
4371 }
4372 }
4373 #else
4374 memset(g2h(vaddr), 0, blocklen);
4375 #endif
4376 }
4377
4378 /* Note that signed overflow is undefined in C. The following routines are
4379 careful to use unsigned types where modulo arithmetic is required.
4380 Failure to do so _will_ break on newer gcc. */
4381
4382 /* Signed saturating arithmetic. */
4383
4384 /* Perform 16-bit signed saturating addition. */
4385 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
4386 {
4387 uint16_t res;
4388
4389 res = a + b;
4390 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
4391 if (a & 0x8000)
4392 res = 0x8000;
4393 else
4394 res = 0x7fff;
4395 }
4396 return res;
4397 }
4398
4399 /* Perform 8-bit signed saturating addition. */
4400 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
4401 {
4402 uint8_t res;
4403
4404 res = a + b;
4405 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
4406 if (a & 0x80)
4407 res = 0x80;
4408 else
4409 res = 0x7f;
4410 }
4411 return res;
4412 }
4413
4414 /* Perform 16-bit signed saturating subtraction. */
4415 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
4416 {
4417 uint16_t res;
4418
4419 res = a - b;
4420 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
4421 if (a & 0x8000)
4422 res = 0x8000;
4423 else
4424 res = 0x7fff;
4425 }
4426 return res;
4427 }
4428
4429 /* Perform 8-bit signed saturating subtraction. */
4430 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
4431 {
4432 uint8_t res;
4433
4434 res = a - b;
4435 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
4436 if (a & 0x80)
4437 res = 0x80;
4438 else
4439 res = 0x7f;
4440 }
4441 return res;
4442 }
4443
4444 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4445 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4446 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
4447 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
4448 #define PFX q
4449
4450 #include "op_addsub.h"
4451
4452 /* Unsigned saturating arithmetic. */
4453 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
4454 {
4455 uint16_t res;
4456 res = a + b;
4457 if (res < a)
4458 res = 0xffff;
4459 return res;
4460 }
4461
4462 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
4463 {
4464 if (a > b)
4465 return a - b;
4466 else
4467 return 0;
4468 }
4469
4470 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
4471 {
4472 uint8_t res;
4473 res = a + b;
4474 if (res < a)
4475 res = 0xff;
4476 return res;
4477 }
4478
4479 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
4480 {
4481 if (a > b)
4482 return a - b;
4483 else
4484 return 0;
4485 }
4486
4487 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4488 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4489 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
4490 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
4491 #define PFX uq
4492
4493 #include "op_addsub.h"
4494
4495 /* Signed modulo arithmetic. */
4496 #define SARITH16(a, b, n, op) do { \
4497 int32_t sum; \
4498 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4499 RESULT(sum, n, 16); \
4500 if (sum >= 0) \
4501 ge |= 3 << (n * 2); \
4502 } while(0)
4503
4504 #define SARITH8(a, b, n, op) do { \
4505 int32_t sum; \
4506 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4507 RESULT(sum, n, 8); \
4508 if (sum >= 0) \
4509 ge |= 1 << n; \
4510 } while(0)
4511
4512
4513 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4514 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4515 #define ADD8(a, b, n) SARITH8(a, b, n, +)
4516 #define SUB8(a, b, n) SARITH8(a, b, n, -)
4517 #define PFX s
4518 #define ARITH_GE
4519
4520 #include "op_addsub.h"
4521
4522 /* Unsigned modulo arithmetic. */
4523 #define ADD16(a, b, n) do { \
4524 uint32_t sum; \
4525 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4526 RESULT(sum, n, 16); \
4527 if ((sum >> 16) == 1) \
4528 ge |= 3 << (n * 2); \
4529 } while(0)
4530
4531 #define ADD8(a, b, n) do { \
4532 uint32_t sum; \
4533 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4534 RESULT(sum, n, 8); \
4535 if ((sum >> 8) == 1) \
4536 ge |= 1 << n; \
4537 } while(0)
4538
4539 #define SUB16(a, b, n) do { \
4540 uint32_t sum; \
4541 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4542 RESULT(sum, n, 16); \
4543 if ((sum >> 16) == 0) \
4544 ge |= 3 << (n * 2); \
4545 } while(0)
4546
4547 #define SUB8(a, b, n) do { \
4548 uint32_t sum; \
4549 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4550 RESULT(sum, n, 8); \
4551 if ((sum >> 8) == 0) \
4552 ge |= 1 << n; \
4553 } while(0)
4554
4555 #define PFX u
4556 #define ARITH_GE
4557
4558 #include "op_addsub.h"
4559
4560 /* Halved signed arithmetic. */
4561 #define ADD16(a, b, n) \
4562 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4563 #define SUB16(a, b, n) \
4564 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4565 #define ADD8(a, b, n) \
4566 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4567 #define SUB8(a, b, n) \
4568 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4569 #define PFX sh
4570
4571 #include "op_addsub.h"
4572
4573 /* Halved unsigned arithmetic. */
4574 #define ADD16(a, b, n) \
4575 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4576 #define SUB16(a, b, n) \
4577 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4578 #define ADD8(a, b, n) \
4579 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4580 #define SUB8(a, b, n) \
4581 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4582 #define PFX uh
4583
4584 #include "op_addsub.h"
4585
4586 static inline uint8_t do_usad(uint8_t a, uint8_t b)
4587 {
4588 if (a > b)
4589 return a - b;
4590 else
4591 return b - a;
4592 }
4593
4594 /* Unsigned sum of absolute byte differences. */
4595 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
4596 {
4597 uint32_t sum;
4598 sum = do_usad(a, b);
4599 sum += do_usad(a >> 8, b >> 8);
4600 sum += do_usad(a >> 16, b >>16);
4601 sum += do_usad(a >> 24, b >> 24);
4602 return sum;
4603 }
4604
4605 /* For ARMv6 SEL instruction. */
4606 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
4607 {
4608 uint32_t mask;
4609
4610 mask = 0;
4611 if (flags & 1)
4612 mask |= 0xff;
4613 if (flags & 2)
4614 mask |= 0xff00;
4615 if (flags & 4)
4616 mask |= 0xff0000;
4617 if (flags & 8)
4618 mask |= 0xff000000;
4619 return (a & mask) | (b & ~mask);
4620 }
4621
4622 /* VFP support. We follow the convention used for VFP instructions:
4623 Single precision routines have a "s" suffix, double precision a
4624 "d" suffix. */
4625
4626 /* Convert host exception flags to vfp form. */
4627 static inline int vfp_exceptbits_from_host(int host_bits)
4628 {
4629 int target_bits = 0;
4630
4631 if (host_bits & float_flag_invalid)
4632 target_bits |= 1;
4633 if (host_bits & float_flag_divbyzero)
4634 target_bits |= 2;
4635 if (host_bits & float_flag_overflow)
4636 target_bits |= 4;
4637 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4638 target_bits |= 8;
4639 if (host_bits & float_flag_inexact)
4640 target_bits |= 0x10;
4641 if (host_bits & float_flag_input_denormal)
4642 target_bits |= 0x80;
4643 return target_bits;
4644 }
4645
4646 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4647 {
4648 int i;
4649 uint32_t fpscr;
4650
4651 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4652 | (env->vfp.vec_len << 16)
4653 | (env->vfp.vec_stride << 20);
4654 i = get_float_exception_flags(&env->vfp.fp_status);
4655 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4656 fpscr |= vfp_exceptbits_from_host(i);
4657 return fpscr;
4658 }
4659
4660 uint32_t vfp_get_fpscr(CPUARMState *env)
4661 {
4662 return HELPER(vfp_get_fpscr)(env);
4663 }
4664
4665 /* Convert vfp exception flags to target form. */
4666 static inline int vfp_exceptbits_to_host(int target_bits)
4667 {
4668 int host_bits = 0;
4669
4670 if (target_bits & 1)
4671 host_bits |= float_flag_invalid;
4672 if (target_bits & 2)
4673 host_bits |= float_flag_divbyzero;
4674 if (target_bits & 4)
4675 host_bits |= float_flag_overflow;
4676 if (target_bits & 8)
4677 host_bits |= float_flag_underflow;
4678 if (target_bits & 0x10)
4679 host_bits |= float_flag_inexact;
4680 if (target_bits & 0x80)
4681 host_bits |= float_flag_input_denormal;
4682 return host_bits;
4683 }
4684
4685 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4686 {
4687 int i;
4688 uint32_t changed;
4689
4690 changed = env->vfp.xregs[ARM_VFP_FPSCR];
4691 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4692 env->vfp.vec_len = (val >> 16) & 7;
4693 env->vfp.vec_stride = (val >> 20) & 3;
4694
4695 changed ^= val;
4696 if (changed & (3 << 22)) {
4697 i = (val >> 22) & 3;
4698 switch (i) {
4699 case FPROUNDING_TIEEVEN:
4700 i = float_round_nearest_even;
4701 break;
4702 case FPROUNDING_POSINF:
4703 i = float_round_up;
4704 break;
4705 case FPROUNDING_NEGINF:
4706 i = float_round_down;
4707 break;
4708 case FPROUNDING_ZERO:
4709 i = float_round_to_zero;
4710 break;
4711 }
4712 set_float_rounding_mode(i, &env->vfp.fp_status);
4713 }
4714 if (changed & (1 << 24)) {
4715 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4716 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4717 }
4718 if (changed & (1 << 25))
4719 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4720
4721 i = vfp_exceptbits_to_host(val);
4722 set_float_exception_flags(i, &env->vfp.fp_status);
4723 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4724 }
4725
4726 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4727 {
4728 HELPER(vfp_set_fpscr)(env, val);
4729 }
4730
4731 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4732
4733 #define VFP_BINOP(name) \
4734 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4735 { \
4736 float_status *fpst = fpstp; \
4737 return float32_ ## name(a, b, fpst); \
4738 } \
4739 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4740 { \
4741 float_status *fpst = fpstp; \
4742 return float64_ ## name(a, b, fpst); \
4743 }
4744 VFP_BINOP(add)
4745 VFP_BINOP(sub)
4746 VFP_BINOP(mul)
4747 VFP_BINOP(div)
4748 VFP_BINOP(min)
4749 VFP_BINOP(max)
4750 VFP_BINOP(minnum)
4751 VFP_BINOP(maxnum)
4752 #undef VFP_BINOP
4753
4754 float32 VFP_HELPER(neg, s)(float32 a)
4755 {
4756 return float32_chs(a);
4757 }
4758
4759 float64 VFP_HELPER(neg, d)(float64 a)
4760 {
4761 return float64_chs(a);
4762 }
4763
4764 float32 VFP_HELPER(abs, s)(float32 a)
4765 {
4766 return float32_abs(a);
4767 }
4768
4769 float64 VFP_HELPER(abs, d)(float64 a)
4770 {
4771 return float64_abs(a);
4772 }
4773
4774 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4775 {
4776 return float32_sqrt(a, &env->vfp.fp_status);
4777 }
4778
4779 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4780 {
4781 return float64_sqrt(a, &env->vfp.fp_status);
4782 }
4783
4784 /* XXX: check quiet/signaling case */
4785 #define DO_VFP_cmp(p, type) \
4786 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4787 { \
4788 uint32_t flags; \
4789 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4790 case 0: flags = 0x6; break; \
4791 case -1: flags = 0x8; break; \
4792 case 1: flags = 0x2; break; \
4793 default: case 2: flags = 0x3; break; \
4794 } \
4795 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4796 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4797 } \
4798 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4799 { \
4800 uint32_t flags; \
4801 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4802 case 0: flags = 0x6; break; \
4803 case -1: flags = 0x8; break; \
4804 case 1: flags = 0x2; break; \
4805 default: case 2: flags = 0x3; break; \
4806 } \
4807 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4808 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4809 }
4810 DO_VFP_cmp(s, float32)
4811 DO_VFP_cmp(d, float64)
4812 #undef DO_VFP_cmp
4813
4814 /* Integer to float and float to integer conversions */
4815
4816 #define CONV_ITOF(name, fsz, sign) \
4817 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4818 { \
4819 float_status *fpst = fpstp; \
4820 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4821 }
4822
4823 #define CONV_FTOI(name, fsz, sign, round) \
4824 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4825 { \
4826 float_status *fpst = fpstp; \
4827 if (float##fsz##_is_any_nan(x)) { \
4828 float_raise(float_flag_invalid, fpst); \
4829 return 0; \
4830 } \
4831 return float##fsz##_to_##sign##int32##round(x, fpst); \
4832 }
4833
4834 #define FLOAT_CONVS(name, p, fsz, sign) \
4835 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4836 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4837 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4838
4839 FLOAT_CONVS(si, s, 32, )
4840 FLOAT_CONVS(si, d, 64, )
4841 FLOAT_CONVS(ui, s, 32, u)
4842 FLOAT_CONVS(ui, d, 64, u)
4843
4844 #undef CONV_ITOF
4845 #undef CONV_FTOI
4846 #undef FLOAT_CONVS
4847
4848 /* floating point conversion */
4849 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4850 {
4851 float64 r = float32_to_float64(x, &env->vfp.fp_status);
4852 /* ARM requires that S<->D conversion of any kind of NaN generates
4853 * a quiet NaN by forcing the most significant frac bit to 1.
4854 */
4855 return float64_maybe_silence_nan(r);
4856 }
4857
4858 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4859 {
4860 float32 r = float64_to_float32(x, &env->vfp.fp_status);
4861 /* ARM requires that S<->D conversion of any kind of NaN generates
4862 * a quiet NaN by forcing the most significant frac bit to 1.
4863 */
4864 return float32_maybe_silence_nan(r);
4865 }
4866
4867 /* VFP3 fixed point conversion. */
4868 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4869 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
4870 void *fpstp) \
4871 { \
4872 float_status *fpst = fpstp; \
4873 float##fsz tmp; \
4874 tmp = itype##_to_##float##fsz(x, fpst); \
4875 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4876 }
4877
4878 /* Notice that we want only input-denormal exception flags from the
4879 * scalbn operation: the other possible flags (overflow+inexact if
4880 * we overflow to infinity, output-denormal) aren't correct for the
4881 * complete scale-and-convert operation.
4882 */
4883 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4884 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4885 uint32_t shift, \
4886 void *fpstp) \
4887 { \
4888 float_status *fpst = fpstp; \
4889 int old_exc_flags = get_float_exception_flags(fpst); \
4890 float##fsz tmp; \
4891 if (float##fsz##_is_any_nan(x)) { \
4892 float_raise(float_flag_invalid, fpst); \
4893 return 0; \
4894 } \
4895 tmp = float##fsz##_scalbn(x, shift, fpst); \
4896 old_exc_flags |= get_float_exception_flags(fpst) \
4897 & float_flag_input_denormal; \
4898 set_float_exception_flags(old_exc_flags, fpst); \
4899 return float##fsz##_to_##itype##round(tmp, fpst); \
4900 }
4901
4902 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
4903 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4904 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4905 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4906
4907 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
4908 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4909 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4910
4911 VFP_CONV_FIX(sh, d, 64, 64, int16)
4912 VFP_CONV_FIX(sl, d, 64, 64, int32)
4913 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
4914 VFP_CONV_FIX(uh, d, 64, 64, uint16)
4915 VFP_CONV_FIX(ul, d, 64, 64, uint32)
4916 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
4917 VFP_CONV_FIX(sh, s, 32, 32, int16)
4918 VFP_CONV_FIX(sl, s, 32, 32, int32)
4919 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
4920 VFP_CONV_FIX(uh, s, 32, 32, uint16)
4921 VFP_CONV_FIX(ul, s, 32, 32, uint32)
4922 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
4923 #undef VFP_CONV_FIX
4924 #undef VFP_CONV_FIX_FLOAT
4925 #undef VFP_CONV_FLOAT_FIX_ROUND
4926
4927 /* Set the current fp rounding mode and return the old one.
4928 * The argument is a softfloat float_round_ value.
4929 */
4930 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
4931 {
4932 float_status *fp_status = &env->vfp.fp_status;
4933
4934 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4935 set_float_rounding_mode(rmode, fp_status);
4936
4937 return prev_rmode;
4938 }
4939
4940 /* Set the current fp rounding mode in the standard fp status and return
4941 * the old one. This is for NEON instructions that need to change the
4942 * rounding mode but wish to use the standard FPSCR values for everything
4943 * else. Always set the rounding mode back to the correct value after
4944 * modifying it.
4945 * The argument is a softfloat float_round_ value.
4946 */
4947 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
4948 {
4949 float_status *fp_status = &env->vfp.standard_fp_status;
4950
4951 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4952 set_float_rounding_mode(rmode, fp_status);
4953
4954 return prev_rmode;
4955 }
4956
4957 /* Half precision conversions. */
4958 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4959 {
4960 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4961 float32 r = float16_to_float32(make_float16(a), ieee, s);
4962 if (ieee) {
4963 return float32_maybe_silence_nan(r);
4964 }
4965 return r;
4966 }
4967
4968 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
4969 {
4970 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4971 float16 r = float32_to_float16(a, ieee, s);
4972 if (ieee) {
4973 r = float16_maybe_silence_nan(r);
4974 }
4975 return float16_val(r);
4976 }
4977
4978 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4979 {
4980 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4981 }
4982
4983 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4984 {
4985 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4986 }
4987
4988 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4989 {
4990 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4991 }
4992
4993 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4994 {
4995 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4996 }
4997
4998 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
4999 {
5000 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5001 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
5002 if (ieee) {
5003 return float64_maybe_silence_nan(r);
5004 }
5005 return r;
5006 }
5007
5008 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
5009 {
5010 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5011 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
5012 if (ieee) {
5013 r = float16_maybe_silence_nan(r);
5014 }
5015 return float16_val(r);
5016 }
5017
5018 #define float32_two make_float32(0x40000000)
5019 #define float32_three make_float32(0x40400000)
5020 #define float32_one_point_five make_float32(0x3fc00000)
5021
5022 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
5023 {
5024 float_status *s = &env->vfp.standard_fp_status;
5025 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5026 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5027 if (!(float32_is_zero(a) || float32_is_zero(b))) {
5028 float_raise(float_flag_input_denormal, s);
5029 }
5030 return float32_two;
5031 }
5032 return float32_sub(float32_two, float32_mul(a, b, s), s);
5033 }
5034
5035 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
5036 {
5037 float_status *s = &env->vfp.standard_fp_status;
5038 float32 product;
5039 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5040 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5041 if (!(float32_is_zero(a) || float32_is_zero(b))) {
5042 float_raise(float_flag_input_denormal, s);
5043 }
5044 return float32_one_point_five;
5045 }
5046 product = float32_mul(a, b, s);
5047 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
5048 }
5049
5050 /* NEON helpers. */
5051
5052 /* Constants 256 and 512 are used in some helpers; we avoid relying on
5053 * int->float conversions at run-time. */
5054 #define float64_256 make_float64(0x4070000000000000LL)
5055 #define float64_512 make_float64(0x4080000000000000LL)
5056 #define float32_maxnorm make_float32(0x7f7fffff)
5057 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
5058
5059 /* Reciprocal functions
5060 *
5061 * The algorithm that must be used to calculate the estimate
5062 * is specified by the ARM ARM, see FPRecipEstimate()
5063 */
5064
5065 static float64 recip_estimate(float64 a, float_status *real_fp_status)
5066 {
5067 /* These calculations mustn't set any fp exception flags,
5068 * so we use a local copy of the fp_status.
5069 */
5070 float_status dummy_status = *real_fp_status;
5071 float_status *s = &dummy_status;
5072 /* q = (int)(a * 512.0) */
5073 float64 q = float64_mul(float64_512, a, s);
5074 int64_t q_int = float64_to_int64_round_to_zero(q, s);
5075
5076 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
5077 q = int64_to_float64(q_int, s);
5078 q = float64_add(q, float64_half, s);
5079 q = float64_div(q, float64_512, s);
5080 q = float64_div(float64_one, q, s);
5081
5082 /* s = (int)(256.0 * r + 0.5) */
5083 q = float64_mul(q, float64_256, s);
5084 q = float64_add(q, float64_half, s);
5085 q_int = float64_to_int64_round_to_zero(q, s);
5086
5087 /* return (double)s / 256.0 */
5088 return float64_div(int64_to_float64(q_int, s), float64_256, s);
5089 }
5090
5091 /* Common wrapper to call recip_estimate */
5092 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
5093 {
5094 uint64_t val64 = float64_val(num);
5095 uint64_t frac = extract64(val64, 0, 52);
5096 int64_t exp = extract64(val64, 52, 11);
5097 uint64_t sbit;
5098 float64 scaled, estimate;
5099
5100 /* Generate the scaled number for the estimate function */
5101 if (exp == 0) {
5102 if (extract64(frac, 51, 1) == 0) {
5103 exp = -1;
5104 frac = extract64(frac, 0, 50) << 2;
5105 } else {
5106 frac = extract64(frac, 0, 51) << 1;
5107 }
5108 }
5109
5110 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
5111 scaled = make_float64((0x3feULL << 52)
5112 | extract64(frac, 44, 8) << 44);
5113
5114 estimate = recip_estimate(scaled, fpst);
5115
5116 /* Build new result */
5117 val64 = float64_val(estimate);
5118 sbit = 0x8000000000000000ULL & val64;
5119 exp = off - exp;
5120 frac = extract64(val64, 0, 52);
5121
5122 if (exp == 0) {
5123 frac = 1ULL << 51 | extract64(frac, 1, 51);
5124 } else if (exp == -1) {
5125 frac = 1ULL << 50 | extract64(frac, 2, 50);
5126 exp = 0;
5127 }
5128
5129 return make_float64(sbit | (exp << 52) | frac);
5130 }
5131
5132 static bool round_to_inf(float_status *fpst, bool sign_bit)
5133 {
5134 switch (fpst->float_rounding_mode) {
5135 case float_round_nearest_even: /* Round to Nearest */
5136 return true;
5137 case float_round_up: /* Round to +Inf */
5138 return !sign_bit;
5139 case float_round_down: /* Round to -Inf */
5140 return sign_bit;
5141 case float_round_to_zero: /* Round to Zero */
5142 return false;
5143 }
5144
5145 g_assert_not_reached();
5146 }
5147
5148 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
5149 {
5150 float_status *fpst = fpstp;
5151 float32 f32 = float32_squash_input_denormal(input, fpst);
5152 uint32_t f32_val = float32_val(f32);
5153 uint32_t f32_sbit = 0x80000000ULL & f32_val;
5154 int32_t f32_exp = extract32(f32_val, 23, 8);
5155 uint32_t f32_frac = extract32(f32_val, 0, 23);
5156 float64 f64, r64;
5157 uint64_t r64_val;
5158 int64_t r64_exp;
5159 uint64_t r64_frac;
5160
5161 if (float32_is_any_nan(f32)) {
5162 float32 nan = f32;
5163 if (float32_is_signaling_nan(f32)) {
5164 float_raise(float_flag_invalid, fpst);
5165 nan = float32_maybe_silence_nan(f32);
5166 }
5167 if (fpst->default_nan_mode) {
5168 nan = float32_default_nan;
5169 }
5170 return nan;
5171 } else if (float32_is_infinity(f32)) {
5172 return float32_set_sign(float32_zero, float32_is_neg(f32));
5173 } else if (float32_is_zero(f32)) {
5174 float_raise(float_flag_divbyzero, fpst);
5175 return float32_set_sign(float32_infinity, float32_is_neg(f32));
5176 } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
5177 /* Abs(value) < 2.0^-128 */
5178 float_raise(float_flag_overflow | float_flag_inexact, fpst);
5179 if (round_to_inf(fpst, f32_sbit)) {
5180 return float32_set_sign(float32_infinity, float32_is_neg(f32));
5181 } else {
5182 return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
5183 }
5184 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
5185 float_raise(float_flag_underflow, fpst);
5186 return float32_set_sign(float32_zero, float32_is_neg(f32));
5187 }
5188
5189
5190 f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
5191 r64 = call_recip_estimate(f64, 253, fpst);
5192 r64_val = float64_val(r64);
5193 r64_exp = extract64(r64_val, 52, 11);
5194 r64_frac = extract64(r64_val, 0, 52);
5195
5196 /* result = sign : result_exp<7:0> : fraction<51:29>; */
5197 return make_float32(f32_sbit |
5198 (r64_exp & 0xff) << 23 |
5199 extract64(r64_frac, 29, 24));
5200 }
5201
5202 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
5203 {
5204 float_status *fpst = fpstp;
5205 float64 f64 = float64_squash_input_denormal(input, fpst);
5206 uint64_t f64_val = float64_val(f64);
5207 uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
5208 int64_t f64_exp = extract64(f64_val, 52, 11);
5209 float64 r64;
5210 uint64_t r64_val;
5211 int64_t r64_exp;
5212 uint64_t r64_frac;
5213
5214 /* Deal with any special cases */
5215 if (float64_is_any_nan(f64)) {
5216 float64 nan = f64;
5217 if (float64_is_signaling_nan(f64)) {
5218 float_raise(float_flag_invalid, fpst);
5219 nan = float64_maybe_silence_nan(f64);
5220 }
5221 if (fpst->default_nan_mode) {
5222 nan = float64_default_nan;
5223 }
5224 return nan;
5225 } else if (float64_is_infinity(f64)) {
5226 return float64_set_sign(float64_zero, float64_is_neg(f64));
5227 } else if (float64_is_zero(f64)) {
5228 float_raise(float_flag_divbyzero, fpst);
5229 return float64_set_sign(float64_infinity, float64_is_neg(f64));
5230 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
5231 /* Abs(value) < 2.0^-1024 */
5232 float_raise(float_flag_overflow | float_flag_inexact, fpst);
5233 if (round_to_inf(fpst, f64_sbit)) {
5234 return float64_set_sign(float64_infinity, float64_is_neg(f64));
5235 } else {
5236 return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
5237 }
5238 } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
5239 float_raise(float_flag_underflow, fpst);
5240 return float64_set_sign(float64_zero, float64_is_neg(f64));
5241 }
5242
5243 r64 = call_recip_estimate(f64, 2045, fpst);
5244 r64_val = float64_val(r64);
5245 r64_exp = extract64(r64_val, 52, 11);
5246 r64_frac = extract64(r64_val, 0, 52);
5247
5248 /* result = sign : result_exp<10:0> : fraction<51:0> */
5249 return make_float64(f64_sbit |
5250 ((r64_exp & 0x7ff) << 52) |
5251 r64_frac);
5252 }
5253
5254 /* The algorithm that must be used to calculate the estimate
5255 * is specified by the ARM ARM.
5256 */
5257 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
5258 {
5259 /* These calculations mustn't set any fp exception flags,
5260 * so we use a local copy of the fp_status.
5261 */
5262 float_status dummy_status = *real_fp_status;
5263 float_status *s = &dummy_status;
5264 float64 q;
5265 int64_t q_int;
5266
5267 if (float64_lt(a, float64_half, s)) {
5268 /* range 0.25 <= a < 0.5 */
5269
5270 /* a in units of 1/512 rounded down */
5271 /* q0 = (int)(a * 512.0); */
5272 q = float64_mul(float64_512, a, s);
5273 q_int = float64_to_int64_round_to_zero(q, s);
5274
5275 /* reciprocal root r */
5276 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
5277 q = int64_to_float64(q_int, s);
5278 q = float64_add(q, float64_half, s);
5279 q = float64_div(q, float64_512, s);
5280 q = float64_sqrt(q, s);
5281 q = float64_div(float64_one, q, s);
5282 } else {
5283 /* range 0.5 <= a < 1.0 */
5284
5285 /* a in units of 1/256 rounded down */
5286 /* q1 = (int)(a * 256.0); */
5287 q = float64_mul(float64_256, a, s);
5288 int64_t q_int = float64_to_int64_round_to_zero(q, s);
5289
5290 /* reciprocal root r */
5291 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5292 q = int64_to_float64(q_int, s);
5293 q = float64_add(q, float64_half, s);
5294 q = float64_div(q, float64_256, s);
5295 q = float64_sqrt(q, s);
5296 q = float64_div(float64_one, q, s);
5297 }
5298 /* r in units of 1/256 rounded to nearest */
5299 /* s = (int)(256.0 * r + 0.5); */
5300
5301 q = float64_mul(q, float64_256,s );
5302 q = float64_add(q, float64_half, s);
5303 q_int = float64_to_int64_round_to_zero(q, s);
5304
5305 /* return (double)s / 256.0;*/
5306 return float64_div(int64_to_float64(q_int, s), float64_256, s);
5307 }
5308
5309 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
5310 {
5311 float_status *s = fpstp;
5312 float32 f32 = float32_squash_input_denormal(input, s);
5313 uint32_t val = float32_val(f32);
5314 uint32_t f32_sbit = 0x80000000 & val;
5315 int32_t f32_exp = extract32(val, 23, 8);
5316 uint32_t f32_frac = extract32(val, 0, 23);
5317 uint64_t f64_frac;
5318 uint64_t val64;
5319 int result_exp;
5320 float64 f64;
5321
5322 if (float32_is_any_nan(f32)) {
5323 float32 nan = f32;
5324 if (float32_is_signaling_nan(f32)) {
5325 float_raise(float_flag_invalid, s);
5326 nan = float32_maybe_silence_nan(f32);
5327 }
5328 if (s->default_nan_mode) {
5329 nan = float32_default_nan;
5330 }
5331 return nan;
5332 } else if (float32_is_zero(f32)) {
5333 float_raise(float_flag_divbyzero, s);
5334 return float32_set_sign(float32_infinity, float32_is_neg(f32));
5335 } else if (float32_is_neg(f32)) {
5336 float_raise(float_flag_invalid, s);
5337 return float32_default_nan;
5338 } else if (float32_is_infinity(f32)) {
5339 return float32_zero;
5340 }
5341
5342 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5343 * preserving the parity of the exponent. */
5344
5345 f64_frac = ((uint64_t) f32_frac) << 29;
5346 if (f32_exp == 0) {
5347 while (extract64(f64_frac, 51, 1) == 0) {
5348 f64_frac = f64_frac << 1;
5349 f32_exp = f32_exp-1;
5350 }
5351 f64_frac = extract64(f64_frac, 0, 51) << 1;
5352 }
5353
5354 if (extract64(f32_exp, 0, 1) == 0) {
5355 f64 = make_float64(((uint64_t) f32_sbit) << 32
5356 | (0x3feULL << 52)
5357 | f64_frac);
5358 } else {
5359 f64 = make_float64(((uint64_t) f32_sbit) << 32
5360 | (0x3fdULL << 52)
5361 | f64_frac);
5362 }
5363
5364 result_exp = (380 - f32_exp) / 2;
5365
5366 f64 = recip_sqrt_estimate(f64, s);
5367
5368 val64 = float64_val(f64);
5369
5370 val = ((result_exp & 0xff) << 23)
5371 | ((val64 >> 29) & 0x7fffff);
5372 return make_float32(val);
5373 }
5374
5375 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
5376 {
5377 float_status *s = fpstp;
5378 float64 f64 = float64_squash_input_denormal(input, s);
5379 uint64_t val = float64_val(f64);
5380 uint64_t f64_sbit = 0x8000000000000000ULL & val;
5381 int64_t f64_exp = extract64(val, 52, 11);
5382 uint64_t f64_frac = extract64(val, 0, 52);
5383 int64_t result_exp;
5384 uint64_t result_frac;
5385
5386 if (float64_is_any_nan(f64)) {
5387 float64 nan = f64;
5388 if (float64_is_signaling_nan(f64)) {
5389 float_raise(float_flag_invalid, s);
5390 nan = float64_maybe_silence_nan(f64);
5391 }
5392 if (s->default_nan_mode) {
5393 nan = float64_default_nan;
5394 }
5395 return nan;
5396 } else if (float64_is_zero(f64)) {
5397 float_raise(float_flag_divbyzero, s);
5398 return float64_set_sign(float64_infinity, float64_is_neg(f64));
5399 } else if (float64_is_neg(f64)) {
5400 float_raise(float_flag_invalid, s);
5401 return float64_default_nan;
5402 } else if (float64_is_infinity(f64)) {
5403 return float64_zero;
5404 }
5405
5406 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5407 * preserving the parity of the exponent. */
5408
5409 if (f64_exp == 0) {
5410 while (extract64(f64_frac, 51, 1) == 0) {
5411 f64_frac = f64_frac << 1;
5412 f64_exp = f64_exp - 1;
5413 }
5414 f64_frac = extract64(f64_frac, 0, 51) << 1;
5415 }
5416
5417 if (extract64(f64_exp, 0, 1) == 0) {
5418 f64 = make_float64(f64_sbit
5419 | (0x3feULL << 52)
5420 | f64_frac);
5421 } else {
5422 f64 = make_float64(f64_sbit
5423 | (0x3fdULL << 52)
5424 | f64_frac);
5425 }
5426
5427 result_exp = (3068 - f64_exp) / 2;
5428
5429 f64 = recip_sqrt_estimate(f64, s);
5430
5431 result_frac = extract64(float64_val(f64), 0, 52);
5432
5433 return make_float64(f64_sbit |
5434 ((result_exp & 0x7ff) << 52) |
5435 result_frac);
5436 }
5437
5438 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
5439 {
5440 float_status *s = fpstp;
5441 float64 f64;
5442
5443 if ((a & 0x80000000) == 0) {
5444 return 0xffffffff;
5445 }
5446
5447 f64 = make_float64((0x3feULL << 52)
5448 | ((int64_t)(a & 0x7fffffff) << 21));
5449
5450 f64 = recip_estimate(f64, s);
5451
5452 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5453 }
5454
5455 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
5456 {
5457 float_status *fpst = fpstp;
5458 float64 f64;
5459
5460 if ((a & 0xc0000000) == 0) {
5461 return 0xffffffff;
5462 }
5463
5464 if (a & 0x80000000) {
5465 f64 = make_float64((0x3feULL << 52)
5466 | ((uint64_t)(a & 0x7fffffff) << 21));
5467 } else { /* bits 31-30 == '01' */
5468 f64 = make_float64((0x3fdULL << 52)
5469 | ((uint64_t)(a & 0x3fffffff) << 22));
5470 }
5471
5472 f64 = recip_sqrt_estimate(f64, fpst);
5473
5474 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5475 }
5476
5477 /* VFPv4 fused multiply-accumulate */
5478 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
5479 {
5480 float_status *fpst = fpstp;
5481 return float32_muladd(a, b, c, 0, fpst);
5482 }
5483
5484 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
5485 {
5486 float_status *fpst = fpstp;
5487 return float64_muladd(a, b, c, 0, fpst);
5488 }
5489
5490 /* ARMv8 round to integral */
5491 float32 HELPER(rints_exact)(float32 x, void *fp_status)
5492 {
5493 return float32_round_to_int(x, fp_status);
5494 }
5495
5496 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
5497 {
5498 return float64_round_to_int(x, fp_status);
5499 }
5500
5501 float32 HELPER(rints)(float32 x, void *fp_status)
5502 {
5503 int old_flags = get_float_exception_flags(fp_status), new_flags;
5504 float32 ret;
5505
5506 ret = float32_round_to_int(x, fp_status);
5507
5508 /* Suppress any inexact exceptions the conversion produced */
5509 if (!(old_flags & float_flag_inexact)) {
5510 new_flags = get_float_exception_flags(fp_status);
5511 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5512 }
5513
5514 return ret;
5515 }
5516
5517 float64 HELPER(rintd)(float64 x, void *fp_status)
5518 {
5519 int old_flags = get_float_exception_flags(fp_status), new_flags;
5520 float64 ret;
5521
5522 ret = float64_round_to_int(x, fp_status);
5523
5524 new_flags = get_float_exception_flags(fp_status);
5525
5526 /* Suppress any inexact exceptions the conversion produced */
5527 if (!(old_flags & float_flag_inexact)) {
5528 new_flags = get_float_exception_flags(fp_status);
5529 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5530 }
5531
5532 return ret;
5533 }
5534
5535 /* Convert ARM rounding mode to softfloat */
5536 int arm_rmode_to_sf(int rmode)
5537 {
5538 switch (rmode) {
5539 case FPROUNDING_TIEAWAY:
5540 rmode = float_round_ties_away;
5541 break;
5542 case FPROUNDING_ODD:
5543 /* FIXME: add support for TIEAWAY and ODD */
5544 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
5545 rmode);
5546 case FPROUNDING_TIEEVEN:
5547 default:
5548 rmode = float_round_nearest_even;
5549 break;
5550 case FPROUNDING_POSINF:
5551 rmode = float_round_up;
5552 break;
5553 case FPROUNDING_NEGINF:
5554 rmode = float_round_down;
5555 break;
5556 case FPROUNDING_ZERO:
5557 rmode = float_round_to_zero;
5558 break;
5559 }
5560 return rmode;
5561 }
5562
5563 static void crc_init_buffer(uint8_t *buf, uint32_t val, uint32_t bytes)
5564 {
5565 memset(buf, 0, 4);
5566
5567 if (bytes == 1) {
5568 buf[0] = val & 0xff;
5569 } else if (bytes == 2) {
5570 buf[0] = val & 0xff;
5571 buf[1] = (val >> 8) & 0xff;
5572 } else {
5573 buf[0] = val & 0xff;
5574 buf[1] = (val >> 8) & 0xff;
5575 buf[2] = (val >> 16) & 0xff;
5576 buf[3] = (val >> 24) & 0xff;
5577 }
5578 }
5579
5580 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
5581 {
5582 uint8_t buf[4];
5583
5584 crc_init_buffer(buf, val, bytes);
5585
5586 /* zlib crc32 converts the accumulator and output to one's complement. */
5587 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
5588 }
5589
5590 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
5591 {
5592 uint8_t buf[4];
5593
5594 crc_init_buffer(buf, val, bytes);
5595
5596 /* Linux crc32c converts the output to one's complement. */
5597 return crc32c(acc, buf, bytes) ^ 0xffffffff;
5598 }