2 #include "exec/gdbstub.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/sysemu.h"
6 #include "qemu/bitops.h"
8 #ifndef CONFIG_USER_ONLY
9 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
10 int access_type
, int is_user
,
11 hwaddr
*phys_ptr
, int *prot
,
12 target_ulong
*page_size
);
15 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
19 /* VFP data registers are always little-endian. */
20 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
22 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
25 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
26 /* Aliases for Q regs. */
29 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
30 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
34 switch (reg
- nregs
) {
35 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
36 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
37 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
42 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
46 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
48 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
51 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
54 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
55 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
59 switch (reg
- nregs
) {
60 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
61 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
62 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
67 static int raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
70 *value
= CPREG_FIELD32(env
, ri
);
74 static int raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
77 CPREG_FIELD32(env
, ri
) = value
;
81 static bool read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
84 /* Raw read of a coprocessor register (as needed for migration, etc)
85 * return true on success, false if the read is impossible for some reason.
87 if (ri
->type
& ARM_CP_CONST
) {
89 } else if (ri
->raw_readfn
) {
90 return (ri
->raw_readfn(env
, ri
, v
) == 0);
91 } else if (ri
->readfn
) {
92 return (ri
->readfn(env
, ri
, v
) == 0);
94 if (ri
->type
& ARM_CP_64BIT
) {
95 *v
= CPREG_FIELD64(env
, ri
);
97 *v
= CPREG_FIELD32(env
, ri
);
103 static bool write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
106 /* Raw write of a coprocessor register (as needed for migration, etc).
107 * Return true on success, false if the write is impossible for some reason.
108 * Note that constant registers are treated as write-ignored; the
109 * caller should check for success by whether a readback gives the
112 if (ri
->type
& ARM_CP_CONST
) {
114 } else if (ri
->raw_writefn
) {
115 return (ri
->raw_writefn(env
, ri
, v
) == 0);
116 } else if (ri
->writefn
) {
117 return (ri
->writefn(env
, ri
, v
) == 0);
119 if (ri
->type
& ARM_CP_64BIT
) {
120 CPREG_FIELD64(env
, ri
) = v
;
122 CPREG_FIELD32(env
, ri
) = v
;
128 bool write_cpustate_to_list(ARMCPU
*cpu
)
130 /* Write the coprocessor state from cpu->env to the (index,value) list. */
134 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
135 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
136 const ARMCPRegInfo
*ri
;
138 ri
= get_arm_cp_reginfo(cpu
, regidx
);
143 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
146 if (!read_raw_cp_reg(&cpu
->env
, ri
, &v
)) {
150 cpu
->cpreg_values
[i
] = v
;
155 bool write_list_to_cpustate(ARMCPU
*cpu
)
160 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
161 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
162 uint64_t v
= cpu
->cpreg_values
[i
];
164 const ARMCPRegInfo
*ri
;
166 ri
= get_arm_cp_reginfo(cpu
, regidx
);
171 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
174 /* Write value and confirm it reads back as written
175 * (to catch read-only registers and partially read-only
176 * registers where the incoming migration value doesn't match)
178 if (!write_raw_cp_reg(&cpu
->env
, ri
, v
) ||
179 !read_raw_cp_reg(&cpu
->env
, ri
, &readback
) ||
187 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
189 ARMCPU
*cpu
= opaque
;
191 const ARMCPRegInfo
*ri
;
193 regidx
= *(uint32_t *)key
;
194 ri
= get_arm_cp_reginfo(cpu
, regidx
);
196 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
197 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
198 /* The value array need not be initialized at this point */
199 cpu
->cpreg_array_len
++;
203 static void count_cpreg(gpointer key
, gpointer opaque
)
205 ARMCPU
*cpu
= opaque
;
207 const ARMCPRegInfo
*ri
;
209 regidx
= *(uint32_t *)key
;
210 ri
= get_arm_cp_reginfo(cpu
, regidx
);
212 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
213 cpu
->cpreg_array_len
++;
217 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
219 uint32_t aidx
= *(uint32_t *)a
;
220 uint32_t bidx
= *(uint32_t *)b
;
225 void init_cpreg_list(ARMCPU
*cpu
)
227 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
228 * Note that we require cpreg_tuples[] to be sorted by key ID.
233 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
234 keys
= g_list_sort(keys
, cpreg_key_compare
);
236 cpu
->cpreg_array_len
= 0;
238 g_list_foreach(keys
, count_cpreg
, cpu
);
240 arraylen
= cpu
->cpreg_array_len
;
241 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
242 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
243 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
244 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
245 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
246 cpu
->cpreg_array_len
= 0;
248 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
250 assert(cpu
->cpreg_array_len
== arraylen
);
255 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
257 env
->cp15
.c3
= value
;
258 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
262 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
264 if (env
->cp15
.c13_fcse
!= value
) {
265 /* Unlike real hardware the qemu TLB uses virtual addresses,
266 * not modified virtual addresses, so this causes a TLB flush.
269 env
->cp15
.c13_fcse
= value
;
273 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
276 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
277 /* For VMSA (when not using the LPAE long descriptor page table
278 * format) this register includes the ASID, so do a TLB flush.
279 * For PMSA it is purely a process ID and no action is needed.
283 env
->cp15
.c13_context
= value
;
287 static int tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
290 /* Invalidate all (TLBIALL) */
295 static int tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
298 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
299 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
303 static int tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
306 /* Invalidate by ASID (TLBIASID) */
307 tlb_flush(env
, value
== 0);
311 static int tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
314 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
315 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
319 static const ARMCPRegInfo cp_reginfo
[] = {
320 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
321 * version" bits will read as a reserved value, which should cause
322 * Linux to not try to use the debug hardware.
324 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
325 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
326 /* MMU Domain access control / MPU write buffer control */
327 { .name
= "DACR", .cp
= 15,
328 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
329 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
330 .resetvalue
= 0, .writefn
= dacr_write
, .raw_writefn
= raw_write
, },
331 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
332 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
333 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
334 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
335 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
336 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
337 /* ??? This covers not just the impdef TLB lockdown registers but also
338 * some v7VMSA registers relating to TEX remap, so it is overly broad.
340 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
341 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
342 /* MMU TLB control. Note that the wildcarding means we cover not just
343 * the unified TLB ops but also the dside/iside/inner-shareable variants.
345 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
346 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
347 .type
= ARM_CP_NO_MIGRATE
},
348 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
349 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
350 .type
= ARM_CP_NO_MIGRATE
},
351 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
352 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
353 .type
= ARM_CP_NO_MIGRATE
},
354 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
355 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
356 .type
= ARM_CP_NO_MIGRATE
},
357 /* Cache maintenance ops; some of this space may be overridden later. */
358 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
359 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
360 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
364 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
365 /* Not all pre-v6 cores implemented this WFI, so this is slightly
368 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
369 .access
= PL1_W
, .type
= ARM_CP_WFI
},
373 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
374 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
375 * is UNPREDICTABLE; we choose to NOP as most implementations do).
377 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
378 .access
= PL1_W
, .type
= ARM_CP_WFI
},
379 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
380 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
381 * OMAPCP will override this space.
383 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
384 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
386 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
387 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
389 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
390 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
391 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
396 static int cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
398 if (env
->cp15
.c1_coproc
!= value
) {
399 env
->cp15
.c1_coproc
= value
;
400 /* ??? Is this safe when called from within a TB? */
406 static const ARMCPRegInfo v6_cp_reginfo
[] = {
407 /* prefetch by MVA in v6, NOP in v7 */
408 { .name
= "MVA_prefetch",
409 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
410 .access
= PL1_W
, .type
= ARM_CP_NOP
},
411 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
412 .access
= PL0_W
, .type
= ARM_CP_NOP
},
413 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
414 .access
= PL0_W
, .type
= ARM_CP_NOP
},
415 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
416 .access
= PL0_W
, .type
= ARM_CP_NOP
},
417 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
418 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
420 /* Watchpoint Fault Address Register : should actually only be present
421 * for 1136, 1176, 11MPCore.
423 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
424 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
425 { .name
= "CPACR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
426 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
427 .resetvalue
= 0, .writefn
= cpacr_write
},
432 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
435 /* Generic performance monitor register read function for where
436 * user access may be allowed by PMUSERENR.
438 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
441 *value
= CPREG_FIELD32(env
, ri
);
445 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
448 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
451 /* only the DP, X, D and E bits are writable */
452 env
->cp15
.c9_pmcr
&= ~0x39;
453 env
->cp15
.c9_pmcr
|= (value
& 0x39);
457 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
460 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
464 env
->cp15
.c9_pmcnten
|= value
;
468 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
471 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
475 env
->cp15
.c9_pmcnten
&= ~value
;
479 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
482 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
485 env
->cp15
.c9_pmovsr
&= ~value
;
489 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
492 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
495 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
499 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 env
->cp15
.c9_pmuserenr
= value
& 1;
506 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
509 /* We have no event counters so only the C bit can be changed */
511 env
->cp15
.c9_pminten
|= value
;
515 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
519 env
->cp15
.c9_pminten
&= ~value
;
523 static int ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
526 ARMCPU
*cpu
= arm_env_get_cpu(env
);
527 *value
= cpu
->ccsidr
[env
->cp15
.c0_cssel
];
531 static int csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
534 env
->cp15
.c0_cssel
= value
& 0xf;
538 static const ARMCPRegInfo v7_cp_reginfo
[] = {
539 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
542 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
543 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
544 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
545 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
546 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
547 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
548 .access
= PL1_W
, .type
= ARM_CP_NOP
},
549 /* Performance monitors are implementation defined in v7,
550 * but with an ARM recommended set of registers, which we
551 * follow (although we don't actually implement any counters)
553 * Performance registers fall into three categories:
554 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
555 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
556 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
557 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
558 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
560 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
561 .access
= PL0_RW
, .resetvalue
= 0,
562 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
563 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
,
564 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
},
565 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
566 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
567 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
,
568 .type
= ARM_CP_NO_MIGRATE
},
569 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
570 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
571 .readfn
= pmreg_read
, .writefn
= pmovsr_write
,
572 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
},
573 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
576 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
577 .access
= PL0_W
, .type
= ARM_CP_NOP
},
578 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
579 * We choose to RAZ/WI. XXX should respect PMUSERENR.
581 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
582 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
583 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
584 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
585 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
586 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
588 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
589 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
,
590 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
},
591 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
592 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
593 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
594 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
595 .access
= PL0_R
| PL1_RW
,
596 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
598 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
599 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
601 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
603 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
604 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
605 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
606 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
607 .resetvalue
= 0, .writefn
= pmintenclr_write
, },
608 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
609 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
611 { .name
= "CCSIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
612 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_MIGRATE
},
613 { .name
= "CSSELR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
614 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
615 .writefn
= csselr_write
, .resetvalue
= 0 },
616 /* Auxiliary ID register: this actually has an IMPDEF value but for now
617 * just RAZ for all cores:
619 { .name
= "AIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 7,
620 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
624 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
631 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
634 /* This is a helper function because the user access rights
635 * depend on the value of the TEECR.
637 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
640 *value
= env
->teehbr
;
644 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
647 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
654 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
655 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
656 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
658 .writefn
= teecr_write
},
659 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
660 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
661 .resetvalue
= 0, .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
662 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
666 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
667 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
669 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
671 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
672 .access
= PL0_R
|PL1_W
,
673 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
675 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
677 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
682 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
683 /* Dummy implementation: RAZ/WI the whole crn=14 space */
684 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
685 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
686 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
691 static int par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
693 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
694 env
->cp15
.c7_par
= value
;
695 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
696 env
->cp15
.c7_par
= value
& 0xfffff6ff;
698 env
->cp15
.c7_par
= value
& 0xfffff1ff;
703 #ifndef CONFIG_USER_ONLY
704 /* get_phys_addr() isn't present for user-mode-only targets */
706 /* Return true if extended addresses are enabled, ie this is an
707 * LPAE implementation and we are using the long-descriptor translation
708 * table format because the TTBCR EAE bit is set.
710 static inline bool extended_addresses_enabled(CPUARMState
*env
)
712 return arm_feature(env
, ARM_FEATURE_LPAE
)
713 && (env
->cp15
.c2_control
& (1 << 31));
716 static int ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
719 target_ulong page_size
;
721 int ret
, is_user
= ri
->opc2
& 2;
722 int access_type
= ri
->opc2
& 1;
725 /* Other states are only available with TrustZone */
728 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
729 &phys_addr
, &prot
, &page_size
);
730 if (extended_addresses_enabled(env
)) {
731 /* ret is a DFSR/IFSR value for the long descriptor
732 * translation table format, but with WnR always clear.
733 * Convert it to a 64-bit PAR.
735 uint64_t par64
= (1 << 11); /* LPAE bit always set */
737 par64
|= phys_addr
& ~0xfffULL
;
738 /* We don't set the ATTR or SH fields in the PAR. */
741 par64
|= (ret
& 0x3f) << 1; /* FS */
742 /* Note that S2WLK and FSTAGE are always zero, because we don't
743 * implement virtualization and therefore there can't be a stage 2
747 env
->cp15
.c7_par
= par64
;
748 env
->cp15
.c7_par_hi
= par64
>> 32;
750 /* ret is a DFSR/IFSR value for the short descriptor
751 * translation table format (with WnR always clear).
752 * Convert it to a 32-bit PAR.
755 /* We do not set any attribute bits in the PAR */
756 if (page_size
== (1 << 24)
757 && arm_feature(env
, ARM_FEATURE_V7
)) {
758 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
760 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
763 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
764 ((ret
& (12 << 1)) >> 6) |
765 ((ret
& 0xf) << 1) | 1;
767 env
->cp15
.c7_par_hi
= 0;
773 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
774 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
775 .access
= PL1_RW
, .resetvalue
= 0,
776 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
777 .writefn
= par_write
},
778 #ifndef CONFIG_USER_ONLY
779 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
780 .access
= PL1_W
, .writefn
= ats_write
, .type
= ARM_CP_NO_MIGRATE
},
785 /* Return basic MPU access permission bits. */
786 static uint32_t simple_mpu_ap_bits(uint32_t val
)
793 for (i
= 0; i
< 16; i
+= 2) {
794 ret
|= (val
>> i
) & mask
;
800 /* Pad basic MPU access permission bits to extended format. */
801 static uint32_t extended_mpu_ap_bits(uint32_t val
)
808 for (i
= 0; i
< 16; i
+= 2) {
809 ret
|= (val
& mask
) << i
;
815 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
818 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
822 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
825 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
829 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
832 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
836 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
839 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
843 static int arm946_prbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
849 *value
= env
->cp15
.c6_region
[ri
->crm
];
853 static int arm946_prbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
859 env
->cp15
.c6_region
[ri
->crm
] = value
;
863 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
864 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
865 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
866 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
867 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
868 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
869 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
870 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
871 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
872 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
874 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
875 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
877 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
878 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
880 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
881 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
883 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
884 /* Protection region base and size registers */
885 { .name
= "946_PRBS", .cp
= 15, .crn
= 6, .crm
= CP_ANY
, .opc1
= 0,
886 .opc2
= CP_ANY
, .access
= PL1_RW
,
887 .readfn
= arm946_prbs_read
, .writefn
= arm946_prbs_write
, },
891 static int vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
894 int maskshift
= extract32(value
, 0, 3);
896 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
897 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
901 /* Note that we always calculate c2_mask and c2_base_mask, but
902 * they are only used for short-descriptor tables (ie if EAE is 0);
903 * for long-descriptor tables the TTBCR fields are used differently
904 * and the c2_mask and c2_base_mask values are meaningless.
906 env
->cp15
.c2_control
= value
;
907 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
908 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
912 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
915 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
916 /* With LPAE the TTBCR could result in a change of ASID
917 * via the TTBCR.A1 bit, so do a TLB flush.
921 return vmsa_ttbcr_raw_write(env
, ri
, value
);
924 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
926 env
->cp15
.c2_base_mask
= 0xffffc000u
;
927 env
->cp15
.c2_control
= 0;
928 env
->cp15
.c2_mask
= 0;
931 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
932 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
934 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
935 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
937 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
938 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
940 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
941 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
943 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base1
), .resetvalue
= 0, },
944 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
945 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
946 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
947 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
948 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
949 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
954 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
957 env
->cp15
.c15_ticonfig
= value
& 0xe7;
958 /* The OS_TYPE bit in this register changes the reported CPUID! */
959 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
960 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
964 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
967 env
->cp15
.c15_threadid
= value
& 0xffff;
971 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
974 /* Wait-for-interrupt (deprecated) */
975 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
979 static int omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
982 /* On OMAP there are registers indicating the max/min index of dcache lines
983 * containing a dirty line; cache flush operations have to reset these.
985 env
->cp15
.c15_i_max
= 0x000;
986 env
->cp15
.c15_i_min
= 0xff0;
990 static const ARMCPRegInfo omap_cp_reginfo
[] = {
991 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
992 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
993 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
994 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
995 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
996 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
998 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
999 .writefn
= omap_ticonfig_write
},
1000 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
1002 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
1003 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
1004 .access
= PL1_RW
, .resetvalue
= 0xff0,
1005 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
1006 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
1008 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
1009 .writefn
= omap_threadid_write
},
1010 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
1011 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1012 .type
= ARM_CP_NO_MIGRATE
,
1013 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
1014 /* TODO: Peripheral port remap register:
1015 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1016 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1019 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
1020 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
1021 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
,
1022 .writefn
= omap_cachemaint_write
},
1023 { .name
= "C9", .cp
= 15, .crn
= 9,
1024 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
1025 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
1029 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1033 if (env
->cp15
.c15_cpar
!= value
) {
1034 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1036 env
->cp15
.c15_cpar
= value
;
1041 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
1042 { .name
= "XSCALE_CPAR",
1043 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1044 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
1045 .writefn
= xscale_cpar_write
, },
1046 { .name
= "XSCALE_AUXCR",
1047 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
1048 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
1053 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
1054 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1055 * implementation of this implementation-defined space.
1056 * Ideally this should eventually disappear in favour of actually
1057 * implementing the correct behaviour for all cores.
1059 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
1060 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1061 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1066 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
1067 /* Cache status: RAZ because we have no cache so it's always clean */
1068 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
1069 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1074 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
1075 /* We never have a a block transfer operation in progress */
1076 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
1077 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1079 /* The cache ops themselves: these all NOP for QEMU */
1080 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
1081 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1082 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
1083 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1084 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
1085 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1086 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
1087 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1088 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
1089 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1090 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
1091 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1095 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
1096 /* The cache test-and-clean instructions always return (1 << 30)
1097 * to indicate that there are no dirty cache lines.
1099 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
1100 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1101 .resetvalue
= (1 << 30) },
1102 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
1103 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1104 .resetvalue
= (1 << 30) },
1108 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
1109 /* Ignore ReadBuffer accesses */
1110 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
1111 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1112 .access
= PL1_RW
, .resetvalue
= 0,
1113 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
},
1117 static int mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1120 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
1121 uint32_t mpidr
= cs
->cpu_index
;
1122 /* We don't support setting cluster ID ([8..11])
1123 * so these bits always RAZ.
1125 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1127 /* Cores which are uniprocessor (non-coherent)
1128 * but still implement the MP extensions set
1129 * bit 30. (For instance, A9UP.) However we do
1130 * not currently model any of those cores.
1137 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
1138 { .name
= "MPIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
1139 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_MIGRATE
},
1143 static int par64_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1145 *value
= ((uint64_t)env
->cp15
.c7_par_hi
<< 32) | env
->cp15
.c7_par
;
1149 static int par64_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1151 env
->cp15
.c7_par_hi
= value
>> 32;
1152 env
->cp15
.c7_par
= value
;
1156 static void par64_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1158 env
->cp15
.c7_par_hi
= 0;
1159 env
->cp15
.c7_par
= 0;
1162 static int ttbr064_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1165 *value
= ((uint64_t)env
->cp15
.c2_base0_hi
<< 32) | env
->cp15
.c2_base0
;
1169 static int ttbr064_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1172 env
->cp15
.c2_base0_hi
= value
>> 32;
1173 env
->cp15
.c2_base0
= value
;
1177 static int ttbr064_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1180 /* Writes to the 64 bit format TTBRs may change the ASID */
1182 return ttbr064_raw_write(env
, ri
, value
);
1185 static void ttbr064_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1187 env
->cp15
.c2_base0_hi
= 0;
1188 env
->cp15
.c2_base0
= 0;
1191 static int ttbr164_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1194 *value
= ((uint64_t)env
->cp15
.c2_base1_hi
<< 32) | env
->cp15
.c2_base1
;
1198 static int ttbr164_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1201 env
->cp15
.c2_base1_hi
= value
>> 32;
1202 env
->cp15
.c2_base1
= value
;
1206 static void ttbr164_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1208 env
->cp15
.c2_base1_hi
= 0;
1209 env
->cp15
.c2_base1
= 0;
1212 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
1213 /* NOP AMAIR0/1: the override is because these clash with the rather
1214 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1216 { .name
= "AMAIR0", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
1217 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1219 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
1220 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1222 /* 64 bit access versions of the (dummy) debug registers */
1223 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
1224 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1225 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
1226 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1227 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
1228 .access
= PL1_RW
, .type
= ARM_CP_64BIT
,
1229 .readfn
= par64_read
, .writefn
= par64_write
, .resetfn
= par64_reset
},
1230 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
1231 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr064_read
,
1232 .writefn
= ttbr064_write
, .raw_writefn
= ttbr064_raw_write
,
1233 .resetfn
= ttbr064_reset
},
1234 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
1235 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr164_read
,
1236 .writefn
= ttbr164_write
, .resetfn
= ttbr164_reset
},
1240 static int sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1242 env
->cp15
.c1_sys
= value
;
1243 /* ??? Lots of these bits are not implemented. */
1244 /* This may enable/disable the MMU, so do a TLB flush. */
1249 void register_cp_regs_for_features(ARMCPU
*cpu
)
1251 /* Register all the coprocessor registers based on feature bits */
1252 CPUARMState
*env
= &cpu
->env
;
1253 if (arm_feature(env
, ARM_FEATURE_M
)) {
1254 /* M profile has no coprocessor registers */
1258 define_arm_cp_regs(cpu
, cp_reginfo
);
1259 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1260 /* The ID registers all have impdef reset values */
1261 ARMCPRegInfo v6_idregs
[] = {
1262 { .name
= "ID_PFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1263 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1264 .resetvalue
= cpu
->id_pfr0
},
1265 { .name
= "ID_PFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1266 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1267 .resetvalue
= cpu
->id_pfr1
},
1268 { .name
= "ID_DFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1269 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1270 .resetvalue
= cpu
->id_dfr0
},
1271 { .name
= "ID_AFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1272 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1273 .resetvalue
= cpu
->id_afr0
},
1274 { .name
= "ID_MMFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1275 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1276 .resetvalue
= cpu
->id_mmfr0
},
1277 { .name
= "ID_MMFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1278 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1279 .resetvalue
= cpu
->id_mmfr1
},
1280 { .name
= "ID_MMFR2", .cp
= 15, .crn
= 0, .crm
= 1,
1281 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1282 .resetvalue
= cpu
->id_mmfr2
},
1283 { .name
= "ID_MMFR3", .cp
= 15, .crn
= 0, .crm
= 1,
1284 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1285 .resetvalue
= cpu
->id_mmfr3
},
1286 { .name
= "ID_ISAR0", .cp
= 15, .crn
= 0, .crm
= 2,
1287 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1288 .resetvalue
= cpu
->id_isar0
},
1289 { .name
= "ID_ISAR1", .cp
= 15, .crn
= 0, .crm
= 2,
1290 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1291 .resetvalue
= cpu
->id_isar1
},
1292 { .name
= "ID_ISAR2", .cp
= 15, .crn
= 0, .crm
= 2,
1293 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1294 .resetvalue
= cpu
->id_isar2
},
1295 { .name
= "ID_ISAR3", .cp
= 15, .crn
= 0, .crm
= 2,
1296 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1297 .resetvalue
= cpu
->id_isar3
},
1298 { .name
= "ID_ISAR4", .cp
= 15, .crn
= 0, .crm
= 2,
1299 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1300 .resetvalue
= cpu
->id_isar4
},
1301 { .name
= "ID_ISAR5", .cp
= 15, .crn
= 0, .crm
= 2,
1302 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1303 .resetvalue
= cpu
->id_isar5
},
1304 /* 6..7 are as yet unallocated and must RAZ */
1305 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
1306 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1308 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
1309 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1313 define_arm_cp_regs(cpu
, v6_idregs
);
1314 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
1316 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
1318 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1319 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
1321 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1322 /* v7 performance monitor control register: same implementor
1323 * field as main ID register, and we implement no event counters.
1325 ARMCPRegInfo pmcr
= {
1326 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
1327 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
1328 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
1329 .readfn
= pmreg_read
, .writefn
= pmcr_write
,
1330 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
,
1332 ARMCPRegInfo clidr
= {
1333 .name
= "CLIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
1334 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
1336 define_one_arm_cp_reg(cpu
, &pmcr
);
1337 define_one_arm_cp_reg(cpu
, &clidr
);
1338 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
1340 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
1342 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1343 /* These are the MPU registers prior to PMSAv6. Any new
1344 * PMSA core later than the ARM946 will require that we
1345 * implement the PMSAv6 or PMSAv7 registers, which are
1346 * completely different.
1348 assert(!arm_feature(env
, ARM_FEATURE_V6
));
1349 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
1351 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
1353 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
1354 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
1356 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1357 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
1359 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1360 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
1362 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
1363 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
1365 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
1366 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
1368 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
1369 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
1371 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1372 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
1374 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1375 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
1377 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1378 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
1380 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
1381 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
1383 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1384 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
1386 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1387 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1388 * be read-only (ie write causes UNDEF exception).
1391 ARMCPRegInfo id_cp_reginfo
[] = {
1392 /* Note that the MIDR isn't a simple constant register because
1393 * of the TI925 behaviour where writes to another register can
1394 * cause the MIDR value to change.
1396 * Unimplemented registers in the c15 0 0 0 space default to
1397 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1398 * and friends override accordingly.
1401 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
1402 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
1403 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
1404 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
1405 .type
= ARM_CP_OVERRIDE
},
1407 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
1408 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
1410 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
1411 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1413 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
1414 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1415 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1417 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
1418 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1420 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
1421 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1423 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
1424 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1426 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
1427 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1429 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
1430 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1433 ARMCPRegInfo crn0_wi_reginfo
= {
1434 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
1435 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
1436 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
1438 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
1439 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1441 /* Register the blanket "writes ignored" value first to cover the
1442 * whole space. Then update the specific ID registers to allow write
1443 * access, so that they ignore writes rather than causing them to
1446 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
1447 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1451 define_arm_cp_regs(cpu
, id_cp_reginfo
);
1454 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
1455 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
1458 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
1459 ARMCPRegInfo auxcr
= {
1460 .name
= "AUXCR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1,
1461 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
1462 .resetvalue
= cpu
->reset_auxcr
1464 define_one_arm_cp_reg(cpu
, &auxcr
);
1467 /* Generic registers whose values depend on the implementation */
1469 ARMCPRegInfo sctlr
= {
1470 .name
= "SCTLR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
1471 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
1472 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
1473 .raw_writefn
= raw_write
,
1475 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1476 /* Normally we would always end the TB on an SCTLR write, but Linux
1477 * arch/arm/mach-pxa/sleep.S expects two instructions following
1478 * an MMU enable to execute from cache. Imitate this behaviour.
1480 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
1482 define_one_arm_cp_reg(cpu
, &sctlr
);
1486 ARMCPU
*cpu_arm_init(const char *cpu_model
)
1492 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpu_model
);
1496 cpu
= ARM_CPU(object_new(object_class_get_name(oc
)));
1498 env
->cpu_model_str
= cpu_model
;
1500 /* TODO this should be set centrally, once possible */
1501 object_property_set_bool(OBJECT(cpu
), true, "realized", NULL
);
1506 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
1508 CPUARMState
*env
= &cpu
->env
;
1510 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
1511 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1512 51, "arm-neon.xml", 0);
1513 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
1514 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1515 35, "arm-vfp3.xml", 0);
1516 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
1517 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1518 19, "arm-vfp.xml", 0);
1522 /* Sort alphabetically by type name, except for "any". */
1523 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
1525 ObjectClass
*class_a
= (ObjectClass
*)a
;
1526 ObjectClass
*class_b
= (ObjectClass
*)b
;
1527 const char *name_a
, *name_b
;
1529 name_a
= object_class_get_name(class_a
);
1530 name_b
= object_class_get_name(class_b
);
1531 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
1533 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
1536 return strcmp(name_a
, name_b
);
1540 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
1542 ObjectClass
*oc
= data
;
1543 CPUListState
*s
= user_data
;
1544 const char *typename
;
1547 typename
= object_class_get_name(oc
);
1548 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
1549 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
1554 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1558 .cpu_fprintf
= cpu_fprintf
,
1562 list
= object_class_get_list(TYPE_ARM_CPU
, false);
1563 list
= g_slist_sort(list
, arm_cpu_list_compare
);
1564 (*cpu_fprintf
)(f
, "Available CPUs:\n");
1565 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
1569 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1570 const ARMCPRegInfo
*r
, void *opaque
)
1572 /* Define implementations of coprocessor registers.
1573 * We store these in a hashtable because typically
1574 * there are less than 150 registers in a space which
1575 * is 16*16*16*8*8 = 262144 in size.
1576 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1577 * If a register is defined twice then the second definition is
1578 * used, so this can be used to define some generic registers and
1579 * then override them with implementation specific variations.
1580 * At least one of the original and the second definition should
1581 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1582 * against accidental use.
1584 int crm
, opc1
, opc2
;
1585 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
1586 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
1587 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
1588 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
1589 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
1590 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
1591 /* 64 bit registers have only CRm and Opc1 fields */
1592 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
1593 /* Check that the register definition has enough info to handle
1594 * reads and writes if they are permitted.
1596 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
1597 if (r
->access
& PL3_R
) {
1598 assert(r
->fieldoffset
|| r
->readfn
);
1600 if (r
->access
& PL3_W
) {
1601 assert(r
->fieldoffset
|| r
->writefn
);
1604 /* Bad type field probably means missing sentinel at end of reg list */
1605 assert(cptype_valid(r
->type
));
1606 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
1607 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
1608 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
1609 uint32_t *key
= g_new(uint32_t, 1);
1610 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
1611 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
1612 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
1614 r2
->opaque
= opaque
;
1616 /* Make sure reginfo passed to helpers for wildcarded regs
1617 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1622 /* By convention, for wildcarded registers only the first
1623 * entry is used for migration; the others are marked as
1624 * NO_MIGRATE so we don't try to transfer the register
1625 * multiple times. Special registers (ie NOP/WFI) are
1628 if ((r
->type
& ARM_CP_SPECIAL
) ||
1629 ((r
->crm
== CP_ANY
) && crm
!= 0) ||
1630 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
1631 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
1632 r2
->type
|= ARM_CP_NO_MIGRATE
;
1635 /* Overriding of an existing definition must be explicitly
1638 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
1639 ARMCPRegInfo
*oldreg
;
1640 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
1641 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
1642 fprintf(stderr
, "Register redefined: cp=%d %d bit "
1643 "crn=%d crm=%d opc1=%d opc2=%d, "
1644 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
1645 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
1646 oldreg
->name
, r2
->name
);
1650 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
1656 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1657 const ARMCPRegInfo
*regs
, void *opaque
)
1659 /* Define a whole list of registers */
1660 const ARMCPRegInfo
*r
;
1661 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1662 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
1666 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
1668 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
1671 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1674 /* Helper coprocessor write function for write-ignore registers */
1678 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1680 /* Helper coprocessor write function for read-as-zero registers */
1685 static int bad_mode_switch(CPUARMState
*env
, int mode
)
1687 /* Return true if it is not valid for us to switch to
1688 * this CPU mode (ie all the UNPREDICTABLE cases in
1689 * the ARM ARM CPSRWriteByInstr pseudocode).
1692 case ARM_CPU_MODE_USR
:
1693 case ARM_CPU_MODE_SYS
:
1694 case ARM_CPU_MODE_SVC
:
1695 case ARM_CPU_MODE_ABT
:
1696 case ARM_CPU_MODE_UND
:
1697 case ARM_CPU_MODE_IRQ
:
1698 case ARM_CPU_MODE_FIQ
:
1705 uint32_t cpsr_read(CPUARMState
*env
)
1708 ZF
= (env
->ZF
== 0);
1709 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
1710 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1711 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
1712 | ((env
->condexec_bits
& 0xfc) << 8)
1716 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1718 if (mask
& CPSR_NZCV
) {
1719 env
->ZF
= (~val
) & CPSR_Z
;
1721 env
->CF
= (val
>> 29) & 1;
1722 env
->VF
= (val
<< 3) & 0x80000000;
1725 env
->QF
= ((val
& CPSR_Q
) != 0);
1727 env
->thumb
= ((val
& CPSR_T
) != 0);
1728 if (mask
& CPSR_IT_0_1
) {
1729 env
->condexec_bits
&= ~3;
1730 env
->condexec_bits
|= (val
>> 25) & 3;
1732 if (mask
& CPSR_IT_2_7
) {
1733 env
->condexec_bits
&= 3;
1734 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1736 if (mask
& CPSR_GE
) {
1737 env
->GE
= (val
>> 16) & 0xf;
1740 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
1741 if (bad_mode_switch(env
, val
& CPSR_M
)) {
1742 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1743 * We choose to ignore the attempt and leave the CPSR M field
1748 switch_mode(env
, val
& CPSR_M
);
1751 mask
&= ~CACHED_CPSR_BITS
;
1752 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
1755 /* Sign/zero extend */
1756 uint32_t HELPER(sxtb16
)(uint32_t x
)
1759 res
= (uint16_t)(int8_t)x
;
1760 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
1764 uint32_t HELPER(uxtb16
)(uint32_t x
)
1767 res
= (uint16_t)(uint8_t)x
;
1768 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
1772 uint32_t HELPER(clz
)(uint32_t x
)
1777 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
1781 if (num
== INT_MIN
&& den
== -1)
1786 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
1793 uint32_t HELPER(rbit
)(uint32_t x
)
1795 x
= ((x
& 0xff000000) >> 24)
1796 | ((x
& 0x00ff0000) >> 8)
1797 | ((x
& 0x0000ff00) << 8)
1798 | ((x
& 0x000000ff) << 24);
1799 x
= ((x
& 0xf0f0f0f0) >> 4)
1800 | ((x
& 0x0f0f0f0f) << 4);
1801 x
= ((x
& 0x88888888) >> 3)
1802 | ((x
& 0x44444444) >> 1)
1803 | ((x
& 0x22222222) << 1)
1804 | ((x
& 0x11111111) << 3);
1808 #if defined(CONFIG_USER_ONLY)
1810 void arm_cpu_do_interrupt(CPUState
*cs
)
1812 ARMCPU
*cpu
= ARM_CPU(cs
);
1813 CPUARMState
*env
= &cpu
->env
;
1815 env
->exception_index
= -1;
1818 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
1822 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1823 env
->cp15
.c6_insn
= address
;
1825 env
->exception_index
= EXCP_DATA_ABORT
;
1826 env
->cp15
.c6_data
= address
;
1831 /* These should probably raise undefined insn exceptions. */
1832 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
1834 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1837 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
1839 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1843 void switch_mode(CPUARMState
*env
, int mode
)
1845 if (mode
!= ARM_CPU_MODE_USR
)
1846 cpu_abort(env
, "Tried to switch out of user mode\n");
1849 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
1851 cpu_abort(env
, "banked r13 write\n");
1854 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
1856 cpu_abort(env
, "banked r13 read\n");
1862 /* Map CPU modes onto saved register banks. */
1863 int bank_number(int mode
)
1866 case ARM_CPU_MODE_USR
:
1867 case ARM_CPU_MODE_SYS
:
1869 case ARM_CPU_MODE_SVC
:
1871 case ARM_CPU_MODE_ABT
:
1873 case ARM_CPU_MODE_UND
:
1875 case ARM_CPU_MODE_IRQ
:
1877 case ARM_CPU_MODE_FIQ
:
1880 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode
);
1883 void switch_mode(CPUARMState
*env
, int mode
)
1888 old_mode
= env
->uncached_cpsr
& CPSR_M
;
1889 if (mode
== old_mode
)
1892 if (old_mode
== ARM_CPU_MODE_FIQ
) {
1893 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1894 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
1895 } else if (mode
== ARM_CPU_MODE_FIQ
) {
1896 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1897 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
1900 i
= bank_number(old_mode
);
1901 env
->banked_r13
[i
] = env
->regs
[13];
1902 env
->banked_r14
[i
] = env
->regs
[14];
1903 env
->banked_spsr
[i
] = env
->spsr
;
1905 i
= bank_number(mode
);
1906 env
->regs
[13] = env
->banked_r13
[i
];
1907 env
->regs
[14] = env
->banked_r14
[i
];
1908 env
->spsr
= env
->banked_spsr
[i
];
1911 static void v7m_push(CPUARMState
*env
, uint32_t val
)
1914 stl_phys(env
->regs
[13], val
);
1917 static uint32_t v7m_pop(CPUARMState
*env
)
1920 val
= ldl_phys(env
->regs
[13]);
1925 /* Switch to V7M main or process stack pointer. */
1926 static void switch_v7m_sp(CPUARMState
*env
, int process
)
1929 if (env
->v7m
.current_sp
!= process
) {
1930 tmp
= env
->v7m
.other_sp
;
1931 env
->v7m
.other_sp
= env
->regs
[13];
1932 env
->regs
[13] = tmp
;
1933 env
->v7m
.current_sp
= process
;
1937 static void do_v7m_exception_exit(CPUARMState
*env
)
1942 type
= env
->regs
[15];
1943 if (env
->v7m
.exception
!= 0)
1944 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
1946 /* Switch to the target stack. */
1947 switch_v7m_sp(env
, (type
& 4) != 0);
1948 /* Pop registers. */
1949 env
->regs
[0] = v7m_pop(env
);
1950 env
->regs
[1] = v7m_pop(env
);
1951 env
->regs
[2] = v7m_pop(env
);
1952 env
->regs
[3] = v7m_pop(env
);
1953 env
->regs
[12] = v7m_pop(env
);
1954 env
->regs
[14] = v7m_pop(env
);
1955 env
->regs
[15] = v7m_pop(env
);
1956 xpsr
= v7m_pop(env
);
1957 xpsr_write(env
, xpsr
, 0xfffffdff);
1958 /* Undo stack alignment. */
1961 /* ??? The exception return type specifies Thread/Handler mode. However
1962 this is also implied by the xPSR value. Not sure what to do
1963 if there is a mismatch. */
1964 /* ??? Likewise for mismatches between the CONTROL register and the stack
1968 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
1970 ARMCPU
*cpu
= ARM_CPU(cs
);
1971 CPUARMState
*env
= &cpu
->env
;
1972 uint32_t xpsr
= xpsr_read(env
);
1977 if (env
->v7m
.current_sp
)
1979 if (env
->v7m
.exception
== 0)
1982 /* For exceptions we just mark as pending on the NVIC, and let that
1984 /* TODO: Need to escalate if the current priority is higher than the
1985 one we're raising. */
1986 switch (env
->exception_index
) {
1988 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1991 /* The PC already points to the next instruction. */
1992 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1994 case EXCP_PREFETCH_ABORT
:
1995 case EXCP_DATA_ABORT
:
1996 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1999 if (semihosting_enabled
) {
2001 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
2004 env
->regs
[0] = do_arm_semihosting(env
);
2008 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
2011 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
2013 case EXCP_EXCEPTION_EXIT
:
2014 do_v7m_exception_exit(env
);
2017 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
2018 return; /* Never happens. Keep compiler happy. */
2021 /* Align stack pointer. */
2022 /* ??? Should only do this if Configuration Control Register
2023 STACKALIGN bit is set. */
2024 if (env
->regs
[13] & 4) {
2028 /* Switch to the handler mode. */
2029 v7m_push(env
, xpsr
);
2030 v7m_push(env
, env
->regs
[15]);
2031 v7m_push(env
, env
->regs
[14]);
2032 v7m_push(env
, env
->regs
[12]);
2033 v7m_push(env
, env
->regs
[3]);
2034 v7m_push(env
, env
->regs
[2]);
2035 v7m_push(env
, env
->regs
[1]);
2036 v7m_push(env
, env
->regs
[0]);
2037 switch_v7m_sp(env
, 0);
2039 env
->condexec_bits
= 0;
2041 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
2042 env
->regs
[15] = addr
& 0xfffffffe;
2043 env
->thumb
= addr
& 1;
2046 /* Handle a CPU exception. */
2047 void arm_cpu_do_interrupt(CPUState
*cs
)
2049 ARMCPU
*cpu
= ARM_CPU(cs
);
2050 CPUARMState
*env
= &cpu
->env
;
2058 /* TODO: Vectored interrupt controller. */
2059 switch (env
->exception_index
) {
2061 new_mode
= ARM_CPU_MODE_UND
;
2070 if (semihosting_enabled
) {
2071 /* Check for semihosting interrupt. */
2073 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
2076 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
2079 /* Only intercept calls from privileged modes, to provide some
2080 semblance of security. */
2081 if (((mask
== 0x123456 && !env
->thumb
)
2082 || (mask
== 0xab && env
->thumb
))
2083 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
2084 env
->regs
[0] = do_arm_semihosting(env
);
2088 new_mode
= ARM_CPU_MODE_SVC
;
2091 /* The PC already points to the next instruction. */
2095 /* See if this is a semihosting syscall. */
2096 if (env
->thumb
&& semihosting_enabled
) {
2097 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
2099 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
2101 env
->regs
[0] = do_arm_semihosting(env
);
2105 env
->cp15
.c5_insn
= 2;
2106 /* Fall through to prefetch abort. */
2107 case EXCP_PREFETCH_ABORT
:
2108 new_mode
= ARM_CPU_MODE_ABT
;
2110 mask
= CPSR_A
| CPSR_I
;
2113 case EXCP_DATA_ABORT
:
2114 new_mode
= ARM_CPU_MODE_ABT
;
2116 mask
= CPSR_A
| CPSR_I
;
2120 new_mode
= ARM_CPU_MODE_IRQ
;
2122 /* Disable IRQ and imprecise data aborts. */
2123 mask
= CPSR_A
| CPSR_I
;
2127 new_mode
= ARM_CPU_MODE_FIQ
;
2129 /* Disable FIQ, IRQ and imprecise data aborts. */
2130 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
2134 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
2135 return; /* Never happens. Keep compiler happy. */
2138 if (env
->cp15
.c1_sys
& (1 << 13)) {
2141 switch_mode (env
, new_mode
);
2142 env
->spsr
= cpsr_read(env
);
2143 /* Clear IT bits. */
2144 env
->condexec_bits
= 0;
2145 /* Switch to the new mode, and to the correct instruction set. */
2146 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
2147 env
->uncached_cpsr
|= mask
;
2148 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2149 * and we should just guard the thumb mode on V4 */
2150 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
2151 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
2153 env
->regs
[14] = env
->regs
[15] + offset
;
2154 env
->regs
[15] = addr
;
2155 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
2158 /* Check section/page access permissions.
2159 Returns the page protection flags, or zero if the access is not
2161 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
2162 int access_type
, int is_user
)
2166 if (domain_prot
== 3) {
2167 return PAGE_READ
| PAGE_WRITE
;
2170 if (access_type
== 1)
2173 prot_ro
= PAGE_READ
;
2177 if (access_type
== 1)
2179 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
2181 return is_user
? 0 : PAGE_READ
;
2188 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
2193 return PAGE_READ
| PAGE_WRITE
;
2195 return PAGE_READ
| PAGE_WRITE
;
2196 case 4: /* Reserved. */
2199 return is_user
? 0 : prot_ro
;
2203 if (!arm_feature (env
, ARM_FEATURE_V6K
))
2211 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
2215 if (address
& env
->cp15
.c2_mask
)
2216 table
= env
->cp15
.c2_base1
& 0xffffc000;
2218 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
2220 table
|= (address
>> 18) & 0x3ffc;
2224 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
2225 int is_user
, hwaddr
*phys_ptr
,
2226 int *prot
, target_ulong
*page_size
)
2237 /* Pagetable walk. */
2238 /* Lookup l1 descriptor. */
2239 table
= get_level1_table_address(env
, address
);
2240 desc
= ldl_phys(table
);
2242 domain
= (desc
>> 5) & 0x0f;
2243 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
2245 /* Section translation fault. */
2249 if (domain_prot
== 0 || domain_prot
== 2) {
2251 code
= 9; /* Section domain fault. */
2253 code
= 11; /* Page domain fault. */
2258 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2259 ap
= (desc
>> 10) & 3;
2261 *page_size
= 1024 * 1024;
2263 /* Lookup l2 entry. */
2265 /* Coarse pagetable. */
2266 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2268 /* Fine pagetable. */
2269 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
2271 desc
= ldl_phys(table
);
2273 case 0: /* Page translation fault. */
2276 case 1: /* 64k page. */
2277 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2278 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2279 *page_size
= 0x10000;
2281 case 2: /* 4k page. */
2282 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2283 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2284 *page_size
= 0x1000;
2286 case 3: /* 1k page. */
2288 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2289 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2291 /* Page translation fault. */
2296 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
2298 ap
= (desc
>> 4) & 3;
2302 /* Never happens, but compiler isn't smart enough to tell. */
2307 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2309 /* Access permission fault. */
2313 *phys_ptr
= phys_addr
;
2316 return code
| (domain
<< 4);
2319 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
2320 int is_user
, hwaddr
*phys_ptr
,
2321 int *prot
, target_ulong
*page_size
)
2334 /* Pagetable walk. */
2335 /* Lookup l1 descriptor. */
2336 table
= get_level1_table_address(env
, address
);
2337 desc
= ldl_phys(table
);
2339 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
2340 /* Section translation fault, or attempt to use the encoding
2341 * which is Reserved on implementations without PXN.
2346 if ((type
== 1) || !(desc
& (1 << 18))) {
2347 /* Page or Section. */
2348 domain
= (desc
>> 5) & 0x0f;
2350 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
2351 if (domain_prot
== 0 || domain_prot
== 2) {
2353 code
= 9; /* Section domain fault. */
2355 code
= 11; /* Page domain fault. */
2360 if (desc
& (1 << 18)) {
2362 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
2363 *page_size
= 0x1000000;
2366 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2367 *page_size
= 0x100000;
2369 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
2370 xn
= desc
& (1 << 4);
2374 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
2375 pxn
= (desc
>> 2) & 1;
2377 /* Lookup l2 entry. */
2378 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2379 desc
= ldl_phys(table
);
2380 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
2382 case 0: /* Page translation fault. */
2385 case 1: /* 64k page. */
2386 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2387 xn
= desc
& (1 << 15);
2388 *page_size
= 0x10000;
2390 case 2: case 3: /* 4k page. */
2391 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2393 *page_size
= 0x1000;
2396 /* Never happens, but compiler isn't smart enough to tell. */
2401 if (domain_prot
== 3) {
2402 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2404 if (pxn
&& !is_user
) {
2407 if (xn
&& access_type
== 2)
2410 /* The simplified model uses AP[0] as an access control bit. */
2411 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
2412 /* Access flag fault. */
2413 code
= (code
== 15) ? 6 : 3;
2416 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2418 /* Access permission fault. */
2425 *phys_ptr
= phys_addr
;
2428 return code
| (domain
<< 4);
2431 /* Fault type for long-descriptor MMU fault reporting; this corresponds
2432 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2435 translation_fault
= 1,
2437 permission_fault
= 3,
2440 static int get_phys_addr_lpae(CPUARMState
*env
, uint32_t address
,
2441 int access_type
, int is_user
,
2442 hwaddr
*phys_ptr
, int *prot
,
2443 target_ulong
*page_size_ptr
)
2445 /* Read an LPAE long-descriptor translation table. */
2446 MMUFaultType fault_type
= translation_fault
;
2454 uint32_t tableattrs
;
2455 target_ulong page_size
;
2458 /* Determine whether this address is in the region controlled by
2459 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2460 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2461 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2463 uint32_t t0sz
= extract32(env
->cp15
.c2_control
, 0, 3);
2464 uint32_t t1sz
= extract32(env
->cp15
.c2_control
, 16, 3);
2465 if (t0sz
&& !extract32(address
, 32 - t0sz
, t0sz
)) {
2466 /* there is a ttbr0 region and we are in it (high bits all zero) */
2468 } else if (t1sz
&& !extract32(~address
, 32 - t1sz
, t1sz
)) {
2469 /* there is a ttbr1 region and we are in it (high bits all one) */
2472 /* ttbr0 region is "everything not in the ttbr1 region" */
2475 /* ttbr1 region is "everything not in the ttbr0 region" */
2478 /* in the gap between the two regions, this is a Translation fault */
2479 fault_type
= translation_fault
;
2483 /* Note that QEMU ignores shareability and cacheability attributes,
2484 * so we don't need to do anything with the SH, ORGN, IRGN fields
2485 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2486 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2487 * implement any ASID-like capability so we can ignore it (instead
2488 * we will always flush the TLB any time the ASID is changed).
2490 if (ttbr_select
== 0) {
2491 ttbr
= ((uint64_t)env
->cp15
.c2_base0_hi
<< 32) | env
->cp15
.c2_base0
;
2492 epd
= extract32(env
->cp15
.c2_control
, 7, 1);
2495 ttbr
= ((uint64_t)env
->cp15
.c2_base1_hi
<< 32) | env
->cp15
.c2_base1
;
2496 epd
= extract32(env
->cp15
.c2_control
, 23, 1);
2501 /* Translation table walk disabled => Translation fault on TLB miss */
2505 /* If the region is small enough we will skip straight to a 2nd level
2506 * lookup. This affects the number of bits of the address used in
2507 * combination with the TTBR to find the first descriptor. ('n' here
2508 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2509 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2518 /* Clear the vaddr bits which aren't part of the within-region address,
2519 * so that we don't have to special case things when calculating the
2520 * first descriptor address.
2522 address
&= (0xffffffffU
>> tsz
);
2524 /* Now we can extract the actual base address from the TTBR */
2525 descaddr
= extract64(ttbr
, 0, 40);
2526 descaddr
&= ~((1ULL << n
) - 1);
2530 uint64_t descriptor
;
2532 descaddr
|= ((address
>> (9 * (4 - level
))) & 0xff8);
2533 descriptor
= ldq_phys(descaddr
);
2534 if (!(descriptor
& 1) ||
2535 (!(descriptor
& 2) && (level
== 3))) {
2536 /* Invalid, or the Reserved level 3 encoding */
2539 descaddr
= descriptor
& 0xfffffff000ULL
;
2541 if ((descriptor
& 2) && (level
< 3)) {
2542 /* Table entry. The top five bits are attributes which may
2543 * propagate down through lower levels of the table (and
2544 * which are all arranged so that 0 means "no effect", so
2545 * we can gather them up by ORing in the bits at each level).
2547 tableattrs
|= extract64(descriptor
, 59, 5);
2551 /* Block entry at level 1 or 2, or page entry at level 3.
2552 * These are basically the same thing, although the number
2553 * of bits we pull in from the vaddr varies.
2555 page_size
= (1 << (39 - (9 * level
)));
2556 descaddr
|= (address
& (page_size
- 1));
2557 /* Extract attributes from the descriptor and merge with table attrs */
2558 attrs
= extract64(descriptor
, 2, 10)
2559 | (extract64(descriptor
, 52, 12) << 10);
2560 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
2561 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
2562 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2563 * means "force PL1 access only", which means forcing AP[1] to 0.
2565 if (extract32(tableattrs
, 2, 1)) {
2568 /* Since we're always in the Non-secure state, NSTable is ignored. */
2571 /* Here descaddr is the final physical address, and attributes
2574 fault_type
= access_fault
;
2575 if ((attrs
& (1 << 8)) == 0) {
2579 fault_type
= permission_fault
;
2580 if (is_user
&& !(attrs
& (1 << 4))) {
2581 /* Unprivileged access not enabled */
2584 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2585 if (attrs
& (1 << 12) || (!is_user
&& (attrs
& (1 << 11)))) {
2587 if (access_type
== 2) {
2590 *prot
&= ~PAGE_EXEC
;
2592 if (attrs
& (1 << 5)) {
2593 /* Write access forbidden */
2594 if (access_type
== 1) {
2597 *prot
&= ~PAGE_WRITE
;
2600 *phys_ptr
= descaddr
;
2601 *page_size_ptr
= page_size
;
2605 /* Long-descriptor format IFSR/DFSR value */
2606 return (1 << 9) | (fault_type
<< 2) | level
;
2609 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
,
2610 int access_type
, int is_user
,
2611 hwaddr
*phys_ptr
, int *prot
)
2617 *phys_ptr
= address
;
2618 for (n
= 7; n
>= 0; n
--) {
2619 base
= env
->cp15
.c6_region
[n
];
2620 if ((base
& 1) == 0)
2622 mask
= 1 << ((base
>> 1) & 0x1f);
2623 /* Keep this shift separate from the above to avoid an
2624 (undefined) << 32. */
2625 mask
= (mask
<< 1) - 1;
2626 if (((base
^ address
) & ~mask
) == 0)
2632 if (access_type
== 2) {
2633 mask
= env
->cp15
.c5_insn
;
2635 mask
= env
->cp15
.c5_data
;
2637 mask
= (mask
>> (n
* 4)) & 0xf;
2644 *prot
= PAGE_READ
| PAGE_WRITE
;
2649 *prot
|= PAGE_WRITE
;
2652 *prot
= PAGE_READ
| PAGE_WRITE
;
2663 /* Bad permission. */
2670 /* get_phys_addr - get the physical address for this virtual address
2672 * Find the physical address corresponding to the given virtual address,
2673 * by doing a translation table walk on MMU based systems or using the
2674 * MPU state on MPU based systems.
2676 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2677 * prot and page_size are not filled in, and the return value provides
2678 * information on why the translation aborted, in the format of a
2679 * DFSR/IFSR fault register, with the following caveats:
2680 * * we honour the short vs long DFSR format differences.
2681 * * the WnR bit is never set (the caller must do this).
2682 * * for MPU based systems we don't bother to return a full FSR format
2686 * @address: virtual address to get physical address for
2687 * @access_type: 0 for read, 1 for write, 2 for execute
2688 * @is_user: 0 for privileged access, 1 for user
2689 * @phys_ptr: set to the physical address corresponding to the virtual address
2690 * @prot: set to the permissions for the page containing phys_ptr
2691 * @page_size: set to the size of the page containing phys_ptr
2693 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
2694 int access_type
, int is_user
,
2695 hwaddr
*phys_ptr
, int *prot
,
2696 target_ulong
*page_size
)
2698 /* Fast Context Switch Extension. */
2699 if (address
< 0x02000000)
2700 address
+= env
->cp15
.c13_fcse
;
2702 if ((env
->cp15
.c1_sys
& 1) == 0) {
2703 /* MMU/MPU disabled. */
2704 *phys_ptr
= address
;
2705 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2706 *page_size
= TARGET_PAGE_SIZE
;
2708 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2709 *page_size
= TARGET_PAGE_SIZE
;
2710 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
2712 } else if (extended_addresses_enabled(env
)) {
2713 return get_phys_addr_lpae(env
, address
, access_type
, is_user
, phys_ptr
,
2715 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
2716 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
2719 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
2724 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
2725 int access_type
, int mmu_idx
)
2728 target_ulong page_size
;
2732 is_user
= mmu_idx
== MMU_USER_IDX
;
2733 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
2736 /* Map a single [sub]page. */
2737 phys_addr
&= ~(hwaddr
)0x3ff;
2738 address
&= ~(uint32_t)0x3ff;
2739 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
2743 if (access_type
== 2) {
2744 env
->cp15
.c5_insn
= ret
;
2745 env
->cp15
.c6_insn
= address
;
2746 env
->exception_index
= EXCP_PREFETCH_ABORT
;
2748 env
->cp15
.c5_data
= ret
;
2749 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
2750 env
->cp15
.c5_data
|= (1 << 11);
2751 env
->cp15
.c6_data
= address
;
2752 env
->exception_index
= EXCP_DATA_ABORT
;
2757 hwaddr
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
2760 target_ulong page_size
;
2764 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
2772 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2774 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2775 env
->regs
[13] = val
;
2777 env
->banked_r13
[bank_number(mode
)] = val
;
2781 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2783 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2784 return env
->regs
[13];
2786 return env
->banked_r13
[bank_number(mode
)];
2790 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2794 return xpsr_read(env
) & 0xf8000000;
2796 return xpsr_read(env
) & 0xf80001ff;
2798 return xpsr_read(env
) & 0xff00fc00;
2800 return xpsr_read(env
) & 0xff00fdff;
2802 return xpsr_read(env
) & 0x000001ff;
2804 return xpsr_read(env
) & 0x0700fc00;
2806 return xpsr_read(env
) & 0x0700edff;
2808 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2810 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2811 case 16: /* PRIMASK */
2812 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2813 case 17: /* BASEPRI */
2814 case 18: /* BASEPRI_MAX */
2815 return env
->v7m
.basepri
;
2816 case 19: /* FAULTMASK */
2817 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2818 case 20: /* CONTROL */
2819 return env
->v7m
.control
;
2821 /* ??? For debugging only. */
2822 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2827 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2831 xpsr_write(env
, val
, 0xf8000000);
2834 xpsr_write(env
, val
, 0xf8000000);
2837 xpsr_write(env
, val
, 0xfe00fc00);
2840 xpsr_write(env
, val
, 0xfe00fc00);
2843 /* IPSR bits are readonly. */
2846 xpsr_write(env
, val
, 0x0600fc00);
2849 xpsr_write(env
, val
, 0x0600fc00);
2852 if (env
->v7m
.current_sp
)
2853 env
->v7m
.other_sp
= val
;
2855 env
->regs
[13] = val
;
2858 if (env
->v7m
.current_sp
)
2859 env
->regs
[13] = val
;
2861 env
->v7m
.other_sp
= val
;
2863 case 16: /* PRIMASK */
2865 env
->uncached_cpsr
|= CPSR_I
;
2867 env
->uncached_cpsr
&= ~CPSR_I
;
2869 case 17: /* BASEPRI */
2870 env
->v7m
.basepri
= val
& 0xff;
2872 case 18: /* BASEPRI_MAX */
2874 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2875 env
->v7m
.basepri
= val
;
2877 case 19: /* FAULTMASK */
2879 env
->uncached_cpsr
|= CPSR_F
;
2881 env
->uncached_cpsr
&= ~CPSR_F
;
2883 case 20: /* CONTROL */
2884 env
->v7m
.control
= val
& 3;
2885 switch_v7m_sp(env
, (val
& 2) != 0);
2888 /* ??? For debugging only. */
2889 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2896 /* Note that signed overflow is undefined in C. The following routines are
2897 careful to use unsigned types where modulo arithmetic is required.
2898 Failure to do so _will_ break on newer gcc. */
2900 /* Signed saturating arithmetic. */
2902 /* Perform 16-bit signed saturating addition. */
2903 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2908 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2917 /* Perform 8-bit signed saturating addition. */
2918 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2923 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2932 /* Perform 16-bit signed saturating subtraction. */
2933 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2938 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2947 /* Perform 8-bit signed saturating subtraction. */
2948 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2953 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2962 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2963 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2964 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2965 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2968 #include "op_addsub.h"
2970 /* Unsigned saturating arithmetic. */
2971 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2980 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2988 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2997 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
3005 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3006 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3007 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3008 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3011 #include "op_addsub.h"
3013 /* Signed modulo arithmetic. */
3014 #define SARITH16(a, b, n, op) do { \
3016 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
3017 RESULT(sum, n, 16); \
3019 ge |= 3 << (n * 2); \
3022 #define SARITH8(a, b, n, op) do { \
3024 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
3025 RESULT(sum, n, 8); \
3031 #define ADD16(a, b, n) SARITH16(a, b, n, +)
3032 #define SUB16(a, b, n) SARITH16(a, b, n, -)
3033 #define ADD8(a, b, n) SARITH8(a, b, n, +)
3034 #define SUB8(a, b, n) SARITH8(a, b, n, -)
3038 #include "op_addsub.h"
3040 /* Unsigned modulo arithmetic. */
3041 #define ADD16(a, b, n) do { \
3043 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3044 RESULT(sum, n, 16); \
3045 if ((sum >> 16) == 1) \
3046 ge |= 3 << (n * 2); \
3049 #define ADD8(a, b, n) do { \
3051 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3052 RESULT(sum, n, 8); \
3053 if ((sum >> 8) == 1) \
3057 #define SUB16(a, b, n) do { \
3059 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3060 RESULT(sum, n, 16); \
3061 if ((sum >> 16) == 0) \
3062 ge |= 3 << (n * 2); \
3065 #define SUB8(a, b, n) do { \
3067 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3068 RESULT(sum, n, 8); \
3069 if ((sum >> 8) == 0) \
3076 #include "op_addsub.h"
3078 /* Halved signed arithmetic. */
3079 #define ADD16(a, b, n) \
3080 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3081 #define SUB16(a, b, n) \
3082 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3083 #define ADD8(a, b, n) \
3084 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3085 #define SUB8(a, b, n) \
3086 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3089 #include "op_addsub.h"
3091 /* Halved unsigned arithmetic. */
3092 #define ADD16(a, b, n) \
3093 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3094 #define SUB16(a, b, n) \
3095 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3096 #define ADD8(a, b, n) \
3097 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3098 #define SUB8(a, b, n) \
3099 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3102 #include "op_addsub.h"
3104 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
3112 /* Unsigned sum of absolute byte differences. */
3113 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
3116 sum
= do_usad(a
, b
);
3117 sum
+= do_usad(a
>> 8, b
>> 8);
3118 sum
+= do_usad(a
>> 16, b
>>16);
3119 sum
+= do_usad(a
>> 24, b
>> 24);
3123 /* For ARMv6 SEL instruction. */
3124 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
3137 return (a
& mask
) | (b
& ~mask
);
3140 /* VFP support. We follow the convention used for VFP instructions:
3141 Single precision routines have a "s" suffix, double precision a
3144 /* Convert host exception flags to vfp form. */
3145 static inline int vfp_exceptbits_from_host(int host_bits
)
3147 int target_bits
= 0;
3149 if (host_bits
& float_flag_invalid
)
3151 if (host_bits
& float_flag_divbyzero
)
3153 if (host_bits
& float_flag_overflow
)
3155 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
3157 if (host_bits
& float_flag_inexact
)
3158 target_bits
|= 0x10;
3159 if (host_bits
& float_flag_input_denormal
)
3160 target_bits
|= 0x80;
3164 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
3169 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
3170 | (env
->vfp
.vec_len
<< 16)
3171 | (env
->vfp
.vec_stride
<< 20);
3172 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
3173 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
3174 fpscr
|= vfp_exceptbits_from_host(i
);
3178 uint32_t vfp_get_fpscr(CPUARMState
*env
)
3180 return HELPER(vfp_get_fpscr
)(env
);
3183 /* Convert vfp exception flags to target form. */
3184 static inline int vfp_exceptbits_to_host(int target_bits
)
3188 if (target_bits
& 1)
3189 host_bits
|= float_flag_invalid
;
3190 if (target_bits
& 2)
3191 host_bits
|= float_flag_divbyzero
;
3192 if (target_bits
& 4)
3193 host_bits
|= float_flag_overflow
;
3194 if (target_bits
& 8)
3195 host_bits
|= float_flag_underflow
;
3196 if (target_bits
& 0x10)
3197 host_bits
|= float_flag_inexact
;
3198 if (target_bits
& 0x80)
3199 host_bits
|= float_flag_input_denormal
;
3203 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
3208 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
3209 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
3210 env
->vfp
.vec_len
= (val
>> 16) & 7;
3211 env
->vfp
.vec_stride
= (val
>> 20) & 3;
3214 if (changed
& (3 << 22)) {
3215 i
= (val
>> 22) & 3;
3218 i
= float_round_nearest_even
;
3224 i
= float_round_down
;
3227 i
= float_round_to_zero
;
3230 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
3232 if (changed
& (1 << 24)) {
3233 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
3234 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
3236 if (changed
& (1 << 25))
3237 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
3239 i
= vfp_exceptbits_to_host(val
);
3240 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
3241 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
3244 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
3246 HELPER(vfp_set_fpscr
)(env
, val
);
3249 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3251 #define VFP_BINOP(name) \
3252 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3254 float_status *fpst = fpstp; \
3255 return float32_ ## name(a, b, fpst); \
3257 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3259 float_status *fpst = fpstp; \
3260 return float64_ ## name(a, b, fpst); \
3268 float32
VFP_HELPER(neg
, s
)(float32 a
)
3270 return float32_chs(a
);
3273 float64
VFP_HELPER(neg
, d
)(float64 a
)
3275 return float64_chs(a
);
3278 float32
VFP_HELPER(abs
, s
)(float32 a
)
3280 return float32_abs(a
);
3283 float64
VFP_HELPER(abs
, d
)(float64 a
)
3285 return float64_abs(a
);
3288 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
3290 return float32_sqrt(a
, &env
->vfp
.fp_status
);
3293 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
3295 return float64_sqrt(a
, &env
->vfp
.fp_status
);
3298 /* XXX: check quiet/signaling case */
3299 #define DO_VFP_cmp(p, type) \
3300 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3303 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3304 case 0: flags = 0x6; break; \
3305 case -1: flags = 0x8; break; \
3306 case 1: flags = 0x2; break; \
3307 default: case 2: flags = 0x3; break; \
3309 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3310 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3312 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3315 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3316 case 0: flags = 0x6; break; \
3317 case -1: flags = 0x8; break; \
3318 case 1: flags = 0x2; break; \
3319 default: case 2: flags = 0x3; break; \
3321 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3322 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3324 DO_VFP_cmp(s
, float32
)
3325 DO_VFP_cmp(d
, float64
)
3328 /* Integer to float and float to integer conversions */
3330 #define CONV_ITOF(name, fsz, sign) \
3331 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3333 float_status *fpst = fpstp; \
3334 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3337 #define CONV_FTOI(name, fsz, sign, round) \
3338 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3340 float_status *fpst = fpstp; \
3341 if (float##fsz##_is_any_nan(x)) { \
3342 float_raise(float_flag_invalid, fpst); \
3345 return float##fsz##_to_##sign##int32##round(x, fpst); \
3348 #define FLOAT_CONVS(name, p, fsz, sign) \
3349 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3350 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3351 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3353 FLOAT_CONVS(si
, s
, 32, )
3354 FLOAT_CONVS(si
, d
, 64, )
3355 FLOAT_CONVS(ui
, s
, 32, u
)
3356 FLOAT_CONVS(ui
, d
, 64, u
)
3362 /* floating point conversion */
3363 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
3365 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
3366 /* ARM requires that S<->D conversion of any kind of NaN generates
3367 * a quiet NaN by forcing the most significant frac bit to 1.
3369 return float64_maybe_silence_nan(r
);
3372 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
3374 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
3375 /* ARM requires that S<->D conversion of any kind of NaN generates
3376 * a quiet NaN by forcing the most significant frac bit to 1.
3378 return float32_maybe_silence_nan(r
);
3381 /* VFP3 fixed point conversion. */
3382 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
3383 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3386 float_status *fpst = fpstp; \
3388 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3389 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
3391 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3394 float_status *fpst = fpstp; \
3396 if (float##fsz##_is_any_nan(x)) { \
3397 float_raise(float_flag_invalid, fpst); \
3400 tmp = float##fsz##_scalbn(x, shift, fpst); \
3401 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
3404 VFP_CONV_FIX(sh
, d
, 64, int16
, )
3405 VFP_CONV_FIX(sl
, d
, 64, int32
, )
3406 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
3407 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
3408 VFP_CONV_FIX(sh
, s
, 32, int16
, )
3409 VFP_CONV_FIX(sl
, s
, 32, int32
, )
3410 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
3411 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
3414 /* Half precision conversions. */
3415 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
3417 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
3418 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
3420 return float32_maybe_silence_nan(r
);
3425 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
3427 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
3428 float16 r
= float32_to_float16(a
, ieee
, s
);
3430 r
= float16_maybe_silence_nan(r
);
3432 return float16_val(r
);
3435 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3437 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
3440 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3442 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
3445 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3447 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
3450 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3452 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
3455 #define float32_two make_float32(0x40000000)
3456 #define float32_three make_float32(0x40400000)
3457 #define float32_one_point_five make_float32(0x3fc00000)
3459 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3461 float_status
*s
= &env
->vfp
.standard_fp_status
;
3462 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3463 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3464 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3465 float_raise(float_flag_input_denormal
, s
);
3469 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
3472 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3474 float_status
*s
= &env
->vfp
.standard_fp_status
;
3476 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3477 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3478 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3479 float_raise(float_flag_input_denormal
, s
);
3481 return float32_one_point_five
;
3483 product
= float32_mul(a
, b
, s
);
3484 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
3489 /* Constants 256 and 512 are used in some helpers; we avoid relying on
3490 * int->float conversions at run-time. */
3491 #define float64_256 make_float64(0x4070000000000000LL)
3492 #define float64_512 make_float64(0x4080000000000000LL)
3494 /* The algorithm that must be used to calculate the estimate
3495 * is specified by the ARM ARM.
3497 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
3499 /* These calculations mustn't set any fp exception flags,
3500 * so we use a local copy of the fp_status.
3502 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3503 float_status
*s
= &dummy_status
;
3504 /* q = (int)(a * 512.0) */
3505 float64 q
= float64_mul(float64_512
, a
, s
);
3506 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3508 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3509 q
= int64_to_float64(q_int
, s
);
3510 q
= float64_add(q
, float64_half
, s
);
3511 q
= float64_div(q
, float64_512
, s
);
3512 q
= float64_div(float64_one
, q
, s
);
3514 /* s = (int)(256.0 * r + 0.5) */
3515 q
= float64_mul(q
, float64_256
, s
);
3516 q
= float64_add(q
, float64_half
, s
);
3517 q_int
= float64_to_int64_round_to_zero(q
, s
);
3519 /* return (double)s / 256.0 */
3520 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3523 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
3525 float_status
*s
= &env
->vfp
.standard_fp_status
;
3527 uint32_t val32
= float32_val(a
);
3530 int a_exp
= (val32
& 0x7f800000) >> 23;
3531 int sign
= val32
& 0x80000000;
3533 if (float32_is_any_nan(a
)) {
3534 if (float32_is_signaling_nan(a
)) {
3535 float_raise(float_flag_invalid
, s
);
3537 return float32_default_nan
;
3538 } else if (float32_is_infinity(a
)) {
3539 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3540 } else if (float32_is_zero_or_denormal(a
)) {
3541 if (!float32_is_zero(a
)) {
3542 float_raise(float_flag_input_denormal
, s
);
3544 float_raise(float_flag_divbyzero
, s
);
3545 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3546 } else if (a_exp
>= 253) {
3547 float_raise(float_flag_underflow
, s
);
3548 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3551 f64
= make_float64((0x3feULL
<< 52)
3552 | ((int64_t)(val32
& 0x7fffff) << 29));
3554 result_exp
= 253 - a_exp
;
3556 f64
= recip_estimate(f64
, env
);
3559 | ((result_exp
& 0xff) << 23)
3560 | ((float64_val(f64
) >> 29) & 0x7fffff);
3561 return make_float32(val32
);
3564 /* The algorithm that must be used to calculate the estimate
3565 * is specified by the ARM ARM.
3567 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
3569 /* These calculations mustn't set any fp exception flags,
3570 * so we use a local copy of the fp_status.
3572 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3573 float_status
*s
= &dummy_status
;
3577 if (float64_lt(a
, float64_half
, s
)) {
3578 /* range 0.25 <= a < 0.5 */
3580 /* a in units of 1/512 rounded down */
3581 /* q0 = (int)(a * 512.0); */
3582 q
= float64_mul(float64_512
, a
, s
);
3583 q_int
= float64_to_int64_round_to_zero(q
, s
);
3585 /* reciprocal root r */
3586 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3587 q
= int64_to_float64(q_int
, s
);
3588 q
= float64_add(q
, float64_half
, s
);
3589 q
= float64_div(q
, float64_512
, s
);
3590 q
= float64_sqrt(q
, s
);
3591 q
= float64_div(float64_one
, q
, s
);
3593 /* range 0.5 <= a < 1.0 */
3595 /* a in units of 1/256 rounded down */
3596 /* q1 = (int)(a * 256.0); */
3597 q
= float64_mul(float64_256
, a
, s
);
3598 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3600 /* reciprocal root r */
3601 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3602 q
= int64_to_float64(q_int
, s
);
3603 q
= float64_add(q
, float64_half
, s
);
3604 q
= float64_div(q
, float64_256
, s
);
3605 q
= float64_sqrt(q
, s
);
3606 q
= float64_div(float64_one
, q
, s
);
3608 /* r in units of 1/256 rounded to nearest */
3609 /* s = (int)(256.0 * r + 0.5); */
3611 q
= float64_mul(q
, float64_256
,s
);
3612 q
= float64_add(q
, float64_half
, s
);
3613 q_int
= float64_to_int64_round_to_zero(q
, s
);
3615 /* return (double)s / 256.0;*/
3616 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3619 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3621 float_status
*s
= &env
->vfp
.standard_fp_status
;
3627 val
= float32_val(a
);
3629 if (float32_is_any_nan(a
)) {
3630 if (float32_is_signaling_nan(a
)) {
3631 float_raise(float_flag_invalid
, s
);
3633 return float32_default_nan
;
3634 } else if (float32_is_zero_or_denormal(a
)) {
3635 if (!float32_is_zero(a
)) {
3636 float_raise(float_flag_input_denormal
, s
);
3638 float_raise(float_flag_divbyzero
, s
);
3639 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3640 } else if (float32_is_neg(a
)) {
3641 float_raise(float_flag_invalid
, s
);
3642 return float32_default_nan
;
3643 } else if (float32_is_infinity(a
)) {
3644 return float32_zero
;
3647 /* Normalize to a double-precision value between 0.25 and 1.0,
3648 * preserving the parity of the exponent. */
3649 if ((val
& 0x800000) == 0) {
3650 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3652 | ((uint64_t)(val
& 0x7fffff) << 29));
3654 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3656 | ((uint64_t)(val
& 0x7fffff) << 29));
3659 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3661 f64
= recip_sqrt_estimate(f64
, env
);
3663 val64
= float64_val(f64
);
3665 val
= ((result_exp
& 0xff) << 23)
3666 | ((val64
>> 29) & 0x7fffff);
3667 return make_float32(val
);
3670 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3674 if ((a
& 0x80000000) == 0) {
3678 f64
= make_float64((0x3feULL
<< 52)
3679 | ((int64_t)(a
& 0x7fffffff) << 21));
3681 f64
= recip_estimate (f64
, env
);
3683 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3686 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3690 if ((a
& 0xc0000000) == 0) {
3694 if (a
& 0x80000000) {
3695 f64
= make_float64((0x3feULL
<< 52)
3696 | ((uint64_t)(a
& 0x7fffffff) << 21));
3697 } else { /* bits 31-30 == '01' */
3698 f64
= make_float64((0x3fdULL
<< 52)
3699 | ((uint64_t)(a
& 0x3fffffff) << 22));
3702 f64
= recip_sqrt_estimate(f64
, env
);
3704 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3707 /* VFPv4 fused multiply-accumulate */
3708 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3710 float_status
*fpst
= fpstp
;
3711 return float32_muladd(a
, b
, c
, 0, fpst
);
3714 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3716 float_status
*fpst
= fpstp
;
3717 return float64_muladd(a
, b
, c
, 0, fpst
);