]>
git.proxmox.com Git - mirror_qemu.git/blob - target-arm/helper.c
10 static uint32_t cortexa8_cp15_c0_c1
[8] =
11 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
13 static uint32_t cortexa8_cp15_c0_c2
[8] =
14 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
16 static uint32_t mpcore_cp15_c0_c1
[8] =
17 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
19 static uint32_t mpcore_cp15_c0_c2
[8] =
20 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
22 static uint32_t arm1136_cp15_c0_c1
[8] =
23 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
25 static uint32_t arm1136_cp15_c0_c2
[8] =
26 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
28 static uint32_t cpu_arm_find_by_name(const char *name
);
30 static inline void set_feature(CPUARMState
*env
, int feature
)
32 env
->features
|= 1u << feature
;
35 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
37 env
->cp15
.c0_cpuid
= id
;
39 case ARM_CPUID_ARM926
:
40 set_feature(env
, ARM_FEATURE_VFP
);
41 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
42 env
->cp15
.c0_cachetype
= 0x1dd20d2;
43 env
->cp15
.c1_sys
= 0x00090078;
45 case ARM_CPUID_ARM946
:
46 set_feature(env
, ARM_FEATURE_MPU
);
47 env
->cp15
.c0_cachetype
= 0x0f004006;
48 env
->cp15
.c1_sys
= 0x00000078;
50 case ARM_CPUID_ARM1026
:
51 set_feature(env
, ARM_FEATURE_VFP
);
52 set_feature(env
, ARM_FEATURE_AUXCR
);
53 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
54 env
->cp15
.c0_cachetype
= 0x1dd20d2;
55 env
->cp15
.c1_sys
= 0x00090078;
57 case ARM_CPUID_ARM1136
:
58 set_feature(env
, ARM_FEATURE_V6
);
59 set_feature(env
, ARM_FEATURE_VFP
);
60 set_feature(env
, ARM_FEATURE_AUXCR
);
61 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
62 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
63 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
64 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
65 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
66 env
->cp15
.c0_cachetype
= 0x1dd20d2;
68 case ARM_CPUID_ARM11MPCORE
:
69 set_feature(env
, ARM_FEATURE_V6
);
70 set_feature(env
, ARM_FEATURE_V6K
);
71 set_feature(env
, ARM_FEATURE_VFP
);
72 set_feature(env
, ARM_FEATURE_AUXCR
);
73 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
74 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
75 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
76 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
77 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
78 env
->cp15
.c0_cachetype
= 0x1dd20d2;
80 case ARM_CPUID_CORTEXA8
:
81 set_feature(env
, ARM_FEATURE_V6
);
82 set_feature(env
, ARM_FEATURE_V6K
);
83 set_feature(env
, ARM_FEATURE_V7
);
84 set_feature(env
, ARM_FEATURE_AUXCR
);
85 set_feature(env
, ARM_FEATURE_THUMB2
);
86 set_feature(env
, ARM_FEATURE_VFP
);
87 set_feature(env
, ARM_FEATURE_VFP3
);
88 set_feature(env
, ARM_FEATURE_NEON
);
89 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
90 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
91 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
92 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
93 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
94 env
->cp15
.c0_cachetype
= 0x1dd20d2;
96 case ARM_CPUID_CORTEXM3
:
97 set_feature(env
, ARM_FEATURE_V6
);
98 set_feature(env
, ARM_FEATURE_THUMB2
);
99 set_feature(env
, ARM_FEATURE_V7
);
100 set_feature(env
, ARM_FEATURE_M
);
101 set_feature(env
, ARM_FEATURE_DIV
);
103 case ARM_CPUID_ANY
: /* For userspace emulation. */
104 set_feature(env
, ARM_FEATURE_V6
);
105 set_feature(env
, ARM_FEATURE_V6K
);
106 set_feature(env
, ARM_FEATURE_V7
);
107 set_feature(env
, ARM_FEATURE_THUMB2
);
108 set_feature(env
, ARM_FEATURE_VFP
);
109 set_feature(env
, ARM_FEATURE_VFP3
);
110 set_feature(env
, ARM_FEATURE_NEON
);
111 set_feature(env
, ARM_FEATURE_DIV
);
113 case ARM_CPUID_TI915T
:
114 case ARM_CPUID_TI925T
:
115 set_feature(env
, ARM_FEATURE_OMAPCP
);
116 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
117 env
->cp15
.c0_cachetype
= 0x5109149;
118 env
->cp15
.c1_sys
= 0x00000070;
119 env
->cp15
.c15_i_max
= 0x000;
120 env
->cp15
.c15_i_min
= 0xff0;
122 case ARM_CPUID_PXA250
:
123 case ARM_CPUID_PXA255
:
124 case ARM_CPUID_PXA260
:
125 case ARM_CPUID_PXA261
:
126 case ARM_CPUID_PXA262
:
127 set_feature(env
, ARM_FEATURE_XSCALE
);
128 /* JTAG_ID is ((id << 28) | 0x09265013) */
129 env
->cp15
.c0_cachetype
= 0xd172172;
130 env
->cp15
.c1_sys
= 0x00000078;
132 case ARM_CPUID_PXA270_A0
:
133 case ARM_CPUID_PXA270_A1
:
134 case ARM_CPUID_PXA270_B0
:
135 case ARM_CPUID_PXA270_B1
:
136 case ARM_CPUID_PXA270_C0
:
137 case ARM_CPUID_PXA270_C5
:
138 set_feature(env
, ARM_FEATURE_XSCALE
);
139 /* JTAG_ID is ((id << 28) | 0x09265013) */
140 set_feature(env
, ARM_FEATURE_IWMMXT
);
141 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
142 env
->cp15
.c0_cachetype
= 0xd172172;
143 env
->cp15
.c1_sys
= 0x00000078;
146 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
151 void cpu_reset(CPUARMState
*env
)
154 id
= env
->cp15
.c0_cpuid
;
155 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
157 cpu_reset_model_id(env
, id
);
158 #if defined (CONFIG_USER_ONLY)
159 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
160 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
162 /* SVC mode with interrupts disabled. */
163 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
164 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
167 env
->uncached_cpsr
&= ~CPSR_I
;
168 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
174 CPUARMState
*cpu_arm_init(const char *cpu_model
)
178 static int inited
= 0;
180 id
= cpu_arm_find_by_name(cpu_model
);
183 env
= qemu_mallocz(sizeof(CPUARMState
));
189 arm_translate_init();
192 env
->cpu_model_str
= cpu_model
;
193 env
->cp15
.c0_cpuid
= id
;
203 static const struct arm_cpu_t arm_cpu_names
[] = {
204 { ARM_CPUID_ARM926
, "arm926"},
205 { ARM_CPUID_ARM946
, "arm946"},
206 { ARM_CPUID_ARM1026
, "arm1026"},
207 { ARM_CPUID_ARM1136
, "arm1136"},
208 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
209 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
210 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
211 { ARM_CPUID_TI925T
, "ti925t" },
212 { ARM_CPUID_PXA250
, "pxa250" },
213 { ARM_CPUID_PXA255
, "pxa255" },
214 { ARM_CPUID_PXA260
, "pxa260" },
215 { ARM_CPUID_PXA261
, "pxa261" },
216 { ARM_CPUID_PXA262
, "pxa262" },
217 { ARM_CPUID_PXA270
, "pxa270" },
218 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
219 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
220 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
221 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
222 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
223 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
224 { ARM_CPUID_ANY
, "any"},
228 void arm_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
232 (*cpu_fprintf
)(f
, "Available CPUs:\n");
233 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
234 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
238 /* return 0 if not found */
239 static uint32_t cpu_arm_find_by_name(const char *name
)
245 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
246 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
247 id
= arm_cpu_names
[i
].id
;
254 void cpu_arm_close(CPUARMState
*env
)
259 /* Polynomial multiplication is like integer multiplcation except the
260 partial products are XORed, not added. */
261 uint32_t helper_neon_mul_p8(uint32_t op1
, uint32_t op2
)
273 mask
|= (0xff << 16);
275 mask
|= (0xff << 24);
276 result
^= op2
& mask
;
277 op1
= (op1
>> 1) & 0x7f7f7f7f;
278 op2
= (op2
<< 1) & 0xfefefefe;
283 uint32_t cpsr_read(CPUARMState
*env
)
286 ZF
= (env
->NZF
== 0);
287 return env
->uncached_cpsr
| (env
->NZF
& 0x80000000) | (ZF
<< 30) |
288 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
289 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
290 | ((env
->condexec_bits
& 0xfc) << 8)
294 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
296 /* NOTE: N = 1 and Z = 1 cannot be stored currently */
297 if (mask
& CPSR_NZCV
) {
298 env
->NZF
= (val
& 0xc0000000) ^ 0x40000000;
299 env
->CF
= (val
>> 29) & 1;
300 env
->VF
= (val
<< 3) & 0x80000000;
303 env
->QF
= ((val
& CPSR_Q
) != 0);
305 env
->thumb
= ((val
& CPSR_T
) != 0);
306 if (mask
& CPSR_IT_0_1
) {
307 env
->condexec_bits
&= ~3;
308 env
->condexec_bits
|= (val
>> 25) & 3;
310 if (mask
& CPSR_IT_2_7
) {
311 env
->condexec_bits
&= 3;
312 env
->condexec_bits
|= (val
>> 8) & 0xfc;
314 if (mask
& CPSR_GE
) {
315 env
->GE
= (val
>> 16) & 0xf;
318 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
319 switch_mode(env
, val
& CPSR_M
);
321 mask
&= ~CACHED_CPSR_BITS
;
322 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
325 /* Sign/zero extend */
326 uint32_t HELPER(sxtb16
)(uint32_t x
)
329 res
= (uint16_t)(int8_t)x
;
330 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
334 uint32_t HELPER(uxtb16
)(uint32_t x
)
337 res
= (uint16_t)(uint8_t)x
;
338 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
342 uint32_t HELPER(clz
)(uint32_t x
)
345 for (count
= 32; x
; count
--)
350 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
357 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
364 uint32_t HELPER(rbit
)(uint32_t x
)
366 x
= ((x
& 0xff000000) >> 24)
367 | ((x
& 0x00ff0000) >> 8)
368 | ((x
& 0x0000ff00) << 8)
369 | ((x
& 0x000000ff) << 24);
370 x
= ((x
& 0xf0f0f0f0) >> 4)
371 | ((x
& 0x0f0f0f0f) << 4);
372 x
= ((x
& 0x88888888) >> 3)
373 | ((x
& 0x44444444) >> 1)
374 | ((x
& 0x22222222) << 1)
375 | ((x
& 0x11111111) << 3);
379 #if defined(CONFIG_USER_ONLY)
381 void do_interrupt (CPUState
*env
)
383 env
->exception_index
= -1;
386 /* Structure used to record exclusive memory locations. */
387 typedef struct mmon_state
{
388 struct mmon_state
*next
;
389 CPUARMState
*cpu_env
;
393 /* Chain of current locks. */
394 static mmon_state
* mmon_head
= NULL
;
396 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
397 int mmu_idx
, int is_softmmu
)
400 env
->exception_index
= EXCP_PREFETCH_ABORT
;
401 env
->cp15
.c6_insn
= address
;
403 env
->exception_index
= EXCP_DATA_ABORT
;
404 env
->cp15
.c6_data
= address
;
409 static void allocate_mmon_state(CPUState
*env
)
411 env
->mmon_entry
= malloc(sizeof (mmon_state
));
412 if (!env
->mmon_entry
)
414 memset (env
->mmon_entry
, 0, sizeof (mmon_state
));
415 env
->mmon_entry
->cpu_env
= env
;
416 mmon_head
= env
->mmon_entry
;
419 /* Flush any monitor locks for the specified address. */
420 static void flush_mmon(uint32_t addr
)
424 for (mon
= mmon_head
; mon
; mon
= mon
->next
)
426 if (mon
->addr
!= addr
)
434 /* Mark an address for exclusive access. */
435 void helper_mark_exclusive(CPUState
*env
, uint32_t addr
)
437 if (!env
->mmon_entry
)
438 allocate_mmon_state(env
);
439 /* Clear any previous locks. */
441 env
->mmon_entry
->addr
= addr
;
444 /* Test if an exclusive address is still exclusive. Returns zero
445 if the address is still exclusive. */
446 int helper_test_exclusive(CPUState
*env
, uint32_t addr
)
450 if (!env
->mmon_entry
)
452 if (env
->mmon_entry
->addr
== addr
)
460 void helper_clrex(CPUState
*env
)
462 if (!(env
->mmon_entry
&& env
->mmon_entry
->addr
))
464 flush_mmon(env
->mmon_entry
->addr
);
467 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
472 /* These should probably raise undefined insn exceptions. */
473 void helper_set_cp(CPUState
*env
, uint32_t insn
, uint32_t val
)
475 int op1
= (insn
>> 8) & 0xf;
476 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
480 uint32_t helper_get_cp(CPUState
*env
, uint32_t insn
)
482 int op1
= (insn
>> 8) & 0xf;
483 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
487 void helper_set_cp15(CPUState
*env
, uint32_t insn
, uint32_t val
)
489 cpu_abort(env
, "cp15 insn %08x\n", insn
);
492 uint32_t helper_get_cp15(CPUState
*env
, uint32_t insn
)
494 cpu_abort(env
, "cp15 insn %08x\n", insn
);
498 /* These should probably raise undefined insn exceptions. */
499 void helper_v7m_msr(CPUState
*env
, int reg
, uint32_t val
)
501 cpu_abort(env
, "v7m_mrs %d\n", reg
);
504 uint32_t helper_v7m_mrs(CPUState
*env
, int reg
)
506 cpu_abort(env
, "v7m_mrs %d\n", reg
);
510 void switch_mode(CPUState
*env
, int mode
)
512 if (mode
!= ARM_CPU_MODE_USR
)
513 cpu_abort(env
, "Tried to switch out of user mode\n");
516 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
518 cpu_abort(env
, "banked r13 write\n");
521 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
523 cpu_abort(env
, "banked r13 read\n");
529 extern int semihosting_enabled
;
531 /* Map CPU modes onto saved register banks. */
532 static inline int bank_number (int mode
)
535 case ARM_CPU_MODE_USR
:
536 case ARM_CPU_MODE_SYS
:
538 case ARM_CPU_MODE_SVC
:
540 case ARM_CPU_MODE_ABT
:
542 case ARM_CPU_MODE_UND
:
544 case ARM_CPU_MODE_IRQ
:
546 case ARM_CPU_MODE_FIQ
:
549 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
553 void switch_mode(CPUState
*env
, int mode
)
558 old_mode
= env
->uncached_cpsr
& CPSR_M
;
559 if (mode
== old_mode
)
562 if (old_mode
== ARM_CPU_MODE_FIQ
) {
563 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
564 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
565 } else if (mode
== ARM_CPU_MODE_FIQ
) {
566 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
567 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
570 i
= bank_number(old_mode
);
571 env
->banked_r13
[i
] = env
->regs
[13];
572 env
->banked_r14
[i
] = env
->regs
[14];
573 env
->banked_spsr
[i
] = env
->spsr
;
575 i
= bank_number(mode
);
576 env
->regs
[13] = env
->banked_r13
[i
];
577 env
->regs
[14] = env
->banked_r14
[i
];
578 env
->spsr
= env
->banked_spsr
[i
];
581 static void v7m_push(CPUARMState
*env
, uint32_t val
)
584 stl_phys(env
->regs
[13], val
);
587 static uint32_t v7m_pop(CPUARMState
*env
)
590 val
= ldl_phys(env
->regs
[13]);
595 /* Switch to V7M main or process stack pointer. */
596 static void switch_v7m_sp(CPUARMState
*env
, int process
)
599 if (env
->v7m
.current_sp
!= process
) {
600 tmp
= env
->v7m
.other_sp
;
601 env
->v7m
.other_sp
= env
->regs
[13];
603 env
->v7m
.current_sp
= process
;
607 static void do_v7m_exception_exit(CPUARMState
*env
)
612 type
= env
->regs
[15];
613 if (env
->v7m
.exception
!= 0)
614 armv7m_nvic_complete_irq(env
->v7m
.nvic
, env
->v7m
.exception
);
616 /* Switch to the target stack. */
617 switch_v7m_sp(env
, (type
& 4) != 0);
619 env
->regs
[0] = v7m_pop(env
);
620 env
->regs
[1] = v7m_pop(env
);
621 env
->regs
[2] = v7m_pop(env
);
622 env
->regs
[3] = v7m_pop(env
);
623 env
->regs
[12] = v7m_pop(env
);
624 env
->regs
[14] = v7m_pop(env
);
625 env
->regs
[15] = v7m_pop(env
);
627 xpsr_write(env
, xpsr
, 0xfffffdff);
628 /* Undo stack alignment. */
631 /* ??? The exception return type specifies Thread/Handler mode. However
632 this is also implied by the xPSR value. Not sure what to do
633 if there is a mismatch. */
634 /* ??? Likewise for mismatches between the CONTROL register and the stack
638 void do_interrupt_v7m(CPUARMState
*env
)
640 uint32_t xpsr
= xpsr_read(env
);
645 if (env
->v7m
.current_sp
)
647 if (env
->v7m
.exception
== 0)
650 /* For exceptions we just mark as pending on the NVIC, and let that
652 /* TODO: Need to escalate if the current priority is higher than the
653 one we're raising. */
654 switch (env
->exception_index
) {
656 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_USAGE
);
660 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_SVC
);
662 case EXCP_PREFETCH_ABORT
:
663 case EXCP_DATA_ABORT
:
664 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_MEM
);
667 if (semihosting_enabled
) {
669 nr
= lduw_code(env
->regs
[15]) & 0xff;
672 env
->regs
[0] = do_arm_semihosting(env
);
676 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_DEBUG
);
679 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->v7m
.nvic
);
681 case EXCP_EXCEPTION_EXIT
:
682 do_v7m_exception_exit(env
);
685 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
686 return; /* Never happens. Keep compiler happy. */
689 /* Align stack pointer. */
690 /* ??? Should only do this if Configuration Control Register
691 STACKALIGN bit is set. */
692 if (env
->regs
[13] & 4) {
696 /* Switch to the hander mode. */
698 v7m_push(env
, env
->regs
[15]);
699 v7m_push(env
, env
->regs
[14]);
700 v7m_push(env
, env
->regs
[12]);
701 v7m_push(env
, env
->regs
[3]);
702 v7m_push(env
, env
->regs
[2]);
703 v7m_push(env
, env
->regs
[1]);
704 v7m_push(env
, env
->regs
[0]);
705 switch_v7m_sp(env
, 0);
706 env
->uncached_cpsr
&= ~CPSR_IT
;
708 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
709 env
->regs
[15] = addr
& 0xfffffffe;
710 env
->thumb
= addr
& 1;
713 /* Handle a CPU exception. */
714 void do_interrupt(CPUARMState
*env
)
722 do_interrupt_v7m(env
);
725 /* TODO: Vectored interrupt controller. */
726 switch (env
->exception_index
) {
728 new_mode
= ARM_CPU_MODE_UND
;
737 if (semihosting_enabled
) {
738 /* Check for semihosting interrupt. */
740 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
742 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
744 /* Only intercept calls from privileged modes, to provide some
745 semblance of security. */
746 if (((mask
== 0x123456 && !env
->thumb
)
747 || (mask
== 0xab && env
->thumb
))
748 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
749 env
->regs
[0] = do_arm_semihosting(env
);
753 new_mode
= ARM_CPU_MODE_SVC
;
756 /* The PC already points to the next instructon. */
760 /* See if this is a semihosting syscall. */
761 if (env
->thumb
&& semihosting_enabled
) {
762 mask
= lduw_code(env
->regs
[15]) & 0xff;
764 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
766 env
->regs
[0] = do_arm_semihosting(env
);
770 /* Fall through to prefetch abort. */
771 case EXCP_PREFETCH_ABORT
:
772 new_mode
= ARM_CPU_MODE_ABT
;
774 mask
= CPSR_A
| CPSR_I
;
777 case EXCP_DATA_ABORT
:
778 new_mode
= ARM_CPU_MODE_ABT
;
780 mask
= CPSR_A
| CPSR_I
;
784 new_mode
= ARM_CPU_MODE_IRQ
;
786 /* Disable IRQ and imprecise data aborts. */
787 mask
= CPSR_A
| CPSR_I
;
791 new_mode
= ARM_CPU_MODE_FIQ
;
793 /* Disable FIQ, IRQ and imprecise data aborts. */
794 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
798 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
799 return; /* Never happens. Keep compiler happy. */
802 if (env
->cp15
.c1_sys
& (1 << 13)) {
805 switch_mode (env
, new_mode
);
806 env
->spsr
= cpsr_read(env
);
808 env
->condexec_bits
= 0;
809 /* Switch to the new mode, and switch to Arm mode. */
810 /* ??? Thumb interrupt handlers not implemented. */
811 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
812 env
->uncached_cpsr
|= mask
;
814 env
->regs
[14] = env
->regs
[15] + offset
;
815 env
->regs
[15] = addr
;
816 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
819 /* Check section/page access permissions.
820 Returns the page protection flags, or zero if the access is not
822 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
828 return PAGE_READ
| PAGE_WRITE
;
830 if (access_type
== 1)
837 if (access_type
== 1)
839 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
841 return is_user
? 0 : PAGE_READ
;
848 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
853 return PAGE_READ
| PAGE_WRITE
;
855 return PAGE_READ
| PAGE_WRITE
;
856 case 4: case 7: /* Reserved. */
859 return is_user
? 0 : prot_ro
;
867 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
868 int is_user
, uint32_t *phys_ptr
, int *prot
)
878 /* Pagetable walk. */
879 /* Lookup l1 descriptor. */
880 if (address
& env
->cp15
.c2_mask
)
881 table
= env
->cp15
.c2_base1
;
883 table
= env
->cp15
.c2_base0
;
884 table
= (table
& 0xffffc000) | ((address
>> 18) & 0x3ffc);
885 desc
= ldl_phys(table
);
887 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
889 /* Secton translation fault. */
893 if (domain
== 0 || domain
== 2) {
895 code
= 9; /* Section domain fault. */
897 code
= 11; /* Page domain fault. */
902 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
903 ap
= (desc
>> 10) & 3;
906 /* Lookup l2 entry. */
908 /* Coarse pagetable. */
909 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
911 /* Fine pagetable. */
912 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
914 desc
= ldl_phys(table
);
916 case 0: /* Page translation fault. */
919 case 1: /* 64k page. */
920 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
921 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
923 case 2: /* 4k page. */
924 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
925 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
927 case 3: /* 1k page. */
929 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
930 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
932 /* Page translation fault. */
937 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
939 ap
= (desc
>> 4) & 3;
942 /* Never happens, but compiler isn't smart enough to tell. */
947 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
949 /* Access permission fault. */
952 *phys_ptr
= phys_addr
;
955 return code
| (domain
<< 4);
958 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
959 int is_user
, uint32_t *phys_ptr
, int *prot
)
970 /* Pagetable walk. */
971 /* Lookup l1 descriptor. */
972 if (address
& env
->cp15
.c2_mask
)
973 table
= env
->cp15
.c2_base1
;
975 table
= env
->cp15
.c2_base0
;
976 table
= (table
& 0xffffc000) | ((address
>> 18) & 0x3ffc);
977 desc
= ldl_phys(table
);
980 /* Secton translation fault. */
984 } else if (type
== 2 && (desc
& (1 << 18))) {
988 /* Section or page. */
989 domain
= (desc
>> 4) & 0x1e;
991 domain
= (env
->cp15
.c3
>> domain
) & 3;
992 if (domain
== 0 || domain
== 2) {
994 code
= 9; /* Section domain fault. */
996 code
= 11; /* Page domain fault. */
1000 if (desc
& (1 << 18)) {
1002 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1005 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1007 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1008 xn
= desc
& (1 << 4);
1011 /* Lookup l2 entry. */
1012 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1013 desc
= ldl_phys(table
);
1014 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1016 case 0: /* Page translation fault. */
1019 case 1: /* 64k page. */
1020 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1021 xn
= desc
& (1 << 15);
1023 case 2: case 3: /* 4k page. */
1024 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1028 /* Never happens, but compiler isn't smart enough to tell. */
1033 if (xn
&& access_type
== 2)
1036 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1038 /* Access permission fault. */
1041 *phys_ptr
= phys_addr
;
1044 return code
| (domain
<< 4);
1047 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1048 int is_user
, uint32_t *phys_ptr
, int *prot
)
1054 *phys_ptr
= address
;
1055 for (n
= 7; n
>= 0; n
--) {
1056 base
= env
->cp15
.c6_region
[n
];
1057 if ((base
& 1) == 0)
1059 mask
= 1 << ((base
>> 1) & 0x1f);
1060 /* Keep this shift separate from the above to avoid an
1061 (undefined) << 32. */
1062 mask
= (mask
<< 1) - 1;
1063 if (((base
^ address
) & ~mask
) == 0)
1069 if (access_type
== 2) {
1070 mask
= env
->cp15
.c5_insn
;
1072 mask
= env
->cp15
.c5_data
;
1074 mask
= (mask
>> (n
* 4)) & 0xf;
1081 *prot
= PAGE_READ
| PAGE_WRITE
;
1086 *prot
|= PAGE_WRITE
;
1089 *prot
= PAGE_READ
| PAGE_WRITE
;
1100 /* Bad permission. */
1106 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1107 int access_type
, int is_user
,
1108 uint32_t *phys_ptr
, int *prot
)
1110 /* Fast Context Switch Extension. */
1111 if (address
< 0x02000000)
1112 address
+= env
->cp15
.c13_fcse
;
1114 if ((env
->cp15
.c1_sys
& 1) == 0) {
1115 /* MMU/MPU disabled. */
1116 *phys_ptr
= address
;
1117 *prot
= PAGE_READ
| PAGE_WRITE
;
1119 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1120 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1122 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1123 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1126 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1131 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1132 int access_type
, int mmu_idx
, int is_softmmu
)
1138 is_user
= mmu_idx
== MMU_USER_IDX
;
1139 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
);
1141 /* Map a single [sub]page. */
1142 phys_addr
&= ~(uint32_t)0x3ff;
1143 address
&= ~(uint32_t)0x3ff;
1144 return tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
,
1148 if (access_type
== 2) {
1149 env
->cp15
.c5_insn
= ret
;
1150 env
->cp15
.c6_insn
= address
;
1151 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1153 env
->cp15
.c5_data
= ret
;
1154 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1155 env
->cp15
.c5_data
|= (1 << 11);
1156 env
->cp15
.c6_data
= address
;
1157 env
->exception_index
= EXCP_DATA_ABORT
;
1162 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1168 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
);
1176 /* Not really implemented. Need to figure out a sane way of doing this.
1177 Maybe add generic watchpoint support and use that. */
1179 void helper_mark_exclusive(CPUState
*env
, uint32_t addr
)
1181 env
->mmon_addr
= addr
;
1184 int helper_test_exclusive(CPUState
*env
, uint32_t addr
)
1186 return (env
->mmon_addr
!= addr
);
1189 void helper_clrex(CPUState
*env
)
1191 env
->mmon_addr
= -1;
1194 void helper_set_cp(CPUState
*env
, uint32_t insn
, uint32_t val
)
1196 int cp_num
= (insn
>> 8) & 0xf;
1197 int cp_info
= (insn
>> 5) & 7;
1198 int src
= (insn
>> 16) & 0xf;
1199 int operand
= insn
& 0xf;
1201 if (env
->cp
[cp_num
].cp_write
)
1202 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1203 cp_info
, src
, operand
, val
);
1206 uint32_t helper_get_cp(CPUState
*env
, uint32_t insn
)
1208 int cp_num
= (insn
>> 8) & 0xf;
1209 int cp_info
= (insn
>> 5) & 7;
1210 int dest
= (insn
>> 16) & 0xf;
1211 int operand
= insn
& 0xf;
1213 if (env
->cp
[cp_num
].cp_read
)
1214 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1215 cp_info
, dest
, operand
);
1219 /* Return basic MPU access permission bits. */
1220 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1227 for (i
= 0; i
< 16; i
+= 2) {
1228 ret
|= (val
>> i
) & mask
;
1234 /* Pad basic MPU access permission bits to extended format. */
1235 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1242 for (i
= 0; i
< 16; i
+= 2) {
1243 ret
|= (val
& mask
) << i
;
1249 void helper_set_cp15(CPUState
*env
, uint32_t insn
, uint32_t val
)
1255 op1
= (insn
>> 21) & 7;
1256 op2
= (insn
>> 5) & 7;
1258 switch ((insn
>> 16) & 0xf) {
1260 if (((insn
>> 21) & 7) == 2) {
1261 /* ??? Select cache level. Ignore. */
1265 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1267 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1270 case 1: /* System configuration. */
1271 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1275 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1276 env
->cp15
.c1_sys
= val
;
1277 /* ??? Lots of these bits are not implemented. */
1278 /* This may enable/disable the MMU, so do a TLB flush. */
1281 case 1: /* Auxiliary cotrol register. */
1282 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1283 env
->cp15
.c1_xscaleauxcr
= val
;
1286 /* Not implemented. */
1289 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1291 env
->cp15
.c1_coproc
= val
;
1292 /* ??? Is this safe when called from within a TB? */
1299 case 2: /* MMU Page table control / MPU cache control. */
1300 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1303 env
->cp15
.c2_data
= val
;
1306 env
->cp15
.c2_insn
= val
;
1314 env
->cp15
.c2_base0
= val
;
1317 env
->cp15
.c2_base1
= val
;
1320 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1327 case 3: /* MMU Domain access control / MPU write buffer control. */
1329 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1331 case 4: /* Reserved. */
1333 case 5: /* MMU Fault status / MPU access permission. */
1334 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1338 if (arm_feature(env
, ARM_FEATURE_MPU
))
1339 val
= extended_mpu_ap_bits(val
);
1340 env
->cp15
.c5_data
= val
;
1343 if (arm_feature(env
, ARM_FEATURE_MPU
))
1344 val
= extended_mpu_ap_bits(val
);
1345 env
->cp15
.c5_insn
= val
;
1348 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1350 env
->cp15
.c5_data
= val
;
1353 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1355 env
->cp15
.c5_insn
= val
;
1361 case 6: /* MMU Fault address / MPU base/size. */
1362 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1365 env
->cp15
.c6_region
[crm
] = val
;
1367 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1371 env
->cp15
.c6_data
= val
;
1373 case 1: /* ??? This is WFAR on armv6 */
1375 env
->cp15
.c6_insn
= val
;
1382 case 7: /* Cache control. */
1383 env
->cp15
.c15_i_max
= 0x000;
1384 env
->cp15
.c15_i_min
= 0xff0;
1385 /* No cache, so nothing to do. */
1386 /* ??? MPCore has VA to PA translation functions. */
1388 case 8: /* MMU TLB control. */
1390 case 0: /* Invalidate all. */
1393 case 1: /* Invalidate single TLB entry. */
1395 /* ??? This is wrong for large pages and sections. */
1396 /* As an ugly hack to make linux work we always flush a 4K
1399 tlb_flush_page(env
, val
);
1400 tlb_flush_page(env
, val
+ 0x400);
1401 tlb_flush_page(env
, val
+ 0x800);
1402 tlb_flush_page(env
, val
+ 0xc00);
1407 case 2: /* Invalidate on ASID. */
1408 tlb_flush(env
, val
== 0);
1410 case 3: /* Invalidate single entry on MVA. */
1411 /* ??? This is like case 1, but ignores ASID. */
1419 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1422 case 0: /* Cache lockdown. */
1424 case 0: /* L1 cache. */
1427 env
->cp15
.c9_data
= val
;
1430 env
->cp15
.c9_insn
= val
;
1436 case 1: /* L2 cache. */
1437 /* Ignore writes to L2 lockdown/auxiliary registers. */
1443 case 1: /* TCM memory region registers. */
1444 /* Not implemented. */
1450 case 10: /* MMU TLB lockdown. */
1451 /* ??? TLB lockdown not implemented. */
1453 case 12: /* Reserved. */
1455 case 13: /* Process ID. */
1458 /* Unlike real hardware the qemu TLB uses virtual addresses,
1459 not modified virtual addresses, so this causes a TLB flush.
1461 if (env
->cp15
.c13_fcse
!= val
)
1463 env
->cp15
.c13_fcse
= val
;
1466 /* This changes the ASID, so do a TLB flush. */
1467 if (env
->cp15
.c13_context
!= val
1468 && !arm_feature(env
, ARM_FEATURE_MPU
))
1470 env
->cp15
.c13_context
= val
;
1473 env
->cp15
.c13_tls1
= val
;
1476 env
->cp15
.c13_tls2
= val
;
1479 env
->cp15
.c13_tls3
= val
;
1485 case 14: /* Reserved. */
1487 case 15: /* Implementation specific. */
1488 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1489 if (op2
== 0 && crm
== 1) {
1490 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1491 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1493 env
->cp15
.c15_cpar
= val
& 0x3fff;
1499 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1503 case 1: /* Set TI925T configuration. */
1504 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1505 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1506 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1508 case 2: /* Set I_max. */
1509 env
->cp15
.c15_i_max
= val
;
1511 case 3: /* Set I_min. */
1512 env
->cp15
.c15_i_min
= val
;
1514 case 4: /* Set thread-ID. */
1515 env
->cp15
.c15_threadid
= val
& 0xffff;
1517 case 8: /* Wait-for-interrupt (deprecated). */
1518 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1528 /* ??? For debugging only. Should raise illegal instruction exception. */
1529 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1530 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1533 uint32_t helper_get_cp15(CPUState
*env
, uint32_t insn
)
1539 op1
= (insn
>> 21) & 7;
1540 op2
= (insn
>> 5) & 7;
1542 switch ((insn
>> 16) & 0xf) {
1543 case 0: /* ID codes. */
1549 case 0: /* Device ID. */
1550 return env
->cp15
.c0_cpuid
;
1551 case 1: /* Cache Type. */
1552 return env
->cp15
.c0_cachetype
;
1553 case 2: /* TCM status. */
1555 case 3: /* TLB type register. */
1556 return 0; /* No lockable TLB entries. */
1557 case 5: /* CPU ID */
1558 return env
->cpu_index
;
1563 if (!arm_feature(env
, ARM_FEATURE_V6
))
1565 return env
->cp15
.c0_c1
[op2
];
1567 if (!arm_feature(env
, ARM_FEATURE_V6
))
1569 return env
->cp15
.c0_c2
[op2
];
1570 case 3: case 4: case 5: case 6: case 7:
1576 /* These registers aren't documented on arm11 cores. However
1577 Linux looks at them anyway. */
1578 if (!arm_feature(env
, ARM_FEATURE_V6
))
1582 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1588 case 1: /* System configuration. */
1589 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1592 case 0: /* Control register. */
1593 return env
->cp15
.c1_sys
;
1594 case 1: /* Auxiliary control register. */
1595 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1596 return env
->cp15
.c1_xscaleauxcr
;
1597 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1599 switch (ARM_CPUID(env
)) {
1600 case ARM_CPUID_ARM1026
:
1602 case ARM_CPUID_ARM1136
:
1604 case ARM_CPUID_ARM11MPCORE
:
1606 case ARM_CPUID_CORTEXA8
:
1611 case 2: /* Coprocessor access register. */
1612 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1614 return env
->cp15
.c1_coproc
;
1618 case 2: /* MMU Page table control / MPU cache control. */
1619 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1622 return env
->cp15
.c2_data
;
1625 return env
->cp15
.c2_insn
;
1633 return env
->cp15
.c2_base0
;
1635 return env
->cp15
.c2_base1
;
1641 mask
= env
->cp15
.c2_mask
;
1652 case 3: /* MMU Domain access control / MPU write buffer control. */
1653 return env
->cp15
.c3
;
1654 case 4: /* Reserved. */
1656 case 5: /* MMU Fault status / MPU access permission. */
1657 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1661 if (arm_feature(env
, ARM_FEATURE_MPU
))
1662 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1663 return env
->cp15
.c5_data
;
1665 if (arm_feature(env
, ARM_FEATURE_MPU
))
1666 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1667 return env
->cp15
.c5_insn
;
1669 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1671 return env
->cp15
.c5_data
;
1673 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1675 return env
->cp15
.c5_insn
;
1679 case 6: /* MMU Fault address. */
1680 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1683 return env
->cp15
.c6_region
[crm
];
1685 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1689 return env
->cp15
.c6_data
;
1691 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1692 /* Watchpoint Fault Adrress. */
1693 return 0; /* Not implemented. */
1695 /* Instruction Fault Adrress. */
1696 /* Arm9 doesn't have an IFAR, but implementing it anyway
1697 shouldn't do any harm. */
1698 return env
->cp15
.c6_insn
;
1701 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1702 /* Instruction Fault Adrress. */
1703 return env
->cp15
.c6_insn
;
1711 case 7: /* Cache control. */
1712 /* ??? This is for test, clean and invaidate operations that set the
1713 Z flag. We can't represent N = Z = 1, so it also clears
1714 the N flag. Oh well. */
1717 case 8: /* MMU TLB control. */
1719 case 9: /* Cache lockdown. */
1721 case 0: /* L1 cache. */
1722 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1726 return env
->cp15
.c9_data
;
1728 return env
->cp15
.c9_insn
;
1732 case 1: /* L2 cache */
1735 /* L2 Lockdown and Auxiliary control. */
1740 case 10: /* MMU TLB lockdown. */
1741 /* ??? TLB lockdown not implemented. */
1743 case 11: /* TCM DMA control. */
1744 case 12: /* Reserved. */
1746 case 13: /* Process ID. */
1749 return env
->cp15
.c13_fcse
;
1751 return env
->cp15
.c13_context
;
1753 return env
->cp15
.c13_tls1
;
1755 return env
->cp15
.c13_tls2
;
1757 return env
->cp15
.c13_tls3
;
1761 case 14: /* Reserved. */
1763 case 15: /* Implementation specific. */
1764 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1765 if (op2
== 0 && crm
== 1)
1766 return env
->cp15
.c15_cpar
;
1770 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1774 case 1: /* Read TI925T configuration. */
1775 return env
->cp15
.c15_ticonfig
;
1776 case 2: /* Read I_max. */
1777 return env
->cp15
.c15_i_max
;
1778 case 3: /* Read I_min. */
1779 return env
->cp15
.c15_i_min
;
1780 case 4: /* Read thread-ID. */
1781 return env
->cp15
.c15_threadid
;
1782 case 8: /* TI925T_status */
1790 /* ??? For debugging only. Should raise illegal instruction exception. */
1791 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1792 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1796 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
1798 env
->banked_r13
[bank_number(mode
)] = val
;
1801 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
1803 return env
->banked_r13
[bank_number(mode
)];
1806 uint32_t helper_v7m_mrs(CPUState
*env
, int reg
)
1810 return xpsr_read(env
) & 0xf8000000;
1812 return xpsr_read(env
) & 0xf80001ff;
1814 return xpsr_read(env
) & 0xff00fc00;
1816 return xpsr_read(env
) & 0xff00fdff;
1818 return xpsr_read(env
) & 0x000001ff;
1820 return xpsr_read(env
) & 0x0700fc00;
1822 return xpsr_read(env
) & 0x0700edff;
1824 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1826 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1827 case 16: /* PRIMASK */
1828 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1829 case 17: /* FAULTMASK */
1830 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1831 case 18: /* BASEPRI */
1832 case 19: /* BASEPRI_MAX */
1833 return env
->v7m
.basepri
;
1834 case 20: /* CONTROL */
1835 return env
->v7m
.control
;
1837 /* ??? For debugging only. */
1838 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1843 void helper_v7m_msr(CPUState
*env
, int reg
, uint32_t val
)
1847 xpsr_write(env
, val
, 0xf8000000);
1850 xpsr_write(env
, val
, 0xf8000000);
1853 xpsr_write(env
, val
, 0xfe00fc00);
1856 xpsr_write(env
, val
, 0xfe00fc00);
1859 /* IPSR bits are readonly. */
1862 xpsr_write(env
, val
, 0x0600fc00);
1865 xpsr_write(env
, val
, 0x0600fc00);
1868 if (env
->v7m
.current_sp
)
1869 env
->v7m
.other_sp
= val
;
1871 env
->regs
[13] = val
;
1874 if (env
->v7m
.current_sp
)
1875 env
->regs
[13] = val
;
1877 env
->v7m
.other_sp
= val
;
1879 case 16: /* PRIMASK */
1881 env
->uncached_cpsr
|= CPSR_I
;
1883 env
->uncached_cpsr
&= ~CPSR_I
;
1885 case 17: /* FAULTMASK */
1887 env
->uncached_cpsr
|= CPSR_F
;
1889 env
->uncached_cpsr
&= ~CPSR_F
;
1891 case 18: /* BASEPRI */
1892 env
->v7m
.basepri
= val
& 0xff;
1894 case 19: /* BASEPRI_MAX */
1896 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1897 env
->v7m
.basepri
= val
;
1899 case 20: /* CONTROL */
1900 env
->v7m
.control
= val
& 3;
1901 switch_v7m_sp(env
, (val
& 2) != 0);
1904 /* ??? For debugging only. */
1905 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
1910 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
1911 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
1914 if (cpnum
< 0 || cpnum
> 14) {
1915 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
1919 env
->cp
[cpnum
].cp_read
= cp_read
;
1920 env
->cp
[cpnum
].cp_write
= cp_write
;
1921 env
->cp
[cpnum
].opaque
= opaque
;
1926 /* Note that signed overflow is undefined in C. The following routines are
1927 careful to use unsigned types where modulo arithmetic is required.
1928 Failure to do so _will_ break on newer gcc. */
1930 /* Signed saturating arithmetic. */
1932 /* Perform 16-bit signed satruating addition. */
1933 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
1938 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
1947 /* Perform 8-bit signed satruating addition. */
1948 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
1953 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
1962 /* Perform 16-bit signed satruating subtraction. */
1963 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
1968 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
1977 /* Perform 8-bit signed satruating subtraction. */
1978 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
1983 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
1992 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
1993 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
1994 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
1995 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
1998 #include "op_addsub.h"
2000 /* Unsigned saturating arithmetic. */
2001 static inline uint16_t add16_usat(uint16_t a
, uint8_t b
)
2010 static inline uint16_t sub16_usat(uint16_t a
, uint8_t b
)
2018 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2027 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2035 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2036 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2037 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2038 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2041 #include "op_addsub.h"
2043 /* Signed modulo arithmetic. */
2044 #define SARITH16(a, b, n, op) do { \
2046 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2047 RESULT(sum, n, 16); \
2049 ge |= 3 << (n * 2); \
2052 #define SARITH8(a, b, n, op) do { \
2054 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2055 RESULT(sum, n, 8); \
2061 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2062 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2063 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2064 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2068 #include "op_addsub.h"
2070 /* Unsigned modulo arithmetic. */
2071 #define ADD16(a, b, n) do { \
2073 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2074 RESULT(sum, n, 16); \
2075 if ((sum >> 16) == 0) \
2076 ge |= 3 << (n * 2); \
2079 #define ADD8(a, b, n) do { \
2081 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2082 RESULT(sum, n, 8); \
2083 if ((sum >> 8) == 0) \
2084 ge |= 3 << (n * 2); \
2087 #define SUB16(a, b, n) do { \
2089 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2090 RESULT(sum, n, 16); \
2091 if ((sum >> 16) == 0) \
2092 ge |= 3 << (n * 2); \
2095 #define SUB8(a, b, n) do { \
2097 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2098 RESULT(sum, n, 8); \
2099 if ((sum >> 8) == 0) \
2100 ge |= 3 << (n * 2); \
2106 #include "op_addsub.h"
2108 /* Halved signed arithmetic. */
2109 #define ADD16(a, b, n) \
2110 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2111 #define SUB16(a, b, n) \
2112 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2113 #define ADD8(a, b, n) \
2114 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2115 #define SUB8(a, b, n) \
2116 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2119 #include "op_addsub.h"
2121 /* Halved unsigned arithmetic. */
2122 #define ADD16(a, b, n) \
2123 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2124 #define SUB16(a, b, n) \
2125 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2126 #define ADD8(a, b, n) \
2127 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2128 #define SUB8(a, b, n) \
2129 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2132 #include "op_addsub.h"
2134 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2142 /* Unsigned sum of absolute byte differences. */
2143 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2146 sum
= do_usad(a
, b
);
2147 sum
+= do_usad(a
>> 8, b
>> 8);
2148 sum
+= do_usad(a
>> 16, b
>>16);
2149 sum
+= do_usad(a
>> 24, b
>> 24);
2153 /* For ARMv6 SEL instruction. */
2154 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2167 return (a
& mask
) | (b
& ~mask
);
2170 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2172 return (val
>> 32) | (val
!= 0);
2175 /* VFP support. We follow the convention used for VFP instrunctions:
2176 Single precition routines have a "s" suffix, double precision a
2179 /* Convert host exception flags to vfp form. */
2180 static inline int vfp_exceptbits_from_host(int host_bits
)
2182 int target_bits
= 0;
2184 if (host_bits
& float_flag_invalid
)
2186 if (host_bits
& float_flag_divbyzero
)
2188 if (host_bits
& float_flag_overflow
)
2190 if (host_bits
& float_flag_underflow
)
2192 if (host_bits
& float_flag_inexact
)
2193 target_bits
|= 0x10;
2197 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2202 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2203 | (env
->vfp
.vec_len
<< 16)
2204 | (env
->vfp
.vec_stride
<< 20);
2205 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2206 fpscr
|= vfp_exceptbits_from_host(i
);
2210 /* Convert vfp exception flags to target form. */
2211 static inline int vfp_exceptbits_to_host(int target_bits
)
2215 if (target_bits
& 1)
2216 host_bits
|= float_flag_invalid
;
2217 if (target_bits
& 2)
2218 host_bits
|= float_flag_divbyzero
;
2219 if (target_bits
& 4)
2220 host_bits
|= float_flag_overflow
;
2221 if (target_bits
& 8)
2222 host_bits
|= float_flag_underflow
;
2223 if (target_bits
& 0x10)
2224 host_bits
|= float_flag_inexact
;
2228 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2233 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2234 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2235 env
->vfp
.vec_len
= (val
>> 16) & 7;
2236 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2239 if (changed
& (3 << 22)) {
2240 i
= (val
>> 22) & 3;
2243 i
= float_round_nearest_even
;
2249 i
= float_round_down
;
2252 i
= float_round_to_zero
;
2255 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2258 i
= vfp_exceptbits_to_host((val
>> 8) & 0x1f);
2259 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2260 /* XXX: FZ and DN are not implemented. */
2263 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2265 #define VFP_BINOP(name) \
2266 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2268 return float32_ ## name (a, b, &env->vfp.fp_status); \
2270 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2272 return float64_ ## name (a, b, &env->vfp.fp_status); \
2280 float32
VFP_HELPER(neg
, s
)(float32 a
)
2282 return float32_chs(a
);
2285 float64
VFP_HELPER(neg
, d
)(float64 a
)
2287 return float32_chs(a
);
2290 float32
VFP_HELPER(abs
, s
)(float32 a
)
2292 return float32_abs(a
);
2295 float64
VFP_HELPER(abs
, d
)(float64 a
)
2297 return float32_abs(a
);
2300 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2302 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2305 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2307 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2310 /* XXX: check quiet/signaling case */
2311 #define DO_VFP_cmp(p, type) \
2312 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2315 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2316 case 0: flags = 0x6; break; \
2317 case -1: flags = 0x8; break; \
2318 case 1: flags = 0x2; break; \
2319 default: case 2: flags = 0x3; break; \
2321 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2322 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2324 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2327 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2328 case 0: flags = 0x6; break; \
2329 case -1: flags = 0x8; break; \
2330 case 1: flags = 0x2; break; \
2331 default: case 2: flags = 0x3; break; \
2333 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2334 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2336 DO_VFP_cmp(s
, float32
)
2337 DO_VFP_cmp(d
, float64
)
2340 /* Helper routines to perform bitwise copies between float and int. */
2341 static inline float32
vfp_itos(uint32_t i
)
2352 static inline uint32_t vfp_stoi(float32 s
)
2363 static inline float64
vfp_itod(uint64_t i
)
2374 static inline uint64_t vfp_dtoi(float64 d
)
2385 /* Integer to float conversion. */
2386 float32
VFP_HELPER(uito
, s
)(float32 x
, CPUState
*env
)
2388 return uint32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2391 float64
VFP_HELPER(uito
, d
)(float32 x
, CPUState
*env
)
2393 return uint32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2396 float32
VFP_HELPER(sito
, s
)(float32 x
, CPUState
*env
)
2398 return int32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2401 float64
VFP_HELPER(sito
, d
)(float32 x
, CPUState
*env
)
2403 return int32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2406 /* Float to integer conversion. */
2407 float32
VFP_HELPER(toui
, s
)(float32 x
, CPUState
*env
)
2409 return vfp_itos(float32_to_uint32(x
, &env
->vfp
.fp_status
));
2412 float32
VFP_HELPER(toui
, d
)(float64 x
, CPUState
*env
)
2414 return vfp_itos(float64_to_uint32(x
, &env
->vfp
.fp_status
));
2417 float32
VFP_HELPER(tosi
, s
)(float32 x
, CPUState
*env
)
2419 return vfp_itos(float32_to_int32(x
, &env
->vfp
.fp_status
));
2422 float32
VFP_HELPER(tosi
, d
)(float64 x
, CPUState
*env
)
2424 return vfp_itos(float64_to_int32(x
, &env
->vfp
.fp_status
));
2427 float32
VFP_HELPER(touiz
, s
)(float32 x
, CPUState
*env
)
2429 return vfp_itos(float32_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2432 float32
VFP_HELPER(touiz
, d
)(float64 x
, CPUState
*env
)
2434 return vfp_itos(float64_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2437 float32
VFP_HELPER(tosiz
, s
)(float32 x
, CPUState
*env
)
2439 return vfp_itos(float32_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2442 float32
VFP_HELPER(tosiz
, d
)(float64 x
, CPUState
*env
)
2444 return vfp_itos(float64_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2447 /* floating point conversion */
2448 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2450 return float32_to_float64(x
, &env
->vfp
.fp_status
);
2453 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2455 return float64_to_float32(x
, &env
->vfp
.fp_status
);
2458 /* VFP3 fixed point conversion. */
2459 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2460 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2463 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2464 &env->vfp.fp_status); \
2465 return ftype##_scalbn(tmp, shift, &env->vfp.fp_status); \
2467 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2470 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2471 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2472 &env->vfp.fp_status)); \
2475 VFP_CONV_FIX(sh
, d
, float64
, int16
, )
2476 VFP_CONV_FIX(sl
, d
, float64
, int32
, )
2477 VFP_CONV_FIX(uh
, d
, float64
, uint16
, u
)
2478 VFP_CONV_FIX(ul
, d
, float64
, uint32
, u
)
2479 VFP_CONV_FIX(sh
, s
, float32
, int16
, )
2480 VFP_CONV_FIX(sl
, s
, float32
, int32
, )
2481 VFP_CONV_FIX(uh
, s
, float32
, uint16
, u
)
2482 VFP_CONV_FIX(ul
, s
, float32
, uint32
, u
)
2485 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2487 float_status
*s
= &env
->vfp
.fp_status
;
2488 float32 two
= int32_to_float32(2, s
);
2489 return float32_sub(two
, float32_mul(a
, b
, s
), s
);
2492 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2494 float_status
*s
= &env
->vfp
.fp_status
;
2495 float32 three
= int32_to_float32(3, s
);
2496 return float32_sub(three
, float32_mul(a
, b
, s
), s
);
2499 /* TODO: The architecture specifies the value that the estimate functions
2500 should return. We return the exact reciprocal/root instead. */
2501 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2503 float_status
*s
= &env
->vfp
.fp_status
;
2504 float32 one
= int32_to_float32(1, s
);
2505 return float32_div(one
, a
, s
);
2508 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
2510 float_status
*s
= &env
->vfp
.fp_status
;
2511 float32 one
= int32_to_float32(1, s
);
2512 return float32_div(one
, float32_sqrt(a
, s
), s
);
2515 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
2517 float_status
*s
= &env
->vfp
.fp_status
;
2519 tmp
= int32_to_float32(a
, s
);
2520 tmp
= float32_scalbn(tmp
, -32, s
);
2521 tmp
= helper_recpe_f32(tmp
, env
);
2522 tmp
= float32_scalbn(tmp
, 31, s
);
2523 return float32_to_int32(tmp
, s
);
2526 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
2528 float_status
*s
= &env
->vfp
.fp_status
;
2530 tmp
= int32_to_float32(a
, s
);
2531 tmp
= float32_scalbn(tmp
, -32, s
);
2532 tmp
= helper_rsqrte_f32(tmp
, env
);
2533 tmp
= float32_scalbn(tmp
, 31, s
);
2534 return float32_to_int32(tmp
, s
);